#----------------------------------------------------------- # Vivado v2016.2 (64-bit) # SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 # IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 # Start of session at: Thu Dec 20 17:31:19 2018 # Process ID: 5736 # Current directory: C:/Users/53194/Desktop/project_789 # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8016 C:\Users\53194\Desktop\project_789\project_78.xpr # Log file: C:/Users/53194/Desktop/project_789/vivado.log # Journal file: C:/Users/53194/Desktop/project_789\vivado.jou #----------------------------------------------------------- start_gui open_project C:/Users/53194/Desktop/project_789/project_78.xpr Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'J:/Xilinx/Vivado/2016.2/data/ip'. open_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 792.137 ; gain = 128.984 update_compile_order -fileset sources_1 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory ERROR: [VRFC 10-1346] second argument of $readmemb must be a memory [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:37] ERROR: [VRFC 10-1040] module InstructionMemory ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:23] INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory ERROR: [VRFC 10-1346] second argument of $readmemb must be a memory [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:37] ERROR: [VRFC 10-1040] module InstructionMemory ignored due to previous errors [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v:23] INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-529] concurrent assignment to a non-net pcin is not permitted [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:87] WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds INFO: [USF-XSim-99] Step results log file:'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/elaborate.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Dec 20 17:37:39 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 806.980 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 806.980 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Dec 20 17:39:29 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 820.516 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Dec 20 17:40:40 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 828.488 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '1' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Dec 20 17:42:22 2018... INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 828.488 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 839.563 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Dec 20 17:59:50 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 839.563 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:13 . Memory (MB): peak = 839.563 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 839.563 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Dec 20 18:01:43 2018... run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 839.563 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:11 . Memory (MB): peak = 839.563 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 863.246 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '3' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Dec 20 18:05:31 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 863.246 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:13 . Memory (MB): peak = 863.246 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 863.246 ; gain = 0.000 launch_simulation INFO: [USF-XSim-27] Simulation object is 'sim_1' INFO: [USF-XSim-37] Inspecting design source files for 'top' in fileset 'sim_1'... INFO: [USF-XSim-97] Finding global include files... INFO: [USF-XSim-98] Fetching design files from 'sim_1'... INFO: [USF-XSim-2] XSim::Compile design INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' "xvlog -m64 --relax -prj top_vlog.prj" INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SignalExtension.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SignalExtension INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ShiftUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ShiftUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/RegisterFile.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module RegisterFile INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ProgramCounter.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ProgramCounter INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Multiplexer.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Multiplexer INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module InstructionMemory INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module DataMemory INFO: [VRFC 10-2458] undeclared symbol out, assumed default net type wire [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/DataMemory.v:44] INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ControlUnit.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ControlUnit INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/ALUControl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module ALUControl INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/Add1.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module Add1 INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/SimpleALU.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module SimpleALU INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module top INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/glbl.v" into library xil_defaultlib INFO: [VRFC 10-311] analyzing module glbl INFO: [USF-XSim-69] 'compile' step finished in '2' seconds INFO: [USF-XSim-3] XSim::Elaborate design INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' Vivado Simulator 2016.2 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: J:/Xilinx/Vivado/2016.2/bin/unwrapped/win64.o/xelab.exe -wto 4c388791a4e240948a5554cd0b3617d7 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot top_behav xil_defaultlib.top xil_defaultlib.glbl -log elaborate.log Using 2 slave threads. Starting static elaboration WARNING: [VRFC 10-278] actual bit length 32 differs from formal bit length 1 for port rdata1 [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:80] WARNING: [VRFC 10-278] actual bit length 4 differs from formal bit length 3 for port op [C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/top.v:83] Completed static elaboration Starting simulation data flow analysis Completed simulation data flow analysis Time Resolution for simulation is 1ps Compiling module xil_defaultlib.ControlUnit Compiling module xil_defaultlib.ProgramCounter Compiling module xil_defaultlib.Add1 Compiling module xil_defaultlib.InstructionMemory Compiling module xil_defaultlib.RegisterFile Compiling module xil_defaultlib.SignalExtension Compiling module xil_defaultlib.ALUControl Compiling module xil_defaultlib.SimpleALU Compiling module xil_defaultlib.Multiplexer Compiling module xil_defaultlib.ShiftUnit Compiling module xil_defaultlib.DataMemory Compiling module xil_defaultlib.top Compiling module xil_defaultlib.glbl Built simulation snapshot top_behav ****** Webtalk v2016.2 (64-bit) **** SW Build 1577090 on Thu Jun 2 16:32:40 MDT 2016 **** IP Build 1577682 on Fri Jun 3 12:00:54 MDT 2016 ** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. source C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav/xsim.dir/top_behav/webtalk/xsim_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Thu Dec 20 18:06:54 2018... run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 863.246 ; gain = 0.000 INFO: [USF-XSim-69] 'elaborate' step finished in '6' seconds INFO: [USF-XSim-4] XSim::Simulate design INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/53194/Desktop/project_789/project_78.sim/sim_1/behav' INFO: [USF-XSim-98] *** Running xsim with args "top_behav -key {Behavioral:sim_1:Functional:top} -tclbatch {top.tcl} -log {simulate.log}" INFO: [USF-XSim-8] Loading simulator feature Vivado Simulator 2016.2 Time resolution is 1 ps source top.tcl # set curr_wave [current_wave_config] # if { [string length $curr_wave] == 0 } { # if { [llength [get_objects]] > 0} { # add_wave / # set_property needs_save false [current_wave_config] # } else { # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." # } # } # run 1000ns WARNING: File C:UsersY94Desktopproject_789instruction.txt referenced on C:/Users/53194/Desktop/project_789/project_78.srcs/sources_1/new/InstructionMemory.v at line 37 cannot be opened for reading. Please ensure that this file is available in the current working directory. INFO: [USF-XSim-96] XSim completed. Design snapshot 'top_behav' loaded. INFO: [USF-XSim-97] XSim simulation ran for 1000ns launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:13 . Memory (MB): peak = 863.246 ; gain = 0.000 close_sim INFO: [Simtcl 6-16] Simulation closed close_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 863.246 ; gain = 0.000 exit INFO: [Common 17-206] Exiting Vivado at Thu Dec 20 21:32:02 2018...