(kicad_pcb (version 4) (host pcbnew 4.0.1-stable) (general (links 135) (no_connects 0) (area 118.127143 74.1 280.680001 191.83) (thickness 1.6) (drawings 63) (tracks 974) (zones 0) (modules 19) (nets 78) ) (page A4) (layers (0 F.Cu signal) (31 B.Cu signal) (32 B.Adhes user) (33 F.Adhes user) (34 B.Paste user) (35 F.Paste user) (36 B.SilkS user) (37 F.SilkS user) (38 B.Mask user) (39 F.Mask user) (40 Dwgs.User user) (41 Cmts.User user) (42 Eco1.User user hide) (43 Eco2.User user hide) (44 Edge.Cuts user) (45 Margin user) (46 B.CrtYd user) (47 F.CrtYd user) (48 B.Fab user) (49 F.Fab user) ) (setup (last_trace_width 0.1524) (user_trace_width 0.2032) (trace_clearance 0.14986) (zone_clearance 0.254) (zone_45_only no) (trace_min 0.1524) (segment_width 0.2) (edge_width 0.15) (via_size 0.6858) (via_drill 0.3302) (via_min_size 0.6858) (via_min_drill 0.3302) (uvia_size 0.3) (uvia_drill 0.1) (uvias_allowed no) (uvia_min_size 0.2) (uvia_min_drill 0.1) (pcb_text_width 0.3) (pcb_text_size 1.5 1.5) (mod_edge_width 0.15) (mod_text_size 1 1) (mod_text_width 0.15) (pad_size 1.524 1.524) (pad_drill 0.762) (pad_to_mask_clearance 0.2) (aux_axis_origin 0 0) (visible_elements FFFFFF7F) (pcbplotparams (layerselection 0x010f0_80000001) (usegerberextensions true) (excludeedgelayer true) (linewidth 0.100000) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15) (hpglpenoverlay 2) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 0) (scaleselection 1) (outputdirectory gerber)) ) (net 0 "") (net 1 /ExpansionPort/HEIGHT_1) (net 2 GNDPWR) (net 3 /ExpansionPort/HEIGHT_2) (net 4 /ExpansionPort/NEW_HEIGHT_4) (net 5 /ExpansionPort/3V3_0.3A_LL) (net 6 /ExpansionPort/HEIGHT_4) (net 7 "Net-(PORT_IC1-Pad7)") (net 8 /ExpansionPort/NEW_HEIGHT_1) (net 9 /ExpansionPort/NEW_HEIGHT_2) (net 10 +5V) (net 11 /ExpansionPort/UART1_TX) (net 12 /ExpansionPort/UART1_RX) (net 13 "Net-(CRADLE_PORT1-Pad6)") (net 14 /FTDI_PWR) (net 15 /ExpansionPort/i2c_SDA) (net 16 /ExpansionPort/i2c_SCL) (net 17 /ExpansionPort/SPI1_MOSI) (net 18 /ExpansionPort/TIMG1_CH1) (net 19 /ExpansionPort/TIM1) (net 20 /ExpansionPort/SPI1_MISO) (net 21 /ExpansionPort/SPI1_SCK) (net 22 /ExpansionPort/SPI1_NSS) (net 23 /ExpansionPort/SPI2_MOSI) (net 24 /ExpansionPort/SPI2_MISO) (net 25 /ExpansionPort/SPI2_SCK) (net 26 /ExpansionPort/SPI2_NSS) (net 27 /ExpansionPort/SPI3_MOSI) (net 28 /ExpansionPort/SPI3_MISO) (net 29 /ExpansionPort/SPI3_SCK) (net 30 /ExpansionPort/SPI3_NSS) (net 31 /ExpansionPort/CAN_LO) (net 32 /ExpansionPort/CAN_HI) (net 33 /ExpansionPort/RESET) (net 34 /ExpansionPort/BOOT) (net 35 /ExpansionPort/SDMMC1_CMD) (net 36 /ExpansionPort/SDMMC1_CK) (net 37 /ExpansionPort/SDMMC1_D3) (net 38 /ExpansionPort/SDMMC1_D2) (net 39 /ExpansionPort/SDMMC1_D1) (net 40 /ExpansionPort/SDMMC1_D0) (net 41 /ExpansionPort/ADC2) (net 42 /ExpansionPort/ADC1) (net 43 /ExpansionPort/TIMG2_CH4) (net 44 /ExpansionPort/TIMG2_CH3) (net 45 /ExpansionPort/TIMG2_CH2) (net 46 /ExpansionPort/TIMG2_CH1) (net 47 /ExpansionPort/TIMG1_CH4) (net 48 /ExpansionPort/TIMG1_CH3) (net 49 /ExpansionPort/TIMG1_CH2) (net 50 /ExpansionPort/TIM2) (net 51 /ExpansionPort/TIM3) (net 52 /ExpansionPort/TIM4) (net 53 /ExpansionPort/GPIO1) (net 54 /ExpansionPort/GPIO2) (net 55 /ExpansionPort/GPIO3) (net 56 /ExpansionPort/GPIO4) (net 57 /ExpansionPort/GPIO5) (net 58 /ExpansionPort/GPIO6) (net 59 /ExpansionPort/3V3_0.3A_E) (net 60 /ExpansionPort/+BATT) (net 61 /ExpansionPort/UART8_TX) (net 62 /ExpansionPort/UART8_RX) (net 63 /ExpansionPort/UART7_TX) (net 64 /ExpansionPort/UART7_RX) (net 65 /ExpansionPort/UART6_TX) (net 66 /ExpansionPort/UART6_RX) (net 67 /ExpansionPort/UART5_TX) (net 68 /ExpansionPort/UART5_RX) (net 69 /ExpansionPort/UART4_TX) (net 70 /ExpansionPort/UART4_RX) (net 71 /ExpansionPort/UART3_TX) (net 72 /ExpansionPort/UART3_RX) (net 73 /ExpansionPort/UART2_TX) (net 74 /ExpansionPort/UART2_RX) (net 75 "Net-(PORT_OUT1-Pad26)") (net 76 "Net-(PORT_OUT1-Pad25)") (net 77 "Net-(C1-Pad1)") (net_class Default "This is the default net class." (clearance 0.14986) (trace_width 0.1524) (via_dia 0.6858) (via_drill 0.3302) (uvia_dia 0.3) (uvia_drill 0.1) (add_net +5V) (add_net /ExpansionPort/+BATT) (add_net /ExpansionPort/3V3_0.3A_E) (add_net /ExpansionPort/3V3_0.3A_LL) (add_net /ExpansionPort/ADC1) (add_net /ExpansionPort/ADC2) (add_net /ExpansionPort/BOOT) (add_net /ExpansionPort/CAN_HI) (add_net /ExpansionPort/CAN_LO) (add_net /ExpansionPort/GPIO1) (add_net /ExpansionPort/GPIO2) (add_net /ExpansionPort/GPIO3) (add_net /ExpansionPort/GPIO4) (add_net /ExpansionPort/GPIO5) (add_net /ExpansionPort/GPIO6) (add_net /ExpansionPort/HEIGHT_1) (add_net /ExpansionPort/HEIGHT_2) (add_net /ExpansionPort/HEIGHT_4) (add_net /ExpansionPort/NEW_HEIGHT_1) (add_net /ExpansionPort/NEW_HEIGHT_2) (add_net /ExpansionPort/NEW_HEIGHT_4) (add_net /ExpansionPort/RESET) (add_net /ExpansionPort/SDMMC1_CK) (add_net /ExpansionPort/SDMMC1_CMD) (add_net /ExpansionPort/SDMMC1_D0) (add_net /ExpansionPort/SDMMC1_D1) (add_net /ExpansionPort/SDMMC1_D2) (add_net /ExpansionPort/SDMMC1_D3) (add_net /ExpansionPort/SPI1_MISO) (add_net /ExpansionPort/SPI1_MOSI) (add_net /ExpansionPort/SPI1_NSS) (add_net /ExpansionPort/SPI1_SCK) (add_net /ExpansionPort/SPI2_MISO) (add_net /ExpansionPort/SPI2_MOSI) (add_net /ExpansionPort/SPI2_NSS) (add_net /ExpansionPort/SPI2_SCK) (add_net /ExpansionPort/SPI3_MISO) (add_net /ExpansionPort/SPI3_MOSI) (add_net /ExpansionPort/SPI3_NSS) (add_net /ExpansionPort/SPI3_SCK) (add_net /ExpansionPort/TIM1) (add_net /ExpansionPort/TIM2) (add_net /ExpansionPort/TIM3) (add_net /ExpansionPort/TIM4) (add_net /ExpansionPort/TIMG1_CH1) (add_net /ExpansionPort/TIMG1_CH2) (add_net /ExpansionPort/TIMG1_CH3) (add_net /ExpansionPort/TIMG1_CH4) (add_net /ExpansionPort/TIMG2_CH1) (add_net /ExpansionPort/TIMG2_CH2) (add_net /ExpansionPort/TIMG2_CH3) (add_net /ExpansionPort/TIMG2_CH4) (add_net /ExpansionPort/UART1_RX) (add_net /ExpansionPort/UART1_TX) (add_net /ExpansionPort/UART2_RX) (add_net /ExpansionPort/UART2_TX) (add_net /ExpansionPort/UART3_RX) (add_net /ExpansionPort/UART3_TX) (add_net /ExpansionPort/UART4_RX) (add_net /ExpansionPort/UART4_TX) (add_net /ExpansionPort/UART5_RX) (add_net /ExpansionPort/UART5_TX) (add_net /ExpansionPort/UART6_RX) (add_net /ExpansionPort/UART6_TX) (add_net /ExpansionPort/UART7_RX) (add_net /ExpansionPort/UART7_TX) (add_net /ExpansionPort/UART8_RX) (add_net /ExpansionPort/UART8_TX) (add_net /ExpansionPort/i2c_SCL) (add_net /ExpansionPort/i2c_SDA) (add_net /FTDI_PWR) (add_net GNDPWR) (add_net "Net-(C1-Pad1)") (add_net "Net-(CRADLE_PORT1-Pad6)") (add_net "Net-(PORT_IC1-Pad7)") (add_net "Net-(PORT_OUT1-Pad25)") (add_net "Net-(PORT_OUT1-Pad26)") ) (module chickadee:chickadee_3mm_fcu (layer B.Cu) (tedit 0) (tstamp 56944A39) (at 157.33 123.17 180) (fp_text reference G*** (at 0 0 180) (layer B.SilkS) hide (effects (font (thickness 0.3)) (justify mirror)) ) (fp_text value "Chickadee 3mm" (at 0.75 0 180) (layer B.SilkS) hide (effects (font (thickness 0.3)) (justify mirror)) ) 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-0.899869) (xy -0.294297 -0.927125) (xy -0.347632 -0.956975) (xy -0.40532 -0.989684) (xy -0.467932 -1.025519) (xy -0.532694 -1.062815) (xy -0.582887 -1.091743) (xy -0.627657 -1.11745) (xy -0.667661 -1.140298) (xy -0.703555 -1.160648) (xy -0.735994 -1.178863) (xy -0.765635 -1.195303) (xy -0.793134 -1.21033) (xy -0.819147 -1.224307) (xy -0.84433 -1.237594) (xy -0.869338 -1.250554) (xy -0.894828 -1.263549) (xy -0.917222 -1.27482) (xy -0.982539 -1.306741) (xy -1.043326 -1.334702) (xy -1.100631 -1.359064) (xy -1.155499 -1.380188) (xy -1.208978 -1.398436) (xy -1.262115 -1.414169) (xy -1.315957 -1.427748) (xy -1.371551 -1.439537) (xy -1.419025 -1.448094) (xy -1.478301 -1.457475) (xy -1.532886 -1.464849) (xy -1.584804 -1.470377) (xy -1.636074 -1.474223) (xy -1.688721 -1.47655) (xy -1.744766 -1.477522) (xy -1.783292 -1.477509) (xy -1.80988 -1.477309) (xy -1.834924 -1.477051) (xy -1.85733 -1.476751) (xy -1.876003 -1.476426) (xy -1.889851 -1.476092) (xy -1.897777 -1.475767) (xy -1.897944 -1.475755) (xy -1.988991 -1.46674) (xy -2.0788 -1.453096) (xy -2.166515 -1.435042) (xy -2.251282 -1.412798) (xy -2.332244 -1.386583) (xy -2.408545 -1.356619) (xy -2.466209 -1.329817) (xy -2.552043 -1.282919) (xy -2.63567 -1.229377) (xy -2.717012 -1.169273) (xy -2.795994 -1.10269) (xy -2.872539 -1.029708) (xy -2.946571 -0.950411) (xy -3.018015 -0.864879) (xy -3.086793 -0.773196) (xy -3.152829 -0.675442) (xy -3.216048 -0.571701) (xy -3.276373 -0.462053) (xy -3.2807 -0.453746) (xy -3.317707 -0.378734) (xy -3.352221 -0.300989) (xy -3.3846 -0.21958) (xy -3.415202 -0.133574) (xy -3.444388 -0.042039) (xy -3.46089 0.014242) (xy -3.468457 0.040831) (xy -3.714194 0.139956) (xy -3.753671 0.155931) (xy -3.791187 0.171209) (xy -3.826234 0.185578) (xy -3.858306 0.198827) (xy -3.886898 0.210743) (xy -3.911502 0.221113) (xy -3.931612 0.229726) (xy -3.946722 0.23637) (xy -3.956326 0.240832) (xy -3.959917 0.242899) (xy -3.959931 0.242945) (xy -3.957356 0.245822) (xy -3.949885 0.253035) (xy -3.937902 0.264238) (xy -3.921787 0.279083) (xy -3.901922 0.297224) (xy -3.87869 0.318314) (xy -3.852471 0.342006) (xy -3.823649 0.367952) (xy -3.792605 0.395807) (xy -3.75972 0.425222) (xy -3.734153 0.448034) (xy -3.508375 0.649259) (xy -3.493997 0.688978) (xy -3.465662 0.759052) (xy -3.432414 0.825955) (xy -3.393848 0.890293) (xy -3.349555 0.952676) (xy -3.29913 1.013713) (xy -3.242165 1.07401) (xy -3.225776 1.090083) (xy -3.158462 1.150261) (xy -3.08587 1.205941) (xy -3.008266 1.25699) (xy -2.925914 1.303278) (xy -2.839079 1.34467) (xy -2.748026 1.381036) (xy -2.653021 1.412242) (xy -2.554329 1.438158) (xy -2.50825 1.448166) (xy -2.463853 1.456803) (xy -2.424131 1.463573) (xy -2.387021 1.468705) (xy -2.35046 1.472428) (xy -2.312386 1.474971) (xy -2.270735 1.476561) (xy -2.247194 1.477084) (xy -2.200426 1.477507) (xy -2.158969 1.476897)) (layer B.Mask) (width 0.01)) ) (module DF40-80pin-Header (layer B.Cu) (tedit 56414F24) (tstamp 5645E7C5) (at 159.65 108) (path /564009DE/56401367) (fp_text reference PORT_IN1 (at 0.05 -10.2) (layer B.SilkS) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_text value CKD_SANDWICH (at -2.99 0.72 90) (layer B.Fab) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_line (start -0.925 -8.76) (end 0.925 -8.76) (layer B.SilkS) (width 0.15)) (fp_line (start -0.925 8.76) (end 0.925 8.76) (layer B.SilkS) (width 0.15)) (fp_line (start 0 7.8) (end 0 -7.8) (layer B.SilkS) (width 0.15)) (pad 80 smd rect (at 1.355 7.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 17 /ExpansionPort/SPI1_MOSI)) (pad 40 smd rect (at -1.355 7.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 12 /ExpansionPort/UART1_RX)) (pad 41 smd rect (at 1.355 -7.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 18 /ExpansionPort/TIMG1_CH1)) (pad 1 smd rect (at -1.355 -7.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 19 /ExpansionPort/TIM1)) (pad 79 smd rect (at 1.355 7.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 20 /ExpansionPort/SPI1_MISO)) (pad 78 smd rect (at 1.355 7) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 21 /ExpansionPort/SPI1_SCK)) (pad 77 smd rect (at 1.355 6.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 22 /ExpansionPort/SPI1_NSS)) (pad 76 smd rect (at 1.355 6.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 23 /ExpansionPort/SPI2_MOSI)) (pad 75 smd rect (at 1.355 5.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 24 /ExpansionPort/SPI2_MISO)) (pad 74 smd rect (at 1.355 5.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 25 /ExpansionPort/SPI2_SCK)) (pad 73 smd rect (at 1.355 5) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 26 /ExpansionPort/SPI2_NSS)) (pad 72 smd rect (at 1.355 4.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 27 /ExpansionPort/SPI3_MOSI)) (pad 71 smd rect (at 1.355 4.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 28 /ExpansionPort/SPI3_MISO)) (pad 70 smd rect (at 1.355 3.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 29 /ExpansionPort/SPI3_SCK)) (pad 69 smd rect (at 1.355 3.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 30 /ExpansionPort/SPI3_NSS)) (pad 68 smd rect (at 1.355 3) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 31 /ExpansionPort/CAN_LO)) (pad 67 smd rect (at 1.355 2.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 32 /ExpansionPort/CAN_HI)) (pad 66 smd rect (at 1.355 2.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 33 /ExpansionPort/RESET)) (pad 65 smd rect (at 1.355 1.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 34 /ExpansionPort/BOOT)) (pad 64 smd rect (at 1.355 1.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 63 smd rect (at 1.355 1) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 62 smd rect (at 1.355 0.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 61 smd rect (at 1.355 0.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 60 smd rect (at 1.355 -0.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 59 smd rect (at 1.355 -0.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 58 smd rect (at 1.355 -1) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 57 smd rect (at 1.355 -1.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 56 smd rect (at 1.355 -1.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 35 /ExpansionPort/SDMMC1_CMD)) (pad 55 smd rect (at 1.355 -2.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 36 /ExpansionPort/SDMMC1_CK)) (pad 54 smd rect (at 1.355 -2.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 37 /ExpansionPort/SDMMC1_D3)) (pad 53 smd rect (at 1.355 -3) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 38 /ExpansionPort/SDMMC1_D2)) (pad 52 smd rect (at 1.355 -3.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 39 /ExpansionPort/SDMMC1_D1)) (pad 51 smd rect (at 1.355 -3.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 40 /ExpansionPort/SDMMC1_D0)) (pad 50 smd rect (at 1.355 -4.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 41 /ExpansionPort/ADC2)) (pad 49 smd rect (at 1.355 -4.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 42 /ExpansionPort/ADC1)) (pad 48 smd rect (at 1.355 -5) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 43 /ExpansionPort/TIMG2_CH4)) (pad 47 smd rect (at 1.355 -5.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 44 /ExpansionPort/TIMG2_CH3)) (pad 46 smd rect (at 1.355 -5.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 45 /ExpansionPort/TIMG2_CH2)) (pad 45 smd rect (at 1.355 -6.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 46 /ExpansionPort/TIMG2_CH1)) (pad 44 smd rect (at 1.355 -6.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 47 /ExpansionPort/TIMG1_CH4)) (pad 43 smd rect (at 1.355 -7) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 48 /ExpansionPort/TIMG1_CH3)) (pad 42 smd rect (at 1.355 -7.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 49 /ExpansionPort/TIMG1_CH2)) (pad 41 smd rect (at 1.355 -8.2) (size 0.66 0.35) (drill (offset 0 -0.075)) (layers B.Cu B.Paste B.Mask) (net 18 /ExpansionPort/TIMG1_CH1)) (pad 1 smd rect (at -1.355 -8.2) (size 0.66 0.35) (drill (offset 0 -0.075)) (layers B.Cu B.Paste B.Mask) (net 19 /ExpansionPort/TIM1)) (pad 80 smd rect (at 1.355 8.2) (size 0.66 0.35) (drill (offset 0 0.075)) (layers B.Cu B.Paste B.Mask) (net 17 /ExpansionPort/SPI1_MOSI)) (pad 40 smd rect (at -1.355 8.2) (size 0.66 0.35) (drill (offset 0 0.075)) (layers B.Cu B.Paste B.Mask) (net 12 /ExpansionPort/UART1_RX)) (pad 2 smd rect (at -1.355 -7.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 50 /ExpansionPort/TIM2)) (pad 3 smd rect (at -1.355 -7) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 51 /ExpansionPort/TIM3)) (pad 4 smd rect (at -1.355 -6.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 52 /ExpansionPort/TIM4)) (pad 5 smd rect (at -1.355 -6.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 53 /ExpansionPort/GPIO1)) (pad 6 smd rect (at -1.355 -5.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 54 /ExpansionPort/GPIO2)) (pad 7 smd rect (at -1.355 -5.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 55 /ExpansionPort/GPIO3)) (pad 8 smd rect (at -1.355 -5) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 56 /ExpansionPort/GPIO4)) (pad 9 smd rect (at -1.355 -4.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 57 /ExpansionPort/GPIO5)) (pad 10 smd rect (at -1.355 -4.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 58 /ExpansionPort/GPIO6)) (pad 11 smd rect (at -1.355 -3.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 15 /ExpansionPort/i2c_SDA)) (pad 12 smd rect (at -1.355 -3.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 16 /ExpansionPort/i2c_SCL)) (pad 13 smd rect (at -1.355 -3) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 6 /ExpansionPort/HEIGHT_4)) (pad 14 smd rect (at -1.355 -2.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 3 /ExpansionPort/HEIGHT_2)) (pad 15 smd rect (at -1.355 -2.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 1 /ExpansionPort/HEIGHT_1)) (pad 16 smd rect (at -1.355 -1.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (pad 17 smd rect (at -1.355 -1.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 59 /ExpansionPort/3V3_0.3A_E)) (pad 18 smd rect (at -1.355 -1) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 60 /ExpansionPort/+BATT)) (pad 19 smd rect (at -1.355 -0.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 10 +5V)) (pad 20 smd rect (at -1.355 -0.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 10 +5V)) (pad 21 smd rect (at -1.355 0.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 10 +5V)) (pad 22 smd rect (at -1.355 0.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 10 +5V)) (pad 23 smd rect (at -1.355 1) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 10 +5V)) (pad 24 smd rect (at -1.355 1.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 10 +5V)) (pad 25 smd rect (at -1.355 1.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 61 /ExpansionPort/UART8_TX)) (pad 26 smd rect (at -1.355 2.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 62 /ExpansionPort/UART8_RX)) (pad 27 smd rect (at -1.355 2.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 63 /ExpansionPort/UART7_TX)) (pad 28 smd rect (at -1.355 3) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 64 /ExpansionPort/UART7_RX)) (pad 29 smd rect (at -1.355 3.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 65 /ExpansionPort/UART6_TX)) (pad 30 smd rect (at -1.355 3.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 66 /ExpansionPort/UART6_RX)) (pad 31 smd rect (at -1.355 4.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 67 /ExpansionPort/UART5_TX)) (pad 32 smd rect (at -1.355 4.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 68 /ExpansionPort/UART5_RX)) (pad 33 smd rect (at -1.355 5) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 69 /ExpansionPort/UART4_TX)) (pad 34 smd rect (at -1.355 5.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 70 /ExpansionPort/UART4_RX)) (pad 35 smd rect (at -1.355 5.8) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 71 /ExpansionPort/UART3_TX)) (pad 36 smd rect (at -1.355 6.2) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 72 /ExpansionPort/UART3_RX)) (pad 37 smd rect (at -1.355 6.6) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 73 /ExpansionPort/UART2_TX)) (pad 38 smd rect (at -1.355 7) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 74 /ExpansionPort/UART2_RX)) (pad 39 smd rect (at -1.355 7.4) (size 0.66 0.23) (layers B.Cu B.Paste B.Mask) (net 11 /ExpansionPort/UART1_TX)) ) (module DF40-3-4mm-80pin-Receptacle (layer F.Cu) (tedit 56414DE1) (tstamp 563935BD) (at 159.65 108) (path /564009DE/5640139F) (fp_text reference PORT_OUT1 (at 0 -10.2) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value CKD_SANDWICH (at 3.87 -0.52 90) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -0.49 7.875) (end 0.49 7.875) (layer F.Fab) (width 0.15)) (fp_line (start -1.47 9.2) (end 1.47 9.2) (layer F.Fab) (width 0.15)) (fp_line (start -1.47 -9.4) (end 1.47 -9.4) (layer F.Fab) (width 0.15)) (fp_line (start -0.49 -7.825) (end 0.49 -7.825) (layer F.Fab) (width 0.15)) (pad 41 smd rect (at 1.54 -7.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 18 /ExpansionPort/TIMG1_CH1)) (pad 42 smd rect (at 1.54 -7.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 49 /ExpansionPort/TIMG1_CH2)) (pad 43 smd rect (at 1.54 -7) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 48 /ExpansionPort/TIMG1_CH3)) (pad 44 smd rect (at 1.54 -6.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 47 /ExpansionPort/TIMG1_CH4)) (pad 45 smd rect (at 1.54 -6.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 46 /ExpansionPort/TIMG2_CH1)) (pad 46 smd rect (at 1.54 -5.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 45 /ExpansionPort/TIMG2_CH2)) (pad 47 smd rect (at 1.54 -5.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 44 /ExpansionPort/TIMG2_CH3)) (pad 48 smd rect (at 1.54 -5) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 43 /ExpansionPort/TIMG2_CH4)) (pad 49 smd rect (at 1.54 -4.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 42 /ExpansionPort/ADC1)) (pad 50 smd rect (at 1.54 -4.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 41 /ExpansionPort/ADC2)) (pad 60 smd rect (at 1.54 -0.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 59 smd rect (at 1.54 -0.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 58 smd rect (at 1.54 -1) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 57 smd rect (at 1.54 -1.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 56 smd rect (at 1.54 -1.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 35 /ExpansionPort/SDMMC1_CMD)) (pad 55 smd rect (at 1.54 -2.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 36 /ExpansionPort/SDMMC1_CK)) (pad 54 smd rect (at 1.54 -2.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 37 /ExpansionPort/SDMMC1_D3)) (pad 53 smd rect (at 1.54 -3) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 38 /ExpansionPort/SDMMC1_D2)) (pad 52 smd rect (at 1.54 -3.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 39 /ExpansionPort/SDMMC1_D1)) (pad 51 smd rect (at 1.54 -3.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 40 /ExpansionPort/SDMMC1_D0)) (pad 61 smd rect (at 1.54 0.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 62 smd rect (at 1.54 0.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 63 smd rect (at 1.54 1) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 64 smd rect (at 1.54 1.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 65 smd rect (at 1.54 1.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 34 /ExpansionPort/BOOT)) (pad 66 smd rect (at 1.54 2.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 33 /ExpansionPort/RESET)) (pad 67 smd rect (at 1.54 2.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 32 /ExpansionPort/CAN_HI)) (pad 68 smd rect (at 1.54 3) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 31 /ExpansionPort/CAN_LO)) (pad 69 smd rect (at 1.54 3.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 30 /ExpansionPort/SPI3_NSS)) (pad 70 smd rect (at 1.54 3.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 29 /ExpansionPort/SPI3_SCK)) (pad 80 smd rect (at 1.54 7.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 17 /ExpansionPort/SPI1_MOSI)) (pad 79 smd rect (at 1.54 7.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 20 /ExpansionPort/SPI1_MISO)) (pad 78 smd rect (at 1.54 7) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 21 /ExpansionPort/SPI1_SCK)) (pad 77 smd rect (at 1.54 6.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 22 /ExpansionPort/SPI1_NSS)) (pad 76 smd rect (at 1.54 6.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 23 /ExpansionPort/SPI2_MOSI)) (pad 75 smd rect (at 1.54 5.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 24 /ExpansionPort/SPI2_MISO)) (pad 74 smd rect (at 1.54 5.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 25 /ExpansionPort/SPI2_SCK)) (pad 73 smd rect (at 1.54 5) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 26 /ExpansionPort/SPI2_NSS)) (pad 72 smd rect (at 1.54 4.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 27 /ExpansionPort/SPI3_MOSI)) (pad 71 smd rect (at 1.54 4.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 28 /ExpansionPort/SPI3_MISO)) (pad 31 smd rect (at -1.54 4.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 65 /ExpansionPort/UART6_TX)) (pad 32 smd rect (at -1.54 4.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 66 /ExpansionPort/UART6_RX)) (pad 33 smd rect (at -1.54 5) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 67 /ExpansionPort/UART5_TX)) (pad 34 smd rect (at -1.54 5.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 68 /ExpansionPort/UART5_RX)) (pad 35 smd rect (at -1.54 5.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 69 /ExpansionPort/UART4_TX)) (pad 36 smd rect (at -1.54 6.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 70 /ExpansionPort/UART4_RX)) (pad 37 smd rect (at -1.54 6.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 71 /ExpansionPort/UART3_TX)) (pad 38 smd rect (at -1.54 7) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 72 /ExpansionPort/UART3_RX)) (pad 39 smd rect (at -1.54 7.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 73 /ExpansionPort/UART2_TX)) (pad 40 smd rect (at -1.54 7.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 74 /ExpansionPort/UART2_RX)) (pad 30 smd rect (at -1.54 3.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 64 /ExpansionPort/UART7_RX)) (pad 29 smd rect (at -1.54 3.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 63 /ExpansionPort/UART7_TX)) (pad 28 smd rect (at -1.54 3) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 62 /ExpansionPort/UART8_RX)) (pad 27 smd rect (at -1.54 2.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 61 /ExpansionPort/UART8_TX)) (pad 26 smd rect (at -1.54 2.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 75 "Net-(PORT_OUT1-Pad26)")) (pad 25 smd rect (at -1.54 1.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 76 "Net-(PORT_OUT1-Pad25)")) (pad 24 smd rect (at -1.54 1.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 10 +5V)) (pad 23 smd rect (at -1.54 1) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 10 +5V)) (pad 22 smd rect (at -1.54 0.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 10 +5V)) (pad 21 smd rect (at -1.54 0.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 10 +5V)) (pad 11 smd rect (at -1.54 -3.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 15 /ExpansionPort/i2c_SDA)) (pad 12 smd rect (at -1.54 -3.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 16 /ExpansionPort/i2c_SCL)) (pad 13 smd rect (at -1.54 -3) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 4 /ExpansionPort/NEW_HEIGHT_4)) (pad 14 smd rect (at -1.54 -2.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 9 /ExpansionPort/NEW_HEIGHT_2)) (pad 15 smd rect (at -1.54 -2.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 8 /ExpansionPort/NEW_HEIGHT_1)) (pad 16 smd rect (at -1.54 -1.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (pad 17 smd rect (at -1.54 -1.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 59 /ExpansionPort/3V3_0.3A_E)) (pad 18 smd rect (at -1.54 -1) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 60 /ExpansionPort/+BATT)) (pad 19 smd rect (at -1.54 -0.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 10 +5V)) (pad 20 smd rect (at -1.54 -0.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 10 +5V)) (pad 10 smd rect (at -1.54 -4.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 58 /ExpansionPort/GPIO6)) (pad 9 smd rect (at -1.54 -4.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 57 /ExpansionPort/GPIO5)) (pad 8 smd rect (at -1.54 -5) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 56 /ExpansionPort/GPIO4)) (pad 7 smd rect (at -1.54 -5.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 55 /ExpansionPort/GPIO3)) (pad 6 smd rect (at -1.54 -5.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 54 /ExpansionPort/GPIO2)) (pad 5 smd rect (at -1.54 -6.2) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 53 /ExpansionPort/GPIO1)) (pad 4 smd rect (at -1.54 -6.6) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 52 /ExpansionPort/TIM4)) (pad 3 smd rect (at -1.54 -7) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 51 /ExpansionPort/TIM3)) (pad 2 smd rect (at -1.54 -7.4) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 50 /ExpansionPort/TIM2)) (pad 1 smd rect (at -1.54 -7.8) (size 0.7 0.2) (layers F.Cu F.Paste F.Mask) (net 19 /ExpansionPort/TIM1)) ) (module Mounting_Holes:MountingHole_3mm locked (layer F.Cu) (tedit 5640F1E2) (tstamp 5637D813) (at 163.25 123.25) (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,") (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,") (fp_text reference REF** (at 0 -4.0005) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value MountingHole_3mm (at 1.00076 5.00126) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_circle (center 0 0) (end 3 0) (layer Cmts.User) (width 0.381)) (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 3) (layers)) ) (module Mounting_Holes:MountingHole_3mm locked (layer F.Cu) (tedit 5640F1DE) (tstamp 5637D80D) (at 132.75 123.25) (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,") (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,") (fp_text reference REF** (at 0 -4.0005) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value MountingHole_3mm (at 1.00076 5.00126) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_circle (center 0 0) (end 3 0) (layer Cmts.User) (width 0.381)) (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 3) (layers)) ) (module Mounting_Holes:MountingHole_3mm locked (layer F.Cu) (tedit 5640F1E9) (tstamp 5637D807) (at 132.75 92.75) (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,") (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,") (fp_text reference REF** (at 0 -4.0005) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value MountingHole_3mm (at 1.00076 5.00126) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_circle (center 0 0) (end 3 0) (layer Cmts.User) (width 0.381)) (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 3) (layers)) ) (module Mounting_Holes:MountingHole_3mm locked (layer F.Cu) (tedit 5640F1EF) (tstamp 56251307) (at 163.25 92.75) (descr "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,") (tags "Mounting hole, Befestigungsbohrung, 3mm, No Annular, Kein Restring,") (fp_text reference REF** (at 0 -4.0005) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value MountingHole_3mm (at 1.00076 5.00126) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_circle (center 0 0) (end 3 0) (layer Cmts.User) (width 0.381)) (pad 1 thru_hole circle (at 0 0) (size 3 3) (drill 3) (layers)) ) (module Housings_SOT-23_SOT-143_TSOT-6:SC-70-6_Handsoldering (layer F.Cu) (tedit 56414E77) (tstamp 56461034) (at 157.13096 93.59976 90) (descr "SC-70-6, Handsoldering,") (tags "SC-70-6, Handsoldering,") (path /564009DE/564017F8) (attr smd) (fp_text reference PORT_ANDOR1 (at -0.02032 -3.98018 90) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value SN74LVC1G0832 (at -0.23876 4.11988 90) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -1.3208 1.97866) (end -1.3208 2.54762) (layer F.SilkS) (width 0.15)) (fp_line (start -1.3208 2.54762) (end -0.90932 2.54762) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -0.65024 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 1 /ExpansionPort/HEIGHT_1)) (pad 2 smd rect (at 0 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 3 smd rect (at 0.65024 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 3 /ExpansionPort/HEIGHT_2)) (pad 4 smd rect (at 0.65024 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 4 /ExpansionPort/NEW_HEIGHT_4)) (pad 5 smd rect (at 0 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (pad 6 smd rect (at -0.65024 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 6 /ExpansionPort/HEIGHT_4)) (model Housings_SOT-23_SOT-143_TSOT-6.3dshapes/SC-70-6_Handsoldering.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 56414ECE) (tstamp 56461040) (at 157.2 95.9) (descr "Capacitor SMD 0603, hand soldering") (tags "capacitor 0603") (path /564009DE/564029BB) (attr smd) (fp_text reference PORT_C1 (at 0 1.9) (layer B.SilkS) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_text value 0.1uF (at 0 -1.9) (layer B.Fab) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05)) (fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15)) (fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15)) (pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Housings_DFN_QFN:DFN-8-1EP_3x2mm_Pitch0.5mm (layer B.Cu) (tedit 56414E71) (tstamp 56461056) (at 157.2625 93.6125 180) (descr "8-Lead Plastic Dual Flat, No Lead Package (MC) - 2x3x0.9 mm Body [DFN] (see Microchip Packaging Specification 00000049BS.pdf)") (tags "DFN 0.5") (path /564009DE/564013BD) (attr smd) (fp_text reference PORT_IC1 (at 0 2.05 180) (layer B.SilkS) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_text value AT24CS02-MAHM (at 0 -2.05 180) (layer B.Fab) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_line (start -2.1 1.3) (end -2.1 -1.3) (layer B.CrtYd) (width 0.05)) (fp_line (start 2.1 1.3) (end 2.1 -1.3) (layer B.CrtYd) (width 0.05)) (fp_line (start -2.1 1.3) (end 2.1 1.3) (layer B.CrtYd) (width 0.05)) (fp_line (start -2.1 -1.3) (end 2.1 -1.3) (layer B.CrtYd) (width 0.05)) (fp_line (start -1.075 -1.125) (end 1.075 -1.125) (layer B.SilkS) (width 0.15)) (fp_line (start -1.9 1.125) (end 1.075 1.125) (layer B.SilkS) (width 0.15)) (pad 1 smd rect (at -1.45 0.75 180) (size 0.75 0.3) (layers B.Cu B.Paste B.Mask) (net 1 /ExpansionPort/HEIGHT_1)) (pad 2 smd rect (at -1.45 0.25 180) (size 0.75 0.3) (layers B.Cu B.Paste B.Mask) (net 3 /ExpansionPort/HEIGHT_2)) (pad 3 smd rect (at -1.45 -0.25 180) (size 0.75 0.3) (layers B.Cu B.Paste B.Mask) (net 6 /ExpansionPort/HEIGHT_4)) (pad 4 smd rect (at -1.45 -0.75 180) (size 0.75 0.3) (layers B.Cu B.Paste B.Mask) (net 2 GNDPWR)) (pad 5 smd rect (at 1.45 -0.75 180) (size 0.75 0.3) (layers B.Cu B.Paste B.Mask) (net 15 /ExpansionPort/i2c_SDA)) (pad 6 smd rect (at 1.45 -0.25 180) (size 0.75 0.3) (layers B.Cu B.Paste B.Mask) (net 16 /ExpansionPort/i2c_SCL)) (pad 7 smd rect (at 1.45 0.25 180) (size 0.75 0.3) (layers B.Cu B.Paste B.Mask) (net 7 "Net-(PORT_IC1-Pad7)")) (pad 8 smd rect (at 1.45 0.75 180) (size 0.75 0.3) (layers B.Cu B.Paste B.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (pad 9 smd rect (at 0.4375 -0.3625 180) (size 0.875 0.725) (layers B.Cu B.Paste B.Mask) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at 0.4375 0.3625 180) (size 0.875 0.725) (layers B.Cu B.Paste B.Mask) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at -0.4375 -0.3625 180) (size 0.875 0.725) (layers B.Cu B.Paste B.Mask) (solder_paste_margin_ratio -0.2)) (pad 9 smd rect (at -0.4375 0.3625 180) (size 0.875 0.725) (layers B.Cu B.Paste B.Mask) (solder_paste_margin_ratio -0.2)) (model Housings_DFN_QFN.3dshapes/DFN-8-1EP_3x2mm_Pitch0.5mm.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Housings_SOT-23_SOT-143_TSOT-6:SC-70-6_Handsoldering (layer F.Cu) (tedit 56414E7E) (tstamp 56461062) (at 162.96904 97.59976 90) (descr "SC-70-6, Handsoldering,") (tags "SC-70-6, Handsoldering,") (path /564009DE/56401612) (attr smd) (fp_text reference PORT_INV1 (at -0.02032 -3.98018 90) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value SN74LVC1G58 (at -0.23876 4.11988 90) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -1.3208 1.97866) (end -1.3208 2.54762) (layer F.SilkS) (width 0.15)) (fp_line (start -1.3208 2.54762) (end -0.90932 2.54762) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -0.65024 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 1 /ExpansionPort/HEIGHT_1)) (pad 2 smd rect (at 0 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 3 smd rect (at 0.65024 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 4 smd rect (at 0.65024 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 8 /ExpansionPort/NEW_HEIGHT_1)) (pad 5 smd rect (at 0 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (pad 6 smd rect (at -0.65024 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (model Housings_SOT-23_SOT-143_TSOT-6.3dshapes/SC-70-6_Handsoldering.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 56414ED9) (tstamp 5646107B) (at 155.45 91.2 180) (descr "Resistor SMD 0603, hand soldering") (tags "resistor 0603") (path /564009DE/5640243A) (attr smd) (fp_text reference PORT_R1 (at 0 1.9 180) (layer B.SilkS) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_text value 10k (at 0 -1.9 180) (layer B.Fab) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05)) (fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05)) (fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05)) (fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05)) (fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15)) (fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15)) (pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask) (net 7 "Net-(PORT_IC1-Pad7)")) (pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Housings_SOT-23_SOT-143_TSOT-6:SC-70-6_Handsoldering (layer F.Cu) (tedit 56414E7B) (tstamp 56461087) (at 157.28096 96.04976 90) (descr "SC-70-6, Handsoldering,") (tags "SC-70-6, Handsoldering,") (path /564009DE/5640163C) (attr smd) (fp_text reference PORT_XOR1 (at -0.02032 -3.98018 90) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value SN74LVC1G58 (at -0.23876 4.11988 90) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -1.3208 1.97866) (end -1.3208 2.54762) (layer F.SilkS) (width 0.15)) (fp_line (start -1.3208 2.54762) (end -0.90932 2.54762) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -0.65024 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 1 /ExpansionPort/HEIGHT_1)) (pad 2 smd rect (at 0 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (pad 3 smd rect (at 0.65024 1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 1 /ExpansionPort/HEIGHT_1)) (pad 4 smd rect (at 0.65024 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 9 /ExpansionPort/NEW_HEIGHT_2)) (pad 5 smd rect (at 0 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 5 /ExpansionPort/3V3_0.3A_LL)) (pad 6 smd rect (at -0.65024 -1.33096 90) (size 0.39878 1.50114) (layers F.Cu F.Paste F.Mask) (net 3 /ExpansionPort/HEIGHT_2)) (model Housings_SOT-23_SOT-143_TSOT-6.3dshapes/SC-70-6_Handsoldering.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Measurement_Points:Measurement_Point_Round-SMD-Pad_Small (layer B.Cu) (tedit 56414E65) (tstamp 56496854) (at 158.55 91.25) (descr "Mesurement Point, Round, SMD Pad, DM 1.5mm,") (tags "Mesurement Point, Round, SMD Pad, DM 1.5mm,") (path /564009DE/564024DB) (fp_text reference PORT_P1 (at 0 2.54) (layer B.SilkS) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (fp_text value CONN_01X01 (at 1.27 -2.54) (layer B.Fab) hide (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) ) (pad 1 smd circle (at 0 0) (size 1.524 1.524) (layers B.Cu B.Paste B.Mask) (net 7 "Net-(PORT_IC1-Pad7)")) ) (module Capacitors_SMD:C_1206_HandSoldering (layer F.Cu) (tedit 541A9C03) (tstamp 569418F4) (at 140.82 102.07 180) (descr "Capacitor SMD 1206, hand soldering") (tags "capacitor 1206") (path /569413BF) (attr smd) (fp_text reference C1 (at -4.4 0.03 270) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value 10uF (at 0 2.3 180) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -3.3 -1.15) (end 3.3 -1.15) (layer F.CrtYd) (width 0.05)) (fp_line (start -3.3 1.15) (end 3.3 1.15) (layer F.CrtYd) (width 0.05)) (fp_line (start -3.3 -1.15) (end -3.3 1.15) (layer F.CrtYd) (width 0.05)) (fp_line (start 3.3 -1.15) (end 3.3 1.15) (layer F.CrtYd) (width 0.05)) (fp_line (start 1 -1.025) (end -1 -1.025) (layer F.SilkS) (width 0.15)) (fp_line (start -1 1.025) (end 1 1.025) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -2 0 180) (size 2 1.6) (layers F.Cu F.Paste F.Mask) (net 77 "Net-(C1-Pad1)")) (pad 2 smd rect (at 2 0 180) (size 2 1.6) (layers F.Cu F.Paste F.Mask) (net 2 GNDPWR)) (model Capacitors_SMD.3dshapes/C_1206_HandSoldering.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Pin_Headers:Pin_Header_Straight_1x06 (layer F.Cu) (tedit 569447A1) (tstamp 569418FE) (at 138.57 108.31 90) (descr "Through hole pin header") (tags "pin header") (path /5694134A) (fp_text reference CRADLE_PORT1 (at 0 -5.1 90) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value CONN_01X06 (at 0 -3.1 90) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -1.75 -1.75) (end -1.75 14.45) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.75 -1.75) (end 1.75 14.45) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.75 14.45) (end 1.75 14.45) (layer F.CrtYd) (width 0.05)) (fp_line (start 1.27 1.27) (end 1.27 13.97) (layer F.SilkS) (width 0.15)) (fp_line (start 1.27 13.97) (end -1.27 13.97) (layer F.SilkS) (width 0.15)) (fp_line (start -1.27 13.97) (end -1.27 1.27) (layer F.SilkS) (width 0.15)) (fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15)) (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15)) (fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) (fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15)) (pad 1 thru_hole rect (at 0 0 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 2 GNDPWR)) (pad 2 thru_hole oval (at 0 2.54 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 2 GNDPWR)) (pad 3 thru_hole oval (at 0 5.08 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 77 "Net-(C1-Pad1)")) (pad 4 thru_hole oval (at 0 7.62 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 11 /ExpansionPort/UART1_TX)) (pad 5 thru_hole oval (at 0 10.16 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 12 /ExpansionPort/UART1_RX)) (pad 6 thru_hole oval (at 0 12.7 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 13 "Net-(CRADLE_PORT1-Pad6)")) (model Pin_Headers.3dshapes/Pin_Header_Straight_1x06.wrl (at (xyz 0 -0.25 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 90)) ) ) (module TO_SOT_Packages_SMD:SOT-23_Handsoldering (layer F.Cu) (tedit 54E9291B) (tstamp 56941905) (at 140.8 98.48 270) (descr "SOT-23, Handsoldering") (tags SOT-23) (path /569420B2) (attr smd) (fp_text reference D1 (at 0 -3.81 270) (layer F.SilkS) (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value D_Schottky_x2_KCom_AAK (at 0 3.81 270) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -1.49982 0.0508) (end -1.49982 -0.65024) (layer F.SilkS) (width 0.15)) (fp_line (start -1.49982 -0.65024) (end -1.2509 -0.65024) (layer F.SilkS) (width 0.15)) (fp_line (start 1.29916 -0.65024) (end 1.49982 -0.65024) (layer F.SilkS) (width 0.15)) (fp_line (start 1.49982 -0.65024) (end 1.49982 0.0508) (layer F.SilkS) (width 0.15)) (pad 1 smd rect (at -0.95 1.50114 270) (size 0.8001 1.80086) (layers F.Cu F.Paste F.Mask) (net 14 /FTDI_PWR)) (pad 2 smd rect (at 0.95 1.50114 270) (size 0.8001 1.80086) (layers F.Cu F.Paste F.Mask) (net 10 +5V)) (pad 3 smd rect (at 0 -1.50114 270) (size 0.8001 1.80086) (layers F.Cu F.Paste F.Mask) (net 77 "Net-(C1-Pad1)")) (model TO_SOT_Packages_SMD.3dshapes/SOT-23_Handsoldering.wrl (at (xyz 0 0 0)) (scale (xyz 1 1 1)) (rotate (xyz 0 0 0)) ) ) (module Pin_Headers:Pin_Header_Angled_1x06 (layer F.Cu) (tedit 56944799) (tstamp 5694190F) (at 138.57 91.35 90) (descr "Through hole pin header") (tags "pin header") (path /5694138D) (fp_text reference PROGRAM_PORT1 (at 0 -5.1 90) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value CONN_01X06 (at 0 -3.1 90) (layer F.Fab) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -1.5 -1.75) (end -1.5 14.45) (layer F.CrtYd) (width 0.05)) (fp_line (start 10.65 -1.75) (end 10.65 14.45) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.5 -1.75) (end 10.65 -1.75) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.5 14.45) (end 10.65 14.45) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.3 -1.55) (end -1.3 0) (layer F.SilkS) (width 0.15)) (fp_line (start 0 -1.55) (end -1.3 -1.55) (layer F.SilkS) (width 0.15)) (fp_line (start 4.191 -0.127) (end 10.033 -0.127) (layer F.SilkS) (width 0.15)) (fp_line (start 10.033 -0.127) (end 10.033 0.127) (layer F.SilkS) (width 0.15)) (fp_line (start 10.033 0.127) (end 4.191 0.127) (layer F.SilkS) (width 0.15)) (fp_line (start 4.191 0.127) (end 4.191 0) (layer F.SilkS) (width 0.15)) (fp_line (start 4.191 0) (end 10.033 0) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 -0.254) (end 1.143 -0.254) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 0.254) (end 1.143 0.254) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 2.286) (end 1.143 2.286) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 2.794) (end 1.143 2.794) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 4.826) (end 1.143 4.826) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 5.334) (end 1.143 5.334) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 12.954) (end 1.143 12.954) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 12.446) (end 1.143 12.446) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 10.414) (end 1.143 10.414) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 9.906) (end 1.143 9.906) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 7.874) (end 1.143 7.874) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 7.366) (end 1.143 7.366) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 -1.27) (end 4.064 -1.27) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 1.27) (end 4.064 1.27) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 1.27) (end 1.524 3.81) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 3.81) (end 4.064 3.81) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 2.286) (end 10.16 2.286) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 2.286) (end 10.16 2.794) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 2.794) (end 4.064 2.794) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 3.81) (end 4.064 1.27) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 1.27) (end 4.064 -1.27) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 0.254) (end 4.064 0.254) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 -0.254) (end 10.16 0.254) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 -0.254) (end 10.16 -0.254) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 1.27) (end 4.064 1.27) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 -1.27) (end 1.524 1.27) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 8.89) (end 4.064 8.89) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 8.89) (end 1.524 11.43) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 11.43) (end 4.064 11.43) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 9.906) (end 10.16 9.906) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 9.906) (end 10.16 10.414) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 10.414) (end 4.064 10.414) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 11.43) (end 4.064 8.89) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 13.97) (end 4.064 11.43) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 12.954) (end 4.064 12.954) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 12.446) (end 10.16 12.954) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 12.446) (end 10.16 12.446) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 13.97) (end 4.064 13.97) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 11.43) (end 1.524 13.97) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 11.43) (end 4.064 11.43) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 6.35) (end 4.064 6.35) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 6.35) (end 1.524 8.89) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 8.89) (end 4.064 8.89) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 7.366) (end 10.16 7.366) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 7.366) (end 10.16 7.874) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 7.874) (end 4.064 7.874) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 8.89) (end 4.064 6.35) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 6.35) (end 4.064 3.81) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 5.334) (end 4.064 5.334) (layer F.SilkS) (width 0.15)) (fp_line (start 10.16 4.826) (end 10.16 5.334) (layer F.SilkS) (width 0.15)) (fp_line (start 4.064 4.826) (end 10.16 4.826) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 6.35) (end 4.064 6.35) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 3.81) (end 1.524 6.35) (layer F.SilkS) (width 0.15)) (fp_line (start 1.524 3.81) (end 4.064 3.81) (layer F.SilkS) (width 0.15)) (pad 1 thru_hole rect (at 0 0 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 2 GNDPWR)) (pad 2 thru_hole oval (at 0 2.54 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 2 GNDPWR)) (pad 3 thru_hole oval (at 0 5.08 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 14 /FTDI_PWR)) (pad 4 thru_hole oval (at 0 7.62 90) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) (net 12 /ExpansionPort/UART1_RX)) (pad 5 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The\nChickadee logo and Polystack logo\nare owned by Chickadee Tech.\n\nYou may license the Polystack logo for\nfree by emailing support@chickadee.tech\nand receiving express written permission\nfrom Chickadee Tech LLC." (at 129.98 145.61) (layer Cmts.User) (effects (font (size 1.5 1.5) (thickness 0.3)) (justify left)) ) (gr_text "Copyright 2016 Chickadee Tech LLC, \n\nThis work is licensed under the Creative Commons Attribution 4.0 International License.\nTo view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/\nor send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA." 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