(kicad_pcb (version 20221018) (generator pcbnew) (general (thickness 1.57112) ) (paper "A4" portrait) (title_block (title "reDIP 64") (date "2022-04-23") (rev "1.0") (company "Nimrod") (comment 1 "© 2021-2022 Dag Lem") (comment 2 "Licensed under CERN-OHL-S v2 (https://ohwr.org/cern_ohl_s_v2.txt)") ) (layers (0 "F.Cu" signal) (1 "In1.Cu" mixed) (2 "In2.Cu" power) (3 "In3.Cu" signal) (4 "In4.Cu" power) (31 "B.Cu" signal) (34 "B.Paste" user) (35 "F.Paste" user) (36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen") (38 "B.Mask" user) (39 "F.Mask" user) (40 "Dwgs.User" user "User.Drawings") (44 "Edge.Cuts" user) (45 "Margin" user) (46 "B.CrtYd" user "B.Courtyard") (47 "F.CrtYd" user "F.Courtyard") (48 "B.Fab" user) (49 "F.Fab" user) ) (setup (stackup (layer "F.SilkS" (type "Top Silk Screen") (color "White")) (layer "F.Paste" (type "Top Solder Paste")) (layer "F.Mask" (type "Top Solder Mask") (color "Black") (thickness 0.01)) (layer "F.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 1" (type "prepreg") (thickness 0.08128 locked) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) (layer "In1.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 2" (type "prepreg") (thickness 0.08128 locked) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) (layer "In2.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 3" (type "core") (thickness 1.016) (material "FR4") (epsilon_r 4.2) (loss_tangent 0.02)) (layer "In3.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 4" (type "prepreg") (thickness 0.08128 locked) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) (layer "In4.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 5" (type "prepreg") (thickness 0.08128 locked) (material "FR4") (epsilon_r 3.9) (loss_tangent 0.02)) (layer "B.Cu" (type "copper") (thickness 0.035)) (layer "B.Mask" (type "Bottom Solder Mask") (color "Black") (thickness 0.01)) (layer "B.Paste" (type "Bottom Solder Paste")) (layer "B.SilkS" (type "Bottom Silk Screen") (color "White")) (copper_finish "ENIG") (dielectric_constraints yes) ) (pad_to_mask_clearance 0.05) (aux_axis_origin 93.65 149.53) (pcbplotparams (layerselection 0x00311fc_ffffffff) (plot_on_all_layers_selection 0x0000000_00000000) (disableapertmacros false) (usegerberextensions false) (usegerberattributes true) (usegerberadvancedattributes true) (creategerberjobfile true) (dashed_line_dash_ratio 12.000000) (dashed_line_gap_ratio 3.000000) (svgprecision 6) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin true) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) (dxfpolygonmode true) (dxfimperialunits true) (dxfusepcbnewfont true) (psnegative false) (psa4output false) (plotreference true) (plotvalue false) (plotinvisibletext false) (sketchpadsonfab false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 0) (scaleselection 1) (outputdirectory "manufacture/") ) ) (net 0 "") (net 1 "GND") (net 2 "+3V3") (net 3 "+1V2") (net 4 "+5V") (net 5 "/Audio/I2C_SDA") (net 6 "/Audio/I2C_SCL") (net 7 "/USB_DisplayPort/RX1+") (net 8 "/USB_DisplayPort/TX2-") (net 9 "/USB_DisplayPort/SBU2") (net 10 "/USB_DisplayPort/CC2") (net 11 "/USB_DisplayPort/TX2+") (net 12 "/USB_DisplayPort/RX1-") (net 13 "/USB_DisplayPort/D-") (net 14 "/USB_DisplayPort/D+") (net 15 "/USB_DisplayPort/RX2-") (net 16 "/USB_DisplayPort/RX2+") (net 17 "/USB_DisplayPort/TX1+") (net 18 "/USB_DisplayPort/TX1-") (net 19 "/USB_DisplayPort/CC1") (net 20 "/USB_DisplayPort/SBU1") (net 21 "/Audio/AUDIO_OUT_R") (net 22 "/Audio/AUDIO_OUT_L") (net 23 "/Audio/EXT_IN_R") (net 24 "/Audio/EXT_IN_L") (net 25 "/FPGA_IO/A13") (net 26 "/FPGA_IO/A12") (net 27 "/FPGA_IO/A11") (net 28 "/FPGA_IO/A10") (net 29 "/FPGA_IO/A9") (net 30 "/FPGA_IO/A8") (net 31 "/FPGA_IO/A7") (net 32 "/FPGA_IO/A6") (net 33 "/FPGA_IO/A5") (net 34 "/FPGA_IO/A4") (net 35 "/FPGA_IO/A3") (net 36 "/FPGA_IO/A2") (net 37 "/FPGA_IO/A1") (net 38 "/FPGA_IO/A0") (net 39 "/FPGA_IO/AEC") (net 40 "/FPGA_IO/~{NMI}") (net 41 "/FPGA_IO/~{IRQ}") (net 42 "/FPGA_IO/RDY") (net 43 "/FPGA_IO/Ø1_IN") (net 44 "/FPGA_IO/A14") (net 45 "/FPGA_IO/A15") (net 46 "/FPGA_IO/P5") (net 47 "/FPGA_IO/P4") (net 48 "/FPGA_IO/P3") (net 49 "/FPGA_IO/P2") (net 50 "/FPGA_IO/P1") (net 51 "/FPGA_IO/P0") (net 52 "/FPGA_IO/D7") (net 53 "/FPGA_IO/D6") (net 54 "/FPGA_IO/D5") (net 55 "/FPGA_IO/D4") (net 56 "/FPGA_IO/D3") (net 57 "/FPGA_IO/D2") (net 58 "/FPGA_IO/D1") (net 59 "/FPGA_IO/D0") (net 60 "/FPGA_IO/R_W") (net 61 "/FPGA_IO/Ø2_OUT") (net 62 "/FPGA_IO/~{RES}") (net 63 "/FPGA_IO/CIA1_~{FLAG}") (net 64 "/FPGA_IO/CIA2_~{FLAG}") (net 65 "/FPGA_IO/CIA1_TOD") (net 66 "/FPGA_IO/CIA2_~{PC}") (net 67 "/FPGA_IO/CIA1_PB7") (net 68 "/FPGA_IO/CIA2_PB7") (net 69 "/FPGA_IO/CIA1_PB6") (net 70 "/FPGA_IO/CIA2_PB6") (net 71 "/FPGA_IO/CIA1_PB5") (net 72 "/FPGA_IO/CIA2_PB5") (net 73 "/FPGA_IO/CIA1_PB4") (net 74 "/FPGA_IO/CIA2_PB4") (net 75 "/FPGA_IO/CIA1_PB3") (net 76 "/FPGA_IO/CIA2_PB3") (net 77 "/FPGA_IO/CIA1_PB2") (net 78 "/FPGA_IO/CIA2_PB2") (net 79 "/FPGA_IO/CIA1_PB1") (net 80 "/FPGA_IO/CIA2_PB1") (net 81 "/FPGA_IO/CIA1_PB0") (net 82 "/FPGA_IO/CIA2_PB0") (net 83 "/FPGA_IO/CIA1_PA7") (net 84 "/FPGA_IO/CIA2_PA7") (net 85 "/FPGA_IO/CIA1_PA6") (net 86 "/FPGA_IO/CIA2_PA6") (net 87 "/FPGA_IO/CIA1_PA5") (net 88 "/FPGA_IO/CIA2_PA5") (net 89 "/FPGA_IO/CIA1_PA4") (net 90 "/FPGA_IO/CIA2_PA4") (net 91 "/FPGA_IO/CIA1_PA3") (net 92 "/FPGA_IO/CIA2_PA3") (net 93 "/FPGA_IO/CIA1_PA2") (net 94 "/FPGA_IO/CIA2_PA2") (net 95 "/FPGA_IO/CIA1_PA1") (net 96 "/FPGA_IO/CIA2_PA1") (net 97 "/FPGA_IO/CIA1_PA0") (net 98 "/FPGA_IO/CIA2_PA0") (net 99 "/FPGA_IO/CIA1_SP") (net 100 "/FPGA_IO/CIA2_SP") (net 101 "/FPGA_IO/CIA1_CNT") (net 102 "/FPGA_IO/CIA2_CNT") (net 103 "/FPGA_IO/~{DMA}") (net 104 "/FPGA_IO/~{EXROM}") (net 105 "/FPGA_IO/~{GAME}") (net 106 "/FPGA_IO/~{ROMH}") (net 107 "/FPGA_IO/~{ROML}") (net 108 "/FPGA_IO/~{IO2}") (net 109 "/FPGA_IO/~{IO1}") (net 110 "/FPGA_IO/DOT_CLOCK") (net 111 "/FPGA_IO/SYNC_LUM") (net 112 "/FPGA_IO/COLOR") (net 113 "/FPGA_IO/BA") (net 114 "/FPGA_IO/POT_Y") (net 115 "/FPGA_IO/POT_X") (net 116 "/USB_DisplayPort/USB_~{CONN}") (net 117 "/FPGA_IO/I2_~{FLAG}") (net 118 "/FPGA_IO/I1_PB7") (net 119 "/FPGA_IO/I1_PB6") (net 120 "/FPGA_IO/I1_PB5") (net 121 "/FPGA_IO/I1_PA6") (net 122 "/FPGA_IO/I1_PA1") (net 123 "/FPGA_IO/I1_PA0") (net 124 "/FPGA_IO/I1_SP") (net 125 "/FPGA_IO/I2_PB6") (net 126 "/FPGA_IO/I2_~{PC}") (net 127 "/FPGA_IO/I1_PB4") (net 128 "/FPGA_IO/I1_PA7") (net 129 "/FPGA_IO/I1_PA2") (net 130 "/FPGA_IO/I1_CNT") (net 131 "/FPGA_IO/I2_PB7") (net 132 "/FPGA_IO/I2_PB5") (net 133 "/FPGA_IO/I2_PB4") (net 134 "/FPGA_IO/I_POT_Y") (net 135 "/FPGA_IO/I1_PB3") (net 136 "/FPGA_IO/I1_PB2") (net 137 "/FPGA_IO/I1_PA5") (net 138 "/FPGA_IO/I1_PA3") (net 139 "/FPGA_IO/I2_PB0") (net 140 "/FPGA_IO/I2_PB3") (net 141 "/FPGA_IO/I2_PB2") (net 142 "/FPGA_IO/I_POT_X") (net 143 "/FPGA_IO/I1_~{FLAG}") (net 144 "/FPGA_IO/I1_PB1") (net 145 "/FPGA_IO/I1_PB0") (net 146 "/FPGA_IO/I1_PA4") (net 147 "/FPGA_IO/I2_PA7") (net 148 "/FPGA_IO/I2_PA5") (net 149 "/FPGA_IO/I2_PB1") (net 150 "/FPGA_IO/I2_PA6") (net 151 "/FPGA_IO/I2_PA1") (net 152 "/FPGA_IO/I2_PA2") (net 153 "/FPGA_IO/I2_PA3") (net 154 "/FPGA_IO/I2_PA4") (net 155 "/FPGA_IO/I2_CNT") (net 156 "/FPGA_IO/I2_SP") (net 157 "/FPGA_IO/I2_PA0") (net 158 "/Audio/I2S_LRCLK") (net 159 "/Audio/I2S_MCLK") (net 160 "/Audio/I2S_SCLK") (net 161 "/Audio/I2S_DIN") (net 162 "/Audio/I2S_DOUT") (net 163 "/FPGA_IO/I_Ø1_IN") (net 164 "/FPGA_IO/I_RDY") (net 165 "/FPGA_IO/I_A0") (net 166 "/FPGA_IO/I_~{IRQ}") (net 167 "/FPGA_IO/I_~{NMI}") (net 168 "/FPGA_IO/I_AEC") (net 169 "/FPGA_IO/I_A1") (net 170 "/FPGA_IO/I_P5") (net 171 "/FPGA_IO/I_P4") (net 172 "/FPGA_IO/I_P3") (net 173 "/FPGA_IO/I_~{RES}") (net 174 "/FPGA_IO/I_Ø2_OUT") (net 175 "/FPGA_IO/I_R_W") (net 176 "/FPGA_IO/I_A3") (net 177 "/FPGA_IO/I_A4") (net 178 "/FPGA_IO/I_A5") (net 179 "/FPGA_IO/I_A2") (net 180 "/FPGA_IO/I_~{IO1}") (net 181 "/FPGA_IO/I_~{IO2}") (net 182 "/FPGA_IO/I_~{ROML}") (net 183 "/FPGA_IO/I_~{ROMH}") (net 184 "/FPGA_IO/I_D3") (net 185 "/FPGA_IO/I_D1") (net 186 "/FPGA_IO/I_D2") (net 187 "/FPGA_IO/I_D0") (net 188 "/FPGA_IO/I_A7") (net 189 "/FPGA_IO/I_A6") (net 190 "/FPGA_IO/I_A9") (net 191 "/FPGA_IO/I_COLOR") (net 192 "/FPGA_IO/I_BA") (net 193 "/FPGA_IO/I_~{EXROM}") (net 194 "/FPGA_IO/I_D7") (net 195 "/FPGA_IO/I_D4") (net 196 "/FPGA_IO/I_D5") (net 197 "/FPGA_IO/I_A12") (net 198 "/FPGA_IO/I_A8") (net 199 "/FPGA_IO/I_A10") (net 200 "/FPGA_IO/I_A11") (net 201 "/FPGA_IO/I_DOT_CLOCK") (net 202 "/FPGA_IO/I_SYNC_LUM") (net 203 "/FPGA_IO/I_~{DMA}") (net 204 "/FPGA_IO/I_~{GAME}") (net 205 "/FPGA_IO/I_P0") (net 206 "/FPGA_IO/I_P2") (net 207 "/FPGA_IO/I_D6") (net 208 "/FPGA_IO/I_P1") (net 209 "/FPGA_IO/I_A14") (net 210 "/FPGA_IO/I_A15") (net 211 "/FPGA_IO/I_A13") (net 212 "/USB_DisplayPort/RX-") (net 213 "/USB_DisplayPort/RX+") (net 214 "/USB_DisplayPort/TX-") (net 215 "/USB_DisplayPort/TX+") (net 216 "/USB_DisplayPort/AUX+") (net 217 "/USB_DisplayPort/AUX-") (net 218 "/USB_DisplayPort/USB_~{FLIP}") (net 219 "VCC") (net 220 "/USB_DisplayPort/CLK-") (net 221 "/USB_DisplayPort/CLK+") (net 222 "+2V5") (net 223 "/Power/~{FAULT}") (net 224 "/Power/EN_SNK") (net 225 "/Power/EN_SRC") (net 226 "/USB_DisplayPort/USB_LINK") (net 227 "/FPGA_IO/~{ALERT}") (net 228 "VCCA") (net 229 "VDDD") (net 230 "VDDA") (net 231 "/USB_DisplayPort/ML0-") (net 232 "/USB_DisplayPort/ML0+") (net 233 "/USB_DisplayPort/ML1-") (net 234 "/USB_DisplayPort/ML1+") (net 235 "/FPGA_IO/USB_D+") (net 236 "/FPGA_IO/USB_D-") (net 237 "/FPGA_IO/DP_AUX+") (net 238 "/FPGA_IO/DP_AUX-") (net 239 "/Config_Memory/TMS") (net 240 "/Config_Memory/TCK") (net 241 "/Config_Memory/TDI") (net 242 "/Config_Memory/TDO") (net 243 "/Config_Memory/RAM_~{CS}") (net 244 "/Config_Memory/MEM_CLK") (net 245 "/Config_Memory/FLASH_~{CS}") (net 246 "/Config_Memory/~{BOOT}") (net 247 "/Config_Memory/MEM_IO0") (net 248 "/Config_Memory/MEM_IO1") (net 249 "/Config_Memory/MEM_IO2") (net 250 "/Config_Memory/MEM_IO3") (net 251 "/Config_Memory/MEM_IO4") (net 252 "/Config_Memory/RWDS") (net 253 "/Config_Memory/MEM_IO5") (net 254 "/Config_Memory/MEM_IO6") (net 255 "/Config_Memory/MEM_IO7") (net 256 "/Config_Memory/LED") (net 257 "VCBT") (net 258 "Net-(U1-BYPASS)") (net 259 "/Power/EN_VCC") (net 260 "Net-(U9-EN)") (net 261 "Net-(U9-FB)") (net 262 "Net-(U12-EN)") (net 263 "Net-(U12-FB)") (net 264 "Net-(U23-VAG)") (net 265 "/FPGA_IO/I1_TOD") (net 266 "VBUS") (net 267 "Net-(C10-Pad1)") (net 268 "Net-(C11-Pad1)") (net 269 "Net-(U23-HP_R)") (net 270 "Net-(U23-HP_L)") (net 271 "unconnected-(D4-DO-Pad1)") (net 272 "Net-(U9-SW)") (net 273 "Net-(U12-SW)") (net 274 "Net-(U6-OVLO)") (net 275 "Net-(U10-ISET)") (net 276 "Net-(U2H-CFG_1)") (net 277 "unconnected-(U1-SLV_ADDR-Pad5)") (net 278 "unconnected-(U2H-DONE-PadU15)") (net 279 "unconnected-(U2J-HDRXN0_D0CH1-PadV5)") (net 280 "unconnected-(U2J-HDRXP0_D0CH1-PadV6)") (net 281 "unconnected-(U2J-HDRXN0_D0CH0-PadV8)") (net 282 "unconnected-(U2J-HDRXP0_D0CH0-PadV9)") (net 283 "unconnected-(U2H-INITN-PadV16)") (net 284 "unconnected-(U4-NC-Pad2)") (net 285 "unconnected-(U17-NC-Pad1)") (net 286 "unconnected-(U17-2A10-Pad26)") (net 287 "unconnected-(U17-2A11-Pad27)") (net 288 "unconnected-(U17-2A12-Pad28)") (net 289 "unconnected-(U17-2B12-Pad29)") (net 290 "unconnected-(U17-2B11-Pad30)") (net 291 "unconnected-(U17-2B10-Pad31)") (net 292 "unconnected-(U18-NC-Pad1)") (net 293 "unconnected-(U19-NC-Pad1)") (net 294 "unconnected-(U19-1A1-Pad2)") (net 295 "unconnected-(U19-1B1-Pad54)") (net 296 "unconnected-(U20-NC-Pad1)") (net 297 "unconnected-(U21-RFU-PadA2)") (net 298 "unconnected-(U21-~{RESET}-PadA4)") (net 299 "unconnected-(U21-RFU-PadA5)") (net 300 "unconnected-(U21-~{CK}-PadB1)") (net 301 "unconnected-(U21-RFU-PadB5)") (net 302 "/FPGA_IO/~{BTN}") (net 303 "/Config_Memory/MCLK") (net 304 "/FPGA_IO/I_~{BTN}") (net 305 "unconnected-(U21-RFU-PadC2)") (net 306 "unconnected-(U21-RFU-PadC5)") (net 307 "unconnected-(U23-HP_VGND-Pad2)") (net 308 "unconnected-(U23-LINEOUT_R-Pad6)") (net 309 "Net-(C14-Pad1)") (net 310 "unconnected-(U23-LINEOUT_L-Pad7)") (net 311 "unconnected-(U23-MIC-Pad10)") (net 312 "unconnected-(U23-MIC_BIAS-Pad11)") (footprint "reDIP:PinHeader_1x20_P2.54mm_Vertical" (layer "F.Cu") (tstamp 00000000-0000-0000-0000-00006025e288) (at 117.78 100) (descr "Through hole straight pin header, 1x20, 2.54mm pitch, single row") (tags "Through hole pin header THT 1x20 2.54mm single row") (property "Description" "CONN HDR SQ PIN 0.64mm 20 POS .100\" GOLD MATING 6mm TAIL 3mm") (property "Mfg" "Sullins") (property "PN" "PRPC010SAAN-RC") (property "Sheetfile" "reDIP-64-FPGA.kicad_sch") (property "Sheetname" "FPGA_IO") (property "ki_description" "Generic connector, single row, 01x20, script generated (kicad-library-utils/schlib/autogen/connector/)") (property "ki_keywords" "connector") (path "/00000000-0000-0000-0000-000060305eb8/00000000-0000-0000-0000-0000656c868e") (attr through_hole) (fp_text reference "J3" (at 0 -2.33) (layer "F.SilkS") hide (effects (font (size 1 1) (thickness 0.15))) (tstamp ae5adbe0-d4f4-4499-84c2-96c108c01944) ) (fp_text value "Conn_01x20" (at 0 50.59) (layer "F.Fab") hide (effects (font (size 1 1) (thickness 0.15))) (tstamp 29a1b362-06a3-42e9-a1e1-a3b8ef03e810) ) (fp_text user "${REFERENCE}" (at 0 24.13 90) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15))) (tstamp 01a19697-1787-44f1-b107-b6569570ef96) ) (fp_line (start -1.8 -1.8) (end -1.8 50.05) (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 57d94033-126d-420d-8b3a-9b7fbf7eeca1)) (fp_line (start -1.8 50.05) (end 1.8 50.05) (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp ca139955-ae4a-4f12-baae-1edc1b1ba6cf)) (fp_line (start 1.8 -1.8) (end -1.8 -1.8) (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 6867fe5f-423d-46a6-9bc1-bcd09089bcf0)) (fp_line (start 1.8 50.05) (end 1.8 -1.8) (stroke (width 0.05) (type solid)) (layer "F.CrtYd") (tstamp 3513539e-868e-4073-9274-1bf9687ef32c)) (fp_line (start -1.27 -0.635) (end -0.635 -1.27) (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp d2461a3e-9011-4f86-a0c8-1c6fa49c2c62)) (fp_line (start -1.27 49.53) (end -1.27 -0.635) (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 0bd9d32e-ab2e-4f48-a496-832b07d6c45c)) (fp_line (start -0.635 -1.27) (end 1.27 -1.27) (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 6705b1c9-53a0-4107-8593-d5cefc415e23)) (fp_line (start 1.27 -1.27) (end 1.27 49.53) (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp a054f6c1-434b-4502-9a21-349d00910154)) (fp_line (start 1.27 49.53) (end -1.27 49.53) (stroke (width 0.1) (type solid)) (layer "F.Fab") (tstamp 22c6b221-5a82-4b35-8206-a32788dce6dd)) (pad "1" thru_hole circle (at 0 0) (size 1.6 1.6) (drill 1) (layers "*.Cu" "*.Mask") (net 2 "+3V3") (pinfunction "Pin_1") (pintype "passive") (tstamp 265f33cd-d975-4da0-9a01-2f53aff7dbb0)) (pad "2" thru_hole circle (at 0 2.54) (size 1.6 1.6) (drill 1) (layers "*.Cu" "*.Mask") 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