(kicad_pcb
	(version 20241229)
	(generator "pcbnew")
	(generator_version "9.0")
	(general
		(thickness 1.6)
		(legacy_teardrops no)
	)
	(paper "A4")
	(title_block
		(title "EEG_PROTOTYPE")
		(date "2026-09-01")
		(rev "Ver_01")
		(company "Lugo, Obregon")
		(comment 1 "Prototipo de EEG portatil")
	)
	(layers
		(0 "F.Cu" signal)
		(2 "B.Cu" signal)
		(9 "F.Adhes" user "F.Adhesive")
		(11 "B.Adhes" user "B.Adhesive")
		(13 "F.Paste" user)
		(15 "B.Paste" user)
		(5 "F.SilkS" user "F.Silkscreen")
		(7 "B.SilkS" user "B.Silkscreen")
		(1 "F.Mask" user)
		(3 "B.Mask" user)
		(17 "Dwgs.User" user "User.Drawings")
		(19 "Cmts.User" user "User.Comments")
		(21 "Eco1.User" user "User.Eco1")
		(23 "Eco2.User" user "User.Eco2")
		(25 "Edge.Cuts" user)
		(27 "Margin" user)
		(31 "F.CrtYd" user "F.Courtyard")
		(29 "B.CrtYd" user "B.Courtyard")
		(35 "F.Fab" user)
		(33 "B.Fab" user)
		(39 "User.1" user)
		(41 "User.2" user)
		(43 "User.3" user)
		(45 "User.4" user)
	)
	(setup
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			(layer "F.SilkS"
				(type "Top Silk Screen")
			)
			(layer "F.Paste"
				(type "Top Solder Paste")
			)
			(layer "F.Mask"
				(type "Top Solder Mask")
				(thickness 0.01)
			)
			(layer "F.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "dielectric 1"
				(type "core")
				(thickness 1.51)
				(material "FR4")
				(epsilon_r 4.5)
				(loss_tangent 0.02)
			)
			(layer "B.Cu"
				(type "copper")
				(thickness 0.035)
			)
			(layer "B.Mask"
				(type "Bottom Solder Mask")
				(thickness 0.01)
			)
			(layer "B.Paste"
				(type "Bottom Solder Paste")
			)
			(layer "B.SilkS"
				(type "Bottom Silk Screen")
			)
			(copper_finish "None")
			(dielectric_constraints no)
		)
		(pad_to_mask_clearance 0)
		(allow_soldermask_bridges_in_footprints no)
		(tenting front back)
		(pcbplotparams
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			(usegerberattributes yes)
			(usegerberadvancedattributes yes)
			(creategerberjobfile yes)
			(dashed_line_dash_ratio 12.000000)
			(dashed_line_gap_ratio 3.000000)
			(svgprecision 4)
			(plotframeref no)
			(mode 1)
			(useauxorigin no)
			(hpglpennumber 1)
			(hpglpenspeed 20)
			(hpglpendiameter 15.000000)
			(pdf_front_fp_property_popups yes)
			(pdf_back_fp_property_popups yes)
			(pdf_metadata yes)
			(pdf_single_document no)
			(dxfpolygonmode yes)
			(dxfimperialunits yes)
			(dxfusepcbnewfont yes)
			(psnegative no)
			(psa4output no)
			(plot_black_and_white yes)
			(sketchpadsonfab no)
			(plotpadnumbers no)
			(hidednponfab no)
			(sketchdnponfab yes)
			(crossoutdnponfab yes)
			(subtractmaskfromsilk no)
			(outputformat 1)
			(mirror no)
			(drillshape 0)
			(scaleselection 1)
			(outputdirectory "EEG_Prototype_Gerbers/")
		)
	)
	(net 0 "")
	(net 1 "Net-(C1-Pad1)")
	(net 2 "Net-(C1-Pad2)")
	(net 3 "Net-(U2B--)")
	(net 4 "Net-(U2C--)")
	(net 5 "Net-(C3-Pad1)")
	(net 6 "Net-(C4-Pad2)")
	(net 7 "Net-(U2D--)")
	(net 8 "Net-(C5-Pad1)")
	(net 9 "Net-(C6-Pad2)")
	(net 10 "Net-(U3A--)")
	(net 11 "Net-(C7-Pad1)")
	(net 12 "/Vout_filter")
	(net 13 "Net-(C10-Pad1)")
	(net 14 "Net-(C9-Pad1)")
	(net 15 "Net-(U3D-+)")
	(net 16 "GND")
	(net 17 "Net-(C11-Pad2)")
	(net 18 "unconnected-(J1-Pin_10-Pad10)")
	(net 19 "unconnected-(J1-Pin_12-Pad12)")
	(net 20 "unconnected-(J1-Pin_5-Pad5)")
	(net 21 "unconnected-(J1-Pin_7-Pad7)")
	(net 22 "unconnected-(J1-Pin_3-Pad3)")
	(net 23 "/GPIO22")
	(net 24 "/GPIO21")
	(net 25 "unconnected-(J1-Pin_8-Pad8)")
	(net 26 "unconnected-(J1-Pin_6-Pad6)")
	(net 27 "unconnected-(J1-Pin_4-Pad4)")
	(net 28 "unconnected-(J1-Pin_9-Pad9)")
	(net 29 "/GPIO23")
	(net 30 "unconnected-(J1-Pin_13-Pad13)")
	(net 31 "/3.3V")
	(net 32 "unconnected-(J2-Pin_7-Pad7)")
	(net 33 "unconnected-(J2-Pin_4-Pad4)")
	(net 34 "unconnected-(J2-Pin_5-Pad5)")
	(net 35 "unconnected-(J2-Pin_12-Pad12)")
	(net 36 "unconnected-(J2-Pin_6-Pad6)")
	(net 37 "unconnected-(J2-Pin_15-Pad15)")
	(net 38 "unconnected-(J2-Pin_9-Pad9)")
	(net 39 "unconnected-(J2-Pin_14-Pad14)")
	(net 40 "unconnected-(J2-Pin_10-Pad10)")
	(net 41 "unconnected-(J2-Pin_2-Pad2)")
	(net 42 "unconnected-(J2-Pin_3-Pad3)")
	(net 43 "unconnected-(J2-Pin_11-Pad11)")
	(net 44 "unconnected-(J2-Pin_13-Pad13)")
	(net 45 "unconnected-(J2-Pin_1-Pad1)")
	(net 46 "unconnected-(J2-Pin_8-Pad8)")
	(net 47 "Net-(J4-Pin_1)")
	(net 48 "Net-(J5-Pin_1)")
	(net 49 "Net-(J6-Pin_1)")
	(net 50 "Net-(J6-Pin_3)")
	(net 51 "Net-(U2A--)")
	(net 52 "/Vo")
	(net 53 "Net-(U2B-+)")
	(net 54 "Net-(U2C-+)")
	(net 55 "Net-(U2D-+)")
	(net 56 "Net-(U3A-+)")
	(net 57 "/+9V")
	(net 58 "Net-(U3B-+)")
	(net 59 "Net-(U3C-+)")
	(net 60 "Net-(U3B--)")
	(net 61 "Net-(U3C--)")
	(net 62 "/OUT")
	(net 63 "Net-(U4-ADDR)")
	(net 64 "Net-(RG1-Pad1)")
	(net 65 "Net-(RG1-Pad2)")
	(net 66 "/-9V")
	(net 67 "Net-(U2A-+)")
	(net 68 "unconnected-(U4-AIN2-Pad6)")
	(net 69 "unconnected-(U4-AIN3-Pad7)")
	(net 70 "unconnected-(U4-AIN1-Pad5)")
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		(property "Reference" "R24"
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		(pad "1" thru_hole circle
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			(size 1.4 1.4)
			(drill 0.7)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net 61 "Net-(U3C--)")
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		(pad "2" thru_hole circle
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		)
		(embedded_fonts no)
		(model "${KICAD9_3DMODEL_DIR}/Resistor_THT.3dshapes/R_Axial_DIN0204_L3.6mm_D1.6mm_P5.08mm_Horizontal.step"
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				(xyz 0 0 0)
			)
			(scale
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		)
	)
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		(uuid "02f79bc0-f66b-461e-9e40-c7d3aa283610")
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		(descr "C, Disc series, Radial, pin pitch=5.00mm, diameter*width=4.7*2.5mm^2, Capacitor, http://www.vishay.com/docs/45233/krseries.pdf")
		(tags "C Disc series Radial pin pitch 5.00mm diameter 4.7mm width 2.5mm Capacitor")
		(property "Reference" "C9"
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