# Fabrication notes — NeuroFocus Mark 3

## What this release is good for

- Exact **connectivity** (netlists) + **Gerber zips** for all three boards.
- Rebuild with modules (XIAO + ADS1220 breakout + AFE) if you skip custom fab.
- Firmware and host tools against a known pin map.

## Deliverables

| Asset | Path | Status |
|-------|------|--------|
| Netlists | `schematic/netlist/nf-mark3-*.tel` | ✅ |
| Gerbers | `schematic/gerber/nf-mark3-*.zip` | ✅ |
| Schematic drawings | `schematic/drawings/*.png` | ✅ |
| PCB layout screenshots | `assets/pcb/*.png` | ✅ |
| BOM / pinout | `docs/` | ✅ |
| Photos of built boards | `hardware/photos/` | ✅ |

## Order path (JLCPCB / PCBWay / …)

1. Upload the matching zip from `schematic/gerber/`.
2. Confirm layer count / thickness from the zip’s `*.gbr` set (open in a Gerber viewer).
3. Stuff per [BOM.md](BOM.md); verify R7 on AFE before claiming µV accuracy.
4. Flash [`firmware/`](../firmware/) to the XIAO on the **main** board.

## Expansion as SPI device

`nf-mark3-expansion` has no MCU. Wire U5 to a host:

| Expansion U5 | Host (XIAO names) |
|--------------|-------------------|
| CS | D7 |
| DRDY | D5 |
| SCK | D8 |
| MISO | D9 |
| MOSI | D10 |
| VCC | 3V3 |
| GND | GND |

Same firmware bit-bangs that map via `nf/BoardPins.h`.

## Path without custom PCB

1. XIAO ESP32-S3  
2. ADS1220 breakout  
3. Wire SPI per [PINOUT.md](PINOUT.md)  
4. Optional AD8422 eval / AFE into OUT0  
5. `pio run -t upload` in `firmware/`