<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1.0.xsd">
<name>esp32</name>
<version>1.0</version>
<cpu>
<name>Xtensa LX6</name>
<revision>1</revision>
<endian>little</endian>
<mpuPresent>false</mpuPresent>
<fpuPresent>true</fpuPresent>
<nvicPrioBits>3</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<width>32</width>
<peripherals>
<peripheral>
<name>AES</name>
<baseAddress>0x3ff01000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>START</name>
<description>AES Start</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>START</name>
<description>Write 1 to start AES operation</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDLE</name>
<description>AES Idle</description>
<addressOffset>4</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>1</resetValue>
<fields>
<field>
<name>IDLE</name>
<description>0 when AES is busy, 1 otherwise</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MODE</name>
<description>AES Mode</description>
<addressOffset>8</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>MODE</name>
<description>Selects AES accelerator mode</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>MODE</name>
<usage>read-write</usage>
<enumeratedValue>
<name>AES128_ENCRYPT</name>
<description>AES-128 Encryption</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>AES192_ENCRYPT</name>
<description>AES-192 Encryption</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>AES256_ENCRYPT</name>
<description>AES-256 Encryption</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>AES128_DECRYPT</name>
<description>AES-128 Decryption</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>AES192_DECRYPT</name>
<description>AES-192 Decryption</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>AES256_DECRYPT</name>
<description>AES-256 Decryption</description>
<value>6</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>KEY_0</name>
<description>AES Key material 0</description>
<addressOffset>16</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>KEY_1</name>
<description>AES Key material 1</description>
<addressOffset>20</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>KEY_2</name>
<description>AES Key material 2</description>
<addressOffset>24</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>KEY_3</name>
<description>AES Key material 3</description>
<addressOffset>28</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>KEY_4</name>
<description>AES Key material 4</description>
<addressOffset>32</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>KEY_5</name>
<description>AES Key material 5</description>
<addressOffset>36</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>KEY_6</name>
<description>AES Key material 6</description>
<addressOffset>40</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>KEY_7</name>
<description>AES Key material 7</description>
<addressOffset>44</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>TEXT_0</name>
<description>Plaintext and ciphertext register 0</description>
<addressOffset>48</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>TEXT_1</name>
<description>Plaintext and ciphertext register 1</description>
<addressOffset>52</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>TEXT_2</name>
<description>Plaintext and ciphertext register 2</description>
<addressOffset>56</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>TEXT_3</name>
<description>Plaintext and ciphertext register 3</description>
<addressOffset>60</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
</register>
<register>
<name>ENDIAN</name>
<description>AES Endian selection</description>
<addressOffset>64</addressOffset>
<size>32</size>
<resetValue>63</resetValue>
<fields>
<field>
<name>MODE</name>
<description>Select AES endian mode</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>HINF</name>
<baseAddress>0x3ff4b000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x000001a0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CFG_DATA0</name>
<description>HINF_CFG_DATA0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DEVICE_ID_FN1</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>USER_ID_FN1</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFG_DATA1</name>
<description>HINF_CFG_DATA1</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIO20_CONF1</name>
<bitOffset>29</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>FUNC2_EPS</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_VER</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>SDIO20_CONF0</name>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IOENABLE1</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EMP</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUNC1_EPS</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CD_DISABLE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IOENABLE2</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_INT_MASK</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_IOREADY2</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_CD_ENABLE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HIGHSPEED_MODE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HIGHSPEED_ENABLE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_IOREADY1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_ENABLE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFG_DATA7</name>
<description>HINF_CFG_DATA7</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIO_IOREADY0</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_RST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHIP_STATE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PIN_STATE</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS_CONF0</name>
<description>HINF_CIS_CONF0</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CIS_CONF_W0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS_CONF1</name>
<description>HINF_CIS_CONF1</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CIS_CONF_W1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS_CONF2</name>
<description>HINF_CIS_CONF2</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CIS_CONF_W2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS_CONF3</name>
<description>HINF_CIS_CONF3</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CIS_CONF_W3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS_CONF4</name>
<description>HINF_CIS_CONF4</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CIS_CONF_W4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS_CONF5</name>
<description>HINF_CIS_CONF5</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CIS_CONF_W5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS_CONF6</name>
<description>HINF_CIS_CONF6</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CIS_CONF_W6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CIS_CONF7</name>
<description>HINF_CIS_CONF7</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CIS_CONF_W7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CFG_DATA16</name>
<description>HINF_CFG_DATA16</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DEVICE_ID_FN2</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>USER_ID_FN2</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>HINF_DATE</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIO_DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SPI</name>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000860</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SPI1_DMA_INTR</name>
<description>interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this</description>
<value>52</value>
</interrupt>
<interrupt>
<name>SPI2_DMA_INTR</name>
<description>interrupt of SPI2 DMA, level</description>
<value>53</value>
</interrupt>
<interrupt>
<name>SPI3_DMA_INTR</name>
<description>interrupt of SPI3 DMA, level</description>
<value>54</value>
</interrupt>
<registers>
<register>
<name>CMD</name>
<description>SPI_CMD</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLASH_READ</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_WREN</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_WRDI</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_RDID</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_RDSR</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_WRSR</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_PP</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_SE</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_BE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_CE</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_DP</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_RES</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_HPM</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_PES</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FLASH_PER</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>SPI_CTRL</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WR_BIT_ORDER</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_BIT_ORDER</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREAD_QIO</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREAD_DIO</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WRSR_2B</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WP_REG</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREAD_QUAD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESANDRES</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FREAD_DUAL</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTRD_MODE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAIT_FLASH_IDLE_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CRC_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FCS_CRC_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL1</name>
<description>SPI_CTRL1</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CS_HOLD_DELAY</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CS_HOLD_DELAY_RES</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>RD_STATUS</name>
<description>SPI_RD_STATUS</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_EXT</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WB_MODE</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>STATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL2</name>
<description>SPI_CTRL2</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CS_DELAY_NUM</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CS_DELAY_MODE</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MOSI_DELAY_NUM</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MOSI_DELAY_MODE</name>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MISO_DELAY_NUM</name>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MISO_DELAY_MODE</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CK_OUT_HIGH_MODE</name>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CK_OUT_LOW_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HOLD_TIME</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SETUP_TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLOCK</name>
<description>SPI_CLOCK</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EQU_SYSCLK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKDIV_PRE</name>
<bitOffset>18</bitOffset>
<bitWidth>13</bitWidth>
</field>
<field>
<name>CLKCNT_N</name>
<bitOffset>12</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CLKCNT_H</name>
<bitOffset>6</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CLKCNT_L</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>USER</name>
<description>SPI_USER</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>USR_COMMAND</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_ADDR</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_DUMMY</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_MISO</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_MOSI</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_DUMMY_IDLE</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_MOSI_HIGHPART</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_MISO_HIGHPART</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_PREP_HOLD</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_CMD_HOLD</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_ADDR_HOLD</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_DUMMY_HOLD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_DIN_HOLD</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_DOUT_HOLD</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_HOLD_POL</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIO</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FWRITE_QIO</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FWRITE_DIO</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FWRITE_QUAD</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FWRITE_DUAL</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WR_BYTE_ORDER</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_BYTE_ORDER</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_OUT_EDGE</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_I_EDGE</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS_SETUP</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS_HOLD</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DOUTDIN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>USER1</name>
<description>SPI_USER1</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>USR_ADDR_BITLEN</name>
<bitOffset>26</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>USR_DUMMY_CYCLELEN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>USER2</name>
<description>SPI_USER2</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>USR_COMMAND_BITLEN</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>USR_COMMAND_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>MOSI_DLEN</name>
<description>SPI_MOSI_DLEN</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>USR_MOSI_DBITLEN</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>MISO_DLEN</name>
<description>SPI_MISO_DLEN</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>USR_MISO_DBITLEN</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLV_WR_STATUS</name>
<description>SPI_SLV_WR_STATUS</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLV_WR_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PIN</name>
<description>SPI_PIN</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CS_KEEP_ACTIVE</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK_IDLE_EDGE</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASTER_CK_SEL</name>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MASTER_CS_POL</name>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CK_DIS</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS2_DIS</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS1_DIS</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CS0_DIS</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLAVE</name>
<description>SPI_SLAVE</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SYNC_RESET</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_MODE</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_WR_RD_BUF_EN</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_WR_RD_STA_EN</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_CMD_DEFINE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_CNT</name>
<bitOffset>23</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SLV_LAST_STATE</name>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SLV_LAST_COMMAND</name>
<bitOffset>17</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CS_I_MODE</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INT_EN</name>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TRANS_DONE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_WR_STA_DONE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_RD_STA_DONE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_WR_BUF_DONE</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_RD_BUF_DONE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLAVE1</name>
<description>SPI_SLAVE1</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLV_STATUS_BITLEN</name>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SLV_STATUS_FAST_EN</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_STATUS_READBACK</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_RD_ADDR_BITLEN</name>
<bitOffset>10</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SLV_WR_ADDR_BITLEN</name>
<bitOffset>4</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SLV_WRSTA_DUMMY_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_RDSTA_DUMMY_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_WRBUF_DUMMY_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLV_RDBUF_DUMMY_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLAVE2</name>
<description>SPI_SLAVE2</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLV_WRBUF_DUMMY_CYCLELEN</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SLV_RDBUF_DUMMY_CYCLELEN</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SLV_WRSTA_DUMMY_CYCLELEN</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SLV_RDSTA_DUMMY_CYCLELEN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLAVE3</name>
<description>SPI_SLAVE3</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLV_WRSTA_CMD_VALUE</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SLV_RDSTA_CMD_VALUE</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SLV_WRBUF_CMD_VALUE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SLV_RDBUF_CMD_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLV_WRBUF_DLEN</name>
<description>SPI_SLV_WRBUF_DLEN</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLV_WRBUF_DBITLEN</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLV_RDBUF_DLEN</name>
<description>SPI_SLV_RDBUF_DLEN</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLV_RDBUF_DBITLEN</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>CACHE_FCTRL</name>
<description>SPI_CACHE_FCTRL</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CACHE_FLASH_PES_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_FLASH_USR_CMD</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_USR_CMD_4BYTE</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_REQ_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CACHE_SCTRL</name>
<description>SPI_CACHE_SCTRL</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CACHE_SRAM_USR_WCMD</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM_ADDR_BITLEN</name>
<bitOffset>22</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SRAM_DUMMY_CYCLELEN</name>
<bitOffset>14</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SRAM_BYTES_LEN</name>
<bitOffset>6</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CACHE_SRAM_USR_RCMD</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_RD_SRAM_DUMMY</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_WR_SRAM_DUMMY</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_SRAM_QIO</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>USR_SRAM_DIO</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRAM_CMD</name>
<description>SPI_SRAM_CMD</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SRAM_RSTIO</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM_QIO</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SRAM_DIO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRAM_DRD_CMD</name>
<description>SPI_SRAM_DRD_CMD</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CACHE_SRAM_USR_RD_CMD_BITLEN</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CACHE_SRAM_USR_RD_CMD_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRAM_DWR_CMD</name>
<description>SPI_SRAM_DWR_CMD</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CACHE_SRAM_USR_WR_CMD_BITLEN</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CACHE_SRAM_USR_WR_CMD_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLV_RD_BIT</name>
<description>SPI_SLV_RD_BIT</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLV_RDATA_BIT</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<dim>16</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15</dimIndex>
<name>W%s</name>
<description>SPI_W%s</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BUF</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TX_CRC</name>
<description>SPI_TX_CRC</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_CRC_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT0</name>
<description>SPI_EXT0</description>
<addressOffset>0xf0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T_PP_ENA</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T_PP_SHIFT</name>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>T_PP_TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT1</name>
<description>SPI_EXT1</description>
<addressOffset>0xf4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T_ERASE_ENA</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T_ERASE_SHIFT</name>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>T_ERASE_TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT2</name>
<description>SPI_EXT2</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ST</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT3</name>
<description>SPI_EXT3</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INT_HOLD_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_CONF</name>
<description>SPI_DMA_CONF</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_CONTINUE</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_TX_STOP</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_RX_STOP</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DATA_BURST_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INDSCR_BURST_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTDSCR_BURST_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_MODE</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_AUTO_WRBACK</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_LOOP_TEST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_LOOP_TEST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBM_RST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBM_FIFO_RST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_RST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_RST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_LINK</name>
<description>SPI_DMA_OUT_LINK</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_LINK</name>
<description>SPI_DMA_IN_LINK</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_AUTO_RET</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_STATUS</name>
<description>SPI_DMA_STATUS</description>
<addressOffset>0x10c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_TX_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DMA_RX_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_INT_ENA</name>
<description>SPI_DMA_INT_ENA</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_TOTAL_EOF_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_DSCR_ERROR_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_DSCR_ERROR_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_DSCR_EMPTY_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_INT_RAW</name>
<description>SPI_DMA_INT_RAW</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_TOTAL_EOF_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_DSCR_ERROR_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_DSCR_ERROR_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_DSCR_EMPTY_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_INT_ST</name>
<description>SPI_DMA_INT_ST</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_TOTAL_EOF_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_DSCR_ERROR_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_DSCR_ERROR_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_DSCR_EMPTY_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_INT_CLR</name>
<description>SPI_DMA_INT_CLR</description>
<addressOffset>0x11c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_TOTAL_EOF_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_DSCR_ERROR_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_DSCR_ERROR_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_DSCR_EMPTY_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IN_ERR_EOF_DES_ADDR</name>
<description>SPI_IN_ERR_EOF_DES_ADDR</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_IN_ERR_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IN_SUC_EOF_DES_ADDR</name>
<description>SPI_IN_SUC_EOF_DES_ADDR</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_IN_SUC_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>INLINK_DSCR</name>
<description>SPI_INLINK_DSCR</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_INLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>INLINK_DSCR_BF0</name>
<description>SPI_INLINK_DSCR_BF0</description>
<addressOffset>0x12c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_INLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>INLINK_DSCR_BF1</name>
<description>SPI_INLINK_DSCR_BF1</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_INLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_EOF_BFR_DES_ADDR</name>
<description>SPI_OUT_EOF_BFR_DES_ADDR</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_OUT_EOF_BFR_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_EOF_DES_ADDR</name>
<description>SPI_OUT_EOF_DES_ADDR</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_OUT_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTLINK_DSCR</name>
<description>SPI_OUTLINK_DSCR</description>
<addressOffset>0x13c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_OUTLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTLINK_DSCR_BF0</name>
<description>SPI_OUTLINK_DSCR_BF0</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_OUTLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTLINK_DSCR_BF1</name>
<description>SPI_OUTLINK_DSCR_BF1</description>
<addressOffset>0x144</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_OUTLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_RSTATUS</name>
<description>SPI_DMA_RSTATUS</description>
<addressOffset>0x148</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_OUT_STATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_TSTATUS</name>
<description>SPI_DMA_TSTATUS</description>
<addressOffset>0x14c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_IN_STATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>SPI_DATE</description>
<addressOffset>0x3fc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="I2C">
<name>I2C1</name>
<baseAddress>0x3ff67000</baseAddress>
</peripheral>
<peripheral>
<name>I2C</name>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x000004c0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2C_EXT0_INTR</name>
<description>interrupt of I2C controller0, level</description>
<value>49</value>
</interrupt>
<interrupt>
<name>I2C_EXT1_INTR</name>
<description>interrupt of I2C controller1, level</description>
<value>50</value>
</interrupt>
<interrupt>
<name>PWM0_INTR</name>
<description>interrupt of PWM0, level, Reserved</description>
<value>39</value>
</interrupt>
<interrupt>
<name>PWM1_INTR</name>
<description>interrupt of PWM1, level, Reserved</description>
<value>40</value>
</interrupt>
<interrupt>
<name>PWM2_INTR</name>
<description>interrupt of PWM2, level</description>
<value>41</value>
</interrupt>
<interrupt>
<name>PWM3_INTR</name>
<description>interrupt of PWM3, level</description>
<value>42</value>
</interrupt>
<registers>
<register>
<name>SCL_LOW_PERIOD</name>
<description>I2C_SCL_LOW_PERIOD</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERIOD</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTR</name>
<description>I2C_CTR</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_LSB_FIRST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_LSB_FIRST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_START</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MS_MODE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAMPLE_SCL_LEVEL</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCL_FORCE_OUT</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDA_FORCE_OUT</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SR</name>
<description>I2C_SR</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCL_STATE_LAST</name>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SCL_MAIN_STATE_LAST</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TXFIFO_CNT</name>
<bitOffset>18</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>RXFIFO_CNT</name>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>BYTE_TRANS</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_ADDRESSED</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUS_BUSY</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARB_LOST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_OUT</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_RW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK_REC</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TO</name>
<description>I2C_TO</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME_OUT_REG</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLAVE_ADDR</name>
<description>I2C_SLAVE_ADDR</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADDR_10BIT_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXFIFO_ST</name>
<description>I2C_RXFIFO_ST</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXFIFO_END_ADDR</name>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>TXFIFO_START_ADDR</name>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RXFIFO_END_ADDR</name>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RXFIFO_START_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>FIFO_CONF</name>
<description>I2C_FIFO_CONF</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NONFIFO_TX_THRES</name>
<bitOffset>20</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>NONFIFO_RX_THRES</name>
<bitOffset>14</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TX_FIFO_RST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FIFO_RST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFO_ADDR_CFG_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>NONFIFO_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_THRHD</name>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_THRHD</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATA</name>
<description>I2C_DATA</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FIFO_RDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>I2C_INT_RAW</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_SEND_EMPTY_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_REC_FULL_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK_ERR_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_START_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_OUT_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_COMPLETE_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASTER_TRAN_COMP_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBITRATION_LOST_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_TRAN_COMP_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_DETECT_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_OVF_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>I2C_INT_CLR</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_SEND_EMPTY_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_REC_FULL_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK_ERR_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_START_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_OUT_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_COMPLETE_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASTER_TRAN_COMP_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBITRATION_LOST_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_TRAN_COMP_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_DETECT_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_OVF_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>I2C_INT_ENA</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_SEND_EMPTY_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_REC_FULL_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK_ERR_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_START_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_OUT_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_COMPLETE_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASTER_TRAN_COMP_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBITRATION_LOST_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_TRAN_COMP_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_DETECT_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_OVF_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_STATUS</name>
<description>I2C_INT_STATUS</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_SEND_EMPTY_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_REC_FULL_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK_ERR_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_START_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_OUT_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_COMPLETE_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASTER_TRAN_COMP_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBITRATION_LOST_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_TRAN_COMP_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>END_DETECT_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_OVF_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDA_HOLD</name>
<description>I2C_SDA_HOLD</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDA_SAMPLE</name>
<description>I2C_SDA_SAMPLE</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_HIGH_PERIOD</name>
<description>I2C_SCL_HIGH_PERIOD</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERIOD</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_START_HOLD</name>
<description>I2C_SCL_START_HOLD</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_RSTART_SETUP</name>
<description>I2C_SCL_RSTART_SETUP</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_STOP_HOLD</name>
<description>I2C_SCL_STOP_HOLD</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_STOP_SETUP</name>
<description>I2C_SCL_STOP_SETUP</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_FILTER_CFG</name>
<description>I2C_SCL_FILTER_CFG</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCL_FILTER_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCL_FILTER_THRES</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDA_FILTER_CFG</name>
<description>I2C_SDA_FILTER_CFG</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDA_FILTER_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDA_FILTER_THRES</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD0</name>
<description>I2C_COMD0</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND0_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND0</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD1</name>
<description>I2C_COMD1</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND1_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND1</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD2</name>
<description>I2C_COMD2</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND2_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND2</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD3</name>
<description>I2C_COMD3</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND3_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND3</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD4</name>
<description>I2C_COMD4</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND4_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND4</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD5</name>
<description>I2C_COMD5</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND5_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND5</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD6</name>
<description>I2C_COMD6</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND6_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND6</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD7</name>
<description>I2C_COMD7</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND7_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND7</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD8</name>
<description>I2C_COMD8</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND8_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND8</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD9</name>
<description>I2C_COMD9</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND9_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND9</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD10</name>
<description>I2C_COMD10</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND10_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND10</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD11</name>
<description>I2C_COMD11</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND11_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND11</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD12</name>
<description>I2C_COMD12</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND12_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND12</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD13</name>
<description>I2C_COMD13</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND13_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND13</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD14</name>
<description>I2C_COMD14</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND14_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND14</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>COMD15</name>
<description>I2C_COMD15</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>COMMAND15_DONE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>COMMAND15</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>I2C_DATE</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EFUSE</name>
<baseAddress>0x3ff5a000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000920</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>EFUSE_INTR</name>
<description>interrupt of efuse, level, not likely to use</description>
<value>44</value>
</interrupt>
<registers>
<register>
<name>BLK0_RDATA0</name>
<description>EFUSE_BLK0_RDATA0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RD_FLASH_CRYPT_CNT</name>
<bitOffset>20</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>RD_EFUSE_RD_DIS</name>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_RDATA1</name>
<description>EFUSE_BLK0_RDATA1</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RD_WIFI_MAC_CRC_LOW</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_RDATA2</name>
<description>EFUSE_BLK0_RDATA2</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RD_WIFI_MAC_CRC_HIGH</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_RDATA3</name>
<description>EFUSE_BLK0_RDATA3</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RD_CHIP_VER_REV1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_CHIP_CPU_FREQ_RATED</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_CHIP_CPU_FREQ_LOW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_CHIP_VER_PKG</name>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RD_SPI_PAD_CONFIG_HD</name>
<bitOffset>4</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RD_CHIP_VER_DIS_CACHE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_CHIP_VER_32PAD</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_CHIP_VER_DIS_BT</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_CHIP_VER_DIS_APP_CPU</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_RDATA4</name>
<description>EFUSE_BLK0_RDATA4</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RD_SDIO_FORCE</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_SDIO_TIEH</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_XPD_SDIO_REG</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_ADC_VREF</name>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RD_SDIO_DREFL</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RD_SDIO_DREFM</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RD_SDIO_DREFH</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RD_CK8M_FREQ</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_RDATA5</name>
<description>EFUSE_BLK0_RDATA5</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RD_FLASH_CRYPT_CONFIG</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RD_INST_CONFIG</name>
<bitOffset>20</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RD_SPI_PAD_CONFIG_D</name>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RD_SPI_PAD_CONFIG_Q</name>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>RD_SPI_PAD_CONFIG_CLK</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_RDATA6</name>
<description>EFUSE_BLK0_RDATA6</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RD_KEY_STATUS</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_DISABLE_DL_CACHE</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_DISABLE_DL_DECRYPT</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_DISABLE_DL_ENCRYPT</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_DISABLE_JTAG</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_ABS_DONE_1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_ABS_DONE_0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_DISABLE_SDIO_HOST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_CONSOLE_DEBUG_DISABLE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RD_CODING_SCHEME</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_WDATA0</name>
<description>EFUSE_BLK0_WDATA0</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLASH_CRYPT_CNT</name>
<bitOffset>20</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>RD_DIS</name>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>WR_DIS</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_WDATA1</name>
<description>EFUSE_BLK0_WDATA1</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WIFI_MAC_CRC_LOW</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_WDATA2</name>
<description>EFUSE_BLK0_WDATA2</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WIFI_MAC_CRC_HIGH</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_WDATA3</name>
<description>EFUSE_BLK0_WDATA3</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHIP_VER_REV1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHIP_CPU_FREQ_RATED</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHIP_CPU_FREQ_LOW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHIP_VER_PKG</name>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SPI_PAD_CONFIG_HD</name>
<bitOffset>4</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CHIP_VER_DIS_CACHE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHIP_VER_32PAD</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHIP_VER_DIS_BT</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHIP_VER_DIS_APP_CPU</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_WDATA4</name>
<description>EFUSE_BLK0_WDATA4</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIO_FORCE</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_TIEH</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD_SDIO_REG</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC_VREF</name>
<bitOffset>8</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SDIO_DREFL</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SDIO_DREFM</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SDIO_DREFH</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CK8M_FREQ</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_WDATA5</name>
<description>EFUSE_BLK0_WDATA5</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FLASH_CRYPT_CONFIG</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>INST_CONFIG</name>
<bitOffset>20</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SPI_PAD_CONFIG_D</name>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPI_PAD_CONFIG_Q</name>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SPI_PAD_CONFIG_CLK</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK0_WDATA6</name>
<description>EFUSE_BLK0_WDATA6</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>KEY_STATUS</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISABLE_DL_CACHE</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISABLE_DL_DECRYPT</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISABLE_DL_ENCRYPT</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISABLE_JTAG</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABS_DONE_1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ABS_DONE_0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DISABLE_SDIO_HOST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CONSOLE_DEBUG_DISABLE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CODING_SCHEME</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_RDATA0</name>
<description>EFUSE_BLK1_RDATA0</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DOUT0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_RDATA1</name>
<description>EFUSE_BLK1_RDATA1</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DOUT1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_RDATA2</name>
<description>EFUSE_BLK1_RDATA2</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DOUT2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_RDATA3</name>
<description>EFUSE_BLK1_RDATA3</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DOUT3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_RDATA4</name>
<description>EFUSE_BLK1_RDATA4</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DOUT4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_RDATA5</name>
<description>EFUSE_BLK1_RDATA5</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DOUT5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_RDATA6</name>
<description>EFUSE_BLK1_RDATA6</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DOUT6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_RDATA7</name>
<description>EFUSE_BLK1_RDATA7</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DOUT7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_RDATA0</name>
<description>EFUSE_BLK2_RDATA0</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DOUT0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_RDATA1</name>
<description>EFUSE_BLK2_RDATA1</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DOUT1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_RDATA2</name>
<description>EFUSE_BLK2_RDATA2</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DOUT2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_RDATA3</name>
<description>EFUSE_BLK2_RDATA3</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DOUT3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_RDATA4</name>
<description>EFUSE_BLK2_RDATA4</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DOUT4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_RDATA5</name>
<description>EFUSE_BLK2_RDATA5</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DOUT5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_RDATA6</name>
<description>EFUSE_BLK2_RDATA6</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DOUT6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_RDATA7</name>
<description>EFUSE_BLK2_RDATA7</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DOUT7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_RDATA0</name>
<description>EFUSE_BLK3_RDATA0</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DOUT0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_RDATA1</name>
<description>EFUSE_BLK3_RDATA1</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DOUT1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_RDATA2</name>
<description>EFUSE_BLK3_RDATA2</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DOUT2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_RDATA3</name>
<description>EFUSE_BLK3_RDATA3</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DOUT3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>RD_ADC2_TP_HIGH</name>
<bitOffset>23</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RD_ADC2_TP_LOW</name>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>RD_ADC1_TP_HIGH</name>
<bitOffset>7</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>RD_ADC1_TP_LOW</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_RDATA4</name>
<description>EFUSE_BLK3_RDATA4</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DOUT4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_RDATA5</name>
<description>EFUSE_BLK3_RDATA5</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DOUT5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_RDATA6</name>
<description>EFUSE_BLK3_RDATA6</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DOUT6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_RDATA7</name>
<description>EFUSE_BLK3_RDATA7</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DOUT7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_WDATA0</name>
<description>EFUSE_BLK1_WDATA0</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DIN0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_WDATA1</name>
<description>EFUSE_BLK1_WDATA1</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DIN1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_WDATA2</name>
<description>EFUSE_BLK1_WDATA2</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DIN2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_WDATA3</name>
<description>EFUSE_BLK1_WDATA3</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DIN3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_WDATA4</name>
<description>EFUSE_BLK1_WDATA4</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DIN4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_WDATA5</name>
<description>EFUSE_BLK1_WDATA5</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DIN5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_WDATA6</name>
<description>EFUSE_BLK1_WDATA6</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DIN6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK1_WDATA7</name>
<description>EFUSE_BLK1_WDATA7</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK1_DIN7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_WDATA0</name>
<description>EFUSE_BLK2_WDATA0</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DIN0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_WDATA1</name>
<description>EFUSE_BLK2_WDATA1</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DIN1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_WDATA2</name>
<description>EFUSE_BLK2_WDATA2</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DIN2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_WDATA3</name>
<description>EFUSE_BLK2_WDATA3</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DIN3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_WDATA4</name>
<description>EFUSE_BLK2_WDATA4</description>
<addressOffset>0xc8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DIN4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_WDATA5</name>
<description>EFUSE_BLK2_WDATA5</description>
<addressOffset>0xcc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DIN5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_WDATA6</name>
<description>EFUSE_BLK2_WDATA6</description>
<addressOffset>0xd0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DIN6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK2_WDATA7</name>
<description>EFUSE_BLK2_WDATA7</description>
<addressOffset>0xd4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK2_DIN7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_WDATA0</name>
<description>EFUSE_BLK3_WDATA0</description>
<addressOffset>0xd8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DIN0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_WDATA1</name>
<description>EFUSE_BLK3_WDATA1</description>
<addressOffset>0xdc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DIN1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_WDATA2</name>
<description>EFUSE_BLK3_WDATA2</description>
<addressOffset>0xe0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DIN2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_WDATA3</name>
<description>EFUSE_BLK3_WDATA3</description>
<addressOffset>0xe4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DIN3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>ADC2_TP_HIGH</name>
<bitOffset>23</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>ADC2_TP_LOW</name>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ADC1_TP_HIGH</name>
<bitOffset>7</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>ADC1_TP_LOW</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_WDATA4</name>
<description>EFUSE_BLK3_WDATA4</description>
<addressOffset>0xe8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DIN4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_WDATA5</name>
<description>EFUSE_BLK3_WDATA5</description>
<addressOffset>0xec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DIN5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_WDATA6</name>
<description>EFUSE_BLK3_WDATA6</description>
<addressOffset>0xf0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DIN6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BLK3_WDATA7</name>
<description>EFUSE_BLK3_WDATA7</description>
<addressOffset>0xf4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BLK3_DIN7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK</name>
<description>EFUSE_CLK</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EN</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_SEL1</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CLK_SEL0</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF</name>
<description>EFUSE_CONF</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FORCE_NO_WR_RD_DIS</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP_CODE</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>EFUSE_STATUS</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DEBUG</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMD</name>
<description>EFUSE_CMD</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PGM_CMD</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>READ_CMD</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>EFUSE_INT_RAW</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PGM_DONE_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>READ_DONE_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST</name>
<description>EFUSE_INT_ST</description>
<addressOffset>0x10c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PGM_DONE_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>READ_DONE_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>EFUSE_INT_ENA</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PGM_DONE_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>READ_DONE_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>EFUSE_INT_CLR</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PGM_DONE_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>READ_DONE_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DAC_CONF</name>
<description>EFUSE_DAC_CONF</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAC_CLK_PAD_SEL</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC_CLK_DIV</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEC_STATUS</name>
<description>EFUSE_DEC_STATUS</description>
<addressOffset>0x11c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DEC_WARNINGS</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>EFUSE_DATE</description>
<addressOffset>0x1fc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTCMEM1</name>
<baseAddress>0x3ff62000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral derivedFrom="I2C">
<name>I2C0</name>
<baseAddress>0x3ff53000</baseAddress>
</peripheral>
<peripheral>
<name>RSA</name>
<baseAddress>0x3ff02000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RSA_INTR</name>
<description>interrupt of RSA accelerator, level</description>
<value>51</value>
</interrupt>
<registers />
</peripheral>
<peripheral>
<name>PCNT</name>
<baseAddress>0x3ff57000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x000005c0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>PCNT_INTR</name>
<description>interrupt of pluse count, level</description>
<value>48</value>
</interrupt>
<registers>
<register>
<name>U0_CONF0</name>
<description>PCNT_U0_CONF0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH1_LCTRL_MODE_U0</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_HCTRL_MODE_U0</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_POS_MODE_U0</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_NEG_MODE_U0</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_LCTRL_MODE_U0</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_HCTRL_MODE_U0</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_POS_MODE_U0</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_NEG_MODE_U0</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>THR_THRES1_EN_U0</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_THRES0_EN_U0</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_L_LIM_EN_U0</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_H_LIM_EN_U0</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_ZERO_EN_U0</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_EN_U0</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_THRES_U0</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>U0_CONF1</name>
<description>PCNT_U0_CONF1</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THRES1_U0</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_THRES0_U0</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U0_CONF2</name>
<description>PCNT_U0_CONF2</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L_LIM_U0</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H_LIM_U0</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U1_CONF0</name>
<description>PCNT_U1_CONF0</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH1_LCTRL_MODE_U1</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_HCTRL_MODE_U1</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_POS_MODE_U1</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_NEG_MODE_U1</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_LCTRL_MODE_U1</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_HCTRL_MODE_U1</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_POS_MODE_U1</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_NEG_MODE_U1</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>THR_THRES1_EN_U1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_THRES0_EN_U1</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_L_LIM_EN_U1</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_H_LIM_EN_U1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_ZERO_EN_U1</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_EN_U1</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_THRES_U1</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>U1_CONF1</name>
<description>PCNT_U1_CONF1</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THRES1_U1</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_THRES0_U1</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U1_CONF2</name>
<description>PCNT_U1_CONF2</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L_LIM_U1</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H_LIM_U1</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U2_CONF0</name>
<description>PCNT_U2_CONF0</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH1_LCTRL_MODE_U2</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_HCTRL_MODE_U2</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_POS_MODE_U2</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_NEG_MODE_U2</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_LCTRL_MODE_U2</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_HCTRL_MODE_U2</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_POS_MODE_U2</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_NEG_MODE_U2</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>THR_THRES1_EN_U2</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_THRES0_EN_U2</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_L_LIM_EN_U2</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_H_LIM_EN_U2</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_ZERO_EN_U2</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_EN_U2</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_THRES_U2</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>U2_CONF1</name>
<description>PCNT_U2_CONF1</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THRES1_U2</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_THRES0_U2</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U2_CONF2</name>
<description>PCNT_U2_CONF2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L_LIM_U2</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H_LIM_U2</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U3_CONF0</name>
<description>PCNT_U3_CONF0</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH1_LCTRL_MODE_U3</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_HCTRL_MODE_U3</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_POS_MODE_U3</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_NEG_MODE_U3</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_LCTRL_MODE_U3</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_HCTRL_MODE_U3</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_POS_MODE_U3</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_NEG_MODE_U3</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>THR_THRES1_EN_U3</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_THRES0_EN_U3</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_L_LIM_EN_U3</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_H_LIM_EN_U3</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_ZERO_EN_U3</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_EN_U3</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_THRES_U3</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>U3_CONF1</name>
<description>PCNT_U3_CONF1</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THRES1_U3</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_THRES0_U3</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U3_CONF2</name>
<description>PCNT_U3_CONF2</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L_LIM_U3</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H_LIM_U3</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U4_CONF0</name>
<description>PCNT_U4_CONF0</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH1_LCTRL_MODE_U4</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_HCTRL_MODE_U4</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_POS_MODE_U4</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_NEG_MODE_U4</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_LCTRL_MODE_U4</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_HCTRL_MODE_U4</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_POS_MODE_U4</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_NEG_MODE_U4</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>THR_THRES1_EN_U4</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_THRES0_EN_U4</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_L_LIM_EN_U4</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_H_LIM_EN_U4</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_ZERO_EN_U4</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_EN_U4</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_THRES_U4</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>U4_CONF1</name>
<description>PCNT_U4_CONF1</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THRES1_U4</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_THRES0_U4</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U4_CONF2</name>
<description>PCNT_U4_CONF2</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L_LIM_U4</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H_LIM_U4</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U5_CONF0</name>
<description>PCNT_U5_CONF0</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH1_LCTRL_MODE_U5</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_HCTRL_MODE_U5</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_POS_MODE_U5</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_NEG_MODE_U5</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_LCTRL_MODE_U5</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_HCTRL_MODE_U5</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_POS_MODE_U5</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_NEG_MODE_U5</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>THR_THRES1_EN_U5</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_THRES0_EN_U5</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_L_LIM_EN_U5</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_H_LIM_EN_U5</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_ZERO_EN_U5</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_EN_U5</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_THRES_U5</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>U5_CONF1</name>
<description>PCNT_U5_CONF1</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THRES1_U5</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_THRES0_U5</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U5_CONF2</name>
<description>PCNT_U5_CONF2</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L_LIM_U5</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H_LIM_U5</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U6_CONF0</name>
<description>PCNT_U6_CONF0</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH1_LCTRL_MODE_U6</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_HCTRL_MODE_U6</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_POS_MODE_U6</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_NEG_MODE_U6</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_LCTRL_MODE_U6</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_HCTRL_MODE_U6</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_POS_MODE_U6</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_NEG_MODE_U6</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>THR_THRES1_EN_U6</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_THRES0_EN_U6</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_L_LIM_EN_U6</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_H_LIM_EN_U6</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_ZERO_EN_U6</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_EN_U6</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_THRES_U6</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>U6_CONF1</name>
<description>PCNT_U6_CONF1</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THRES1_U6</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_THRES0_U6</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U6_CONF2</name>
<description>PCNT_U6_CONF2</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L_LIM_U6</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H_LIM_U6</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U7_CONF0</name>
<description>PCNT_U7_CONF0</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH1_LCTRL_MODE_U7</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_HCTRL_MODE_U7</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_POS_MODE_U7</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH1_NEG_MODE_U7</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_LCTRL_MODE_U7</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_HCTRL_MODE_U7</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_POS_MODE_U7</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CH0_NEG_MODE_U7</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>THR_THRES1_EN_U7</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_THRES0_EN_U7</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_L_LIM_EN_U7</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_H_LIM_EN_U7</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>THR_ZERO_EN_U7</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_EN_U7</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FILTER_THRES_U7</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>U7_CONF1</name>
<description>PCNT_U7_CONF1</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THRES1_U7</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_THRES0_U7</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U7_CONF2</name>
<description>PCNT_U7_CONF2</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_L_LIM_U7</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CNT_H_LIM_U7</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U0_CNT</name>
<description>PCNT_U0_CNT</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLUS_CNT_U0</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U1_CNT</name>
<description>PCNT_U1_CNT</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLUS_CNT_U1</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U2_CNT</name>
<description>PCNT_U2_CNT</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLUS_CNT_U2</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U3_CNT</name>
<description>PCNT_U3_CNT</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLUS_CNT_U3</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U4_CNT</name>
<description>PCNT_U4_CNT</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLUS_CNT_U4</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U5_CNT</name>
<description>PCNT_U5_CNT</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLUS_CNT_U5</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U6_CNT</name>
<description>PCNT_U6_CNT</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLUS_CNT_U6</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>U7_CNT</name>
<description>PCNT_U7_CNT</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLUS_CNT_U7</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>PCNT_INT_RAW</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THR_EVENT_U7_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U6_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U5_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U4_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U3_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U2_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U1_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U0_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST</name>
<description>PCNT_INT_ST</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THR_EVENT_U7_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U6_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U5_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U4_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U3_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U2_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U1_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U0_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>PCNT_INT_ENA</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THR_EVENT_U7_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U6_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U5_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U4_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U3_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U2_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>PCNT_INT_CLR</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNT_THR_EVENT_U7_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U6_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U5_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U4_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U3_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U2_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U1_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_THR_EVENT_U0_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>U0_STATUS</name>
<description>PCNT_U0_STATUS</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_STATUS_U0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>U1_STATUS</name>
<description>PCNT_U1_STATUS</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_STATUS_U1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>U2_STATUS</name>
<description>PCNT_U2_STATUS</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_STATUS_U2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>U3_STATUS</name>
<description>PCNT_U3_STATUS</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_STATUS_U3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>U4_STATUS</name>
<description>PCNT_U4_STATUS</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_STATUS_U4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>U5_STATUS</name>
<description>PCNT_U5_STATUS</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_STATUS_U5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>U6_STATUS</name>
<description>PCNT_U6_STATUS</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_STATUS_U6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>U7_STATUS</name>
<description>PCNT_U7_STATUS</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_STATUS_U7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>PCNT_CTRL</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EN</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_PAUSE_U7</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLUS_CNT_RST_U7</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_PAUSE_U6</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLUS_CNT_RST_U6</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_PAUSE_U5</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLUS_CNT_RST_U5</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_PAUSE_U4</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLUS_CNT_RST_U4</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_PAUSE_U3</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLUS_CNT_RST_U3</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_PAUSE_U2</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLUS_CNT_RST_U2</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_PAUSE_U1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLUS_CNT_RST_U1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CNT_PAUSE_U0</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLUS_CNT_RST_U0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>PCNT_DATE</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RMT</name>
<baseAddress>0x3ff56000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x000006c0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RMT_INTR</name>
<description>interrupt of remote controller, level</description>
<value>47</value>
</interrupt>
<registers>
<register>
<name>CH0CONF0</name>
<description>RMT_CH0CONF0</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_PD</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_OUT_LV_CH0</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_EN_CH0</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_SIZE_CH0</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IDLE_THRES_CH0</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DIV_CNT_CH0</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH0CONF1</name>
<description>RMT_CH0CONF1</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_OUT_EN_CH0</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_OUT_LV_CH0</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_ALWAYS_ON_CH0</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_CNT_RST_CH0</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FILTER_THRES_CH0</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RX_FILTER_EN_CH0</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CONTI_MODE_CH0</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_CH0</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_RST_CH0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_RD_RST_CH0</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_RST_CH0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_EN_CH0</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_CH0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH1CONF0</name>
<description>RMT_CH1CONF0</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_OUT_LV_CH1</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_EN_CH1</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_SIZE_CH1</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IDLE_THRES_CH1</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DIV_CNT_CH1</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH1CONF1</name>
<description>RMT_CH1CONF1</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_OUT_EN_CH1</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_OUT_LV_CH1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_ALWAYS_ON_CH1</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_CNT_RST_CH1</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FILTER_THRES_CH1</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RX_FILTER_EN_CH1</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CONTI_MODE_CH1</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_CH1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_RST_CH1</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_RD_RST_CH1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_RST_CH1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_EN_CH1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_CH1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH2CONF0</name>
<description>RMT_CH2CONF0</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_OUT_LV_CH2</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_EN_CH2</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_SIZE_CH2</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IDLE_THRES_CH2</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DIV_CNT_CH2</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH2CONF1</name>
<description>RMT_CH2CONF1</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_OUT_EN_CH2</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_OUT_LV_CH2</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_ALWAYS_ON_CH2</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_CNT_RST_CH2</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FILTER_THRES_CH2</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RX_FILTER_EN_CH2</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CONTI_MODE_CH2</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_CH2</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_RST_CH2</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_RD_RST_CH2</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_RST_CH2</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_EN_CH2</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_CH2</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH3CONF0</name>
<description>RMT_CH3CONF0</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_OUT_LV_CH3</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_EN_CH3</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_SIZE_CH3</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IDLE_THRES_CH3</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DIV_CNT_CH3</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH3CONF1</name>
<description>RMT_CH3CONF1</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_OUT_EN_CH3</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_OUT_LV_CH3</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_ALWAYS_ON_CH3</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_CNT_RST_CH3</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FILTER_THRES_CH3</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RX_FILTER_EN_CH3</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CONTI_MODE_CH3</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_CH3</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_RST_CH3</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_RD_RST_CH3</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_RST_CH3</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_EN_CH3</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_CH3</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH4CONF0</name>
<description>RMT_CH4CONF0</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_OUT_LV_CH4</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_EN_CH4</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_SIZE_CH4</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IDLE_THRES_CH4</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DIV_CNT_CH4</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH4CONF1</name>
<description>RMT_CH4CONF1</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_OUT_EN_CH4</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_OUT_LV_CH4</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_ALWAYS_ON_CH4</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_CNT_RST_CH4</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FILTER_THRES_CH4</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RX_FILTER_EN_CH4</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CONTI_MODE_CH4</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_CH4</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_RST_CH4</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_RD_RST_CH4</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_RST_CH4</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_EN_CH4</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_CH4</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH5CONF0</name>
<description>RMT_CH5CONF0</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_OUT_LV_CH5</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_EN_CH5</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_SIZE_CH5</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IDLE_THRES_CH5</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DIV_CNT_CH5</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH5CONF1</name>
<description>RMT_CH5CONF1</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_OUT_EN_CH5</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_OUT_LV_CH5</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_ALWAYS_ON_CH5</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_CNT_RST_CH5</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FILTER_THRES_CH5</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RX_FILTER_EN_CH5</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CONTI_MODE_CH5</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_CH5</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_RST_CH5</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_RD_RST_CH5</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_RST_CH5</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_EN_CH5</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_CH5</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH6CONF0</name>
<description>RMT_CH6CONF0</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_OUT_LV_CH6</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_EN_CH6</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_SIZE_CH6</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IDLE_THRES_CH6</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DIV_CNT_CH6</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH6CONF1</name>
<description>RMT_CH6CONF1</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_OUT_EN_CH6</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_OUT_LV_CH6</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_ALWAYS_ON_CH6</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_CNT_RST_CH6</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FILTER_THRES_CH6</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RX_FILTER_EN_CH6</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CONTI_MODE_CH6</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_CH6</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_RST_CH6</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_RD_RST_CH6</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_RST_CH6</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_EN_CH6</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_CH6</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH7CONF0</name>
<description>RMT_CH7CONF0</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_OUT_LV_CH7</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER_EN_CH7</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_SIZE_CH7</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>IDLE_THRES_CH7</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>DIV_CNT_CH7</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH7CONF1</name>
<description>RMT_CH7CONF1</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_OUT_EN_CH7</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_OUT_LV_CH7</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_ALWAYS_ON_CH7</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REF_CNT_RST_CH7</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FILTER_THRES_CH7</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RX_FILTER_EN_CH7</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CONTI_MODE_CH7</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_CH7</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_RST_CH7</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_RD_RST_CH7</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_RST_CH7</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_EN_CH7</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_CH7</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH0STATUS</name>
<description>RMT_CH0STATUS</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_CH0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>APB_MEM_RD_ERR_CH0</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_WR_ERR_CH0</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_EMPTY_CH0</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_FULL_CH0</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_ERR_CH0</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STATE_CH0</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MEM_RADDR_EX_CH0</name>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MEM_WADDR_EX_CH0</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH1STATUS</name>
<description>RMT_CH1STATUS</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_CH1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>APB_MEM_RD_ERR_CH1</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_WR_ERR_CH1</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_EMPTY_CH1</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_FULL_CH1</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_ERR_CH1</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STATE_CH1</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MEM_RADDR_EX_CH1</name>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MEM_WADDR_EX_CH1</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH2STATUS</name>
<description>RMT_CH2STATUS</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_CH2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>APB_MEM_RD_ERR_CH2</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_WR_ERR_CH2</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_EMPTY_CH2</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_FULL_CH2</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_ERR_CH2</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STATE_CH2</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MEM_RADDR_EX_CH2</name>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MEM_WADDR_EX_CH2</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH3STATUS</name>
<description>RMT_CH3STATUS</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_CH3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>APB_MEM_RD_ERR_CH3</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_WR_ERR_CH3</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_EMPTY_CH3</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_FULL_CH3</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_ERR_CH3</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STATE_CH3</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MEM_RADDR_EX_CH3</name>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MEM_WADDR_EX_CH3</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH4STATUS</name>
<description>RMT_CH4STATUS</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_CH4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>APB_MEM_RD_ERR_CH4</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_WR_ERR_CH4</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_EMPTY_CH4</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_FULL_CH4</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_ERR_CH4</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STATE_CH4</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MEM_RADDR_EX_CH4</name>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MEM_WADDR_EX_CH4</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH5STATUS</name>
<description>RMT_CH5STATUS</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_CH5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>APB_MEM_RD_ERR_CH5</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_WR_ERR_CH5</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_EMPTY_CH5</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_FULL_CH5</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_ERR_CH5</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STATE_CH5</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MEM_RADDR_EX_CH5</name>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MEM_WADDR_EX_CH5</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH6STATUS</name>
<description>RMT_CH6STATUS</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_CH6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>APB_MEM_RD_ERR_CH6</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_WR_ERR_CH6</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_EMPTY_CH6</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_FULL_CH6</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_ERR_CH6</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STATE_CH6</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MEM_RADDR_EX_CH6</name>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MEM_WADDR_EX_CH6</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH7STATUS</name>
<description>RMT_CH7STATUS</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_CH7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>APB_MEM_RD_ERR_CH7</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_MEM_WR_ERR_CH7</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_EMPTY_CH7</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_FULL_CH7</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_OWNER_ERR_CH7</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STATE_CH7</name>
<bitOffset>24</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MEM_RADDR_EX_CH7</name>
<bitOffset>12</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>MEM_WADDR_EX_CH7</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH0ADDR</name>
<description>RMT_CH0ADDR</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_MEM_ADDR_CH0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH1ADDR</name>
<description>RMT_CH1ADDR</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_MEM_ADDR_CH1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH2ADDR</name>
<description>RMT_CH2ADDR</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_MEM_ADDR_CH2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH3ADDR</name>
<description>RMT_CH3ADDR</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_MEM_ADDR_CH3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH4ADDR</name>
<description>RMT_CH4ADDR</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_MEM_ADDR_CH4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH5ADDR</name>
<description>RMT_CH5ADDR</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_MEM_ADDR_CH5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH6ADDR</name>
<description>RMT_CH6ADDR</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_MEM_ADDR_CH6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH7ADDR</name>
<description>RMT_CH7ADDR</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_MEM_ADDR_CH7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>RMT_INT_RAW</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH7_TX_THR_EVENT_INT_RAW</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_TX_THR_EVENT_INT_RAW</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_TX_THR_EVENT_INT_RAW</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_TX_THR_EVENT_INT_RAW</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_TX_THR_EVENT_INT_RAW</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_TX_THR_EVENT_INT_RAW</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_TX_THR_EVENT_INT_RAW</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_TX_THR_EVENT_INT_RAW</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_ERR_INT_RAW</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_RX_END_INT_RAW</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_TX_END_INT_RAW</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_ERR_INT_RAW</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_RX_END_INT_RAW</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_TX_END_INT_RAW</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_ERR_INT_RAW</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_RX_END_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_TX_END_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_ERR_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_RX_END_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_TX_END_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_ERR_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_RX_END_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_TX_END_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_ERR_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_RX_END_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_TX_END_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_ERR_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_RX_END_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_TX_END_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_ERR_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_RX_END_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_TX_END_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST</name>
<description>RMT_INT_ST</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH7_TX_THR_EVENT_INT_ST</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_TX_THR_EVENT_INT_ST</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_TX_THR_EVENT_INT_ST</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_TX_THR_EVENT_INT_ST</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_TX_THR_EVENT_INT_ST</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_TX_THR_EVENT_INT_ST</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_TX_THR_EVENT_INT_ST</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_TX_THR_EVENT_INT_ST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_ERR_INT_ST</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_RX_END_INT_ST</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_TX_END_INT_ST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_ERR_INT_ST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_RX_END_INT_ST</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_TX_END_INT_ST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_ERR_INT_ST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_RX_END_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_TX_END_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_ERR_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_RX_END_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_TX_END_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_ERR_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_RX_END_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_TX_END_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_ERR_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_RX_END_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_TX_END_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_ERR_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_RX_END_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_TX_END_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_ERR_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_RX_END_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_TX_END_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>RMT_INT_ENA</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH7_TX_THR_EVENT_INT_ENA</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_TX_THR_EVENT_INT_ENA</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_TX_THR_EVENT_INT_ENA</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_TX_THR_EVENT_INT_ENA</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_TX_THR_EVENT_INT_ENA</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_TX_THR_EVENT_INT_ENA</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_TX_THR_EVENT_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_TX_THR_EVENT_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_ERR_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_RX_END_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_TX_END_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_ERR_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_RX_END_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_TX_END_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_ERR_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_RX_END_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_TX_END_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_ERR_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_RX_END_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_TX_END_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_ERR_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_RX_END_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_TX_END_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_ERR_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_RX_END_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_TX_END_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_ERR_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_RX_END_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_TX_END_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_ERR_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_RX_END_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_TX_END_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>RMT_INT_CLR</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CH7_TX_THR_EVENT_INT_CLR</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_TX_THR_EVENT_INT_CLR</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_TX_THR_EVENT_INT_CLR</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_TX_THR_EVENT_INT_CLR</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_TX_THR_EVENT_INT_CLR</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_TX_THR_EVENT_INT_CLR</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_TX_THR_EVENT_INT_CLR</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_TX_THR_EVENT_INT_CLR</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_ERR_INT_CLR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_RX_END_INT_CLR</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH7_TX_END_INT_CLR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_ERR_INT_CLR</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_RX_END_INT_CLR</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH6_TX_END_INT_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_ERR_INT_CLR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_RX_END_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH5_TX_END_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_ERR_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_RX_END_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH4_TX_END_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_ERR_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_RX_END_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH3_TX_END_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_ERR_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_RX_END_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH2_TX_END_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_ERR_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_RX_END_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH1_TX_END_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_ERR_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_RX_END_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CH0_TX_END_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH0CARRIER_DUTY</name>
<description>RMT_CH0CARRIER_DUTY</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_HIGH_CH0</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CARRIER_LOW_CH0</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH1CARRIER_DUTY</name>
<description>RMT_CH1CARRIER_DUTY</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_HIGH_CH1</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CARRIER_LOW_CH1</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH2CARRIER_DUTY</name>
<description>RMT_CH2CARRIER_DUTY</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_HIGH_CH2</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CARRIER_LOW_CH2</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH3CARRIER_DUTY</name>
<description>RMT_CH3CARRIER_DUTY</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_HIGH_CH3</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CARRIER_LOW_CH3</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH4CARRIER_DUTY</name>
<description>RMT_CH4CARRIER_DUTY</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_HIGH_CH4</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CARRIER_LOW_CH4</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH5CARRIER_DUTY</name>
<description>RMT_CH5CARRIER_DUTY</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_HIGH_CH5</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CARRIER_LOW_CH5</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH6CARRIER_DUTY</name>
<description>RMT_CH6CARRIER_DUTY</description>
<addressOffset>0xc8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_HIGH_CH6</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CARRIER_LOW_CH6</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH7CARRIER_DUTY</name>
<description>RMT_CH7CARRIER_DUTY</description>
<addressOffset>0xcc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER_HIGH_CH7</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CARRIER_LOW_CH7</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH0_TX_LIM</name>
<description>RMT_CH0_TX_LIM</description>
<addressOffset>0xd0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_LIM_CH0</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH1_TX_LIM</name>
<description>RMT_CH1_TX_LIM</description>
<addressOffset>0xd4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_LIM_CH1</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH2_TX_LIM</name>
<description>RMT_CH2_TX_LIM</description>
<addressOffset>0xd8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_LIM_CH2</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH3_TX_LIM</name>
<description>RMT_CH3_TX_LIM</description>
<addressOffset>0xdc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_LIM_CH3</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH4_TX_LIM</name>
<description>RMT_CH4_TX_LIM</description>
<addressOffset>0xe0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_LIM_CH4</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH5_TX_LIM</name>
<description>RMT_CH5_TX_LIM</description>
<addressOffset>0xe4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_LIM_CH5</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH6_TX_LIM</name>
<description>RMT_CH6_TX_LIM</description>
<addressOffset>0xe8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_LIM_CH6</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>CH7_TX_LIM</name>
<description>RMT_CH7_TX_LIM</description>
<addressOffset>0xec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_LIM_CH7</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_CONF</name>
<description>RMT_APB_CONF</description>
<addressOffset>0xf0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM_TX_WRAP_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB_FIFO_MASK</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>RMT_DATE</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>EMAC</name>
<baseAddress>0x3ff69000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>RTCMEM2</name>
<baseAddress>0x3ff63000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>GPIO</name>
<baseAddress>0x3ff44000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00002e60</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>GPIO_INTR</name>
<description>interrupt of GPIO, level</description>
<value>22</value>
</interrupt>
<interrupt>
<name>GPIO_NMI</name>
<description>interrupt of GPIO, NMI</description>
<value>23</value>
</interrupt>
<registers>
<register>
<name>BT_SELECT</name>
<description>GPIO_BT_SELECT</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BT_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT</name>
<description>GPIO_OUT</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_W1TS</name>
<description>GPIO_OUT_W1TS</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_DATA_W1TS</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_W1TC</name>
<description>GPIO_OUT_W1TC</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_DATA_W1TC</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT1</name>
<description>GPIO_OUT1</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT1_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT1_W1TS</name>
<description>GPIO_OUT1_W1TS</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT1_DATA_W1TS</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT1_W1TC</name>
<description>GPIO_OUT1_W1TC</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT1_DATA_W1TC</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDIO_SELECT</name>
<description>GPIO_SDIO_SELECT</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIO_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE</name>
<description>GPIO_ENABLE</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE_W1TS</name>
<description>GPIO_ENABLE_W1TS</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE_DATA_W1TS</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE_W1TC</name>
<description>GPIO_ENABLE_W1TC</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE_DATA_W1TC</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE1</name>
<description>GPIO_ENABLE1</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE1_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE1_W1TS</name>
<description>GPIO_ENABLE1_W1TS</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE1_DATA_W1TS</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE1_W1TC</name>
<description>GPIO_ENABLE1_W1TC</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE1_DATA_W1TC</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>STRAP</name>
<description>GPIO_STRAP</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STRAPPING</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>IN</name>
<description>GPIO_IN</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IN1</name>
<description>GPIO_IN1</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN1_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>GPIO_STATUS</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_INT</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS_W1TS</name>
<description>GPIO_STATUS_W1TS</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_INT_W1TS</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS_W1TC</name>
<description>GPIO_STATUS_W1TC</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_INT_W1TC</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS1</name>
<description>GPIO_STATUS1</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS1_INT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS1_W1TS</name>
<description>GPIO_STATUS1_W1TS</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS1_INT_W1TS</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS1_W1TC</name>
<description>GPIO_STATUS1_W1TC</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS1_INT_W1TC</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACPU_INT</name>
<description>GPIO_ACPU_INT</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPCPU_INT</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACPU_NMI_INT</name>
<description>GPIO_ACPU_NMI_INT</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPCPU_NMI_INT</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCPU_INT</name>
<description>GPIO_PCPU_INT</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCPU_INT</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCPU_NMI_INT</name>
<description>GPIO_PCPU_NMI_INT</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCPU_NMI_INT</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUSDIO_INT</name>
<description>GPIO_CPUSDIO_INT</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIO_INT</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACPU_INT1</name>
<description>GPIO_ACPU_INT1</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPCPU_INT_H</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACPU_NMI_INT1</name>
<description>GPIO_ACPU_NMI_INT1</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPCPU_NMI_INT_H</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCPU_INT1</name>
<description>GPIO_PCPU_INT1</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCPU_INT_H</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PCPU_NMI_INT1</name>
<description>GPIO_PCPU_NMI_INT1</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCPU_NMI_INT_H</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPUSDIO_INT1</name>
<description>GPIO_CPUSDIO_INT1</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIO_INT_H</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<dim>40</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39</dimIndex>
<name>PIN%s</name>
<description>GPIO_PIN%s</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CONFIG</name>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>WAKEUP_ENABLE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INT_TYPE</name>
<bitOffset>7</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PAD_DRIVER</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>cali_conf</name>
<description>GPIO_cali_conf</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALI_START</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALI_RTC_MAX</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>cali_data</name>
<description>GPIO_cali_data</description>
<addressOffset>0x12c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CALI_RDY_SYNC2</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALI_RDY_REAL</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CALI_VALUE_SYNC2</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<dim>256</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255</dimIndex>
<name>FUNC%s_IN_SEL_CFG</name>
<description>GPIO_FUNC%s_IN_SEL_CFG</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEL</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_INV_SEL</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<dim>40</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39</dimIndex>
<name>FUNC%s_OUT_SEL_CFG</name>
<description>GPIO_FUNC%s_OUT_SEL_CFG</description>
<addressOffset>0x530</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OEN_INV_SEL</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OEN_SEL</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_INV_SEL</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FRC_TIMER</name>
<baseAddress>0x3ff47000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>UHCI</name>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000620</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>UHCI0_INTR</name>
<description>interrupt of UHCI0, level</description>
<value>12</value>
</interrupt>
<interrupt>
<name>UHCI1_INTR</name>
<description>interrupt of UHCI1, level</description>
<value>13</value>
</interrupt>
<registers>
<register>
<name>CONF0</name>
<description>UHCI_CONF0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UART_RX_BRK_EOF_EN</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_EN</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENCODE_CRC_EN</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LEN_EOF_EN</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART_IDLE_EOF_EN</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_REC_EN</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HEAD_EN</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEPER_EN</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_TRANS_EN</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DATA_BURST_EN</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INDSCR_BURST_EN</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTDSCR_BURST_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART2_CE</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART1_CE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART0_CE</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_NO_RESTART_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_AUTO_WRBACK</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_LOOP_TEST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_LOOP_TEST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBM_RST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBM_FIFO_RST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_RST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_RST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>UHCI_INT_RAW</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_INFIFO_FULL_WM_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_A_Q_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_S_Q_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_TOTAL_EOF_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_EOF_ERR_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_EMPTY_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DSCR_ERR_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_ERR_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_HUNG_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_HUNG_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_START_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST</name>
<description>UHCI_INT_ST</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_INFIFO_FULL_WM_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_A_Q_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_S_Q_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_TOTAL_EOF_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_EOF_ERR_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_EMPTY_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DSCR_ERR_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_ERR_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_HUNG_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_HUNG_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_START_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>UHCI_INT_ENA</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_INFIFO_FULL_WM_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_A_Q_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_S_Q_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_TOTAL_EOF_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_EOF_ERR_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_EMPTY_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DSCR_ERR_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_ERR_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_HUNG_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_HUNG_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_START_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>UHCI_INT_CLR</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_INFIFO_FULL_WM_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_A_Q_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_S_Q_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_TOTAL_EOF_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_EOF_ERR_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_EMPTY_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DSCR_ERR_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_ERR_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_HUNG_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_HUNG_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_START_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_STATUS</name>
<description>UHCI_DMA_OUT_STATUS</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_EMPTY</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_FULL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_PUSH</name>
<description>UHCI_DMA_OUT_PUSH</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTFIFO_PUSH</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTFIFO_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_STATUS</name>
<description>UHCI_DMA_IN_STATUS</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_ERR_CAUSE</name>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>IN_EMPTY</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_FULL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_POP</name>
<description>UHCI_DMA_IN_POP</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INFIFO_POP</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INFIFO_RDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_LINK</name>
<description>UHCI_DMA_OUT_LINK</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_PARK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_LINK</name>
<description>UHCI_DMA_IN_LINK</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_PARK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_AUTO_RET</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF1</name>
<description>UHCI_CONF1</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMA_INFIFO_FULL_THRS</name>
<bitOffset>9</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>SW_START</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAIT_SW_START</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHECK_OWNER</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_ACK_NUM_RE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_CHECK_SUM_RE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAVE_HEAD</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CRC_DISABLE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHECK_SEQ_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHECK_SUM_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATE0</name>
<description>UHCI_STATE0</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATE0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATE1</name>
<description>UHCI_STATE1</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATE1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_EOF_DES_ADDR</name>
<description>UHCI_DMA_OUT_EOF_DES_ADDR</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_SUC_EOF_DES_ADDR</name>
<description>UHCI_DMA_IN_SUC_EOF_DES_ADDR</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN_SUC_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_ERR_EOF_DES_ADDR</name>
<description>UHCI_DMA_IN_ERR_EOF_DES_ADDR</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN_ERR_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_EOF_BFR_DES_ADDR</name>
<description>UHCI_DMA_OUT_EOF_BFR_DES_ADDR</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_EOF_BFR_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB_TEST</name>
<description>UHCI_AHB_TEST</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHB_TESTADDR</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AHB_TESTMODE</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_DSCR</name>
<description>UHCI_DMA_IN_DSCR</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_DSCR_BF0</name>
<description>UHCI_DMA_IN_DSCR_BF0</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_IN_DSCR_BF1</name>
<description>UHCI_DMA_IN_DSCR_BF1</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_DSCR</name>
<description>UHCI_DMA_OUT_DSCR</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_DSCR_BF0</name>
<description>UHCI_DMA_OUT_DSCR_BF0</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMA_OUT_DSCR_BF1</name>
<description>UHCI_DMA_OUT_DSCR_BF1</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESCAPE_CONF</name>
<description>UHCI_ESCAPE_CONF</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_13_ESC_EN</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_11_ESC_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_DB_ESC_EN</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_C0_ESC_EN</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_13_ESC_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_11_ESC_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_DB_ESC_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_C0_ESC_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HUNG_CONF</name>
<description>UHCI_HUNG_CONF</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXFIFO_TIMEOUT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_TIMEOUT_SHIFT</name>
<bitOffset>20</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RXFIFO_TIMEOUT</name>
<bitOffset>12</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TXFIFO_TIMEOUT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_TIMEOUT_SHIFT</name>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TXFIFO_TIMEOUT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RX_HEAD</name>
<description>UHCI_RX_HEAD</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_HEAD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>QUICK_SENT</name>
<description>UHCI_QUICK_SENT</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ALWAYS_SEND_EN</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ALWAYS_SEND_NUM</name>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SINGLE_SEND_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SINGLE_SEND_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q0_WORD0</name>
<description>UHCI_Q0_WORD0</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q0_WORD0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q0_WORD1</name>
<description>UHCI_Q0_WORD1</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q0_WORD1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q1_WORD0</name>
<description>UHCI_Q1_WORD0</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q1_WORD0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q1_WORD1</name>
<description>UHCI_Q1_WORD1</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q1_WORD1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q2_WORD0</name>
<description>UHCI_Q2_WORD0</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q2_WORD0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q2_WORD1</name>
<description>UHCI_Q2_WORD1</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q2_WORD1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q3_WORD0</name>
<description>UHCI_Q3_WORD0</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q3_WORD0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q3_WORD1</name>
<description>UHCI_Q3_WORD1</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q3_WORD1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q4_WORD0</name>
<description>UHCI_Q4_WORD0</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q4_WORD0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q4_WORD1</name>
<description>UHCI_Q4_WORD1</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q4_WORD1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q5_WORD0</name>
<description>UHCI_Q5_WORD0</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q5_WORD0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q5_WORD1</name>
<description>UHCI_Q5_WORD1</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q5_WORD1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q6_WORD0</name>
<description>UHCI_Q6_WORD0</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q6_WORD0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>Q6_WORD1</name>
<description>UHCI_Q6_WORD1</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_Q6_WORD1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESC_CONF0</name>
<description>UHCI_ESC_CONF0</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEPER_ESC_CHAR1</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SEPER_ESC_CHAR0</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SEPER_CHAR</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESC_CONF1</name>
<description>UHCI_ESC_CONF1</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ESC_SEQ0_CHAR1</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ESC_SEQ0_CHAR0</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ESC_SEQ0</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESC_CONF2</name>
<description>UHCI_ESC_CONF2</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ESC_SEQ1_CHAR1</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ESC_SEQ1_CHAR0</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ESC_SEQ1</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESC_CONF3</name>
<description>UHCI_ESC_CONF3</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ESC_SEQ2_CHAR1</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ESC_SEQ2_CHAR0</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ESC_SEQ2</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PKT_THRES</name>
<description>UHCI_PKT_THRES</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PKT_THRS</name>
<bitOffset>0</bitOffset>
<bitWidth>13</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>UHCI_DATE</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SLCHOST</name>
<baseAddress>0x3ff55000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000800</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>HOST_SLCHOST_FUNC2_0</name>
<description>HOST_SLCHOST_FUNC2_0</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC_FUNC2_INT</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_FUNC2_1</name>
<description>HOST_SLCHOST_FUNC2_1</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC_FUNC2_INT_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_FUNC2_2</name>
<description>HOST_SLCHOST_FUNC2_2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC_FUNC1_MDSTAT</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_GPIO_STATUS0</name>
<description>HOST_SLCHOST_GPIO_STATUS0</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_INT0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_GPIO_STATUS1</name>
<description>HOST_SLCHOST_GPIO_STATUS1</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_INT1</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_GPIO_IN0</name>
<description>HOST_SLCHOST_GPIO_IN0</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_IN0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_GPIO_IN1</name>
<description>HOST_SLCHOST_GPIO_IN1</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_IN1</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_TOKEN_RDATA</name>
<description>HOST_SLC0HOST_TOKEN_RDATA</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC0_RX_PF_EOF</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HOST_HOSTSLC0_TOKEN1</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_PF_VALID</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0_HOST_PF</name>
<description>HOST_SLC0_HOST_PF</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC0_PF_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1_HOST_PF</name>
<description>HOST_SLC1_HOST_PF</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1_PF_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_INT_RAW</name>
<description>HOST_SLC0HOST_INT_RAW</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_INT_RAW</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_HOST_RD_RETRY_INT_RAW</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_NEW_PACKET_INT_RAW</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT3_INT_RAW</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT2_INT_RAW</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT1_INT_RAW</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT0_INT_RAW</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_PF_VALID_INT_RAW</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TX_OVF_INT_RAW</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_UDF_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TX_START_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_START_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_EOF_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_SOF_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_0TO1_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_0TO1_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_1TO0_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_1TO0_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT7_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT6_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT5_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT4_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT3_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT2_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT1_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT0_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_INT_RAW</name>
<description>HOST_SLC1HOST_INT_RAW</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1_BT_RX_NEW_PACKET_INT_RAW</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_HOST_RD_RETRY_INT_RAW</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_RAW</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT3_INT_RAW</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT2_INT_RAW</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT1_INT_RAW</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT0_INT_RAW</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_PF_VALID_INT_RAW</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TX_OVF_INT_RAW</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_UDF_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TX_START_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_START_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_EOF_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_SOF_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_0TO1_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_0TO1_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_1TO0_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_1TO0_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT7_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT6_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT5_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT4_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT3_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT2_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT1_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT0_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_INT_ST</name>
<description>HOST_SLC0HOST_INT_ST</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_INT_ST</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_HOST_RD_RETRY_INT_ST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_NEW_PACKET_INT_ST</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT3_INT_ST</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT2_INT_ST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT1_INT_ST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT0_INT_ST</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_PF_VALID_INT_ST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TX_OVF_INT_ST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_UDF_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TX_START_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_START_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_EOF_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_SOF_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_0TO1_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_0TO1_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_1TO0_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_1TO0_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT7_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT6_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT5_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT4_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT3_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT2_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT1_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT0_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_INT_ST</name>
<description>HOST_SLC1HOST_INT_ST</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1_BT_RX_NEW_PACKET_INT_ST</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_HOST_RD_RETRY_INT_ST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ST</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT3_INT_ST</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT2_INT_ST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT1_INT_ST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT0_INT_ST</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_PF_VALID_INT_ST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TX_OVF_INT_ST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_UDF_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TX_START_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_START_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_EOF_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_SOF_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_0TO1_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_0TO1_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_1TO0_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_1TO0_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT7_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT6_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT5_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT4_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT3_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT2_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT1_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT0_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_PKT_LEN</name>
<description>HOST_SLCHOST_PKT_LEN</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_HOSTSLC0_LEN_CHECK</name>
<bitOffset>20</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>HOST_HOSTSLC0_LEN</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_STATE_W0</name>
<description>HOST_SLCHOST_STATE_W0</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_STATE3</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_STATE2</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_STATE1</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_STATE0</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_STATE_W1</name>
<description>HOST_SLCHOST_STATE_W1</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_STATE7</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_STATE6</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_STATE5</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_STATE4</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W0</name>
<description>HOST_SLCHOST_CONF_W0</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF3</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF2</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF1</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF0</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W1</name>
<description>HOST_SLCHOST_CONF_W1</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF7</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF6</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF5</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF4</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W2</name>
<description>HOST_SLCHOST_CONF_W2</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF11</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF10</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF9</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF8</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W3</name>
<description>HOST_SLCHOST_CONF_W3</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF15</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF14</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF13</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF12</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W4</name>
<description>HOST_SLCHOST_CONF_W4</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF19</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF18</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF17</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF16</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W5</name>
<description>HOST_SLCHOST_CONF_W5</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF23</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF22</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF21</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF20</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W6</name>
<description>HOST_SLCHOST_CONF_W6</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF27</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF26</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF25</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF24</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W7</name>
<description>HOST_SLCHOST_CONF_W7</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF31</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF30</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF29</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF28</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_PKT_LEN0</name>
<description>HOST_SLCHOST_PKT_LEN0</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_HOSTSLC0_LEN0</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_PKT_LEN1</name>
<description>HOST_SLCHOST_PKT_LEN1</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_HOSTSLC0_LEN1</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_PKT_LEN2</name>
<description>HOST_SLCHOST_PKT_LEN2</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_HOSTSLC0_LEN2</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W8</name>
<description>HOST_SLCHOST_CONF_W8</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF35</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF34</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF33</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF32</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W9</name>
<description>HOST_SLCHOST_CONF_W9</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF39</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF38</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF37</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF36</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W10</name>
<description>HOST_SLCHOST_CONF_W10</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF43</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF42</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF41</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF40</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W11</name>
<description>HOST_SLCHOST_CONF_W11</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF47</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF46</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF45</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF44</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W12</name>
<description>HOST_SLCHOST_CONF_W12</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF51</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF50</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF49</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF48</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W13</name>
<description>HOST_SLCHOST_CONF_W13</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF55</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF54</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF53</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF52</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W14</name>
<description>HOST_SLCHOST_CONF_W14</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF59</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF58</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF57</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF56</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF_W15</name>
<description>HOST_SLCHOST_CONF_W15</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CONF63</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF62</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF61</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_CONF60</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CHECK_SUM0</name>
<description>HOST_SLCHOST_CHECK_SUM0</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CHECK_SUM0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CHECK_SUM1</name>
<description>HOST_SLCHOST_CHECK_SUM1</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_CHECK_SUM1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_TOKEN_RDATA</name>
<description>HOST_SLC1HOST_TOKEN_RDATA</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1_RX_PF_EOF</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>HOST_HOSTSLC1_TOKEN1</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_PF_VALID</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_TOKEN_WDATA</name>
<description>HOST_SLC0HOST_TOKEN_WDATA</description>
<addressOffset>0xc8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC0HOST_TOKEN1_WD</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TOKEN0_WD</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_TOKEN_WDATA</name>
<description>HOST_SLC1HOST_TOKEN_WDATA</description>
<addressOffset>0xcc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1HOST_TOKEN1_WD</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TOKEN0_WD</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_TOKEN_CON</name>
<description>HOST_SLCHOST_TOKEN_CON</description>
<addressOffset>0xd0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC0HOST_LEN_WR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TOKEN1_WR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TOKEN0_WR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TOKEN1_DEC</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TOKEN0_DEC</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TOKEN1_WR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TOKEN0_WR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TOKEN1_DEC</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TOKEN0_DEC</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_INT_CLR</name>
<description>HOST_SLC0HOST_INT_CLR</description>
<addressOffset>0xd4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_INT_CLR</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_HOST_RD_RETRY_INT_CLR</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_NEW_PACKET_INT_CLR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT3_INT_CLR</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT2_INT_CLR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT1_INT_CLR</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT0_INT_CLR</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_PF_VALID_INT_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TX_OVF_INT_CLR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_UDF_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TX_START_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_START_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_EOF_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_SOF_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_0TO1_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_0TO1_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_1TO0_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_1TO0_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT7_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT6_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT5_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT4_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT3_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT2_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT1_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT0_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_INT_CLR</name>
<description>HOST_SLC1HOST_INT_CLR</description>
<addressOffset>0xd8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1_BT_RX_NEW_PACKET_INT_CLR</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_HOST_RD_RETRY_INT_CLR</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_CLR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT3_INT_CLR</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT2_INT_CLR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT1_INT_CLR</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT0_INT_CLR</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_PF_VALID_INT_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TX_OVF_INT_CLR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_UDF_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TX_START_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_START_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_EOF_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_SOF_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_0TO1_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_0TO1_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_1TO0_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_1TO0_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT7_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT6_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT5_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT4_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT3_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT2_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT1_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT0_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_FUNC1_INT_ENA</name>
<description>HOST_SLC0HOST_FUNC1_INT_ENA</description>
<addressOffset>0xdc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_FN1_GPIO_SDIO_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_EXT_BIT3_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_EXT_BIT2_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_EXT_BIT1_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_EXT_BIT0_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_RX_PF_VALID_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TX_OVF_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_RX_UDF_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0HOST_TX_START_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0HOST_RX_START_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0HOST_RX_EOF_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0HOST_RX_SOF_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_FUNC1_INT_ENA</name>
<description>HOST_SLC1HOST_FUNC1_INT_ENA</description>
<addressOffset>0xe0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_HOST_RD_RETRY_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_EXT_BIT3_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_EXT_BIT2_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_EXT_BIT1_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_EXT_BIT0_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_RX_PF_VALID_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TX_OVF_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_RX_UDF_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1HOST_TX_START_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1HOST_RX_START_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1HOST_RX_EOF_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1HOST_RX_SOF_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOKEN1_0TO1_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOKEN0_0TO1_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOKEN1_1TO0_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOKEN0_1TO0_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOHOST_BIT7_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOHOST_BIT6_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOHOST_BIT5_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOHOST_BIT4_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOHOST_BIT3_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOHOST_BIT2_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOHOST_BIT1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN1_SLC1_TOHOST_BIT0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_FUNC2_INT_ENA</name>
<description>HOST_SLC0HOST_FUNC2_INT_ENA</description>
<addressOffset>0xe4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_FN2_GPIO_SDIO_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_HOST_RD_RETRY_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_EXT_BIT3_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_EXT_BIT2_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_EXT_BIT1_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_EXT_BIT0_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_RX_PF_VALID_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TX_OVF_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_RX_UDF_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0HOST_TX_START_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0HOST_RX_START_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0HOST_RX_EOF_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0HOST_RX_SOF_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOKEN1_0TO1_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOKEN0_0TO1_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOKEN1_1TO0_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOKEN0_1TO0_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOHOST_BIT7_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOHOST_BIT6_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOHOST_BIT5_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOHOST_BIT4_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOHOST_BIT3_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOHOST_BIT2_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOHOST_BIT1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC0_TOHOST_BIT0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_FUNC2_INT_ENA</name>
<description>HOST_SLC1HOST_FUNC2_INT_ENA</description>
<addressOffset>0xe8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_HOST_RD_RETRY_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_EXT_BIT3_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_EXT_BIT2_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_EXT_BIT1_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_EXT_BIT0_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_RX_PF_VALID_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TX_OVF_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_RX_UDF_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1HOST_TX_START_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1HOST_RX_START_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1HOST_RX_EOF_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1HOST_RX_SOF_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOKEN1_0TO1_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOKEN0_0TO1_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOKEN1_1TO0_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOKEN0_1TO0_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOHOST_BIT7_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOHOST_BIT6_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOHOST_BIT5_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOHOST_BIT4_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOHOST_BIT3_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOHOST_BIT2_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOHOST_BIT1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FN2_SLC1_TOHOST_BIT0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_INT_ENA</name>
<description>HOST_SLC0HOST_INT_ENA</description>
<addressOffset>0xec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_HOST_RD_RETRY_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT3_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT2_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT1_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT0_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_PF_VALID_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TX_OVF_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_UDF_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TX_START_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_START_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_EOF_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_SOF_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_0TO1_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_0TO1_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_1TO0_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_1TO0_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT7_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT6_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT5_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT4_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT3_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT2_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_INT_ENA</name>
<description>HOST_SLC1HOST_INT_ENA</description>
<addressOffset>0xf0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_HOST_RD_RETRY_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT3_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT2_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT1_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT0_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_PF_VALID_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TX_OVF_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_UDF_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TX_START_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_START_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_EOF_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_SOF_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_0TO1_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_0TO1_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_1TO0_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_1TO0_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT7_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT6_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT5_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT4_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT3_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT2_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_RX_INFOR</name>
<description>HOST_SLC0HOST_RX_INFOR</description>
<addressOffset>0xf4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC0HOST_RX_INFOR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_RX_INFOR</name>
<description>HOST_SLC1HOST_RX_INFOR</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1HOST_RX_INFOR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_LEN_WD</name>
<description>HOST_SLC0HOST_LEN_WD</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC0HOST_LEN_WD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC_APBWIN_WDATA</name>
<description>HOST_SLC_APBWIN_WDATA</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC_APBWIN_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC_APBWIN_CONF</name>
<description>HOST_SLC_APBWIN_CONF</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC_APBWIN_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC_APBWIN_WR</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC_APBWIN_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC_APBWIN_RDATA</name>
<description>HOST_SLC_APBWIN_RDATA</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC_APBWIN_RDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_RDCLR0</name>
<description>HOST_SLCHOST_RDCLR0</description>
<addressOffset>0x10c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_SLC0_BIT6_CLRADDR</name>
<bitOffset>9</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_SLC0_BIT7_CLRADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_RDCLR1</name>
<description>HOST_SLCHOST_RDCLR1</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_SLC1_BIT6_CLRADDR</name>
<bitOffset>9</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>HOST_SLCHOST_SLC1_BIT7_CLRADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC0HOST_INT_ENA1</name>
<description>HOST_SLC0HOST_INT_ENA1</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_GPIO_SDIO_INT_ENA1</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_HOST_RD_RETRY_INT_ENA1</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_NEW_PACKET_INT_ENA1</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT3_INT_ENA1</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT2_INT_ENA1</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT1_INT_ENA1</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_EXT_BIT0_INT_ENA1</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_PF_VALID_INT_ENA1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TX_OVF_INT_ENA1</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_RX_UDF_INT_ENA1</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_TX_START_INT_ENA1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_START_INT_ENA1</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_EOF_INT_ENA1</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0HOST_RX_SOF_INT_ENA1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_0TO1_INT_ENA1</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_0TO1_INT_ENA1</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN1_1TO0_INT_ENA1</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOKEN0_1TO0_INT_ENA1</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT7_INT_ENA1</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT6_INT_ENA1</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT5_INT_ENA1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT4_INT_ENA1</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT3_INT_ENA1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT2_INT_ENA1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT1_INT_ENA1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC0_TOHOST_BIT0_INT_ENA1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLC1HOST_INT_ENA1</name>
<description>HOST_SLC1HOST_INT_ENA1</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLC1_BT_RX_NEW_PACKET_INT_ENA1</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_HOST_RD_RETRY_INT_ENA1</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_WIFI_RX_NEW_PACKET_INT_ENA1</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT3_INT_ENA1</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT2_INT_ENA1</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT1_INT_ENA1</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_EXT_BIT0_INT_ENA1</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_PF_VALID_INT_ENA1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TX_OVF_INT_ENA1</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_RX_UDF_INT_ENA1</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_TX_START_INT_ENA1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_START_INT_ENA1</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_EOF_INT_ENA1</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1HOST_RX_SOF_INT_ENA1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_0TO1_INT_ENA1</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_0TO1_INT_ENA1</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN1_1TO0_INT_ENA1</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOKEN0_1TO0_INT_ENA1</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT7_INT_ENA1</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT6_INT_ENA1</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT5_INT_ENA1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT4_INT_ENA1</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT3_INT_ENA1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT2_INT_ENA1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT1_INT_ENA1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SLC1_TOHOST_BIT0_INT_ENA1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOSTDATE</name>
<description>HOST_SLCHOSTDATE</description>
<addressOffset>0x178</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOSTID</name>
<description>HOST_SLCHOSTID</description>
<addressOffset>0x17c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SLCHOST_ID</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_CONF</name>
<description>HOST_SLCHOST_CONF</description>
<addressOffset>0x1f0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_HSPEED_CON_EN</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SDIO_PAD_PULLUP</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_SDIO20_INT_DELAY</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_FRC_QUICK_IN</name>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>HOST_FRC_POS_SAMP</name>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>HOST_FRC_NEG_SAMP</name>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>HOST_FRC_SDIO20</name>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>HOST_FRC_SDIO11</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_SLCHOST_INF_ST</name>
<description>HOST_SLCHOST_INF_ST</description>
<addressOffset>0x1f4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOST_SDIO_QUICK_IN</name>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>HOST_SDIO_NEG_SAMP</name>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>HOST_SDIO20_MODE</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SLC</name>
<baseAddress>0x3ff58000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000a60</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>SLC0_INTR</name>
<description>interrupt of SLC0, level</description>
<value>10</value>
</interrupt>
<interrupt>
<name>SLC1_INTR</name>
<description>interrupt of SLC1, level</description>
<value>11</value>
</interrupt>
<registers>
<register>
<name>CONF0</name>
<description>SLC_CONF0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TOKEN_SEL</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN_AUTO_CLR</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TXDATA_BURST_EN</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TXDSCR_BURST_EN</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TXLINK_AUTO_RET</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RXLINK_AUTO_RET</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RXDATA_BURST_EN</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RXDSCR_BURST_EN</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_NO_RESTART_CLR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_AUTO_WRBACK</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_LOOP_TEST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_LOOP_TEST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_WR_RETRY_MASK_EN</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_WR_RETRY_MASK_EN</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_RST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_RST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN_SEL</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN_AUTO_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TXDATA_BURST_EN</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TXDSCR_BURST_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TXLINK_AUTO_RET</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RXLINK_AUTO_RET</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RXDATA_BURST_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RXDSCR_BURST_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_NO_RESTART_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_AUTO_WRBACK</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_LOOP_TEST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_LOOP_TEST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBM_RST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBM_FIFO_RST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_RST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_RST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0INT_RAW</name>
<description>SLC_0INT_RAW</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_QUICK_EOF_INT_RAW</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMD_DTC_INT_RAW</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_ERR_EOF_INT_RAW</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_WR_RETRY_DONE_INT_RAW</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_HOST_RD_ACK_INT_RAW</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_EMPTY_INT_RAW</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DSCR_ERR_INT_RAW</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_ERR_INT_RAW</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOHOST_INT_RAW</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_EOF_INT_RAW</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DONE_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_SUC_EOF_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DONE_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_1TO0_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_1TO0_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_OVF_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_UDF_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_START_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_START_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT7_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT6_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT5_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT4_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT3_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT2_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT1_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT0_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0INT_ST</name>
<description>SLC_0INT_ST</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_QUICK_EOF_INT_ST</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMD_DTC_INT_ST</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_ERR_EOF_INT_ST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_WR_RETRY_DONE_INT_ST</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_HOST_RD_ACK_INT_ST</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_EMPTY_INT_ST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DSCR_ERR_INT_ST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_ERR_INT_ST</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOHOST_INT_ST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_EOF_INT_ST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DONE_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_SUC_EOF_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DONE_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_1TO0_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_1TO0_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_OVF_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_UDF_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_START_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_START_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT7_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT6_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT5_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT4_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT3_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT2_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT1_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT0_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0INT_ENA</name>
<description>SLC_0INT_ENA</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_QUICK_EOF_INT_ENA</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMD_DTC_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_ERR_EOF_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_WR_RETRY_DONE_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_HOST_RD_ACK_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_EMPTY_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DSCR_ERR_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_ERR_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOHOST_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_EOF_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DONE_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_SUC_EOF_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DONE_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_1TO0_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_1TO0_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_OVF_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_UDF_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_START_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_START_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT7_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT6_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT5_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT4_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT3_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT2_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0INT_CLR</name>
<description>SLC_0INT_CLR</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_QUICK_EOF_INT_CLR</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMD_DTC_INT_CLR</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_ERR_EOF_INT_CLR</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_WR_RETRY_DONE_INT_CLR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_HOST_RD_ACK_INT_CLR</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_EMPTY_INT_CLR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DSCR_ERR_INT_CLR</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_ERR_INT_CLR</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOHOST_INT_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_EOF_INT_CLR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DONE_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_SUC_EOF_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DONE_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_1TO0_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_1TO0_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_OVF_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_UDF_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_START_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_START_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT7_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT6_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT5_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT4_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT3_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT2_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT1_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT0_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>1INT_RAW</name>
<description>SLC_1INT_RAW</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_ERR_EOF_INT_RAW</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_WR_RETRY_DONE_INT_RAW</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_HOST_RD_ACK_INT_RAW</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_EMPTY_INT_RAW</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DSCR_ERR_INT_RAW</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_ERR_INT_RAW</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOHOST_INT_RAW</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_EOF_INT_RAW</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DONE_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_SUC_EOF_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DONE_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_1TO0_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_1TO0_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_OVF_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_UDF_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_START_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_START_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT15_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT14_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT13_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT12_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT11_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT10_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT9_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT8_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>1INT_ST</name>
<description>SLC_1INT_ST</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_ERR_EOF_INT_ST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_WR_RETRY_DONE_INT_ST</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_HOST_RD_ACK_INT_ST</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_EMPTY_INT_ST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DSCR_ERR_INT_ST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_ERR_INT_ST</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOHOST_INT_ST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_EOF_INT_ST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DONE_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_SUC_EOF_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DONE_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_1TO0_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_1TO0_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_OVF_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_UDF_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_START_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_START_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT15_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT14_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT13_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT12_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT11_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT10_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT9_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT8_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>1INT_ENA</name>
<description>SLC_1INT_ENA</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_ERR_EOF_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_WR_RETRY_DONE_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_HOST_RD_ACK_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_EMPTY_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DSCR_ERR_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_ERR_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOHOST_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_EOF_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DONE_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_SUC_EOF_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DONE_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_1TO0_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_1TO0_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_OVF_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_UDF_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_START_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_START_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT15_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT14_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT13_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT12_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT11_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT10_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT9_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT8_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>1INT_CLR</name>
<description>SLC_1INT_CLR</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_ERR_EOF_INT_CLR</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_WR_RETRY_DONE_INT_CLR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_HOST_RD_ACK_INT_CLR</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_EMPTY_INT_CLR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DSCR_ERR_INT_CLR</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_ERR_INT_CLR</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOHOST_INT_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_EOF_INT_CLR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DONE_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_SUC_EOF_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DONE_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_1TO0_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_1TO0_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_OVF_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_UDF_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_START_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_START_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT15_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT14_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT13_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT12_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT11_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT10_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT9_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT8_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RX_STATUS</name>
<description>SLC_RX_STATUS</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_RX_EMPTY</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_FULL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_EMPTY</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_FULL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0RXFIFO_PUSH</name>
<description>SLC_0RXFIFO_PUSH</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RXFIFO_PUSH</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RXFIFO_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>1RXFIFO_PUSH</name>
<description>SLC_1RXFIFO_PUSH</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_RXFIFO_PUSH</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RXFIFO_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TX_STATUS</name>
<description>SLC_TX_STATUS</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_EMPTY</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_FULL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_EMPTY</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_FULL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0TXFIFO_POP</name>
<description>SLC_0TXFIFO_POP</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TXFIFO_POP</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TXFIFO_RDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>1TXFIFO_POP</name>
<description>SLC_1TXFIFO_POP</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TXFIFO_POP</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TXFIFO_RDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>0RX_LINK</name>
<description>SLC_0RX_LINK</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RXLINK_PARK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RXLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RXLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RXLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RXLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>0TX_LINK</name>
<description>SLC_0TX_LINK</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TXLINK_PARK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TXLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TXLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TXLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TXLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>1RX_LINK</name>
<description>SLC_1RX_LINK</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_RXLINK_PARK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RXLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RXLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RXLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_BT_PACKET</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RXLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>1TX_LINK</name>
<description>SLC_1TX_LINK</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TXLINK_PARK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TXLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TXLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TXLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TXLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>INTVEC_TOHOST</name>
<description>SLC_INTVEC_TOHOST</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TOHOST_INTVEC</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SLC0_TOHOST_INTVEC</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>0TOKEN0</name>
<description>SLC_0TOKEN0</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TOKEN0</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_INC_MORE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_INC</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_WR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>0TOKEN1</name>
<description>SLC_0TOKEN1</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TOKEN1</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_INC_MORE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_INC</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_WR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>1TOKEN0</name>
<description>SLC_1TOKEN0</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TOKEN0</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_INC_MORE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_INC</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_WR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>1TOKEN1</name>
<description>SLC_1TOKEN1</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TOKEN1</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_INC_MORE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_INC</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_WR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF1</name>
<description>SLC_CONF1</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EN</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_STITCH_EN</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_STITCH_EN</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HOST_INT_LEVEL_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_CHECK_SUM_EN</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_CHECK_SUM_EN</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_CHECK_OWNER</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_STITCH_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_STITCH_EN</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_LEN_AUTO_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMD_HOLD_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_CHECK_SUM_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_CHECK_SUM_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_CHECK_OWNER</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_STATE0</name>
<description>SLC_0_STATE0</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_STATE0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_STATE1</name>
<description>SLC_0_STATE1</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_STATE1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_STATE0</name>
<description>SLC_1_STATE0</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_STATE0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_STATE1</name>
<description>SLC_1_STATE1</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_STATE1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BRIDGE_CONF</name>
<description>SLC_BRIDGE_CONF</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_PUSH_IDLE_NUM</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>SLC1_TX_DUMMY_MODE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HDA_MAP_128K</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DUMMY_MODE</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFO_MAP_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>TXEOF_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TO_EOF_DES_ADDR</name>
<description>SLC_0_TO_EOF_DES_ADDR</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TO_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TX_EOF_DES_ADDR</name>
<description>SLC_0_TX_EOF_DES_ADDR</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TX_SUC_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TO_EOF_BFR_DES_ADDR</name>
<description>SLC_0_TO_EOF_BFR_DES_ADDR</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TO_EOF_BFR_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_TO_EOF_DES_ADDR</name>
<description>SLC_1_TO_EOF_DES_ADDR</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TO_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_TX_EOF_DES_ADDR</name>
<description>SLC_1_TX_EOF_DES_ADDR</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_SUC_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_TO_EOF_BFR_DES_ADDR</name>
<description>SLC_1_TO_EOF_BFR_DES_ADDR</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TO_EOF_BFR_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB_TEST</name>
<description>SLC_AHB_TEST</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHB_TESTADDR</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AHB_TESTMODE</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDIO_ST</name>
<description>SLC_SDIO_ST</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FUNC2_ACC_STATE</name>
<bitOffset>24</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>FUNC1_ACC_STATE</name>
<bitOffset>16</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>BUS_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SDIO_WAKEUP</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUNC_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CMD_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>RX_DSCR_CONF</name>
<description>SLC_RX_DSCR_CONF</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_RD_RETRY_THRESHOLD</name>
<bitOffset>21</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>SLC1_RX_FILL_EN</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_EOF_MODE</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_FILL_MODE</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_INFOR_NO_REPLACE</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN_NO_REPLACE</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RD_RETRY_THRESHOLD</name>
<bitOffset>5</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>SLC0_RX_FILL_EN</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_EOF_MODE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_FILL_MODE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_INFOR_NO_REPLACE</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN_NO_REPLACE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TXLINK_DSCR</name>
<description>SLC_0_TXLINK_DSCR</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TXLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TXLINK_DSCR_BF0</name>
<description>SLC_0_TXLINK_DSCR_BF0</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TXLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TXLINK_DSCR_BF1</name>
<description>SLC_0_TXLINK_DSCR_BF1</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TXLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_RXLINK_DSCR</name>
<description>SLC_0_RXLINK_DSCR</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RXLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_RXLINK_DSCR_BF0</name>
<description>SLC_0_RXLINK_DSCR_BF0</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RXLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_RXLINK_DSCR_BF1</name>
<description>SLC_0_RXLINK_DSCR_BF1</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RXLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_TXLINK_DSCR</name>
<description>SLC_1_TXLINK_DSCR</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TXLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_TXLINK_DSCR_BF0</name>
<description>SLC_1_TXLINK_DSCR_BF0</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TXLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_TXLINK_DSCR_BF1</name>
<description>SLC_1_TXLINK_DSCR_BF1</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TXLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_RXLINK_DSCR</name>
<description>SLC_1_RXLINK_DSCR</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_RXLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_RXLINK_DSCR_BF0</name>
<description>SLC_1_RXLINK_DSCR_BF0</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_RXLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_RXLINK_DSCR_BF1</name>
<description>SLC_1_RXLINK_DSCR_BF1</description>
<addressOffset>0xc8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_RXLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TX_ERREOF_DES_ADDR</name>
<description>SLC_0_TX_ERREOF_DES_ADDR</description>
<addressOffset>0xcc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TX_ERR_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>1_TX_ERREOF_DES_ADDR</name>
<description>SLC_1_TX_ERREOF_DES_ADDR</description>
<addressOffset>0xd0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_ERR_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOKEN_LAT</name>
<description>SLC_TOKEN_LAT</description>
<addressOffset>0xd4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TOKEN</name>
<bitOffset>16</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>SLC0_TOKEN</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>TX_DSCR_CONF</name>
<description>SLC_TX_DSCR_CONF</description>
<addressOffset>0xd8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WR_RETRY_THRESHOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMD_INFOR0</name>
<description>SLC_CMD_INFOR0</description>
<addressOffset>0xdc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMD_CONTENT0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CMD_INFOR1</name>
<description>SLC_CMD_INFOR1</description>
<addressOffset>0xe0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CMD_CONTENT1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_LEN_CONF</name>
<description>SLC_0_LEN_CONF</description>
<addressOffset>0xe4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TX_NEW_PKT_IND</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_NEW_PKT_IND</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_GET_USED_DSCR</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_GET_USED_DSCR</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_PACKET_LOAD_EN</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_PACKET_LOAD_EN</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_LEN_INC_MORE</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_LEN_INC</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_LEN_WR</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_LEN_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_LENGTH</name>
<description>SLC_0_LENGTH</description>
<addressOffset>0xe8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_LEN</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TXPKT_H_DSCR</name>
<description>SLC_0_TXPKT_H_DSCR</description>
<addressOffset>0xec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TX_PKT_H_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TXPKT_E_DSCR</name>
<description>SLC_0_TXPKT_E_DSCR</description>
<addressOffset>0xf0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TX_PKT_E_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_RXPKT_H_DSCR</name>
<description>SLC_0_RXPKT_H_DSCR</description>
<addressOffset>0xf4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_PKT_H_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_RXPKT_E_DSCR</name>
<description>SLC_0_RXPKT_E_DSCR</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_PKT_E_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TXPKTU_H_DSCR</name>
<description>SLC_0_TXPKTU_H_DSCR</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TX_PKT_START_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_TXPKTU_E_DSCR</name>
<description>SLC_0_TXPKTU_E_DSCR</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_TX_PKT_END_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_RXPKTU_H_DSCR</name>
<description>SLC_0_RXPKTU_H_DSCR</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_PKT_START_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_RXPKTU_E_DSCR</name>
<description>SLC_0_RXPKTU_E_DSCR</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_PKT_END_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SEQ_POSITION</name>
<description>SLC_SEQ_POSITION</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_SEQ_POSITION</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SLC0_SEQ_POSITION</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_DSCR_REC_CONF</name>
<description>SLC_0_DSCR_REC_CONF</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_DSCR_REC_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDIO_CRC_ST0</name>
<description>SLC_SDIO_CRC_ST0</description>
<addressOffset>0x11c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAT3_CRC_ERR_CNT</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DAT2_CRC_ERR_CNT</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DAT1_CRC_ERR_CNT</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DAT0_CRC_ERR_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDIO_CRC_ST1</name>
<description>SLC_SDIO_CRC_ST1</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ERR_CNT_CLR</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMD_CRC_ERR_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_EOF_START_DES</name>
<description>SLC_0_EOF_START_DES</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_EOF_START_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_PUSH_DSCR_ADDR</name>
<description>SLC_0_PUSH_DSCR_ADDR</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_PUSH_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_DONE_DSCR_ADDR</name>
<description>SLC_0_DONE_DSCR_ADDR</description>
<addressOffset>0x12c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_DONE_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_SUB_START_DES</name>
<description>SLC_0_SUB_START_DES</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_SUB_PAC_START_DSCR_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_DSCR_CNT</name>
<description>SLC_0_DSCR_CNT</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_GET_EOF_OCC</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DSCR_CNT_LAT</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>0_LEN_LIM_CONF</name>
<description>SLC_0_LEN_LIM_CONF</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_LEN_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>0INT_ST1</name>
<description>SLC_0INT_ST1</description>
<addressOffset>0x13c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_QUICK_EOF_INT_ST1</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMD_DTC_INT_ST1</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_ERR_EOF_INT_ST1</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_WR_RETRY_DONE_INT_ST1</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_HOST_RD_ACK_INT_ST1</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_EMPTY_INT_ST1</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DSCR_ERR_INT_ST1</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_ERR_INT_ST1</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOHOST_INT_ST1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_EOF_INT_ST1</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DONE_INT_ST1</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_SUC_EOF_INT_ST1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DONE_INT_ST1</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_1TO0_INT_ST1</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_1TO0_INT_ST1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_OVF_INT_ST1</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_UDF_INT_ST1</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_START_INT_ST1</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_START_INT_ST1</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT7_INT_ST1</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT6_INT_ST1</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT5_INT_ST1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT4_INT_ST1</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT3_INT_ST1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT2_INT_ST1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT1_INT_ST1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT0_INT_ST1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>0INT_ENA1</name>
<description>SLC_0INT_ENA1</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC0_RX_QUICK_EOF_INT_ENA1</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CMD_DTC_INT_ENA1</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_ERR_EOF_INT_ENA1</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_WR_RETRY_DONE_INT_ENA1</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_HOST_RD_ACK_INT_ENA1</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_EMPTY_INT_ENA1</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DSCR_ERR_INT_ENA1</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DSCR_ERR_INT_ENA1</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOHOST_INT_ENA1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_EOF_INT_ENA1</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_DONE_INT_ENA1</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_SUC_EOF_INT_ENA1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_DONE_INT_ENA1</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN1_1TO0_INT_ENA1</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TOKEN0_1TO0_INT_ENA1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_OVF_INT_ENA1</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_UDF_INT_ENA1</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_TX_START_INT_ENA1</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC0_RX_START_INT_ENA1</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT7_INT_ENA1</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT6_INT_ENA1</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT5_INT_ENA1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT4_INT_ENA1</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT3_INT_ENA1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT2_INT_ENA1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT1_INT_ENA1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT0_INT_ENA1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>1INT_ST1</name>
<description>SLC_1INT_ST1</description>
<addressOffset>0x144</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_ERR_EOF_INT_ST1</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_WR_RETRY_DONE_INT_ST1</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_HOST_RD_ACK_INT_ST1</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_EMPTY_INT_ST1</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DSCR_ERR_INT_ST1</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_ERR_INT_ST1</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOHOST_INT_ST1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_EOF_INT_ST1</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DONE_INT_ST1</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_SUC_EOF_INT_ST1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DONE_INT_ST1</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_1TO0_INT_ST1</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_1TO0_INT_ST1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_OVF_INT_ST1</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_UDF_INT_ST1</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_START_INT_ST1</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_START_INT_ST1</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT15_INT_ST1</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT14_INT_ST1</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT13_INT_ST1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT12_INT_ST1</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT11_INT_ST1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT10_INT_ST1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT9_INT_ST1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT8_INT_ST1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>1INT_ENA1</name>
<description>SLC_1INT_ENA1</description>
<addressOffset>0x148</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC1_TX_ERR_EOF_INT_ENA1</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_WR_RETRY_DONE_INT_ENA1</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_HOST_RD_ACK_INT_ENA1</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_EMPTY_INT_ENA1</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DSCR_ERR_INT_ENA1</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DSCR_ERR_INT_ENA1</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOHOST_INT_ENA1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_EOF_INT_ENA1</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_DONE_INT_ENA1</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_SUC_EOF_INT_ENA1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_DONE_INT_ENA1</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN1_1TO0_INT_ENA1</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TOKEN0_1TO0_INT_ENA1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_OVF_INT_ENA1</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_UDF_INT_ENA1</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_TX_START_INT_ENA1</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLC1_RX_START_INT_ENA1</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT15_INT_ENA1</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT14_INT_ENA1</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT13_INT_ENA1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT12_INT_ENA1</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT11_INT_ENA1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT10_INT_ENA1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT9_INT_ENA1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRHOST_BIT8_INT_ENA1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>SLC_DATE</description>
<addressOffset>0x1f8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ID</name>
<description>SLC_ID</description>
<addressOffset>0x1fc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ID</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>RTCMEM0</name>
<baseAddress>0x3ff61000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral derivedFrom="TIMG">
<name>TIMG1</name>
<baseAddress>0x3ff60000</baseAddress>
</peripheral>
<peripheral>
<name>SHA</name>
<baseAddress>0x3ff03000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral derivedFrom="MCPWM">
<name>PWM1</name>
<baseAddress>0x3ff6c000</baseAddress>
</peripheral>
<peripheral>
<name>RTCCNTL</name>
<baseAddress>0x3ff48000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>1696</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>537681920</offset>
<size>4</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>RTC_CORE_INTR</name>
<description>interrupt of rtc core, level, include rtc watchdog</description>
<value>46</value>
</interrupt>
<registers>
<register>
<name>OPTIONS0</name>
<description>RTC_CNTL_OPTIONS0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SW_SYS_RST</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_WRAP_FORCE_NORST</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_WRAP_FORCE_RST</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ANALOG_FORCE_NOISO</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLL_FORCE_NOISO</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XTL_FORCE_NOISO</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ANALOG_FORCE_ISO</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLL_FORCE_ISO</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XTL_FORCE_ISO</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_CORE_FORCE_PU</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_CORE_FORCE_PD</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_CORE_FOLW_8M</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_I2C_FORCE_PU</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_I2C_FORCE_PD</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_I2C_FOLW_8M</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_FORCE_NOSLEEP</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_FORCE_SLEEP</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BIAS_SLEEP_FOLW_8M</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XTL_FORCE_PU</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XTL_FORCE_PD</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBPLL_FORCE_PU</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBPLL_FORCE_PD</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBPLL_I2C_FORCE_PU</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBPLL_I2C_FORCE_PD</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BB_I2C_FORCE_PU</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BB_I2C_FORCE_PD</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_PROCPU_RST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_APPCPU_RST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_STALL_PROCPU_C0</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SW_STALL_APPCPU_C0</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLP_TIMER0</name>
<description>RTC_CNTL_SLP_TIMER0</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLP_VAL_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLP_TIMER1</name>
<description>RTC_CNTL_SLP_TIMER1</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAIN_TIMER_ALARM_EN</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_VAL_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIME_UPDATE</name>
<description>RTC_CNTL_TIME_UPDATE</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME_UPDATE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_VALID</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIME0</name>
<description>RTC_CNTL_TIME0</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIME1</name>
<description>RTC_CNTL_TIME1</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATE0</name>
<description>RTC_CNTL_STATE0</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEP_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_REJECT</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_WAKEUP</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_ACTIVE_IND</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ULP_CP_SLP_TIMER_EN</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_SLP_TIMER_EN</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APB2RTC_BRIDGE_SEL</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ULP_CP_WAKEUP_FORCE_EN</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_WAKEUP_FORCE_EN</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER1</name>
<description>RTC_CNTL_TIMER1</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLL_BUF_WAIT</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>XTL_BUF_WAIT</name>
<bitOffset>14</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>CK8M_WAIT</name>
<bitOffset>6</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CPU_STALL_WAIT</name>
<bitOffset>1</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CPU_STALL_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER2</name>
<description>RTC_CNTL_TIMER2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MIN_TIME_CK8M_OFF</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ULPCP_TOUCH_START_WAIT</name>
<bitOffset>15</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER3</name>
<description>RTC_CNTL_TIMER3</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ROM_RAM_POWERUP_TIMER</name>
<bitOffset>25</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>ROM_RAM_WAIT_TIMER</name>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>WIFI_POWERUP_TIMER</name>
<bitOffset>9</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>WIFI_WAIT_TIMER</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER4</name>
<description>RTC_CNTL_TIMER4</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DG_WRAP_POWERUP_TIMER</name>
<bitOffset>25</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>DG_WRAP_WAIT_TIMER</name>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>POWERUP_TIMER</name>
<bitOffset>9</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>WAIT_TIMER</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER5</name>
<description>RTC_CNTL_TIMER5</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RTCMEM_POWERUP_TIMER</name>
<bitOffset>25</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>RTCMEM_WAIT_TIMER</name>
<bitOffset>16</bitOffset>
<bitWidth>9</bitWidth>
</field>
<field>
<name>MIN_SLP_VAL</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ULP_CP_SUBTIMER_PREDIV</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>ANA_CONF</name>
<description>RTC_CNTL_ANA_CONF</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLL_I2C_PU</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CKGEN_I2C_PU</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RFRX_PBUS_PU</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXRF_I2C_PU</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PVTMON_PU</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BBPLL_CAL_SLP_START</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLA_FORCE_PU</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLLA_FORCE_PD</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RESET_STATE</name>
<description>RTC_CNTL_RESET_STATE</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PROCPU_STAT_VECTOR_SEL</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APPCPU_STAT_VECTOR_SEL</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RESET_CAUSE_APPCPU</name>
<bitOffset>6</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>RESET_CAUSE_PROCPU</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>WAKEUP_STATE</name>
<description>RTC_CNTL_WAKEUP_STATE</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GPIO_WAKEUP_FILTER</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WAKEUP_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>WAKEUP_CAUSE</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>RTC_CNTL_INT_ENA</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAIN_TIMER_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BROWN_OUT_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ULP_CP_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_VALID_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_IDLE_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_REJECT_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_WAKEUP_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>RTC_CNTL_INT_RAW</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAIN_TIMER_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BROWN_OUT_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ULP_CP_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_VALID_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_IDLE_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_REJECT_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_WAKEUP_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST</name>
<description>RTC_CNTL_INT_ST</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAIN_TIMER_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BROWN_OUT_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_VALID_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_IDLE_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_REJECT_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_WAKEUP_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>RTC_CNTL_INT_CLR</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAIN_TIMER_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BROWN_OUT_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIME_VALID_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_IDLE_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_REJECT_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_WAKEUP_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STORE0</name>
<description>RTC_CNTL_STORE0</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCRATCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STORE1</name>
<description>RTC_CNTL_STORE1</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCRATCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STORE2</name>
<description>RTC_CNTL_STORE2</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCRATCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STORE3</name>
<description>RTC_CNTL_STORE3</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCRATCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT_XTL_CONF</name>
<description>RTC_CNTL_EXT_XTL_CONF</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XTL_EXT_CTR_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XTL_EXT_CTR_LV</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT_WAKEUP_CONF</name>
<description>RTC_CNTL_EXT_WAKEUP_CONF</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXT_WAKEUP1_LV</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXT_WAKEUP0_LV</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLP_REJECT_CONF</name>
<description>RTC_CNTL_SLP_REJECT_CONF</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>REJECT_CAUSE</name>
<bitOffset>28</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DEEP_SLP_REJECT_EN</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LIGHT_SLP_REJECT_EN</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_REJECT_EN</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GPIO_REJECT_EN</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPU_PERIOD_CONF</name>
<description>RTC_CNTL_CPU_PERIOD_CONF</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPUPERIOD_SEL</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CPUSEL_CONF</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDIO_ACT_CONF</name>
<description>RTC_CNTL_SDIO_ACT_CONF</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIO_ACT_DNUM</name>
<bitOffset>22</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK_CONF</name>
<description>RTC_CNTL_CLK_CONF</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ANA_CLK_RTC_SEL</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>ANA_CLK_RTC_SEL</name>
<usage>read-write</usage>
<enumeratedValue>
<name>SLOW_CK</name>
<description>Select slow clock</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CK_XTAL_32K</name>
<description>Select XTAL_32K</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CK8M_D256_OUT</name>
<description>Internal 8 MHz RC oscillator, divided by 256</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>FAST_CLK_RTC_SEL</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>FAST_CLK_RTC_SEL</name>
<usage>read-write</usage>
<enumeratedValue>
<name>XTAL</name>
<description>Select XTAL</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CK8M</name>
<description>Select CK8M</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>SOC_CLK_SEL</name>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>SOC_CLK_SEL</name>
<usage>read-write</usage>
<enumeratedValue>
<name>XTAL</name>
<description>Select XTAL clock</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>PLL</name>
<description>Select PLL clock</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>CK8M</name>
<description>Select CK8M clock</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>APLL</name>
<description>Select APLL clock</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CK8M_FORCE_PU</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CK8M_FORCE_PU</name>
<usage>read-write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Don't force power up</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Force</name>
<description>Force power up</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CK8M_FORCE_PD</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>CK8M_FORCE_PD</name>
<usage>read-write</usage>
<enumeratedValue>
<name>Clear</name>
<description>Don't force power down</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Force</name>
<description>Force power down</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>CK8M_DFREQ</name>
<bitOffset>17</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CK8M_FORCE_NOGATING</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XTAL_FORCE_NOGATING</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK8M_DIV_SEL</name>
<bitOffset>12</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CK8M_DFREQ_FORCE</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIG_CLK8M_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DIG_CLK8M_EN</name>
<usage>read-write</usage>
<enumeratedValue>
<name>Disable</name>
<description>Disable CK8M</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Enable CK8M for digital core (no relation to RTC core)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIG_CLK8M_D256_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DIG_CLK8M_D256_EN</name>
<usage>read-write</usage>
<enumeratedValue>
<name>Disable</name>
<description>Disable CK8M_D256_OUT</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Enable CK8M_D256_OUT for digital core (no relation to RTC core)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DIG_XTAL32K_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
<name>DIG_XTAL32K_EN</name>
<usage>read-write</usage>
<enumeratedValue>
<name>Disable</name>
<description>Disable CK_XTAL_32K</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Enable</name>
<description>Enable CK_XTAL_32K for digital core(no relation to RTC core)</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>ENB_CK8M_DIV</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENB_CK8M</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CK8M_DIV</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CK8M_DIV</name>
<usage>read-write</usage>
<enumeratedValue>
<name>div128</name>
<description>div128</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>div256</name>
<description>div256</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>div512</name>
<description>div512</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>div1024</name>
<description>div1024</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>SDIO_CONF</name>
<description>RTC_CNTL_SDIO_CONF</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XPD_SDIO_REG</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DREFH_SDIO</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DREFM_SDIO</name>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DREFL_SDIO</name>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>REG1P8_READY</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_TIEH</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_FORCE</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDIO_PD_EN</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>BIAS_CONF</name>
<description>RTC_CNTL_BIAS_CONF</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RST_BIAS_I2C</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEC_HEARTBEAT_WIDTH</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INC_HEARTBEAT_PERIOD</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEC_HEARTBEAT_PERIOD</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INC_HEARTBEAT_REFRESH</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ENB_SCK_XTAL</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBG_ATTEN</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FORCE_PU</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_PD</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBOOST_FORCE_PU</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBOOST_FORCE_PD</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBIAS_WAK</name>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DBIAS_SLP</name>
<bitOffset>22</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SCK_DCAP</name>
<bitOffset>14</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DIG_DBIAS_WAK</name>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DIG_DBIAS_SLP</name>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SCK_DCAP_FORCE</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PWC</name>
<description>RTC_CNTL_PWC</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PD_EN</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_PU</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_PD</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLOWMEM_PD_EN</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLOWMEM_FORCE_PU</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLOWMEM_FORCE_PD</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTMEM_PD_EN</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTMEM_FORCE_PU</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTMEM_FORCE_PD</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLOWMEM_FORCE_LPU</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLOWMEM_FORCE_LPD</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLOWMEM_FOLW_CPU</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTMEM_FORCE_LPU</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTMEM_FORCE_LPD</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTMEM_FOLW_CPU</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_NOISO</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_ISO</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLOWMEM_FORCE_ISO</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLOWMEM_FORCE_NOISO</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTMEM_FORCE_ISO</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FASTMEM_FORCE_NOISO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIG_PWC</name>
<description>RTC_CNTL_DIG_PWC</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DG_WRAP_PD_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WIFI_PD_EN</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM4_PD_EN</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM3_PD_EN</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM2_PD_EN</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM1_PD_EN</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM0_PD_EN</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROM0_PD_EN</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_WRAP_FORCE_PU</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_WRAP_FORCE_PD</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WIFI_FORCE_PU</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WIFI_FORCE_PD</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM4_FORCE_PU</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM4_FORCE_PD</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM3_FORCE_PU</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM3_FORCE_PD</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM2_FORCE_PU</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM2_FORCE_PD</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM1_FORCE_PU</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM1_FORCE_PD</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM0_FORCE_PU</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM0_FORCE_PD</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROM0_FORCE_PU</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROM0_FORCE_PD</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSLP_MEM_FORCE_PU</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSLP_MEM_FORCE_PD</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIG_ISO</name>
<description>RTC_CNTL_DIG_ISO</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DG_WRAP_FORCE_NOISO</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_WRAP_FORCE_ISO</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WIFI_FORCE_NOISO</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WIFI_FORCE_ISO</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM4_FORCE_NOISO</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM4_FORCE_ISO</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM3_FORCE_NOISO</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM3_FORCE_ISO</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM2_FORCE_NOISO</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM2_FORCE_ISO</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM1_FORCE_NOISO</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM1_FORCE_ISO</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM0_FORCE_NOISO</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INTER_RAM0_FORCE_ISO</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROM0_FORCE_NOISO</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ROM0_FORCE_ISO</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_PAD_FORCE_HOLD</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_PAD_FORCE_UNHOLD</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_PAD_FORCE_ISO</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_PAD_FORCE_NOISO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_PAD_AUTOHOLD_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLR_DG_PAD_AUTOHOLD</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DG_PAD_AUTOHOLD</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIG_ISO_FORCE_ON</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIG_ISO_FORCE_OFF</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG0</name>
<description>RTC_CNTL_WDTCONFIG0</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_STG0</name>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>WDT_STG0</name>
<usage>read-write</usage>
<enumeratedValue>
<name>Disable</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Interrupt</name>
<description>Trigger an interrupt</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ResetCPU</name>
<description>Reset CPU core</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ResetSystem</name>
<description>Reset System, but not RTC</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>ResetRTC</name>
<description>Reset System & RTC</description>
<value>4</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT_STG1</name>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="WDT_STG0" />
</field>
<field>
<name>WDT_STG2</name>
<bitOffset>22</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="WDT_STG0" />
</field>
<field>
<name>WDT_STG3</name>
<bitOffset>19</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="WDT_STG0" />
</field>
<field>
<name>WDT_EDGE_INT_EN</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_LEVEL_INT_EN</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_CPU_RESET_LENGTH</name>
<bitOffset>14</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>WDT_CPU_RESET_LENGTH</name>
<usage>read-write</usage>
<enumeratedValue>
<name>T100ns</name>
<description>100ns</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>T200ns</name>
<description>200ns</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>T300ns</name>
<description>300ns</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>T400ns</name>
<description>400ns</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>T500ns</name>
<description>500ns</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>T800ns</name>
<description>800ns</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>T1600ns</name>
<description>1600ns</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>T3200ns</name>
<description>3200ns</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT_SYS_RESET_LENGTH</name>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="WDT_CPU_RESET_LENGTH" />
</field>
<field>
<name>WDT_FLASHBOOT_MOD_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_PROCPU_RESET_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_APPCPU_RESET_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_PAUSE_IN_SLP</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG1</name>
<description>RTC_CNTL_WDTCONFIG1</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_STG0_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG2</name>
<description>RTC_CNTL_WDTCONFIG2</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_STG1_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG3</name>
<description>RTC_CNTL_WDTCONFIG3</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_STG2_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG4</name>
<description>RTC_CNTL_WDTCONFIG4</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_STG3_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTFEED</name>
<description>RTC_CNTL_WDTFEED</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_FEED</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTWPROTECT</name>
<description>RTC_CNTL_WDTWPROTECT</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_WKEY</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TEST_MUX</name>
<description>RTC_CNTL_TEST_MUX</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DTEST_RTC</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ENT_RTC</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SW_CPU_STALL</name>
<description>RTC_CNTL_SW_CPU_STALL</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SW_STALL_PROCPU_C1</name>
<bitOffset>26</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>SW_STALL_APPCPU_C1</name>
<bitOffset>20</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>STORE4</name>
<description>RTC_CNTL_STORE4</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCRATCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STORE5</name>
<description>RTC_CNTL_STORE5</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCRATCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STORE6</name>
<description>RTC_CNTL_STORE6</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCRATCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>STORE7</name>
<description>RTC_CNTL_STORE7</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCRATCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIAG1</name>
<description>RTC_CNTL_DIAG1</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOW_POWER_DIAG1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOLD_FORCE</name>
<description>RTC_CNTL_HOLD_FORCE</description>
<addressOffset>0xc8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>X32N_HOLD_FORCE</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_HOLD_FORCE</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_PAD7_HOLD_FORCE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_PAD6_HOLD_FORCE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_PAD5_HOLD_FORCE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_PAD4_HOLD_FORCE</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_PAD3_HOLD_FORCE</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_PAD2_HOLD_FORCE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_PAD1_HOLD_FORCE</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_PAD0_HOLD_FORCE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE4_HOLD_FORCE</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE3_HOLD_FORCE</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE2_HOLD_FORCE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE1_HOLD_FORCE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_HOLD_FORCE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_HOLD_FORCE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC2_HOLD_FORCE</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC1_HOLD_FORCE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT_WAKEUP1</name>
<description>RTC_CNTL_EXT_WAKEUP1</description>
<addressOffset>0xcc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXT_WAKEUP1_STATUS_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXT_WAKEUP1_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT_WAKEUP1_STATUS</name>
<description>RTC_CNTL_EXT_WAKEUP1_STATUS</description>
<addressOffset>0xd0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXT_WAKEUP1_STATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>BROWN_OUT</name>
<description>RTC_CNTL_BROWN_OUT</description>
<addressOffset>0xd4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BROWN_OUT_DET</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BROWN_OUT_ENA</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBROWN_OUT_THRES</name>
<bitOffset>27</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>BROWN_OUT_RST_ENA</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BROWN_OUT_RST_WAIT</name>
<bitOffset>16</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>BROWN_OUT_PD_RF_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BROWN_OUT_CLOSE_FLASH_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>RTC_CNTL_DATE</description>
<addressOffset>0x13c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CNTL_DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
<register>
<name>CNTL</name>
<description>RTC Control Register</description>
<addressOffset>124</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>FORCE_PU</name>
<description>Force RTC power up</description>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_PD</name>
<description>Force RTC power down (decrease voltage to 0.8V or lower)</description>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_DBOOST_PU</name>
<description>Force DBOOST power up</description>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_DBOOST_PD</name>
<description>Force DBOOST power down</description>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DBIAS_WAK</name>
<description>RTC DBIAS during wakeup</description>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>DBIAS_WAK</name>
<usage>read-write</usage>
<enumeratedValue>
<name>BIAS_0V90</name>
<description>Core voltage 0.90V</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>BIAS_0V95</name>
<description>Core voltage 0.95V</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>BIAS_1V00</name>
<description>Core voltage 1.00V</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>BIAS_1V05</name>
<description>Core voltage 1.05V</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>BIAS_1V10</name>
<description>Core voltage 1.10V</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>BIAS_1V15</name>
<description>Core voltage 1.15V</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>BIAS_1V20</name>
<description>Core voltage 1.20V</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>BIAS_1V25</name>
<description>Core voltage 1.25V</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>DBIAS_SLP</name>
<description>RTC DBIAS during sleep</description>
<bitOffset>22</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="DBIAS_WAK" />
</field>
<field>
<name>SCK_DCAP</name>
<description>150kHz oscillator tuning</description>
<bitOffset>14</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DIG_DBIAS_WAK</name>
<description>DBIAS during wakeup</description>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="DBIAS_WAK" />
</field>
<field>
<name>DIG_DBIAS_SLP</name>
<description>DBIAS during wakeup</description>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="DBIAS_WAK" />
</field>
<field>
<name>SCK_DCAP_FORCE</name>
<description>150kHz tuning force</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APLL</name>
<description>APLL I2C Register</description>
<addressOffset>537681932</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>BLOCK</name>
<description>Block</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>Address</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WRITE</name>
<description>Write</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>Ready</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PLL</name>
<description>PLL I2C Register</description>
<addressOffset>537681936</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0</resetValue>
<fields>
<field>
<name>BLOCK</name>
<description>Block</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>ADDR</name>
<description>Address</description>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DATA</name>
<description>Data</description>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>WRITE</name>
<description>Write</description>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUSY</name>
<description>Ready</description>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="MCPWM">
<name>PWM2</name>
<baseAddress>0x3ff6f000</baseAddress>
</peripheral>
<peripheral derivedFrom="UHCI">
<name>UHCI0</name>
<baseAddress>0x3ff54000</baseAddress>
</peripheral>
<peripheral>
<name>SENS</name>
<baseAddress>0x3ff48800</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000540</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SAR_READ_CTRL</name>
<description>SENS_SAR_READ_CTRL</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR1_DATA_INV</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR1_DIG_FORCE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR1_SAMPLE_NUM</name>
<bitOffset>19</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SAR1_CLK_GATED</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR1_SAMPLE_BIT</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAR1_SAMPLE_CYCLE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SAR1_CLK_DIV</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_READ_STATUS1</name>
<description>SENS_SAR_READ_STATUS1</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR1_READER_STATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_MEAS_WAIT1</name>
<description>SENS_SAR_MEAS_WAIT1</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR_AMP_WAIT2</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>SAR_AMP_WAIT1</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_MEAS_WAIT2</name>
<description>SENS_SAR_MEAS_WAIT2</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR2_RSTB_WAIT</name>
<bitOffset>20</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>FORCE_XPD_SAR</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FORCE_XPD_AMP</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAR_AMP_WAIT3</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_MEAS_CTRL</name>
<description>SENS_SAR_MEAS_CTRL</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR2_XPD_WAIT</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SAR_RSTB_FSM</name>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>XPD_SAR_FSM</name>
<bitOffset>16</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AMP_SHORT_REF_GND_FSM</name>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AMP_SHORT_REF_FSM</name>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>AMP_RST_FB_FSM</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>XPD_SAR_AMP_FSM</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_READ_STATUS2</name>
<description>SENS_SAR_READ_STATUS2</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR2_READER_STATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ULP_CP_SLEEP_CYC0</name>
<description>SENS_ULP_CP_SLEEP_CYC0</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEP_CYCLES_S0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ULP_CP_SLEEP_CYC1</name>
<description>SENS_ULP_CP_SLEEP_CYC1</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEP_CYCLES_S1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ULP_CP_SLEEP_CYC2</name>
<description>SENS_ULP_CP_SLEEP_CYC2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEP_CYCLES_S2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ULP_CP_SLEEP_CYC3</name>
<description>SENS_ULP_CP_SLEEP_CYC3</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEP_CYCLES_S3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ULP_CP_SLEEP_CYC4</name>
<description>SENS_ULP_CP_SLEEP_CYC4</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLEEP_CYCLES_S4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_START_FORCE</name>
<description>SENS_SAR_START_FORCE</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR2_PWDET_EN</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR1_STOP</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR2_STOP</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PC_INIT</name>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>SARCLK_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ULP_CP_START_TOP</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ULP_CP_FORCE_START_TOP</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR2_PWDET_CCT</name>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>SAR2_EN_TEST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR2_BIT_WIDTH</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAR1_BIT_WIDTH</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_MEM_WR_CTRL</name>
<description>SENS_SAR_MEM_WR_CTRL</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RTC_MEM_WR_OFFST_CLR</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEM_WR_ADDR_SIZE</name>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>MEM_WR_ADDR_INIT</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_ATTEN1</name>
<description>SENS_SAR_ATTEN1</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR1_ATTEN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_ATTEN2</name>
<description>SENS_SAR_ATTEN2</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR2_ATTEN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_SLAVE_ADDR1</name>
<description>SENS_SAR_SLAVE_ADDR1</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEAS_STATUS</name>
<bitOffset>22</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>I2C_SLAVE_ADDR0</name>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>I2C_SLAVE_ADDR1</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_SLAVE_ADDR2</name>
<description>SENS_SAR_SLAVE_ADDR2</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2C_SLAVE_ADDR2</name>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>I2C_SLAVE_ADDR3</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_SLAVE_ADDR3</name>
<description>SENS_SAR_SLAVE_ADDR3</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSENS_RDY_OUT</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSENS_OUT</name>
<bitOffset>22</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>I2C_SLAVE_ADDR4</name>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>I2C_SLAVE_ADDR5</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_SLAVE_ADDR4</name>
<description>SENS_SAR_SLAVE_ADDR4</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2C_DONE</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C_RDATA</name>
<bitOffset>22</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>I2C_SLAVE_ADDR6</name>
<bitOffset>11</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>I2C_SLAVE_ADDR7</name>
<bitOffset>0</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TSENS_CTRL</name>
<description>SENS_SAR_TSENS_CTRL</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TSENS_DUMP_OUT</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSENS_POWER_UP_FORCE</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSENS_POWER_UP</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSENS_CLK_DIV</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TSENS_IN_INV</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSENS_CLK_GATED</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSENS_CLK_INV</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSENS_XPD_FORCE</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TSENS_XPD_WAIT</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_I2C_CTRL</name>
<description>SENS_SAR_I2C_CTRL</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR_I2C_START_FORCE</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR_I2C_START</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR_I2C_CTRL</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_MEAS_START1</name>
<description>SENS_SAR_MEAS_START1</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR1_EN_PAD_FORCE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR1_EN_PAD</name>
<bitOffset>19</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>MEAS1_START_FORCE</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEAS1_START_SAR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEAS1_DONE_SAR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEAS1_DATA_SAR</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_CTRL1</name>
<description>SENS_SAR_TOUCH_CTRL1</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HALL_PHASE_FORCE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD_HALL_FORCE</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_OUT_1EN</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_OUT_SEL</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_XPD_WAIT</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TOUCH_MEAS_DELAY</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_THRES1</name>
<description>SENS_SAR_TOUCH_THRES1</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_OUT_TH0</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_OUT_TH1</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_THRES2</name>
<description>SENS_SAR_TOUCH_THRES2</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_OUT_TH2</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_OUT_TH3</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_THRES3</name>
<description>SENS_SAR_TOUCH_THRES3</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_OUT_TH4</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_OUT_TH5</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_THRES4</name>
<description>SENS_SAR_TOUCH_THRES4</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_OUT_TH6</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_OUT_TH7</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_THRES5</name>
<description>SENS_SAR_TOUCH_THRES5</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_OUT_TH8</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_OUT_TH9</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_OUT1</name>
<description>SENS_SAR_TOUCH_OUT1</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_MEAS_OUT0</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_MEAS_OUT1</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_OUT2</name>
<description>SENS_SAR_TOUCH_OUT2</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_MEAS_OUT2</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_MEAS_OUT3</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_OUT3</name>
<description>SENS_SAR_TOUCH_OUT3</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_MEAS_OUT4</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_MEAS_OUT5</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_OUT4</name>
<description>SENS_SAR_TOUCH_OUT4</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_MEAS_OUT6</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_MEAS_OUT7</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_OUT5</name>
<description>SENS_SAR_TOUCH_OUT5</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_MEAS_OUT8</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_MEAS_OUT9</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_CTRL2</name>
<description>SENS_SAR_TOUCH_CTRL2</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_MEAS_EN_CLR</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_SLEEP_CYCLES</name>
<bitOffset>14</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TOUCH_START_FORCE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_START_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_START_FSM_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_MEAS_DONE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_MEAS_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_TOUCH_ENABLE</name>
<description>SENS_SAR_TOUCH_ENABLE</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_PAD_OUTEN1</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>TOUCH_PAD_OUTEN2</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>TOUCH_PAD_WORKEN</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_READ_CTRL2</name>
<description>SENS_SAR_READ_CTRL2</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR2_DATA_INV</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR2_DIG_FORCE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR2_PWDET_FORCE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR2_SAMPLE_NUM</name>
<bitOffset>19</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SAR2_CLK_GATED</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR2_SAMPLE_BIT</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAR2_SAMPLE_CYCLE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SAR2_CLK_DIV</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_MEAS_START2</name>
<description>SENS_SAR_MEAS_START2</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR2_EN_PAD_FORCE</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR2_EN_PAD</name>
<bitOffset>19</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>MEAS2_START_FORCE</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEAS2_START_SAR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEAS2_DONE_SAR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MEAS2_DATA_SAR</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_DAC_CTRL1</name>
<description>SENS_SAR_DAC_CTRL1</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAC_CLK_INV</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC_CLK_FORCE_HIGH</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC_CLK_FORCE_LOW</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC_DIG_FORCE</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBUG_BIT_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>SW_TONE_EN</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_FSTEP</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_DAC_CTRL2</name>
<description>SENS_SAR_DAC_CTRL2</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAC_CW_EN2</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC_CW_EN1</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC_INV2</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAC_INV1</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAC_SCALE2</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAC_SCALE1</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DAC_DC2</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>DAC_DC1</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_MEAS_CTRL2</name>
<description>SENS_SAR_MEAS_CTRL2</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AMP_SHORT_REF_GND_FORCE</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AMP_SHORT_REF_FORCE</name>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AMP_RST_FB_FORCE</name>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAR2_RSTB_FORCE</name>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAR_RSTB_FSM_IDLE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD_SAR_FSM_IDLE</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AMP_SHORT_REF_GND_FSM_IDLE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AMP_SHORT_REF_FSM_IDLE</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AMP_RST_FB_FSM_IDLE</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD_SAR_AMP_FSM_IDLE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR1_DAC_XPD_FSM_IDLE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SAR1_DAC_XPD_FSM</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_NOUSE</name>
<description>SENS_SAR_NOUSE</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR_NOUSE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARDATE</name>
<description>SENS_SARDATE</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR_DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>NRX</name>
<baseAddress>0x3ff5cc00</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>RTCIO</name>
<baseAddress>0x3ff48400</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000660</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>OUT</name>
<description>RTC_GPIO_OUT</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_DATA</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_W1TS</name>
<description>RTC_GPIO_OUT_W1TS</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_DATA_W1TS</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_W1TC</name>
<description>RTC_GPIO_OUT_W1TC</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_DATA_W1TC</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE</name>
<description>RTC_GPIO_ENABLE</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE_W1TS</name>
<description>RTC_GPIO_ENABLE_W1TS</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE_W1TS</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>ENABLE_W1TC</name>
<description>RTC_GPIO_ENABLE_W1TC</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ENABLE_W1TC</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>RTC_GPIO_STATUS</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_INT</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS_W1TS</name>
<description>RTC_GPIO_STATUS_W1TS</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_INT_W1TS</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS_W1TC</name>
<description>RTC_GPIO_STATUS_W1TC</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>STATUS_INT_W1TC</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<name>IN</name>
<description>RTC_GPIO_IN</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN_NEXT</name>
<bitOffset>14</bitOffset>
<bitWidth>18</bitWidth>
</field>
</fields>
</register>
<register>
<dim>18</dim>
<dimIncrement>0x4</dimIncrement>
<dimIndex>0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17</dimIndex>
<name>PIN%s</name>
<description>RTC_GPIO_PIN%s</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WAKEUP_ENABLE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INT_TYPE</name>
<bitOffset>7</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PAD_DRIVER</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTC_DEBUG_SEL</name>
<description>RTC_IO_RTC_DEBUG_SEL</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DEBUG_12M_NO_GATING</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DEBUG_SEL4</name>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DEBUG_SEL3</name>
<bitOffset>15</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DEBUG_SEL2</name>
<bitOffset>10</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DEBUG_SEL1</name>
<bitOffset>5</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>DEBUG_SEL0</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DIG_PAD_HOLD</name>
<description>RTC_IO_DIG_PAD_HOLD</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DIG_PAD_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>HALL_SENS</name>
<description>RTC_IO_HALL_SENS</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XPD_HALL</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HALL_PHASE</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SENSOR_PADS</name>
<description>RTC_IO_SENSOR_PADS</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SENSE1_HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE2_HOLD</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE3_HOLD</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE4_HOLD</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE1_MUX_SEL</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE2_MUX_SEL</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE3_MUX_SEL</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE4_MUX_SEL</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE1_FUN_SEL</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SENSE1_SLP_SEL</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE1_SLP_IE</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE1_FUN_IE</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE2_FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SENSE2_SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE2_SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE2_FUN_IE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE3_FUN_SEL</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SENSE3_SLP_SEL</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE3_SLP_IE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE3_FUN_IE</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE4_FUN_SEL</name>
<bitOffset>7</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SENSE4_SLP_SEL</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE4_SLP_IE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SENSE4_FUN_IE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ADC_PAD</name>
<description>RTC_IO_ADC_PAD</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ADC1_HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC2_HOLD</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC1_MUX_SEL</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC2_MUX_SEL</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC1_FUN_SEL</name>
<bitOffset>26</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADC1_SLP_SEL</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC1_SLP_IE</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC1_FUN_IE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC2_FUN_SEL</name>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ADC2_SLP_SEL</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC2_SLP_IE</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ADC2_FUN_IE</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PAD_DAC1</name>
<description>RTC_IO_PAD_DAC1</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDAC1_DRV</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PDAC1_HOLD</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_DAC</name>
<bitOffset>19</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PDAC1_XPD_DAC</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_MUX_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_FUN_SEL</name>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PDAC1_SLP_SEL</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_SLP_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_SLP_OE</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_FUN_IE</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC1_DAC_XPD_FORCE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PAD_DAC2</name>
<description>RTC_IO_PAD_DAC2</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PDAC2_DRV</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PDAC2_HOLD</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_DAC</name>
<bitOffset>19</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PDAC2_XPD_DAC</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_MUX_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_FUN_SEL</name>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PDAC2_SLP_SEL</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_SLP_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_SLP_OE</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_FUN_IE</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PDAC2_DAC_XPD_FORCE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>XTAL_32K_PAD</name>
<description>RTC_IO_XTAL_32K_PAD</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>X32N_DRV</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>X32N_HOLD</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32N_RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32N_RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_DRV</name>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>X32P_HOLD</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_RDE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_RUE</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC_XTAL_32K</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>XPD_XTAL_32K</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32N_MUX_SEL</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_MUX_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32N_FUN_SEL</name>
<bitOffset>15</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>X32N_SLP_SEL</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32N_SLP_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32N_SLP_OE</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32N_FUN_IE</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_FUN_SEL</name>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>X32P_SLP_SEL</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_SLP_IE</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_SLP_OE</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>X32P_FUN_IE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRES_XTAL_32K</name>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>DBIAS_XTAL_32K</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_CFG</name>
<description>RTC_IO_TOUCH_CFG</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TOUCH_XPD_BIAS</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TOUCH_DREFH</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TOUCH_DREFL</name>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TOUCH_DRANGE</name>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TOUCH_DCUR</name>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD0</name>
<description>RTC_IO_TOUCH_PAD0</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRV</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_OE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD1</name>
<description>RTC_IO_TOUCH_PAD1</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRV</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_OE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD2</name>
<description>RTC_IO_TOUCH_PAD2</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRV</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_OE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD3</name>
<description>RTC_IO_TOUCH_PAD3</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRV</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_OE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD4</name>
<description>RTC_IO_TOUCH_PAD4</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRV</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_OE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD5</name>
<description>RTC_IO_TOUCH_PAD5</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRV</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_OE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD6</name>
<description>RTC_IO_TOUCH_PAD6</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRV</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_OE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD7</name>
<description>RTC_IO_TOUCH_PAD7</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HOLD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DRV</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RDE</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RUE</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MUX_SEL</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_IE</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_OE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD8</name>
<description>RTC_IO_TOUCH_PAD8</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TOUCH_PAD9</name>
<description>RTC_IO_TOUCH_PAD9</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DAC</name>
<bitOffset>23</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>START</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIE_OPT</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XPD</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TO_GPIO</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>EXT_WAKEUP0</name>
<description>RTC_IO_EXT_WAKEUP0</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXT_WAKEUP0_SEL</name>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>XTL_EXT_CTR</name>
<description>RTC_IO_XTL_EXT_CTR</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XTL_EXT_CTR_SEL</name>
<bitOffset>27</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAR_I2C_IO</name>
<description>RTC_IO_SAR_I2C_IO</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SAR_I2C_SDA_SEL</name>
<bitOffset>30</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAR_I2C_SCL_SEL</name>
<bitOffset>28</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SAR_DEBUG_BIT_SEL</name>
<bitOffset>23</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>RTC_IO_DATE</description>
<addressOffset>0xc8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IO_DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FE</name>
<baseAddress>0x3ff46000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>BB</name>
<baseAddress>0x3ff5d000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>DPORT</name>
<baseAddress>0x3ff00000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00002de0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PRO_BOOT_REMAP_CTRL</name>
<description>DPORT_PRO_BOOT_REMAP_CTRL</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_BOOT_REMAP</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_BOOT_REMAP_CTRL</name>
<description>DPORT_APP_BOOT_REMAP_CTRL</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_BOOT_REMAP</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ACCESS_CHECK</name>
<description>DPORT_ACCESS_CHECK</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACCESS_CHECK_APP</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACCESS_CHECK_PRO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DPORT_APB_MASK0</name>
<description>DPORT_PRO_DPORT_APB_MASK0</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRODPORT_APB_MASK0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DPORT_APB_MASK1</name>
<description>DPORT_PRO_DPORT_APB_MASK1</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRODPORT_APB_MASK1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DPORT_APB_MASK0</name>
<description>DPORT_APP_DPORT_APB_MASK0</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPDPORT_APB_MASK0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DPORT_APB_MASK1</name>
<description>DPORT_APP_DPORT_APB_MASK1</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPDPORT_APB_MASK1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERI_CLK_EN</name>
<description>DPORT_PERI_CLK_EN</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERI_CLK_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>DIGITAL_SIGNATURE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SECURE_BOOT</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSA_ACCELERATOR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHA_ACCELERATOR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AES_ACCELERATOR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERI_RST_EN</name>
<description>DPORT_PERI_RST_EN</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERI_RST_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>DIGITAL_SIGNATURE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SECURE_BOOT</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RSA_ACCELERATOR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHA_ACCELERATOR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AES_ACCELERATOR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WIFI_BB_CFG</name>
<description>DPORT_WIFI_BB_CFG</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WIFI_BB_CFG</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WIFI_BB_CFG_2</name>
<description>DPORT_WIFI_BB_CFG_2</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WIFI_BB_CFG_2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APPCPU_CTRL_A</name>
<description>DPORT_APPCPU_CTRL_A</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPCPU_RESETTING</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APPCPU_CTRL_B</name>
<description>DPORT_APPCPU_CTRL_B</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPCPU_CLKGATE_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APPCPU_CTRL_C</name>
<description>DPORT_APPCPU_CTRL_C</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPCPU_RUNSTALL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APPCPU_CTRL_D</name>
<description>DPORT_APPCPU_CTRL_D</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APPCPU_BOOT_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPU_PER_CONF</name>
<description>DPORT_CPU_PER_CONF</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FAST_CLK_RTC_SEL</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOWSPEED_CLK_SEL</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CPUPERIOD_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CPUPERIOD_SEL</name>
<usage>read-write</usage>
<enumeratedValue>
<name>SEL_80</name>
<description>Select 80 MHz clock</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>SEL_160</name>
<description>Select 160 MHz clock</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>SEL_240</name>
<description>Select 240 MHz clock</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_CTRL</name>
<description>DPORT_PRO_CACHE_CTRL</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_DRAM_HL</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_REQ</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHB_SPI_REQ</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_SLAVE_REQ</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_AHB_SPI_REQ</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_DRAM_SPLIT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_SINGLE_IRAM_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_3_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_2_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_1_EN</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_0_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_FLUSH_DONE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_FLUSH_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_ENABLE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_MODE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_CTRL1</name>
<description>DPORT_PRO_CACHE_CTRL1</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CACHE_MMU_IA_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CMMU_PD</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CMMU_FORCE_ON</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CMMU_FLASH_PAGE_MODE</name>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>PRO_CMMU_SRAM_PAGE_MODE</name>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PRO_CACHE_MASK_OPSDRAM</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_MASK_DROM0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_MASK_DRAM1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_MASK_IROM0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_MASK_IRAM1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_MASK_IRAM0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_LOCK_0_ADDR</name>
<description>DPORT_PRO_CACHE_LOCK_0_ADDR</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CACHE_LOCK_0_ADDR_MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_0_ADDR_MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_0_ADDR_PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_LOCK_1_ADDR</name>
<description>DPORT_PRO_CACHE_LOCK_1_ADDR</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CACHE_LOCK_1_ADDR_MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_1_ADDR_MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_1_ADDR_PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_LOCK_2_ADDR</name>
<description>DPORT_PRO_CACHE_LOCK_2_ADDR</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CACHE_LOCK_2_ADDR_MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_2_ADDR_MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_2_ADDR_PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_LOCK_3_ADDR</name>
<description>DPORT_PRO_CACHE_LOCK_3_ADDR</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CACHE_LOCK_3_ADDR_MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_3_ADDR_MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PRO_CACHE_LOCK_3_ADDR_PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_CTRL</name>
<description>DPORT_APP_CACHE_CTRL</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_DRAM_HL</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_SLAVE_REQ</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_AHB_SPI_REQ</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_DRAM_SPLIT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_SINGLE_IRAM_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_3_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_2_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_1_EN</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_0_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_FLUSH_DONE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_FLUSH_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_ENABLE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_MODE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_CTRL1</name>
<description>DPORT_APP_CACHE_CTRL1</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_MMU_IA_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CMMU_PD</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CMMU_FORCE_ON</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CMMU_FLASH_PAGE_MODE</name>
<bitOffset>9</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>APP_CMMU_SRAM_PAGE_MODE</name>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>APP_CACHE_MASK_OPSDRAM</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_MASK_DROM0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_MASK_DRAM1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_MASK_IROM0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_MASK_IRAM1</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_MASK_IRAM0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_LOCK_0_ADDR</name>
<description>DPORT_APP_CACHE_LOCK_0_ADDR</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_LOCK_0_ADDR_MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_0_ADDR_MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_0_ADDR_PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_LOCK_1_ADDR</name>
<description>DPORT_APP_CACHE_LOCK_1_ADDR</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_LOCK_1_ADDR_MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_1_ADDR_MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_1_ADDR_PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_LOCK_2_ADDR</name>
<description>DPORT_APP_CACHE_LOCK_2_ADDR</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_LOCK_2_ADDR_MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_2_ADDR_MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_2_ADDR_PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_LOCK_3_ADDR</name>
<description>DPORT_APP_CACHE_LOCK_3_ADDR</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_LOCK_3_ADDR_MAX</name>
<bitOffset>18</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_3_ADDR_MIN</name>
<bitOffset>14</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>APP_CACHE_LOCK_3_ADDR_PRE</name>
<bitOffset>0</bitOffset>
<bitWidth>14</bitWidth>
</field>
</fields>
</register>
<register>
<name>TRACEMEM_MUX_MODE</name>
<description>DPORT_TRACEMEM_MUX_MODE</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TRACEMEM_MUX_MODE</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TRACEMEM_ENA</name>
<description>DPORT_PRO_TRACEMEM_ENA</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TRACEMEM_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TRACEMEM_ENA</name>
<description>DPORT_APP_TRACEMEM_ENA</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TRACEMEM_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CACHE_MUX_MODE</name>
<description>DPORT_CACHE_MUX_MODE</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CACHE_MUX_MODE</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_PAGE_MODE</name>
<description>DPORT_IMMU_PAGE_MODE</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_PAGE_MODE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INTERNAL_SRAM_IMMU_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_PAGE_MODE</name>
<description>DPORT_DMMU_PAGE_MODE</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_PAGE_MODE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INTERNAL_SRAM_DMMU_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ROM_MPU_ENA</name>
<description>DPORT_ROM_MPU_ENA</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_ROM_MPU_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_ROM_MPU_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SHARE_ROM_MPU_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MEM_PD_MASK</name>
<description>DPORT_MEM_PD_MASK</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSLP_MEM_PD_MASK</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ROM_PD_CTRL</name>
<description>DPORT_ROM_PD_CTRL</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHARE_ROM_PD</name>
<bitOffset>2</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>APP_ROM_PD</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_ROM_PD</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ROM_FO_CTRL</name>
<description>DPORT_ROM_FO_CTRL</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHARE_ROM_FO</name>
<bitOffset>2</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>APP_ROM_FO</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_ROM_FO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRAM_PD_CTRL_0</name>
<description>DPORT_SRAM_PD_CTRL_0</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SRAM_PD_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRAM_PD_CTRL_1</name>
<description>DPORT_SRAM_PD_CTRL_1</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SRAM_PD_1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRAM_FO_CTRL_0</name>
<description>DPORT_SRAM_FO_CTRL_0</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SRAM_FO_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SRAM_FO_CTRL_1</name>
<description>DPORT_SRAM_FO_CTRL_1</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SRAM_FO_1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>IRAM_DRAM_AHB_SEL</name>
<description>DPORT_IRAM_DRAM_AHB_SEL</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MAC_DUMP_MODE</name>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MASK_AHB</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASK_APP_DRAM</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASK_PRO_DRAM</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASK_APP_IRAM</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASK_PRO_IRAM</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TAG_FO_CTRL</name>
<description>DPORT_TAG_FO_CTRL</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_TAG_PD</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_TAG_FORCE_ON</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_TAG_PD</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_TAG_FORCE_ON</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB_LITE_MASK</name>
<description>DPORT_AHB_LITE_MASK</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHB_LITE_SDHOST_PID_REG</name>
<bitOffset>11</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>AHB_LITE_MASK_APPDPORT</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHB_LITE_MASK_PRODPORT</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHB_LITE_MASK_SDIO</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHB_LITE_MASK_APP</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHB_LITE_MASK_PRO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB_MPU_TABLE_0</name>
<description>DPORT_AHB_MPU_TABLE_0</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHB_ACCESS_GRANT_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB_MPU_TABLE_1</name>
<description>DPORT_AHB_MPU_TABLE_1</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHB_ACCESS_GRANT_1</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>HOST_INF_SEL</name>
<description>DPORT_HOST_INF_SEL</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LINK_DEVICE_SEL</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>PERI_IO_SWAP</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERIP_CLK_EN</name>
<description>DPORT_PERIP_CLK_EN</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERIP_CLK_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>PWM3</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWM2</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART_MEM</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART2</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI_DMA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2S1</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWM1</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAN</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWM0</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI3</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_GROUP1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EFUSE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_GROUP0</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UHCI1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LED_PWM</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PULSE_CNT</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REMOTE_CONTROLLER</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UHCI0</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C0</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2S0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDG</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI0</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMERS</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PERIP_RST_EN</name>
<description>DPORT_PERIP_RST_EN</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PERIP_RST</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
<field>
<name>SPI_DECRYPT_ENABLE</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI_ENCRYPT_ENABLE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_SPI_MASK_APP</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_SPI_MASK_PRO</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWM3</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWM2</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART_MEM</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART2</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI_DMA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2S1</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWM1</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAN</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PWM0</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI3</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_GROUP1</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EFUSE</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_GROUP0</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UHCI1</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LED_PWM</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PULSE_CNT</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>REMOTE_CONTROLLER</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UHCI0</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2C0</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI2</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART1</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>I2S0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDG</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>UART0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SPI0</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMERS</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WIFI_CLK_EN</name>
<description>DPORT_WIFI_CLK_EN</description>
<addressOffset>0xcc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WIFI_CLK_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CORE_RST_EN</name>
<description>DPORT_CORE_RST_EN</description>
<addressOffset>0xd0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CORE_RST</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>BT_LPCK_DIV_INT</name>
<description>DPORT_BT_LPCK_DIV_INT</description>
<addressOffset>0xd4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BTEXTWAKEUP_REQ</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BT_LPCK_DIV_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>BT_LPCK_DIV_FRAC</name>
<description>DPORT_BT_LPCK_DIV_FRAC</description>
<addressOffset>0xd8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LPCLK_SEL_XTAL32K</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPCLK_SEL_XTAL</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPCLK_SEL_8M</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LPCLK_SEL_RTC_SLOW</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BT_LPCK_DIV_A</name>
<bitOffset>12</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>BT_LPCK_DIV_B</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPU_INTR_FROM_CPU_0</name>
<description>DPORT_CPU_INTR_FROM_CPU_0</description>
<addressOffset>0xdc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPU_INTR_FROM_CPU_0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPU_INTR_FROM_CPU_1</name>
<description>DPORT_CPU_INTR_FROM_CPU_1</description>
<addressOffset>0xe0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPU_INTR_FROM_CPU_1</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPU_INTR_FROM_CPU_2</name>
<description>DPORT_CPU_INTR_FROM_CPU_2</description>
<addressOffset>0xe4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPU_INTR_FROM_CPU_2</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CPU_INTR_FROM_CPU_3</name>
<description>DPORT_CPU_INTR_FROM_CPU_3</description>
<addressOffset>0xe8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CPU_INTR_FROM_CPU_3</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_INTR_STATUS_0</name>
<description>DPORT_PRO_INTR_STATUS_0</description>
<addressOffset>0xec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_INTR_STATUS_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_INTR_STATUS_1</name>
<description>DPORT_PRO_INTR_STATUS_1</description>
<addressOffset>0xf0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_INTR_STATUS_1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_INTR_STATUS_2</name>
<description>DPORT_PRO_INTR_STATUS_2</description>
<addressOffset>0xf4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_INTR_STATUS_2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_INTR_STATUS_0</name>
<description>DPORT_APP_INTR_STATUS_0</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_INTR_STATUS_0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_INTR_STATUS_1</name>
<description>DPORT_APP_INTR_STATUS_1</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_INTR_STATUS_1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_INTR_STATUS_2</name>
<description>DPORT_APP_INTR_STATUS_2</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_INTR_STATUS_2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_MAC_INTR_MAP</name>
<description>DPORT_PRO_MAC_INTR_MAP</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_MAC_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_MAC_NMI_MAP</name>
<description>DPORT_PRO_MAC_NMI_MAP</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_MAC_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_BB_INT_MAP</name>
<description>DPORT_PRO_BB_INT_MAP</description>
<addressOffset>0x10c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_BB_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_BT_MAC_INT_MAP</name>
<description>DPORT_PRO_BT_MAC_INT_MAP</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_BT_MAC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_BT_BB_INT_MAP</name>
<description>DPORT_PRO_BT_BB_INT_MAP</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_BT_BB_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_BT_BB_NMI_MAP</name>
<description>DPORT_PRO_BT_BB_NMI_MAP</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_BT_BB_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_RWBT_IRQ_MAP</name>
<description>DPORT_PRO_RWBT_IRQ_MAP</description>
<addressOffset>0x11c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_RWBT_IRQ_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_RWBLE_IRQ_MAP</name>
<description>DPORT_PRO_RWBLE_IRQ_MAP</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_RWBLE_IRQ_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_RWBT_NMI_MAP</name>
<description>DPORT_PRO_RWBT_NMI_MAP</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_RWBT_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_RWBLE_NMI_MAP</name>
<description>DPORT_PRO_RWBLE_NMI_MAP</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_RWBLE_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SLC0_INTR_MAP</name>
<description>DPORT_PRO_SLC0_INTR_MAP</description>
<addressOffset>0x12c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SLC0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SLC1_INTR_MAP</name>
<description>DPORT_PRO_SLC1_INTR_MAP</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SLC1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_UHCI0_INTR_MAP</name>
<description>DPORT_PRO_UHCI0_INTR_MAP</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_UHCI0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_UHCI1_INTR_MAP</name>
<description>DPORT_PRO_UHCI1_INTR_MAP</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_UHCI1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG_T0_LEVEL_INT_MAP</name>
<description>DPORT_PRO_TG_T0_LEVEL_INT_MAP</description>
<addressOffset>0x13c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG_T0_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG_T1_LEVEL_INT_MAP</name>
<description>DPORT_PRO_TG_T1_LEVEL_INT_MAP</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG_T1_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG_WDT_LEVEL_INT_MAP</name>
<description>DPORT_PRO_TG_WDT_LEVEL_INT_MAP</description>
<addressOffset>0x144</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG_WDT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG_LACT_LEVEL_INT_MAP</name>
<description>DPORT_PRO_TG_LACT_LEVEL_INT_MAP</description>
<addressOffset>0x148</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG_LACT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_T0_LEVEL_INT_MAP</name>
<description>DPORT_PRO_TG1_T0_LEVEL_INT_MAP</description>
<addressOffset>0x14c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG1_T0_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_T1_LEVEL_INT_MAP</name>
<description>DPORT_PRO_TG1_T1_LEVEL_INT_MAP</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG1_T1_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_WDT_LEVEL_INT_MAP</name>
<description>DPORT_PRO_TG1_WDT_LEVEL_INT_MAP</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG1_WDT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_LACT_LEVEL_INT_MAP</name>
<description>DPORT_PRO_TG1_LACT_LEVEL_INT_MAP</description>
<addressOffset>0x158</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG1_LACT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_GPIO_INTERRUPT_MAP</name>
<description>DPORT_PRO_GPIO_INTERRUPT_MAP</description>
<addressOffset>0x15c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_GPIO_INTERRUPT_PRO_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_GPIO_INTERRUPT_NMI_MAP</name>
<description>DPORT_PRO_GPIO_INTERRUPT_NMI_MAP</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_GPIO_INTERRUPT_PRO_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_INTR_FROM_CPU_0_MAP</name>
<description>DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP</description>
<addressOffset>0x164</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CPU_INTR_FROM_CPU_0_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_INTR_FROM_CPU_1_MAP</name>
<description>DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP</description>
<addressOffset>0x168</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CPU_INTR_FROM_CPU_1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_INTR_FROM_CPU_2_MAP</name>
<description>DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP</description>
<addressOffset>0x16c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CPU_INTR_FROM_CPU_2_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_INTR_FROM_CPU_3_MAP</name>
<description>DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CPU_INTR_FROM_CPU_3_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SPI_INTR_0_MAP</name>
<description>DPORT_PRO_SPI_INTR_0_MAP</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SPI_INTR_0_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SPI_INTR_1_MAP</name>
<description>DPORT_PRO_SPI_INTR_1_MAP</description>
<addressOffset>0x178</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SPI_INTR_1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SPI_INTR_2_MAP</name>
<description>DPORT_PRO_SPI_INTR_2_MAP</description>
<addressOffset>0x17c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SPI_INTR_2_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SPI_INTR_3_MAP</name>
<description>DPORT_PRO_SPI_INTR_3_MAP</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SPI_INTR_3_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_I2S0_INT_MAP</name>
<description>DPORT_PRO_I2S0_INT_MAP</description>
<addressOffset>0x184</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_I2S0_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_I2S1_INT_MAP</name>
<description>DPORT_PRO_I2S1_INT_MAP</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_I2S1_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_UART_INTR_MAP</name>
<description>DPORT_PRO_UART_INTR_MAP</description>
<addressOffset>0x18c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_UART_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_UART1_INTR_MAP</name>
<description>DPORT_PRO_UART1_INTR_MAP</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_UART1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_UART2_INTR_MAP</name>
<description>DPORT_PRO_UART2_INTR_MAP</description>
<addressOffset>0x194</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_UART2_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SDIO_HOST_INTERRUPT_MAP</name>
<description>DPORT_PRO_SDIO_HOST_INTERRUPT_MAP</description>
<addressOffset>0x198</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SDIO_HOST_INTERRUPT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_EMAC_INT_MAP</name>
<description>DPORT_PRO_EMAC_INT_MAP</description>
<addressOffset>0x19c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_EMAC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_PWM0_INTR_MAP</name>
<description>DPORT_PRO_PWM0_INTR_MAP</description>
<addressOffset>0x1a0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_PWM0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_PWM1_INTR_MAP</name>
<description>DPORT_PRO_PWM1_INTR_MAP</description>
<addressOffset>0x1a4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_PWM1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_PWM2_INTR_MAP</name>
<description>DPORT_PRO_PWM2_INTR_MAP</description>
<addressOffset>0x1a8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_PWM2_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_PWM3_INTR_MAP</name>
<description>DPORT_PRO_PWM3_INTR_MAP</description>
<addressOffset>0x1ac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_PWM3_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_LEDC_INT_MAP</name>
<description>DPORT_PRO_LEDC_INT_MAP</description>
<addressOffset>0x1b0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_LEDC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_EFUSE_INT_MAP</name>
<description>DPORT_PRO_EFUSE_INT_MAP</description>
<addressOffset>0x1b4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_EFUSE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CAN_INT_MAP</name>
<description>DPORT_PRO_CAN_INT_MAP</description>
<addressOffset>0x1b8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CAN_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_RTC_CORE_INTR_MAP</name>
<description>DPORT_PRO_RTC_CORE_INTR_MAP</description>
<addressOffset>0x1bc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_RTC_CORE_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_RMT_INTR_MAP</name>
<description>DPORT_PRO_RMT_INTR_MAP</description>
<addressOffset>0x1c0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_RMT_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_PCNT_INTR_MAP</name>
<description>DPORT_PRO_PCNT_INTR_MAP</description>
<addressOffset>0x1c4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_PCNT_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_I2C_EXT0_INTR_MAP</name>
<description>DPORT_PRO_I2C_EXT0_INTR_MAP</description>
<addressOffset>0x1c8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_I2C_EXT0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_I2C_EXT1_INTR_MAP</name>
<description>DPORT_PRO_I2C_EXT1_INTR_MAP</description>
<addressOffset>0x1cc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_I2C_EXT1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_RSA_INTR_MAP</name>
<description>DPORT_PRO_RSA_INTR_MAP</description>
<addressOffset>0x1d0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_RSA_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SPI1_DMA_INT_MAP</name>
<description>DPORT_PRO_SPI1_DMA_INT_MAP</description>
<addressOffset>0x1d4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SPI1_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SPI2_DMA_INT_MAP</name>
<description>DPORT_PRO_SPI2_DMA_INT_MAP</description>
<addressOffset>0x1d8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SPI2_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_SPI3_DMA_INT_MAP</name>
<description>DPORT_PRO_SPI3_DMA_INT_MAP</description>
<addressOffset>0x1dc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_SPI3_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_WDG_INT_MAP</name>
<description>DPORT_PRO_WDG_INT_MAP</description>
<addressOffset>0x1e0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_WDG_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TIMER_INT1_MAP</name>
<description>DPORT_PRO_TIMER_INT1_MAP</description>
<addressOffset>0x1e4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TIMER_INT1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TIMER_INT2_MAP</name>
<description>DPORT_PRO_TIMER_INT2_MAP</description>
<addressOffset>0x1e8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TIMER_INT2_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG_T0_EDGE_INT_MAP</name>
<description>DPORT_PRO_TG_T0_EDGE_INT_MAP</description>
<addressOffset>0x1ec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG_T0_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG_T1_EDGE_INT_MAP</name>
<description>DPORT_PRO_TG_T1_EDGE_INT_MAP</description>
<addressOffset>0x1f0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG_T1_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG_WDT_EDGE_INT_MAP</name>
<description>DPORT_PRO_TG_WDT_EDGE_INT_MAP</description>
<addressOffset>0x1f4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG_WDT_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG_LACT_EDGE_INT_MAP</name>
<description>DPORT_PRO_TG_LACT_EDGE_INT_MAP</description>
<addressOffset>0x1f8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG_LACT_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_T0_EDGE_INT_MAP</name>
<description>DPORT_PRO_TG1_T0_EDGE_INT_MAP</description>
<addressOffset>0x1fc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG1_T0_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_T1_EDGE_INT_MAP</name>
<description>DPORT_PRO_TG1_T1_EDGE_INT_MAP</description>
<addressOffset>0x200</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG1_T1_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_WDT_EDGE_INT_MAP</name>
<description>DPORT_PRO_TG1_WDT_EDGE_INT_MAP</description>
<addressOffset>0x204</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG1_WDT_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_TG1_LACT_EDGE_INT_MAP</name>
<description>DPORT_PRO_TG1_LACT_EDGE_INT_MAP</description>
<addressOffset>0x208</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_TG1_LACT_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_MMU_IA_INT_MAP</name>
<description>DPORT_PRO_MMU_IA_INT_MAP</description>
<addressOffset>0x20c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_MMU_IA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_MPU_IA_INT_MAP</name>
<description>DPORT_PRO_MPU_IA_INT_MAP</description>
<addressOffset>0x210</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_MPU_IA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CACHE_IA_INT_MAP</name>
<description>DPORT_PRO_CACHE_IA_INT_MAP</description>
<addressOffset>0x214</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CACHE_IA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_MAC_INTR_MAP</name>
<description>DPORT_APP_MAC_INTR_MAP</description>
<addressOffset>0x218</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_MAC_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_MAC_NMI_MAP</name>
<description>DPORT_APP_MAC_NMI_MAP</description>
<addressOffset>0x21c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_MAC_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_BB_INT_MAP</name>
<description>DPORT_APP_BB_INT_MAP</description>
<addressOffset>0x220</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_BB_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_BT_MAC_INT_MAP</name>
<description>DPORT_APP_BT_MAC_INT_MAP</description>
<addressOffset>0x224</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_BT_MAC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_BT_BB_INT_MAP</name>
<description>DPORT_APP_BT_BB_INT_MAP</description>
<addressOffset>0x228</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_BT_BB_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_BT_BB_NMI_MAP</name>
<description>DPORT_APP_BT_BB_NMI_MAP</description>
<addressOffset>0x22c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_BT_BB_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_RWBT_IRQ_MAP</name>
<description>DPORT_APP_RWBT_IRQ_MAP</description>
<addressOffset>0x230</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_RWBT_IRQ_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_RWBLE_IRQ_MAP</name>
<description>DPORT_APP_RWBLE_IRQ_MAP</description>
<addressOffset>0x234</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_RWBLE_IRQ_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_RWBT_NMI_MAP</name>
<description>DPORT_APP_RWBT_NMI_MAP</description>
<addressOffset>0x238</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_RWBT_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_RWBLE_NMI_MAP</name>
<description>DPORT_APP_RWBLE_NMI_MAP</description>
<addressOffset>0x23c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_RWBLE_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SLC0_INTR_MAP</name>
<description>DPORT_APP_SLC0_INTR_MAP</description>
<addressOffset>0x240</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SLC0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SLC1_INTR_MAP</name>
<description>DPORT_APP_SLC1_INTR_MAP</description>
<addressOffset>0x244</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SLC1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_UHCI0_INTR_MAP</name>
<description>DPORT_APP_UHCI0_INTR_MAP</description>
<addressOffset>0x248</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_UHCI0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_UHCI1_INTR_MAP</name>
<description>DPORT_APP_UHCI1_INTR_MAP</description>
<addressOffset>0x24c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_UHCI1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG_T0_LEVEL_INT_MAP</name>
<description>DPORT_APP_TG_T0_LEVEL_INT_MAP</description>
<addressOffset>0x250</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG_T0_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG_T1_LEVEL_INT_MAP</name>
<description>DPORT_APP_TG_T1_LEVEL_INT_MAP</description>
<addressOffset>0x254</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG_T1_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG_WDT_LEVEL_INT_MAP</name>
<description>DPORT_APP_TG_WDT_LEVEL_INT_MAP</description>
<addressOffset>0x258</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG_WDT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG_LACT_LEVEL_INT_MAP</name>
<description>DPORT_APP_TG_LACT_LEVEL_INT_MAP</description>
<addressOffset>0x25c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG_LACT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG1_T0_LEVEL_INT_MAP</name>
<description>DPORT_APP_TG1_T0_LEVEL_INT_MAP</description>
<addressOffset>0x260</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG1_T0_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG1_T1_LEVEL_INT_MAP</name>
<description>DPORT_APP_TG1_T1_LEVEL_INT_MAP</description>
<addressOffset>0x264</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG1_T1_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG1_WDT_LEVEL_INT_MAP</name>
<description>DPORT_APP_TG1_WDT_LEVEL_INT_MAP</description>
<addressOffset>0x268</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG1_WDT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG1_LACT_LEVEL_INT_MAP</name>
<description>DPORT_APP_TG1_LACT_LEVEL_INT_MAP</description>
<addressOffset>0x26c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG1_LACT_LEVEL_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_GPIO_INTERRUPT_MAP</name>
<description>DPORT_APP_GPIO_INTERRUPT_MAP</description>
<addressOffset>0x270</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_GPIO_INTERRUPT_APP_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_GPIO_INTERRUPT_NMI_MAP</name>
<description>DPORT_APP_GPIO_INTERRUPT_NMI_MAP</description>
<addressOffset>0x274</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_GPIO_INTERRUPT_APP_NMI_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_INTR_FROM_CPU_0_MAP</name>
<description>DPORT_APP_CPU_INTR_FROM_CPU_0_MAP</description>
<addressOffset>0x278</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CPU_INTR_FROM_CPU_0_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_INTR_FROM_CPU_1_MAP</name>
<description>DPORT_APP_CPU_INTR_FROM_CPU_1_MAP</description>
<addressOffset>0x27c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CPU_INTR_FROM_CPU_1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_INTR_FROM_CPU_2_MAP</name>
<description>DPORT_APP_CPU_INTR_FROM_CPU_2_MAP</description>
<addressOffset>0x280</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CPU_INTR_FROM_CPU_2_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_INTR_FROM_CPU_3_MAP</name>
<description>DPORT_APP_CPU_INTR_FROM_CPU_3_MAP</description>
<addressOffset>0x284</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CPU_INTR_FROM_CPU_3_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SPI_INTR_0_MAP</name>
<description>DPORT_APP_SPI_INTR_0_MAP</description>
<addressOffset>0x288</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SPI_INTR_0_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SPI_INTR_1_MAP</name>
<description>DPORT_APP_SPI_INTR_1_MAP</description>
<addressOffset>0x28c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SPI_INTR_1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SPI_INTR_2_MAP</name>
<description>DPORT_APP_SPI_INTR_2_MAP</description>
<addressOffset>0x290</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SPI_INTR_2_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SPI_INTR_3_MAP</name>
<description>DPORT_APP_SPI_INTR_3_MAP</description>
<addressOffset>0x294</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SPI_INTR_3_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_I2S0_INT_MAP</name>
<description>DPORT_APP_I2S0_INT_MAP</description>
<addressOffset>0x298</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_I2S0_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_I2S1_INT_MAP</name>
<description>DPORT_APP_I2S1_INT_MAP</description>
<addressOffset>0x29c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_I2S1_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_UART_INTR_MAP</name>
<description>DPORT_APP_UART_INTR_MAP</description>
<addressOffset>0x2a0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_UART_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_UART1_INTR_MAP</name>
<description>DPORT_APP_UART1_INTR_MAP</description>
<addressOffset>0x2a4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_UART1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_UART2_INTR_MAP</name>
<description>DPORT_APP_UART2_INTR_MAP</description>
<addressOffset>0x2a8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_UART2_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SDIO_HOST_INTERRUPT_MAP</name>
<description>DPORT_APP_SDIO_HOST_INTERRUPT_MAP</description>
<addressOffset>0x2ac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SDIO_HOST_INTERRUPT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_EMAC_INT_MAP</name>
<description>DPORT_APP_EMAC_INT_MAP</description>
<addressOffset>0x2b0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_EMAC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_PWM0_INTR_MAP</name>
<description>DPORT_APP_PWM0_INTR_MAP</description>
<addressOffset>0x2b4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_PWM0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_PWM1_INTR_MAP</name>
<description>DPORT_APP_PWM1_INTR_MAP</description>
<addressOffset>0x2b8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_PWM1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_PWM2_INTR_MAP</name>
<description>DPORT_APP_PWM2_INTR_MAP</description>
<addressOffset>0x2bc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_PWM2_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_PWM3_INTR_MAP</name>
<description>DPORT_APP_PWM3_INTR_MAP</description>
<addressOffset>0x2c0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_PWM3_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_LEDC_INT_MAP</name>
<description>DPORT_APP_LEDC_INT_MAP</description>
<addressOffset>0x2c4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_LEDC_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_EFUSE_INT_MAP</name>
<description>DPORT_APP_EFUSE_INT_MAP</description>
<addressOffset>0x2c8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_EFUSE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CAN_INT_MAP</name>
<description>DPORT_APP_CAN_INT_MAP</description>
<addressOffset>0x2cc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CAN_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_RTC_CORE_INTR_MAP</name>
<description>DPORT_APP_RTC_CORE_INTR_MAP</description>
<addressOffset>0x2d0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_RTC_CORE_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_RMT_INTR_MAP</name>
<description>DPORT_APP_RMT_INTR_MAP</description>
<addressOffset>0x2d4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_RMT_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_PCNT_INTR_MAP</name>
<description>DPORT_APP_PCNT_INTR_MAP</description>
<addressOffset>0x2d8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_PCNT_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_I2C_EXT0_INTR_MAP</name>
<description>DPORT_APP_I2C_EXT0_INTR_MAP</description>
<addressOffset>0x2dc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_I2C_EXT0_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_I2C_EXT1_INTR_MAP</name>
<description>DPORT_APP_I2C_EXT1_INTR_MAP</description>
<addressOffset>0x2e0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_I2C_EXT1_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_RSA_INTR_MAP</name>
<description>DPORT_APP_RSA_INTR_MAP</description>
<addressOffset>0x2e4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_RSA_INTR_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SPI1_DMA_INT_MAP</name>
<description>DPORT_APP_SPI1_DMA_INT_MAP</description>
<addressOffset>0x2e8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SPI1_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SPI2_DMA_INT_MAP</name>
<description>DPORT_APP_SPI2_DMA_INT_MAP</description>
<addressOffset>0x2ec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SPI2_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_SPI3_DMA_INT_MAP</name>
<description>DPORT_APP_SPI3_DMA_INT_MAP</description>
<addressOffset>0x2f0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_SPI3_DMA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_WDG_INT_MAP</name>
<description>DPORT_APP_WDG_INT_MAP</description>
<addressOffset>0x2f4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_WDG_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TIMER_INT1_MAP</name>
<description>DPORT_APP_TIMER_INT1_MAP</description>
<addressOffset>0x2f8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TIMER_INT1_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TIMER_INT2_MAP</name>
<description>DPORT_APP_TIMER_INT2_MAP</description>
<addressOffset>0x2fc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TIMER_INT2_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG_T0_EDGE_INT_MAP</name>
<description>DPORT_APP_TG_T0_EDGE_INT_MAP</description>
<addressOffset>0x300</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG_T0_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG_T1_EDGE_INT_MAP</name>
<description>DPORT_APP_TG_T1_EDGE_INT_MAP</description>
<addressOffset>0x304</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG_T1_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG_WDT_EDGE_INT_MAP</name>
<description>DPORT_APP_TG_WDT_EDGE_INT_MAP</description>
<addressOffset>0x308</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG_WDT_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG_LACT_EDGE_INT_MAP</name>
<description>DPORT_APP_TG_LACT_EDGE_INT_MAP</description>
<addressOffset>0x30c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG_LACT_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG1_T0_EDGE_INT_MAP</name>
<description>DPORT_APP_TG1_T0_EDGE_INT_MAP</description>
<addressOffset>0x310</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG1_T0_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG1_T1_EDGE_INT_MAP</name>
<description>DPORT_APP_TG1_T1_EDGE_INT_MAP</description>
<addressOffset>0x314</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG1_T1_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG1_WDT_EDGE_INT_MAP</name>
<description>DPORT_APP_TG1_WDT_EDGE_INT_MAP</description>
<addressOffset>0x318</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG1_WDT_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_TG1_LACT_EDGE_INT_MAP</name>
<description>DPORT_APP_TG1_LACT_EDGE_INT_MAP</description>
<addressOffset>0x31c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_TG1_LACT_EDGE_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_MMU_IA_INT_MAP</name>
<description>DPORT_APP_MMU_IA_INT_MAP</description>
<addressOffset>0x320</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_MMU_IA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_MPU_IA_INT_MAP</name>
<description>DPORT_APP_MPU_IA_INT_MAP</description>
<addressOffset>0x324</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_MPU_IA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CACHE_IA_INT_MAP</name>
<description>DPORT_APP_CACHE_IA_INT_MAP</description>
<addressOffset>0x328</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_IA_INT_MAP</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_UART</name>
<description>DPORT_AHBLITE_MPU_TABLE_UART</description>
<addressOffset>0x32c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UART_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_SPI1</name>
<description>DPORT_AHBLITE_MPU_TABLE_SPI1</description>
<addressOffset>0x330</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPI1_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_SPI0</name>
<description>DPORT_AHBLITE_MPU_TABLE_SPI0</description>
<addressOffset>0x334</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPI0_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_GPIO</name>
<description>DPORT_AHBLITE_MPU_TABLE_GPIO</description>
<addressOffset>0x338</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GPIO_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_FE2</name>
<description>DPORT_AHBLITE_MPU_TABLE_FE2</description>
<addressOffset>0x33c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FE2_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_FE</name>
<description>DPORT_AHBLITE_MPU_TABLE_FE</description>
<addressOffset>0x340</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FE_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_TIMER</name>
<description>DPORT_AHBLITE_MPU_TABLE_TIMER</description>
<addressOffset>0x344</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_RTC</name>
<description>DPORT_AHBLITE_MPU_TABLE_RTC</description>
<addressOffset>0x348</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RTC_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_IO_MUX</name>
<description>DPORT_AHBLITE_MPU_TABLE_IO_MUX</description>
<addressOffset>0x34c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IOMUX_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_WDG</name>
<description>DPORT_AHBLITE_MPU_TABLE_WDG</description>
<addressOffset>0x350</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDG_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_HINF</name>
<description>DPORT_AHBLITE_MPU_TABLE_HINF</description>
<addressOffset>0x354</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HINF_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_UHCI1</name>
<description>DPORT_AHBLITE_MPU_TABLE_UHCI1</description>
<addressOffset>0x358</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UHCI1_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_MISC</name>
<description>DPORT_AHBLITE_MPU_TABLE_MISC</description>
<addressOffset>0x35c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MISC_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_I2C</name>
<description>DPORT_AHBLITE_MPU_TABLE_I2C</description>
<addressOffset>0x360</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2C_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_I2S0</name>
<description>DPORT_AHBLITE_MPU_TABLE_I2S0</description>
<addressOffset>0x364</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2S0_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_UART1</name>
<description>DPORT_AHBLITE_MPU_TABLE_UART1</description>
<addressOffset>0x368</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UART1_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_BT</name>
<description>DPORT_AHBLITE_MPU_TABLE_BT</description>
<addressOffset>0x36c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BT_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_BT_BUFFER</name>
<description>DPORT_AHBLITE_MPU_TABLE_BT_BUFFER</description>
<addressOffset>0x370</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BTBUFFER_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_I2C_EXT0</name>
<description>DPORT_AHBLITE_MPU_TABLE_I2C_EXT0</description>
<addressOffset>0x374</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2CEXT0_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_UHCI0</name>
<description>DPORT_AHBLITE_MPU_TABLE_UHCI0</description>
<addressOffset>0x378</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UHCI0_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_SLCHOST</name>
<description>DPORT_AHBLITE_MPU_TABLE_SLCHOST</description>
<addressOffset>0x37c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLCHOST_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_RMT</name>
<description>DPORT_AHBLITE_MPU_TABLE_RMT</description>
<addressOffset>0x380</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RMT_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_PCNT</name>
<description>DPORT_AHBLITE_MPU_TABLE_PCNT</description>
<addressOffset>0x384</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PCNT_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_SLC</name>
<description>DPORT_AHBLITE_MPU_TABLE_SLC</description>
<addressOffset>0x388</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLC_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_LEDC</name>
<description>DPORT_AHBLITE_MPU_TABLE_LEDC</description>
<addressOffset>0x38c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LEDC_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_EFUSE</name>
<description>DPORT_AHBLITE_MPU_TABLE_EFUSE</description>
<addressOffset>0x390</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EFUSE_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_SPI_ENCRYPT</name>
<description>DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT</description>
<addressOffset>0x394</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPI_ENCRYPY_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_BB</name>
<description>DPORT_AHBLITE_MPU_TABLE_BB</description>
<addressOffset>0x398</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BB_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_PWM0</name>
<description>DPORT_AHBLITE_MPU_TABLE_PWM0</description>
<addressOffset>0x39c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWM0_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_TIMERGROUP</name>
<description>DPORT_AHBLITE_MPU_TABLE_TIMERGROUP</description>
<addressOffset>0x3a0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMERGROUP_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_TIMERGROUP1</name>
<description>DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1</description>
<addressOffset>0x3a4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMERGROUP1_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_SPI2</name>
<description>DPORT_AHBLITE_MPU_TABLE_SPI2</description>
<addressOffset>0x3a8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPI2_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_SPI3</name>
<description>DPORT_AHBLITE_MPU_TABLE_SPI3</description>
<addressOffset>0x3ac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPI3_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_APB_CTRL</name>
<description>DPORT_AHBLITE_MPU_TABLE_APB_CTRL</description>
<addressOffset>0x3b0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APBCTRL_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_I2C_EXT1</name>
<description>DPORT_AHBLITE_MPU_TABLE_I2C_EXT1</description>
<addressOffset>0x3b4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2CEXT1_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_SDIO_HOST</name>
<description>DPORT_AHBLITE_MPU_TABLE_SDIO_HOST</description>
<addressOffset>0x3b8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDIOHOST_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_EMAC</name>
<description>DPORT_AHBLITE_MPU_TABLE_EMAC</description>
<addressOffset>0x3bc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EMAC_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_CAN</name>
<description>DPORT_AHBLITE_MPU_TABLE_CAN</description>
<addressOffset>0x3c0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAN_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_PWM1</name>
<description>DPORT_AHBLITE_MPU_TABLE_PWM1</description>
<addressOffset>0x3c4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWM1_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_I2S1</name>
<description>DPORT_AHBLITE_MPU_TABLE_I2S1</description>
<addressOffset>0x3c8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2S1_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_UART2</name>
<description>DPORT_AHBLITE_MPU_TABLE_UART2</description>
<addressOffset>0x3cc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>UART2_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_PWM2</name>
<description>DPORT_AHBLITE_MPU_TABLE_PWM2</description>
<addressOffset>0x3d0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWM2_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_PWM3</name>
<description>DPORT_AHBLITE_MPU_TABLE_PWM3</description>
<addressOffset>0x3d4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWM3_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_RWBT</name>
<description>DPORT_AHBLITE_MPU_TABLE_RWBT</description>
<addressOffset>0x3d8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RWBT_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_BTMAC</name>
<description>DPORT_AHBLITE_MPU_TABLE_BTMAC</description>
<addressOffset>0x3dc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>BTMAC_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_WIFIMAC</name>
<description>DPORT_AHBLITE_MPU_TABLE_WIFIMAC</description>
<addressOffset>0x3e0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WIFIMAC_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHBLITE_MPU_TABLE_PWR</name>
<description>DPORT_AHBLITE_MPU_TABLE_PWR</description>
<addressOffset>0x3e4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PWR_ACCESS_GRANT_CONFIG</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>MEM_ACCESS_DBUG0</name>
<description>DPORT_MEM_ACCESS_DBUG0</description>
<addressOffset>0x3e8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTERNAL_SRAM_MMU_MULTI_HIT</name>
<bitOffset>26</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>INTERNAL_SRAM_IA</name>
<bitOffset>14</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>INTERNAL_SRAM_MMU_AD</name>
<bitOffset>10</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SHARE_ROM_IA</name>
<bitOffset>6</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SHARE_ROM_MPU_AD</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>APP_ROM_IA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_ROM_MPU_AD</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_ROM_IA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_ROM_MPU_AD</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MEM_ACCESS_DBUG1</name>
<description>DPORT_MEM_ACCESS_DBUG1</description>
<addressOffset>0x3ec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHBLITE_IA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBLITE_ACCESS_DENY</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHB_ACCESS_DENY</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PIDGEN_IA</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>ARB_IA</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>INTERNAL_SRAM_MMU_MISS</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG0</name>
<description>DPORT_PRO_DCACHE_DBUG0</description>
<addressOffset>0x3f0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_RX_END</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_SLAVE_WDATA_V</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_SLAVE_WR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_TX_END</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_WR_BAK_TO_READ</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CACHE_STATE</name>
<bitOffset>7</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>PRO_CACHE_IA</name>
<bitOffset>1</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>PRO_CACHE_MMU_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG1</name>
<description>DPORT_PRO_DCACHE_DBUG1</description>
<addressOffset>0x3f4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CTAG_RAM_RDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG2</name>
<description>DPORT_PRO_DCACHE_DBUG2</description>
<addressOffset>0x3f8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CACHE_VADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>27</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG3</name>
<description>DPORT_PRO_DCACHE_DBUG3</description>
<addressOffset>0x3fc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CACHE_IRAM0_PID_ERROR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CPU_DISABLED_CACHE_IA</name>
<bitOffset>9</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG4</name>
<description>DPORT_PRO_DCACHE_DBUG4</description>
<addressOffset>0x400</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_DRAM1ADDR0_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG5</name>
<description>DPORT_PRO_DCACHE_DBUG5</description>
<addressOffset>0x404</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_DROM0ADDR0_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG6</name>
<description>DPORT_PRO_DCACHE_DBUG6</description>
<addressOffset>0x408</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_IRAM0ADDR_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG7</name>
<description>DPORT_PRO_DCACHE_DBUG7</description>
<addressOffset>0x40c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_IRAM1ADDR_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG8</name>
<description>DPORT_PRO_DCACHE_DBUG8</description>
<addressOffset>0x410</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_IROM0ADDR_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_DCACHE_DBUG9</name>
<description>DPORT_PRO_DCACHE_DBUG9</description>
<addressOffset>0x414</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_OPSDRAMADDR_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG0</name>
<description>DPORT_APP_DCACHE_DBUG0</description>
<addressOffset>0x418</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_RX_END</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_SLAVE_WDATA_V</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_SLAVE_WR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_TX_END</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_WR_BAK_TO_READ</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CACHE_STATE</name>
<bitOffset>7</bitOffset>
<bitWidth>12</bitWidth>
</field>
<field>
<name>APP_CACHE_IA</name>
<bitOffset>1</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>APP_CACHE_MMU_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG1</name>
<description>DPORT_APP_DCACHE_DBUG1</description>
<addressOffset>0x41c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CTAG_RAM_RDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG2</name>
<description>DPORT_APP_DCACHE_DBUG2</description>
<addressOffset>0x420</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_VADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>27</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG3</name>
<description>DPORT_APP_DCACHE_DBUG3</description>
<addressOffset>0x424</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CACHE_IRAM0_PID_ERROR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CPU_DISABLED_CACHE_IA</name>
<bitOffset>9</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG4</name>
<description>DPORT_APP_DCACHE_DBUG4</description>
<addressOffset>0x428</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_DRAM1ADDR0_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG5</name>
<description>DPORT_APP_DCACHE_DBUG5</description>
<addressOffset>0x42c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_DROM0ADDR0_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG6</name>
<description>DPORT_APP_DCACHE_DBUG6</description>
<addressOffset>0x430</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_IRAM0ADDR_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG7</name>
<description>DPORT_APP_DCACHE_DBUG7</description>
<addressOffset>0x434</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_IRAM1ADDR_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG8</name>
<description>DPORT_APP_DCACHE_DBUG8</description>
<addressOffset>0x438</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_IROM0ADDR_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_DCACHE_DBUG9</name>
<description>DPORT_APP_DCACHE_DBUG9</description>
<addressOffset>0x43c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_OPSDRAMADDR_IA</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_CTRL</name>
<description>DPORT_PRO_CPU_RECORD_CTRL</description>
<addressOffset>0x440</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CPU_PDEBUG_ENABLE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CPU_RECORD_DISABLE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRO_CPU_RECORD_ENABLE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_STATUS</name>
<description>DPORT_PRO_CPU_RECORD_STATUS</description>
<addressOffset>0x444</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_CPU_RECORDING</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_PID</name>
<description>DPORT_PRO_CPU_RECORD_PID</description>
<addressOffset>0x448</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_PRO_PID</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_PDEBUGINST</name>
<description>DPORT_PRO_CPU_RECORD_PDEBUGINST</description>
<addressOffset>0x44c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_PRO_PDEBUGINST</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_PDEBUGSTATUS</name>
<description>DPORT_PRO_CPU_RECORD_PDEBUGSTATUS</description>
<addressOffset>0x450</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_PRO_PDEBUGSTATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_PDEBUGDATA</name>
<description>DPORT_PRO_CPU_RECORD_PDEBUGDATA</description>
<addressOffset>0x454</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_PRO_PDEBUGDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_PDEBUGPC</name>
<description>DPORT_PRO_CPU_RECORD_PDEBUGPC</description>
<addressOffset>0x458</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_PRO_PDEBUGPC</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_PDEBUGLS0STAT</name>
<description>DPORT_PRO_CPU_RECORD_PDEBUGLS0STAT</description>
<addressOffset>0x45c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_PRO_PDEBUGLS0STAT</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_PDEBUGLS0ADDR</name>
<description>DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR</description>
<addressOffset>0x460</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_PRO_PDEBUGLS0ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_CPU_RECORD_PDEBUGLS0DATA</name>
<description>DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA</description>
<addressOffset>0x464</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_PRO_PDEBUGLS0DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_CTRL</name>
<description>DPORT_APP_CPU_RECORD_CTRL</description>
<addressOffset>0x468</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CPU_PDEBUG_ENABLE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CPU_RECORD_DISABLE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>APP_CPU_RECORD_ENABLE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_STATUS</name>
<description>DPORT_APP_CPU_RECORD_STATUS</description>
<addressOffset>0x46c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_CPU_RECORDING</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_PID</name>
<description>DPORT_APP_CPU_RECORD_PID</description>
<addressOffset>0x470</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_APP_PID</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_PDEBUGINST</name>
<description>DPORT_APP_CPU_RECORD_PDEBUGINST</description>
<addressOffset>0x474</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_APP_PDEBUGINST</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_PDEBUGSTATUS</name>
<description>DPORT_APP_CPU_RECORD_PDEBUGSTATUS</description>
<addressOffset>0x478</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_APP_PDEBUGSTATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_PDEBUGDATA</name>
<description>DPORT_APP_CPU_RECORD_PDEBUGDATA</description>
<addressOffset>0x47c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_APP_PDEBUGDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_PDEBUGPC</name>
<description>DPORT_APP_CPU_RECORD_PDEBUGPC</description>
<addressOffset>0x480</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_APP_PDEBUGPC</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_PDEBUGLS0STAT</name>
<description>DPORT_APP_CPU_RECORD_PDEBUGLS0STAT</description>
<addressOffset>0x484</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_APP_PDEBUGLS0STAT</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_PDEBUGLS0ADDR</name>
<description>DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR</description>
<addressOffset>0x488</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_APP_PDEBUGLS0ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_CPU_RECORD_PDEBUGLS0DATA</name>
<description>DPORT_APP_CPU_RECORD_PDEBUGLS0DATA</description>
<addressOffset>0x48c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RECORD_APP_PDEBUGLS0DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RSA_PD_CTRL</name>
<description>DPORT_RSA_PD_CTRL</description>
<addressOffset>0x490</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RSA_PD</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>ROM_MPU_TABLE0</name>
<description>DPORT_ROM_MPU_TABLE0</description>
<addressOffset>0x494</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ROM_MPU_TABLE0</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ROM_MPU_TABLE1</name>
<description>DPORT_ROM_MPU_TABLE1</description>
<addressOffset>0x498</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ROM_MPU_TABLE1</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ROM_MPU_TABLE2</name>
<description>DPORT_ROM_MPU_TABLE2</description>
<addressOffset>0x49c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ROM_MPU_TABLE2</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ROM_MPU_TABLE3</name>
<description>DPORT_ROM_MPU_TABLE3</description>
<addressOffset>0x4a0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ROM_MPU_TABLE3</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE0</name>
<description>DPORT_SHROM_MPU_TABLE0</description>
<addressOffset>0x4a4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE0</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE1</name>
<description>DPORT_SHROM_MPU_TABLE1</description>
<addressOffset>0x4a8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE1</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE2</name>
<description>DPORT_SHROM_MPU_TABLE2</description>
<addressOffset>0x4ac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE2</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE3</name>
<description>DPORT_SHROM_MPU_TABLE3</description>
<addressOffset>0x4b0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE3</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE4</name>
<description>DPORT_SHROM_MPU_TABLE4</description>
<addressOffset>0x4b4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE4</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE5</name>
<description>DPORT_SHROM_MPU_TABLE5</description>
<addressOffset>0x4b8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE5</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE6</name>
<description>DPORT_SHROM_MPU_TABLE6</description>
<addressOffset>0x4bc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE6</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE7</name>
<description>DPORT_SHROM_MPU_TABLE7</description>
<addressOffset>0x4c0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE7</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE8</name>
<description>DPORT_SHROM_MPU_TABLE8</description>
<addressOffset>0x4c4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE8</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE9</name>
<description>DPORT_SHROM_MPU_TABLE9</description>
<addressOffset>0x4c8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE9</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE10</name>
<description>DPORT_SHROM_MPU_TABLE10</description>
<addressOffset>0x4cc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE10</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE11</name>
<description>DPORT_SHROM_MPU_TABLE11</description>
<addressOffset>0x4d0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE11</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE12</name>
<description>DPORT_SHROM_MPU_TABLE12</description>
<addressOffset>0x4d4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE12</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE13</name>
<description>DPORT_SHROM_MPU_TABLE13</description>
<addressOffset>0x4d8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE13</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE14</name>
<description>DPORT_SHROM_MPU_TABLE14</description>
<addressOffset>0x4dc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE14</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE15</name>
<description>DPORT_SHROM_MPU_TABLE15</description>
<addressOffset>0x4e0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE15</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE16</name>
<description>DPORT_SHROM_MPU_TABLE16</description>
<addressOffset>0x4e4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE16</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE17</name>
<description>DPORT_SHROM_MPU_TABLE17</description>
<addressOffset>0x4e8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE17</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE18</name>
<description>DPORT_SHROM_MPU_TABLE18</description>
<addressOffset>0x4ec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE18</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE19</name>
<description>DPORT_SHROM_MPU_TABLE19</description>
<addressOffset>0x4f0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE19</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE20</name>
<description>DPORT_SHROM_MPU_TABLE20</description>
<addressOffset>0x4f4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE20</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE21</name>
<description>DPORT_SHROM_MPU_TABLE21</description>
<addressOffset>0x4f8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE21</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE22</name>
<description>DPORT_SHROM_MPU_TABLE22</description>
<addressOffset>0x4fc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE22</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>SHROM_MPU_TABLE23</name>
<description>DPORT_SHROM_MPU_TABLE23</description>
<addressOffset>0x500</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SHROM_MPU_TABLE23</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE0</name>
<description>DPORT_IMMU_TABLE0</description>
<addressOffset>0x504</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE0</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE1</name>
<description>DPORT_IMMU_TABLE1</description>
<addressOffset>0x508</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE1</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE2</name>
<description>DPORT_IMMU_TABLE2</description>
<addressOffset>0x50c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE2</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE3</name>
<description>DPORT_IMMU_TABLE3</description>
<addressOffset>0x510</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE3</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE4</name>
<description>DPORT_IMMU_TABLE4</description>
<addressOffset>0x514</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE4</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE5</name>
<description>DPORT_IMMU_TABLE5</description>
<addressOffset>0x518</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE5</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE6</name>
<description>DPORT_IMMU_TABLE6</description>
<addressOffset>0x51c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE6</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE7</name>
<description>DPORT_IMMU_TABLE7</description>
<addressOffset>0x520</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE7</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE8</name>
<description>DPORT_IMMU_TABLE8</description>
<addressOffset>0x524</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE8</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE9</name>
<description>DPORT_IMMU_TABLE9</description>
<addressOffset>0x528</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE9</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE10</name>
<description>DPORT_IMMU_TABLE10</description>
<addressOffset>0x52c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE10</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE11</name>
<description>DPORT_IMMU_TABLE11</description>
<addressOffset>0x530</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE11</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE12</name>
<description>DPORT_IMMU_TABLE12</description>
<addressOffset>0x534</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE12</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE13</name>
<description>DPORT_IMMU_TABLE13</description>
<addressOffset>0x538</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE13</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE14</name>
<description>DPORT_IMMU_TABLE14</description>
<addressOffset>0x53c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE14</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>IMMU_TABLE15</name>
<description>DPORT_IMMU_TABLE15</description>
<addressOffset>0x540</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IMMU_TABLE15</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE0</name>
<description>DPORT_DMMU_TABLE0</description>
<addressOffset>0x544</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE0</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE1</name>
<description>DPORT_DMMU_TABLE1</description>
<addressOffset>0x548</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE1</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE2</name>
<description>DPORT_DMMU_TABLE2</description>
<addressOffset>0x54c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE2</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE3</name>
<description>DPORT_DMMU_TABLE3</description>
<addressOffset>0x550</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE3</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE4</name>
<description>DPORT_DMMU_TABLE4</description>
<addressOffset>0x554</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE4</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE5</name>
<description>DPORT_DMMU_TABLE5</description>
<addressOffset>0x558</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE5</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE6</name>
<description>DPORT_DMMU_TABLE6</description>
<addressOffset>0x55c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE6</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE7</name>
<description>DPORT_DMMU_TABLE7</description>
<addressOffset>0x560</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE7</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE8</name>
<description>DPORT_DMMU_TABLE8</description>
<addressOffset>0x564</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE8</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE9</name>
<description>DPORT_DMMU_TABLE9</description>
<addressOffset>0x568</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE9</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE10</name>
<description>DPORT_DMMU_TABLE10</description>
<addressOffset>0x56c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE10</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE11</name>
<description>DPORT_DMMU_TABLE11</description>
<addressOffset>0x570</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE11</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE12</name>
<description>DPORT_DMMU_TABLE12</description>
<addressOffset>0x574</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE12</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE13</name>
<description>DPORT_DMMU_TABLE13</description>
<addressOffset>0x578</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE13</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE14</name>
<description>DPORT_DMMU_TABLE14</description>
<addressOffset>0x57c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE14</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>DMMU_TABLE15</name>
<description>DPORT_DMMU_TABLE15</description>
<addressOffset>0x580</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DMMU_TABLE15</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_INTRUSION_CTRL</name>
<description>DPORT_PRO_INTRUSION_CTRL</description>
<addressOffset>0x584</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_INTRUSION_RECORD_RESET_N</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_INTRUSION_STATUS</name>
<description>DPORT_PRO_INTRUSION_STATUS</description>
<addressOffset>0x588</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_INTRUSION_RECORD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_INTRUSION_CTRL</name>
<description>DPORT_APP_INTRUSION_CTRL</description>
<addressOffset>0x58c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_INTRUSION_RECORD_RESET_N</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_INTRUSION_STATUS</name>
<description>DPORT_APP_INTRUSION_STATUS</description>
<addressOffset>0x590</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_INTRUSION_RECORD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>FRONT_END_MEM_PD</name>
<description>DPORT_FRONT_END_MEM_PD</description>
<addressOffset>0x594</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PBUS_MEM_FORCE_PD</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PBUS_MEM_FORCE_PU</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AGC_MEM_FORCE_PD</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AGC_MEM_FORCE_PU</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MMU_IA_INT_EN</name>
<description>DPORT_MMU_IA_INT_EN</description>
<addressOffset>0x598</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MMU_IA_INT_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>MPU_IA_INT_EN</name>
<description>DPORT_MPU_IA_INT_EN</description>
<addressOffset>0x59c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MPU_IA_INT_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>17</bitWidth>
</field>
</fields>
</register>
<register>
<name>CACHE_IA_INT_EN</name>
<description>DPORT_CACHE_IA_INT_EN</description>
<addressOffset>0x5a0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CACHE_IA_INT_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_PRO_OPPOSITE</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_PRO_DRAM1</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_PRO_IROM0</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_PRO_IRAM1</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_PRO_IRAM0</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_PRO_DROM0</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_APP_OPPOSITE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_APP_IROM0</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_APP_IRAM1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_APP_IRAM0</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CACHE_IA_INT_APP_DROM0</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SECURE_BOOT_CTRL</name>
<description>DPORT_SECURE_BOOT_CTRL</description>
<addressOffset>0x5a4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SW_BOOTLOADER_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SPI_DMA_CHAN_SEL</name>
<description>DPORT_SPI_DMA_CHAN_SEL</description>
<addressOffset>0x5a8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPI3_DMA_CHAN_SEL</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SPI2_DMA_CHAN_SEL</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SPI1_DMA_CHAN_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_VECBASE_CTRL</name>
<description>DPORT_PRO_VECBASE_CTRL</description>
<addressOffset>0x5ac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_OUT_VECBASE_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>PRO_VECBASE_SET</name>
<description>DPORT_PRO_VECBASE_SET</description>
<addressOffset>0x5b0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRO_OUT_VECBASE_REG</name>
<bitOffset>0</bitOffset>
<bitWidth>22</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_VECBASE_CTRL</name>
<description>DPORT_APP_VECBASE_CTRL</description>
<addressOffset>0x5b4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_OUT_VECBASE_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>APP_VECBASE_SET</name>
<description>DPORT_APP_VECBASE_SET</description>
<addressOffset>0x5b8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APP_OUT_VECBASE_REG</name>
<bitOffset>0</bitOffset>
<bitWidth>22</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>DPORT_DATE</description>
<addressOffset>0xffc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI">
<name>SPI3</name>
<baseAddress>0x3ff65000</baseAddress>
</peripheral>
<peripheral derivedFrom="UART">
<name>UART2</name>
<baseAddress>0x3ff6e000</baseAddress>
</peripheral>
<peripheral>
<name>TIMG</name>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000580</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>TG0_T0_LEVEL_INTR</name>
<description>interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission</description>
<value>14</value>
</interrupt>
<interrupt>
<name>TG0_T1_LEVEL_INTR</name>
<description>interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission</description>
<value>15</value>
</interrupt>
<interrupt>
<name>TG0_WDT_LEVEL_INTR</name>
<description>interrupt of TIMER_GROUP0, WATCHDOG, level</description>
<value>16</value>
</interrupt>
<interrupt>
<name>TG0_LACT_LEVEL_INTR</name>
<description>interrupt of TIMER_GROUP0, LACT, level</description>
<value>17</value>
</interrupt>
<interrupt>
<name>TG1_T0_LEVEL_INTR</name>
<description>interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission</description>
<value>18</value>
</interrupt>
<interrupt>
<name>TG1_T1_LEVEL_INTR</name>
<description>interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission</description>
<value>19</value>
</interrupt>
<interrupt>
<name>TG1_WDT_LEVEL_INTR</name>
<description>interrupt of TIMER_GROUP1, WATCHDOG, level</description>
<value>20</value>
</interrupt>
<interrupt>
<name>TG1_LACT_LEVEL_INTR</name>
<description>interrupt of TIMER_GROUP1, LACT, level</description>
<value>21</value>
</interrupt>
<interrupt>
<name>TG0_T0_EDGE_INTR</name>
<description>interrupt of TIMER_GROUP0, TIMER0, EDGE</description>
<value>58</value>
</interrupt>
<interrupt>
<name>TG0_T1_EDGE_INTR</name>
<description>interrupt of TIMER_GROUP0, TIMER1, EDGE</description>
<value>59</value>
</interrupt>
<interrupt>
<name>TG0_WDT_EDGE_INTR</name>
<description>interrupt of TIMER_GROUP0, WATCH DOG, EDGE</description>
<value>60</value>
</interrupt>
<interrupt>
<name>TG0_LACT_EDGE_INTR</name>
<description>interrupt of TIMER_GROUP0, LACT, EDGE</description>
<value>61</value>
</interrupt>
<interrupt>
<name>TG1_T0_EDGE_INTR</name>
<description>interrupt of TIMER_GROUP1, TIMER0, EDGE</description>
<value>62</value>
</interrupt>
<interrupt>
<name>TG1_T1_EDGE_INTR</name>
<description>interrupt of TIMER_GROUP1, TIMER1, EDGE</description>
<value>63</value>
</interrupt>
<interrupt>
<name>TG1_WDT_EDGE_INTR</name>
<description>interrupt of TIMER_GROUP1, WATCHDOG, EDGE</description>
<value>64</value>
</interrupt>
<interrupt>
<name>TG1_LACT_EDGE_INTR</name>
<description>interrupt of TIMER_GROUP0, LACT, EDGE</description>
<value>65</value>
</interrupt>
<registers>
<register>
<name>T0CONFIG</name>
<description>TIMG_T0CONFIG</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_INCREASE</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_AUTORELOAD</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_DIVIDER</name>
<bitOffset>13</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>T0_EDGE_INT_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_LEVEL_INT_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_ALARM_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>T0LO</name>
<description>TIMG_T0LO</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T0HI</name>
<description>TIMG_T0HI</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T0UPDATE</name>
<description>TIMG_T0UPDATE</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_UPDATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T0ALARMLO</name>
<description>TIMG_T0ALARMLO</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_ALARM_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T0ALARMHI</name>
<description>TIMG_T0ALARMHI</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_ALARM_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T0LOADLO</name>
<description>TIMG_T0LOADLO</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_LOAD_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T0LOADHI</name>
<description>TIMG_T0LOADHI</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_LOAD_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T0LOAD</name>
<description>TIMG_T0LOAD</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T0_LOAD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1CONFIG</name>
<description>TIMG_T1CONFIG</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_INCREASE</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_AUTORELOAD</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_DIVIDER</name>
<bitOffset>13</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>T1_EDGE_INT_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_LEVEL_INT_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_ALARM_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1LO</name>
<description>TIMG_T1LO</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1HI</name>
<description>TIMG_T1HI</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1UPDATE</name>
<description>TIMG_T1UPDATE</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_UPDATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1ALARMLO</name>
<description>TIMG_T1ALARMLO</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_ALARM_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1ALARMHI</name>
<description>TIMG_T1ALARMHI</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_ALARM_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1LOADLO</name>
<description>TIMG_T1LOADLO</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_LOAD_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1LOADHI</name>
<description>TIMG_T1LOADHI</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_LOAD_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>T1LOAD</name>
<description>TIMG_T1LOAD</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1_LOAD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG0</name>
<description>TIMG_WDTCONFIG0</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_STG0</name>
<bitOffset>29</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>WDT_STG0</name>
<usage>read-write</usage>
<enumeratedValue>
<name>Disable</name>
<description>Disabled</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Interrupt</name>
<description>Trigger an interrupt</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>ResetCPU</name>
<description>Reset CPU core</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>ResetSystem</name>
<description>Reset System</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT_STG1</name>
<bitOffset>27</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="WDT_STG0" />
</field>
<field>
<name>WDT_STG2</name>
<bitOffset>25</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="WDT_STG0" />
</field>
<field>
<name>WDT_STG3</name>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues derivedFrom="WDT_STG0" />
</field>
<field>
<name>WDT_EDGE_INT_EN</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_LEVEL_INT_EN</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_CPU_RESET_LENGTH</name>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues>
<name>WDT_CPU_RESET_LENGTH</name>
<usage>read-write</usage>
<enumeratedValue>
<name>T100ns</name>
<description>100ns</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>T200ns</name>
<description>200ns</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>T300ns</name>
<description>300ns</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>T400ns</name>
<description>400ns</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>T500ns</name>
<description>500ns</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>T800ns</name>
<description>800ns</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>T1600ns</name>
<description>1600ns</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>T3200ns</name>
<description>3200ns</description>
<value>7</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>WDT_SYS_RESET_LENGTH</name>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
<enumeratedValues derivedFrom="WDT_CPU_RESET_LENGTH" />
</field>
<field>
<name>WDT_FLASHBOOT_MOD_EN</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG1</name>
<description>TIMG_WDTCONFIG1</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_CLK_PRESCALE</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG2</name>
<description>TIMG_WDTCONFIG2</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_STG0_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG3</name>
<description>TIMG_WDTCONFIG3</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_STG1_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG4</name>
<description>TIMG_WDTCONFIG4</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_STG2_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTCONFIG5</name>
<description>TIMG_WDTCONFIG5</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_STG3_HOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTFEED</name>
<description>TIMG_WDTFEED</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_FEED</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>WDTWPROTECT</name>
<description>TIMG_WDTWPROTECT</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>WDT_WKEY</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTCCALICFG</name>
<description>TIMG_RTCCALICFG</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>START</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MAX</name>
<bitOffset>16</bitOffset>
<bitWidth>15</bitWidth>
</field>
<field>
<name>RDY</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_SEL</name>
<bitOffset>13</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>CLK_SEL</name>
<usage>read-write</usage>
<enumeratedValue>
<name>RTC_MUX</name>
<description>Select RTC slow clock</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>CK8M_D256</name>
<description>Internal 8 MHz RC oscillator, divided by 256</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>XTAL32K</name>
<description>Select XTAL_32K</description>
<value>2</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>START_CYCLING</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>RTCCALICFG1</name>
<description>TIMG_RTCCALICFG1</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>VALUE</name>
<bitOffset>7</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTCONFIG</name>
<description>TIMG_LACTCONFIG</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LACT_INCREASE</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LACT_AUTORELOAD</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LACT_DIVIDER</name>
<bitOffset>13</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>LACT_EDGE_INT_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LACT_LEVEL_INT_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LACT_ALARM_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LACT_LAC_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LACT_CPST_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LACT_RTC_ONLY</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTRTC</name>
<description>TIMG_LACTRTC</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_RTC_STEP_LEN</name>
<bitOffset>6</bitOffset>
<bitWidth>26</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTLO</name>
<description>TIMG_LACTLO</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTHI</name>
<description>TIMG_LACTHI</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTUPDATE</name>
<description>TIMG_LACTUPDATE</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_UPDATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTALARMLO</name>
<description>TIMG_LACTALARMLO</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_ALARM_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTALARMHI</name>
<description>TIMG_LACTALARMHI</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_ALARM_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTLOADLO</name>
<description>TIMG_LACTLOADLO</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_LOAD_LO</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTLOADHI</name>
<description>TIMG_LACTLOADHI</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_LOAD_HI</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LACTLOAD</name>
<description>TIMG_LACTLOAD</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_LOAD</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA_TIMERS</name>
<description>TIMG_INT_ENA_TIMERS</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW_TIMERS</name>
<description>TIMG_INT_RAW_TIMERS</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST_TIMERS</name>
<description>TIMG_INT_ST_TIMERS</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR_TIMERS</name>
<description>TIMG_INT_CLR_TIMERS</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LACT_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>WDT_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T1_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>T0_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>NTIMERS_DATE</name>
<description>TIMG_NTIMERS_DATE</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NTIMERS_DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMGCLK</name>
<description>TIMGCLK</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="MCPWM">
<name>PWM3</name>
<baseAddress>0x3ff70000</baseAddress>
</peripheral>
<peripheral derivedFrom="TIMG">
<name>TIMG0</name>
<baseAddress>0x3ff5f000</baseAddress>
</peripheral>
<peripheral>
<name>SPI_ENCRYPT</name>
<baseAddress>0x3ff5b000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>GPIO_SD</name>
<baseAddress>0x3ff44f00</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000160</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SIGMADELTA0</name>
<description>GPIO_SIGMADELTA0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD0_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD0_IN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA1</name>
<description>GPIO_SIGMADELTA1</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD1_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD1_IN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA2</name>
<description>GPIO_SIGMADELTA2</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD2_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD2_IN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA3</name>
<description>GPIO_SIGMADELTA3</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD3_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD3_IN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA4</name>
<description>GPIO_SIGMADELTA4</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD4_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD4_IN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA5</name>
<description>GPIO_SIGMADELTA5</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD5_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD5_IN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA6</name>
<description>GPIO_SIGMADELTA6</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD6_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD6_IN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA7</name>
<description>GPIO_SIGMADELTA7</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD7_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SD7_IN</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA_CG</name>
<description>GPIO_SIGMADELTA_CG</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD_CLK_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA_MISC</name>
<description>GPIO_SIGMADELTA_MISC</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SPI_SWAP</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SIGMADELTA_VERSION</name>
<description>GPIO_SIGMADELTA_VERSION</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SD_DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI">
<name>SPI0</name>
<baseAddress>0x3ff43000</baseAddress>
</peripheral>
<peripheral>
<name>SDMMC</name>
<baseAddress>0x3ff68000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral derivedFrom="MCPWM">
<name>PWM0</name>
<baseAddress>0x3ff5e000</baseAddress>
</peripheral>
<peripheral derivedFrom="UHCI">
<name>UHCI1</name>
<baseAddress>0x3ff4c000</baseAddress>
</peripheral>
<peripheral>
<name>IO_MUX</name>
<baseAddress>0x3ff49000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>PIN_CTRL</name>
<description>configures clock source and clock output pins</description>
<addressOffset>0</addressOffset>
<size>32</size>
<resetValue>0</resetValue>
<fields>
<field>
<name>PIN_CTRL_CLK3</name>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PIN_CTRL_CLK2</name>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PIN_CTRL_CLK1</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO36</name>
<description>configures IO_MUX for GPIO36</description>
<addressOffset>4</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO37</name>
<description>configures IO_MUX for GPIO37</description>
<addressOffset>8</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO38</name>
<description>configures IO_MUX for GPIO38</description>
<addressOffset>12</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO39</name>
<description>configures IO_MUX for GPIO39</description>
<addressOffset>16</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO34</name>
<description>configures IO_MUX for GPIO34</description>
<addressOffset>20</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO35</name>
<description>configures IO_MUX for GPIO35</description>
<addressOffset>24</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO32</name>
<description>configures IO_MUX for GPIO32</description>
<addressOffset>28</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO33</name>
<description>configures IO_MUX for GPIO33</description>
<addressOffset>32</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO25</name>
<description>configures IO_MUX for GPIO25</description>
<addressOffset>36</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO26</name>
<description>configures IO_MUX for GPIO26</description>
<addressOffset>40</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO27</name>
<description>configures IO_MUX for GPIO27</description>
<addressOffset>44</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MTMS</name>
<description>configures IO_MUX for MTMS</description>
<addressOffset>48</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MTDI</name>
<description>configures IO_MUX for MTDI</description>
<addressOffset>52</addressOffset>
<size>32</size>
<resetValue>2688</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MTCK</name>
<description>configures IO_MUX for MTCK</description>
<addressOffset>56</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MTDO</name>
<description>configures IO_MUX for MTDO</description>
<addressOffset>60</addressOffset>
<size>32</size>
<resetValue>2816</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO2</name>
<description>configures IO_MUX for GPIO2</description>
<addressOffset>64</addressOffset>
<size>32</size>
<resetValue>2688</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO0</name>
<description>configures IO_MUX for GPIO0</description>
<addressOffset>68</addressOffset>
<size>32</size>
<resetValue>2816</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO4</name>
<description>configures IO_MUX for GPIO4</description>
<addressOffset>72</addressOffset>
<size>32</size>
<resetValue>2688</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO16</name>
<description>configures IO_MUX for GPIO16</description>
<addressOffset>76</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO17</name>
<description>configures IO_MUX for GPIO17</description>
<addressOffset>80</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SD_DATA2</name>
<description>configures IO_MUX for SD_DATA2</description>
<addressOffset>84</addressOffset>
<size>32</size>
<resetValue>2816</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SD_DATA3</name>
<description>configures IO_MUX for SD_DATA3</description>
<addressOffset>88</addressOffset>
<size>32</size>
<resetValue>2816</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SD_CMD</name>
<description>configures IO_MUX for SD_CMD</description>
<addressOffset>92</addressOffset>
<size>32</size>
<resetValue>6912</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SD_CLK</name>
<description>configures IO_MUX for SD_CLK</description>
<addressOffset>96</addressOffset>
<size>32</size>
<resetValue>5888</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SD_DATA0</name>
<description>configures IO_MUX for SD_DATA0</description>
<addressOffset>100</addressOffset>
<size>32</size>
<resetValue>6912</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SD_DATA1</name>
<description>configures IO_MUX for SD_DATA1</description>
<addressOffset>104</addressOffset>
<size>32</size>
<resetValue>6912</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO5</name>
<description>configures IO_MUX for GPIO5</description>
<addressOffset>108</addressOffset>
<size>32</size>
<resetValue>2816</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO18</name>
<description>configures IO_MUX for GPIO18</description>
<addressOffset>112</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO19</name>
<description>configures IO_MUX for GPIO19</description>
<addressOffset>116</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO20</name>
<description>configures IO_MUX for GPIO20</description>
<addressOffset>120</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO21</name>
<description>configures IO_MUX for GPIO21</description>
<addressOffset>124</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO22</name>
<description>configures IO_MUX for GPIO22</description>
<addressOffset>128</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>U0RXD</name>
<description>configures IO_MUX for U0RXD</description>
<addressOffset>132</addressOffset>
<size>32</size>
<resetValue>2816</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>U0TXD</name>
<description>configures IO_MUX for U0TXD</description>
<addressOffset>136</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO23</name>
<description>configures IO_MUX for GPIO23</description>
<addressOffset>140</addressOffset>
<size>32</size>
<resetValue>2560</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GPIO24</name>
<description>configures IO_MUX for GPIO24</description>
<addressOffset>144</addressOffset>
<size>32</size>
<resetValue>2048</resetValue>
<fields>
<field>
<name>MCU_SEL</name>
<description>configures IO_MUX function</description>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_DRV</name>
<description>configures drive strength</description>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FUN_IE</name>
<description>configures input enable</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPU</name>
<description>configures pull up</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FUN_WPD</name>
<description>configures pull down</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_DRV</name>
<description>configures drive strength during sleep mode</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>MCU_IE</name>
<description>configures input enable during sleep mode</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPU</name>
<description>configures pull up during sleep mode</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_WPD</name>
<description>configures pull down during sleep mode</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLP_SEL</name>
<description>configures sleep mode selection</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MCU_OE</name>
<description>configures output enable during sleep mode</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>CAN</name>
<baseAddress>0x3ff6b000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>CAN_INTR</name>
<description>interrupt of can, level</description>
<value>45</value>
</interrupt>
<registers />
</peripheral>
<peripheral>
<name>I2S</name>
<baseAddress>0x3ff4f000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x000005a0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>I2S0_INTR</name>
<description>interrupt of I2S0, level</description>
<value>32</value>
</interrupt>
<interrupt>
<name>I2S1_INTR</name>
<description>interrupt of I2S1, level</description>
<value>33</value>
</interrupt>
<registers>
<register>
<name>CONF</name>
<description>I2S_CONF</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIG_LOOPBACK</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_MSB_RIGHT</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_MSB_RIGHT</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_MONO</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_MONO</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_SHORT_SYNC</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_SHORT_SYNC</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_MSB_SHIFT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_MSB_SHIFT</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_RIGHT_FIRST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_RIGHT_FIRST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_SLAVE_MOD</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_SLAVE_MOD</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_START</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_START</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FIFO_RESET</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_FIFO_RESET</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_RESET</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_RESET</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>I2S_INT_RAW</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_TOTAL_EOF_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_EMPTY_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DSCR_ERR_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_ERR_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_HUNG_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_HUNG_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_REMPTY_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_WFULL_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_REMPTY_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_WFULL_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_PUT_DATA_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_TAKE_DATA_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST</name>
<description>I2S_INT_ST</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_TOTAL_EOF_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_EMPTY_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DSCR_ERR_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_ERR_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_HUNG_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_HUNG_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_REMPTY_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_WFULL_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_REMPTY_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_WFULL_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_PUT_DATA_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_TAKE_DATA_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>I2S_INT_ENA</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_TOTAL_EOF_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_EMPTY_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DSCR_ERR_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_ERR_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_HUNG_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_HUNG_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_REMPTY_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_WFULL_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_REMPTY_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_WFULL_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_PUT_DATA_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_TAKE_DATA_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>I2S_INT_CLR</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_TOTAL_EOF_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_EMPTY_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DSCR_ERR_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DSCR_ERR_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DONE_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_ERR_EOF_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_SUC_EOF_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_DONE_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_HUNG_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_HUNG_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_REMPTY_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_WFULL_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_REMPTY_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_WFULL_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PUT_DATA_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TAKE_DATA_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMING</name>
<description>I2S_TIMING</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_BCK_IN_INV</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATA_ENABLE_DELAY</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX_DSYNC_SW</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_DSYNC_SW</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_BCK_OUT_DELAY</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX_WS_OUT_DELAY</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_SD_OUT_DELAY</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_WS_OUT_DELAY</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_BCK_OUT_DELAY</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX_SD_IN_DELAY</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX_WS_IN_DELAY</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX_BCK_IN_DELAY</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_WS_IN_DELAY</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_BCK_IN_DELAY</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>FIFO_CONF</name>
<description>I2S_FIFO_CONF</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_FIFO_MOD_FORCE_EN</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_FIFO_MOD_FORCE_EN</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FIFO_MOD</name>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TX_FIFO_MOD</name>
<bitOffset>13</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>DSCR_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_DATA_NUM</name>
<bitOffset>6</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>RX_DATA_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXEOF_NUM</name>
<description>I2S_RXEOF_NUM</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_EOF_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF_SIGLE_DATA</name>
<description>I2S_CONF_SIGLE_DATA</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SIGLE_DATA</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF_CHAN</name>
<description>I2S_CONF_CHAN</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_CHAN_MOD</name>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_CHAN_MOD</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_LINK</name>
<description>I2S_OUT_LINK</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_PARK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>IN_LINK</name>
<description>I2S_IN_LINK</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_PARK</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_RESTART</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_START</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_STOP</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INLINK_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_EOF_DES_ADDR</name>
<description>I2S_OUT_EOF_DES_ADDR</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>IN_EOF_DES_ADDR</name>
<description>I2S_IN_EOF_DES_ADDR</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IN_SUC_EOF_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUT_EOF_BFR_DES_ADDR</name>
<description>I2S_OUT_EOF_BFR_DES_ADDR</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUT_EOF_BFR_DES_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>AHB_TEST</name>
<description>I2S_AHB_TEST</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AHB_TESTADDR</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>AHB_TESTMODE</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>INLINK_DSCR</name>
<description>I2S_INLINK_DSCR</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>INLINK_DSCR_BF0</name>
<description>I2S_INLINK_DSCR_BF0</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>INLINK_DSCR_BF1</name>
<description>I2S_INLINK_DSCR_BF1</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTLINK_DSCR</name>
<description>I2S_OUTLINK_DSCR</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_DSCR</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTLINK_DSCR_BF0</name>
<description>I2S_OUTLINK_DSCR_BF0</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_DSCR_BF0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTLINK_DSCR_BF1</name>
<description>I2S_OUTLINK_DSCR_BF1</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTLINK_DSCR_BF1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LC_CONF</name>
<description>I2S_LC_CONF</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM_TRANS_EN</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CHECK_OWNER</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_DATA_BURST_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INDSCR_BURST_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTDSCR_BURST_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_EOF_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_NO_RESTART_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_AUTO_WRBACK</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_LOOP_TEST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_LOOP_TEST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBM_RST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>AHBM_FIFO_RST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUT_RST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IN_RST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>OUTFIFO_PUSH</name>
<description>I2S_OUTFIFO_PUSH</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OUTFIFO_PUSH</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OUTFIFO_WDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>9</bitWidth>
</field>
</fields>
</register>
<register>
<name>INFIFO_POP</name>
<description>I2S_INFIFO_POP</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INFIFO_POP</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>INFIFO_RDATA</name>
<bitOffset>0</bitOffset>
<bitWidth>12</bitWidth>
</field>
</fields>
</register>
<register>
<name>LC_STATE0</name>
<description>I2S_LC_STATE0</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LC_STATE0</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LC_STATE1</name>
<description>I2S_LC_STATE1</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LC_STATE1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>LC_HUNG_CONF</name>
<description>I2S_LC_HUNG_CONF</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LC_FIFO_TIMEOUT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LC_FIFO_TIMEOUT_SHIFT</name>
<bitOffset>8</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>LC_FIFO_TIMEOUT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVSD_CONF0</name>
<description>I2S_CVSD_CONF0</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVSD_Y_MIN</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CVSD_Y_MAX</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVSD_CONF1</name>
<description>I2S_CVSD_CONF1</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVSD_SIGMA_MIN</name>
<bitOffset>16</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>CVSD_SIGMA_MAX</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CVSD_CONF2</name>
<description>I2S_CVSD_CONF2</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVSD_H</name>
<bitOffset>16</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CVSD_BETA</name>
<bitOffset>6</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>CVSD_J</name>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CVSD_K</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>PLC_CONF0</name>
<description>I2S_PLC_CONF0</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>N_MIN_ERR</name>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>PACK_LEN_8K</name>
<bitOffset>20</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>MAX_SLIDE_SAMPLE</name>
<bitOffset>12</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SHIFT_RATE</name>
<bitOffset>9</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>N_ERR_SEG</name>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GOOD_PACK_MAX</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>PLC_CONF1</name>
<description>I2S_PLC_CONF1</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLIDE_WIN_LEN</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BAD_OLA_WIN2_PARA</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>BAD_OLA_WIN2_PARA_SHIFT</name>
<bitOffset>12</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BAD_CEF_ATTEN_PARA_SHIFT</name>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>BAD_CEF_ATTEN_PARA</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PLC_CONF2</name>
<description>I2S_PLC_CONF2</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MIN_PERIOD</name>
<bitOffset>2</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>CVSD_SEG_MOD</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>ESCO_CONF0</name>
<description>I2S_ESCO_CONF0</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLC2DMA_EN</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLC_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CVSD_DEC_RESET</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CVSD_DEC_START</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESCO_CVSD_INF_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESCO_CVSD_PACK_LEN_8K</name>
<bitOffset>3</bitOffset>
<bitWidth>5</bitWidth>
</field>
<field>
<name>ESCO_CVSD_DEC_PACK_ERR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESCO_CHAN_MOD</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ESCO_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCO_CONF0</name>
<description>I2S_SCO_CONF0</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CVSD_ENC_RESET</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CVSD_ENC_START</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCO_NO_I2S_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCO_WITH_I2S_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF1</name>
<description>I2S_CONF1</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_ZEROS_RM_EN</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_STOP_EN</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_PCM_BYPASS</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_PCM_CONF</name>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TX_PCM_BYPASS</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_PCM_CONF</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>PD_CONF</name>
<description>I2S_PD_CONF</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLC_MEM_FORCE_PU</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PLC_MEM_FORCE_PD</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFO_FORCE_PU</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FIFO_FORCE_PD</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF2</name>
<description>I2S_CONF2</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>INTER_VALID_EN</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXT_ADC_START_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCD_EN</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATA_ENABLE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DATA_ENABLE_TEST_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCD_TX_SDX2_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LCD_TX_WRX2_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAMERA_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLKM_CONF</name>
<description>I2S_CLKM_CONF</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLKA_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_EN</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLKM_DIV_A</name>
<bitOffset>14</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CLKM_DIV_B</name>
<bitOffset>8</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>CLKM_DIV_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SAMPLE_RATE_CONF</name>
<description>I2S_SAMPLE_RATE_CONF</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_BITS_MOD</name>
<bitOffset>18</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TX_BITS_MOD</name>
<bitOffset>12</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>RX_BCK_DIV_NUM</name>
<bitOffset>6</bitOffset>
<bitWidth>6</bitWidth>
</field>
<field>
<name>TX_BCK_DIV_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDM_CONF</name>
<description>I2S_PDM_CONF</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_PDM_HP_BYPASS</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_PDM_SINC_DSR_16_EN</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_PDM_SIGMADELTA_IN_SHIFT</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_PDM_SINC_IN_SHIFT</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_PDM_LP_IN_SHIFT</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_PDM_HP_IN_SHIFT</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TX_PDM_PRESCALE</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TX_PDM_SINC_OSR2</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>PDM2PCM_CONV_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PCM2PDM_CONV_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_PDM_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_PDM_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>PDM_FREQ_CONF</name>
<description>I2S_PDM_FREQ_CONF</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_PDM_FP</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>TX_PDM_FS</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATE</name>
<description>I2S_STATE</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_FIFO_RESET_BACK</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_FIFO_RESET_BACK</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_IDLE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>I2S_DATE</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>I2SDATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="SPI">
<name>SPI2</name>
<baseAddress>0x3ff64000</baseAddress>
</peripheral>
<peripheral>
<name>APB_CTRL</name>
<baseAddress>0x3ff66000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000220</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SYSCLK_CONF</name>
<description>APB_CTRL_SYSCLK_CONF</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>QUICK_CLK_CHNG</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST_TICK_CNT</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_320M_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRE_DIV_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>XTAL_TICK_CONF</name>
<description>APB_CTRL_XTAL_TICK_CONF</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XTAL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PLL_TICK_CONF</name>
<description>APB_CTRL_PLL_TICK_CONF</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CK8M_TICK_CONF</name>
<description>APB_CTRL_CK8M_TICK_CONF</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CK8M_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_CTRL</name>
<description>APB_CTRL_APB_SARADC_CTRL</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_DATA_TO_I2S</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_DATA_SAR_SEL</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR2_PATT_P_CLEAR</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR1_PATT_P_CLEAR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR2_PATT_LEN</name>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SARADC_SAR1_PATT_LEN</name>
<bitOffset>15</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SARADC_SAR_CLK_DIV</name>
<bitOffset>7</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_SAR_CLK_GATED</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR_SEL</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_WORK_MODE</name>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SARADC_SAR2_MUX</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_START</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_START_FORCE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_CTRL2</name>
<description>APB_CTRL_APB_SARADC_CTRL2</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_INV</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR1_INV</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_MAX_MEAS_NUM</name>
<bitOffset>1</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_MEAS_NUM_LIMIT</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_FSM</name>
<description>APB_CTRL_APB_SARADC_FSM</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAMPLE_CYCLE</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_START_WAIT</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_STANDBY_WAIT</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_RSTB_WAIT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR1_PATT_TAB1</name>
<description>APB_CTRL_APB_SARADC_SAR1_PATT_TAB1</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR1_PATT_TAB2</name>
<description>APB_CTRL_APB_SARADC_SAR1_PATT_TAB2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR1_PATT_TAB3</name>
<description>APB_CTRL_APB_SARADC_SAR1_PATT_TAB3</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR1_PATT_TAB4</name>
<description>APB_CTRL_APB_SARADC_SAR1_PATT_TAB4</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR2_PATT_TAB1</name>
<description>APB_CTRL_APB_SARADC_SAR2_PATT_TAB1</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR2_PATT_TAB2</name>
<description>APB_CTRL_APB_SARADC_SAR2_PATT_TAB2</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR2_PATT_TAB3</name>
<description>APB_CTRL_APB_SARADC_SAR2_PATT_TAB3</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APB_SARADC_SAR2_PATT_TAB4</name>
<description>APB_CTRL_APB_SARADC_SAR2_PATT_TAB4</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APLL_TICK_CONF</name>
<description>APB_CTRL_APLL_TICK_CONF</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APLL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>APB_CTRL_DATE</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>SYSCON</name>
<baseAddress>0x3ff66000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000220</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SYSCLK_CONF</name>
<description>SYSCON_SYSCLK_CONF</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>QUICK_CLK_CHNG</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RST_TICK_CNT</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_EN</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_320M_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PRE_DIV_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>XTAL_TICK_CONF</name>
<description>SYSCON_XTAL_TICK_CONF</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XTAL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>PLL_TICK_CONF</name>
<description>SYSCON_PLL_TICK_CONF</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PLL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CK8M_TICK_CONF</name>
<description>SYSCON_CK8M_TICK_CONF</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CK8M_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_CTRL</name>
<description>SYSCON_SARADC_CTRL</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_DATA_TO_I2S</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_DATA_SAR_SEL</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR2_PATT_P_CLEAR</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR1_PATT_P_CLEAR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR2_PATT_LEN</name>
<bitOffset>19</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SARADC_SAR1_PATT_LEN</name>
<bitOffset>15</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>SARADC_SAR_CLK_DIV</name>
<bitOffset>7</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_SAR_CLK_GATED</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR_SEL</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_WORK_MODE</name>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>SARADC_SAR2_MUX</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_START</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_START_FORCE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_CTRL2</name>
<description>SYSCON_SARADC_CTRL2</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_INV</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_SAR1_INV</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SARADC_MAX_MEAS_NUM</name>
<bitOffset>1</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_MEAS_NUM_LIMIT</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_FSM</name>
<description>SYSCON_SARADC_FSM</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAMPLE_CYCLE</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_START_WAIT</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_STANDBY_WAIT</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>SARADC_RSTB_WAIT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_SAR1_PATT_TAB1</name>
<description>SYSCON_SARADC_SAR1_PATT_TAB1</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_SAR1_PATT_TAB2</name>
<description>SYSCON_SARADC_SAR1_PATT_TAB2</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_SAR1_PATT_TAB3</name>
<description>SYSCON_SARADC_SAR1_PATT_TAB3</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_SAR1_PATT_TAB4</name>
<description>SYSCON_SARADC_SAR1_PATT_TAB4</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR1_PATT_TAB4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_SAR2_PATT_TAB1</name>
<description>SYSCON_SARADC_SAR2_PATT_TAB1</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB1</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_SAR2_PATT_TAB2</name>
<description>SYSCON_SARADC_SAR2_PATT_TAB2</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB2</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_SAR2_PATT_TAB3</name>
<description>SYSCON_SARADC_SAR2_PATT_TAB3</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB3</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>SARADC_SAR2_PATT_TAB4</name>
<description>SYSCON_SARADC_SAR2_PATT_TAB4</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SARADC_SAR2_PATT_TAB4</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>APLL_TICK_CONF</name>
<description>SYSCON_APLL_TICK_CONF</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APLL_TICK_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>SYSCON_DATE</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>FE2</name>
<baseAddress>0x3ff45000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>RTC_I2C</name>
<baseAddress>0x3ff48c00</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000160</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SCL_LOW_PERIOD</name>
<description>RTC_I2C_SCL_LOW_PERIOD</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCL_LOW_PERIOD</name>
<bitOffset>0</bitOffset>
<bitWidth>19</bitWidth>
</field>
</fields>
</register>
<register>
<name>CTRL</name>
<description>RTC_I2C_CTRL</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_LSB_FIRST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_LSB_FIRST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_START</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MS_MODE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SCL_FORCE_OUT</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SDA_FORCE_OUT</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DEBUG_STATUS</name>
<description>RTC_I2C_DEBUG_STATUS</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCL_STATE</name>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>MAIN_STATE</name>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>BYTE_TRANS</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_ADDR_MATCH</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BUS_BUSY</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARB_LOST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMED_OUT</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_RW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ACK_VAL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMEOUT</name>
<description>RTC_I2C_TIMEOUT</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMEOUT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLAVE_ADDR</name>
<description>RTC_I2C_SLAVE_ADDR</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SLAVE_ADDR_10BIT</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_ADDR</name>
<bitOffset>0</bitOffset>
<bitWidth>15</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>RTC_I2C_INT_RAW</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME_OUT_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_COMPLETE_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASTER_TRANS_COMPLETE_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBITRATION_LOST_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_TRANS_COMPLETE_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>RTC_I2C_INT_CLR</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIME_OUT_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TRANS_COMPLETE_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>MASTER_TRANS_COMPLETE_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ARBITRATION_LOST_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SLAVE_TRANS_COMPLETE_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SDA_DUTY</name>
<description>RTC_I2C_SDA_DUTY</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SDA_DUTY</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_HIGH_PERIOD</name>
<description>RTC_I2C_SCL_HIGH_PERIOD</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCL_HIGH_PERIOD</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_START_PERIOD</name>
<description>RTC_I2C_SCL_START_PERIOD</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCL_START_PERIOD</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>SCL_STOP_PERIOD</name>
<description>RTC_I2C_SCL_STOP_PERIOD</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SCL_STOP_PERIOD</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>BT</name>
<baseAddress>0x3ff51000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral>
<name>UART</name>
<baseAddress>0x3ff40000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>1024</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>537657344</offset>
<size>4</size>
<usage>buffer</usage>
</addressBlock>
<interrupt>
<name>UART0_INTR</name>
<description>interrupt of UART0, level</description>
<value>34</value>
</interrupt>
<interrupt>
<name>UART1_INTR</name>
<description>interrupt of UART1, level</description>
<value>35</value>
</interrupt>
<interrupt>
<name>UART2_INTR</name>
<description>interrupt of UART2, level</description>
<value>36</value>
</interrupt>
<interrupt>
<name>SPI0_INTR</name>
<description>interrupt of SPI0, level, SPI0 is for Cache Access, do not use this</description>
<value>28</value>
</interrupt>
<interrupt>
<name>SPI1_INTR</name>
<description>interrupt of SPI1, level, SPI1 is for flash read/write, do not use this</description>
<value>29</value>
</interrupt>
<interrupt>
<name>SPI2_INTR</name>
<description>interrupt of SPI2, level</description>
<value>30</value>
</interrupt>
<interrupt>
<name>SPI3_INTR</name>
<description>interrupt of SPI3, level</description>
<value>31</value>
</interrupt>
<registers>
<register>
<name>INT_RAW</name>
<description>UART_INT_RAW</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AT_CMD_CHAR_DET_INT_RAW</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_CLASH_INT_RAW</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_FRM_ERR_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_PARITY_ERR_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_DONE_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_BRK_IDLE_DONE_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_BRK_DONE_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GLITCH_DET_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_XOFF_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_XON_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_TOUT_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRK_DET_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS_CHG_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSR_CHG_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_OVF_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRM_ERR_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARITY_ERR_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST</name>
<description>UART_INT_ST</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AT_CMD_CHAR_DET_INT_ST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_CLASH_INT_ST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_FRM_ERR_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_PARITY_ERR_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_DONE_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_BRK_IDLE_DONE_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_BRK_DONE_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GLITCH_DET_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_XOFF_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_XON_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_TOUT_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRK_DET_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS_CHG_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSR_CHG_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_OVF_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRM_ERR_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARITY_ERR_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>UART_INT_ENA</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AT_CMD_CHAR_DET_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_CLASH_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_FRM_ERR_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_PARITY_ERR_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_DONE_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_BRK_IDLE_DONE_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_BRK_DONE_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GLITCH_DET_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_XOFF_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_XON_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_TOUT_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRK_DET_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS_CHG_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSR_CHG_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_OVF_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRM_ERR_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARITY_ERR_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>UART_INT_CLR</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>AT_CMD_CHAR_DET_INT_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_CLASH_INT_CLR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_FRM_ERR_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_PARITY_ERR_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_DONE_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_BRK_IDLE_DONE_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_BRK_DONE_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GLITCH_DET_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_XOFF_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_XON_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_TOUT_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>BRK_DET_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS_CHG_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSR_CHG_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_OVF_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FRM_ERR_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARITY_ERR_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLKDIV</name>
<description>UART_CLKDIV</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLKDIV_FRAG</name>
<bitOffset>20</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CLKDIV</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>AUTOBAUD</name>
<description>UART_AUTOBAUD</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GLITCH_FILT</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>AUTOBAUD_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>STATUS</name>
<description>UART_STATUS</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TXD</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTSN</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTRN</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST_UTX_OUT</name>
<bitOffset>24</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>UART_ST_UTX_OUT</name>
<usage>read-write</usage>
<enumeratedValue>
<name>TX_IDLE</name>
<description>TX_IDLE</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_STRT</name>
<description>TX_STRT</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DAT0</name>
<description>TX_DAT0</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DAT1</name>
<description>TX_DAT1</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DAT2</name>
<description>TX_DAT2</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DAT3</name>
<description>TX_DAT3</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DAT4</name>
<description>TX_DAT4</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DAT5</name>
<description>TX_DAT5</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DAT6</name>
<description>TX_DAT6</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DAT7</name>
<description>TX_DAT7</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_PRTY</name>
<description>TX_PRTY</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_STP1</name>
<description>TX_STP1</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_STP2</name>
<description>TX_STP2</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DL0</name>
<description>TX_DL0</description>
<value>13</value>
</enumeratedValue>
<enumeratedValue>
<name>TX_DL1</name>
<description>TX_DL1</description>
<value>14</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>TXFIFO_CNT</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>RXD</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTSN</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSRN</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ST_URX_OUT</name>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
<enumeratedValues>
<name>UART_ST_URX_OUT</name>
<usage>read-write</usage>
<enumeratedValue>
<name>RX_IDLE</name>
<description>RX_IDLE</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_STRT</name>
<description>RX_STRT</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DAT0</name>
<description>RX_DAT0</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DAT1</name>
<description>RX_DAT1</description>
<value>3</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DAT2</name>
<description>RX_DAT2</description>
<value>4</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DAT3</name>
<description>RX_DAT3</description>
<value>5</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DAT4</name>
<description>RX_DAT4</description>
<value>6</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DAT5</name>
<description>RX_DAT5</description>
<value>7</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DAT6</name>
<description>RX_DAT6</description>
<value>8</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DAT7</name>
<description>RX_DAT7</description>
<value>9</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_PRTY</name>
<description>RX_PRTY</description>
<value>10</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_STP1</name>
<description>RX_STP1</description>
<value>11</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_STP2</name>
<description>RX_STP2</description>
<value>12</value>
</enumeratedValue>
<enumeratedValue>
<name>RX_DL1</name>
<description>RX_DL1</description>
<value>13</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>RXFIFO_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF0</name>
<description>UART_CONF0</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TICK_REF_ALWAYS_ON</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>ERR_WR_MASK</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CLK_EN</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DTR_INV</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RTS_INV</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXD_INV</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DSR_INV</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CTS_INV</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXD_INV</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXFIFO_RST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RXFIFO_RST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRDA_EN</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TX_FLOW_EN</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LOOPBACK</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRDA_RX_INV</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRDA_TX_INV</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRDA_WCTL</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRDA_TX_EN</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IRDA_DPLX</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TXD_BRK</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_DTR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_RTS</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>STOP_BIT_NUM</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>UART_STOP_BIT_NUM</name>
<usage>read-write</usage>
<enumeratedValue>
<name>STOP_BITS_1</name>
<description>1 stop bits</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>STOP_BITS_1p5</name>
<description>1.5 stop bits</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>STOP_BITS_2</name>
<description>2 stop bits</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>BIT_NUM</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
<enumeratedValues>
<name>UART_BIT_NUM</name>
<usage>read-write</usage>
<enumeratedValue>
<name>DATA_BITS_5</name>
<description>5 data bits</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_BITS_6</name>
<description>6 data bits</description>
<value>1</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_BITS_7</name>
<description>7 data bits</description>
<value>2</value>
</enumeratedValue>
<enumeratedValue>
<name>DATA_BITS_8</name>
<description>8 data bits</description>
<value>3</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
<name>PARITY_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>PARITY</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF1</name>
<description>UART_CONF1</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_TOUT_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_TOUT_THRHD</name>
<bitOffset>24</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>RX_FLOW_EN</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RX_FLOW_THRHD</name>
<bitOffset>16</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>TXFIFO_EMPTY_THRHD</name>
<bitOffset>8</bitOffset>
<bitWidth>7</bitWidth>
</field>
<field>
<name>RXFIFO_FULL_THRHD</name>
<bitOffset>0</bitOffset>
<bitWidth>7</bitWidth>
</field>
</fields>
</register>
<register>
<name>LOWPULSE</name>
<description>UART_LOWPULSE</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LOWPULSE_MIN_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HIGHPULSE</name>
<description>UART_HIGHPULSE</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HIGHPULSE_MIN_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>RXD_CNT</name>
<description>UART_RXD_CNT</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RXD_EDGE_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>FLOW_CONF</name>
<description>UART_FLOW_CONF</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>SEND_XOFF</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SEND_XON</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_XOFF</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FORCE_XON</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>XONOFF_DEL</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SW_FLOW_CON_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>SLEEP_CONF</name>
<description>UART_SLEEP_CONF</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ACTIVE_THRESHOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>SWFC_CONF</name>
<description>UART_SWFC_CONF</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>XOFF_CHAR</name>
<bitOffset>24</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>XON_CHAR</name>
<bitOffset>16</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>XOFF_THRESHOLD</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>XON_THRESHOLD</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>IDLE_CONF</name>
<description>UART_IDLE_CONF</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_BRK_NUM</name>
<bitOffset>20</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>TX_IDLE_NUM</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>RX_IDLE_THRHD</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>RS485_CONF</name>
<description>UART_RS485_CONF</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RS485_TX_DLY_NUM</name>
<bitOffset>6</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RS485_RX_DLY_NUM</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485RXBY_TX_EN</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485TX_RX_EN</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DL1_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DL0_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>RS485_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>AT_CMD_PRECNT</name>
<description>UART_AT_CMD_PRECNT</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PRE_IDLE_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>AT_CMD_POSTCNT</name>
<description>UART_AT_CMD_POSTCNT</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>POST_IDLE_NUM</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>AT_CMD_GAPTOUT</name>
<description>UART_AT_CMD_GAPTOUT</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>RX_GAP_TOUT</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>AT_CMD_CHAR</name>
<description>UART_AT_CMD_CHAR</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CHAR_NUM</name>
<bitOffset>8</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>AT_CMD_CHAR</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>MEM_CONF</name>
<description>UART_MEM_CONF</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_MEM_EMPTY_THRHD</name>
<bitOffset>28</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RX_MEM_FULL_THRHD</name>
<bitOffset>25</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>XOFF_THRESHOLD_H2</name>
<bitOffset>23</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>XON_THRESHOLD_H2</name>
<bitOffset>21</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>RX_TOUT_THRHD_H3</name>
<bitOffset>18</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RX_FLOW_THRHD_H3</name>
<bitOffset>15</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TX_SIZE</name>
<bitOffset>7</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>RX_SIZE</name>
<bitOffset>3</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>MEM_PD</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MEM_TX_STATUS</name>
<description>UART_MEM_TX_STATUS</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM_TX_STATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
</fields>
</register>
<register>
<name>MEM_RX_STATUS</name>
<description>UART_MEM_RX_STATUS</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>MEM_RX_STATUS</name>
<bitOffset>0</bitOffset>
<bitWidth>24</bitWidth>
</field>
<field>
<name>MEM_RX_RD_ADDR</name>
<bitOffset>2</bitOffset>
<bitWidth>11</bitWidth>
</field>
<field>
<name>MEM_RX_WR_ADDR</name>
<bitOffset>13</bitOffset>
<bitWidth>11</bitWidth>
</field>
</fields>
</register>
<register>
<name>MEM_CNT_STATUS</name>
<description>UART_MEM_CNT_STATUS</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TX_MEM_CNT</name>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>RX_MEM_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>POSPULSE</name>
<description>UART_POSPULSE</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>POSEDGE_MIN_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>NEGPULSE</name>
<description>UART_NEGPULSE</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>NEGEDGE_MIN_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>UART_DATE</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>ID</name>
<description>UART_ID</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>ID</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>TX_FIFO</name>
<description>UART_TX_FIFO</description>
<addressOffset>537657344</addressOffset>
<size>8</size>
<access>write-only</access>
<fields>
<field>
<name>DATA</name>
<description>TX FIFO Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>RX_FIFO</name>
<description>UART_RX_FIFO</description>
<addressOffset>0</addressOffset>
<size>8</size>
<access>read-only</access>
<fields>
<field>
<name>DATA</name>
<description>TX FIFO Data</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>LEDC</name>
<baseAddress>0x3ff59000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000cc0</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
<name>LEDC_INTR</name>
<description>interrupt of LED PWM, level</description>
<value>43</value>
</interrupt>
<registers>
<register>
<name>HSCH0_CONF0</name>
<description>LEDC_HSCH0_CONF0</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EN</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_HSCH0</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_HSCH0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_HSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH0_HPOINT</name>
<description>LEDC_HSCH0_HPOINT</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_HSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH0_DUTY</name>
<description>LEDC_HSCH0_DUTY</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH0_CONF1</name>
<description>LEDC_HSCH0_CONF1</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_HSCH0</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_HSCH0</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_HSCH0</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_HSCH0</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_HSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH0_DUTY_R</name>
<description>LEDC_HSCH0_DUTY_R</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH1_CONF0</name>
<description>LEDC_HSCH1_CONF0</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_LV_HSCH1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_HSCH1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_HSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH1_HPOINT</name>
<description>LEDC_HSCH1_HPOINT</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_HSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH1_DUTY</name>
<description>LEDC_HSCH1_DUTY</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH1_CONF1</name>
<description>LEDC_HSCH1_CONF1</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_HSCH1</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_HSCH1</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_HSCH1</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_HSCH1</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_HSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH1_DUTY_R</name>
<description>LEDC_HSCH1_DUTY_R</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH2_CONF0</name>
<description>LEDC_HSCH2_CONF0</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_LV_HSCH2</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_HSCH2</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_HSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH2_HPOINT</name>
<description>LEDC_HSCH2_HPOINT</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_HSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH2_DUTY</name>
<description>LEDC_HSCH2_DUTY</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH2_CONF1</name>
<description>LEDC_HSCH2_CONF1</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_HSCH2</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_HSCH2</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_HSCH2</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_HSCH2</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_HSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH2_DUTY_R</name>
<description>LEDC_HSCH2_DUTY_R</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH3_CONF0</name>
<description>LEDC_HSCH3_CONF0</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_LV_HSCH3</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_HSCH3</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_HSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH3_HPOINT</name>
<description>LEDC_HSCH3_HPOINT</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_HSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH3_DUTY</name>
<description>LEDC_HSCH3_DUTY</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH3_CONF1</name>
<description>LEDC_HSCH3_CONF1</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_HSCH3</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_HSCH3</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_HSCH3</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_HSCH3</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_HSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH3_DUTY_R</name>
<description>LEDC_HSCH3_DUTY_R</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH4_CONF0</name>
<description>LEDC_HSCH4_CONF0</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_LV_HSCH4</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_HSCH4</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_HSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH4_HPOINT</name>
<description>LEDC_HSCH4_HPOINT</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_HSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH4_DUTY</name>
<description>LEDC_HSCH4_DUTY</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH4_CONF1</name>
<description>LEDC_HSCH4_CONF1</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_HSCH4</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_HSCH4</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_HSCH4</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_HSCH4</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_HSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH4_DUTY_R</name>
<description>LEDC_HSCH4_DUTY_R</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH5_CONF0</name>
<description>LEDC_HSCH5_CONF0</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_LV_HSCH5</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_HSCH5</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_HSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH5_HPOINT</name>
<description>LEDC_HSCH5_HPOINT</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_HSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH5_DUTY</name>
<description>LEDC_HSCH5_DUTY</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH5_CONF1</name>
<description>LEDC_HSCH5_CONF1</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_HSCH5</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_HSCH5</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_HSCH5</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_HSCH5</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_HSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH5_DUTY_R</name>
<description>LEDC_HSCH5_DUTY_R</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH6_CONF0</name>
<description>LEDC_HSCH6_CONF0</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_LV_HSCH6</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_HSCH6</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_HSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH6_HPOINT</name>
<description>LEDC_HSCH6_HPOINT</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_HSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH6_DUTY</name>
<description>LEDC_HSCH6_DUTY</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH6_CONF1</name>
<description>LEDC_HSCH6_CONF1</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_HSCH6</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_HSCH6</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_HSCH6</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_HSCH6</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_HSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH6_DUTY_R</name>
<description>LEDC_HSCH6_DUTY_R</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH7_CONF0</name>
<description>LEDC_HSCH7_CONF0</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>IDLE_LV_HSCH7</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_HSCH7</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_HSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH7_HPOINT</name>
<description>LEDC_HSCH7_HPOINT</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_HSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH7_DUTY</name>
<description>LEDC_HSCH7_DUTY</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH7_CONF1</name>
<description>LEDC_HSCH7_CONF1</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_HSCH7</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_HSCH7</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_HSCH7</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_HSCH7</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_HSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSCH7_DUTY_R</name>
<description>LEDC_HSCH7_DUTY_R</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_HSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH0_CONF0</name>
<description>LEDC_LSCH0_CONF0</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PARA_UP_LSCH0</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_LSCH0</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_LSCH0</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_LSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH0_HPOINT</name>
<description>LEDC_LSCH0_HPOINT</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_LSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH0_DUTY</name>
<description>LEDC_LSCH0_DUTY</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH0_CONF1</name>
<description>LEDC_LSCH0_CONF1</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_LSCH0</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_LSCH0</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_LSCH0</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_LSCH0</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_LSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH0_DUTY_R</name>
<description>LEDC_LSCH0_DUTY_R</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH0</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH1_CONF0</name>
<description>LEDC_LSCH1_CONF0</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PARA_UP_LSCH1</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_LSCH1</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_LSCH1</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_LSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH1_HPOINT</name>
<description>LEDC_LSCH1_HPOINT</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_LSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH1_DUTY</name>
<description>LEDC_LSCH1_DUTY</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH1_CONF1</name>
<description>LEDC_LSCH1_CONF1</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_LSCH1</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_LSCH1</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_LSCH1</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_LSCH1</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_LSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH1_DUTY_R</name>
<description>LEDC_LSCH1_DUTY_R</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH1</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH2_CONF0</name>
<description>LEDC_LSCH2_CONF0</description>
<addressOffset>0xc8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PARA_UP_LSCH2</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_LSCH2</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_LSCH2</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_LSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH2_HPOINT</name>
<description>LEDC_LSCH2_HPOINT</description>
<addressOffset>0xcc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_LSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH2_DUTY</name>
<description>LEDC_LSCH2_DUTY</description>
<addressOffset>0xd0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH2_CONF1</name>
<description>LEDC_LSCH2_CONF1</description>
<addressOffset>0xd4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_LSCH2</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_LSCH2</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_LSCH2</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_LSCH2</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_LSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH2_DUTY_R</name>
<description>LEDC_LSCH2_DUTY_R</description>
<addressOffset>0xd8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH2</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH3_CONF0</name>
<description>LEDC_LSCH3_CONF0</description>
<addressOffset>0xdc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PARA_UP_LSCH3</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_LSCH3</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_LSCH3</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_LSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH3_HPOINT</name>
<description>LEDC_LSCH3_HPOINT</description>
<addressOffset>0xe0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_LSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH3_DUTY</name>
<description>LEDC_LSCH3_DUTY</description>
<addressOffset>0xe4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH3_CONF1</name>
<description>LEDC_LSCH3_CONF1</description>
<addressOffset>0xe8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_LSCH3</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_LSCH3</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_LSCH3</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_LSCH3</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_LSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH3_DUTY_R</name>
<description>LEDC_LSCH3_DUTY_R</description>
<addressOffset>0xec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH3</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH4_CONF0</name>
<description>LEDC_LSCH4_CONF0</description>
<addressOffset>0xf0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PARA_UP_LSCH4</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_LSCH4</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_LSCH4</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_LSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH4_HPOINT</name>
<description>LEDC_LSCH4_HPOINT</description>
<addressOffset>0xf4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_LSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH4_DUTY</name>
<description>LEDC_LSCH4_DUTY</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH4_CONF1</name>
<description>LEDC_LSCH4_CONF1</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_LSCH4</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_LSCH4</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_LSCH4</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_LSCH4</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_LSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH4_DUTY_R</name>
<description>LEDC_LSCH4_DUTY_R</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH4</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH5_CONF0</name>
<description>LEDC_LSCH5_CONF0</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PARA_UP_LSCH5</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_LSCH5</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_LSCH5</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_LSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH5_HPOINT</name>
<description>LEDC_LSCH5_HPOINT</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_LSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH5_DUTY</name>
<description>LEDC_LSCH5_DUTY</description>
<addressOffset>0x10c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH5_CONF1</name>
<description>LEDC_LSCH5_CONF1</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_LSCH5</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_LSCH5</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_LSCH5</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_LSCH5</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_LSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH5_DUTY_R</name>
<description>LEDC_LSCH5_DUTY_R</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH5</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH6_CONF0</name>
<description>LEDC_LSCH6_CONF0</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PARA_UP_LSCH6</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_LSCH6</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_LSCH6</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_LSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH6_HPOINT</name>
<description>LEDC_LSCH6_HPOINT</description>
<addressOffset>0x11c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_LSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH6_DUTY</name>
<description>LEDC_LSCH6_DUTY</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH6_CONF1</name>
<description>LEDC_LSCH6_CONF1</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_LSCH6</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_LSCH6</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_LSCH6</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_LSCH6</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_LSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH6_DUTY_R</name>
<description>LEDC_LSCH6_DUTY_R</description>
<addressOffset>0x128</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH6</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH7_CONF0</name>
<description>LEDC_LSCH7_CONF0</description>
<addressOffset>0x12c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>PARA_UP_LSCH7</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>IDLE_LV_LSCH7</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>SIG_OUT_EN_LSCH7</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER_SEL_LSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH7_HPOINT</name>
<description>LEDC_LSCH7_HPOINT</description>
<addressOffset>0x130</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HPOINT_LSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH7_DUTY</name>
<description>LEDC_LSCH7_DUTY</description>
<addressOffset>0x134</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH7_CONF1</name>
<description>LEDC_LSCH7_CONF1</description>
<addressOffset>0x138</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_START_LSCH7</name>
<bitOffset>31</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_INC_LSCH7</name>
<bitOffset>30</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_NUM_LSCH7</name>
<bitOffset>20</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_CYCLE_LSCH7</name>
<bitOffset>10</bitOffset>
<bitWidth>10</bitWidth>
</field>
<field>
<name>DUTY_SCALE_LSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>10</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSCH7_DUTY_R</name>
<description>LEDC_LSCH7_DUTY_R</description>
<addressOffset>0x13c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_LSCH7</name>
<bitOffset>0</bitOffset>
<bitWidth>25</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMER0_CONF</name>
<description>LEDC_HSTIMER0_CONF</description>
<addressOffset>0x140</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TICK_SEL_HSTIMER0</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER0_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER0_PAUSE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_NUM_HSTIMER0</name>
<bitOffset>5</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>HSTIMER0_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMER0_VALUE</name>
<description>LEDC_HSTIMER0_VALUE</description>
<addressOffset>0x144</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HSTIMER0_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMER1_CONF</name>
<description>LEDC_HSTIMER1_CONF</description>
<addressOffset>0x148</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TICK_SEL_HSTIMER1</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER1_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER1_PAUSE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_NUM_HSTIMER1</name>
<bitOffset>5</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>HSTIMER1_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMER1_VALUE</name>
<description>LEDC_HSTIMER1_VALUE</description>
<addressOffset>0x14c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HSTIMER1_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMER2_CONF</name>
<description>LEDC_HSTIMER2_CONF</description>
<addressOffset>0x150</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TICK_SEL_HSTIMER2</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER2_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER2_PAUSE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_NUM_HSTIMER2</name>
<bitOffset>5</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>HSTIMER2_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMER2_VALUE</name>
<description>LEDC_HSTIMER2_VALUE</description>
<addressOffset>0x154</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HSTIMER2_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMER3_CONF</name>
<description>LEDC_HSTIMER3_CONF</description>
<addressOffset>0x158</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TICK_SEL_HSTIMER3</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER3_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER3_PAUSE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_NUM_HSTIMER3</name>
<bitOffset>5</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>HSTIMER3_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>HSTIMER3_VALUE</name>
<description>LEDC_HSTIMER3_VALUE</description>
<addressOffset>0x15c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>HSTIMER3_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSTIMER0_CONF</name>
<description>LEDC_LSTIMER0_CONF</description>
<addressOffset>0x160</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSTIMER0_PARA_UP</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TICK_SEL_LSTIMER0</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER0_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER0_PAUSE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_NUM_LSTIMER0</name>
<bitOffset>5</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>LSTIMER0_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSTIMER0_VALUE</name>
<description>LEDC_LSTIMER0_VALUE</description>
<addressOffset>0x164</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSTIMER0_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSTIMER1_CONF</name>
<description>LEDC_LSTIMER1_CONF</description>
<addressOffset>0x168</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSTIMER1_PARA_UP</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TICK_SEL_LSTIMER1</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER1_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER1_PAUSE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_NUM_LSTIMER1</name>
<bitOffset>5</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>LSTIMER1_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSTIMER1_VALUE</name>
<description>LEDC_LSTIMER1_VALUE</description>
<addressOffset>0x16c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSTIMER1_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSTIMER2_CONF</name>
<description>LEDC_LSTIMER2_CONF</description>
<addressOffset>0x170</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSTIMER2_PARA_UP</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TICK_SEL_LSTIMER2</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER2_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER2_PAUSE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_NUM_LSTIMER2</name>
<bitOffset>5</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>LSTIMER2_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSTIMER2_VALUE</name>
<description>LEDC_LSTIMER2_VALUE</description>
<addressOffset>0x174</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSTIMER2_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSTIMER3_CONF</name>
<description>LEDC_LSTIMER3_CONF</description>
<addressOffset>0x178</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSTIMER3_PARA_UP</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TICK_SEL_LSTIMER3</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER3_RST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER3_PAUSE</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DIV_NUM_LSTIMER3</name>
<bitOffset>5</bitOffset>
<bitWidth>18</bitWidth>
</field>
<field>
<name>LSTIMER3_LIM</name>
<bitOffset>0</bitOffset>
<bitWidth>5</bitWidth>
</field>
</fields>
</register>
<register>
<name>LSTIMER3_VALUE</name>
<description>LEDC_LSTIMER3_VALUE</description>
<addressOffset>0x17c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>LSTIMER3_CNT</name>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_RAW</name>
<description>LEDC_INT_RAW</description>
<addressOffset>0x180</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_CHNG_END_LSCH7_INT_RAW</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH6_INT_RAW</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH5_INT_RAW</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH4_INT_RAW</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH3_INT_RAW</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH2_INT_RAW</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH1_INT_RAW</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH0_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH7_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH6_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH5_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH4_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH3_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH2_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH1_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH0_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER3_OVF_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER2_OVF_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER1_OVF_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER0_OVF_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER3_OVF_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER2_OVF_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER1_OVF_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER0_OVF_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ST</name>
<description>LEDC_INT_ST</description>
<addressOffset>0x184</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_CHNG_END_LSCH7_INT_ST</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH6_INT_ST</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH5_INT_ST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH4_INT_ST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH3_INT_ST</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH2_INT_ST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH1_INT_ST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH0_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH7_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH6_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH5_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH4_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH3_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH2_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH1_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH0_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER3_OVF_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER2_OVF_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER1_OVF_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER0_OVF_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER3_OVF_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER2_OVF_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER1_OVF_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER0_OVF_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_ENA</name>
<description>LEDC_INT_ENA</description>
<addressOffset>0x188</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_CHNG_END_LSCH7_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH6_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH5_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH4_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH3_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH2_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH1_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH0_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH7_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH6_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH5_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH4_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH3_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH2_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH1_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH0_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER3_OVF_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER2_OVF_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER1_OVF_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER0_OVF_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER3_OVF_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER2_OVF_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER1_OVF_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER0_OVF_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>INT_CLR</name>
<description>LEDC_INT_CLR</description>
<addressOffset>0x18c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DUTY_CHNG_END_LSCH7_INT_CLR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH6_INT_CLR</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH5_INT_CLR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH4_INT_CLR</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH3_INT_CLR</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH2_INT_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH1_INT_CLR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_LSCH0_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH7_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH6_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH5_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH4_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH3_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH2_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH1_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DUTY_CHNG_END_HSCH0_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER3_OVF_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER2_OVF_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER1_OVF_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>LSTIMER0_OVF_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER3_OVF_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER2_OVF_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER1_OVF_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>HSTIMER0_OVF_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CONF</name>
<description>LEDC_CONF</description>
<addressOffset>0x190</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>APB_CLK_SEL</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>DATE</name>
<description>LEDC_DATE</description>
<addressOffset>0x1fc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral>
<name>MCPWM</name>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000940</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>CLK_CFG</name>
<description>MCPWM_CLK_CFG</description>
<addressOffset>0x0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_PRESCALE</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER0_CFG0</name>
<description>MCPWM_TIMER0_CFG0</description>
<addressOffset>0x4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER0_PERIOD_UPMETHOD</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER0_PERIOD</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TIMER0_PRESCALE</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER0_CFG1</name>
<description>MCPWM_TIMER0_CFG1</description>
<addressOffset>0x8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER0_MOD</name>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER0_START</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER0_SYNC</name>
<description>MCPWM_TIMER0_SYNC</description>
<addressOffset>0xc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER0_PHASE</name>
<bitOffset>4</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>TIMER0_SYNCO_SEL</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER0_SYNC_SW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_SYNCI_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER0_STATUS</name>
<description>MCPWM_TIMER0_STATUS</description>
<addressOffset>0x10</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER0_DIRECTION</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER1_CFG0</name>
<description>MCPWM_TIMER1_CFG0</description>
<addressOffset>0x14</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER1_PERIOD_UPMETHOD</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER1_PERIOD</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TIMER1_PRESCALE</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER1_CFG1</name>
<description>MCPWM_TIMER1_CFG1</description>
<addressOffset>0x18</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER1_MOD</name>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER1_START</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER1_SYNC</name>
<description>MCPWM_TIMER1_SYNC</description>
<addressOffset>0x1c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER1_PHASE</name>
<bitOffset>4</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>TIMER1_SYNCO_SEL</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER1_SYNC_SW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_SYNCI_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER1_STATUS</name>
<description>MCPWM_TIMER1_STATUS</description>
<addressOffset>0x20</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER1_DIRECTION</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER2_CFG0</name>
<description>MCPWM_TIMER2_CFG0</description>
<addressOffset>0x24</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER2_PERIOD_UPMETHOD</name>
<bitOffset>24</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER2_PERIOD</name>
<bitOffset>8</bitOffset>
<bitWidth>16</bitWidth>
</field>
<field>
<name>TIMER2_PRESCALE</name>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER2_CFG1</name>
<description>MCPWM_TIMER2_CFG1</description>
<addressOffset>0x28</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER2_MOD</name>
<bitOffset>3</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER2_START</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER2_SYNC</name>
<description>MCPWM_TIMER2_SYNC</description>
<addressOffset>0x2c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER2_PHASE</name>
<bitOffset>4</bitOffset>
<bitWidth>17</bitWidth>
</field>
<field>
<name>TIMER2_SYNCO_SEL</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>TIMER2_SYNC_SW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_SYNCI_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER2_STATUS</name>
<description>MCPWM_TIMER2_STATUS</description>
<addressOffset>0x30</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>TIMER2_DIRECTION</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>TIMER_SYNCI_CFG</name>
<description>MCPWM_TIMER_SYNCI_CFG</description>
<addressOffset>0x34</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EXTERNAL_SYNCI2_INVERT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTERNAL_SYNCI1_INVERT</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EXTERNAL_SYNCI0_INVERT</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_SYNCISEL</name>
<bitOffset>6</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TIMER1_SYNCISEL</name>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>TIMER0_SYNCISEL</name>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
</field>
</fields>
</register>
<register>
<name>OPERATOR_TIMERSEL</name>
<description>MCPWM_OPERATOR_TIMERSEL</description>
<addressOffset>0x38</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OPERATOR2_TIMERSEL</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OPERATOR1_TIMERSEL</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>OPERATOR0_TIMERSEL</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN0_STMP_CFG</name>
<description>MCPWM_GEN0_STMP_CFG</description>
<addressOffset>0x3c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN0_B_SHDW_FULL</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN0_A_SHDW_FULL</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN0_B_UPMETHOD</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>GEN0_A_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN0_TSTMP_A</name>
<description>MCPWM_GEN0_TSTMP_A</description>
<addressOffset>0x40</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN0_A</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN0_TSTMP_B</name>
<description>MCPWM_GEN0_TSTMP_B</description>
<addressOffset>0x44</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN0_B</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN0_CFG0</name>
<description>MCPWM_GEN0_CFG0</description>
<addressOffset>0x48</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN0_T1_SEL</name>
<bitOffset>7</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GEN0_T0_SEL</name>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GEN0_CFG_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN0_FORCE</name>
<description>MCPWM_GEN0_FORCE</description>
<addressOffset>0x4c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN0_B_NCIFORCE_MODE</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_NCIFORCE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN0_A_NCIFORCE_MODE</name>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_NCIFORCE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN0_B_CNTUFORCE_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_CNTUFORCE_MODE</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_CNTUFORCE_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN0_A</name>
<description>MCPWM_GEN0_A</description>
<addressOffset>0x50</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN0_A_DT1</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_DT0</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_DTEB</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_DTEA</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_DTEP</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_DTEZ</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_UT1</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_UT0</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_UTEB</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_UTEA</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_UTEP</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_A_UTEZ</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN0_B</name>
<description>MCPWM_GEN0_B</description>
<addressOffset>0x54</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN0_B_DT1</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_DT0</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_DTEB</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_DTEA</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_DTEP</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_DTEZ</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_UT1</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_UT0</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_UTEB</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_UTEA</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_UTEP</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN0_B_UTEZ</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT0_CFG</name>
<description>MCPWM_DT0_CFG</description>
<addressOffset>0x58</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT0_CLK_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_B_OUTBYPASS</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_A_OUTBYPASS</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_FED_OUTINVERT</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_RED_OUTINVERT</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_FED_INSEL</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_RED_INSEL</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_B_OUTSWAP</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_A_OUTSWAP</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_DEB_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT0_RED_UPMETHOD</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT0_FED_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT0_FED_CFG</name>
<description>MCPWM_DT0_FED_CFG</description>
<addressOffset>0x5c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT0_FED</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT0_RED_CFG</name>
<description>MCPWM_DT0_RED_CFG</description>
<addressOffset>0x60</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT0_RED</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CARRIER0_CFG</name>
<description>MCPWM_CARRIER0_CFG</description>
<addressOffset>0x64</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER0_IN_INVERT</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER0_OUT_INVERT</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER0_OSHWTH</name>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CARRIER0_DUTY</name>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CARRIER0_PRESCALE</name>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CARRIER0_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH0_CFG0</name>
<description>MCPWM_FH0_CFG0</description>
<addressOffset>0x68</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH0_B_OST_U</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_B_OST_D</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_B_CBC_U</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_B_CBC_D</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_A_OST_U</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_A_OST_D</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_A_CBC_U</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_A_CBC_D</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_F0_OST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_F1_OST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_F2_OST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_SW_OST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_F0_CBC</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_F1_CBC</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_F2_CBC</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_SW_CBC</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH0_CFG1</name>
<description>MCPWM_FH0_CFG1</description>
<addressOffset>0x6c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH0_FORCE_OST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_FORCE_CBC</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_CBCPULSE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH0_CLR_OST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH0_STATUS</name>
<description>MCPWM_FH0_STATUS</description>
<addressOffset>0x70</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH0_OST_ON</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_CBC_ON</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN1_STMP_CFG</name>
<description>MCPWM_GEN1_STMP_CFG</description>
<addressOffset>0x74</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN1_B_SHDW_FULL</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN1_A_SHDW_FULL</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN1_B_UPMETHOD</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>GEN1_A_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN1_TSTMP_A</name>
<description>MCPWM_GEN1_TSTMP_A</description>
<addressOffset>0x78</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN1_A</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN1_TSTMP_B</name>
<description>MCPWM_GEN1_TSTMP_B</description>
<addressOffset>0x7c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN1_B</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN1_CFG0</name>
<description>MCPWM_GEN1_CFG0</description>
<addressOffset>0x80</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN1_T1_SEL</name>
<bitOffset>7</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GEN1_T0_SEL</name>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GEN1_CFG_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN1_FORCE</name>
<description>MCPWM_GEN1_FORCE</description>
<addressOffset>0x84</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN1_B_NCIFORCE_MODE</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_NCIFORCE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN1_A_NCIFORCE_MODE</name>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_NCIFORCE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN1_B_CNTUFORCE_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_CNTUFORCE_MODE</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_CNTUFORCE_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN1_A</name>
<description>MCPWM_GEN1_A</description>
<addressOffset>0x88</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN1_A_DT1</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_DT0</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_DTEB</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_DTEA</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_DTEP</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_DTEZ</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_UT1</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_UT0</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_UTEB</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_UTEA</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_UTEP</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_A_UTEZ</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN1_B</name>
<description>MCPWM_GEN1_B</description>
<addressOffset>0x8c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN1_B_DT1</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_DT0</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_DTEB</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_DTEA</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_DTEP</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_DTEZ</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_UT1</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_UT0</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_UTEB</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_UTEA</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_UTEP</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN1_B_UTEZ</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT1_CFG</name>
<description>MCPWM_DT1_CFG</description>
<addressOffset>0x90</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT1_CLK_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_B_OUTBYPASS</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_A_OUTBYPASS</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_FED_OUTINVERT</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_RED_OUTINVERT</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_FED_INSEL</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_RED_INSEL</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_B_OUTSWAP</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_A_OUTSWAP</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_DEB_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT1_RED_UPMETHOD</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT1_FED_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT1_FED_CFG</name>
<description>MCPWM_DT1_FED_CFG</description>
<addressOffset>0x94</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT1_FED</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT1_RED_CFG</name>
<description>MCPWM_DT1_RED_CFG</description>
<addressOffset>0x98</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT1_RED</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CARRIER1_CFG</name>
<description>MCPWM_CARRIER1_CFG</description>
<addressOffset>0x9c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER1_IN_INVERT</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER1_OUT_INVERT</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER1_OSHWTH</name>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CARRIER1_DUTY</name>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CARRIER1_PRESCALE</name>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CARRIER1_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH1_CFG0</name>
<description>MCPWM_FH1_CFG0</description>
<addressOffset>0xa0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH1_B_OST_U</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_B_OST_D</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_B_CBC_U</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_B_CBC_D</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_A_OST_U</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_A_OST_D</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_A_CBC_U</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_A_CBC_D</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_F0_OST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_F1_OST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_F2_OST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_SW_OST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_F0_CBC</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_F1_CBC</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_F2_CBC</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_SW_CBC</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH1_CFG1</name>
<description>MCPWM_FH1_CFG1</description>
<addressOffset>0xa4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH1_FORCE_OST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_FORCE_CBC</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_CBCPULSE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH1_CLR_OST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH1_STATUS</name>
<description>MCPWM_FH1_STATUS</description>
<addressOffset>0xa8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH1_OST_ON</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_CBC_ON</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN2_STMP_CFG</name>
<description>MCPWM_GEN2_STMP_CFG</description>
<addressOffset>0xac</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN2_B_SHDW_FULL</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN2_A_SHDW_FULL</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN2_B_UPMETHOD</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>GEN2_A_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN2_TSTMP_A</name>
<description>MCPWM_GEN2_TSTMP_A</description>
<addressOffset>0xb0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN2_A</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN2_TSTMP_B</name>
<description>MCPWM_GEN2_TSTMP_B</description>
<addressOffset>0xb4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN2_B</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN2_CFG0</name>
<description>MCPWM_GEN2_CFG0</description>
<addressOffset>0xb8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN2_T1_SEL</name>
<bitOffset>7</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GEN2_T0_SEL</name>
<bitOffset>4</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>GEN2_CFG_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN2_FORCE</name>
<description>MCPWM_GEN2_FORCE</description>
<addressOffset>0xbc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN2_B_NCIFORCE_MODE</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_NCIFORCE</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN2_A_NCIFORCE_MODE</name>
<bitOffset>11</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_NCIFORCE</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GEN2_B_CNTUFORCE_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_CNTUFORCE_MODE</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_CNTUFORCE_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN2_A</name>
<description>MCPWM_GEN2_A</description>
<addressOffset>0xc0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN2_A_DT1</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_DT0</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_DTEB</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_DTEA</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_DTEP</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_DTEZ</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_UT1</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_UT0</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_UTEB</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_UTEA</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_UTEP</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_A_UTEZ</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>GEN2_B</name>
<description>MCPWM_GEN2_B</description>
<addressOffset>0xc4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>GEN2_B_DT1</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_DT0</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_DTEB</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_DTEA</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_DTEP</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_DTEZ</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_UT1</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_UT0</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_UTEB</name>
<bitOffset>6</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_UTEA</name>
<bitOffset>4</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_UTEP</name>
<bitOffset>2</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>GEN2_B_UTEZ</name>
<bitOffset>0</bitOffset>
<bitWidth>2</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT2_CFG</name>
<description>MCPWM_DT2_CFG</description>
<addressOffset>0xc8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT2_CLK_SEL</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_B_OUTBYPASS</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_A_OUTBYPASS</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_FED_OUTINVERT</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_RED_OUTINVERT</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_FED_INSEL</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_RED_INSEL</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_B_OUTSWAP</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_A_OUTSWAP</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_DEB_MODE</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>DT2_RED_UPMETHOD</name>
<bitOffset>4</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>DT2_FED_UPMETHOD</name>
<bitOffset>0</bitOffset>
<bitWidth>4</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT2_FED_CFG</name>
<description>MCPWM_DT2_FED_CFG</description>
<addressOffset>0xcc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT2_FED</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>DT2_RED_CFG</name>
<description>MCPWM_DT2_RED_CFG</description>
<addressOffset>0xd0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DT2_RED</name>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
</field>
</fields>
</register>
<register>
<name>CARRIER2_CFG</name>
<description>MCPWM_CARRIER2_CFG</description>
<addressOffset>0xd4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CARRIER2_IN_INVERT</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER2_OUT_INVERT</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CARRIER2_OSHWTH</name>
<bitOffset>8</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CARRIER2_DUTY</name>
<bitOffset>5</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CARRIER2_PRESCALE</name>
<bitOffset>1</bitOffset>
<bitWidth>4</bitWidth>
</field>
<field>
<name>CARRIER2_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH2_CFG0</name>
<description>MCPWM_FH2_CFG0</description>
<addressOffset>0xd8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH2_B_OST_U</name>
<bitOffset>22</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_B_OST_D</name>
<bitOffset>20</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_B_CBC_U</name>
<bitOffset>18</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_B_CBC_D</name>
<bitOffset>16</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_A_OST_U</name>
<bitOffset>14</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_A_OST_D</name>
<bitOffset>12</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_A_CBC_U</name>
<bitOffset>10</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_A_CBC_D</name>
<bitOffset>8</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_F0_OST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_F1_OST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_F2_OST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_SW_OST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_F0_CBC</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_F1_CBC</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_F2_CBC</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_SW_CBC</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH2_CFG1</name>
<description>MCPWM_FH2_CFG1</description>
<addressOffset>0xdc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH2_FORCE_OST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_FORCE_CBC</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_CBCPULSE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>FH2_CLR_OST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FH2_STATUS</name>
<description>MCPWM_FH2_STATUS</description>
<addressOffset>0xe0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>FH2_OST_ON</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_CBC_ON</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>FAULT_DETECT</name>
<description>MCPWM_FAULT_DETECT</description>
<addressOffset>0xe4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>EVENT_F2</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVENT_F1</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>EVENT_F0</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>F2_POLE</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>F1_POLE</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>F0_POLE</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>F2_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>F1_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>F0_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_TIMER_CFG</name>
<description>MCPWM_CAP_TIMER_CFG</description>
<addressOffset>0xe8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP_SYNC_SW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP_SYNCI_SEL</name>
<bitOffset>2</bitOffset>
<bitWidth>3</bitWidth>
</field>
<field>
<name>CAP_SYNCI_EN</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP_TIMER_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_TIMER_PHASE</name>
<description>MCPWM_CAP_TIMER_PHASE</description>
<addressOffset>0xec</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP_PHASE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_CH0_CFG</name>
<description>MCPWM_CAP_CH0_CFG</description>
<addressOffset>0xf0</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP0_SW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP0_IN_INVERT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP0_PRESCALE</name>
<bitOffset>3</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CAP0_MODE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CAP0_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_CH1_CFG</name>
<description>MCPWM_CAP_CH1_CFG</description>
<addressOffset>0xf4</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP1_SW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP1_IN_INVERT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP1_PRESCALE</name>
<bitOffset>3</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CAP1_MODE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CAP1_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_CH2_CFG</name>
<description>MCPWM_CAP_CH2_CFG</description>
<addressOffset>0xf8</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP2_SW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP2_IN_INVERT</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP2_PRESCALE</name>
<bitOffset>3</bitOffset>
<bitWidth>8</bitWidth>
</field>
<field>
<name>CAP2_MODE</name>
<bitOffset>1</bitOffset>
<bitWidth>2</bitWidth>
</field>
<field>
<name>CAP2_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_CH0</name>
<description>MCPWM_CAP_CH0</description>
<addressOffset>0xfc</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP0_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_CH1</name>
<description>MCPWM_CAP_CH1</description>
<addressOffset>0x100</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP1_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_CH2</name>
<description>MCPWM_CAP_CH2</description>
<addressOffset>0x104</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP2_VALUE</name>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
</field>
</fields>
</register>
<register>
<name>CAP_STATUS</name>
<description>MCPWM_CAP_STATUS</description>
<addressOffset>0x108</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP2_EDGE</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP1_EDGE</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP0_EDGE</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>UPDATE_CFG</name>
<description>MCPWM_UPDATE_CFG</description>
<addressOffset>0x10c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>OP2_FORCE_UP</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_UP_EN</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_FORCE_UP</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_UP_EN</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_FORCE_UP</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_UP_EN</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GLOBAL_FORCE_UP</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>GLOBAL_UP_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCMCPWM_INT_ENA_MCPWM</name>
<description>MCMCPWM_INT_ENA_MCPWM</description>
<addressOffset>0x110</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP2_INT_ENA</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP1_INT_ENA</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP0_INT_ENA</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_OST_INT_ENA</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_OST_INT_ENA</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_OST_INT_ENA</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_CBC_INT_ENA</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_CBC_INT_ENA</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_CBC_INT_ENA</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_TEB_INT_ENA</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_TEB_INT_ENA</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_TEB_INT_ENA</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_TEA_INT_ENA</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_TEA_INT_ENA</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_TEA_INT_ENA</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2_CLR_INT_ENA</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1_CLR_INT_ENA</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT0_CLR_INT_ENA</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2_INT_ENA</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1_INT_ENA</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT0_INT_ENA</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_TEP_INT_ENA</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_TEP_INT_ENA</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_TEP_INT_ENA</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_TEZ_INT_ENA</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_TEZ_INT_ENA</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_TEZ_INT_ENA</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_STOP_INT_ENA</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_STOP_INT_ENA</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_STOP_INT_ENA</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCMCPWM_INT_RAW_MCPWM</name>
<description>MCMCPWM_INT_RAW_MCPWM</description>
<addressOffset>0x114</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP2_INT_RAW</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP1_INT_RAW</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP0_INT_RAW</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_OST_INT_RAW</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_OST_INT_RAW</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_OST_INT_RAW</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_CBC_INT_RAW</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_CBC_INT_RAW</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_CBC_INT_RAW</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_TEB_INT_RAW</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_TEB_INT_RAW</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_TEB_INT_RAW</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_TEA_INT_RAW</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_TEA_INT_RAW</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_TEA_INT_RAW</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2_CLR_INT_RAW</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1_CLR_INT_RAW</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT0_CLR_INT_RAW</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2_INT_RAW</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1_INT_RAW</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT0_INT_RAW</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_TEP_INT_RAW</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_TEP_INT_RAW</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_TEP_INT_RAW</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_TEZ_INT_RAW</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_TEZ_INT_RAW</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_TEZ_INT_RAW</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_STOP_INT_RAW</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_STOP_INT_RAW</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_STOP_INT_RAW</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCMCPWM_INT_ST_MCPWM</name>
<description>MCMCPWM_INT_ST_MCPWM</description>
<addressOffset>0x118</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP2_INT_ST</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP1_INT_ST</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP0_INT_ST</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_OST_INT_ST</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_OST_INT_ST</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_OST_INT_ST</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_CBC_INT_ST</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_CBC_INT_ST</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_CBC_INT_ST</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_TEB_INT_ST</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_TEB_INT_ST</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_TEB_INT_ST</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_TEA_INT_ST</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_TEA_INT_ST</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_TEA_INT_ST</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2_CLR_INT_ST</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1_CLR_INT_ST</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT0_CLR_INT_ST</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2_INT_ST</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1_INT_ST</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT0_INT_ST</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_TEP_INT_ST</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_TEP_INT_ST</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_TEP_INT_ST</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_TEZ_INT_ST</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_TEZ_INT_ST</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_TEZ_INT_ST</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_STOP_INT_ST</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_STOP_INT_ST</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_STOP_INT_ST</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>MCMCPWM_INT_CLR_MCPWM</name>
<description>MCMCPWM_INT_CLR_MCPWM</description>
<addressOffset>0x11c</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CAP2_INT_CLR</name>
<bitOffset>29</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP1_INT_CLR</name>
<bitOffset>28</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>CAP0_INT_CLR</name>
<bitOffset>27</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_OST_INT_CLR</name>
<bitOffset>26</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_OST_INT_CLR</name>
<bitOffset>25</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_OST_INT_CLR</name>
<bitOffset>24</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH2_CBC_INT_CLR</name>
<bitOffset>23</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH1_CBC_INT_CLR</name>
<bitOffset>22</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FH0_CBC_INT_CLR</name>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_TEB_INT_CLR</name>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_TEB_INT_CLR</name>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_TEB_INT_CLR</name>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP2_TEA_INT_CLR</name>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP1_TEA_INT_CLR</name>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>OP0_TEA_INT_CLR</name>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2_CLR_INT_CLR</name>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1_CLR_INT_CLR</name>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT0_CLR_INT_CLR</name>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT2_INT_CLR</name>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT1_INT_CLR</name>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>FAULT0_INT_CLR</name>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_TEP_INT_CLR</name>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_TEP_INT_CLR</name>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_TEP_INT_CLR</name>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_TEZ_INT_CLR</name>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_TEZ_INT_CLR</name>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_TEZ_INT_CLR</name>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER2_STOP_INT_CLR</name>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER1_STOP_INT_CLR</name>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
<name>TIMER0_STOP_INT_CLR</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>CLK</name>
<description>MCPWM_CLK</description>
<addressOffset>0x120</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>CLK_EN</name>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
</fields>
</register>
<register>
<name>VERSION</name>
<description>MCPWM_VERSION</description>
<addressOffset>0x124</addressOffset>
<size>32</size>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>DATE</name>
<bitOffset>0</bitOffset>
<bitWidth>28</bitWidth>
</field>
</fields>
</register>
</registers>
</peripheral>
<peripheral derivedFrom="UART">
<name>UART1</name>
<baseAddress>0x3ff50000</baseAddress>
</peripheral>
<peripheral derivedFrom="SPI">
<name>SPI1</name>
<baseAddress>0x3ff42000</baseAddress>
</peripheral>
<peripheral>
<name>I2S1</name>
<baseAddress>0x3ff6d000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x00000000</size>
<usage>registers</usage>
</addressBlock>
<registers />
</peripheral>
<peripheral derivedFrom="UART">
<name>UART0</name>
<baseAddress>0x3ff40000</baseAddress>
</peripheral>
<peripheral>
<name>RNG</name>
<description>True Random Number Generator</description>
<baseAddress>1073172804</baseAddress>
<registers>
<register>
<name>RNG_DATA</name>
<description>Random Number Data</description>
<addressOffset>0</addressOffset>
<size>32</size>
<access>read-only</access>
</register>
</registers>
</peripheral>
<peripheral>
<name>XTENSA_INTERNAL</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>INTERNAL_TIMER0_INTR</name>
<description>Internal Timer 0 interrupt</description>
<value>69</value>
</interrupt>
<interrupt>
<name>INTERNAL_SOFTWARE_LEVEL_1_INTR</name>
<description>Software Level 1 interrupt</description>
<value>70</value>
</interrupt>
<interrupt>
<name>INTERNAL_PROFILING_INTR</name>
<description>Profiling interrupt</description>
<value>71</value>
</interrupt>
<interrupt>
<name>INTERNAL_TIMER1_INTR</name>
<description>Internal Timer 1 interrupt</description>
<value>72</value>
</interrupt>
<interrupt>
<name>INTERNAL_TIMER2_INTR</name>
<description>Internal Timer 1 interrupt</description>
<value>73</value>
</interrupt>
<interrupt>
<name>INTERNAL_SOFTWARE_LEVEL_3_INTR</name>
<description>Software Level 3 interrupt</description>
<value>74</value>
</interrupt>
</peripheral>
<peripheral>
<name>XTENSA</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>FROM_CPU_INTR0</name>
<description>interrupt0 generated from a CPU, level</description>
<value>24</value>
</interrupt>
<interrupt>
<name>FROM_CPU_INTR1</name>
<description>interrupt1 generated from a CPU, level</description>
<value>25</value>
</interrupt>
<interrupt>
<name>FROM_CPU_INTR2</name>
<description>interrupt2 generated from a CPU, level</description>
<value>26</value>
</interrupt>
<interrupt>
<name>FROM_CPU_INTR3</name>
<description>interrupt3 generated from a CPU, level</description>
<value>27</value>
</interrupt>
<interrupt>
<name>TIMER1_INTR</name>
<description>will be cancelled</description>
<value>56</value>
</interrupt>
<interrupt>
<name>TIMER2_INTR</name>
<description>will be cancelled</description>
<value>57</value>
</interrupt>
<interrupt>
<name>MMU_IA_INTR</name>
<description>interrupt of MMU Invalid Access, LEVEL</description>
<value>66</value>
</interrupt>
<interrupt>
<name>MPU_IA_INTR</name>
<description>interrupt of MPU Invalid Access, LEVEL</description>
<value>67</value>
</interrupt>
<interrupt>
<name>CACHE_IA_INTR</name>
<description>interrupt of Cache Invalid Access, LEVEL</description>
<value>68</value>
</interrupt>
</peripheral>
<peripheral>
<name>WIFI_MAC</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>WIFI_MAC_INTR</name>
<description>interrupt of WiFi MAC, level</description>
<value>0</value>
</interrupt>
<interrupt>
<name>WIFI_MAC_NMI</name>
<description>interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI</description>
<value>1</value>
</interrupt>
</peripheral>
<peripheral>
<name>WIFI_BB</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>WIFI_BB_INTR</name>
<description>interrupt of WiFi BB, level, we can do some calibration</description>
<value>2</value>
</interrupt>
</peripheral>
<peripheral>
<name>BT_MAC</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>BT_MAC_INTR</name>
<description>will be cancelled</description>
<value>3</value>
</interrupt>
</peripheral>
<peripheral>
<name>BT_BB</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>BT_BB_INTR</name>
<description>interrupt of BT BB, level</description>
<value>4</value>
</interrupt>
<interrupt>
<name>BT_BB_NMI</name>
<description>interrupt of BT BB, NMI, use if BB have bug to fix in NMI</description>
<value>5</value>
</interrupt>
</peripheral>
<peripheral>
<name>RW_BT</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>RWBT_INTR</name>
<description>interrupt of RWBT, level</description>
<value>6</value>
</interrupt>
<interrupt>
<name>RWBT_NMI</name>
<description>interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI</description>
<value>8</value>
</interrupt>
</peripheral>
<peripheral>
<name>RW_BLE</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>RWBLE_INTR</name>
<description>interrupt of RWBLE, level</description>
<value>7</value>
</interrupt>
<interrupt>
<name>RWBLE_NMI</name>
<description>interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI</description>
<value>9</value>
</interrupt>
</peripheral>
<peripheral>
<name>ETH_MAC</name>
<baseAddress>0</baseAddress>
</peripheral>
<peripheral>
<name>SDIO</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>SDIO_HOST_INTR</name>
<description>interrupt of SD/SDIO/MMC HOST, level</description>
<value>37</value>
</interrupt>
</peripheral>
<peripheral>
<name>ETH</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>ETH_MAC_INTR</name>
<description>interrupt of ethernet mac, level</description>
<value>38</value>
</interrupt>
</peripheral>
<peripheral>
<name>WDT</name>
<baseAddress>0</baseAddress>
<interrupt>
<name>WDT_INTR</name>
<description>will be cancelled</description>
<value>55</value>
</interrupt>
</peripheral>
</peripherals>
</device>