CAPI=2:

name: award-winning:wishbone:wb_ram:1.1.0
description: Wishbone RAM with selectable backends
license: ISC

filesets:
  rtl:
    files: 
      - rtl/verilog/wb_ram.v
      - rtl/verilog/wb_ram_generic.v
    file_type: verilogSource
    depend: ['>=award-winning:wishbone:wb_common:0']

  tb:
    files: [bench/wb_ram_tb.v : {file_type : verilogSource}]
    depend: ['>=fusesoc:utils:vlog_tb_utils:1.0', '>=award-winning:wishbone:wb_bfm:1.0']

parameters:
  transactions:
    datatype: int
    description: Number of wishbone transactions to run in test bench
    paramtype: plusarg
    scope: private

targets:
  default:
    filesets: [rtl]

  sim:
    default_tool: icarus
    description : WB RAM testbench
    filesets: [rtl, tb]
    parameters: [transactions]
    toplevel: wb_ram_tb

provider:
  name: github
  user: fusesoc
  repo: wb_ram
  version: v1.1