CAPI=2: '' ############################################################### # WARNING-AUTOGENERATED: DO NOT MODIFY # # Auto-generated by: # # https://github.com/dpetrisko/basejump_stl_cores # # # # Please submit issues / PRs to the generator repo instead! # ############################################################### name: bespoke-silicon-group:basejump_stl:nonsynth:0.0.1 description: 'BaseJump STL: A Standard Template Library for SystemVerilog (Nonsynthesizable)' filesets: rtl: files: - bsg_cache/bsg_nonsynth_cache_axe_tracer.sv - bsg_clk_gen/bsg_nonsynth_clk_watcher.sv - bsg_mem/bsg_nonsynth_mem_1r1w_sync_dma.sv - bsg_mem/bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.sv - bsg_mem/bsg_nonsynth_mem_1rw_sync_assoc.sv - bsg_mem/bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc.sv - bsg_mem/bsg_nonsynth_mem_1rw_sync_mask_write_byte_dma.sv - bsg_test/bsg_nonsynth_ascii_writer.sv - bsg_test/bsg_nonsynth_axi_mem.sv - bsg_test/bsg_nonsynth_clock_gen.sv - bsg_test/bsg_nonsynth_clock_gen_plusarg.sv - bsg_test/bsg_nonsynth_delay_line.sv - bsg_test/bsg_nonsynth_dpi_clock_gen.sv - bsg_test/bsg_nonsynth_dpi_cycle_counter.sv - bsg_test/bsg_nonsynth_dpi_from_fifo.sv - bsg_test/bsg_nonsynth_dpi_gpio.sv - bsg_test/bsg_nonsynth_dpi_rom.sv - bsg_test/bsg_nonsynth_dpi_to_fifo.sv - bsg_test/bsg_nonsynth_dramsim3.sv - bsg_test/bsg_nonsynth_dramsim3_map.sv - bsg_test/bsg_nonsynth_dramsim3_unmap.sv - bsg_test/bsg_nonsynth_ramulator_hbm.sv - bsg_test/bsg_nonsynth_random_gen.sv - bsg_test/bsg_nonsynth_test_rom.sv - bsg_test/bsg_nonsynth_triwire.sv - bsg_test/bsg_nonsynth_val_watcher_1p.sv - bsg_test/bsg_nonsynth_profiler.sv - bsg_test/bsg_nonsynth_reset_gen.sv - bsg_test/bsg_nonsynth_sha256.sv file_type: systemVerilogSource nonsynth: files: - bsg_mem/bsg_mem_dma.cpp - bsg_test/bsg_dramsim3.cpp - bsg_test/bsg_nonsynth_dpi_clock_gen.cpp - bsg_test/bsg_ramulator_hbm.cpp file_type: cppSource provider: name: github user: bespoke-silicon-group repo: basejump_stl version: v0.0.1