{ "cells": [ { "cell_type": "code", "execution_count": 1, "id": "2a18229d-090c-4ef2-9abd-cdc5ddbc8e7e", "metadata": {}, "outputs": [], "source": [ "%load_ext pytest_notebook.ipy_magic" ] }, { "cell_type": "code", "execution_count": 4, "id": "2b8c2905-f313-436b-acea-90c7b4383080", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "\u001b[1m============================= test session starts ==============================\u001b[0m\n", "platform linux -- Python 3.10.0, pytest-8.2.0, pluggy-1.5.0 -- /usr/local/bin/python\n", "cachedir: .pytest_cache\n", "rootdir: /tmp/tmpswkjgwvd\n", "configfile: pytest.ini\n", "plugins: pytest_notebook-0.10.0, anyio-4.3.0\n", "\u001b[1mcollecting ... \u001b[0mcollected 31 items\n", "\n", "test_ipycell.py::test_howto[arrays.ipynb] \u001b[32mPASSED\u001b[0m\u001b[32m [ 3%]\u001b[0m\n", "test_ipycell.py::test_howto[basics.ipynb] \u001b[32mPASSED\u001b[0m\u001b[33m [ 6%]\u001b[0m\n", "test_ipycell.py::test_howto[blinky.ipynb] \u001b[32mPASSED\u001b[0m\u001b[33m [ 9%]\u001b[0m\n", "test_ipycell.py::test_howto[co-verification.ipynb] \u001b[32mPASSED\u001b[0m\u001b[33m [ 12%]\u001b[0m\n", "test_ipycell.py::test_howto[cyrite_memories.ipynb] \u001b[32mPASSED\u001b[0m\u001b[33m [ 16%]\u001b[0m\n", "test_ipycell.py::test_howto[extensions.ipynb] \u001b[32mPASSED\u001b[0m\u001b[33m [ 19%]\u001b[0m\n", "test_ipycell.py::test_howto[fsm_counter.ipynb] \u001b[32mPASSED\u001b[0m\u001b[33m [ 22%]\u001b[0m\n", "test_ipycell.py::test_howto[generators.ipynb] \u001b[32mPASSED\u001b[0m\u001b[33m [ 25%]\u001b[0m\n", "test_ipycell.py::test_howto[library.ipynb] \u001b[31mFAILED\u001b[0m\u001b[31m [ 29%]\u001b[0m\n", "test_ipycell.py::test_howto[methods.ipynb] \u001b[31mFAILED\u001b[0m\u001b[31m [ 32%]\u001b[0m\n", "test_ipycell.py::test_howto[operations.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 35%]\u001b[0m\n", "test_ipycell.py::test_howto[ports.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 38%]\u001b[0m\n", "test_ipycell.py::test_howto[rtlil.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 41%]\u001b[0m\n", "test_ipycell.py::test_howto[sim_intro.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 45%]\u001b[0m\n", "test_ipycell.py::test_howto[signals_interfaces.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 48%]\u001b[0m\n", "test_ipycell.py::test_howto[simulation.ipynb] \u001b[31mFAILED\u001b[0m\u001b[31m [ 51%]\u001b[0m\n", "test_ipycell.py::test_howto[stdlogic.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 54%]\u001b[0m\n", "test_ipycell.py::test_howto[xclkdomain.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 58%]\u001b[0m\n", "test_ipycell.py::test_examples[example_fsm_hysteresis.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 61%]\u001b[0m\n", "test_ipycell.py::test_examples[fun_stuff.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 64%]\u001b[0m\n", "test_ipycell.py::test_examples[generator_functions.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 67%]\u001b[0m\n", "test_ipycell.py::test_examples[gray_counter.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 70%]\u001b[0m\n", "test_ipycell.py::test_examples[advanced_generators.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 74%]\u001b[0m\n", "test_ipycell.py::test_examples[conditional_pitfalls.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 77%]\u001b[0m\n", "test_ipycell.py::test_examples[pipeline_generators.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 80%]\u001b[0m\n", "test_ipycell.py::test_examples[codec10b8b.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 83%]\u001b[0m\n", "test_ipycell.py::test_examples[soc_auxiliaries.ipynb] \u001b[31mFAILED\u001b[0m\u001b[31m [ 87%]\u001b[0m\n", "test_ipycell.py::test_examples[crc.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 90%]\u001b[0m\n", "test_ipycell.py::test_examples[tdpram.ipynb] \u001b[31mFAILED\u001b[0m\u001b[31m [ 93%]\u001b[0m\n", "test_ipycell.py::test_examples[example_barrelshifter.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [ 96%]\u001b[0m\n", "test_ipycell.py::test_examples[composite_classes.ipynb] \u001b[32mPASSED\u001b[0m\u001b[31m [100%]\u001b[0m\n", "\n", "=================================== FAILURES ===================================\n", "\u001b[31m\u001b[1m__________________________ test_howto[library.ipynb] ___________________________\u001b[0m\n", "\n", "nb_regression = NBRegressionFixture(exec_notebook=True, exec_cwd='/home/pyosys/src/myhdl2/myhdl.v2we/howto', exec_allow_errors=False, ... diff_ignore=('/cells/*/outputs/*/data/image/svg+xml',), diff_use_color=True, diff_color_words=False, force_regen=True)\n", "uut = 'library.ipynb'\n", "\n", " \u001b[0m\u001b[37m@pytest\u001b[39;49;00m.mark.parametrize(\u001b[33m\"\u001b[39;49;00m\u001b[33muut\u001b[39;49;00m\u001b[33m\"\u001b[39;49;00m, HOWTO)\u001b[90m\u001b[39;49;00m\n", " \u001b[94mdef\u001b[39;49;00m \u001b[92mtest_howto\u001b[39;49;00m(nb_regression, uut):\u001b[90m\u001b[39;49;00m\n", " nb_regression.force_regen = \u001b[94mTrue\u001b[39;49;00m\u001b[90m\u001b[39;49;00m\n", " \u001b[90m\u001b[39;49;00m\n", " \u001b[94mwith\u001b[39;49;00m importlib_resources.path(howto, uut) \u001b[94mas\u001b[39;49;00m path:\u001b[90m\u001b[39;49;00m\n", "> nb_regression.check(\u001b[96mstr\u001b[39;49;00m(path))\u001b[90m\u001b[39;49;00m\n", "\u001b[1m\u001b[31mE pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-force-regen set, regenerating file at:\u001b[0m\n", "\u001b[1m\u001b[31mE - /home/pyosys/src/myhdl2/myhdl.v2we/howto/library.ipynb\u001b[0m\n", "\n", "\u001b[1m\u001b[31mtest_ipycell.py\u001b[0m:66: NBRegressionError\n", "----------------------------- Captured stdout call -----------------------------\n", "\n", "-- Running command `tee -q hierarchy -top \\unit' --\n", "\n", "-- Running command `tee -q show -format dot -prefix default unit' --\n", "----------------------------- Captured stderr call -----------------------------\n", "Diff before regeneration:\n", "\n", "--- expected\n", "+++ obtained\n", "\u001b[34m\u001b[1m## replaced /cells/17/execution_count:\u001b[0m\n", "\u001b[31m- 1\n", "\u001b[32m+ 8\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## replaced /cells/19/execution_count:\u001b[0m\n", "\u001b[31m- 2\n", "\u001b[32m+ 9\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## replaced /cells/19/outputs/0/execution_count:\u001b[0m\n", "\u001b[31m- 2\n", "\u001b[32m+ 9\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## replaced /cells/22/execution_count:\u001b[0m\n", "\u001b[31m- 3\n", "\u001b[32m+ 10\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## replaced /cells/23/execution_count:\u001b[0m\n", "\u001b[31m- 4\n", "\u001b[32m+ 11\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## replaced /cells/24/execution_count:\u001b[0m\n", "\u001b[31m- 5\n", "\u001b[32m+ 12\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## replaced /cells/25/execution_count:\u001b[0m\n", "\u001b[31m- 6\n", "\u001b[32m+ 13\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## replaced /cells/25/outputs/0/execution_count:\u001b[0m\n", "\u001b[31m- 6\n", "\u001b[32m+ 13\n", "\n", "\u001b[0m\n", "\u001b[31m\u001b[1m__________________________ test_howto[methods.ipynb] ___________________________\u001b[0m\n", "\n", "nb_regression = NBRegressionFixture(exec_notebook=True, exec_cwd='/home/pyosys/src/myhdl2/myhdl.v2we/howto', exec_allow_errors=False, ... diff_ignore=('/cells/*/outputs/*/data/image/svg+xml',), diff_use_color=True, diff_color_words=False, force_regen=True)\n", "uut = 'methods.ipynb'\n", "\n", " \u001b[0m\u001b[37m@pytest\u001b[39;49;00m.mark.parametrize(\u001b[33m\"\u001b[39;49;00m\u001b[33muut\u001b[39;49;00m\u001b[33m\"\u001b[39;49;00m, HOWTO)\u001b[90m\u001b[39;49;00m\n", " \u001b[94mdef\u001b[39;49;00m \u001b[92mtest_howto\u001b[39;49;00m(nb_regression, uut):\u001b[90m\u001b[39;49;00m\n", " nb_regression.force_regen = \u001b[94mTrue\u001b[39;49;00m\u001b[90m\u001b[39;49;00m\n", " \u001b[90m\u001b[39;49;00m\n", " \u001b[94mwith\u001b[39;49;00m importlib_resources.path(howto, uut) \u001b[94mas\u001b[39;49;00m path:\u001b[90m\u001b[39;49;00m\n", "> nb_regression.check(\u001b[96mstr\u001b[39;49;00m(path))\u001b[90m\u001b[39;49;00m\n", "\u001b[1m\u001b[31mE pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-force-regen set, regenerating file at:\u001b[0m\n", "\u001b[1m\u001b[31mE - /home/pyosys/src/myhdl2/myhdl.v2we/howto/methods.ipynb\u001b[0m\n", "\n", "\u001b[1m\u001b[31mtest_ipycell.py\u001b[0m:66: NBRegressionError\n", "----------------------------- Captured stderr call -----------------------------\n", "Diff before regeneration:\n", "\n", "--- expected\n", "+++ obtained\n", "\u001b[34m\u001b[1m## modified /cells/30/outputs/0/text:\u001b[0m\n", "\u001b[36m@@ -1,41 +1,41 @@\u001b[m\n", "\u001b[31m--- File generated from source:\u001b[m\n", "\u001b[31m-IPYKERNEL\u001b[m\n", "\u001b[31m--- (c) 2016-2022 section5.ch\u001b[m\n", "\u001b[31m--- Modifications may be lost, edit the source file instead.\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[31m-library IEEE;\u001b[m\n", "\u001b[31m-use IEEE.std_logic_1164.all;\u001b[m\n", "\u001b[31m-use IEEE.numeric_std.all;\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[31m-library work;\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[31m-use work.txt_util.all;\u001b[m\n", "\u001b[31m-use work.myirl_conversion.all;\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[31m-entity tb is\u001b[m\n", "\u001b[31m-end entity tb;\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[31m-architecture cyriteHDL of tb is\u001b[m\n", "\u001b[31m- -- Local type declarations\u001b[m\n", "\u001b[31m- -- Signal declarations\u001b[m\n", "\u001b[31m- signal s_19c7 : unsigned(7 downto 0);\u001b[m\n", "\u001b[31m- signal q : unsigned(7 downto 0);\u001b[m\n", "\u001b[31m- signal b : unsigned(7 downto 0);\u001b[m\n", "\u001b[31m- signal a : unsigned(7 downto 0);\u001b[m\n", "\u001b[31m- signal en : std_ulogic;\u001b[m\n", "\u001b[31m-begin\u001b[m\n", "\u001b[31m- \u001b[m\n", "\u001b[31m-ff:\u001b[m\n", "\u001b[31m- process(clk)\u001b[m\n", "\u001b[31m- begin\u001b[m\n", "\u001b[31m- if rising_edge(clk) then\u001b[m\n", "\u001b[31m- if (en = '1') then\u001b[m\n", "\u001b[31m- s_19c7 <= a;\u001b[m\n", "\u001b[31m- else\u001b[m\n", "\u001b[31m- s_19c7 <= b;\u001b[m\n", "\u001b[31m- end if;\u001b[m\n", "\u001b[31m- q <= s_19c7;\u001b[m\n", "\u001b[31m- end if;\u001b[m\n", "\u001b[31m- end process;\u001b[m\n", "\u001b[31m-end architecture cyriteHDL;\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[m2m+\u001b[m\u001b[32m-- File generated from source:\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mIPYKERNEL\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m-- (c) 2016-2022 section5.ch\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m-- Modifications may be lost, edit the source file instead.\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mlibrary IEEE;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32muse IEEE.std_logic_1164.all;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32muse IEEE.numeric_std.all;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mlibrary work;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32muse work.txt_util.all;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32muse work.myirl_conversion.all;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mentity tb is\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mend entity tb;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32marchitecture cyriteHDL of tb is\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m -- Local type declarations\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m -- Signal declarations\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m signal s_19c7 : unsigned(7 downto 0);\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m signal q : unsigned(7 downto 0);\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m signal b : unsigned(7 downto 0);\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m signal a : unsigned(7 downto 0);\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m signal en : std_ulogic;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mbegin\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m \n", "\u001b[m2m+\u001b[m\u001b[32mff:\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m process(clk)\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m begin\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m if rising_edge(clk) then\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m if (en = '1') then\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m s_19c7 <= a;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m else\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m s_19c7 <= b;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m end if;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m q <= s_19c7;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m end if;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m end process;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mend architecture cyriteHDL;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m\n", "\n", "\u001b[0m\n", "\u001b[31m\u001b[1m_________________________ test_howto[simulation.ipynb] _________________________\u001b[0m\n", "\n", "nb_regression = NBRegressionFixture(exec_notebook=True, exec_cwd='/home/pyosys/src/myhdl2/myhdl.v2we/howto', exec_allow_errors=False, ... diff_ignore=('/cells/*/outputs/*/data/image/svg+xml',), diff_use_color=True, diff_color_words=False, force_regen=True)\n", "uut = 'simulation.ipynb'\n", "\n", " \u001b[0m\u001b[37m@pytest\u001b[39;49;00m.mark.parametrize(\u001b[33m\"\u001b[39;49;00m\u001b[33muut\u001b[39;49;00m\u001b[33m\"\u001b[39;49;00m, HOWTO)\u001b[90m\u001b[39;49;00m\n", " \u001b[94mdef\u001b[39;49;00m \u001b[92mtest_howto\u001b[39;49;00m(nb_regression, uut):\u001b[90m\u001b[39;49;00m\n", " nb_regression.force_regen = \u001b[94mTrue\u001b[39;49;00m\u001b[90m\u001b[39;49;00m\n", " \u001b[90m\u001b[39;49;00m\n", " \u001b[94mwith\u001b[39;49;00m importlib_resources.path(howto, uut) \u001b[94mas\u001b[39;49;00m path:\u001b[90m\u001b[39;49;00m\n", "> nb_regression.check(\u001b[96mstr\u001b[39;49;00m(path))\u001b[90m\u001b[39;49;00m\n", "\u001b[1m\u001b[31mE pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-force-regen set, regenerating file at:\u001b[0m\n", "\u001b[1m\u001b[31mE - /home/pyosys/src/myhdl2/myhdl.v2we/howto/simulation.ipynb\u001b[0m\n", "\n", "\u001b[1m\u001b[31mtest_ipycell.py\u001b[0m:66: NBRegressionError\n", "----------------------------- Captured stdout call -----------------------------\n", "\n", "-- Running command `tee -q hierarchy -top \\unit_3' --\n", "\n", "-- Running command `tee -q write_cxxrtl -namespace unit -header /tmp/myirl_test_q1fo8nls/unit_rtl.cpp' --\n", "----------------------------- Captured stderr call -----------------------------\n", "Diff before regeneration:\n", "\n", "--- expected\n", "+++ obtained\n", "\u001b[34m\u001b[1m## modified /cells/6/outputs/0/name:\u001b[0m\n", "\u001b[31m- stderr\n", "\u001b[32m+ stdout\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/6/outputs/0/text:\u001b[0m\n", "\u001b[36m@@ -1,2 +1,3 @@\u001b[m\n", "\u001b[31m-HOMEDIRcomponents.py:116: UserWarning: Fallback: Pass through other argument for arg clkname ()\u001b[m\n", "\u001b[31m- base.warnings.warn(msg)\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Creating library file module_defs.vhdl\u001b[m\u001b[41m \u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/6/outputs/1/name:\u001b[0m\n", "\u001b[31m- stdout\n", "\u001b[32m+ stderr\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/6/outputs/1/text:\u001b[0m\n", "\u001b[36m@@ -1,3 +1,2 @@\u001b[m\n", "\u001b[31m-TMPDIR\u001b[m\n", "\u001b[31m-TMPDIR\u001b[m\n", "\u001b[31m- Creating library file module_defs.vhdl \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRcomponents.py:116: UserWarning: Fallback: Pass through other argument for arg clkname ()\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m base.warnings.warn(msg)\u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/28/outputs/0/text:\u001b[0m\n", "\u001b[36m@@ -4,3 +4,13 @@\u001b[m \u001b[mDEBUG MAIN ELAB [Instance unit_3 I/F: [// ID: unit_0 ]]\u001b[m\n", " DEBUG components ['unitu_1u_1u_8u_8'] (TestDesign 'test') \u001b[m\n", " \u001b[32m Adding module with name `unit_3` \u001b[0m\u001b[m\n", " \u001b[7;34m FINALIZE implementation `unit_3` of `unit` \u001b[0m\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mrunning build_ext\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mbuilding 'runtime.unit' extension\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mcopying build/lib.linux-x86_64-3.10/runtime/unit.cpython-310-x86_64-linux-gnu.so -> runtime\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mOpen for writing: tb_unitx.vcd\u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/28/outputs/1/text:\u001b[0m\n", "\u001b[36m@@ -1 +1,2 @@\u001b[m\n", " TMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m\u001b[7;34mSTOP SIMULATION @117\u001b[0m\u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## inserted before /cells/28/outputs/2:\u001b[0m\n", "\u001b[32m+ output:\n", "\u001b[32m+ output_type: execute_result\n", "\u001b[32m+ execution_count: 13\n", "\u001b[32m+ data:\n", "\u001b[32m+ text/plain: 0\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## deleted /cells/28/outputs/2:\u001b[0m\n", "\u001b[31m- output:\n", "\u001b[31m- output_type: stream\n", "\u001b[31m- name: stdout\n", "\u001b[31m- text:\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- running build_ext\n", "\u001b[31m- building 'runtime.unit' extension\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- copying build/lib.linux-x86_64-3.10/runtime/unit.cpython-310-x86_64-linux-gnu.so -> runtime\n", "\u001b[31m- Open for writing: tb_unitx.vcd\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## deleted /cells/28/outputs/5-6:\u001b[0m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/33/outputs/0/name:\u001b[0m\n", "\u001b[31m- stderr\n", "\u001b[32m+ stdout\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/33/outputs/0/text:\u001b[0m\n", "\u001b[36m@@ -1,4 +1,16 @@\u001b[m\n", "\u001b[31m-HOMEDIRcomponents.py:116: UserWarning: Fallback: Pass through other argument for arg VALUES ()\u001b[m\n", "\u001b[31m- base.warnings.warn(msg)\u001b[m\n", "\u001b[31m-HOMEDIR_types.py:112: UserWarning: Implicit sign conversion <= ADD(SGN(), SGN())\u001b[m\n", "\u001b[31m- base.warnings.warn(\"Implicit sign conversion %s <= %s\" % (repr(self), repr(v)))\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Writing 'testbench' to file /tmp/testbench.vhdl\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Creating library file /tmp/module_defs.vhdl\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRtxt_util.vhdl']\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m==== COSIM stdout ====\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRtxt_util.vhdl\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRlibmyirl.vhdl\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32manalyze /tmp/testbench.vhdl\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32melaborate testbench\u001b[m\n", "\u001b[32m+\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m==== COSIM stdout ====\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTesting Values 0x40 0x40 0x80\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTesting Values 0x70 0x8F 0xFF\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTesting Values 0x80 0x80 0x00\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTesting Values 0x8F 0x70 0xFF\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32msimulation stopped @48ns\u001b[m\n", "\u001b[41m+\u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/33/outputs/1/name:\u001b[0m\n", "\u001b[31m- stdout\n", "\u001b[32m+ stderr\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/33/outputs/1/text:\u001b[0m\n", "\u001b[36m@@ -1,16 +1,4 @@\u001b[m\n", "\u001b[31m- Writing 'testbench' to file /tmp/testbench.vhdl \u001b[m\n", "\u001b[31m- Creating library file /tmp/module_defs.vhdl \u001b[m\n", "\u001b[31m-HOMEDIRtxt_util.vhdl']\u001b[m\n", "\u001b[31m-==== COSIM stdout ====\u001b[m\n", "\u001b[31m-HOMEDIRtxt_util.vhdl\u001b[m\n", "\u001b[31m-HOMEDIRlibmyirl.vhdl\u001b[m\n", "\u001b[31m-analyze /tmp/testbench.vhdl\u001b[m\n", "\u001b[31m-elaborate testbench\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[31m-==== COSIM stdout ====\u001b[m\n", "\u001b[31m-Testing Values 0x40 0x40 0x80\u001b[m\n", "\u001b[31m-Testing Values 0x70 0x8F 0xFF\u001b[m\n", "\u001b[31m-Testing Values 0x80 0x80 0x00\u001b[m\n", "\u001b[31m-Testing Values 0x8F 0x70 0xFF\u001b[m\n", "\u001b[31m-simulation stopped @48ns\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRcomponents.py:116: UserWarning: Fallback: Pass through other argument for arg VALUES ()\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m base.warnings.warn(msg)\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIR_types.py:112: UserWarning: Implicit sign conversion <= ADD(SGN(), SGN())\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m base.warnings.warn(\"Implicit sign conversion %s <= %s\" % (repr(self), repr(v)))\u001b[m\n", "\n", "\u001b[0m\n", "\u001b[31m\u001b[1m_____________________ test_examples[soc_auxiliaries.ipynb] _____________________\u001b[0m\n", "\n", "nb_regression = NBRegressionFixture(exec_notebook=True, exec_cwd='/home/pyosys/src/myhdl2/myhdl.v2we/examples', exec_allow_errors=Fals... diff_ignore=('/cells/*/outputs/*/data/image/svg+xml',), diff_use_color=True, diff_color_words=False, force_regen=True)\n", "uut = 'soc_auxiliaries.ipynb'\n", "\n", " \u001b[0m\u001b[37m@pytest\u001b[39;49;00m.mark.parametrize(\u001b[33m\"\u001b[39;49;00m\u001b[33muut\u001b[39;49;00m\u001b[33m\"\u001b[39;49;00m, EXAMPLES)\u001b[90m\u001b[39;49;00m\n", " \u001b[94mdef\u001b[39;49;00m \u001b[92mtest_examples\u001b[39;49;00m(nb_regression, uut):\u001b[90m\u001b[39;49;00m\n", " nb_regression.force_regen = \u001b[94mTrue\u001b[39;49;00m\u001b[90m\u001b[39;49;00m\n", " \u001b[90m\u001b[39;49;00m\n", " \u001b[94mwith\u001b[39;49;00m importlib_resources.path(examples, uut) \u001b[94mas\u001b[39;49;00m path:\u001b[90m\u001b[39;49;00m\n", "> nb_regression.check(\u001b[96mstr\u001b[39;49;00m(path))\u001b[90m\u001b[39;49;00m\n", "\u001b[1m\u001b[31mE pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-force-regen set, regenerating file at:\u001b[0m\n", "\u001b[1m\u001b[31mE - /home/pyosys/src/myhdl2/myhdl.v2we/examples/soc_auxiliaries.ipynb\u001b[0m\n", "\n", "\u001b[1m\u001b[31mtest_ipycell.py\u001b[0m:73: NBRegressionError\n", "----------------------------- Captured stdout call -----------------------------\n", "\n", "-- Running command `ls; check' --\n", "\n", "1. Executing CHECK pass (checking for obvious problems).\n", "Found and reported 0 problems.\n", "\n", "-- Running command `hierarchy -check' --\n", "\n", "2. Executing HIERARCHY pass (managing design hierarchy).\n", "\n", "-- Running command `write_verilog debug.v' --\n", "\n", "3. Executing Verilog backend.\n", "\n", "3.1. Executing BMUXMAP pass.\n", "\n", "3.2. Executing DEMUXMAP pass.\n", "Dumping module `\\mmr_decode'.\n", "\n", "-- Running command `tee -q write_cxxrtl -namespace mmr_decode_2cc0 -header /tmp/myirl_mmr_fhw1y82_/mmr_decode_2cc0_rtl.cpp' --\n", "\n", "-- Running command `tee -q read_verilog -lib -specify /usr/share/yosys/ecp5/cells_sim.v /usr/share/yosys/ecp5/cells_bb.v' --\n", "\n", "-- Running command `tee -q hierarchy -check' --\n", "\n", "-- Running command `tee -q proc' --\n", "\n", "-- Running command `tee -q flatten' --\n", "\n", "-- Running command `tee -q tribuf -logic' --\n", "\n", "-- Running command `tee -q deminout' --\n", "\n", "-- Running command `tee -q opt_expr' --\n", "\n", "-- Running command `tee -q debug opt_clean' --\n", "\n", "-- Running command `tee -q check' --\n", "\n", "-- Running command `tee -q opt' --\n", "\n", "-- Running command `tee -q wreduce' --\n", "\n", "-- Running command `tee -q peepopt' --\n", "\n", "-- Running command `tee -q opt_clean' --\n", "\n", "-- Running command `tee -q share' --\n", "\n", "-- Running command `tee -q techmap -map /usr/share/yosys/cmp2lut.v -D LUT_WIDTH=4' --\n", "\n", "-- Running command `tee -q opt_expr' --\n", "\n", "-- Running command `tee -q opt_clean' --\n", "\n", "-- Running command `tee -q opt' --\n", "\n", "-- Running command `tee -q fsm' --\n", "\n", "-- Running command `tee -q opt -fast' --\n", "\n", "-- Running command `tee -q memory -nomap' --\n", "\n", "-- Running command `tee -q opt_clean' --\n", "\n", "-- Running command `tee -q memory_libmap -lib /usr/share/yosys/ecp5/lutrams.txt -lib /usr/share/yosys/ecp5/brams.txt' --\n", "\n", "-- Running command `tee -q techmap -map /usr/share/yosys/techmap.v -map /usr/share/yosys/ecp5/arith_map.v' --\n", "\n", "-- Running command `tee -q techmap -map /usr/share/yosys/ecp5/cells_map.v' --\n", "\n", "-- Running command `tee -q opt_expr -undriven -mux_undef' --\n", "\n", "-- Running command `tee -q simplemap;' --\n", "\n", "-- Running command `tee -q opt_clean' --\n", "\n", "-- Running command `stat' --\n", "\n", "34. Printing statistics.\n", "\n", "=== mmr_decode ===\n", "\n", " Number of wires: 61\n", " Number of wire bits: 274\n", " Number of public wires: 24\n", " Number of public wire bits: 162\n", " Number of memories: 0\n", " Number of memory bits: 0\n", " Number of processes: 0\n", " Number of cells: 166\n", " $_AND_ 30\n", " $_NOT_ 13\n", " $_OR_ 57\n", " TRELLIS_FF 66\n", "\n", "----------------------------- Captured stderr call -----------------------------\n", "Diff before regeneration:\n", "\n", "--- expected\n", "+++ obtained\n", "\u001b[34m\u001b[1m## deleted /cells/13/outputs/3:\u001b[0m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/14/outputs/0/text:\u001b[0m\n", "\u001b[36m@@ -1 +1,20 @@\u001b[m\n", " DEBUG components ['mmr_decode_obj_SimMMRu_1u_1u_12u_1u_16u_16_d_1_2_4_5'] (SimMMR 'mmr') \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mrunning build_ext\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mbuilding 'runtime.mmr_decode_2cc0' extension\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mTMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mcopying build/lib.linux-x86_64-3.10/runtime/mmr_decode_2cc0.cpython-310-x86_64-linux-gnu.so -> runtime\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mOpen for writing: mmr.vcd\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m\u001b[7;35m CXXRTL context: SKIP INTERFACE ITEM `self` \u001b[0m\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m\u001b[7;35m CXXRTL context: SKIP INTERFACE ITEM `REGDESC` \u001b[0m\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mSTART\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mDEBUG RESUME PROCESS main\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mDONE RESET\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mSETTING stat.read\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mVAL : False\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mDEBUG RESUME PROCESS main\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mDONE\u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/14/outputs/1/text:\u001b[0m\n", "\u001b[36m@@ -1 +1,3 @@\u001b[m\n", " TMPDIR\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m\u001b[32mCosimulation: debug not connected to backend\u001b[0m\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m\u001b[7;34mSTOP SIMULATION @88\u001b[0m\u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## inserted before /cells/14/outputs/2:\u001b[0m\n", "\u001b[32m+ output:\n", "\u001b[32m+ output_type: execute_result\n", "\u001b[32m+ execution_count: 7\n", "\u001b[32m+ data:\n", "\u001b[32m+ text/plain: 0\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## deleted /cells/14/outputs/2:\u001b[0m\n", "\u001b[31m- output:\n", "\u001b[31m- output_type: stream\n", "\u001b[31m- name: stdout\n", "\u001b[31m- text:\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- running build_ext\n", "\u001b[31m- building 'runtime.mmr_decode_2cc0' extension\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- TMPDIR\n", "\u001b[31m- copying build/lib.linux-x86_64-3.10/runtime/mmr_decode_2cc0.cpython-310-x86_64-linux-gnu.so -> runtime\n", "\u001b[31m- Open for writing: mmr.vcd\n", "\u001b[31m- \u001b[7;35m CXXRTL context: SKIP INTERFACE ITEM `self` \u001b[0m\n", "\u001b[31m- \u001b[7;35m CXXRTL context: SKIP INTERFACE ITEM `REGDESC` \u001b[0m\n", "\u001b[31m- START\n", "\u001b[31m- DEBUG RESUME PROCESS main\n", "\u001b[31m- DONE RESET\n", "\u001b[31m- SETTING stat.read\n", "\u001b[31m- VAL : False\n", "\u001b[31m- DEBUG RESUME PROCESS main\n", "\u001b[31m- DONE\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## deleted /cells/14/outputs/5-6:\u001b[0m\n", "\n", "\u001b[0m\n", "\u001b[31m\u001b[1m_________________________ test_examples[tdpram.ipynb] __________________________\u001b[0m\n", "\n", "nb_regression = NBRegressionFixture(exec_notebook=True, exec_cwd='/home/pyosys/src/myhdl2/myhdl.v2we/examples', exec_allow_errors=Fals... diff_ignore=('/cells/*/outputs/*/data/image/svg+xml',), diff_use_color=True, diff_color_words=False, force_regen=True)\n", "uut = 'tdpram.ipynb'\n", "\n", " \u001b[0m\u001b[37m@pytest\u001b[39;49;00m.mark.parametrize(\u001b[33m\"\u001b[39;49;00m\u001b[33muut\u001b[39;49;00m\u001b[33m\"\u001b[39;49;00m, EXAMPLES)\u001b[90m\u001b[39;49;00m\n", " \u001b[94mdef\u001b[39;49;00m \u001b[92mtest_examples\u001b[39;49;00m(nb_regression, uut):\u001b[90m\u001b[39;49;00m\n", " nb_regression.force_regen = \u001b[94mTrue\u001b[39;49;00m\u001b[90m\u001b[39;49;00m\n", " \u001b[90m\u001b[39;49;00m\n", " \u001b[94mwith\u001b[39;49;00m importlib_resources.path(examples, uut) \u001b[94mas\u001b[39;49;00m path:\u001b[90m\u001b[39;49;00m\n", "> nb_regression.check(\u001b[96mstr\u001b[39;49;00m(path))\u001b[90m\u001b[39;49;00m\n", "\u001b[1m\u001b[31mE pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-force-regen set, regenerating file at:\u001b[0m\n", "\u001b[1m\u001b[31mE - /home/pyosys/src/myhdl2/myhdl.v2we/examples/tdpram.ipynb\u001b[0m\n", "\n", "\u001b[1m\u001b[31mtest_ipycell.py\u001b[0m:73: NBRegressionError\n", "----------------------------- Captured stderr call -----------------------------\n", "Diff before regeneration:\n", "\n", "--- expected\n", "+++ obtained\n", "\u001b[34m\u001b[1m## modified /cells/15/outputs/0/text:\u001b[0m\n", "\u001b[36m@@ -1,48 +1,48 @@\u001b[m\n", "\u001b[31m-// File generated from source:\u001b[m\n", "\u001b[31m-IPYKERNEL\u001b[m\n", "\u001b[31m-// (c) 2016-2022 section5.ch\u001b[m\n", "\u001b[31m-// Modifications may be lost, edit the source file instead.\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[31m-`timescale 1 ns / 1 ps\u001b[m\n", "\u001b[31m-`include \"aux.v\"\u001b[m\n", "\u001b[31m-// Architecture myIRL\u001b[m\n", "\u001b[31m-\u001b[m\n", "\u001b[31m-module tdp_ram_1\u001b[m\n", "\u001b[31m- (\u001b[m\n", "\u001b[31m- input wire pa_clk,\u001b[m\n", "\u001b[31m- input wire pa_we,\u001b[m\n", "\u001b[31m- input wire [8:0] pa_ra,\u001b[m\n", "\u001b[31m- input wire [8:0] pa_wa,\u001b[m\n", "\u001b[31m- output wire [7:0] pa_rd,\u001b[m\n", "\u001b[31m- input wire [7:0] pa_wd,\u001b[m\n", "\u001b[31m- input wire pb_clk,\u001b[m\n", "\u001b[31m- input wire pb_we,\u001b[m\n", "\u001b[31m- input wire [8:0] pb_ra,\u001b[m\n", "\u001b[31m- input wire [8:0] pb_wa,\u001b[m\n", "\u001b[31m- output wire [7:0] pb_rd,\u001b[m\n", "\u001b[31m- input wire [7:0] pb_wd\u001b[m\n", "\u001b[31m- );\u001b[m\n", "\u001b[31m- // Local type declarations\u001b[m\n", "\u001b[31m- // Signal declarations\u001b[m\n", "\u001b[31m- reg [7:0] rd0;\u001b[m\n", "\u001b[31m- reg [7:0] v_6288[511:0];\u001b[m\n", "\u001b[31m- initial begin\u001b[m\n", "\u001b[31m- end\u001b[m\n", "\u001b[31m- reg [7:0] rd1;\u001b[m\n", "\u001b[31m- \u001b[m\n", "\u001b[31m- always @ (posedge pa_clk ) begin : PROC0\u001b[m\n", "\u001b[31m- if ((pa_we == 1'b1)) begin\u001b[m\n", "\u001b[31m- v_6288[pa_wa] <= pa_wd;\u001b[m\n", "\u001b[31m- end\u001b[m\n", "\u001b[31m- rd0 <= v_6288[pa_ra];\u001b[m\n", "\u001b[31m- end\u001b[m\n", "\u001b[31m- assign pa_rd = rd0;\u001b[m\n", "\u001b[31m- \u001b[m\n", "\u001b[31m- always @ (posedge pb_clk ) begin : PROC1\u001b[m\n", "\u001b[31m- if ((pb_we == 1'b1)) begin\u001b[m\n", "\u001b[31m- v_6288[pb_wa] <= pb_wd;\u001b[m\n", "\u001b[31m- end\u001b[m\n", "\u001b[31m- rd1 <= v_6288[pb_ra];\u001b[m\n", "\u001b[31m- end\u001b[m\n", "\u001b[31m- assign pb_rd = rd1;\u001b[m\n", "\u001b[31m-endmodule // tdp_ram_1\u001b[m\n", "\u001b[m2m+\u001b[m\u001b[32m// File generated from source:\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mIPYKERNEL\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m// (c) 2016-2022 section5.ch\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m// Modifications may be lost, edit the source file instead.\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m`timescale 1 ns / 1 ps\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m`include \"aux.v\"\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m// Architecture myIRL\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mmodule tdp_ram_1\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m (\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire pa_clk,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire pa_we,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire [8:0] pa_ra,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire [8:0] pa_wa,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m output wire [7:0] pa_rd,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire [7:0] pa_wd,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire pb_clk,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire pb_we,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire [8:0] pb_ra,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire [8:0] pb_wa,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m output wire [7:0] pb_rd,\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m input wire [7:0] pb_wd\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m );\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m // Local type declarations\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m // Signal declarations\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m reg [7:0] rd0;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m reg [7:0] v_6288[511:0];\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m initial begin\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m end\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m reg [7:0] rd1;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m \n", "\u001b[m2m+\u001b[m\u001b[32m always @ (posedge pa_clk ) begin : PROC0\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m if ((pa_we == 1'b1)) begin\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m v_6288[pa_wa] <= pa_wd;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m end\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m rd0 <= v_6288[pa_ra];\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m end\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m assign pa_rd = rd0;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[41m \n", "\u001b[m2m+\u001b[m\u001b[32m always @ (posedge pb_clk ) begin : PROC1\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m if ((pb_we == 1'b1)) begin\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m v_6288[pb_wa] <= pb_wd;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m end\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m rd1 <= v_6288[pb_ra];\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m end\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32m assign pb_rd = rd1;\u001b[m\u001b[41m\n", "\u001b[m2m+\u001b[m\u001b[32mendmodule // tdp_ram_1\u001b[m\u001b[41m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/19/outputs/0/text:\u001b[0m\n", "\u001b[36m@@ -15,3 +15,27 @@\u001b[m \u001b[mDEBUG: INSTANCING uut with wmode = WRITETHROUGH\u001b[m\n", " DELTA: use default 0.2 \u001b[m\n", " DELTA: use default 0.2 \u001b[m\n", " DELTA: use default 0.2 \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Writing 'gray_counter' to file /tmp/gray_counter.v\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Writing 'tdpram' to file /tmp/tdpram.v\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mDEBUG: Source 'v_0bf9' is logic: \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Writing 'tdpram_wrapper' to file /tmp/tdpram_wrapper.v\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Writing 'clkpulse' to file /tmp/clkpulse.v\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Writing 'coincidence_prio' to file /tmp/coincidence_prio.v\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Writing 'trigger_pulse' to file /tmp/trigger_pulse.v\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Writing 'tb_priorities' to file /tmp/tb_priorities.v\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mWarning: Implicit truncation of ADD(a_addr_auto, C:1) result\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mWarning: Implicit truncation of ADD(b_addr_auto, C:1) result\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Note: Changing library path prefix to /tmp/\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m Creating library file /tmp/module_defs.v\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mDEBUG FILES ['/tmp/gray_counter.v', '/tmp/tdpram.v', '/tmp/tdpram_wrapper.v', '/tmp/clkpulse.v', '/tmp/coincidence_prio.v', '/tmp/trigger_pulse.v', '/tmp/tb_priorities.v']\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m==== COSIM stdout ====\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mVCD info: dumpfile tb_priorities.vcd opened for output.\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mis: 0x640f wants: 0x640f\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mis: 0xab82 wants: 0xab82\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mis: 0xa957 wants: 0xa957\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mRUN WRITE SEQUENCE...\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m====== REPORT ======\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mCoincidence occured. GOOD.\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mCoincidence detected. GOOD.\u001b[m\u001b[41m \u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mStop Simulation\u001b[m\n", "\u001b[41m+\u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## modified /cells/19/outputs/1/text:\u001b[0m\n", "\u001b[36m@@ -8,3 +8,13 @@\u001b[m \u001b[mHOMEDIRcomponents.py:116: UserWarning: Fallback: Pass through other argument for\u001b[m\n", " \u001b[32mDEBUG IGNORING SET INIT FOR CLKSIGNAL\u001b[0m\u001b[m\n", " HOMEDIRicarus.py:50: UserWarning: Ignoring wavetrace argument for Verilog simulator\u001b[m\n", " warnings.warn(\"Ignoring wavetrace argument for Verilog simulator\")\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m\u001b[32mDEBUG IGNORING SET INIT FOR CLKSIGNAL\u001b[0m\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRverilog.py:1710: UserWarning: Possible clock forwarding `bc_8233_clk`\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m warnings.warn(\"Possible clock forwarding `%s`\" % n)\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m\u001b[32mDEBUG IGNORING SET INIT FOR CLKSIGNAL\u001b[0m\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRverilog.py:1710: UserWarning: Possible clock forwarding `bc_f268_clk`\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m warnings.warn(\"Possible clock forwarding `%s`\" % n)\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRverilog.py:1626: UserWarning: Renaming reserved identifier: reg -> reg_8ef0\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m warnings.warn(\"Renaming reserved identifier: %s -> %s\" % \\\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32mHOMEDIRverilog.py:1626: UserWarning: Renaming reserved identifier: reg -> reg_f03d\u001b[m\n", "\u001b[32m+\u001b[m\u001b[32m warnings.warn(\"Renaming reserved identifier: %s -> %s\" % \\\u001b[m\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## inserted before /cells/19/outputs/2:\u001b[0m\n", "\u001b[32m+ output:\n", "\u001b[32m+ output_type: execute_result\n", "\u001b[32m+ execution_count: 13\n", "\u001b[32m+ data:\n", "\u001b[32m+ text/plain: 0\n", "\n", "\u001b[0m\u001b[34m\u001b[1m## deleted /cells/19/outputs/2:\u001b[0m\n", "\u001b[31m- output:\n", "\u001b[31m- output_type: stream\n", "\u001b[31m- name: stdout\n", "\u001b[31m- text:\n", "\u001b[31m- Writing 'gray_counter' to file /tmp/gray_counter.v \n", "\u001b[31m- Writing 'tdpram' to file /tmp/tdpram.v \n", "\u001b[31m- DEBUG: Source 'v_0bf9' is logic: \n", "\u001b[31m- Writing 'tdpram_wrapper' to file /tmp/tdpram_wrapper.v \n", "\u001b[31m- Writing 'clkpulse' to file /tmp/clkpulse.v \n", "\u001b[31m- Writing 'coincidence_prio' to file /tmp/coincidence_prio.v \n", "\u001b[31m- Writing 'trigger_pulse' to file /tmp/trigger_pulse.v \n", "\u001b[31m- Writing 'tb_priorities' to file /tmp/tb_priorities.v \n", "\u001b[31m- Warning: Implicit truncation of ADD(a_addr_auto, C:1) result\n", "\u001b[31m- Warning: Implicit truncation of ADD(b_addr_auto, C:1) result\n", "\u001b[31m- Note: Changing library path prefix to /tmp/ \n", "\u001b[31m- Creating library file /tmp/module_defs.v \n", "\u001b[31m- DEBUG FILES ['/tmp/gray_counter.v', '/tmp/tdpram.v', '/tmp/tdpram_wrapper.v', '/tmp/clkpulse.v', '/tmp/coincidence_prio.v', '/tmp/trigger_pulse.v', '/tmp/tb_priorities.v']\n", "\u001b[31m- ==== COSIM stdout ====\n", "\u001b[31m- VCD info: dumpfile tb_priorities.vcd opened for output.\n", "\u001b[31m- is: 0x640f wants: 0x640f \n", "\u001b[31m- is: 0xab82 wants: 0xab82 \n", "\u001b[31m- is: 0xa957 wants: 0xa957 \n", "\u001b[31m- RUN WRITE SEQUENCE... \n", "\u001b[31m- ====== REPORT ====== \n", "\u001b[31m- Coincidence occured. GOOD. \n", "\u001b[31m- Coincidence detected. GOOD. \n", "\u001b[31m- Stop Simulation\n", "\u001b[31m- \n", "\n", "\u001b[0m\u001b[34m\u001b[1m## deleted /cells/19/outputs/5-6:\u001b[0m\n", "\n", "\u001b[0m\n", "\u001b[36m\u001b[1m=========================== short test summary info ============================\u001b[0m\n", "\u001b[31mFAILED\u001b[0m test_ipycell.py::\u001b[1mtest_howto[library.ipynb]\u001b[0m - pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-forc...\n", "\u001b[31mFAILED\u001b[0m test_ipycell.py::\u001b[1mtest_howto[methods.ipynb]\u001b[0m - pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-forc...\n", "\u001b[31mFAILED\u001b[0m test_ipycell.py::\u001b[1mtest_howto[simulation.ipynb]\u001b[0m - pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-forc...\n", "\u001b[31mFAILED\u001b[0m test_ipycell.py::\u001b[1mtest_examples[soc_auxiliaries.ipynb]\u001b[0m - pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-forc...\n", "\u001b[31mFAILED\u001b[0m test_ipycell.py::\u001b[1mtest_examples[tdpram.ipynb]\u001b[0m - pytest_notebook.nb_regression.NBRegressionError: Files differ and --nb-forc...\n", "\u001b[31m============ \u001b[31m\u001b[1m5 failed\u001b[0m, \u001b[32m26 passed\u001b[0m, \u001b[33m31 warnings\u001b[0m\u001b[31m in 220.67s (0:03:40)\u001b[0m\u001b[31m =============\u001b[0m\n" ] } ], "source": [ "%%pytest -v --color=yes --disable-warnings --nb-exec-timeout 50\n", "\n", "---\n", "[pytest]\n", "nb_test_files = True\n", "nb_diff_ignore = \n", " /cells/*/outputs/*/data/image/svg+xml\n", "nb_diff_replace =\n", " /cells/*/outputs/*/data/text .*graphviz\\.files\\.Source.* \"GRAPH-FILE\"\n", " /cells/*/outputs/*/data/text .*graphviz\\.dot\\..* \"DOTGRAPH\"\n", " /cells/*/outputs/*/data/text .*myhdl._block.* \"BLOCK\"\n", " /cells/*/outputs/*/data/text \\-\\-.Date:.* \"DATE\"\n", " /cells/*/outputs/*/text \\-\\-.Date:.* \"DATE\"\n", " /cells/*/outputs/*/data/text .*/tmp/myirl.* \"TMPFILE\" \n", " /cells/*/outputs/*/data/text/html .*svg_container.* \"SVG\" \n", " /cells/*/outputs/*/text .*-rw\\-r\\-\\-r\\-\\-.* \"FILE\"\n", " /cells/*/outputs/*/text .*Finished.(.*).in.*secs \"ELAB_TIME\"\n", " /cells/*/outputs/*/text .*.at.0x.* \"PYOBJ\"\n", " /cells/*/outputs/*/data/text .*.at.0x.* \"PYOBJ\"\n", " /cells/*/outputs/*/text .*.* \"IPYTHON\" \n", " /cells/*/outputs/*/text .*ipykernel_.*\\.py \"IPYKERNEL\"\n", " /cells/*/outputs/*/text .*/tmp/myirl.* \"TMPDIR\"\n", " /cells/*/outputs/*/data/text .*/home/.*/ \"HOMEDIR\" \n", " /cells/*/outputs/*/text .*/home/.*/ \"HOMEDIR\" \n", "\n", "---\n", "\n", "import sys\n", "import importlib_resources\n", "\n", "USERNAME = \"jovyan\"\n", "\n", "sys.path.insert(0, \"/home/%s\" % USERNAME)\n", "sys.path.insert(0, \"/home/pyosys/src/myhdl2/myhdl.v2we\")\n", "\n", "\n", "import pytest\n", "import examples\n", "import howto\n", "\n", "HOWTO = [\"arrays.ipynb\",\n", " \"basics.ipynb\",\n", " \"blinky.ipynb\",\n", " \"co-verification.ipynb\",\n", " \"cyrite_memories.ipynb\",\n", " \"extensions.ipynb\",\n", " \"fsm_counter.ipynb\",\n", " \"generators.ipynb\",\n", " \"library.ipynb\",\n", " \"methods.ipynb\",\n", " \"operations.ipynb\",\n", " \"ports.ipynb\",\n", " \"rtlil.ipynb\",\n", " \"sim_intro.ipynb\",\n", " \"signals_interfaces.ipynb\",\n", " \"simulation.ipynb\",\n", " \"stdlogic.ipynb\",\n", " \"xclkdomain.ipynb\"\n", "]\n", "\n", "EXAMPLES = [\n", " \"example_fsm_hysteresis.ipynb\",\n", " \"fun_stuff.ipynb\",\n", " \"generator_functions.ipynb\",\n", " \"gray_counter.ipynb\",\n", " \"advanced_generators.ipynb\",\n", " \"conditional_pitfalls.ipynb\",\n", " \"pipeline_generators.ipynb\",\n", " # REMOVED: \"class_factories.ipynb\",\n", " \"codec10b8b.ipynb\", \"soc_auxiliaries.ipynb\",\n", " \"crc.ipynb\", \"tdpram.ipynb\",\n", " \"example_barrelshifter.ipynb\", \n", " \"composite_classes.ipynb\",\n", " #\"target_rtlil.ipynb\",\n", " # \"test_pipe.ipynb\",\n", " # \"wavelet.ipynb\"\n", "\n", "]\n", "\n", "# No longer tested. Requires myhdl installation.\n", "MYHDL_LEGACY_UNTESTED = [\n", " \"arith_pitfalls.ipynb\", \"myhdl_concat.ipynb\",\n", " \"bool_pitfalls.ipynb\", \n", "]\n", "\n", "@pytest.mark.parametrize(\"uut\", HOWTO)\n", "def test_howto(nb_regression, uut):\n", " nb_regression.force_regen = True\n", "\n", " with importlib_resources.path(howto, uut) as path:\n", " nb_regression.check(str(path))\n", "\n", "@pytest.mark.parametrize(\"uut\", EXAMPLES)\n", "def test_examples(nb_regression, uut):\n", " nb_regression.force_regen = True\n", "\n", " with importlib_resources.path(examples, uut) as path:\n", " nb_regression.check(str(path))" ] }, { "cell_type": "code", "execution_count": null, "id": "528085b9-acff-45de-8023-abdf84cbcfca", "metadata": {}, "outputs": [], "source": [] } ], "metadata": { "kernelspec": { "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.10.0" } }, "nbformat": 4, "nbformat_minor": 5 }