{ "cells": [ { "cell_type": "markdown", "metadata": {}, "source": [ "## Barrel shifter (cyhdl library)\n", "\n", "This variant uses mixed myIRL and cythonized myhdl code segments. Note that the procedural generation is quite a bit faster." ] }, { "cell_type": "markdown", "metadata": {}, "source": [ "We import the barrelshifter library:" ] }, { "cell_type": "code", "execution_count": 2, "metadata": {}, "outputs": [], "source": [ "from library.barrelshifter import *" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ "[Edit barrelshifter.py](library/barrelshifter.py)" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ "Then we create a barrel shifter generator with data width 32 (power 5):" ] }, { "cell_type": "code", "execution_count": 3, "metadata": {}, "outputs": [], "source": [ "W_POWER = 5\n", "\n", "TEST_VALUES = [\n", " (0xdead, 8, 0xdead << 8),\n", " (0x8f01, 15, 0x8f01 << 15),\n", "]\n", "\n", "b = BarrelShifterGenerator(W_POWER)" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ "Then we instance it first time in the test bench below. Note the instancing time on this first run." ] }, { "cell_type": "code", "execution_count": 4, "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "DEBUG UNHANDLED CLASS \n", "\u001b[7;35m Declare obj 'barrel_shifter' in context '(LIB: BarrelShifterGenerator 'bs')' \u001b[0m\n", "\u001b[7;35m Declare obj 'shifter_stage' in context '(LIB: BarrelShifterGenerator 'bs')' \u001b[0m\n", "\u001b[7;35m Declare obj 'cshift' in context '(LIB: BarrelShifterGenerator 'bs')' \u001b[0m\n", "\u001b[32m Module bs: Existing instance cshift, rename to cshift_1 \u001b[0m\n", "\u001b[32m Module bs: Existing instance shifter_stage, rename to shifter_stage_1 \u001b[0m\n", "\u001b[32m Module bs: Existing instance shifter_stage, rename to shifter_stage_2 \u001b[0m\n", "\u001b[32m Module bs: Existing instance shifter_stage, rename to shifter_stage_3 \u001b[0m\n", "\u001b[32m Module bs: Existing instance shifter_stage, rename to shifter_stage_4 \u001b[0m\n", "Finished test in 0.2787 secs\n" ] } ], "source": [ "from myirl.test.common_test import gen_osc\n", "from myirl.emulation.myhdl import *\n", "\n", "@block\n", "def top_bs(b):\n", " clk = ClkSignal()\n", " ce = Signal(bool())\n", " val, result = [ Signal(intbv(0xaa00)[2 ** W_POWER:]) for i in range(2) ]\n", " s = Signal(intbv()[W_POWER:])\n", " \n", " inst = [\n", " b.barrel_shifter(clk, ce, val, s, result, False),\n", " gen_osc(clk, 2)\n", " ]\n", "\n", "\n", " @instance\n", " def stim():\n", " for item in TEST_VALUES:\n", " ce.next = False\n", " s.next = item[1]\n", " val.next = item[0]\n", " yield(clk.posedge)\n", " ce.next = True\n", " yield(clk.posedge)\n", " yield(clk.posedge)\n", "\n", " print(result)\n", " assert result == item[2]\n", " \n", " raise StopSimulation\n", "\n", " \n", " inst += [ stim ]\n", " return inst\n", " \n", "@utils.timer\n", "def test(b): \n", " return top_bs(b)\n", "\n", "design = test(b)" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ "Running the test bench again, the duration is a little less than on the first run, because this module was already compiled." ] }, { "cell_type": "code", "execution_count": 5, "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "DEBUG UNHANDLED CLASS \n", "\u001b[32m Module top_bs: Existing instance top_bs, rename to top_bs_1 \u001b[0m\n", "Finished test in 0.0844 secs\n" ] } ], "source": [ "design = test(b)" ] }, { "cell_type": "markdown", "metadata": {}, "source": [ "Finally, the quick & dirty verification:" ] }, { "cell_type": "code", "execution_count": 6, "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ " Writing 'top_bs_1' to file /tmp/myirl_top_bs_hkuke_t6/top_bs_1.vhdl \n", " Creating library file /tmp/myirl_module_defs_8zz0e64r/module_defs.vhdl \n", " Writing 'shifter_stage_4' to file /tmp/myirl_bs_se_ljmom/shifter_stage_4.vhdl \n", " Writing 'shifter_stage_3' to file /tmp/myirl_bs_se_ljmom/shifter_stage_3.vhdl \n", " Writing 'shifter_stage_2' to file /tmp/myirl_bs_se_ljmom/shifter_stage_2.vhdl \n", " Writing 'shifter_stage_1' to file /tmp/myirl_bs_se_ljmom/shifter_stage_1.vhdl \n", " Writing 'cshift_1' to file /tmp/myirl_bs_se_ljmom/cshift_1.vhdl \n" ] }, { "name": "stderr", "output_type": "stream", "text": [ "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_4`: Unspecified port I/O 'msb' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_4`: Unspecified port I/O 'sbit' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_3`: Unspecified port I/O 'msb' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_3`: Unspecified port I/O 'sbit' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_2`: Unspecified port I/O 'msb' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_2`: Unspecified port I/O 'sbit' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_1`: Unspecified port I/O 'msb' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage_1`: Unspecified port I/O 'sbit' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage`: Unspecified port I/O 'msb' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n", "../../myirl/kernel/components.py:183: UserWarning: @interface `shifter_stage`: Unspecified port I/O 'sbit' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n" ] }, { "name": "stdout", "output_type": "stream", "text": [ " Writing 'cshift' to file /tmp/myirl_bs_se_ljmom/cshift.vhdl \n", " Writing 'shifter_stage' to file /tmp/myirl_bs_se_ljmom/shifter_stage.vhdl \n", " Writing 'barrel_shifter' to file /tmp/myirl_bs_se_ljmom/barrel_shifter.vhdl \n", " Creating library file /tmp/myirl_module_defs_xpdyoldv/module_defs.vhdl \n", "==== COSIM stderr ====\n", "/tmp/myirl_module_defs_xpdyoldv/module_defs.vhdl:6:1:warning: package \"module_defs\" was also defined in file \"/tmp/myirl_module_defs_8zz0e64r/module_defs.vhdl\" [-Wlibrary]\n", "\n", "==== COSIM stdout ====\n", "0x00DEAD00\n", "0x47808000\n", "simulation stopped @22ns\n", "\n" ] }, { "data": { "text/plain": [ "0" ] }, "execution_count": 6, "metadata": {}, "output_type": "execute_result" } ], "source": [ "from myirl import targets\n", "from myirl.test.common_test import run_ghdl\n", "\n", "f = design.elab(targets.VHDL, elab_all = True)\n", "f += b.elab(targets.VHDL)\n", "# print(f)\n", "run_ghdl(f, design, vcdfile = 'bs.vcd', debug = True)" ] }, { "cell_type": "code", "execution_count": 7, "metadata": {}, "outputs": [], "source": [ "# !cat -n /tmp/barrel_shifter.vhdl" ] }, { "cell_type": "code", "execution_count": null, "metadata": {}, "outputs": [], "source": [] } ], "metadata": { "kernelspec": { "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.9.2" } }, "nbformat": 4, "nbformat_minor": 4 }