{
 "cells": [
  {
   "cell_type": "markdown",
   "id": "bb569f12",
   "metadata": {},
   "source": [
    "# Concat issues\n",
    "\n",
    "MyHDL handles booleans as concat arg, but does not warn early nor resolve to valid VHDL."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 1,
   "id": "50150cd1",
   "metadata": {},
   "outputs": [
    {
     "name": "stderr",
     "output_type": "stream",
     "text": [
      "/home/testing/.local/lib/python3.9/site-packages/myhdl/conversion/_toVHDL.py:467: ToVHDLWarning: Signal is driven but not read: b\n",
      "  warnings.warn(\"%s: %s\" % (_error.UnreadSignal, s._name),\n"
     ]
    },
    {
     "data": {
      "text/plain": [
       "<myhdl._block._Block at 0x7fee510283a0>"
      ]
     },
     "execution_count": 1,
     "metadata": {},
     "output_type": "execute_result"
    }
   ],
   "source": [
    "import myhdl\n",
    "\n",
    "Signal = myhdl.Signal\n",
    "modbv = myhdl.modbv\n",
    "\n",
    "@myhdl.block\n",
    "def unit(clk):\n",
    "    a = [ Signal(bool() ) for _ in range(4) ]\n",
    "    b = Signal(modbv()[4:])\n",
    "    \n",
    "    c = Signal(modbv(0)[4:])\n",
    "\n",
    "    @myhdl.always_comb\n",
    "    def worker():\n",
    "        b.next = myhdl.concat(c >= 0x8, c[3:])\n",
    "        \n",
    "    @myhdl.always(clk.posedge)\n",
    "    def counter():\n",
    "        c.next = c + 1\n",
    "        \n",
    "    return worker, counter\n",
    "\n",
    "clk = Signal(bool())\n",
    "inst = unit(clk)\n",
    "inst.convert(\"VHDL\")"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 2,
   "id": "d0b1997f-3e6d-4d2a-827b-e2957c3592ec",
   "metadata": {},
   "outputs": [
    {
     "name": "stderr",
     "output_type": "stream",
     "text": [
      "/home/testing/.local/lib/python3.9/site-packages/myhdl/conversion/_toVHDL.py:467: ToVHDLWarning: Signal is driven but not read: c\n",
      "  warnings.warn(\"%s: %s\" % (_error.UnreadSignal, s._name),\n"
     ]
    },
    {
     "data": {
      "text/plain": [
       "<myhdl._block._Block at 0x7fee50ff6ee0>"
      ]
     },
     "execution_count": 2,
     "metadata": {},
     "output_type": "execute_result"
    }
   ],
   "source": [
    "@myhdl.block\n",
    "def tb():\n",
    "    a, b = [ Signal(bool()) for _ in range(2) ]\n",
    "    c, d = [ Signal(bool(), delay = 4) for _ in range(2) ]\n",
    "    @myhdl.instance\n",
    "    def main():\n",
    "        a.next = False\n",
    "        yield myhdl.delay(2)\n",
    "        a.next = True\n",
    "        \n",
    "    @myhdl.always_comb\n",
    "    def assign():\n",
    "        c.next = a\n",
    "\n",
    "    return myhdl.instances()\n",
    "\n",
    "inst = tb()\n",
    "inst.convert(\"VHDL\")    \n",
    "    "
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 3,
   "id": "7069c9d0",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "     1\t-- File: tb.vhd\r\n",
      "     2\t-- Generated by MyHDL 0.11\r\n",
      "     3\t-- Date: Sun May 15 13:46:28 2022\r\n",
      "     4\t\r\n",
      "     5\t\r\n",
      "     6\tlibrary IEEE;\r\n",
      "     7\tuse IEEE.std_logic_1164.all;\r\n",
      "     8\tuse IEEE.numeric_std.all;\r\n",
      "     9\tuse std.textio.all;\r\n",
      "    10\t\r\n",
      "    11\tuse work.pck_myhdl_011.all;\r\n",
      "    12\t\r\n",
      "    13\tentity tb is\r\n",
      "    14\tend entity tb;\r\n",
      "    15\t\r\n",
      "    16\t\r\n",
      "    17\tarchitecture MyHDL of tb is\r\n",
      "    18\t\r\n",
      "    19\t\r\n",
      "    20\t\r\n",
      "    21\tsignal a: std_logic;\r\n",
      "    22\tsignal c: std_logic;\r\n",
      "    23\t\r\n",
      "    24\tbegin\r\n",
      "    25\t\r\n",
      "    26\t\r\n",
      "    27\t\r\n",
      "    28\t\r\n",
      "    29\tTB_MAIN: process is\r\n",
      "    30\tbegin\r\n",
      "    31\t    a <= '0';\r\n",
      "    32\t    wait for 2 * 1 ns;\r\n",
      "    33\t    a <= '1';\r\n",
      "    34\t    wait;\r\n",
      "    35\tend process TB_MAIN;\r\n",
      "    36\t\r\n",
      "    37\t\r\n",
      "    38\tc <= a;\r\n",
      "    39\t\r\n",
      "    40\tend architecture MyHDL;\r\n"
     ]
    }
   ],
   "source": [
    "!cat -n tb.vhd"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 4,
   "id": "cc935da1",
   "metadata": {},
   "outputs": [],
   "source": [
    "! ghdl -i unit.vhd pck_myhdl_011.vhd"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 5,
   "id": "1d095a4f",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "\u001b[1munit.vhd:33:25:\u001b[1;31merror:\u001b[0;1m no function declarations for operator \"&\"\u001b[0m\r\n"
     ]
    }
   ],
   "source": [
    "! ghdl -m unit"
   ]
  },
  {
   "cell_type": "markdown",
   "id": "6c8e50da",
   "metadata": {},
   "source": [
    "# MyIRL emulation"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 6,
   "id": "4ba4d25c",
   "metadata": {},
   "outputs": [],
   "source": [
    "from myirl.emulation.myhdl import *\n",
    "from myirl.test.common_test import run_ghdl\n",
    "\n",
    "from myirl.wire import SLV\n",
    "\n",
    "@block\n",
    "def unit1(clk):\n",
    "    a = [ Signal(bool() ) for _ in range(4) ]\n",
    "    b = Signal(modbv()[4:])\n",
    "    \n",
    "    c = Signal(modbv(0)[4:])\n",
    "\n",
    "    \n",
    "    @always_comb\n",
    "    def worker():\n",
    "        b.next = concat(c >= 0x8, c == 0, c[2:])\n",
    "        \n",
    "    @always(clk.posedge)\n",
    "    def counter():\n",
    "        c.next = c + 1\n",
    "        \n",
    "    return instances()"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 7,
   "id": "9c0d8c1e",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "FALLBACK: UNHANDLED ROOT CLASS <class 'ipykernel.zmqshell.ZMQInteractiveShell'>, create new context\n",
      " Writing 'unit1' to file /tmp/myirl_unit1_gaohujft/unit1.vhdl \n",
      "Warning: Implicit truncation of ADD(c, C:1) result\n",
      "==== COSIM stdout ====\n",
      "../../src/ieee/v93/numeric_std-body.vhdl:1461:7:@0ms:(assertion warning): NUMERIC_STD.\">=\": metavalue detected, returning FALSE\n",
      "../../src/ieee/v93/numeric_std-body.vhdl:1613:7:@0ms:(assertion warning): NUMERIC_STD.\"=\": metavalue detected, returning FALSE\n",
      "\n"
     ]
    },
    {
     "name": "stderr",
     "output_type": "stream",
     "text": [
      "/home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/kernel/_types.py:451: UserWarning: Non-ClkSignal 'clk' edge event reference.\n",
      "You might want to use ClkSignal instead.\n",
      "  base.warnings.warn(\"Non-ClkSignal '%s'\" % obj.identifier + \\\n",
      "/home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/kernel/components.py:189: UserWarning: @component `unit1` interface :Unspecified port I/O 'clk' => IN\n",
      "  base.warnings.warn((msg + \" => IN\") % n)\n",
      "/home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/kernel/instance.py:424: TranslationWarning: @component `unit1`: DEBUG UNUSED 'a0'\n",
      "  base.warn(\"@component `%s`: DEBUG UNUSED '%s'\" % (self.obj.func.__name__, n), category = base.TranslationWarning)\n",
      "/home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/kernel/instance.py:424: TranslationWarning: @component `unit1`: DEBUG UNUSED 'a1'\n",
      "  base.warn(\"@component `%s`: DEBUG UNUSED '%s'\" % (self.obj.func.__name__, n), category = base.TranslationWarning)\n",
      "/home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/kernel/instance.py:424: TranslationWarning: @component `unit1`: DEBUG UNUSED 'a2'\n",
      "  base.warn(\"@component `%s`: DEBUG UNUSED '%s'\" % (self.obj.func.__name__, n), category = base.TranslationWarning)\n",
      "/home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/kernel/instance.py:424: TranslationWarning: @component `unit1`: DEBUG UNUSED 'a3'\n",
      "  base.warn(\"@component `%s`: DEBUG UNUSED '%s'\" % (self.obj.func.__name__, n), category = base.TranslationWarning)\n"
     ]
    }
   ],
   "source": [
    "def convert():\n",
    "    clk = Signal(bool())\n",
    "    inst = unit1(clk)\n",
    "    files = inst.elab(targets.VHDL)\n",
    "    run_ghdl(files, inst, std=\"93c\", debug = True)\n",
    "    return files\n",
    "f = convert()"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 8,
   "id": "10787273",
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "-- File generated from source:\r\n",
      "--     /tmp/ipykernel_30359/2136329268.py\r\n",
      "-- (c) 2016-2022 section5.ch\r\n",
      "-- Modifications may be lost, edit the source file instead.\r\n",
      "\r\n",
      "library IEEE;\r\n",
      "use IEEE.std_logic_1164.all;\r\n",
      "use IEEE.numeric_std.all;\r\n",
      "\r\n",
      "library work;\r\n",
      "\r\n",
      "use work.txt_util.all;\r\n",
      "use work.myirl_conversion.all;\r\n",
      "\r\n",
      "entity unit1 is\r\n",
      "    port (\r\n",
      "        clk : in std_ulogic\r\n",
      "    );\r\n",
      "end entity unit1;\r\n",
      "\r\n",
      "architecture myhdl_emulation of unit1 is\r\n",
      "    -- Local type declarations\r\n",
      "    -- Signal declarations\r\n",
      "    signal b : unsigned(3 downto 0);\r\n",
      "    signal c : unsigned(3 downto 0);\r\n",
      "begin\r\n",
      "    \r\n",
      "worker:\r\n",
      "    process(c)\r\n",
      "    begin\r\n",
      "        b <= (std_ulogic'(from_bool((c >= x\"8\"))) & std_ulogic'(from_bool((c = x\"0\"))) & c(2-1 downto 0));\r\n",
      "    end process;\r\n",
      "\r\n",
      "    \r\n",
      "counter:\r\n",
      "    process(clk)\r\n",
      "    begin\r\n",
      "        if rising_edge(clk) then\r\n",
      "            c <= resize((resize(c, 5) + \"00001\"), 4);\r\n",
      "        end if;\r\n",
      "    end process;\r\n",
      "end architecture myhdl_emulation;\r\n",
      "\r\n"
     ]
    }
   ],
   "source": [
    "! cat {f[0]}"
   ]
  }
 ],
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