{ "cells": [ { "cell_type": "markdown", "id": "bb569f12", "metadata": {}, "source": [ "# Concat issues\n", "\n", "MyHDL handles booleans as concat arg, but does not resolve to valid VHDL." ] }, { "cell_type": "code", "execution_count": 1, "id": "50150cd1", "metadata": {}, "outputs": [ { "name": "stderr", "output_type": "stream", "text": [ "/home/cyrite/.local/lib/python3.10/site-packages/myhdl/conversion/_toVHDL.py:471: ToVHDLWarning: Signal is driven but not read: b\n", " warnings.warn(\"%s: %s\" % (_error.UnreadSignal, s._name),\n" ] }, { "data": { "text/plain": [ "" ] }, "execution_count": 1, "metadata": {}, "output_type": "execute_result" } ], "source": [ "import myhdl\n", "\n", "Signal = myhdl.Signal\n", "modbv = myhdl.modbv\n", "\n", "@myhdl.block\n", "def unit(clk):\n", " a = [ Signal(bool() ) for _ in range(4) ]\n", " b = Signal(modbv()[4:])\n", " \n", " c = Signal(modbv(0)[4:])\n", "\n", " @myhdl.always_comb\n", " def worker():\n", " b.next = myhdl.concat(c >= 0x8, c[3:])\n", " \n", " @myhdl.always(clk.posedge)\n", " def counter():\n", " c.next = c + 1\n", " \n", " return worker, counter\n", "\n", "clk = Signal(bool())\n", "inst = unit(clk)\n", "inst.convert(\"VHDL\")" ] }, { "cell_type": "code", "execution_count": 2, "id": "d0b1997f-3e6d-4d2a-827b-e2957c3592ec", "metadata": {}, "outputs": [ { "name": "stderr", "output_type": "stream", "text": [ "/home/cyrite/.local/lib/python3.10/site-packages/myhdl/conversion/_toVHDL.py:471: ToVHDLWarning: Signal is driven but not read: c\n", " warnings.warn(\"%s: %s\" % (_error.UnreadSignal, s._name),\n" ] }, { "data": { "text/plain": [ "" ] }, "execution_count": 2, "metadata": {}, "output_type": "execute_result" } ], "source": [ "@myhdl.block\n", "def tb():\n", " a, b = [ Signal(bool()) for _ in range(2) ]\n", " c, d = [ Signal(bool(), delay = 4) for _ in range(2) ]\n", " @myhdl.instance\n", " def main():\n", " a.next = False\n", " yield myhdl.delay(2)\n", " a.next = True\n", " \n", " @myhdl.always_comb\n", " def assign():\n", " c.next = a\n", "\n", " return myhdl.instances()\n", "\n", "inst = tb()\n", "inst.convert(\"VHDL\") \n", " " ] }, { "cell_type": "code", "execution_count": 3, "id": "7069c9d0", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ " 1\t-- File: tb.vhd\n", " 2\t-- Generated by MyHDL 0.11.49\n", " 3\t-- Date: Wed Jul 17 20:08:54 2024\n", " 4\t\n", " 5\t\n", " 6\tlibrary IEEE;\n", " 7\tuse IEEE.std_logic_1164.all;\n", " 8\tuse IEEE.numeric_std.all;\n", " 9\tuse std.textio.all;\n", " 10\t\n", " 11\tuse work.pck_myhdl_011.all;\n", " 12\t\n", " 13\tentity tb is\n", " 14\tend entity tb;\n", " 15\t\n", " 16\t\n", " 17\tarchitecture MyHDL of tb is\n", " 18\t\n", " 19\t\n", " 20\t\n", " 21\tsignal a: std_logic;\n", " 22\tsignal c: std_logic;\n", " 23\t\n", " 24\tbegin\n", " 25\t\n", " 26\t\n", " 27\t\n", " 28\t\n", " 29\tTB_MAIN: process is\n", " 30\tbegin\n", " 31\t a <= '0';\n", " 32\t wait for 2 * 1 ns;\n", " 33\t a <= '1';\n", " 34\t wait;\n", " 35\tend process TB_MAIN;\n", " 36\t\n", " 37\t\n", " 38\tc <= a;\n", " 39\t\n", " 40\tend architecture MyHDL;\n" ] } ], "source": [ "!cat -n tb.vhd" ] }, { "cell_type": "code", "execution_count": 4, "id": "cc935da1", "metadata": {}, "outputs": [], "source": [ "! ghdl -i unit.vhd pck_myhdl_011.vhd" ] }, { "cell_type": "code", "execution_count": 5, "id": "1d095a4f", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "\u001b[1munit.vhd:33:25:\u001b[1;31merror:\u001b[0;1m no function declarations for operator \"&\"\u001b[0m\n" ] } ], "source": [ "! ghdl -m unit" ] }, { "cell_type": "markdown", "id": "6c8e50da", "metadata": {}, "source": [ "# MyIRL emulation" ] }, { "cell_type": "code", "execution_count": 6, "id": "4ba4d25c", "metadata": {}, "outputs": [], "source": [ "from myirl.emulation.myhdl import *\n", "from myirl.test.common_test import run_ghdl\n", "\n", "from myirl.wire import SLV\n", "\n", "@block\n", "def unit1(clk):\n", " a = [ Signal(bool() ) for _ in range(4) ]\n", " b = Signal(modbv()[4:])\n", " \n", " c = Signal(modbv(0)[4:])\n", "\n", " \n", " @always_comb\n", " def worker():\n", " b.next = concat(c >= 0x8, c == 0, c[2:])\n", " \n", " @always(clk.posedge)\n", " def counter():\n", " c.next = c + 1\n", " \n", " return instances()" ] }, { "cell_type": "code", "execution_count": 7, "id": "9c0d8c1e", "metadata": {}, "outputs": [ { "name": "stderr", "output_type": "stream", "text": [ "/home/cyrite/.local/lib/python3.10/site-packages/cyritehdl-0.1b0-py3.10-linux-x86_64.egg/myirl/kernel/components.py:215: UserWarning: @component `unit1` interface :Unspecified port I/O 'clk' => IN\n", " base.warnings.warn((msg + \" => IN\") % n)\n" ] }, { "name": "stdout", "output_type": "stream", "text": [ " Writing 'unit1' to file /tmp/myirl_unit1_rznah5c6/unit1.vhdl \n", "Warning: Implicit truncation of ADD(c, C:1) result\n", "WORK DIR of instance [Instance unit1 I/F: [// ID: unit1_0 ]] /tmp/myirl_unit1_rznah5c6/\n", "==== COSIM stdout ====\n", "../../src/ieee/v93/numeric_std-body.vhdl:1461:7:@0ms:(assertion warning): NUMERIC_STD.\">=\": metavalue detected, returning FALSE\n", "../../src/ieee/v93/numeric_std-body.vhdl:1613:7:@0ms:(assertion warning): NUMERIC_STD.\"=\": metavalue detected, returning FALSE\n", "\n" ] } ], "source": [ "def convert():\n", " clk = Signal(bool())\n", " inst = unit1(clk)\n", " files = inst.elab(targets.VHDL)\n", " run_ghdl(files, inst, std=\"93c\", debug = True)\n", " return files\n", "f = convert()" ] }, { "cell_type": "code", "execution_count": 8, "id": "10787273", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "-- File generated from source:\n", "-- /tmp/ipykernel_96221/2136329268.py\n", "-- (c) 2016-2022 section5.ch\n", "-- Modifications may be lost, edit the source file instead.\n", "\n", "library IEEE;\n", "use IEEE.std_logic_1164.all;\n", "use IEEE.numeric_std.all;\n", "\n", "library work;\n", "\n", "use work.txt_util.all;\n", "use work.myirl_conversion.all;\n", "\n", "entity unit1 is\n", " port (\n", " clk : in std_ulogic\n", " );\n", "end entity unit1;\n", "\n", "architecture cyriteHDL of unit1 is\n", " -- Local type declarations\n", " -- Signal declarations\n", " signal b : unsigned(3 downto 0);\n", " signal c : unsigned(3 downto 0);\n", "begin\n", " \n", "worker:\n", " process(c)\n", " begin\n", " b <= (std_ulogic'(from_bool((c >= x\"8\"))) & std_ulogic'(from_bool((c = x\"0\"))) & c(2-1 downto 0));\n", " end process;\n", "\n", " \n", "counter:\n", " process(clk)\n", " begin\n", " if rising_edge(clk) then\n", " c <= resize((resize(c, 5) + 1), 4);\n", " end if;\n", " end process;\n", "end architecture cyriteHDL;\n", "\n" ] } ], "source": [ "! cat {f[0]}" ] }, { "cell_type": "code", "execution_count": null, "id": "fedaa7b5-fe53-4977-9164-a5bc48fa41da", "metadata": {}, "outputs": [], "source": [] } ], "metadata": { "kernelspec": { "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.10.0" } }, "nbformat": 4, "nbformat_minor": 5 }