{ "cells": [ { "cell_type": "markdown", "id": "19c772f9-beba-4d58-99da-43e2abef2096", "metadata": {}, "source": [ "# Direct translation to RTL\n", "\n", "The primitive example below demonstrates how to directly synthesize from a cyHDL notation to yosys RTL and display using the .dot backend." ] }, { "cell_type": "code", "execution_count": 1, "id": "594bb478-6c09-41cb-a6aa-ecaf997aa277", "metadata": {}, "outputs": [], "source": [ "from cyhdl import *" ] }, { "cell_type": "code", "execution_count": 2, "id": "701a8949-98b8-49ae-bae2-7b651da76ff7", "metadata": {}, "outputs": [], "source": [ "@block\n", "def unitx(clk : ClkSignal, a : Signal, b : Signal.Output):\n", " @always(clk.posedge)\n", " def worker():\n", " if a < 20:\n", " b.next = concat(a[3:], a[4:])\n", " if a > 6:\n", " b.next = 0\n", " elif a < 4:\n", " b.next = 44\n", " \n", " return instances()" ] }, { "cell_type": "code", "execution_count": 3, "id": "4ebe268a-a029-4741-88b7-1438df761f70", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "\u001b[32m Adding module with name `unitx` \u001b[0m\n", "\u001b[7;34m FINALIZE implementation `unitx` of `unitx` \u001b[0m\n" ] } ], "source": [ "from myirl.targets import pyosys\n", "\n", "def test():\n", " \n", " clk = ClkSignal()\n", " a, b = [ Signal(intbv()[7:]) for _ in range(2) ]\n", " u = unitx(clk, a, b)\n", "\n", " r = pyosys.RTLIL(\"top1\")\n", " d = u.elab(r)\n", " d[0].run(\"opt\")\n", " d[0].display_rtl(fmt=\"dot\")\n", " return d[0]\n", "design = test()" ] }, { "cell_type": "code", "execution_count": 4, "id": "541a925e-6831-4332-8035-6ba424764195", "metadata": {}, "outputs": [ { "data": { "text/html": [ "\n", "