{ "cells": [ { "cell_type": "markdown", "id": "19c772f9-beba-4d58-99da-43e2abef2096", "metadata": {}, "source": [ "# Direct translation to RTL" ] }, { "cell_type": "code", "execution_count": 1, "id": "594bb478-6c09-41cb-a6aa-ecaf997aa277", "metadata": {}, "outputs": [], "source": [ "from myirl.emulation.myhdl import *" ] }, { "cell_type": "code", "execution_count": 2, "id": "701a8949-98b8-49ae-bae2-7b651da76ff7", "metadata": {}, "outputs": [], "source": [ "@block\n", "def unitx(clk, a, b):\n", " @always(clk.posedge)\n", " def worker():\n", " if a < 20:\n", " b.next = concat(a[3:], a[4:])\n", " if a > 6:\n", " b.next = 0\n", " elif a < 4:\n", " b.next = 44\n", " \n", " return instances()" ] }, { "cell_type": "code", "execution_count": 3, "id": "4ebe268a-a029-4741-88b7-1438df761f70", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ " DEBUG CREATE wrapper module for unitx (EmulationModule 'top_unitx') \n", "Creating process 'unitx/worker' with sensitivity (clk'rising,)\n", "\u001b[32m Adding module with name `unitx` \u001b[0m\n", "\n", "-- Running command `opt' --\n", "\n", "1. Executing OPT pass (performing simple optimizations).\n", "\n", "1.1. Executing OPT_EXPR pass (perform const folding).\n", "Optimizing module unitx.\n", "\n", "1.2. Executing OPT_MERGE pass (detect identical cells).\n", "Finding identical cells in module `\\unitx'.\n", "Removed a total of 0 cells.\n", "\n", "1.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n", "Running muxtree optimizer on module \\unitx..\n", " Creating internal representation of mux trees.\n", " Evaluating internal representation of mux trees.\n", " Analyzing evaluation results.\n", "Removed 0 multiplexer ports.\n", "\n", "\n", "1.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n", " Optimizing cells in module \\unitx.\n", "Performed a total of 0 changes.\n", "\n", "1.5. Executing OPT_MERGE pass (detect identical cells).\n", "Finding identical cells in module `\\unitx'.\n", "Removed a total of 0 cells.\n", "\n", "1.6. Executing OPT_DFF pass (perform DFF optimizations).\n", "Adding EN signal on $worker::b_af19 ($dff) from module unitx (D = $auto$yosys.pyosys_wrappers:0:$10, Q = $b_ff).\n", "\n", "1.7. Executing OPT_CLEAN pass (remove unused cells and wires).\n", "Finding unused cells or wires in module \\unitx..\n", "Removed 0 unused cells and 7 unused wires.\n", "\n", "\n", "1.8. Executing OPT_EXPR pass (perform const folding).\n", "Optimizing module unitx.\n", "\n", "\n", "1.9. Rerunning OPT passes. (Maybe there is more to do..)\n", "\n", "1.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n", "Running muxtree optimizer on module \\unitx..\n", " Creating internal representation of mux trees.\n", " Evaluating internal representation of mux trees.\n", " Analyzing evaluation results.\n", "Removed 0 multiplexer ports.\n", "\n", "\n", "1.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n", " Optimizing cells in module \\unitx.\n", "Performed a total of 0 changes.\n", "\n", "1.12. Executing OPT_MERGE pass (detect identical cells).\n", "Finding identical cells in module `\\unitx'.\n", "Removed a total of 0 cells.\n", "\n", "1.13. Executing OPT_DFF pass (perform DFF optimizations).\n", "\n", "1.14. Executing OPT_CLEAN pass (remove unused cells and wires).\n", "Finding unused cells or wires in module \\unitx..\n", "\n", "1.15. Executing OPT_EXPR pass (perform const folding).\n", "Optimizing module unitx.\n", "\n", "1.16. Finished OPT passes. (There is nothing left to do.)\n", "\n", "-- Running command `show -format dot -prefix top1 ' --\n", "\n", "2. Generating Graphviz representation of design.\n", "Writing dot description to `top1.dot'.\n", "Dumping module unitx to page 1.\n" ] } ], "source": [ "from myirl.targets import pyosys\n", "\n", "def test():\n", " \n", " clk = ClkSignal()\n", " a, b = [ Signal(intbv()[7:]) for _ in range(2) ]\n", " u = unitx(clk, a, b)\n", "\n", " r = pyosys.RTLIL(\"top1\")\n", " d = u.elab(r)\n", " d[0].run(\"opt\")\n", " d[0].display_rtl(fmt=\"dot\")\n", " return d[0]\n", "design = test()" ] }, { "cell_type": "code", "execution_count": 4, "id": "541a925e-6831-4332-8035-6ba424764195", "metadata": {}, "outputs": [ { "data": { "text/html": [ "\n", "
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\n", " " ], "text/plain": [ "" ] }, "execution_count": 4, "metadata": {}, "output_type": "execute_result" } ], "source": [ "from yosys import display\n", "display.display_dot(design.name)" ] } ], "metadata": { "kernelspec": { "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.9.2" } }, "nbformat": 4, "nbformat_minor": 5 }