{ "cells": [ { "cell_type": "markdown", "id": "dfd7651d-06e5-482e-9a54-e086f7094cea", "metadata": {}, "source": [ "# Direct RTL via yosys\n", "\n", "**Obsolete, scheduled for removal**\n", "\n", "Status notes:\n", " * Do not rely on pyosys API\n", " * Crashes and irregularities may occur\n" ] }, { "cell_type": "code", "execution_count": 1, "id": "f3a927f3-aba0-4662-a83b-3077b8c78c82", "metadata": {}, "outputs": [], "source": [ "from cyhdl import *\n", "\n", "Byte = Signal.Type(intbv, 8)\n", "Bool = Signal.Type(bool)\n", "\n", "@block\n", "def lfsr8(clk : ClkSignal, ce : Bool, reset : ResetSignal, dout : Byte.Output,\n", " RVAL : int = 1):\n", " \"\"\"LFSR with all states\"\"\"\n", " \n", " v = Signal(intbv(RVAL)[8:])\n", " \n", " fb = Signal(bool())\n", " \n", " e = v[7:0] == 0\n", "\n", " @always_seq(clk.posedge, reset)\n", " def worker():\n", " if ce == 1:\n", " v.next = concat(v[6], v[5], v[4], v[3] ^ fb, v[2] ^ fb, v[1] ^ fb, v[0], fb)\n", "\n", " @always_comb\n", " def assign():\n", " fb.next = v[7] ^ e\n", " dout.next = v\n", "\n", " return instances()\n", "\n", "# Wrapper hack to use local dictionary for instance naming\n", "def use_local_names(arg):\n", " arg.use_local_names = True\n", " return arg\n", "\n", "@use_local_names\n", "@block\n", "def unit_count(clk : ClkSignal, ce: Signal, reset : ResetSignal, q : Signal.Output):\n", " \n", " c, d = [ Signal(intbv(0)[8:]) for _ in range(2) ]\n", " \n", " inst_lfsr = lfsr8(clk, ce, reset, d, RVAL = 0xfa)\n", "\n", " @always_seq(clk.posedge, reset)\n", " def counter():\n", " c.next = c + 1\n", "# q.next = d ^ c\n", "\n", " wires = [ q.wireup(d ^ c) ]\n", " \n", " return instances()" ] }, { "cell_type": "code", "execution_count": 2, "id": "c476cce3-5621-4f1d-86ed-50545e94cff7", "metadata": {}, "outputs": [], "source": [ "from myirl.targets import pyosys\n", "\n", "def test_expr(tgt):\n", " ce = Signal(bool())\n", " clk = ClkSignal()\n", " reset = ResetSignal(0, 1, isasync = True)\n", " q = Signal(intbv()[8:])\n", "\n", " t = unit_count(clk, ce, reset, q)\n", " designs = t.elab(tgt, elab_all = True)\n", "\n", " return designs[0]" ] }, { "cell_type": "code", "execution_count": 3, "id": "17f66eb8-0222-4083-aff3-1577e6ba05a7", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "\u001b[32m Adding module with name `lfsr8` \u001b[0m\n", "\u001b[32m Adding module with name `unit_count` \u001b[0m\n", "\u001b[7;34m FINALIZE implementation `unit_count` of `unit_count` \u001b[0m\n", "\n", "-- Running command `hierarchy -top \\unit_count' --\n", "\n", "1. Executing HIERARCHY pass (managing design hierarchy).\n", "\n", "1.1. Analyzing design hierarchy..\n", "Top module: \\unit_count\n", "Used module: \\lfsr8\n", "\n", "1.2. Analyzing design hierarchy..\n", "Top module: \\unit_count\n", "Used module: \\lfsr8\n", "Removed 0 unused modules.\n" ] } ], "source": [ "tgt = pyosys.RTLIL(\"top\")\n", "\n", "design = test_expr(tgt)\n", "design.display_rtl(selection = \"unit_count\", fmt='dot')\n", "# design.display_rtl(selection = \"lfsr8\", fmt='dot')" ] }, { "cell_type": "markdown", "id": "f66bb0eb-feca-4b75-8050-02cc7d15dc16", "metadata": {}, "source": [ "### RTL Display\n", "\n", "The `@use_local_names` construct sets the myHDL instance variable names for the identifier.\n", "\n", "Note: Pan and zoom may not work on some browsers." ] }, { "cell_type": "code", "execution_count": 4, "id": "fc8b26c2-c4d0-4874-b9df-cb05bc5bcff2", "metadata": {}, "outputs": [ { "data": { "text/html": [ "\n", "