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    "# Cyrite / myhdl.v2we\n",
    "\n",
    "A 'next generation' concept study for myHDL syntax emulation based on a different hardware generator kernel. The *v2we* acronym (working title pun) stands for 'van twee walletjes eten' (dutch meaning to 'take advantage from both sides') or 'version two working environment'.\n",
    "\n",
    "This is the **Cyrite** and `intbv` compatible branch. This is likely going to be the main development path for the future.\n",
    "\n",
    "* [myHDL emulation and library examples](examples/index.ipynb)\n",
    "* [myHDL legacy migration notes](myhdl_migration.ipynb)\n",
    "* [myIRL kernel overview](notebooks/index.ipynb) : The 'kernel reference' and intermediate representation\n",
    "* [Auto-Testing the notebooks](autotesting.ipynb)"
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    "What it is based on:\n",
    "\n",
    "* A Jupyter Lab based IDE setup to develop hardware logic\n",
    "* A toolbox to generate HDL or RTL\n",
    "  * [VHDL](targets.ipynb#VHDL) and [Verilog](targets.ipynb#Verilog) hierarchical output for synthesis and simulation\n",
    "  * Performance-minded mass instancing of logic elements via yosys\n",
    "* A lean and mean kernel optimized for (cython-compiled) Python3 and code reusability (class derivation)\n",
    "  * Ready for System on Chip designs and complex data pipelines\n",
    "  * High level synthesis style digital signal processing capable\n",
    "  * 'CyriteHDL': Cython-Support for closed source code generators\n",
    "* An experimentation ground for academic/learning purposes\n",
    "  * Inline-evaluation/verification of Python code versus generated HDL ('automated testbenches')\n",
    "* Taking advantages of both sides:\n",
    "  * Executable/compiled intermediate language instead of AST-Translation\n",
    "  * Still keeping the well readable myHDL code style and `intbv` benefits\n",
    "\n",
    "What it is not:\n",
    "* Python2 compatible (never)\n",
    "* A native Python simulator (yet)\n",
    "* A ready-made HLS tool (you need to define your own generator framework)\n",
    "* A drop-in replacement for myHDL (not yet intended)"
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    "## FAQs\n",
    "\n",
    "* Why VHDL, despite fading out support for vendor toolchains?\n",
    "\n",
    "  VHDL, due to its strict typing, is still the best golden reference to check against and make sure no implicit magic\n",
    "  slips through. Once the VHDL tool flow is proven to be robust, other targets can be tackled.\n",
    "  \n",
    "* Is VHDL-2019 support planned?\n",
    "\n",
    "  Not for the time being. It is unlikely that any FPGA toolchain on the market will implement the full VHDL-2019 support.\n",
    "  \n",
    "* Is this a myHDL fork?\n",
    "\n",
    "  No. It is a different kernel, originally designed to *procedurally generate* HDL/RTL pipelines.\n",
    "  It was partially rewritten to be compatible with other data types, such as myHDL's `intbv` which may still serve as 'state of the art' reference implementation for bit vectors. MyHDL emulation is implemented using AST-Translation.\n",
    "  \n",
    "* Is functionality being back-ported into MyHDL/a fork?\n",
    "\n",
    "  No, see above. The different kernel architecture doesn't allow that.\n",
    "  \n",
    "* Where is the github repository for the kernel?\n",
    "\n",
    "  There is none. The myIRL binary part of the kernel still contains proprietary code which is hosted in a private repository.\n",
    "  The cleanups for full opensource compatibility will come last.\n",
    "  \n",
    "* What is going to happen to myHDL synthesis via yosys ('jupyosys')?\n",
    "\n",
    "  See above WRT RTLIL. The myHDL support will no longer be maintained for jupyosys and remains as 'experiment only'."
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