{
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  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "## Barrel shifter (cyhdl library)\n",
    "\n",
    "This variant uses mixed myIRL and cythonized myhdl code segments. Note that the procedural generation is quite a bit faster."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 1,
   "metadata": {},
   "outputs": [],
   "source": [
    "import sys\n",
    "sys.path.insert(0, \"../..\")"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "We import the barrelshifter library:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 2,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "Compiling /tmp/_cython_inline_08cfa26591b7492f5757aa87dc70c928c0d51984.pyx because it changed.\n",
      "[1/1] Cythonizing /tmp/_cython_inline_08cfa26591b7492f5757aa87dc70c928c0d51984.pyx\n"
     ]
    }
   ],
   "source": [
    "from library.barrelshifter import *"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "[Edit barrelshifter.py](library/barrelshifter.py)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Then we create a barrel shifter generator with data width 32 (power 5):"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 3,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "DEBUG CALLING CYTHONIZED CODE\n"
     ]
    }
   ],
   "source": [
    "W_POWER = 5\n",
    "\n",
    "TEST_VALUES = [\n",
    "    (0xdead, 8, 0xdead << 8),\n",
    "    (0x8f01, 15, 0x8f01 << 15),\n",
    "]\n",
    "\n",
    "b = BarrelShifterGenerator(W_POWER)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Then we instance it first time in the test bench below. Note the instancing time on this first run."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 4,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      " DEBUG CREATE wrapper module for top_bs (EmulationModule 'top_top_bs') \n",
      "\u001b[7;35m Declare obj 'barrel_shifter' in context '(LIB: BarrelShifterGenerator 'bs')' \u001b[0m\n",
      "\u001b[7;35m Declare obj 'shifter_stage' in context '(LIB: BarrelShifterGenerator 'bs')' \u001b[0m\n",
      "\u001b[7;35m Declare obj 'cshift' in context '(LIB: BarrelShifterGenerator 'bs')' \u001b[0m\n",
      "\u001b[32m Module bs: Existing implementation cshift, rename to cshift_1 \u001b[0m\n",
      "\u001b[32m Module bs: Existing implementation shifter_stage, rename to shifter_stage_1 \u001b[0m\n",
      "\u001b[32m Module bs: Existing implementation shifter_stage, rename to shifter_stage_2 \u001b[0m\n",
      "\u001b[32m Module bs: Existing implementation shifter_stage, rename to shifter_stage_3 \u001b[0m\n",
      "\u001b[32m Module bs: Existing implementation shifter_stage, rename to shifter_stage_4 \u001b[0m\n",
      "Creating process '_run/assign' with sensitivity (clk'rising,)\n",
      "Creating sequential 'top_bs/stim' \n",
      "Finished test in 0.2160 secs\n"
     ]
    }
   ],
   "source": [
    "from myirl.test.common_test import gen_osc\n",
    "from myirl.emulation.myhdl import *\n",
    "\n",
    "@block\n",
    "def top_bs(b):\n",
    "    clk = myirl.ClkSignal()\n",
    "    ce = Signal(bool())\n",
    "    val, result = [ Signal(intbv(0xaa00)[2 ** W_POWER:]) for i in range(2) ]\n",
    "    s = Signal(intbv()[W_POWER:])\n",
    "    \n",
    "    inst = [\n",
    "        b.barrel_shifter(clk, ce, val, s, result, False),\n",
    "        gen_osc(clk, 2)\n",
    "    ]\n",
    "\n",
    "\n",
    "    @instance\n",
    "    def stim():\n",
    "        for item in TEST_VALUES:\n",
    "            ce.next = False\n",
    "            s.next = item[1]\n",
    "            val.next = item[0]\n",
    "            yield(clk.posedge)\n",
    "            ce.next = True\n",
    "            yield(clk.posedge)\n",
    "            yield(clk.posedge)\n",
    "\n",
    "            print(result)\n",
    "            assert result == item[2]\n",
    "            \n",
    "        raise StopSimulation\n",
    "\n",
    "    \n",
    "    inst += [ stim ]\n",
    "    return inst\n",
    " \n",
    "@utils.timer\n",
    "def test(b):    \n",
    "    return top_bs(b)\n",
    "\n",
    "design = test(b)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Running the test bench again, the duration is a little less than on the first run, because this module was already compiled."
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 5,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "Finished test in 0.0139 secs\n"
     ]
    }
   ],
   "source": [
    "design = test(b)"
   ]
  },
  {
   "cell_type": "markdown",
   "metadata": {},
   "source": [
    "Finally, the quick & dirty verification:"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 6,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      " Elaborating component top_bs__BarrelShifterGenerator \n",
      " Writing 'top_bs' to file /tmp/myirl_top_top_bs_dzf9st8l/top_bs.vhdl \n",
      " Creating library file /tmp/myirl_module_defs_kmyuipw3/module_defs.vhdl \n",
      " Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_16_s1_0_0 \n",
      " Writing 'shifter_stage_4' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage_4.vhdl \n",
      " Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_8_s1_0_0 \n",
      " Writing 'shifter_stage_3' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage_3.vhdl \n",
      " Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_4_s1_0_0 \n",
      " Writing 'shifter_stage_2' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage_2.vhdl \n",
      " Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_2_s1_0_0 \n",
      " Writing 'shifter_stage_1' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage_1.vhdl \n",
      " Elaborating component cshift__BarrelShifterGenerator_s1_s1_s1_s1_s1_0_0_1 \n",
      " Writing 'cshift_1' to file /tmp/myirl_bs_gv9ug3vk/cshift_1.vhdl \n",
      " Elaborating component cshift__BarrelShifterGenerator_s1_s1_s1_s1_s1_0_0_0 \n",
      " Writing 'cshift' to file /tmp/myirl_bs_gv9ug3vk/cshift.vhdl \n",
      " Elaborating component shifter_stage__BarrelShifterGenerator_s32_s32_s1_1_s1_0_0 \n",
      " Writing 'shifter_stage' to file /tmp/myirl_bs_gv9ug3vk/shifter_stage.vhdl \n",
      " Elaborating component barrel_shifter__BarrelShifterGenerator_s1_s1_s32_s5_s32_0 \n",
      " Writing 'barrel_shifter' to file /tmp/myirl_bs_gv9ug3vk/barrel_shifter.vhdl \n",
      " Creating library file /tmp/myirl_module_defs_ou6htrhd/module_defs.vhdl \n",
      "==== COSIM stdout ====\n",
      "\n",
      "==== COSIM stderr ====\n",
      "/tmp/myirl_module_defs_ou6htrhd/module_defs.vhdl:6:1:warning: package \"module_defs\" was also defined in file \"/tmp/myirl_module_defs_kmyuipw3/module_defs.vhdl\" [-Wlibrary]\n",
      "\n",
      "==== COSIM stdout ====\n",
      "analyze /home/testing/src/myhdl2/myirl/targets/../test/vhdl/txt_util.vhdl\n",
      "analyze /home/testing/src/myhdl2/myirl/targets/libmyirl.vhdl\n",
      "analyze /tmp/myirl_bs_gv9ug3vk/cshift.vhdl\n",
      "analyze /tmp/myirl_bs_gv9ug3vk/cshift_1.vhdl\n",
      "analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage.vhdl\n",
      "analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage_1.vhdl\n",
      "analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage_2.vhdl\n",
      "analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage_3.vhdl\n",
      "analyze /tmp/myirl_bs_gv9ug3vk/shifter_stage_4.vhdl\n",
      "analyze /tmp/myirl_bs_gv9ug3vk/barrel_shifter.vhdl\n",
      "analyze /tmp/myirl_top_top_bs_dzf9st8l/top_bs.vhdl\n",
      "elaborate top_bs\n",
      "\n",
      "==== COSIM stderr ====\n",
      "\n",
      "==== COSIM stdout ====\n",
      "0x00DEAD00\n",
      "0x47808000\n",
      "/tmp/myirl_top_top_bs_dzf9st8l/top_bs.vhdl:69:9:@22ns:(assertion failure): Stop Simulation\n",
      "/tmp/top_bs:error: assertion failed\n",
      "in process .top_bs(myirl).stim\n",
      "/tmp/top_bs:error: simulation failed\n",
      "\n",
      "==== COSIM stderr ====\n",
      "\n"
     ]
    },
    {
     "data": {
      "text/plain": [
       "0"
      ]
     },
     "execution_count": 6,
     "metadata": {},
     "output_type": "execute_result"
    }
   ],
   "source": [
    "from myirl import targets\n",
    "from myirl.test.common_test import run_ghdl\n",
    "\n",
    "f = design.elab(targets.VHDL, elab_all = True)\n",
    "f += b.elab(targets.VHDL)\n",
    "# print(f)\n",
    "run_ghdl(f, design, vcdfile = 'bs.vcd', debug = True)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 7,
   "metadata": {},
   "outputs": [],
   "source": [
    "# !cat -n /tmp/barrel_shifter.vhdl"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 8,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "DEBUG CALLING CYTHONIZED CODE\n"
     ]
    }
   ],
   "source": [
    "from library.test import *\n",
    "l = cy_library(\"gna\", targets.VHDL)"
   ]
  },
  {
   "cell_type": "code",
   "execution_count": 9,
   "metadata": {},
   "outputs": [
    {
     "name": "stdout",
     "output_type": "stream",
     "text": [
      "\u001b[7;35m Declare obj 'unit0' in context '(LIB: cy_library 'gna')' \u001b[0m\n",
      "Creating process '_run/worker' with sensitivity (clk'rising,)\n"
     ]
    }
   ],
   "source": [
    "def test1():\n",
    "    clk = ClkSignal()\n",
    "    a, b = [ Signal(bool()) for _ in range(2) ]\n",
    "    u = l.unit0(clk, a, b)\n",
    "\n",
    "test1()"
   ]
  }
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