{ "cells": [ { "cell_type": "markdown", "id": "dfd7651d-06e5-482e-9a54-e086f7094cea", "metadata": {}, "source": [ "# Direct RTL via yosys\n", "\n", "The former 'jupyosys' fork from myHDL is in process of migrating into this development tree. However, it is regarded unstable, as the Python API towards yosys is likely going to be redesigned." ] }, { "cell_type": "code", "execution_count": 1, "id": "f3a927f3-aba0-4662-a83b-3077b8c78c82", "metadata": {}, "outputs": [], "source": [ "from myirl.emulation.myhdl import *\n", "\n", "Byte = Signal.Type(intbv, 8)\n", "Bool = Signal.Type(bool)\n", "\n", "@block\n", "def lfsr8(clk : ClkSignal, ce : Bool, reset : ResetSignal, dout : Byte.Output,\n", " RVAL : int = 1):\n", " \"\"\"LFSR with all states\"\"\"\n", " \n", " v = Signal(intbv(RVAL)[8:])\n", " \n", " fb = Signal(bool())\n", " \n", " e = v[7:0] == 0\n", "\n", " @always_seq(clk.posedge, reset)\n", " def worker():\n", " if ce == 1:\n", " v.next = concat(v[6], v[5], v[4], v[3] ^ fb, v[2] ^ fb, v[1] ^ fb, v[0], fb)\n", "\n", " @always_comb\n", " def assign():\n", " fb.next = v[7] ^ e\n", " dout.next = v\n", "\n", " return instances()\n", "\n", "# Wrapper hack to use local dictionary for instance naming\n", "def use_local_names(arg):\n", " arg.use_local_names = True\n", " return arg\n", "\n", "@use_local_names\n", "@block\n", "def unit_count(clk : ClkSignal, ce: Signal, reset : ResetSignal, q : Signal.Output):\n", " \n", " c, d = [ Signal(intbv(0)[8:]) for _ in range(2) ]\n", " \n", " inst_lfsr = lfsr8(clk, ce, reset, d, RVAL = 0xfa)\n", "\n", " @always_seq(clk.posedge, reset)\n", " def counter():\n", " c.next = c + 1\n", "# q.next = d ^ c\n", "\n", " wires = [ q.wireup(d ^ c) ]\n", " \n", " return instances()" ] }, { "cell_type": "code", "execution_count": 2, "id": "c476cce3-5621-4f1d-86ed-50545e94cff7", "metadata": {}, "outputs": [], "source": [ "from myirl.targets import pyosys\n", "\n", "def test_expr(tgt):\n", " ce = Signal(bool())\n", " clk = ClkSignal()\n", " reset = ResetSignal(0, 1, isasync = True)\n", " q = Signal(intbv()[8:])\n", "\n", " t = unit_count(clk, ce, reset, q)\n", " designs = t.elab(tgt, elab_all = True)\n", "\n", " return designs[0]" ] }, { "cell_type": "code", "execution_count": 3, "id": "17f66eb8-0222-4083-aff3-1577e6ba05a7", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ " DEBUG CREATE wrapper module for unit_count (EmulationModule 'top_unit_count') \n", "Creating process 'lfsr8/worker' with sensitivity (clk'rising, )\n", "Creating process 'unit_count/counter' with sensitivity (clk'rising, )\n", " Elaborating component lfsr8_s1_s1_s1_s8_250 \n", "\u001b[32m Adding module with name `lfsr8` \u001b[0m\n", " DEBUG: SKIP NON-SIGNAL ARGUMENT `RVAL` : \n", " Elaborating component unit_count_s1_s1_s1_s8 \n", "\u001b[32m Adding module with name `unit_count` \u001b[0m\n", " DEBUG: Not adding `RVAL` (type ) to ports \n", "\u001b[7;34m FINALIZE implementation `unit_count` of `unit_count` \u001b[0m\n", "\n", "-- Running command `hierarchy -top \\unit_count' --\n", "\n", "1. Executing HIERARCHY pass (managing design hierarchy).\n", "\n", "1.1. Analyzing design hierarchy..\n", "Top module: \\unit_count\n", "Used module: \\lfsr8\n", "\n", "1.2. Analyzing design hierarchy..\n", "Top module: \\unit_count\n", "Used module: \\lfsr8\n", "Removed 0 unused modules.\n", "\n", "-- Running command `show -format dot -prefix top unit_count' --\n", "\n", "2. Generating Graphviz representation of design.\n", "Writing dot description to `top.dot'.\n", "Dumping module unit_count to page 1.\n" ] } ], "source": [ "tgt = pyosys.RTLIL(\"top\")\n", "\n", "design = test_expr(tgt)\n", "design.display_rtl(selection = \"unit_count\", fmt='dot')\n", "# design.display_rtl(selection = \"lfsr8\", fmt='dot')" ] }, { "cell_type": "markdown", "id": "f66bb0eb-feca-4b75-8050-02cc7d15dc16", "metadata": {}, "source": [ "### RTL Display\n", "\n", "The `@use_local_names` construct sets the myHDL instance variable names for the identifier.\n", "\n", "Note: Pan and zoom may not work on some browsers." ] }, { "cell_type": "code", "execution_count": 4, "id": "fc8b26c2-c4d0-4874-b9df-cb05bc5bcff2", "metadata": {}, "outputs": [ { "data": { "text/html": [ "\n", "
\n", " \n", " \n", " \n", " \n", "\n", "unit_count\n", "\n", "unit_count\n", "\n", "\n", "n7\n", "\n", "q\n", "\n", "\n", "\n", "n8\n", "\n", "reset\n", "\n", "\n", "\n", "c21\n", "\n", "ARST\n", "\n", "CLK\n", "\n", "D\n", "\n", "$counter::c_6619\n", "$adff\n", "\n", "Q\n", "\n", "\n", "\n", "n8:e->c21:w\n", "\n", "\n", "\n", "\n", "\n", "c24\n", "\n", "ce\n", "\n", "clk\n", "\n", "reset\n", "\n", "inst_lfsr\n", "lfsr8\n", "\n", "dout\n", "\n", "\n", "\n", "n8:e->c24:w\n", "\n", "\n", "\n", "\n", "\n", "n9\n", "\n", "ce\n", "\n", "\n", "\n", "n9:e->c24:w\n", "\n", "\n", "\n", "\n", "\n", "n10\n", "\n", "clk\n", "\n", "\n", "\n", "n10:e->c21:w\n", "\n", "\n", "\n", "\n", "\n", "n10:e->c24:w\n", "\n", "\n", "\n", "\n", "\n", "n11\n", "\n", "c\n", "\n", "\n", "\n", "c16\n", "\n", "A\n", "\n", "B\n", "\n", "$counter:44::ab0c/xor:_u\n", "$xor\n", "\n", "Y\n", "\n", "\n", "\n", "n11:e->c16:w\n", "\n", "\n", "\n", "\n", "\n", "x2\n", "\n", "BUF\n", "\n", "\n", "\n", "n11:e->x2:w\n", "\n", "\n", "\n", "\n", "\n", "n12\n", "\n", "d\n", "\n", "\n", "\n", "n12:e->c16:w\n", "\n", "\n", "\n", "\n", "\n", "x5\n", "\n", "BUF\n", "\n", "\n", "\n", "c16:e->x5:w\n", "\n", "\n", "\n", "\n", "\n", "x4\n", "\n", "BUF\n", "\n", "\n", "\n", "c21:e->x4:w\n", "\n", "\n", "\n", "\n", "\n", "v0\n", "\n", "9'000000001\n", "\n", "\n", "\n", "c22\n", "\n", "A\n", "\n", "B\n", "\n", "$counter:44::0398/add:_u\n", "$add\n", "\n", "Y\n", "\n", "\n", "\n", "v0:e->c22:w\n", "\n", "\n", "\n", "\n", "\n", "x3\n", "\n", "7:0 - 7:0\n", "\n", "\n", "\n", "c22:e->x3:w\n", "\n", "\n", "\n", "\n", "\n", "x1\n", "\n", "0 -> 8:8\n", "\n", "7:0 - 7:0\n", "\n", "\n", "\n", "x1:e->c22:w\n", "\n", "\n", "\n", "\n", "\n", "\n", "c24:e->n12:w\n", "\n", "\n", "\n", "\n", "\n", "x2:e->x1:w\n", "\n", "\n", "\n", "\n", "\n", "x3:e->c21:w\n", "\n", "\n", "\n", "\n", "\n", "x4:e->n11:w\n", "\n", "\n", "\n", "\n", "\n", "x5:e->n7:w\n", "\n", "\n", "\n", "\n", "\n", "\\n\n", "\n", "\n", "\n", "\n", "
\n", " " ], "text/plain": [ "" ] }, "execution_count": 4, "metadata": {}, "output_type": "execute_result" } ], "source": [ "from yosys import display\n", "display.display_dot(design.name)" ] }, { "cell_type": "markdown", "id": "ee9de89e-781f-4646-a962-5928cd8d3b4b", "metadata": {}, "source": [ "## Test bench (myHDL style)\n", "\n", "Note that `and`, `or` and `not` boolean constructs are no longer allowed with signals." ] }, { "cell_type": "code", "execution_count": 5, "id": "21365dab-9b35-4e8c-927e-68a00d004bc9", "metadata": {}, "outputs": [], "source": [ "from simulation import *\n", "\n", "from yosys.simulator import CXXRTL as Sim\n", "\n", "@sim.testbench(Sim, time_unit = 'ns')\n", "def testbench():\n", " clk = ClkSignal(init = 0)\n", " reset = ResetSignal(1, 1, isasync = False)\n", " ce = Signal(bool())\n", "\n", " a = Signal(intbv()[8:])\n", "\n", " inst = unit_count(clk, ce, reset, a)\n", "\n", " @always(delay(2))\n", " def clkgen():\n", " clk.next = ~ clk\n", "\n", " @sequence\n", " def reset_seq():\n", " yield delay(21)\n", " reset.next = False\n", " yield delay(1)\n", " ce.next = True\n", " yield delay(20)\n", "\n", " return instances()" ] }, { "cell_type": "markdown", "id": "31861a7c-7740-4896-8754-b870ef17e7fe", "metadata": {}, "source": [ "The simulation is executed using the `.run` method below. Note that the simulation may not be fully 'delta' accurate and will only serve for synchronous designs.\n", "\n", "**Note**: It is mandatory to yield an initial delay in the sequential code to properly arm the concurrent process scheduling." ] }, { "cell_type": "code", "execution_count": 6, "id": "441f6d7e-da0f-4175-8087-98f00d72e64f", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ " DEBUG CREATE wrapper module for unit_count (EmulationModule 'top_unit_count') \n", "\u001b[32m Module top_unit_count: Existing implementation unit_count, rename to unit_count_1 \u001b[0m\n", "\u001b[32m Module top_unit_count: Existing implementation lfsr8, rename to lfsr8_1 \u001b[0m\n", "Creating process 'lfsr8/worker' with sensitivity (clk'rising, )\n", "Creating process 'unit_count/counter' with sensitivity (clk'rising, )\n", " Elaborating component lfsr8_s1_s1_s1_s8_250 \n", "\u001b[32m Adding module with name `lfsr8_1` \u001b[0m\n", " DEBUG: SKIP NON-SIGNAL ARGUMENT `RVAL` : \n", " Elaborating component unit_count_s1_s1_s1_s8 \n", "\u001b[32m Adding module with name `unit_count_1` \u001b[0m\n", " DEBUG: Not adding `RVAL` (type ) to ports \n", "\u001b[7;34m FINALIZE implementation `unit_count_1` of `unit_count` \u001b[0m\n", "\n", "-- Running command `hierarchy -check' --\n", "\n", "3. Executing HIERARCHY pass (managing design hierarchy).\n", "\n", "-- Running command `hierarchy -top \\unit_count_1' --\n", "\n", "4. Executing HIERARCHY pass (managing design hierarchy).\n", "\n", "4.1. Analyzing design hierarchy..\n", "Top module: \\unit_count_1\n", "Used module: \\lfsr8_1\n", "\n", "4.2. Analyzing design hierarchy..\n", "Top module: \\unit_count_1\n", "Used module: \\lfsr8_1\n", "Removed 0 unused modules.\n", "\n", "-- Running command `debug write_cxxrtl -namespace unit_count_1_468f -header /tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f_rtl.cpp' --\n", "\n", "5. Executing CXXRTL backend.\n", "\n", "5.1. Executing HIERARCHY pass (managing design hierarchy).\n", "\n", "5.1.1. Analyzing design hierarchy..\n", "Top module: \\unit_count_1\n", "Used module: \\lfsr8_1\n", "\n", "5.1.2. Analyzing design hierarchy..\n", "Top module: \\unit_count_1\n", "Used module: \\lfsr8_1\n", "Removed 0 unused modules.\n", "\n", "5.2. Executing FLATTEN pass (flatten design).\n", "Flattening unit_count_1.inst_lfsr (lfsr8_1).\n", "Deleting now unused module lfsr8_1.\n", "\n", "5.3. Executing PROC pass (convert processes to netlists).\n", "\n", "5.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n", "Cleaned up 0 empty switches.\n", "\n", "5.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n", "Removed a total of 0 dead cases.\n", "\n", "5.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).\n", "Removed 0 redundant assignments.\n", "Promoted 0 assignments to connections.\n", "\n", "5.3.4. Executing PROC_INIT pass (extract init attributes).\n", "\n", "5.3.5. Executing PROC_ARST pass (detect async resets in processes).\n", "\n", "5.3.6. Executing PROC_MUX pass (convert decision trees to multiplexers).\n", "\n", "5.3.7. Executing PROC_DLATCH pass (convert process syncs to latches).\n", "\n", "5.3.8. Executing PROC_DFF pass (convert process syncs to FFs).\n", "\n", "5.3.9. Executing PROC_MEMWR pass (convert process memory writes to cells).\n", "\n", "5.3.10. Executing PROC_CLEAN pass (remove empty switches from decision trees).\n", "Cleaned up 0 empty switches.\n", "\n", "5.3.11. Executing OPT_EXPR pass (perform const folding).\n", "Optimizing module unit_count_1.\n", "Replacing $eq cell `$flatten\\inst_lfsr.$assign:24::a81a/eq:_u' in module `unit_count_1' with $logic_not.\n", "Replacing $eq cell `$flatten\\inst_lfsr.$worker:20::9a6a/eq:_u' (1) in module `\\unit_count_1' with constant driver `$flatten\\inst_lfsr.$auto$yosys.pyosys_wrappers:0:$21 = \\inst_lfsr.ce'.\n", "Compiling /tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f.pyx because it changed.\n", "[1/1] Cythonizing /tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f.pyx\n", "running build_ext\n", "building 'unit_count_1_468f' extension\n", "creating build/temp.linux-x86_64-3.9/tmp/myirl_top_unit_count_36y5jpbr\n", "x86_64-linux-gnu-gcc -pthread -Wno-unused-result -Wsign-compare -DNDEBUG -g -fwrapv -O2 -Wall -g -ffile-prefix-map=/build/python3.9-RNBry6/python3.9-3.9.2=. -fstack-protector-strong -Wformat -Werror=format-security -g -fwrapv -O2 -g -ffile-prefix-map=/build/python3.9-RNBry6/python3.9-3.9.2=. -fstack-protector-strong -Wformat -Werror=format-security -Wdate-time -D_FORTIFY_SOURCE=2 -fPIC -I/home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/../yosys/cxxrtl -I/tmp/myirl_top_unit_count_36y5jpbr/ -I/usr/share/yosys/include -I/usr/include/python3.9 -c /tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f.cpp -o build/temp.linux-x86_64-3.9/tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f.o\n", "x86_64-linux-gnu-gcc -pthread -Wno-unused-result -Wsign-compare -DNDEBUG -g -fwrapv -O2 -Wall -g -ffile-prefix-map=/build/python3.9-RNBry6/python3.9-3.9.2=. -fstack-protector-strong -Wformat -Werror=format-security -g -fwrapv -O2 -g -ffile-prefix-map=/build/python3.9-RNBry6/python3.9-3.9.2=. -fstack-protector-strong -Wformat -Werror=format-security -Wdate-time -D_FORTIFY_SOURCE=2 -fPIC -I/home/testing/.local/lib/python3.9/site-packages/myirl-0.0.0-py3.9-linux-x86_64.egg/myirl/../yosys/cxxrtl -I/tmp/myirl_top_unit_count_36y5jpbr/ -I/usr/share/yosys/include -I/usr/include/python3.9 -c /tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f_rtl.cpp -o build/temp.linux-x86_64-3.9/tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f_rtl.o\n", "x86_64-linux-gnu-g++ -pthread -shared -Wl,-O1 -Wl,-Bsymbolic-functions -Wl,-z,relro -g -fwrapv -O2 -Wl,-z,relro -g -fwrapv -O2 -g -ffile-prefix-map=/build/python3.9-RNBry6/python3.9-3.9.2=. -fstack-protector-strong -Wformat -Werror=format-security -Wdate-time -D_FORTIFY_SOURCE=2 build/temp.linux-x86_64-3.9/tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f.o build/temp.linux-x86_64-3.9/tmp/myirl_top_unit_count_36y5jpbr/unit_count_1_468f_rtl.o -o build/lib.linux-x86_64-3.9/unit_count_1_468f.cpython-39-x86_64-linux-gnu.so\n", "copying build/lib.linux-x86_64-3.9/unit_count_1_468f.cpython-39-x86_64-linux-gnu.so -> \n", "Open for writing: testbench.vcd\n", "STOP PROCESS reset_seq\n" ] } ], "source": [ "def test_simulation(n):\n", " t = testbench()\n", " assert t._uut.obj.ctx == unit_count.ctx\n", " t.run(n)\n", " return t\n", "\n", "t = test_simulation(2000)" ] }, { "cell_type": "code", "execution_count": 7, "id": "340e8b0d-e325-48ed-9ea9-f06352ccae38", "metadata": {}, "outputs": [ { "data": { "text/plain": [ "'./sim_top.cpython-39-x86_64-linux-gnu.so'" ] }, "execution_count": 7, "metadata": {}, "output_type": "execute_result" } ], "source": [ "# Make sure we got the right one, in case the above fails:\n", "sys.path.insert(0, '.')\n", "import sim_top\n", "sim_top.__file__" ] }, { "cell_type": "markdown", "id": "b48fab93-be1e-4b1a-b2cd-a4981a931e70", "metadata": {}, "source": [ "The resulting test bench file: [testbench.vcd](testbench.vcd)" ] }, { "cell_type": "markdown", "id": "6a145b11-29ac-4a55-9580-5e8da1178d33", "metadata": {}, "source": [ "## Customizing RTLIL targets\n", "\n", "When the `.elab()` method is called, the design is elaborated as RTLIL and a list of design elements is returned, the first being a RTLIL Design handle.\n", "The `.finalize()` method is called last inside elaboration, which can perform some optimizations or emissions to specific targets.\n", "\n" ] }, { "cell_type": "code", "execution_count": 8, "id": "f472f6fd-6039-45f6-bda2-219c94cbca33", "metadata": {}, "outputs": [], "source": [ "class MyRTL(pyosys.RTLIL):\n", " def finalize(self, top):\n", " tname = top.name\n", " design = self._design\n", " design.run(\"hierarchy -top %s\" % tname)\n", " print(80 * '=')\n", " design.write_verilog(name = top.obj.name)\n", " design.run(\"flatten; ls; select %s; stat\" % tname)" ] }, { "cell_type": "code", "execution_count": 9, "id": "490b03b6-6cfb-4465-832c-b5ebfa8b5a44", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ " Elaborating component lfsr8_s1_s1_s1_s8_250 \n", "\u001b[32m Adding module with name `lfsr8_1` \u001b[0m\n", " DEBUG: SKIP NON-SIGNAL ARGUMENT `RVAL` : \n", " Elaborating component unit_count_s1_s1_s1_s8 \n", "\u001b[32m Adding module with name `unit_count_1` \u001b[0m\n", " DEBUG: Not adding `RVAL` (type ) to ports \n", "================================================================================\n", "\n", "Debug information statistics for module `unit_count_1':\n", " Public wires: 12, of which:\n", " Member wires: 4, of which:\n", " Undriven: 3 (incl. inputs)\n", " Driven sync: 0\n", " Driven comb: 1\n", " Mixed driver: 0\n", " Inline wires: 1\n", " Alias wires: 7\n", " Const wires: 0\n", " Other wires: 0\n", "\n", "-- Running command `hierarchy -top unit_count_1' --\n", "\n", "6. Executing HIERARCHY pass (managing design hierarchy).\n", "\n", "6.1. Analyzing design hierarchy..\n", "Top module: \\unit_count_1\n", "Used module: \\lfsr8_1\n", "\n", "6.2. Analyzing design hierarchy..\n", "Top module: \\unit_count_1\n", "Used module: \\lfsr8_1\n", "Removed 0 unused modules.\n", "\n", "-- Running command `ls; check' --\n", "\n", "7. Executing CHECK pass (checking for obvious problems).\n", "Found and reported 0 problems.\n", "\n", "-- Running command `hierarchy -check' --\n", "\n", "8. Executing HIERARCHY pass (managing design hierarchy).\n", "\n", "-- Running command `write_verilog unit_count_mapped.v' --\n", "\n", "9. Executing Verilog backend.\n", "Dumping module `\\lfsr8_1'.\n", "Dumping module `\\unit_count_1'.\n", "\n", "-- Running command `flatten; ls; select unit_count_1; stat' --\n", "\n", "10. Executing FLATTEN pass (flatten design).\n", "Deleting now unused module lfsr8_1.\n", "\n", "\n", "1 modules:\n", " unit_count_1\n", "\n", "11. Printing statistics.\n" ] } ], "source": [ "tgt = MyRTL(\"top2\")\n", "\n", "design = test_expr(tgt)" ] }, { "cell_type": "code", "execution_count": 10, "id": "7195d6f9-aeaf-4464-ac62-6dc5ad7dba64", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "/* Generated by Yosys 0.13+3 (git sha1 4656b0171, gcc 10.2.1-6 -Og -fPIC) */\n", "\n", "module lfsr8_1(clk, ce, reset, dout);\n", " wire [7:0] _00_;\n", " wire [-1:0] _01_;\n", " wire _02_;\n", " wire _03_;\n", " wire _04_;\n", " wire _05_;\n", " wire [7:0] _06_;\n", " wire _07_;\n", " wire _08_;\n", " wire _09_;\n", " wire [7:0] _10_;\n", " reg [7:0] _11_;\n", " wire [7:0] _12_;\n", " wire [7:0] _13_;\n", " input ce;\n", " input clk;\n", " output [7:0] dout;\n", " wire fb;\n", " input reset;\n", " wire [7:0] v;\n", " assign _09_ = v[7] ^ _08_;\n", " assign _08_ = v[6:0] == 7'h00;\n", " assign _03_ = v[2] ^ fb;\n", " assign _06_ = _05_ ? _00_ : _13_;\n", " assign _04_ = v[3] ^ fb;\n", " assign _05_ = ce == 1'h1;\n", " assign _02_ = v[1] ^ fb;\n", " always @(posedge clk)\n", " _11_ <= _12_;\n", " assign _12_ = reset ? 8'hfa : _06_;\n", " assign _00_ = { v[6:4], _04_, _03_, _02_, v[0], fb };\n", " assign v = _11_;\n", " assign _13_ = _11_;\n", " assign _07_ = _09_;\n", " assign _10_ = v;\n", " assign fb = _07_;\n", " assign dout = _10_;\n", "endmodule\n", "\n", "(* top = 1 *)\n", "module unit_count_1(clk, ce, reset, q);\n", " wire [7:0] _0_;\n", " wire [7:0] _1_;\n", " wire [9:0] _2_;\n", " wire [7:0] _3_;\n", " reg [7:0] _4_;\n", " wire [7:0] _5_;\n", " wire [7:0] c;\n", " input ce;\n", " input clk;\n", " wire [7:0] d;\n", " output [7:0] q;\n", " input reset;\n", " assign _3_ = d ^ c;\n", " assign _2_ = { 1'h0, _1_ } + 9'h001;\n", " always @(posedge clk)\n", " _4_ <= _5_;\n", " assign _5_ = reset ? 8'h00 : _0_;\n", " lfsr8_1 inst_lfsr (\n", " .ce(ce),\n", " .clk(clk),\n", " .dout(d),\n", " .reset(reset)\n", " );\n", " assign _1_ = c;\n", " assign _0_ = _2_[7:0];\n", " assign c = _4_;\n", " assign q = _3_;\n", "endmodule\n" ] } ], "source": [ "!cat unit_count_mapped.v" ] } ], "metadata": { "kernelspec": { "display_name": "Python 3 (ipykernel)", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.9.2" } }, "nbformat": 4, "nbformat_minor": 5 }