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Std::Bits::Add_int Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Instr_AND AL AL_write Next_IP let operand_size := 8; let src1 := AL; let src2 := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; let result := Instr_AND(operand_size, src1, src2); AL := result; AL imm8 src1 AL result AL src2 imm8 let result := src1 and src2; RFLAGS.OF := 0b0; RFLAGS.SF := result[operand_size-1]; RFLAGS.ZF := Bit(Is_Zero(result)); RFLAGS.AF := UNSPECIFIED : Bit; RFLAGS.PF := Bit(Is_Parity_Even(result[0 +: 8])); RFLAGS.CF := 0b0; Std::Integer::Le Std::Integer::Lt Std::Integer::Subtract Std::Bits::And Std::Bits::Is_Zero Std::Bits::Is_Parity_Even Bit RFLAGS Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_RAX Instr_AND RAX Next_IP let src1 := RAX[0 +: operand_size]; let src2 := Sign_Extend(Mem_Fetch?(ip, Min(operand_size, 32)), operand_size); LockPrefix #UD Next_IP := ip + (Min(operand_size, 32) / 8); let result := Instr_AND(operand_size, src1, src2); Write_RAX(result); AX/EAX/RAX immz src1 AX/EAX/RAX result AX/EAX/RAX src2 immz Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_AND Next_IP let operand_size := 8; let src1 := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let src2 := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; let result := Instr_AND(operand_size, src1, src2); Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result); r8 imm8 src1 ModRM:r/m r8 result ModRM:r/m r8 src2 imm8 Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Mem_Fetch Instr_AND False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0 + 1; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result); mv imm8 src1 ModRM:r/m mv result ModRM:r/m mv src2 imm8 Std::Boolean::Not Std::Boolean::Strict_Or Std::Integer::Add Std::Integer::Ne Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Data_Size_Of_Current_Mode In_64Bit_Mode Mem_Fetch Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_AND Next_IP let operand_size := 8; let src1 := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let src2 := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); if not ((Data_Size_Of_Current_Mode() != 64)) then Report_Invalid_Opcode!(); endif; LockPrefix #UD Mode64 #UD Next_IP := ip + 1; let result := Instr_AND(operand_size, src1, src2); Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result); r8 imm8 src1 ModRM:r/m r8 result ModRM:r/m r8 src2 imm8 Std::Boolean::Not Std::Integer::Ne Std::Bits::Add_int Std::Bits::Sign_Extend Data_Size_Of_Current_Mode Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_AND False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); if not ((Data_Size_Of_Current_Mode() != 64)) then Report_Invalid_Opcode!(); endif; Mode64 #UD let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0 + 1; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result); mv imm8 src1 ModRM:r/m mv result ModRM:r/m mv src2 imm8 Std::Integer::Add Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Read_GPR Report_Invalid_Opcode Write_GPR Instr_AND Next_IP let src1 := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); let src2 := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; let result := Instr_AND(operand_size, src1, src2); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result); rv imm8 src1 ModRM:r/m rv result ModRM:r/m rv src2 imm8 Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Mem_Fetch Instr_AND False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0 + 1; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result); mv imm8 src1 ModRM:r/m mv result ModRM:r/m mv src2 imm8 Std::Integer::Add Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Read_GPR Report_Invalid_Opcode Write_GPR Instr_AND Next_IP let src1 := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); let src2 := Sign_Extend(Mem_Fetch?(ip, Min(operand_size, 32)), operand_size); LockPrefix #UD Next_IP := ip + (Min(operand_size, 32) / 8); let result := Instr_AND(operand_size, src1, src2); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result); rv immz src1 ModRM:r/m rv result ModRM:r/m rv src2 immz Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Mem_Fetch Instr_AND False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, Min(operand_size, 32)), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8)); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result); mv immz src1 ModRM:r/m mv result ModRM:r/m mv src2 immz Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_GPR Instr_AND Next_IP let src1 := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); let src2 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); LockPrefix #UD Next_IP := ip; let result := Instr_AND(operand_size, src1, src2); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result); rv1 rv2 src1 ModRM:r/m rv1 result ModRM:r/m rv1 src2 ModRM:reg rv2 Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Read_GPR Instr_AND False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result); mv1 rv2 src1 ModRM:r/m mv1 result ModRM:r/m mv1 src2 ModRM:reg rv2 Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_GPR Instr_AND Next_IP let src1 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let src2 := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); LockPrefix #UD Next_IP := ip; let result := Instr_AND(operand_size, src1, src2); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result); rv1 rv2 src1 ModRM:reg rv1 result ModRM:reg rv1 src2 ModRM:r/m rv2 Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Read_GPR Report_Invalid_Opcode Write_GPR Instr_AND False Memory_Read Normal_Alignment Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src1 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src2 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_AND(operand_size, src1, src2); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result); rv1 mv2 src1 ModRM:reg rv1 result ModRM:reg rv1 src2 ModRM:r/m mv2 Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_AND Next_IP let operand_size := 8; let src1 := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let src2 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); LockPrefix #UD Next_IP := ip; let result := Instr_AND(operand_size, src1, src2); Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result); r81 r82 src1 ModRM:r/m r81 result ModRM:r/m r81 src2 ModRM:reg r82 Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Read_GPR8 Instr_AND False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result); mv1 r82 src1 ModRM:r/m mv1 result ModRM:r/m mv1 src2 ModRM:reg r82 Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_AND Next_IP let operand_size := 8; let src1 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let src2 := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); LockPrefix #UD Next_IP := ip; let result := Instr_AND(operand_size, src1, src2); Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result); r81 r82 src1 ModRM:reg r81 result ModRM:reg r81 src2 ModRM:r/m r82 Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_AND False Memory_Read Normal_Alignment Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src1 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src2 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_AND(operand_size, src1, src2); Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result); r81 mv2 src1 ModRM:reg r81 result ModRM:reg r81 src2 ModRM:r/m mv2 Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Read_GPR Instr_AND True False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, acquire_lock=>True, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result, release_lock=>True); mv rv src1 ModRM:r/m mv result ModRM:r/m mv src2 ModRM:reg rv Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Read_GPR8 Instr_AND True False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, acquire_lock=>True, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result, release_lock=>True); mv r8 src1 ModRM:r/m mv result ModRM:r/m mv src2 ModRM:reg r8 Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Mem_Fetch Instr_AND True False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, acquire_lock=>True, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0 + 1; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result, release_lock=>True); mv imm8 src1 ModRM:r/m mv result ModRM:r/m mv src2 imm8 Std::Boolean::Not Std::Integer::Ne Std::Bits::Add_int Std::Bits::Sign_Extend Data_Size_Of_Current_Mode Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_AND True False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); if not ((Data_Size_Of_Current_Mode() != 64)) then Report_Invalid_Opcode!(); endif; Mode64 #UD let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, acquire_lock=>True, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0 + 1; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result, release_lock=>True); mv imm8 src1 ModRM:r/m mv result ModRM:r/m mv src2 imm8 Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Mem_Fetch Instr_AND True False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, acquire_lock=>True, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0 + 1; let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result, release_lock=>True); mv imm8 src1 ModRM:r/m mv result ModRM:r/m mv src2 imm8 Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Logical_Mem_Write Mem_Fetch Instr_AND True False Memory_Read_Modify_Write Normal_Alignment Memory_Type_Unknown Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, Min(operand_size, 32)), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8)); let src1 := Logical_Mem_Read?(segment, effective_address, operand_size, acquire_lock=>True, access_type=>Memory_Read_Modify_Write); Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_AND(operand_size, src1, src2); Logical_Mem_Write?(segment, effective_address, result, release_lock=>True); mv immz src1 ModRM:r/m mv result ModRM:r/m mv src2 immz scalar integer logical

A locked read-modify-write memory access is performed. With a REX prefix in 64-bit mode, attempts to access AH, BH, CH, or DH will instead access SPL, DIL, BPL, or SIL, respectively. Operand is sign-extended to operand_size bits.