Copyright (C) Intel Corporation. All Rights Reserved. # Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. All product plans and roadmaps are subject to change without notice. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not “commercial” names and not intended to function as trademarks. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document, with the sole exception that a) you may publish an unmodified copy and b) code, identified as Sample Code in this document is licensed subject to the Zero-Clause BSD open source license (0BSD), [https://opensource.org/licenses/0BSD](https://opensource.org/licenses/0BSD). You may create software implementations based on this document and in compliance with the foregoing that are intended to execute on the Intel product(s) referenced in this document. No rights are granted to create modifications or derivatives of this document. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. If you give Intel any comments or suggestions related to this document or the information contained in it, Intel can use them in any way and disclose them to anyone, without payment or other obligations to you. You represent and warrant that you own, or have sufficient rights from the owner of, any such comments or suggestions, and the intellectual property rights in them, to grant the above permission. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. The code in this file is not 'Sample Code'. Std::Bits::Add_int Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Instr_CMP AL Next_IP let operand_size := 8; let src1 := AL; let src2 := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; Instr_CMP(operand_size, src1, src2); AL imm8 src1 src2 let (result, carry_out, overflow, alternative_carry) := Subtract(src1, src2); RFLAGS.OF := overflow; RFLAGS.SF := result[operand_size-1]; RFLAGS.ZF := Bit(Is_Zero(result)); RFLAGS.AF := alternative_carry; RFLAGS.PF := Bit(Is_Parity_Even(result[0 +: 8])); RFLAGS.CF := carry_out; Std::Integer::Le Std::Integer::Lt Std::Integer::Subtract Std::Bits::Is_Zero Std::Bits::Is_Parity_Even Bit Subtract RFLAGS Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Instr_CMP RAX Next_IP let src1 := RAX[0 +: operand_size]; let src2 := Sign_Extend(Mem_Fetch?(ip, Min(operand_size, 32)), operand_size); LockPrefix #UD Next_IP := ip + (Min(operand_size, 32) / 8); Instr_CMP(operand_size, src1, src2); AX/EAX/RAX immz src1 src2 Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Read_GPR8 Report_Invalid_Opcode Instr_CMP Next_IP let operand_size := 8; let src1 := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let src2 := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; Instr_CMP(operand_size, src1, src2); r8 imm8 src1 ModRM:r/m src2 Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Mem_Fetch Report_Invalid_Opcode Instr_CMP False Memory_Read Normal_Alignment Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); LockPrefix #UD let src1 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0 + 1; Instr_CMP(operand_size, src1, src2); mv imm8 src1 ModRM:r/m src2 Std::Boolean::Not Std::Boolean::Strict_Or Std::Integer::Add Std::Integer::Ne Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Data_Size_Of_Current_Mode In_64Bit_Mode Mem_Fetch Read_GPR8 Report_Invalid_Opcode Instr_CMP Next_IP let operand_size := 8; let src1 := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let src2 := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); if not ((Data_Size_Of_Current_Mode() != 64)) then Report_Invalid_Opcode!(); endif; LockPrefix #UD Mode64 #UD Next_IP := ip + 1; Instr_CMP(operand_size, src1, src2); r8 imm8 src1 ModRM:r/m src2 Std::Boolean::Not Std::Integer::Ne Std::Bits::Add_int Std::Bits::Sign_Extend Data_Size_Of_Current_Mode Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Mem_Fetch Report_Invalid_Opcode Instr_CMP False Memory_Read Normal_Alignment Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); if not ((Data_Size_Of_Current_Mode() != 64)) then Report_Invalid_Opcode!(); endif; LockPrefix #UD Mode64 #UD let src1 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0 + 1; Instr_CMP(operand_size, src1, src2); mv imm8 src1 ModRM:r/m src2 Std::Integer::Add Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Read_GPR Report_Invalid_Opcode Instr_CMP Next_IP let src1 := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); let src2 := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; Instr_CMP(operand_size, src1, src2); rv imm8 src1 ModRM:r/m src2 Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Mem_Fetch Report_Invalid_Opcode Instr_CMP False Memory_Read Normal_Alignment Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); LockPrefix #UD let src1 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0 + 1; Instr_CMP(operand_size, src1, src2); mv imm8 src1 ModRM:r/m src2 Std::Integer::Add Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Read_GPR Report_Invalid_Opcode Instr_CMP Next_IP let src1 := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); let src2 := Sign_Extend(Mem_Fetch?(ip, Min(operand_size, 32)), operand_size); LockPrefix #UD Next_IP := ip + (Min(operand_size, 32) / 8); Instr_CMP(operand_size, src1, src2); rv immz src1 ModRM:r/m src2 Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Mem_Fetch Report_Invalid_Opcode Instr_CMP False Memory_Read Normal_Alignment Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Sign_Extend(Mem_Fetch?(next_ip0, Min(operand_size, 32)), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8)); LockPrefix #UD let src1 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0 + (Min(operand_size, 32) / 8); Instr_CMP(operand_size, src1, src2); mv immz src1 ModRM:r/m src2 Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Instr_CMP Next_IP let src1 := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); let src2 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); LockPrefix #UD Next_IP := ip; Instr_CMP(operand_size, src1, src2); rv1 rv2 src1 ModRM:r/m src2 ModRM:reg Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Read_GPR Report_Invalid_Opcode Instr_CMP False Memory_Read Normal_Alignment Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src1 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; Instr_CMP(operand_size, src1, src2); mv1 rv2 src1 ModRM:r/m src2 ModRM:reg Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Instr_CMP Next_IP let src1 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let src2 := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); LockPrefix #UD Next_IP := ip; Instr_CMP(operand_size, src1, src2); rv1 rv2 src1 ModRM:reg src2 ModRM:r/m Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Read_GPR Report_Invalid_Opcode Instr_CMP False Memory_Read Normal_Alignment Next_IP let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src1 := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src2 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; Instr_CMP(operand_size, src1, src2); rv1 mv2 src1 ModRM:reg src2 ModRM:r/m Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Instr_CMP Next_IP let operand_size := 8; let src1 := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let src2 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); LockPrefix #UD Next_IP := ip; Instr_CMP(operand_size, src1, src2); r81 r82 src1 ModRM:r/m src2 ModRM:reg Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Read_GPR8 Report_Invalid_Opcode Instr_CMP False Memory_Read Normal_Alignment Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src2 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src1 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; Instr_CMP(operand_size, src1, src2); mv1 r82 src1 ModRM:r/m src2 ModRM:reg Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Instr_CMP Next_IP let operand_size := 8; let src1 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let src2 := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); LockPrefix #UD Next_IP := ip; Instr_CMP(operand_size, src1, src2); r81 r82 src1 ModRM:reg src2 ModRM:r/m Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Read_GPR8 Report_Invalid_Opcode Instr_CMP False Memory_Read Normal_Alignment Next_IP let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src1 := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present)); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src2 := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; Instr_CMP(operand_size, src1, src2); r81 mv2 src1 ModRM:reg src2 ModRM:r/m scalar integer/arithmetic/binary integer/comparison With a REX prefix in 64-bit mode, attempts to access AH, BH, CH, or DH will instead access SPL, DIL, BPL, or SIL, respectively. Operand is sign-extended to operand_size bits.