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Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_GPR8 Instr_MOV

Next_IP

let operand_size := 8; let src := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ opcode[2:0], (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

imm8

result opcode[2:0] r8 src imm8

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_GPR8 Instr_MOV

Next_IP

let operand_size := 8; let src := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ opcode[2:0], (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

imm8

result opcode[2:0] r8 src imm8

let result := src;

MOVDQ2Q

MOVNTDQ

MOVNTDQA

MOVNTI

MOVNTPD

MOVNTPS

MOVNTQ

MOVQ2DQ

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); LockPrefix #UD Next_IP := next_ip0 + 1; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_GPR8 Instr_MOV

Next_IP

let operand_size := 8; let src := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

imm8

result ModRM:r/m r8 src imm8

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_GPR8 Instr_MOV

Next_IP

let operand_size := 8; let src := Sign_Extend(Mem_Fetch?(ip, 8), operand_size); LockPrefix #UD Next_IP := ip + 1; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

imm8

result ModRM:r/m r8 src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); LockPrefix #UD Mode64 #UD Next_IP := next_ip0 + 1; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src := Sign_Extend(Mem_Fetch?(next_ip0, 8), operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1); LockPrefix #UD Mode64 #UD Next_IP := next_ip0 + 1; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

imm8

result ModRM:r/m mv src imm8

Std::Integer::Add Std::Integer::Le Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_GPR Instr_MOV

Next_IP

let src := Sign_Extend(Mem_Fetch?(ip, operand_size), operand_size); LockPrefix #UD Next_IP := ip + (operand_size / 8); let result := Instr_MOV(operand_size, src); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ opcode[2:0], result);

immv

result opcode[2:0] rv src immv

Std::Integer::Add Std::Integer::Le Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_GPR Instr_MOV

Next_IP

immv

result opcode[2:0] rv src immv

Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src := Sign_Extend(Mem_Fetch?(next_ip0, Min(operand_size, 32)), operand_size);

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

Std::Integer::Add Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_GPR Instr_MOV

Next_IP

let src := Sign_Extend(Mem_Fetch?(ip, Min(operand_size, 32)), operand_size); LockPrefix #UD Next_IP := ip + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result);

immz

result ModRM:r/m rv src immz

Std::Integer::Add Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Append Std::Bits::Sign_Extend Mem_Fetch Report_Invalid_Opcode Write_GPR Instr_MOV

Next_IP

immz

result ModRM:r/m rv src immz

Std::Integer::Le Std::Integer::Min Std::Integer::Positive_Divide Std::Bits::Add_int Std::Bits::Sign_Extend Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Write Mem_Fetch Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Mode64 #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Mode64 #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + (Min(operand_size, 32) / 8));

LockPrefix #UD Next_IP := next_ip0 + (Min(operand_size, 32) / 8); let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

immz

result ModRM:r/m mv src immz

Std::Boolean::Not Direct_Memory_Offset Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Instr_MOV AL_write

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 8; let (segment, ea_offset, next_ip0) := Direct_Memory_Offset?(address_size, context, ip); let is_rip_relative := False; let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); if not (not context.rex2_prefix_present) then Report_Invalid_Opcode!(); endif; LockPrefix #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); AL := result;

result AL src ModRM:r/m mv

Std::Boolean::Not Direct_Memory_Offset Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Instr_MOV AL_write

False

Memory_Read

Normal_Alignment

Next_IP

result AL src ModRM:r/m mv

Direct_Memory_Offset Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_RAX Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

let (segment, ea_offset, next_ip0) := Direct_Memory_Offset?(address_size, context, ip); let is_rip_relative := False; let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Write_RAX(result);

AX/EAX/RAX

result AX/EAX/RAX src ModRM:r/m mv

Direct_Memory_Offset Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_RAX Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

AX/EAX/RAX

result AX/EAX/RAX src ModRM:r/m mv

Std::Boolean::Not Direct_Memory_Offset Handle_RIP_Relative_Address Logical_Mem_Write Report_Invalid_Opcode Instr_MOV AL

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let (segment, ea_offset, next_ip0) := Direct_Memory_Offset?(address_size, context, ip); let is_rip_relative := False; let src := AL; let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); if not (not context.rex2_prefix_present) then Report_Invalid_Opcode!(); endif; LockPrefix #UD Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

result ModRM:r/m mv src AL

Std::Boolean::Not Direct_Memory_Offset Handle_RIP_Relative_Address Logical_Mem_Write Report_Invalid_Opcode Instr_MOV AL

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

result ModRM:r/m mv src AL

Std::Boolean::Not Std::Integer::Le Direct_Memory_Offset Handle_RIP_Relative_Address Logical_Mem_Write Report_Invalid_Opcode Instr_MOV RAX

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let (segment, ea_offset, next_ip0) := Direct_Memory_Offset?(address_size, context, ip); let is_rip_relative := False; let src := RAX[0 +: operand_size]; let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); if not (not context.rex2_prefix_present) then Report_Invalid_Opcode!(); endif; LockPrefix #UD Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

AX/EAX/RAX

result ModRM:r/m mv src AX/EAX/RAX

Std::Boolean::Not Std::Integer::Le Direct_Memory_Offset Handle_RIP_Relative_Address Logical_Mem_Write Report_Invalid_Opcode Instr_MOV RAX

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

AX/EAX/RAX

result ModRM:r/m mv src AX/EAX/RAX

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

result ModRM:r/m mv src ModRM:reg rv

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

result ModRM:r/m mv src ModRM:reg rv

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

result ModRM:reg rv src ModRM:r/m mv

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

result ModRM:reg rv src ModRM:r/m mv

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

result ModRM:r/m mv src ModRM:reg r8

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

result ModRM:r/m mv src ModRM:reg r8

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

result ModRM:reg r8 src ModRM:r/m mv

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

result ModRM:reg r8 src ModRM:r/m mv

Std::Integer::Add Std::Bits::Append Read_Segment Report_Invalid_Opcode Write_GPR Instr_MOV_from_SEG

Next_IP

let src := Read_Segment(context.rex_r3 ++ reg); LockPrefix #UD Next_IP := ip; let result := Instr_MOV_from_SEG(operand_size, src); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result);

Sreg

result ModRM:r/m rv src ModRM:reg Sreg

Std::Integer::Add Std::Bits::Append Read_Segment Report_Invalid_Opcode Write_GPR Instr_MOV_from_SEG

Next_IP

let src := Read_Segment(context.rex_r3 ++ reg); LockPrefix #UD Next_IP := ip; let result := Instr_MOV_from_SEG(operand_size, src); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result);

Sreg

result ModRM:r/m rv src ModRM:reg Sreg

Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_Segment Report_Invalid_Opcode Instr_MOV_from_SEG

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 16; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src := Read_Segment(context.rex_r3 ++ reg); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Next_IP := next_ip0; let result := Instr_MOV_from_SEG(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

Sreg

result ModRM:r/m mv src ModRM:reg Sreg

Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_Segment Report_Invalid_Opcode Instr_MOV_from_SEG

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

Sreg

result ModRM:r/m mv src ModRM:reg Sreg

let result := Zero_Extend(src, operand_size); Std::Bits::Zero_Extend

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_MOV

Next_IP

let operand_size := 8;

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

LockPrefix #UD Next_IP := ip; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

r82

result ModRM:r/m r81 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_MOV

Next_IP

let operand_size := 8;

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

LockPrefix #UD Next_IP := ip; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

r82

result ModRM:r/m r81 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR8 Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);

let src := Read_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

mv1

r82

result ModRM:r/m mv1 src ModRM:reg r82

Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_GPR Instr_MOV

Next_IP

let src := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); LockPrefix #UD Next_IP := ip; let result := Instr_MOV(operand_size, src); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result);

rv1

rv2

result ModRM:r/m rv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_GPR Instr_MOV

Next_IP

rv1

rv2

result ModRM:r/m rv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let src := Read_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, operand_size); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Logical_Mem_Write?(segment, effective_address, result);

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Write Read_GPR Report_Invalid_Opcode Instr_MOV

False

Normal_Alignment

Memory_Type_Unknown

Next_IP

mv1

rv2

result ModRM:r/m mv1 src ModRM:reg rv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_MOV

Next_IP

let operand_size := 8;

let src := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

LockPrefix #UD Next_IP := ip; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

r82

result ModRM:reg r81 src ModRM:r/m r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Write_GPR8 Instr_MOV

Next_IP

let operand_size := 8;

let src := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

LockPrefix #UD Next_IP := ip; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

r82

result ModRM:reg r81 src ModRM:r/m r82

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV(operand_size, src);

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR8 Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

Write_GPR8(context.rex_r4 ++ context.rex_r3 ++ reg, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present), result);

r81

mv2

result ModRM:reg r81 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_GPR Instr_MOV

Next_IP

let src := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, operand_size); LockPrefix #UD Next_IP := ip; let result := Instr_MOV(operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

rv1

rv2

result ModRM:reg rv1 src ModRM:r/m rv2

Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_GPR Instr_MOV

Next_IP

rv1

rv2

result ModRM:reg rv1 src ModRM:r/m rv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV(operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOV

False

Memory_Read

Normal_Alignment

Next_IP

rv1

mv2

result ModRM:reg rv1 src ModRM:r/m mv2

Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_Segment Instr_MOV_to_SEG

Next_IP

let operand_size := 16; let src := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, 16); LockPrefix #UD Next_IP := ip; let result := Instr_MOV_to_SEG(operand_size, src); Write_Segment?(context.rex_r3 ++ reg, result);

Sreg

r16

result ModRM:reg Sreg src ModRM:r/m r16

Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_Segment Instr_MOV_to_SEG

Next_IP

Sreg

r16

result ModRM:reg Sreg src ModRM:r/m r16

Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_Segment Instr_MOV_to_SEG

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 16; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV_to_SEG(operand_size, src); Write_Segment?(context.rex_r3 ++ reg, result);

Sreg

result ModRM:reg Sreg src ModRM:r/m mv

Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_Segment Instr_MOV_to_SEG

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 16; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src := Logical_Mem_Read?(segment, effective_address, operand_size); Next_IP := next_ip0; let result := Instr_MOV_to_SEG(operand_size, src); Write_Segment?(context.rex_r3 ++ reg, result);

Sreg

result ModRM:reg Sreg src ModRM:r/m mv

let result := src[0 +: 16]; Std::Integer::Le

Std::Boolean::Strict_And Std::Integer::Add Std::Integer::Eq Std::Integer::Ne Std::Integer::Power2 Std::Integer::Subtract Std::Bits::Append Std::Bits::Unsigned Std::Bits::Eq Std::Bits::Zero In_64Bit_Mode Read_CR Report_General_Protection_Exception Report_Invalid_Opcode VM_Exec_Controls1 VM_Exit Write_GPR Instr_MOV_from_CR

CPL

VMX_Operation_Mode

VMX_Non_Root

Next_IP

VMX_EXIT_CR_ACCESS

let result_size := 32; let cr_index := Unsigned(context.rex_r3 ++ reg[2:0]); let src := Read_CR?(context.rex_r4 ++ context.rex_r3 ++ reg); LockPrefix #UD Mode64 #UD CPL_Not0 #GP VMX_EVAL(cr_index == 3 and VM_Exec_Controls1().CR3_Store_Exiting == 0b1) VMEXIT(VMX_EXIT_CR_ACCESS) VMX_EVAL(cr_index == 8 and VM_Exec_Controls1().CR8_Store_Exiting == 0b1) VMEXIT(VMX_EXIT_CR_ACCESS) Next_IP := ip; let result := Instr_MOV_from_CR(result_size, src, cr_index); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result);

r32

CR0-8

result ModRM:r/m r32 src ModRM:reg CR0-8 cr_index Unsigned(context.rex_r3 ++ reg[2:0])

Std::Boolean::Strict_And Std::Integer::Add Std::Integer::Eq Std::Integer::Ne Std::Integer::Power2 Std::Integer::Subtract Std::Bits::Append Std::Bits::Unsigned Std::Bits::Eq Std::Bits::Zero Read_CR Report_General_Protection_Exception Report_Invalid_Opcode VM_Exec_Controls1 VM_Exit Write_GPR Instr_MOV_from_CR

CPL

VMX_Operation_Mode

VMX_Non_Root

Next_IP

VMX_EXIT_CR_ACCESS

let result_size := 64; let cr_index := Unsigned(context.rex_r3 ++ reg[2:0]); let src := Read_CR?(context.rex_r4 ++ context.rex_r3 ++ reg); LockPrefix #UD CPL_Not0 #GP VMX_EVAL(cr_index == 3 and VM_Exec_Controls1().CR3_Store_Exiting == 0b1) VMEXIT(VMX_EXIT_CR_ACCESS) VMX_EVAL(cr_index == 8 and VM_Exec_Controls1().CR8_Store_Exiting == 0b1) VMEXIT(VMX_EXIT_CR_ACCESS) Next_IP := ip; let result := Instr_MOV_from_CR(result_size, src, cr_index); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result);

r64

CR0-8

result ModRM:r/m r64 src ModRM:reg CR0-8 cr_index Unsigned(context.rex_r3 ++ reg[2:0])

Serialize_Instructions(); var result := src[0 +: result_size]; if VMX_Operation_Mode == VMX_Non_Root then if cr_index == 0 then let cr0_guest_host_mask := CR0_Guest_Host_Mask[Current_VMCS_Pointer]; let cr0_read_shadow := CR0_Read_Shadow[Current_VMCS_Pointer]; result := (cr0_read_shadow[0 +: result_size] and cr0_guest_host_mask[0 +: result_size]) or (result[0 +: result_size] and not cr0_guest_host_mask[0 +: result_size]); elsif cr_index == 4 then let cr4_guest_host_mask := CR4_Guest_Host_Mask[Current_VMCS_Pointer]; let cr4_read_shadow := CR4_Read_Shadow[Current_VMCS_Pointer]; result := (cr4_read_shadow[0 +: result_size] and cr4_guest_host_mask[0 +: result_size]) or (result[0 +: result_size] and not cr4_guest_host_mask[0 +: result_size]); elsif cr_index == 8 then if VMX_Operation_Mode == VMX_Non_Root then if VM_Exec_Controls1().Use_TPR_Shadow == 0b1 then Unimplemented_Feature("APIC VTPR"); // MOV from CR8. The instruction loads bits 3:0 of its destination operand // with bits 7:4 of VTPR (see Section 32.1.1). // Bits 63:4 of the destination operand are cleared. // result := Zero(60) ++ VTPR[7:4]; endif; endif; endif; endif; Std::Integer::Eq Std::Integer::Le Std::Bits::And Std::Bits::Eq Std::Bits::Not Std::Bits::Or Serialize_Instructions Unimplemented_Feature VM_Exec_Controls1 CR0_Guest_Host_Mask CR0_Read_Shadow CR4_Guest_Host_Mask CR4_Read_Shadow

True

False

Current_VMCS_Pointer

VMX_Operation_Mode

VMX_Non_Root

Std::Boolean::Strict_And Std::Integer::Add Std::Integer::Gt Std::Integer::Ne Std::Integer::Power2 Std::Integer::Subtract Std::Bits::Append Std::Bits::Unsigned Std::Bits::Eq Std::Bits::Zero Current_Mode In_64Bit_Mode Read_DR Report_General_Protection_Exception Report_Invalid_Opcode VM_Exec_Controls1 VM_Exit Write_GPR Instr_MOV_from_DR

Real_Address_Mode

CPL

Virtual_8086_Mode

CR4

VMX_Operation_Mode

VMX_Non_Root

Next_IP

VMX_EXIT_DR_ACCESS

let result_size := 32; let dr_index := Unsigned(context.rex_r3 ++ reg[2:0]); let src := Read_DR?(context.rex_r4 ++ context.rex_r3 ++ reg); LockPrefix #UD Mode64 #UD ModeV86 #GP EVAL(dr_index > 7) #UD EVAL(CR4.DE == 0b1 and dr_index in {4, 5}) #UD VMX_EXEC_1(MOV_DR_Exiting == 0b1) VMEXIT(VMX_EXIT_DR_ACCESS) EVAL(CPL != 0 and Current_Mode() != Real_Address_Mode) #GP Next_IP := ip; let result := Instr_MOV_from_DR?(result_size, src, dr_index); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result);

r32

DR0-7

result ModRM:r/m r32 src ModRM:reg DR0-7 dr_index Unsigned(context.rex_r3 ++ reg[2:0])

Std::Boolean::Strict_And Std::Integer::Add Std::Integer::Gt Std::Integer::Ne Std::Integer::Power2 Std::Integer::Subtract Std::Bits::Append Std::Bits::Unsigned Std::Bits::Eq Std::Bits::Zero Current_Mode Read_DR Report_General_Protection_Exception Report_Invalid_Opcode VM_Exec_Controls1 VM_Exit Write_GPR Instr_MOV_from_DR

Real_Address_Mode

CPL

Virtual_8086_Mode

CR4

VMX_Operation_Mode

VMX_Non_Root

Next_IP

VMX_EXIT_DR_ACCESS

let result_size := 64; let dr_index := Unsigned(context.rex_r3 ++ reg[2:0]); let src := Read_DR?(context.rex_r4 ++ context.rex_r3 ++ reg); LockPrefix #UD ModeV86 #GP EVAL(dr_index > 7) #UD EVAL(CR4.DE == 0b1 and dr_index in {4, 5}) #UD VMX_EXEC_1(MOV_DR_Exiting == 0b1) VMEXIT(VMX_EXIT_DR_ACCESS) EVAL(CPL != 0 and Current_Mode() != Real_Address_Mode) #GP Next_IP := ip; let result := Instr_MOV_from_DR?(result_size, src, dr_index); Write_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, result);

r64

DR0-7

result ModRM:r/m r64 src ModRM:reg DR0-7 dr_index Unsigned(context.rex_r3 ++ reg[2:0])

if DR7.GD == 0b1 then DR6.BD := 0b1; (_, DR6.B) := Get_Instruction_Breakpoint_Match(); DR6.B := DR6.B or Debug_Breakpoints_Matched; Clear_Debug_Traps(); DR7.GD := 0b0; Report_Debug_Exception!(); endif; let result := src[0 +: result_size]; Std::Integer::Le Std::Bits::Eq Std::Bits::Or Clear_Debug_Traps Get_Instruction_Breakpoint_Match Report_Debug_Exception

Debug_Breakpoints_Matched

DR6

DR7

Std::Integer::Add Std::Integer::Ne Std::Integer::Power2 Std::Integer::Subtract Std::Bits::Append Std::Bits::Unsigned Std::Bits::Zero In_64Bit_Mode Read_GPR Report_General_Protection_Exception Report_Invalid_Opcode Write_CR Instr_MOV_to_CR

CPL

Next_IP

let src_size := 32; let cr_index := Unsigned(context.rex_r3 ++ reg[2:0]); let src := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, 32); LockPrefix #UD Mode64 #UD CPL_Not0 #GP Next_IP := ip; let result := Instr_MOV_to_CR?(src_size, src, cr_index); Write_CR?(context.rex_r4 ++ context.rex_r3 ++ reg, result);

CR0-8

r32

result ModRM:reg CR0-8 src ModRM:r/m r32 cr_index Unsigned(context.rex_r3 ++ reg[2:0])

Std::Integer::Add Std::Integer::Ne Std::Integer::Power2 Std::Integer::Subtract Std::Bits::Append Std::Bits::Unsigned Std::Bits::Zero Read_GPR Report_General_Protection_Exception Report_Invalid_Opcode Write_CR Instr_MOV_to_CR

CPL

Next_IP

let src_size := 64; let cr_index := Unsigned(context.rex_r3 ++ reg[2:0]); let src := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, 64); LockPrefix #UD CPL_Not0 #GP Next_IP := ip; let result := Instr_MOV_to_CR?(src_size, src, cr_index); Write_CR?(context.rex_r4 ++ context.rex_r3 ++ reg, result);

CR0-8

r64

result ModRM:reg CR0-8 src ModRM:r/m r64 cr_index Unsigned(context.rex_r3 ++ reg[2:0])

var result := Zero_Extend(src, 64); case cr_index of when 0 => Serialize_Instructions(); var new_cr0 : CR0_Type := result; if VMX_Operation_Mode != Outside_VMX_Operation then if VMX_Operation_Mode == VMX_Non_Root then let cr0_guest_host_mask := CR0_Guest_Host_Mask[Current_VMCS_Pointer]; let cr0_read_shadow := CR0_Read_Shadow[Current_VMCS_Pointer]; if not Is_Zero(cr0_guest_host_mask and (new_cr0 xor cr0_read_shadow)) then VM_Exit!(VMX_EXIT_CR_ACCESS); endif; new_cr0 := (CR0 and cr0_guest_host_mask) or (new_cr0 and not cr0_guest_host_mask); endif; VMX::Check_CR0_Fixed_Bits?(new_cr0); endif; if not Is_Zero(new_cr0[63:32]) then Report_General_Protection_Exception!(Zero(32)); endif; // General Protection fault is reported if an attempt is made to // write invalid bit combinations in CR0 if new_cr0.PG == 0b1 and new_cr0.PE == 0b0 then Report_General_Protection_Exception!(Zero(32)); endif; if new_cr0.CD == 0b0 and new_cr0.NW == 0b1 then Report_General_Protection_Exception!(Zero(32)); endif; if CR4.CET == 0b1 and CR0.WP == 0b1 and new_cr0.WP == 0b0 then Report_General_Protection_Exception!(Zero(32)); endif; if In_64Bit_Mode() and new_cr0.PG == 0b0 then Report_General_Protection_Exception!(Zero(32)); endif; if Current_Mode() == IA32e_Mode and not In_64Bit_Mode() and CR4.PCIDE == 0b1 and new_cr0.PG == 0b0 then Report_General_Protection_Exception!(Zero(32)); endif; // IA-32e mode is enabled and an attempt is made to enable paging prior to enabling // physical-address extensions (PAE) if IA32_EFER.LME == 0b1 and CR4.PAE == 0b0 and CR0.PG == 0b0 and new_cr0.PG == 0b1 then Report_General_Protection_Exception!(Zero(32)); endif; // If the current CS has the L-bit set on an attempt to activate IA-32e mode if CS.descriptor.L == 0b1 and IA32_EFER.LME == 0b1 and CR0.PG == 0b0 and new_cr0.PG == 0b1 then Report_General_Protection_Exception!(Zero(32)); endif; // The TR contains a 16-bit TSS on an attempt to activate IA-32e mode if IA32_EFER.LME == 0b1 and CR0.PG == 0b0 and new_cr0.PG == 0b1 and Is_16Bit_Task(TR) then Report_General_Protection_Exception!(Zero(32)); endif; if CR4.CET == 0b1 and CR0.WP == 0b1 and new_cr0.WP == 0b0 then Report_General_Protection_Exception!(Zero(32)); endif; // todo: reset monitor if paging mode changes // todo: reload PDPTR cache under certain conditions // CR0.ET remains set after any load of CR0 // attempts to clear this bit have no impact new_cr0.ET := 0b1; IA32_EFER.LMA := Bit(new_cr0.PG == 0b1 and IA32_EFER.LME == 0b1 and CR4.PAE == 0b1); // attempts to set reserved bits in CR0 are ignored new_cr0.RESERVED := Zero(53); result := new_cr0; when 1 => Serialize_Instructions(); when 2 => Serialize_Instructions(); when 3 => Serialize_Instructions(); if VMX_Operation_Mode == VMX_Non_Root then VMX::Check_CR3_Target?(result); endif; // todo: load of CR3 affect PDPTR cache if CR4.PCIDE == 0b1 then // If CR4.PCIDE := 1, Bit 63 of the source operand to MOV to CR3 // determines whether the instruction invalidates entries in the TLBs // and the paging-structure caches. The instruction does not modify // bit 63 of CR3, which is reserved and always 0 result[63] := 0b0; endif; if not Is_CR3_Value_Valid(result) then Report_General_Protection_Exception!(Zero(32)); endif; when 4 => Serialize_Instructions(); var new_cr4 : CR4_Type := result; if VMX_Operation_Mode != Outside_VMX_Operation then if VMX_Operation_Mode == VMX_Non_Root then let cr4_guest_host_mask := CR4_Guest_Host_Mask[Current_VMCS_Pointer]; let cr4_read_shadow := CR4_Read_Shadow[Current_VMCS_Pointer]; if not Is_Zero(cr4_guest_host_mask and (new_cr4 xor cr4_read_shadow)) then VM_Exit!(VMX_EXIT_CR_ACCESS); endif; new_cr4 := (CR4 and cr4_guest_host_mask) or (new_cr4 and not cr4_guest_host_mask); endif; VMX::Check_CR4_Fixed_Bits?(new_cr4); endif; if not Is_Zero(new_cr4.RESERVED) then Report_General_Protection_Exception!(Zero(32)); endif; if not CPUID_PAE and new_cr4.PAE == 0b1 then Report_General_Protection_Exception!(Zero(32)); endif; if IA32_EFER.LMA == 0b1 then if CR4.PAE == 0b1 and new_cr4.PAE == 0b0 then Report_General_Protection_Exception!(Zero(32)); endif; if CR4.LA57 != new_cr4.LA57 then Report_General_Protection_Exception!(Zero(32)); endif; if CR4.PCIDE == 0b0 and new_cr4.PCIDE == 0b1 and not Is_Zero(CR3[11:0]) then Report_General_Protection_Exception!(Zero(32)); endif; else if new_cr4.PCIDE == 0b1 then Report_General_Protection_Exception!(Zero(32)); endif; endif; if not Is_CR4_Value_Valid(new_cr4) then Report_General_Protection_Exception!(Zero(32)); endif; IA32_EFER.LMA := Bit(CR0.PG == 0b1 and IA32_EFER.LME == 0b1 and new_cr4.PAE == 0b1); // Attempts to enable FRED when LMA=0 are ignored if IA32_EFER.LMA == 0b0 and new_cr4.FRED == 0b1 then new_cr4.FRED := 0b0; endif; result := new_cr4; when 8 => if VMX_Operation_Mode == VMX_Non_Root then if VM_Exec_Controls1().CR8_Load_Exiting == 0b1 then VM_Exit!(VMX_EXIT_CR_ACCESS); endif; if VM_Exec_Controls1().Use_TPR_Shadow == 0b1 then Unimplemented_Feature("APIC TPR virtualization"); // VTPR[7:4] := result[3:0]; // perform TPR virtualization endif; endif; // MOV CR* instructions, except for MOV CR8, are serializing instructions. // MOV CR8 is not architecturally defined as a serializing instruction. if not Is_Zero(result[63:4]) then Report_General_Protection_Exception!(Zero(32)); endif; otherwise => Report_Invalid_Opcode!(); endcase; Std::Boolean::Not Std::Boolean::Strict_And Std::Integer::Add Std::Bits::And Std::Bits::Eq Std::Bits::Is_Zero Std::Bits::Ne Std::Bits::Not Std::Bits::Or Std::Bits::Xor Std::Bits::Zero_Extend Std::Bits::Zero Bit Current_Mode In_64Bit_Mode Is_16Bit_Task Is_CR3_Value_Valid Is_CR4_Value_Valid Report_General_Protection_Exception Report_Invalid_Opcode Serialize_Instructions Unimplemented_Feature VM_Exec_Controls1 VMX::Check_CR0_Fixed_Bits VMX::Check_CR3_Target VMX::Check_CR4_Fixed_Bits VM_Exit CR0_Guest_Host_Mask CR0_Read_Shadow CR4_Guest_Host_Mask CR4_Read_Shadow

True

False

CR4

CR0

IA32_EFER

IA32e_Mode

Current_VMCS_Pointer

VMX_Operation_Mode

VMX_Non_Root

CPUID_PAE

CR3

Outside_VMX_Operation

VMX_EXIT_CR_ACCESS

Std::Boolean::Strict_And Std::Integer::Add Std::Integer::Gt Std::Integer::Ne Std::Integer::Power2 Std::Integer::Subtract Std::Bits::Append Std::Bits::Unsigned Std::Bits::Eq Std::Bits::Zero Current_Mode In_64Bit_Mode Read_GPR Report_General_Protection_Exception Report_Invalid_Opcode VM_Exec_Controls1 VM_Exit Write_DR Instr_MOV_to_DR

Real_Address_Mode

CPL

Virtual_8086_Mode

CR4

VMX_Operation_Mode

VMX_Non_Root

Next_IP

VMX_EXIT_DR_ACCESS

let src_size := 32; let dr_index := Unsigned(context.rex_r3 ++ reg[2:0]); let src := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, 32); LockPrefix #UD Mode64 #UD ModeV86 #GP EVAL(dr_index > 7) #UD EVAL(CR4.DE == 0b1 and dr_index in {4, 5}) #UD VMX_EXEC_1(MOV_DR_Exiting == 0b1) VMEXIT(VMX_EXIT_DR_ACCESS) EVAL(CPL != 0 and Current_Mode() != Real_Address_Mode) #GP Next_IP := ip; let result := Instr_MOV_to_DR?(src_size, src, dr_index); Write_DR?(context.rex_r4 ++ context.rex_r3 ++ reg, result);

DR0-7

r32

result ModRM:reg DR0-7 src ModRM:r/m r32 dr_index Unsigned(context.rex_r3 ++ reg[2:0])

Std::Boolean::Strict_And Std::Integer::Add Std::Integer::Gt Std::Integer::Ne Std::Integer::Power2 Std::Integer::Subtract Std::Bits::Append Std::Bits::Unsigned Std::Bits::Eq Std::Bits::Zero Current_Mode Read_GPR Report_General_Protection_Exception Report_Invalid_Opcode VM_Exec_Controls1 VM_Exit Write_DR Instr_MOV_to_DR

Real_Address_Mode

CPL

Virtual_8086_Mode

CR4

VMX_Operation_Mode

VMX_Non_Root

Next_IP

VMX_EXIT_DR_ACCESS

let src_size := 64; let dr_index := Unsigned(context.rex_r3 ++ reg[2:0]); let src := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, 64); LockPrefix #UD ModeV86 #GP EVAL(dr_index > 7) #UD EVAL(CR4.DE == 0b1 and dr_index in {4, 5}) #UD VMX_EXEC_1(MOV_DR_Exiting == 0b1) VMEXIT(VMX_EXIT_DR_ACCESS) EVAL(CPL != 0 and Current_Mode() != Real_Address_Mode) #GP Next_IP := ip; let result := Instr_MOV_to_DR?(src_size, src, dr_index); Write_DR?(context.rex_r4 ++ context.rex_r3 ++ reg, result);

DR0-7

r64

result ModRM:reg DR0-7 src ModRM:r/m r64 dr_index Unsigned(context.rex_r3 ++ reg[2:0])

if DR7.GD == 0b1 then DR6.BD := 0b1; (_, DR6.B) := Get_Instruction_Breakpoint_Match(); DR6.B := DR6.B or Debug_Breakpoints_Matched; DR7.GD := 0b0; Report_Debug_Exception!(); endif; // upper 32 bits of DR4-7 are reserved if src_size == 64 and dr_index in {4..7} then if dr_index == 7 and CPUID_TRIGGER_DR_MATCH then if not Is_Zero(src[63:36]) then Report_General_Protection_Exception!(Zero(32)); endif; else if not Is_Zero(src[63:32]) then Report_General_Protection_Exception!(Zero(32)); endif; endif; endif; var result := Zero_Extend(src, 64); Std::Boolean::Not Std::Boolean::Strict_And Std::Integer::Eq Std::Integer::Lt Std::Bits::Eq Std::Bits::Is_Zero Std::Bits::Or Std::Bits::Zero_Extend Std::Bits::Zero Get_Instruction_Breakpoint_Match Report_Debug_Exception Report_General_Protection_Exception

Debug_Breakpoints_Matched

DR6

DR7

CPUID_TRIGGER_DR_MATCH

registers/debug With a REX prefix in 64-bit mode, attempts to access AH, BH, CH, or DH will instead access SPL, DIL, BPL, or SIL, respectively. Operand is sign-extended to operand_size bits.