Copyright (C) Intel Corporation. All Rights Reserved. # Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. All product plans and roadmaps are subject to change without notice. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Code names are used by Intel to identify products, technologies, or services that are in development and not publicly available. These are not “commercial” names and not intended to function as trademarks. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document, with the sole exception that a) you may publish an unmodified copy and b) code, identified as Sample Code in this document is licensed subject to the Zero-Clause BSD open source license (0BSD), [https://opensource.org/licenses/0BSD](https://opensource.org/licenses/0BSD). You may create software implementations based on this document and in compliance with the foregoing that are intended to execute on the Intel product(s) referenced in this document. No rights are granted to create modifications or derivatives of this document. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. If you give Intel any comments or suggestions related to this document or the information contained in it, Intel can use them in any way and disclose them to anyone, without payment or other obligations to you. You represent and warrant that you own, or have sufficient rights from the owner of, any such comments or suggestions, and the intellectual property rights in them, to grant the above permission. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. The code in this file is not 'Sample Code'.

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

let src_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD let src := Logical_Mem_Read?(segment, effective_address, src_size); Next_IP := next_ip0; let result := Instr_MOVZX(src_size, operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

result ModRM:reg rv src ModRM:r/m m8

let result := Zero_Extend(src, operand_size); Std::Bits::Zero_Extend

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 16; let src_size := 16; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD VEX_W_1 #UD let src := Logical_Mem_Read?(segment, effective_address, src_size); Next_IP := next_ip0; let result := Instr_MOVZX(src_size, operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

r16

m16

result ModRM:reg r16 src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 32; let src_size := 16; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD VEX_W_1 #UD OSZ_Prefix #UD let src := Logical_Mem_Read?(segment, effective_address, src_size); Next_IP := next_ip0; let result := Instr_MOVZX(src_size, operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

r32

m16

result ModRM:reg r32 src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

r32

m16

result ModRM:reg r32 src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

r32

m16

result ModRM:reg r32 src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

let operand_size := 64; let src_size := 16; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD VEX_W_0 #UD let src := Logical_Mem_Read?(segment, effective_address, src_size); Next_IP := next_ip0; let result := Instr_MOVZX(src_size, operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

r64

m16

result ModRM:reg r64 src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

r64

m16

result ModRM:reg r64 src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

r64

m16

result ModRM:reg r64 src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Read_GPR Report_Invalid_Opcode Write_GPR Instr_MOVZX

Next_IP

let src_size := 16; let src := Read_GPR(context.rex_b4 ++ context.rex_b3 ++ rm, 16); LockPrefix #UD Next_IP := ip; let result := Instr_MOVZX(src_size, operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

r16

result ModRM:reg rv src ModRM:r/m r16

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

let src_size := 16; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD let src := Logical_Mem_Read?(segment, effective_address, src_size); Next_IP := next_ip0; let result := Instr_MOVZX(src_size, operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

m16

result ModRM:reg rv src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

r32

m16

result ModRM:reg r32 src ModRM:r/m m16

Std::Integer::Add Std::Bits::Append Std::Bits::Eq Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

r64

m16

result ModRM:reg r64 src ModRM:r/m m16

Std::Boolean::Strict_Or Std::Integer::Add Std::Bits::Append Read_GPR8 Report_Invalid_Opcode Write_GPR Instr_MOVZX

Next_IP

let src_size := 8;

let src := Read_GPR8(context.rex_b4 ++ context.rex_b3 ++ rm, (context.rex_prefix_present or context.rex2_prefix_present or context.vex_prefix_present or context.evex_prefix_present));

LockPrefix #UD Next_IP := ip; let result := Instr_MOVZX(src_size, operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

result ModRM:reg rv src ModRM:r/m r8

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address In_64Bit_Mode Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

let src_size := 8; let disp8n := 1; let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip); let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0); LockPrefix #UD Mode64 #UD let src := Logical_Mem_Read?(segment, effective_address, src_size); Next_IP := next_ip0; let result := Instr_MOVZX(src_size, operand_size, src); Write_GPR(context.rex_r4 ++ context.rex_r3 ++ reg, result);

result ModRM:reg rv src ModRM:r/m m8

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

result ModRM:reg rv src ModRM:r/m m8

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

result ModRM:reg rv src ModRM:r/m m8

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

result ModRM:reg rv src ModRM:r/m m8

Std::Integer::Add Std::Bits::Append Effective_Address Handle_RIP_Relative_Address Logical_Mem_Read Report_Invalid_Opcode Write_GPR Instr_MOVZX

False

Memory_Read

Normal_Alignment

Next_IP

result ModRM:reg rv src ModRM:r/m m8

scalar integer/data_transfer With a REX prefix in 64-bit mode, attempts to access AH, BH, CH, or DH will instead access SPL, DIL, BPL, or SIL, respectively.