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The code in this file is not 'Sample Code'.
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Integer::Ne
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Effective_Address
Handle_RIP_Relative_Address
Logical_Mem_Read
Mem_Fetch
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_XMM
Instr_SHUF_lanes
False
CR4
CR0
Memory_Read
Explicitly_Aligned
Next_IP
let register_size := 128;
let element_size := 32;
let disp8n := 1;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
LockPrefix
#UD
REP_Not0
#UD
CR4_OSFXSR_0
#UD
CR0_EM_1
#UD
CR0_TS_1
#NM
let src1 := Logical_Mem_Read?(segment, effective_address, register_size, alignment_type=>Explicitly_Aligned);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes(element_size, register_size, src1, imm8);
Write_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, result, (context.vex_prefix_present or context.evex_prefix_present));
xmm1
m1282
imm8
SSE2
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Integer::Ne
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Calculate_RM
Mem_Fetch
Read_XMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_XMM
Instr_SHUF_lanes
CR4
CR0
Next_IP
let register_size := 128;
let element_size := 32;
let src1 := Read_XMM(Calculate_RM(mod, rm, context), register_size);
let imm8 := Mem_Fetch?(ip, 8);
LockPrefix
#UD
REP_Not0
#UD
CR4_OSFXSR_0
#UD
CR0_EM_1
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes(element_size, register_size, src1, imm8);
Write_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, result, (context.vex_prefix_present or context.evex_prefix_present));
xmm1
xmm2
imm8
SSE2
result
ModRM:reg
src1
ModRM:r/m
let lanes := register_size / 128;
let elements := 128 / element_size;
let index_size := Log2(elements);
var result := Zero(register_size);
for lane := 0 to lanes-1 do
let s1 := src1[lane *: 128];
var lane_result := Zero(128);
for i := 0 to elements-1 do
let index := Integer::Align_Down(i, elements) + Unsigned(imm8[i % elements *: index_size]);
let r := s1[index *: element_size];
lane_result[i *: element_size] := r;
endfor;
result[lane *: 128] := lane_result;
endfor;
Std::Integer::Add
Std::Integer::Align_Down
Std::Integer::Le
Std::Integer::Lt
Std::Integer::Multiply
Std::Integer::Positive_Divide
Std::Integer::Positive_Remainder
Std::Integer::Subtract
Std::Bits::Unsigned
Std::Bits::Zero
Std::Integer::Log2
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Current_Mode
Effective_Address
Handle_RIP_Relative_Address
Logical_Mem_Read
Mem_Fetch
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_XMM
Instr_SHUF_lanes
False
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
Memory_Read
Normal_Alignment
XCR0
Next_IP
let register_size := 128;
let element_size := 32;
let disp8n := 1;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
if not ((not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
let src1 := Logical_Mem_Read?(segment, effective_address, register_size);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes(element_size, register_size, src1, imm8);
Write_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, result, (context.vex_prefix_present or context.evex_prefix_present));
xmm1
m1282
imm8
AVX
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Calculate_RM
Current_Mode
Mem_Fetch
Read_XMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_XMM
Instr_SHUF_lanes
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 128;
let element_size := 32;
let src1 := Read_XMM(Calculate_RM(mod, rm, context), register_size);
let imm8 := Mem_Fetch?(ip, 8);
if not ((not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes(element_size, register_size, src1, imm8);
Write_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, result, (context.vex_prefix_present or context.evex_prefix_present));
xmm1
xmm2
imm8
AVX
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Current_Mode
Effective_Address
Handle_RIP_Relative_Address
Logical_Mem_Read
Mem_Fetch
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_YMM
Instr_SHUF_lanes
False
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
Memory_Read
Normal_Alignment
XCR0
Next_IP
let register_size := 256;
let element_size := 32;
let disp8n := 1;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
if not ((not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
let src1 := Logical_Mem_Read?(segment, effective_address, register_size);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes(element_size, register_size, src1, imm8);
Write_YMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
ymm1
m2562
imm8
AVX2
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Calculate_RM
Current_Mode
Mem_Fetch
Read_YMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_YMM
Instr_SHUF_lanes
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 256;
let element_size := 32;
let src1 := Read_YMM(Calculate_RM(mod, rm, context));
let imm8 := Mem_Fetch?(ip, 8);
if not ((not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes(element_size, register_size, src1, imm8);
Write_YMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
ymm1
ymm2
imm8
AVX2
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Integer::Le
Std::Integer::Positive_Divide
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Current_Mode
Effective_Address
Handle_RIP_Relative_Address
Mem_Fetch
Read_Mask
Read_XMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Vector_Mem_Read
Write_XMM
Instr_SHUF_lanes_m
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 128;
let element_size := 32;
let disp8n := if context.evex_b == 0b1 then element_size / 8 else 16;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let old := Read_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, register_size);
let k := Read_Mask(context.evex_aaa);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
if not ((context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
let src1 := Vector_Mem_Read?(register_size, element_size, context.evex_b == 0b1, segment, effective_address);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes_m(element_size, register_size, old, k, src1, imm8, context, mod);
Write_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, result, (context.vex_prefix_present or context.evex_prefix_present));
xmm1
{k1}{z}
m1282
imm8
AVX512FAVX512VL
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Calculate_RM
Current_Mode
Mem_Fetch
Read_Mask
Read_XMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_XMM
Instr_SHUF_lanes_m
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 128;
let element_size := 32;
let old := Read_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, register_size);
let k := Read_Mask(context.evex_aaa);
let src1 := Read_XMM(Calculate_RM(mod, rm, context), register_size);
let imm8 := Mem_Fetch?(ip, 8);
if not ((context.evex_b == 0b0) and (context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes_m(element_size, register_size, old, k, src1, imm8, context, mod);
Write_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, result, (context.vex_prefix_present or context.evex_prefix_present));
xmm1
{k1}{z}
xmm2
imm8
AVX512FAVX512VL
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Integer::Le
Std::Integer::Positive_Divide
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Current_Mode
Effective_Address
Handle_RIP_Relative_Address
Mem_Fetch
Read_Mask
Report_Invalid_Opcode
Report_Not_Available_Exception
Vector_Mem_Read
Write_XMM
Instr_SHUF_lanes_z
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 128;
let element_size := 32;
let disp8n := if context.evex_b == 0b1 then element_size / 8 else 16;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let k := Read_Mask(context.evex_aaa);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
if not ((context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
let src1 := Vector_Mem_Read?(register_size, element_size, context.evex_b == 0b1, segment, effective_address);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes_z(element_size, register_size, k, src1, imm8, context, mod);
Write_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, result, (context.vex_prefix_present or context.evex_prefix_present));
xmm1
{k1}{z}
m1282
imm8
AVX512FAVX512VL
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Calculate_RM
Current_Mode
Mem_Fetch
Read_Mask
Read_XMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_XMM
Instr_SHUF_lanes_z
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 128;
let element_size := 32;
let k := Read_Mask(context.evex_aaa);
let src1 := Read_XMM(Calculate_RM(mod, rm, context), register_size);
let imm8 := Mem_Fetch?(ip, 8);
if not ((context.evex_b == 0b0) and (context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes_z(element_size, register_size, k, src1, imm8, context, mod);
Write_XMM(context.rex_r4 ++ context.rex_r3 ++ reg, result, (context.vex_prefix_present or context.evex_prefix_present));
xmm1
{k1}{z}
xmm2
imm8
AVX512FAVX512VL
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
let lanes := register_size / 128;
let elements := 128 / element_size;
let index_size := Log2(elements);
var result := Zero(register_size);
for lane := 0 to lanes-1 do
let lane_old := old[lane *: 128];
let s1 := src1[lane *: 128];
var lane_result := Zero(128);
for i := 0 to elements-1 do
if k[lane * elements + i] == 0b1 then
let index := Integer::Align_Down(i, elements) + Unsigned(imm8[i % elements *: index_size]);
let r := s1[index *: element_size];
lane_result[i *: element_size] := r;
else
lane_result[i *: element_size] := lane_old[i *: element_size];
endif;
endfor;
result[lane *: 128] := lane_result;
endfor;
Std::Integer::Add
Std::Integer::Align_Down
Std::Integer::Le
Std::Integer::Lt
Std::Integer::Multiply
Std::Integer::Positive_Divide
Std::Integer::Positive_Remainder
Std::Integer::Subtract
Std::Bits::Unsigned
Std::Bits::Eq
Std::Bits::Zero
Std::Integer::Log2
let lanes := register_size / 128;
let elements := 128 / element_size;
let index_size := Log2(elements);
var result := Zero(register_size);
for lane := 0 to lanes-1 do
let s1 := src1[lane *: 128];
var lane_result := Zero(128);
for i := 0 to elements-1 do
if k[lane * elements + i] == 0b1 then
let index := Integer::Align_Down(i, elements) + Unsigned(imm8[i % elements *: index_size]);
let r := s1[index *: element_size];
lane_result[i *: element_size] := r;
else
lane_result[i *: element_size] := Zero(element_size);
endif;
endfor;
result[lane *: 128] := lane_result;
endfor;
Std::Integer::Add
Std::Integer::Align_Down
Std::Integer::Le
Std::Integer::Lt
Std::Integer::Multiply
Std::Integer::Positive_Divide
Std::Integer::Positive_Remainder
Std::Integer::Subtract
Std::Bits::Unsigned
Std::Bits::Eq
Std::Bits::Zero
Std::Integer::Log2
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Integer::Le
Std::Integer::Positive_Divide
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Current_Mode
Effective_Address
Handle_RIP_Relative_Address
Mem_Fetch
Read_Mask
Read_YMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Vector_Mem_Read
Write_YMM
Instr_SHUF_lanes_m
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 256;
let element_size := 32;
let disp8n := if context.evex_b == 0b1 then element_size / 8 else 32;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let old := Read_YMM(context.rex_r4 ++ context.rex_r3 ++ reg);
let k := Read_Mask(context.evex_aaa);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
if not ((context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
let src1 := Vector_Mem_Read?(register_size, element_size, context.evex_b == 0b1, segment, effective_address);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes_m(element_size, register_size, old, k, src1, imm8, context, mod);
Write_YMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
ymm1
{k1}{z}
m2562
imm8
AVX512FAVX512VL
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Calculate_RM
Current_Mode
Mem_Fetch
Read_Mask
Read_YMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_YMM
Instr_SHUF_lanes_m
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 256;
let element_size := 32;
let old := Read_YMM(context.rex_r4 ++ context.rex_r3 ++ reg);
let k := Read_Mask(context.evex_aaa);
let src1 := Read_YMM(Calculate_RM(mod, rm, context));
let imm8 := Mem_Fetch?(ip, 8);
if not ((context.evex_b == 0b0) and (context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes_m(element_size, register_size, old, k, src1, imm8, context, mod);
Write_YMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
ymm1
{k1}{z}
ymm2
imm8
AVX512FAVX512VL
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Integer::Le
Std::Integer::Positive_Divide
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Current_Mode
Effective_Address
Handle_RIP_Relative_Address
Mem_Fetch
Read_Mask
Report_Invalid_Opcode
Report_Not_Available_Exception
Vector_Mem_Read
Write_YMM
Instr_SHUF_lanes_z
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 256;
let element_size := 32;
let disp8n := if context.evex_b == 0b1 then element_size / 8 else 32;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let k := Read_Mask(context.evex_aaa);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
if not ((context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
let src1 := Vector_Mem_Read?(register_size, element_size, context.evex_b == 0b1, segment, effective_address);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes_z(element_size, register_size, k, src1, imm8, context, mod);
Write_YMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
ymm1
{k1}{z}
m2562
imm8
AVX512FAVX512VL
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Calculate_RM
Current_Mode
Mem_Fetch
Read_Mask
Read_YMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_YMM
Instr_SHUF_lanes_z
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 256;
let element_size := 32;
let k := Read_Mask(context.evex_aaa);
let src1 := Read_YMM(Calculate_RM(mod, rm, context));
let imm8 := Mem_Fetch?(ip, 8);
if not ((context.evex_b == 0b0) and (context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes_z(element_size, register_size, k, src1, imm8, context, mod);
Write_YMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
ymm1
{k1}{z}
ymm2
imm8
AVX512FAVX512VL
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Integer::Le
Std::Integer::Positive_Divide
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Current_Mode
Effective_Address
Handle_RIP_Relative_Address
Mem_Fetch
Read_Mask
Read_ZMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Vector_Mem_Read
Write_ZMM
Instr_SHUF_lanes_m
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 512;
let element_size := 32;
let disp8n := if context.evex_b == 0b1 then element_size / 8 else 64;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let old := Read_ZMM(context.rex_r4 ++ context.rex_r3 ++ reg);
let k := Read_Mask(context.evex_aaa);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
if not ((context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
let src1 := Vector_Mem_Read?(register_size, element_size, context.evex_b == 0b1, segment, effective_address);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes_m(element_size, register_size, old, k, src1, imm8, context, mod);
Write_ZMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
zmm1
{k1}{z}
m5122
imm8
AVX512F
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Calculate_RM
Current_Mode
Mem_Fetch
Read_Mask
Read_ZMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_ZMM
Instr_SHUF_lanes_m
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 512;
let element_size := 32;
let old := Read_ZMM(context.rex_r4 ++ context.rex_r3 ++ reg);
let k := Read_Mask(context.evex_aaa);
let src1 := Read_ZMM(Calculate_RM(mod, rm, context));
let imm8 := Mem_Fetch?(ip, 8);
if not ((context.evex_b == 0b0) and (context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes_m(element_size, register_size, old, k, src1, imm8, context, mod);
Write_ZMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
zmm1
{k1}{z}
zmm2
imm8
AVX512F
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Integer::Le
Std::Integer::Positive_Divide
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Current_Mode
Effective_Address
Handle_RIP_Relative_Address
Mem_Fetch
Read_Mask
Report_Invalid_Opcode
Report_Not_Available_Exception
Vector_Mem_Read
Write_ZMM
Instr_SHUF_lanes_z
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 512;
let element_size := 32;
let disp8n := if context.evex_b == 0b1 then element_size / 8 else 64;
let (ea_offset, segment, next_ip0, is_rip_relative) := Effective_Address?(address_size, context, mod, rm, disp8n, ip);
let k := Read_Mask(context.evex_aaa);
let imm8 := Mem_Fetch?(next_ip0, 8);
let effective_address := Handle_RIP_Relative_Address(address_size, is_rip_relative, ea_offset, next_ip0 + 1);
if not ((context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
let src1 := Vector_Mem_Read?(register_size, element_size, context.evex_b == 0b1, segment, effective_address);
Next_IP := next_ip0 + 1;
let result := Instr_SHUF_lanes_z(element_size, register_size, k, src1, imm8, context, mod);
Write_ZMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
zmm1
{k1}{z}
m5122
imm8
AVX512F
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
Std::Boolean::Not
Std::Boolean::Strict_And
Std::Boolean::Strict_Or
Std::Integer::Add
Std::Bits::Add_int
Std::Bits::Append
Std::Bits::Eq
Std::Bits::Not
Calculate_RM
Current_Mode
Mem_Fetch
Read_Mask
Read_ZMM
Report_Invalid_Opcode
Report_Not_Available_Exception
Write_ZMM
Instr_SHUF_lanes_z
Real_Address_Mode
Virtual_8086_Mode
CR4
CR0
XCR0
Next_IP
let register_size := 512;
let element_size := 32;
let k := Read_Mask(context.evex_aaa);
let src1 := Read_ZMM(Calculate_RM(mod, rm, context));
let imm8 := Mem_Fetch?(ip, 8);
if not ((context.evex_b == 0b0) and (context.rex_w == 0b0) and (not context.vvvv[3] == 0b1) and (not context.vvvv[2:0] == 0b111) and (context.evex_v4 == 0b0)) then Report_Invalid_Opcode!(); endif;
LockPrefix
#UD
ModeRealOrVirtual
#UD
VEX_W_1
#UD
CR4_OSXSAVE_0
#UD
XCR0_AVX_0
#UD
CR0_TS_1
#NM
Next_IP := ip + 1;
let result := Instr_SHUF_lanes_z(element_size, register_size, k, src1, imm8, context, mod);
Write_ZMM(context.rex_r4 ++ context.rex_r3 ++ reg, result);
zmm1
{k1}{z}
zmm2
imm8
AVX512F
AVX10.1
result
ModRM:reg
src1
ModRM:r/m
vector/permute
An explicitly-aligned memory access is performed.
If EVEX.b == 0b1, a single element is read from memory and broadcast across the vector.
If EVEX.z == 0b0, the previous value of the result is read into `old` and the masking variant of the operation is used; if EVEX.z == 0b1, the zeroing variant of the operation is used.