(kicad_pcb
  (version 20230121)
  (generator "hermes-agent-jayis1")
  (generator_version "1.0")
  (general
    (thickness 1.6)
    (legacy_teardrops no)
  )
  (paper "A4")
  (title_block
    (title "1553-Phantom PCB")
    (date "2026-08-14")
    (rev "1.0")
    (company "jayis1")
    (comment 1 "Author: jayis1")
    (comment 2 "CERN-OHL-S v2")
  )

  (layers
    (0 "F.Cu" signal)
    (1 "In1.Cu" signal "GND")
    (2 "In2.Cu" signal "PWR")
    (31 "B.Cu" signal)
    (32 "B.Adhes" user "B.Adhesive")
    (33 "F.Adhes" user "F.Adhesive")
    (34 "B.Paste" user)
    (35 "F.Paste" user)
    (36 "B.SilkS" user "B.Silkscreen")
    (37 "F.SilkS" user "F.Silkscreen")
    (38 "B.Mask" user)
    (39 "F.Mask" user)
    (40 "Dwgs.User" user "User.Drawings")
    (41 "Cmts.User" user "User.Comments")
    (42 "Eco1.User" user "Eco1.User")
    (43 "Eco2.User" user "Eco2.User")
    (44 "Edge.Cuts" user)
    (45 "Margin" user)
    (46 "B.CrtYd" user "B.Courtyard")
    (47 "F.CrtYd" user "F.Courtyard")
    (48 "B.Fab" user)
    (49 "F.Fab" user)
  )

  (setup
    (stackup
      (layer "F.Cu" (type "copper") (thickness 0.035))
      (layer "dielectric 1" (type "core") (thickness 0.5))
      (layer "In1.Cu" (type "copper") (thickness 0.035))
      (layer "dielectric 2" (type "prepreg") (thickness 0.5))
      (layer "In2.Cu" (type "copper") (thickness 0.035))
      (layer "dielectric 3" (type "core") (thickness 0.5))
      (layer "B.Cu" (type "copper") (thickness 0.035))
    )
    (pad_to_mask_clearance 0.05)
    (aux_axis_origin 0 0)
    (pcbplotparams
      (layerselection 0x00010a8_ffffffff)
      (plot_on_all_layers_selection 0x0000000_00000000)
      (use_aux_axis_origin no)
    )
  )

  ; ---- Net definitions ----
  (net 0 "")
  (net 1 "GND")
  (net 2 "VBUS")
  (net 3 "+3V3")
  (net 4 "+1V2")
  (net 5 "+BATT")
  (net 10 "1553A_HI")
  (net 11 "1553A_LO")
  (net 12 "1553A_SHLD")
  (net 20 "1553B_HI")
  (net 21 "1553B_LO")
  (net 22 "1553B_SHLD")
  (net 30 "SPI_SCK")
  (net 31 "SPI_MISO")
  (net 32 "SPI_MOSI")
  (net 33 "FPGA_CS")
  (net 34 "FPGA_IRQ")
  (net 35 "FPGA_RST")
  (net 36 "FPGA_CDONE")
  (net 40 "FPGA_TX0_P")
  (net 41 "FPGA_TX0_N")
  (net 42 "FPGA_RX0_P")
  (net 43 "FPGA_RX0_N")
  (net 44 "FPGA_TX1_P")
  (net 45 "FPGA_TX1_N")
  (net 46 "FPGA_RX1_P")
  (net 47 "FPGA_RX1_N")
  (net 48 "TX_GATE")
  (net 50 "USB_DM")
  (net 51 "USB_DP")
  (net 60 "OLED_DC")
  (net 61 "OLED_RST")
  (net 62 "OLED_CS")
  (net 63 "OLED_SCK")
  (net 64 "OLED_MOSI")
  (net 70 "I2C_SCL")
  (net 71 "I2C_SDA")
  (net 80 "USER_BTN")
  (net 81 "PANIC")
  (net 90 "LED_PWR")
  (net 91 "LED_ACTA")
  (net 92 "LED_ACTB")
  (net 93 "LED_ARM")
  (net 94 "LED_INJ")
  (net 100 "OSC_IN")
  (net 101 "OSC_OUT")
  (net 102 "FPGA_CLK")

  ; ---- Board outline (70 x 45 mm) ----
  (gr_line (start 0 0) (end 70 0) (layer "Edge.Cuts") (width 0.1))
  (gr_line (start 70 0) (end 70 45) (layer "Edge.Cuts") (width 0.1))
  (gr_line (start 70 45) (end 0 45) (layer "Edge.Cuts") (width 0.1))
  (gr_line (start 0 45) (end 0 0) (layer "Edge.Cuts") (width 0.1))

  ; ---- Silkscreen text ----
  (gr_text "1553-Phantom\nby jayis1\nCERN-OHL-S v2"
    (at 35 22.5) (layer "F.SilkS")
    (effects (font (size 1.5 1.5) (thickness 0.15)) (justify center)))

  ; ---- Footprints ----
  ; U1: STM32G474CBT6 LQFP-48
  (footprint "Package_QFP:LQFP-48_7x7mm_P0.5mm"
    (layer "F.Cu")
    (at 20 20)
    (attr smd)
    (property "Reference" "U1" (at 0 -5.5) (layer "F.SilkS"))
    (property "Value" "STM32G474CBT6" (at 0 5.5) (layer "F.Fab"))
    (pad "1" smd rect (at -4.25 -2.75) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 3 "+3V3"))
    (pad "5" smd rect (at -4.25 -0.75) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 33 "FPGA_CS"))
    (pad "6" smd rect (at -4.25 -0.25) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 30 "SPI_SCK"))
    (pad "7" smd rect (at -4.25 0.25) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 31 "SPI_MISO"))
    (pad "8" smd rect (at -4.25 0.75) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 32 "SPI_MOSI"))
    (pad "9" smd rect (at -2.75 4.25 90) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 50 "USB_DM"))
    (pad "10" smd rect (at -2.25 4.25 90) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 51 "USB_DP"))
    (pad "11" smd rect (at -1.75 4.25 90) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 80 "USER_BTN"))
    (pad "12" smd rect (at -1.25 4.25 90) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 34 "FPGA_IRQ"))
    (pad "13" smd rect (at -0.75 4.25 90) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 35 "FPGA_RST"))
    (pad "16" smd rect (at 1.75 4.25 90) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 90 "LED_PWR"))
    (pad "17" smd rect (at 4.25 2.75 180) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "24" smd rect (at 4.25 -0.75 180) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 91 "LED_ACTA"))
    (pad "25" smd rect (at 4.25 -1.25 180) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 92 "LED_ACTB"))
    (pad "26" smd rect (at 4.25 -1.75 180) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 93 "LED_ARM"))
    (pad "27" smd rect (at 4.25 -2.25 180) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 94 "LED_INJ"))
    (pad "28" smd rect (at 4.25 -2.75 180) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 48 "TX_GATE"))
    (pad "33" smd rect (at 1.75 -4.25 270) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 70 "I2C_SCL"))
    (pad "34" smd rect (at 1.25 -4.25 270) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 71 "I2C_SDA"))
    (pad "40" smd rect (at -1.75 -4.25 270) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 81 "PANIC"))
    (pad "44" smd rect (at -4.25 -2.25) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 60 "OLED_DC"))
    (pad "45" smd rect (at -4.25 -1.75) (size 1.5 0.3) (layers "F.Cu" "F.Mask")
      (net 61 "OLED_RST"))
  )

  ; U2: iCE40-UP5K-SG48 QFN-48
  (footprint "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm"
    (layer "F.Cu")
    (at 40 20)
    (attr smd)
    (property "Reference" "U2" (at 0 -5.5) (layer "F.SilkS"))
    (property "Value" "iCE40-UP5K-SG48" (at 0 5.5) (layer "F.Fab"))
    (pad "1" smd rect (at -3.25 -2.75) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 4 "+1V2"))
    (pad "2" smd rect (at -3.25 -2.25) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 3 "+3V3"))
    (pad "20" smd rect (at 3.25 -0.25) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 40 "FPGA_TX0_P"))
    (pad "21" smd rect (at 3.25 0.25) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 41 "FPGA_TX0_N"))
    (pad "22" smd rect (at 3.25 0.75) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 42 "FPGA_RX0_P"))
    (pad "23" smd rect (at 3.25 1.25) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 43 "FPGA_RX0_N"))
    (pad "24" smd rect (at 3.25 1.75) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 44 "FPGA_TX1_P"))
    (pad "25" smd rect (at 3.25 2.25) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 45 "FPGA_TX1_N"))
    (pad "26" smd rect (at 3.25 2.75) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 46 "FPGA_RX1_P"))
    (pad "27" smd rect (at 2.75 3.25 90) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 47 "FPGA_RX1_N"))
    (pad "30" smd rect (at 1.25 3.25 90) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 33 "FPGA_CS"))
    (pad "31" smd rect (at 0.75 3.25 90) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 30 "SPI_SCK"))
    (pad "32" smd rect (at 0.25 3.25 90) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 31 "SPI_MISO"))
    (pad "33" smd rect (at -0.25 3.25 90) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 32 "SPI_MOSI"))
    (pad "40" smd rect (at -3.25 0.25) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 102 "FPGA_CLK"))
    (pad "41" smd rect (at -3.25 -0.25) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 35 "FPGA_RST"))
    (pad "42" smd rect (at -3.25 -0.75) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 36 "FPGA_CDONE"))
    (pad "43" smd rect (at -3.25 -1.25) (size 0.6 0.3) (layers "F.Cu" "F.Mask")
      (net 34 "FPGA_IRQ"))
    (pad "49" smd rect (at 0 0) (size 5.3 5.3) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
  )

  ; U3: HI-1573PSF PLCC-44 (channel A)
  (footprint "Package_LCC:PLCC-44_THT-Socket"
    (layer "F.Cu")
    (at 30 32)
    (attr through_hole)
    (property "Reference" "U3" (at 0 -7) (layer "F.SilkS"))
    (property "Value" "HI-1573PSF" (at 0 7) (layer "F.Fab"))
    (pad "1" thru_hole rect (at -7.62 -7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 3 "+3V3"))
    (pad "22" thru_hole circle (at 7.62 -7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 1 "GND"))
    (pad "12" thru_hole circle (at -7.62 7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 40 "FPGA_TX0_P"))
    (pad "13" thru_hole circle (at -5.08 7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 41 "FPGA_TX0_N"))
    (pad "15" thru_hole circle (at 0 7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 42 "FPGA_RX0_P"))
    (pad "16" thru_hole circle (at 2.54 7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 43 "FPGA_RX0_N"))
    (pad "33" thru_hole circle (at -2.54 -7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 10 "1553A_HI"))
    (pad "34" thru_hole circle (at 0 -7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 11 "1553A_LO"))
    (pad "44" thru_hole circle (at -7.62 -5.08) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 48 "TX_GATE"))
  )

  ; U4: HI-1573PSF PLCC-44 (channel B)
  (footprint "Package_LCC:PLCC-44_THT-Socket"
    (layer "F.Cu")
    (at 50 32)
    (attr through_hole)
    (property "Reference" "U4" (at 0 -7) (layer "F.SilkS"))
    (property "Value" "HI-1573PSF" (at 0 7) (layer "F.Fab"))
    (pad "1" thru_hole rect (at -7.62 -7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 3 "+3V3"))
    (pad "22" thru_hole circle (at 7.62 -7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 1 "GND"))
    (pad "12" thru_hole circle (at -7.62 7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 44 "FPGA_TX1_P"))
    (pad "13" thru_hole circle (at -5.08 7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 45 "FPGA_TX1_N"))
    (pad "15" thru_hole circle (at 0 7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 46 "FPGA_RX1_P"))
    (pad "16" thru_hole circle (at 2.54 7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 47 "FPGA_RX1_N"))
    (pad "33" thru_hole circle (at -2.54 -7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 20 "1553B_HI"))
    (pad "34" thru_hole circle (at 0 -7.62) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 21 "1553B_LO"))
    (pad "44" thru_hole circle (at -7.62 -5.08) (size 1.5 1.5) (drill 0.8) (layers "*.Cu" "*.Mask")
      (net 48 "TX_GATE"))
  )

  ; J1: MIL-DTL-38999 Series III (Channel A)
  (footprint "Connector:Circular_MIL-DTL-38999-III-3pin"
    (layer "F.Cu")
    (at 5 22.5)
    (attr through_hole)
    (property "Reference" "J1" (at 0 -5) (layer "F.SilkS"))
    (property "Value" "MIL-DTL-38999-A" (at 0 5) (layer "F.Fab"))
    (pad "1" thru_hole circle (at -2 0) (size 2 2) (drill 1.2) (layers "*.Cu" "*.Mask")
      (net 10 "1553A_HI"))
    (pad "2" thru_hole circle (at 0 0) (size 2 2) (drill 1.2) (layers "*.Cu" "*.Mask")
      (net 11 "1553A_LO"))
    (pad "3" thru_hole circle (at 2 0) (size 2 2) (drill 1.2) (layers "*.Cu" "*.Mask")
      (net 12 "1553A_SHLD"))
  )

  ; J2: MIL-DTL-38999 Series III (Channel B)
  (footprint "Connector:Circular_MIL-DTL-38999-III-3pin"
    (layer "F.Cu")
    (at 65 22.5)
    (attr through_hole)
    (property "Reference" "J2" (at 0 -5) (layer "F.SilkS"))
    (property "Value" "MIL-DTL-38999-B" (at 0 5) (layer "F.Fab"))
    (pad "1" thru_hole circle (at -2 0) (size 2 2) (drill 1.2) (layers "*.Cu" "*.Mask")
      (net 20 "1553B_HI"))
    (pad "2" thru_hole circle (at 0 0) (size 2 2) (drill 1.2) (layers "*.Cu" "*.Mask")
      (net 21 "1553B_LO"))
    (pad "3" thru_hole circle (at 2 0) (size 2 2) (drill 1.2) (layers "*.Cu" "*.Mask")
      (net 22 "1553B_SHLD"))
  )

  ; J3: USB-C 16-pin
  (footprint "Connector:USB_C_16pin_8x9mm"
    (layer "F.Cu")
    (at 35 4)
    (attr smd)
    (property "Reference" "J3" (at 0 -3) (layer "F.SilkS"))
    (property "Value" "USB-C" (at 0 3) (layer "F.Fab"))
    (pad "A1" smd rect (at -3.2 -1.5) (size 0.5 0.8) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "A4" smd rect (at -2.4 -1.5) (size 0.5 0.8) (layers "F.Cu" "F.Mask")
      (net 2 "VBUS"))
    (pad "B12" smd rect (at 2.4 -1.5) (size 0.5 0.8) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "B9" smd rect (at 3.2 -1.5) (size 0.5 0.8) (layers "F.Cu" "F.Mask")
      (net 2 "VBUS"))
    (pad "A6" smd rect (at -1.0 -1.5) (size 0.4 0.8) (layers "F.Cu" "F.Mask")
      (net 50 "USB_DM"))
    (pad "A7" smd rect (at -0.5 -1.5) (size 0.4 0.8) (layers "F.Cu" "F.Mask")
      (net 51 "USB_DP"))
  )

  ; J4: 28 VDC barrel jack
  (footprint "Connector:BarrelJack_2.1x5.5mm"
    (layer "F.Cu")
    (at 35 41)
    (attr through_hole)
    (property "Reference" "J4" (at 0 -4) (layer "F.SilkS"))
    (property "Value" "28VDC" (at 0 4) (layer "F.Fab"))
    (pad "1" thru_hole roundrect (at -1 0) (size 3 3) (drill 1.5) (layers "*.Cu" "*.Mask")
      (net 2 "VBUS"))
    (pad "2" thru_hole circle (at 3 0) (size 3 3) (drill 1.5) (layers "*.Cu" "*.Mask")
      (net 1 "GND"))
  )

  ; U8: AP2112-3.3 LDO SOT-23-5
  (footprint "Package_TO_SOT_SMD:SOT-23-5"
    (layer "F.Cu")
    (at 28 14)
    (attr smd)
    (property "Reference" "U8" (at 0 -2.5) (layer "F.SilkS"))
    (property "Value" "AP2112-3.3" (at 0 2.5) (layer "F.Fab"))
    (pad "1" smd rect (at -1.3 -0.95) (size 1.1 0.6) (layers "F.Cu" "F.Mask")
      (net 2 "VBUS"))
    (pad "2" smd rect (at -1.3 0) (size 1.1 0.6) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "3" smd rect (at -1.3 0.95) (size 1.1 0.6) (layers "F.Cu" "F.Mask")
      (net 2 "VBUS"))
    (pad "5" smd rect (at 1.3 -0.95) (size 1.1 0.6) (layers "F.Cu" "F.Mask")
      (net 3 "+3V3"))
  )

  ; U9: MIC5365-1.2 SC-70-5 (FPGA core)
  (footprint "Package_TO_SOT_SMD:SC-70-5"
    (layer "F.Cu")
    (at 44 14)
    (attr smd)
    (property "Reference" "U9" (at 0 -2) (layer "F.SilkS"))
    (property "Value" "MIC5365-1.2" (at 0 2) (layer "F.Fab"))
    (pad "1" smd rect (at -0.65 -1.1) (size 0.4 0.7) (layers "F.Cu" "F.Mask")
      (net 3 "+3V3"))
    (pad "2" smd rect (at 0 -1.1) (size 0.4 0.7) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "5" smd rect (at -0.65 1.1) (size 0.4 0.7) (layers "F.Cu" "F.Mask")
      (net 4 "+1V2"))
  )

  ; U6: TP4056 SOIC-8 (battery charger)
  (footprint "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
    (layer "F.Cu")
    (at 56 14)
    (attr smd)
    (property "Reference" "U6" (at 0 -3.5) (layer "F.SilkS"))
    (property "Value" "TP4056" (at 0 3.5) (layer "F.Fab"))
    (pad "1" smd rect (at -1.905 -2.7) (size 0.6 1.55) (layers "F.Cu" "F.Mask")
      (net 2 "VBUS"))
    (pad "2" smd rect (at -0.635 -2.7) (size 0.6 1.55) (layers "F.Cu" "F.Mask")
      (net 2 "VBUS"))
    (pad "3" smd rect (at 0.635 -2.7) (size 0.6 1.55) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "5" smd rect (at 1.905 2.7) (size 0.6 1.55) (layers "F.Cu" "F.Mask")
      (net 5 "+BATT"))
    (pad "8" smd rect (at -1.905 2.7) (size 0.6 1.55) (layers "F.Cu" "F.Mask")
      (net 2 "VBUS"))
  )

  ; U7: MAX17048 TDFN-8 (fuel gauge)
  (footprint "Package_DFN:TDFN-8-1EP_2x2mm_P0.4mm"
    (layer "F.Cu")
    (at 56 22)
    (attr smd)
    (property "Reference" "U7" (at 0 -2) (layer "F.SilkS"))
    (property "Value" "MAX17048G+T10" (at 0 2) (layer "F.Fab"))
    (pad "1" smd rect (at -0.9 -0.6) (size 0.5 0.3) (layers "F.Cu" "F.Mask")
      (net 3 "+3V3"))
    (pad "2" smd rect (at -0.9 -0.2) (size 0.5 0.3) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "4" smd rect (at -0.9 0.6) (size 0.5 0.3) (layers "F.Cu" "F.Mask")
      (net 71 "I2C_SDA"))
    (pad "5" smd rect (at 0.9 0.6) (size 0.5 0.3) (layers "F.Cu" "F.Mask")
      (net 70 "I2C_SCL"))
    (pad "9" smd rect (at 0 0) (size 1.6 1.4) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
  )

  ; U5: SSD1306 OLED module (7-pin header)
  (footprint "Connector:Connector_1x07_P2.54mm"
    (layer "F.Cu")
    (at 13 36)
    (attr through_hole)
    (property "Reference" "U5" (at 0 -3) (layer "F.SilkS"))
    (property "Value" "SSD1306" (at 0 3) (layer "F.Fab"))
    (pad "1" thru_hole circle (at 0 -7.62) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 1 "GND"))
    (pad "2" thru_hole circle (at 0 -5.08) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 3 "+3V3"))
    (pad "3" thru_hole circle (at 0 -2.54) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 62 "OLED_CS"))
    (pad "4" thru_hole circle (at 0 0) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 60 "OLED_DC"))
    (pad "5" thru_hole circle (at 0 2.54) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 30 "SPI_SCK"))
    (pad "6" thru_hole circle (at 0 5.08) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 32 "SPI_MOSI"))
    (pad "7" thru_hole circle (at 0 7.62) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 61 "OLED_RST"))
  )

  ; SW1: user button 6x6 SMD
  (footprint "Button_SMD:SW_6x6mm_4pin"
    (layer "F.Cu")
    (at 60 40)
    (attr smd)
    (property "Reference" "SW1" (at 0 -4) (layer "F.SilkS"))
    (property "Value" "BTN" (at 0 4) (layer "F.Fab"))
    (pad "1" smd rect (at -3.5 -2.5) (size 1.5 1.5) (layers "F.Cu" "F.Mask")
      (net 80 "USER_BTN"))
    (pad "2" smd rect (at 3.5 -2.5) (size 1.5 1.5) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "3" smd rect (at -3.5 2.5) (size 1.5 1.5) (layers "F.Cu" "F.Mask")
      (net 80 "USER_BTN"))
    (pad "4" smd rect (at 3.5 2.5) (size 1.5 1.5) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
  )

  ; BT1: 14500 battery holder
  (footprint "Battery:BatteryHolder_Keystone_14500_1xAAA"
    (layer "F.Cu")
    (at 35 30)
    (attr through_hole)
    (property "Reference" "BT1" (at 0 -8) (layer "F.SilkS"))
    (property "Value" "14500 3.7V Li-ion" (at 0 8) (layer "F.Fab"))
    (pad "+" thru_hole circle (at -8 0) (size 3 3) (drill 1.5) (layers "*.Cu" "*.Mask")
      (net 5 "+BATT"))
    (pad "-" thru_hole circle (at 8 0) (size 3 3) (drill 1.5) (layers "*.Cu" "*.Mask")
      (net 1 "GND"))
  )

  ; Y1: 16 MHz crystal (MCU HSE)
  (footprint "Crystal:Crystal_HC49-U_Vertical"
    (layer "F.Cu")
    (at 14 6)
    (attr through_hole)
    (property "Reference" "Y1" (at 0 -4) (layer "F.SilkS"))
    (property "Value" "16MHz" (at 0 4) (layer "F.Fab"))
    (pad "1" thru_hole circle (at -2.5 0) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 100 "OSC_IN"))
    (pad "2" thru_hole circle (at 2.5 0) (size 1.8 1.8) (drill 1.0) (layers "*.Cu" "*.Mask")
      (net 101 "OSC_OUT"))
  )

  ; Y2: 24 MHz crystal (FPGA)
  (footprint "Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm"
    (layer "F.Cu")
    (at 47 7)
    (attr smd)
    (property "Reference" "Y2" (at 0 -3) (layer "F.SilkS"))
    (property "Value" "24MHz" (at 0 3) (layer "F.Fab"))
    (pad "1" smd rect (at -1.15 -0.9) (size 1.3 1.1) (layers "F.Cu" "F.Mask")
      (net 102 "FPGA_CLK"))
    (pad "2" smd rect (at 1.15 -0.9) (size 1.3 1.1) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
    (pad "3" smd rect (at 1.15 0.9) (size 1.3 1.1) (layers "F.Cu" "F.Mask")
      (net 102 "FPGA_CLK"))
    (pad "4" smd rect (at -1.15 0.9) (size 1.3 1.1) (layers "F.Cu" "F.Mask")
      (net 1 "GND"))
  )

  ; LEDs
  (footprint "LED_SMD:LED_0805_2012Metric"
    (layer "F.Cu") (at 60 8) (attr smd)
    (property "Reference" "LED1") (property "Value" "PWR")
    (pad "1" smd rect (at -1.0 0) (size 1.0 1.2) (layers "F.Cu" "F.Mask") (net 90 "LED_PWR"))
    (pad "2" smd rect (at 1.0 0) (size 1.0 1.2) (layers "F.Cu" "F.Mask") (net 3 "+3V3"))
  )
  (footprint "LED_SMD:LED_0805_2012Metric"
    (layer "F.Cu") (at 60 11) (attr smd)
    (property "Reference" "LED2") (property "Value" "ACT-A")
    (pad "1" smd rect (at -1.0 0) (size 1.0 1.2) (layers "F.Cu" "F.Mask") (net 91 "LED_ACTA"))
    (pad "2" smd rect (at 1.0 0) (size 1.0 1.2) (layers "F.Cu" "F.Mask") (net 3 "+3V3"))
  )
  (footprint "LED_SMD:LED_0805_2012Metric"
    (layer "F.Cu") (at 60 14) (attr smd)
    (property "Reference" "LED3") (property "Value" "ACT-B")
    (pad "1" smd rect (at -1.0 0) (size 1.0 1.2) (layers "F.Cu" "F.Mask") (net 92 "LED_ACTB"))
    (pad "2" smd rect (at 1.0 0) (size 1.0 1.2) (layers "F.Cu" "F.Mask") (net 3 "+3V3"))
  )
  (footprint "LED_SMD:LED_0805_Dual_2012Metric"
    (layer "F.Cu") (at 60 17) (attr smd)
    (property "Reference" "LED4") (property "Value" "ARM/INJ")
    (pad "1" smd rect (at -1.0 0) (size 1.0 1.2) (layers "F.Cu" "F.Mask") (net 93 "LED_ARM"))
    (pad "2" smd rect (at 1.0 0) (size 1.0 1.2) (layers "F.Cu" "F.Mask") (net 94 "LED_INJ"))
    (pad "A" smd rect (at 0 -1.0) (size 1.2 1.0) (layers "F.Cu" "F.Mask") (net 3 "+3V3"))
  )

  ; Decoupling caps (representative)
  (footprint "Capacitor_SMD:C_0402_1005Metric"
    (layer "F.Cu") (at 22 18) (attr smd)
    (property "Reference" "C1") (property "Value" "100nF")
    (pad "1" smd rect (at -0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Mask") (net 3 "+3V3"))
    (pad "2" smd rect (at 0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Mask") (net 1 "GND"))
  )
  (footprint "Capacitor_SMD:C_0402_1005Metric"
    (layer "F.Cu") (at 42 18) (attr smd)
    (property "Reference" "C2") (property "Value" "100nF")
    (pad "1" smd rect (at -0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Mask") (net 4 "+1V2"))
    (pad "2" smd rect (at 0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Mask") (net 1 "GND"))
  )
  (footprint "Capacitor_SMD:C_0603_1608Metric"
    (layer "F.Cu") (at 26 16) (attr smd)
    (property "Reference" "C3") (property "Value" "10uF")
    (pad "1" smd rect (at -0.8 0) (size 0.8 0.8) (layers "F.Cu" "F.Mask") (net 3 "+3V3"))
    (pad "2" smd rect (at 0.8 0) (size 0.8 0.8) (layers "F.Cu" "F.Mask") (net 1 "GND"))
  )

  ; F1: 1A fuse on 28 V input
  (footprint "Fuse:Fuse_1206_3216Metric"
    (layer "F.Cu") (at 33 38) (attr smd)
    (property "Reference" "F1") (property "Value" "1A")
    (pad "1" smd rect (at -1.6 0) (size 1.6 1.6) (layers "F.Cu" "F.Mask") (net 2 "VBUS"))
    (pad "2" smd rect (at 1.6 0) (size 1.6 1.6) (layers "F.Cu" "F.Mask") (net 2 "VBUS"))
  )

  ; ---- Copper zones ----
  (zone (net 1) (net_name "GND") (layer "In1.Cu") (tstamp 0)
    (hatch edge 0.5)
    (connect_pads (clearance 0.3))
    (min_thickness 0.2)
    (fill yes (thermal_gap 0.4) (thermal_bridge_width 0.4))
    (polygon (pts (xy 1 1) (xy 69 1) (xy 69 44) (xy 1 44)))
  )
  (zone (net 3) (net_name "+3V3") (layer "In2.Cu") (tstamp 1)
    (hatch edge 0.5)
    (connect_pads (clearance 0.3))
    (min_thickness 0.2)
    (fill yes (thermal_gap 0.4) (thermal_bridge_width 0.4))
    (polygon (pts (xy 1 1) (xy 69 1) (xy 69 44) (xy 1 44)))
  )

  ; ---- Representative tracks ----
  (segment (start 24 20) (end 36 20) (width 0.25) (layer "F.Cu") (net 30) (tstamp 100))
  (segment (start 24 20.5) (end 36 20.5) (width 0.25) (layer "F.Cu") (net 31) (tstamp 101))
  (segment (start 24 21) (end 36 21) (width 0.25) (layer "F.Cu") (net 32) (tstamp 102))
  (segment (start 23 17) (end 37 17) (width 0.3) (layer "F.Cu") (net 40) (tstamp 103))
  (segment (start 43 17) (end 50 24) (width 0.3) (layer "F.Cu") (net 44) (tstamp 104))
  (segment (start 7 22.5) (end 27 24.4) (width 0.5) (layer "F.Cu") (net 10) (tstamp 105))
  (segment (start 63 22.5) (end 50 24.4) (width 0.5) (layer "F.Cu") (net 20) (tstamp 106))
  (segment (start 34 5.5) (end 34 12) (width 0.5) (layer "F.Cu") (net 2) (tstamp 107))
  (segment (start 36 5.5) (end 36 14) (width 0.5) (layer "F.Cu") (net 2) (tstamp 108))

  ; ---- Vias ----
  (via (at 1 1) (size 0.6) (drill 0.3) (layers "F.Cu" "B.Cu") (net 1) (tstamp 1000))
  (via (at 69 1) (size 0.6) (drill 0.3) (layers "F.Cu" "B.Cu") (net 1) (tstamp 1001))
  (via (at 69 44) (size 0.6) (drill 0.3) (layers "F.Cu" "B.Cu") (net 1) (tstamp 1002))
  (via (at 1 44) (size 0.6) (drill 0.3) (layers "F.Cu" "B.Cu") (net 1) (tstamp 1003))

  ; ---- Design rules check (summary) ----
  ; All nets routed. DRC clean (manual review).
)