(kicad_pcb (version 20240108) (generator "nvme-phantom-pcb-gen") (generator_version "8.0") (uuid "a1b2c3d4-0002-4a02-9002-nvme-phantom-pcb") (general (thickness 1.6) (legacy_teardrops no)) (paper "A4") (title_block (title "NVMe-Phantom PCB") (date "2026-07-29") (rev "1.0") (company "jayis1") (comment 1 "Author: jayis1") (comment 2 "6-layer FR-4, 110x22mm, M.2 2280 + flex tail") (comment 3 "CERN-OHL-S v2") ) (layers (0 "F.Cu" signal "top copper — PCIe Gen3 signal, component side") (1 "In1.Cu" signal "inner 1 — GND plane (0.2mm dielectric from L1)") (2 "In2.Cu" signal "inner 2 — 3.3V power plane") (3 "In3.Cu" signal "inner 3 — 1.2V / 1.8V power rails") (4 "In4.Cu" signal "inner 4 — GND plane (0.2mm dielectric from L6)") (5 "B.Cu" signal "bottom copper — routing + passives") (6 "F.Paste" mask "front solder paste") (7 "B.Paste" mask "bottom solder paste") (8 "F.SilkS" silk "front silkscreen") (9 "B.SilkS" silk "bottom silkscreen") (10 "F.Mask" mask "front solder mask") (11 "B.Mask" mask "bottom solder mask") (12 "Dwgs.User" user "design guide") (13 "Cmts.User" user "comments") (14 "Eco1.User" user "eco 1") (15 "Eco2.User" user "eco 2") (16 "Edge.Cuts" user "board outline") (17 "Margin" user "margin") ) (setup (stackup (layer "F.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 1" (type "core") (thickness 0.2) (material "FR-4")) (layer "In1.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 2" (type "prepreg") (thickness 0.7) (material "FR-4")) (layer "In2.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 3" (type "core") (thickness 0.7) (material "FR-4")) (layer "In3.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 4" (type "prepreg") (thickness 0.2) (material "FR-4")) (layer "In4.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 5" (type "core") (thickness 0.2) (material "FR-4")) (layer "B.Cu" (type "copper") (thickness 0.035)) ) (pad_to_mask_clearance 0.05) (solder_mask_min_width 0.04) (grid_origin 0 0) (plotsetup (psnegative no) (psa4output no) (plotreference yes) (plotvalue no) (plotinvisibletext no) (sketchpadsonfab no) (subtractmaskfromsilk no) (outputformat 1) (mirror no) (drillshape 0) (scaleselection 3) (outputdirectory "gerbers/")) ) (net 0 "") (net 1 "+3V3") (net 2 "GND") (net 3 "+1V2") (net 4 "+1V8") (net 5 "VBAT") (net 10 "PCIe_TX_P0") (net 11 "PCIe_TX_N0") (net 12 "PCIe_TX_P1") (net 13 "PCIe_TX_N1") (net 14 "PCIe_TX_P2") (net 15 "PCIe_TX_N2") (net 16 "PCIe_TX_P3") (net 17 "PCIe_TX_N3") (net 18 "PCIe_RX_P0") (net 19 "PCIe_RX_N0") (net 20 "PCIe_RX_P1") (net 21 "PCIe_RX_N1") (net 22 "PCIe_RX_P2") (net 23 "PCIe_RX_N2") (net 24 "PCIe_RX_P3") (net 25 "PCIe_RX_N3") (net 30 "PCIe_SSD_TX_P0") (net 31 "PCIe_SSD_TX_N0") (net 32 "PCIe_SSD_RX_P0") (net 33 "PCIe_SSD_RX_N0") (net 40 "PCIe_FPGA_TX_P0") (net 41 "PCIe_FPGA_TX_N0") (net 42 "PCIe_FPGA_RX_P0") (net 43 "PCIe_FPGA_RX_N0") (net 50 "SPI1_SCK") (net 51 "SPI1_MOSI") (net 52 "SPI1_MISO") (net 53 "SPI1_CS_N") (net 54 "FPGA_INT") (net 55 "FPGA_CDONE") (net 56 "FPGA_CRESET") (net 60 "I2C1_SCL") (net 61 "I2C1_SDA") (net 70 "UART4_TX") (net 71 "UART4_RX") (net 72 "BLE_RESET") (net 80 "SD_CMD") (net 81 "SD_CLK") (net 82 "SD_D0") (net 83 "SD_CD") (net 90 "SPI3_SCK") (net 91 "SPI3_MOSI") (net 92 "SPI3_MISO") (net 93 "SPI3_CS_N") (net 100 "I2C2_SCL") (net 101 "I2C2_SDA") (net 110 "USB_DM") (net 111 "USB_DP") (net 120 "VBAT_SENSE") (net 121 "CHRG_STAT") (net 130 "LED_STATUS") (net 131 "LED_ERROR") (net 132 "BTN_USER") (net 140 "PEX_LINKOK") (net 141 "PEX_MODIFY_N") (footprint "Package_QFP:LQFP-64_10x10mm_P0.5mm" (layer "F.Cu") (tedit 0) (tstamp 00000001) (at 55 35) (property "Ref" "U1" (at 0 7 0)) (property "Value" "STM32H563ZIT6" (at 0 -7 0)) (property "Footprint" "Package_QFP:LQFP-64_10x10mm_P0.5mm" (at 0 0 0)) (property "Datasheet" "https://www.st.com/resource/en/datasheet/stm32h563zi.pdf") (property "Description" "STM32H5 Cortex-M33 MCU") (property "Author" "jayis1") (pad "1" smd rect (at -4.5 -3.75) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) (pad "2" smd rect (at -4.5 -3.25) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "13" smd rect (at -4.5 2.25) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 50 "SPI1_SCK")) (pad "14" smd rect (at -4.5 2.75) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 51 "SPI1_MOSI")) (pad "15" smd rect (at -4.5 3.25) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 52 "SPI1_MISO")) (pad "16" smd rect (at -4.5 3.75) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 53 "SPI1_CS_N")) (pad "29" smd rect (at -3.25 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 71 "UART4_RX")) (pad "30" smd rect (at -2.75 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 70 "UART4_TX")) (pad "42" smd rect (at 3.75 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 60 "I2C1_SCL")) (pad "43" smd rect (at 3.25 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 61 "I2C1_SDA")) (pad "44" smd rect (at 2.75 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 110 "USB_DM")) (pad "45" smd rect (at 2.25 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 111 "USB_DP")) (pad "46" smd rect (at 1.75 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 100 "I2C2_SCL")) (pad "47" smd rect (at 1.25 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 101 "I2C2_SDA")) (pad "50" smd rect (at -1.25 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 92 "SPI3_MISO")) (pad "51" smd rect (at -1.75 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 90 "SPI3_SCK")) (pad "52" smd rect (at -2.25 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 91 "SPI3_MOSI")) (pad "55" smd rect (at -3.75 4.5) (size 1.2 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 93 "SPI3_CS_N")) ) (footprint "Package_BGA:BGA-324_23.0x23.0mm_15x15" (layer "F.Cu") (tedit 0) (tstamp 00000002) (at 130 35) (property "Ref" "U2" (at 0 13 0)) (property "Value" "PEX8606-AB65BIG" (at 0 -13 0)) (property "Footprint" "Package_BGA:BGA-324_23.0x23.0mm_15x15" (at 0 0 0)) (property "Datasheet" "https://docs.broadcom.com/doc/PEX8606-AB-Data-Sheet") (property "Description" "Broadcom PEX8606 PCIe Gen3 switch") (property "Author" "jayis1") (pad "A1" smd circle (at -10.5 -10.5) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) (pad "A2" smd circle (at -9.0 -10.5) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "B1" smd circle (at -10.5 -9.0) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 10 "PCIe_TX_P0")) (pad "B2" smd circle (at -9.0 -9.0) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 11 "PCIe_TX_N0")) (pad "B3" smd circle (at -7.5 -9.0) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 18 "PCIe_RX_P0")) (pad "B4" smd circle (at -6.0 -9.0) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 19 "PCIe_RX_N0")) (pad "C1" smd circle (at -10.5 -7.5) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 30 "PCIe_SSD_TX_P0")) (pad "C2" smd circle (at -9.0 -7.5) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 31 "PCIe_SSD_TX_N0")) (pad "C3" smd circle (at -7.5 -7.5) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 32 "PCIe_SSD_RX_P0")) (pad "C4" smd circle (at -6.0 -7.5) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 33 "PCIe_SSD_RX_N0")) (pad "D1" smd circle (at -10.5 -6.0) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 40 "PCIe_FPGA_TX_P0")) (pad "D3" smd circle (at -7.5 -6.0) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 42 "PCIe_FPGA_RX_P0")) (pad "E1" smd circle (at -10.5 -4.5) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 60 "I2C1_SCL")) (pad "E2" smd circle (at -9.0 -4.5) (size 0.6 0.6) (layers "F.Cu" "F.Paste" "F.Mask") (net 61 "I2C1_SDA")) ) (footprint "Package_BGA:BGA-285_17.0x17.0mm_15x15" (layer "F.Cu") (tedit 0) (tstamp 00000003) (at 200 35) (property "Ref" "U3" (at 0 11 0)) (property "Value" "LFE5UM-45F-8MG285I" (at 0 -11 0)) (property "Footprint" "Package_BGA:BGA-285_17.0x17.0mm_15x15" (at 0 0 0)) (property "Datasheet" "https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/ECP5/ECP5andECP5GDataSheet.pdf") (property "Description" "Lattice ECP5 45K LUT FPGA") (property "Author" "jayis1") (pad "A1" smd circle (at -7.5 -7.5) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) (pad "A2" smd circle (at -6.5 -7.5) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "B5" smd circle (at -3.5 -6.5) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 40 "PCIe_FPGA_TX_P0")) (pad "B6" smd circle (at -2.5 -6.5) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 42 "PCIe_FPGA_RX_P0")) (pad "C7" smd circle (at -1.5 -5.5) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 50 "SPI1_SCK")) (pad "C8" smd circle (at -0.5 -5.5) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 51 "SPI1_MOSI")) (pad "C9" smd circle (at 0.5 -5.5) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 52 "SPI1_MISO")) (pad "C10" smd circle (at 1.5 -5.5) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 53 "SPI1_CS_N")) ) (footprint "Connector_Edge:M.2-M-Key-75pos-0.5mm" (layer "F.Cu") (tedit 0) (tstamp 00000004) (at 130 5) (property "Ref" "J1" (at 0 -6 0)) (property "Value" "M.2_M_Key_Edge" (at 0 6 0)) (property "Description" "M.2 M-key edge finger to host slot") (property "Author" "jayis1") (pad "1" smd rect (at -9.25 -2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 10 "PCIe_TX_P0")) (pad "3" smd rect (at -8.75 -2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 11 "PCIe_TX_N0")) (pad "5" smd rect (at -8.25 -2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 18 "PCIe_RX_P0")) (pad "7" smd rect (at -7.75 -2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 19 "PCIe_RX_N0")) (pad "75" smd rect (at 9.25 -2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) (pad "74" smd rect (at 8.75 -2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) ) (footprint "Connector:M.2-M-Key-Socket-75pos" (layer "F.Cu") (tedit 0) (tstamp 00000005) (at 130 65) (property "Ref" "J2" (at 0 -6 0)) (property "Value" "M.2_M_Key_Socket" (at 0 6 0)) (property "Description" "Amphenol M.2 M-key socket for target SSD") (property "Author" "jayis1") (pad "1" smd rect (at -9.25 2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 32 "PCIe_SSD_RX_P0")) (pad "3" smd rect (at -8.75 2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 33 "PCIe_SSD_RX_N0")) (pad "5" smd rect (at -8.25 2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 30 "PCIe_SSD_TX_P0")) (pad "7" smd rect (at -7.75 2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 31 "PCIe_SSD_TX_N0")) (pad "75" smd rect (at 9.25 2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) (pad "74" smd rect (at 8.75 2) (size 0.3 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) ) (footprint "RF_Module:nRF52840-M2-Module" (layer "F.Cu") (tedit 0) (tstamp 00000006) (at 55 75) (property "Ref" "U4" (at 0 -8 0)) (property "Value" "nRF52840-M2" (at 0 8 0)) (property "Description" "Adafruit nRF52840 M.2 BLE module") (property "Author" "jayis1") (pad "1" smd rect (at -7 -1) (size 1 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) (pad "2" smd rect (at -7 1) (size 1 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "5" smd rect (at -4 -1) (size 1 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 70 "UART4_TX")) (pad "6" smd rect (at -4 1) (size 1 2) (layers "F.Cu" "F.Paste" "F.Mask") (net 71 "UART4_RX")) ) (footprint "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" (layer "F.Cu") (tedit 0) (tstamp 00000007) (at 200 75) (property "Ref" "U5" (at 0 -4 0)) (property "Value" "W25Q128JVSIQ" (at 0 4 0)) (property "Description" "Winbond 16MB SPI NOR flash") (property "Author" "jayis1") (pad "1" smd rect (at -2.7 -1.9) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 93 "SPI3_CS_N")) (pad "2" smd rect (at -1.4 -1.9) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 92 "SPI3_MISO")) (pad "4" smd rect (at 0 -1.9) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "5" smd rect (at 1.4 -1.9) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 91 "SPI3_MOSI")) (pad "6" smd rect (at 2.7 -1.9) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 90 "SPI3_SCK")) (pad "8" smd rect (at -2.7 1.9) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) ) ;; Decoupling capacitors (footprint "Capacitor_SMD:C_0402_1005Metric" (layer "F.Cu") (tstamp 00000010) (at 50 45) (property "Ref" "C1") (property "Value" "100nF") (pad "1" smd rect (at -0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) (pad "2" smd rect (at 0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND"))) (footprint "Capacitor_SMD:C_0402_1005Metric" (layer "F.Cu") (tstamp 00000011) (at 195 45) (property "Ref" "C2") (property "Value" "10uF") (pad "1" smd rect (at -0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "+3V3")) (pad "2" smd rect (at 0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND"))) (footprint "Capacitor_SMD:C_0402_1005Metric" (layer "F.Cu") (tstamp 00000012) (at 205 45) (property "Ref" "C3") (property "Value" "100nF") (pad "1" smd rect (at -0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 3 "+1V2")) (pad "2" smd rect (at 0.5 0) (size 0.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND"))) ;; Board outline — 110mm x 22mm (M.2 2280 stick + 30mm flex tail) (gr_line (start 0 0) (end 110 0) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 110 0) (end 110 22) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 110 22) (end 0 22) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 0 22) (end 0 0) (layer "Edge.Cuts") (width 0.1)) ;; Design rules: PCIe Gen3 impedance-controlled (gr_text "NVMe-Phantom rev1.0 jayis1 110x22mm 6L FR-4 85ohm/100ohm" (at 55 11) (layer "F.SilkS") (effects (font (size 1 1)))) (zone (net 2) (net_name "GND") (layer "In1.Cu") (tstamp 00000100) (hatch edge 0.5) (connect_pads (clearance 0.2)) (fill yes (thermal_gap 0.2) (thermal_bridge_width 0.3)) (polygon (pts (xy 0 0) (xy 110 0) (xy 110 22) (xy 0 22)))) (zone (net 1) (net_name "+3V3") (layer "In2.Cu") (tstamp 00000101) (hatch edge 0.5) (connect_pads (clearance 0.2)) (fill yes) (polygon (pts (xy 0 0) (xy 110 0) (xy 110 22) (xy 0 22)))) (zone (net 2) (net_name "GND") (layer "In4.Cu") (tstamp 00000102) (hatch edge 0.5) (connect_pads (clearance 0.2)) (fill yes) (polygon (pts (xy 0 0) (xy 110 0) (xy 110 22) (xy 0 22)))) (segment (start 55.3 35) (end 129.5 35) (width 0.15) (layer "F.Cu") (net 50)) (segment (start 55.5 35.5) (end 199.5 35.5) (width 0.15) (layer "F.Cu") (net 51)) (segment (start 55.7 36) (end 200.5 36) (width 0.15) (layer "F.Cu") (net 52)) (segment (start 55.9 36.5) (end 201.5 36.5) (width 0.15) (layer "F.Cu") (net 53)) )