(kicad_pcb (version 20241128) (generator "planner")

  (general
    (thickness 1.6)
    (drawings 12)
    (tracks 2400)
    (zones 8)
    (modules 28)
    (nets 85)
  )

  (page "A4")
  (title_block
    (title "PhantomBridge - PoE Network Implant")
    (date "2026-06-15")
    (rev "1.0")
    (company "Hacker Devices")
  )

  ============================================================
  -- Layer Stackup
  ============================================================
  (setup
    (stackup
      (layer 0 "F.Cu" signal)
        (thickness 0.035)
        (material "Copper")
        (roughness 0.2)
      (layer 1 "Prepreg" dielectric)
        (thickness 0.12)
        (material "2116")
        (epsilon_r 4.2)
        (loss_tan 0.02)
      (layer 2 "In1.Cu" power)
        (thickness 0.035)
        (material "Copper")
        (roughness 0.2)
      (layer 3 "Core" dielectric)
        (thickness 0.9)
        (material "FR-4")
        (epsilon_r 4.5)
        (loss_tan 0.02)
      (layer 4 "In2.Cu" power)
        (thickness 0.035)
        (material "Copper")
        (roughness 0.2)
      (layer 5 "Prepreg" dielectric)
        (thickness 0.12)
        (material "2116")
        (epsilon_r 4.2)
        (loss_tan 0.02)
      (layer 6 "B.Cu" signal)
        (thickness 0.035)
        (material "Copper")
        (roughness 0.2)
    )
    (user_trace_width 0.127)   ;; 5mil diff pair
    (user_trace_width 0.178)   ;; 7mil diff pair gap
    (user_trace_width 0.249)   ;; 50Ω SE
    (user_trace_width 0.15)    ;; SDRAM
    (user_trace_width 1.0)     ;; PoE power
    (user_via (diameter 0.45) (drill 0.2))   ;; Signal
    (user_via (diameter 0.6) (drill 0.3))    ;; Power
    (user_via (diameter 0.8) (drill 0.5))    ;; PoE
    (pad_size 1.5 0.5)  ;; QFP pad
  )

  ============================================================
  -- Board Outline
  ============================================================
  (gr_rect (start 0 0) (end 35 20) (layer "Edge.Cuts") (width 0.15)
    (round_offset 1.0)
  )

  ;; Mounting holes
  (pad "" np_thru_hole (at 3.5 2.0) (size 1.6 1.6) (drill 1.6)
    (property "pad_type" "np_thru_hole"))
  (pad "" np_thru_hole (at 31.5 2.0) (size 1.6 1.6) (drill 1.6)
    (property "pad_type" "np_thru_hole"))

  ============================================================
  -- Net Classes
  ============================================================
  (net_class "Default"
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.45)
    (via_drill 0.2)
  )
  (net_class "100Ω Diff"
    (clearance 0.5)
    (trace_width 0.127)
    (via_dia 0.45)
    (via_drill 0.2)
    (diff_pair_gap 0.178)
  )
  (net_class "50Ω SE"
    (clearance 0.2)
    (trace_width 0.249)
    (via_dia 0.45)
    (via_drill 0.2)
  )
  (net_class "SDRAM"
    (clearance 0.15)
    (trace_width 0.15)
    (via_dia 0.45)
    (via_drill 0.2)
  )
  (net_class "PoE Power"
    (clearance 0.5)
    (trace_width 1.0)
    (via_dia 0.8)
    (via_drill 0.5)
  )

  ============================================================
  -- Component Placement
  ============================================================

  ;; RJ45 Input Connector
  (module "Footprint:RJ45_Shielded_SideEntry" (at 3.5 10) (layer "F.Cu")
    (fp_text reference "J1" (at 0 -3) (layer "F.SilkS"))
    (pad 1 smd rect (at -2.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 80 "T1_P1_TX+"))
    (pad 2 smd rect (at -1.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 81 "T1_P1_TX-"))
    (pad 3 smd rect (at -0.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 82 "T1_P1_RX+"))
    (pad 4 smd rect (at 0.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 70 "POE_VIN_RAW"))  ;; PoE spare pair A
    (pad 5 smd rect (at 1.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 70 "POE_VIN_RAW"))  ;; PoE spare pair B
    (pad 6 smd rect (at 2.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 83 "T1_P1_RX-"))
    (pad 7 smd rect (at 3.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 70 "POE_VIN_RAW"))  ;; PoE spare pair C
    (pad 8 smd rect (at 4.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 70 "POE_VIN_RAW"))  ;; PoE spare pair D
    (pad SH smd rect (at -4 0) (size 2 5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 99 "CHASSIS_GND"))
  )

  ;; RJ45 Output Connector
  (module "Footprint:RJ45_Shielded_SideEntry" (at 31.5 10) (layer "F.Cu")
    (fp_text reference "J2" (at 0 -3) (layer "F.SilkS"))
    (pad 1 smd rect (at -2.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "T2_P2_TX+"))
    (pad 2 smd rect (at -1.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "T2_P2_TX-"))
    (pad 3 smd rect (at -0.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "T2_P2_RX+"))
    (pad 4 smd rect (at 0.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 72 "POE_OUT"))  ;; PoE pass-through
    (pad 5 smd rect (at 1.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 72 "POE_OUT"))
    (pad 6 smd rect (at 2.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "T2_P2_RX-"))
    (pad 7 smd rect (at 3.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 72 "POE_OUT"))
    (pad 8 smd rect (at 4.5 0) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 72 "POE_OUT"))
    (pad SH smd rect (at -4 0) (size 2 5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 99 "CHASSIS_GND"))
  )

  ;; Magnetics 1 (Input)
  (module "Footprint:DIP-16_21x13mm" (at 8 10) (layer "F.Cu")
    (fp_text reference "T1" (at 0 -8) (layer "F.SilkS"))
    (pad 1 smd rect (at -9.5 -2.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 2 smd rect (at -9.5 -1.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 3 smd rect (at -9.5 -0.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 4 smd rect (at -9.5 0.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 5 smd rect (at -9.5 1.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 6 smd rect (at -9.5 2.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 7 smd rect (at 9.5 -2.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 8 smd rect (at 9.5 -1.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 9 smd rect (at 9.5 -0.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 14 smd rect (at 9.5 2.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 15 smd rect (at 9.5 3.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 70 "POE_VIN_RAW"))  ;; Center tap → PoE extraction
    (pad 16 smd rect (at 9.5 4.5) (size 1.5 0.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 70 "POE_VIN_RAW"))
  )

  ;; Magnetics 2 (Output)
  (module "Footprint:DIP-16_21x13mm" (at 27 10) (layer "F.Cu")
    (fp_text reference "T2" (at 0 -8) (layer "F.SilkS"))
  )

  ;; Ethernet Switch KSZ9897R
  (module "Footprint:QFN-128_12x12mm_P0.4mm" (at 17.5 10) (layer "F.Cu")
    (fp_text reference "U2" (at 0 0) (layer "F.SilkS"))
    (pad "" smd rect (at 0 0) (size 8 8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND") (property "pad_type" "thermal_pad"))
    ;; Port 1 pins (left side)
    (pad 3 smd rect (at -5.8 -3.6) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 84 "SW_P1_TX+") (class "100Ω Diff"))
    (pad 4 smd rect (at -5.8 -3.2) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 85 "SW_P1_TX-") (class "100Ω Diff"))
    (pad 5 smd rect (at -5.8 -2.8) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 86 "SW_P1_RX+") (class "100Ω Diff"))
    (pad 6 smd rect (at -5.8 -2.4) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 87 "SW_P1_RX-") (class "100Ω Diff"))
    ;; Port 2 pins (right side)
    (pad 11 smd rect (at 5.8 -3.6) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "SW_P2_TX+") (class "100Ω Diff"))
    (pad 12 smd rect (at 5.8 -3.2) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "SW_P2_TX-") (class "100Ω Diff"))
    (pad 13 smd rect (at 5.8 -2.8) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "SW_P2_RX+") (class "100Ω Diff"))
    (pad 14 smd rect (at 5.8 -2.4) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "SW_P2_RX-") (class "100Ω Diff"))
    ;; RGMII CPU port pins (top)
    (pad 65 smd rect (at -2.0 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 11 "ETH_TXD0") (class "50Ω SE"))
    (pad 66 smd rect (at -1.6 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 12 "ETH_TXD1") (class "50Ω SE"))
    (pad 67 smd rect (at -1.2 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 13 "ETH_TXD2") (class "50Ω SE"))
    (pad 68 smd rect (at -0.8 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 14 "ETH_TXD3") (class "50Ω SE"))
    (pad 69 smd rect (at -0.4 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 15 "ETH_TXCTL") (class "50Ω SE"))
    (pad 70 smd rect (at 0.0 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 10 "ETH_TXCLK") (class "50Ω SE"))
    (pad 71 smd rect (at 0.4 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 20 "ETH_RXD0") (class "50Ω SE"))
    (pad 72 smd rect (at 0.8 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 21 "ETH_RXD1") (class "50Ω SE"))
    (pad 73 smd rect (at 1.2 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 22 "ETH_RXD2") (class "50Ω SE"))
    (pad 74 smd rect (at 1.6 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 23 "ETH_RXD3") (class "50Ω SE"))
    (pad 75 smd rect (at 2.0 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 24 "ETH_RXCTL") (class "50Ω SE"))
    (pad 76 smd rect (at 2.4 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 25 "ETH_RXCLK") (class "50Ω SE"))
    ;; MDC/MDIO management
    (pad 80 smd rect (at 3.6 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 30 "ETH_MDC"))
    (pad 81 smd rect (at 4.0 -5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 31 "ETH_MDIO"))
    ;; Power pins
    (pad 15 smd rect (at -5.8 -2.0) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "VDDA_3V3"))
    (pad 40 smd rect (at -5.8 0.0) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "VDD_3V3"))
    (pad 50 smd rect (at 0.0 5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 2 "VDD_1V2"))
    (pad 128 smd rect (at 5.8 5.8) (size 0.2 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
    ;; Crystal pins
    (pad 120 smd rect (at 4.0 5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "Y1_XI"))
    (pad 121 smd rect (at 4.4 5.8) (size 1.5 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "Y1_XO"))
  )

  ;; STM32H743ZIT6 Main MCU
  (module "Footprint:LQFP-144_10x10mm_P0.5mm" (at 17.5 15) (layer "F.Cu")
    (fp_text reference "U1" (at 0 0) (layer "F.SilkS"))
    ;; RGMII pins
    (pad 17 smd rect (at -4.5 -2.0) (size 0.25 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 30 "ETH_MDC"))
    (pad 18 smd rect (at -4.5 -1.5) (size 0.25 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 31 "ETH_MDIO"))
    (pad 30 smd rect (at -4.5 4.5) (size 0.25 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 10 "ETH_TXCLK"))
    (pad 31 smd rect (at -4.5 5.0) (size 0.25 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 11 "ETH_TXD0"))
    (pad 32 smd rect (at -4.0 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 12 "ETH_TXD1"))
    (pad 33 smd rect (at -3.5 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 13 "ETH_TXD2"))
    (pad 34 smd rect (at -3.0 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 14 "ETH_TXD3"))
    (pad 35 smd rect (at -2.5 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 15 "ETH_TXCTL"))
    (pad 44 smd rect (at 2.0 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 20 "ETH_RXD0"))
    (pad 45 smd rect (at 2.5 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 21 "ETH_RXD1"))
    (pad 46 smd rect (at 3.0 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 22 "ETH_RXD2"))
    (pad 47 smd rect (at 3.5 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 23 "ETH_RXD3"))
    (pad 48 smd rect (at 4.0 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 24 "ETH_RXCTL"))
    (pad 49 smd rect (at 4.5 5.5) (size 1.5 0.25) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 25 "ETH_RXCLK"))
    ;; System pins
    (pad 7 smd rect (at -4.5 -5.0) (size 0.25 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "VDD_3V3"))
    (pad 8 smd rect (at -4.5 -4.5) (size 0.25 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
    (pad 19 smd rect (at -4.5 0.0) (size 0.25 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 90 "NRST"))
    (pad 20 smd rect (at -4.5 0.5) (size 0.25 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 91 "BOOT0"))
  )

  ;; SDRAM IS42S32800G
  (module "Footprint:VFBGA-54_8x13mm_P0.8mm" (at 17.5 18) (layer "F.Cu")
    (fp_text reference "U9" (at 0 0) (layer "F.SilkS"))
  )

  ;; SPI Flash W25Q128JVSIQ
  (module "Footprint:SOIC-8_5x6mm_P1.27mm" (at 25 18) (layer "F.Cu")
    (fp_text reference "U10" (at 0 -4) (layer "F.SilkS"))
    (pad 1 smd rect (at -1.905 -2.7) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 63 "FLASH_CS#"))
    (pad 2 smd rect (at -0.635 -2.7) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 62 "FLASH_MISO"))
    (pad 3 smd rect (at 0.635 -2.7) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))  ;; WP# tied low
    (pad 4 smd rect (at 1.905 -2.7) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
    (pad 5 smd rect (at 1.905 2.7) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 61 "FLASH_MOSI"))
    (pad 6 smd rect (at 0.635 2.7) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 60 "FLASH_SCK"))
    (pad 7 smd rect (at -0.635 2.7) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "VDD_3V3"))  ;; HOLD# tied high
    (pad 8 smd rect (at -1.905 2.7) (size 0.6 1.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "VDD_3V3"))
  )

  ;; BLE Module nRF52832
  (module "Footprint:QFN-48_6x6mm_P0.4mm" (at 28 14) (layer "F.Cu")
    (fp_text reference "U11" (at 0 0) (layer "F.SilkS"))
    (pad 2 smd rect (at -2.8 -1.2) (size 0.2 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 41 "BLE_UART_RX"))  ;; P0.02
    (pad 3 smd rect (at -2.8 -0.8) (size 0.2 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 40 "BLE_UART_TX"))  ;; P0.03
    (pad 9 smd rect (at -2.8 1.2) (size 0.2 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "VDD_3V3"))
    (pad 10 smd rect (at -2.8 1.6) (size 0.2 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
    (pad 14 smd rect (at 0 2.8) (size 1.0 0.2) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "BLE_ANT"))  ;; Antenna feed
    (pad "" smd rect (at 0 0) (size 3.5 3.5) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND") (property "pad_type" "thermal_pad"))
  )

  ;; PoE PD Controller (Input)
  (module "Footprint:TSSOP-20_6.5x6.5mm_P0.65mm" (at 8 15) (layer "F.Cu")
    (fp_text reference "U3" (at 0 -4) (layer "F.SilkS"))
    (pad 1 smd rect (at -2.8 -3.25) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 71 "VPOE_48V"))
    (pad 6 smd rect (at -2.8 -0.65) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 72 "POE_PG"))
    (pad 8 smd rect (at -2.8 0.0) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 51 "POE_SDA"))
    (pad 9 smd rect (at -2.8 0.65) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 50 "POE_SCL"))
    (pad 11 smd rect (at 2.8 3.25) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
    (pad 12 smd rect (at 2.8 2.6) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 7 "POE_GATE"))
  )

  ;; PoE PD Controller (Output pass-through)
  (module "Footprint:TSSOP-20_6.5x6.5mm_P0.65mm" (at 27 4) (layer "F.Cu")
    (fp_text reference "U4" (at 0 -4) (layer "F.SilkS"))
  )

  ;; Main DC-DC 48V→3.3V
  (module "Footprint:SOT-563-6" (at 12 16) (layer "F.Cu")
    (fp_text reference "U5" (at 0 -2) (layer "F.SilkS"))
    (pad 1 smd rect (at -0.95 -0.65) (size 0.5 0.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 71 "VPOE_48V") (class "PoE Power"))
    (pad 2 smd rect (at 0 -0.65) (size 0.5 0.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
    (pad 3 smd rect (at 0.95 -0.65) (size 0.5 0.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 1 "VDD_3V3"))
    (pad 4 smd rect (at -0.95 0.65) (size 0.5 0.35) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 5 smd rect (at 0 0.65) (size 0.5 0.35) (layers "F.Cu" "F.Paste" "F.Mask"))
    (pad 6 smd rect (at 0.95 0.65) (size 0.5 0.35) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
  )

  ;; 1.2V Buck
  (module "Footprint:SOT-23-5" (at 14 16) (layer "F.Cu")
    (fp_text reference "U6" (at 0 -2) (layer "F.SilkS"))
  )

  ;; 1.8V Buck
  (module "Footprint:SOT-23-5" (at 16 16) (layer "F.Cu")
    (fp_text reference "U7" (at 0 -2) (layer "F.SilkS"))
  )

  ;; 2.5V Buck
  (module "Footprint:SOT-23-5" (at 18 16) (layer "F.Cu")
    (fp_text reference "U8" (at 0 -2) (layer "F.SilkS"))
  )

  ;; TVS Diode
  (module "Footprint:DO-214AA" (at 6 15) (layer "F.Cu")
    (fp_text reference "D1" (at 0 -2) (layer "F.SilkS"))
    (pad 1 smd rect (at -2.1 0) (size 1.5 2.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 70 "POE_VIN_RAW") (class "PoE Power"))
    (pad 2 smd rect (at 2.1 0) (size 1.5 2.3) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
  )

  ;; ESD protection
  (module "Footprint:SOT-143" (at 25 16) (layer "F.Cu")
    (fp_text reference "D2" (at 0 -2) (layer "F.SilkS"))
  )

  ;; Inductors
  (module "Footprint:3015" (at 10 17) (layer "F.Cu")
    (fp_text reference "L1" (at 0 -2) (layer "F.SilkS"))
    (property "Value" "4.7µH 1.5A"))
  )
  (module "Footprint:3015" (at 12 18) (layer "F.Cu")
    (fp_text reference "L2" (at 0 -2) (layer "F.SilkS"))
  )
  (module "Footprint:3015" (at 14 18) (layer "F.Cu")
    (fp_text reference "L3" (at 0 -2) (layer "F.SilkS"))
  )
  (module "Footprint:3015" (at 16 18) (layer "F.Cu")
    (fp_text reference "L4" (at 0 -2) (layer "F.SilkS"))
  )

  ;; Tactile switches
  (module "Footprint:B3U-1000P" (at 30 17) (layer "F.Cu")
    (fp_text reference "SW1" (at 0 -2) (layer "F.SilkS"))
    (pad 1 smd rect (at -1.5 0) (size 0.8 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 90 "NRST"))
    (pad 2 smd rect (at 1.5 0) (size 0.8 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
  )
  (module "Footprint:B3U-1000P" (at 32 17) (layer "F.Cu")
    (fp_text reference "SW2" (at 0 -2) (layer "F.SilkS"))
    (pad 1 smd rect (at -1.5 0) (size 0.8 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 91 "BOOT0"))
    (pad 2 smd rect (at 1.5 0) (size 0.8 1.0) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
  )

  ;; Crystals
  (module "Footprint:Crystal_SMD_ABM8" (at 17.5 7) (layer "F.Cu")
    (fp_text reference "Y1" (at 0 -2) (layer "F.SilkS"))
    (property "Value" "48.000MHz")
    (pad 1 smd rect (at -1.25 0) (size 1.0 1.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "Y1_XI"))
    (pad 2 smd rect (at 1.25 0) (size 1.0 1.8) (layers "F.Cu" "F.Paste" "F.Mask")
      (net "Y1_XO"))
    (pad 3 smd rect (at -1.25 1.4) (size 1.0 0.4) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
    (pad 4 smd rect (at 1.25 1.4) (size 1.0 0.4) (layers "F.Cu" "F.Paste" "F.Mask")
      (net 5 "GND"))
  )

  (module "Footprint:Crystal_SMD_ABM8" (at 20 8) (layer "F.Cu")
    (fp_text reference "Y2" (at 0 -2) (layer "F.SilkS"))
    (property "Value" "25.000MHz")
  )
  (module "Footprint:Crystal_SMD_3215" (at 22 8) (layer "F.Cu")
    (fp_text reference "Y3" (at 0 -2) (layer "F.SilkS"))
    (property "Value" "32.768kHz")
  )
  (module "Footprint:Crystal_SMD_ABM8" (at 29 12) (layer "F.Cu")
    (fp_text reference "Y4" (at 0 -2) (layer "F.SilkS"))
    (property "Value" "32.000MHz")
  )

  ============================================================
  -- Zones (Power Planes)
  ============================================================
  ;; L2 Ground Plane (solid, entire layer)
  (zone (net 5 "GND") (net_name "GND") (layer "In1.Cu")
    (hatch edge 0.5)
    (connect_pads (mode solid))
    (fill (mode solid))
    (polygon (pts (xy 0.5 0.5) (xy 34.5 0.5) (xy 34.5 19.5) (xy 0.5 19.5)))
  )

  ;; L3 Power Plane - VPOE 48V (left section)
  (zone (net 71 "VPOE_48V") (net_name "VPOE_48V") (layer "In2.Cu")
    (hatch edge 0.5)
    (connect_pads (mode solid))
    (fill (mode solid))
    (polygon (pts (xy 0.5 0.5) (xy 15 0.5) (xy 15 19.5) (xy 0.5 19.5)))
  )

  ;; L3 Power Plane - VDD_3V3 (center section)
  (zone (net 1 "VDD_3V3") (net_name "VDD_3V3") (layer "In2.Cu")
    (hatch edge 0.5)
    (connect_pads (mode solid))
    (fill (mode solid))
    (polygon (pts (xy 15.5 0.5) (xy 25 0.5) (xy 25 19.5) (xy 15.5 19.5)))
  )

  ;; L3 Power Plane - VDD_1V2 (right section)
  (zone (net 2 "VDD_1V2") (net_name "VDD_1V2") (layer "In2.Cu")
    (hatch edge 0.5)
    (connect_pads (mode solid))
    (fill (mode solid))
    (polygon (pts (xy 25.5 0.5) (xy 34.5 0.5) (xy 34.5 19.5) (xy 25.5 19.5)))
  )

  ;; Bottom copper pour for BLE antenna keepout clearance
  (zone (net 0 "") (net_name "") (layer "B.Cu")
    (hatch edge 0.5)
    (connect_pads (mode none))
    (fill (mode none))
    (polygon (pts (xy 25 11) (xy 34 11) (xy 34 17) (xy 25 17)))
    (property "keepout" "true")
  )
)