(kicad_pcb (version 20240108) (generator "pcbnew") (generator_version "8.0") (general (thickness 1.2) (legacy_teardrops no) ) (paper "A4") (title_block (title "Prism-Tap — MIPI CSI-2 / DSI Interface Tap & Injection Implant") (date "2026-08-07") (rev "1.0") (company "Author: jayis1") (comment 1 "Open-source MIPI CSI-2/DSI tap for security research") (comment 2 "MCU: STM32H730VB | FPGA: iCE40-UP5K | BLE: nRF52840") (comment 3 "License: GPL-2.0 / CERN-OHL-S v2") ) (layers (0 "F.Cu" signal) (1 "In1.Cu" signal "GND") (2 "In2.Cu" signal "PWR") (31 "B.Cu" signal) (32 "B.Adhes" user "B.Adhesive") (33 "F.Adhes" user "F.Adhesive") (34 "B.Paste" user) (35 "F.Paste" user) (36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen") (38 "B.Mask" user) (39 "F.Mask" user) (40 "Dwgs.User" user "User.Drawings") (41 "Cmts.User" user "User.Comments") (42 "Eco1.User" user "User.Eco1") (43 "Eco2.User" user "User.Eco2") (44 "Edge.Cuts" user) (45 "Margin" user) (46 "B.CrtYd" user "B.Courtyard") (47 "F.CrtYd" user "F.Courtyard") (48 "B.Fab" user) (49 "F.Fab" user) ) (setup (stackup (layer "F.SilkS" (type "Silk Screen") (color "White")) (layer "F.Paste" (type "Solder Paste")) (layer "F.Mask" (type "Solder Mask") (color "Black") (thickness 0.01)) (layer "F.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 1" (type "core") (thickness 0.2) (material "FR4") (epsilon_r 4.5)) (layer "In1.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 2" (type "prepreg") (thickness 0.36) (material "FR4") (epsilon_r 4.5)) (layer "In2.Cu" (type "copper") (thickness 0.035)) (layer "dielectric 3" (type "core") (thickness 0.2) (material "FR4") (epsilon_r 4.5)) (layer "B.Cu" (type "copper") (thickness 0.035)) (layer "B.Mask" (type "Solder Mask") (color "Black") (thickness 0.01)) (layer "B.Paste" (type "Solder Paste")) (layer "B.SilkS" (type "Silk Screen") (color "White")) (copper_finish "ENIG") ) (pad_to_mask_clearance 0.05) (pcbplotparams (layerselection 0x0001000ffffffff) (plot_on_all_layers_selection 0x0001000ffffffff) (disableapertmacros no) (usegerberextensions yes) (usegerberattributes yes) (usegerberadvancedattributes yes) (creategerberjobfile yes) (dashed_line_dash_ratio 12.000000) (dashed_line_gap_ratio 3.000000) (svgprecision 6) (plotframeref no) (mode 1) (useauxorigin no) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) (pdf_front_fp_property yes) (pdf_back_fp_property yes) (dxfpolygonmode yes) (dxfimperialunits no) (dxfusepcbnewfont yes) (psnegative no) (psa4output yes) (plotreference yes) (plotvalue yes) (plotfptext yes) (plotinvisibletext no) (sketchpadsonfab no) (sketchholesno no) (subtractmaskfromsilk no) (outputformat 1) (mirror no) (drillmarks 1) (scaleselection 1) (outputdirectory "gerbers/") ) ) ;; ============== BOARD OUTLINE (45 x 25 mm) ============== (gr_line (start 0 0) (end 45 0) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 45 0) (end 45 25) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 45 25) (end 0 25) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 0 25) (end 0 0) (layer "Edge.Cuts") (width 0.1)) ;; Mounting holes (gr_circle (center 2 2) (end 3 2) (layer "Edge.Cuts") (width 0.1)) (gr_circle (center 43 2) (end 44 2) (layer "Edge.Cuts") (width 0.1)) (gr_circle (center 2 23) (end 3 23) (layer "Edge.Cuts") (width 0.1)) (gr_circle (center 43 23) (end 44 23) (layer "Edge.Cuts") (width 0.1)) ;; Silkscreen title (gr_text "Prism-Tap v1.0 — jayis1" (at 22.5 12.5) (layer "F.SilkS") (effects (font (size 1.0 1.0) (thickness 0.15)))) ;; ============== NETS ============== (net 0 "") (net 1 "VCC_3V3") (net 2 "GND") (net 3 "VBUS_5V") (net 4 "VBAT_3.7") (net 10 "FPGA_SPI_SCK") (net 11 "FPGA_SPI_MISO") (net 12 "FPGA_SPI_MOSI") (net 13 "FPGA_CS") (net 14 "FPGA_CRESET") (net 15 "FPGA_CDONE") (net 20 "I2C1_SCL") (net 21 "I2C1_SDA") (net 30 "BLE_UART_TX") (net 31 "BLE_UART_RX") (net 40 "NOR_SPI_SCK") (net 41 "NOR_SPI_MISO") (net 42 "NOR_SPI_MOSI") (net 43 "NOR_CS") (net 50 "SD_SPI_SCK") (net 51 "SD_SPI_MISO") (net 52 "SD_SPI_MOSI") (net 53 "SD_CS") (net 54 "SD_DETECT") (net 60 "USB_DM") (net 61 "USB_DP") (net 70 "CSI_CLKP") (net 71 "CSI_CLKN") (net 72 "CSI_D0P") (net 73 "CSI_D0N") (net 74 "CSI_D1P") (net 75 "CSI_D1N") (net 80 "PAR_D0") (net 81 "PAR_D1") (net 82 "PAR_D2") (net 83 "PAR_D3") (net 84 "PAR_CLK") (net 90 "OLED_SCL") (net 91 "OLED_SDA") (net 100 "LED_STATUS") (net 101 "LED_CAPTURE") (net 102 "LED_INJECT") ;; ============== FOOTPRINTS ============== ;; U1: STM32H730VBT6 (LQFP-48) at center (footprint "Package_QFP:LQFP-48_7x7mm_P0.5mm" (layer "F.Cu") (at 20 12) (property "Reference" "U1" (at 0 -6.5) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "STM32H730VBT6" (at 0 6.5) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "1" smd rect (at -4.25 -2.75) (size 1.5 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "2" smd rect (at -4.25 -2.25) (size 1.5 0.3) (layers "F.Cu" "F.Paste" "F.Mask")) (pad "9" smd rect (at -4.25 1.25) (size 1.5 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "19" smd rect (at -2.25 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask")) (pad "20" smd rect (at -1.75 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask")) (pad "21" smd rect (at -1.25 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 10 "FPGA_SPI_SCK")) (pad "22" smd rect (at -0.75 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 11 "FPGA_SPI_MISO")) (pad "25" smd rect (at 0.75 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 12 "FPGA_SPI_MOSI")) (pad "26" smd rect (at 1.25 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 14 "FPGA_CRESET")) (pad "27" smd rect (at 1.75 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 13 "FPGA_CS")) (pad "28" smd rect (at 2.25 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 20 "I2C1_SCL")) (pad "29" smd rect (at 2.75 -4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 21 "I2C1_SDA")) (pad "30" smd rect (at 4.25 -2.75) (size 1.5 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 30 "BLE_UART_TX")) (pad "31" smd rect (at 4.25 -2.25) (size 1.5 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 31 "BLE_UART_RX")) (pad "33" smd rect (at 4.25 -1.25) (size 1.5 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 60 "USB_DM")) (pad "34" smd rect (at 4.25 -0.75) (size 1.5 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 61 "USB_DP")) (pad "8" smd rect (at -4.25 2.75) (size 1.5 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "23" smd rect (at -4.25 4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "48" smd rect (at 4.25 4.25) (size 0.3 1.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) ) ;; U2: iCE40-UP5K (QFN-48) at right of MCU (footprint "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm" (layer "F.Cu") (at 35 12) (property "Reference" "U2" (at 0 -5) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "iCE40-UP5K-SG48" (at 0 5) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "1" smd rect (at -3.75 -3.5) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "2" smd rect (at -3.25 -3.5) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask") (net 10 "FPGA_SPI_SCK")) (pad "3" smd rect (at -2.75 -3.5) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask") (net 11 "FPGA_SPI_MISO")) (pad "4" smd rect (at -2.25 -3.5) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask") (net 12 "FPGA_SPI_MOSI")) (pad "5" smd rect (at -1.75 -3.5) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask") (net 13 "FPGA_CS")) (pad "6" smd rect (at -1.25 -3.5) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask") (net 14 "FPGA_CRESET")) (pad "7" smd rect (at -0.75 -3.5) (size 0.3 1.0) (layers "F.Cu" "F.Paste" "F.Mask") (net 15 "FPGA_CDONE")) (pad "13" smd rect (at 3.5 -3.75) (size 1.0 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "24" smd rect (at 3.5 3.75) (size 1.0 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "26" smd rect (at 3.5 -2.75) (size 1.0 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 80 "PAR_D0")) (pad "27" smd rect (at 3.5 -2.25) (size 1.0 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 81 "PAR_D1")) (pad "28" smd rect (at 3.5 -1.75) (size 1.0 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 82 "PAR_D2")) (pad "29" smd rect (at 3.5 -1.25) (size 1.0 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 83 "PAR_D3")) (pad "30" smd rect (at 3.5 -0.75) (size 1.0 0.3) (layers "F.Cu" "F.Paste" "F.Mask") (net 84 "PAR_CLK")) (pad "49" smd rect (at 0 0) (size 5.15 5.15) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) ) ;; U3: TC358746XBG (BGA-84) above FPGA (footprint "Package_BGA:Toshiba_BGA-84_7x7mm_P0.4mm" (layer "F.Cu") (at 35 5) (property "Reference" "U3" (at 0 -5) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "TC358746XBG" (at 0 5) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "A1" smd circle (at -3.2 -3.2) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "A2" smd circle (at -2.8 -3.2) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "B1" smd circle (at -3.2 -2.8) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 70 "CSI_CLKP")) (pad "B2" smd circle (at -2.8 -2.8) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 71 "CSI_CLKN")) (pad "C1" smd circle (at -3.2 -2.4) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 72 "CSI_D0P")) (pad "C2" smd circle (at -2.8 -2.4) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 73 "CSI_D0N")) (pad "D1" smd circle (at -3.2 -2.0) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 74 "CSI_D1P")) (pad "D2" smd circle (at -2.8 -2.0) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 75 "CSI_D1N")) (pad "E1" smd circle (at -3.2 -1.6) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 20 "I2C1_SCL")) (pad "E2" smd circle (at -2.8 -1.6) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 21 "I2C1_SDA")) (pad "F1" smd circle (at 2.8 -1.6) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 80 "PAR_D0")) (pad "F2" smd circle (at 3.2 -1.6) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 81 "PAR_D1")) (pad "G1" smd circle (at 2.8 -2.0) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 82 "PAR_D2")) (pad "G2" smd circle (at 3.2 -2.0) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 83 "PAR_D3")) (pad "H1" smd circle (at 2.8 -2.4) (size 0.2 0.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 84 "PAR_CLK")) ) ;; U7: nRF52840-M2 (module) left of MCU (footprint "RF_Module:u-blox_NINA-B3" (layer "F.Cu") (at 8 12) (property "Reference" "U7" (at 0 -5) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "nRF52840-M2" (at 0 5) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "1" smd rect (at -5 -4) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "2" smd rect (at -5 -3) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "3" smd rect (at -5 -2) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 31 "BLE_UART_RX")) (pad "4" smd rect (at -5 -1) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 30 "BLE_UART_TX")) (pad "7" smd rect (at 5 -1) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask")) ) ;; U8: W25Q256 (SOIC-16) bottom left (footprint "Package_SO:SOIC-16W_5.3x10.2mm_P1.27mm" (layer "F.Cu") (at 5 20) (property "Reference" "U8" (at 0 -6) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "W25Q256JVSIQ" (at 0 6) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "1" smd rect (at -4 -4.445) (size 0.6 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (net 43 "NOR_CS")) (pad "2" smd rect (at -4 -3.175) (size 0.6 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (net 42 "NOR_SPI_MOSI")) (pad "5" smd rect (at -4 0.635) (size 0.6 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (net 41 "NOR_SPI_MISO")) (pad "6" smd rect (at -4 1.905) (size 0.6 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (net 40 "NOR_SPI_SCK")) (pad "8" smd rect (at -4 4.445) (size 0.6 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "16" smd rect (at 4 -4.445) (size 0.6 0.55) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) ) ;; U9: SSD1306 OLED (top left) (footprint "Display OLED:OLED_0.96_I2C" (layer "F.Cu") (at 8 5) (property "Reference" "U9" (at 0 -4) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "SSD1306_OLED" (at 0 4) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "1" smd rect (at -3 -2) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "2" smd rect (at -3 0) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "3" smd rect (at -3 2) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 90 "OLED_SCL")) (pad "4" smd rect (at -3 4) (size 1.5 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 91 "OLED_SDA")) ) ;; U10: bq24074 (top right) (footprint "Package_DFN_QFN:VQFN-10-1EP_2.5x2.5mm_P0.5mm" (layer "F.Cu") (at 40 5) (property "Reference" "U10" (at 0 -3) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "bq24074" (at 0 3) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "1" smd rect (at -1.25 -1) (size 0.3 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 3 "VBUS_5V")) (pad "3" smd rect (at -1.25 0) (size 0.3 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "8" smd rect (at 1.25 -1) (size 0.3 0.5) (layers "F.Cu" "F.Paste" "F.Mask") (net 4 "VBAT_3.7")) (pad "11" smd rect (at 0 0) (size 1.7 1.7) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) ) ;; U11: TPS62743 (bottom right) (footprint "Package_BGA:DSBGA-6_1.5x1.5mm_P0.5mm" (layer "F.Cu") (at 40 20) (property "Reference" "U11" (at 0 -3) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "TPS62743" (at 0 3) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "A1" smd circle (at -0.5 -0.25) (size 0.25 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (net 4 "VBAT_3.7")) (pad "B1" smd circle (at -0.5 0.25) (size 0.25 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "C1" smd circle (at 0.5 -0.25) (size 0.25 0.25) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "A2" smd circle (at 0 0.25) (size 0.25 0.25) (layers "F.Cu" "F.Paste" "F.Mask")) ) ;; J1: USB-C connector (bottom left) (footprint "Connector_USB:USB_C_Receptacle_HRO_TYPE-C-31-M-12" (layer "F.Cu") (at 3 22) (property "Reference" "J1" (at 0 -3) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "USB_C_16P" (at 0 3) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "A1" smd rect (at -3 -1.5) (size 0.3 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "A4" smd rect (at -2 -1.5) (size 0.3 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 3 "VBUS_5V")) (pad "A6" smd rect (at 1 -1.5) (size 0.3 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 61 "USB_DP")) (pad "B7" smd rect (at 2 -1.5) (size 0.3 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 60 "USB_DM")) (pad "B12" smd rect (at 3 -1.5) (size 0.3 0.8) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) ) ;; J2: MicroSD slot (bottom right) (footprint "Connector_Card:microSD_HC_Hirose_DM3D-SF" (layer "F.Cu") (at 38 22) (property "Reference" "J2" (at 0 -3) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "MicroSD" (at 0 3) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "2" smd rect (at -3 -1) (size 0.6 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 53 "SD_CS")) (pad "3" smd rect (at -2 -1) (size 0.6 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 52 "SD_SPI_MOSI")) (pad "4" smd rect (at -1 -1) (size 0.6 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "5" smd rect (at 0 -1) (size 0.6 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 50 "SD_SPI_SCK")) (pad "6" smd rect (at 1 -1) (size 0.6 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "7" smd rect (at 2 -1) (size 0.6 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 51 "SD_SPI_MISO")) ) ;; J3: MIPI CSI-2 input FPC (bottom center) (footprint "Connector_FFC-FPC:FPC_0.5mm_22P" (layer "F.Cu") (at 20 22) (property "Reference" "J3" (at 0 -3) (layer "F.SilkS") (effects (font (size 1 1) (thickness 0.15)))) (property "Value" "FPC_22P_0.5mm" (at 0 3) (layer "F.Fab") (effects (font (size 1 1) (thickness 0.15)))) (pad "1" smd rect (at -5 -1) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "VCC_3V3")) (pad "2" smd rect (at -4.5 -1) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 2 "GND")) (pad "3" smd rect (at -4 -1) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 70 "CSI_CLKP")) (pad "4" smd rect (at -3.5 -1) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 71 "CSI_CLKN")) (pad "5" smd rect (at -3 -1) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 72 "CSI_D0P")) (pad "6" smd rect (at -2.5 -1) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 73 "CSI_D0N")) (pad "7" smd rect (at -2 -1) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 74 "CSI_D1P")) (pad "8" smd rect (at -1.5 -1) (size 0.3 1.2) (layers "F.Cu" "F.Paste" "F.Mask") (net 75 "CSI_D1N")) ) ;; ============== ZONES ============== ;; GND pour on In1.Cu (internal ground plane) (zone (net 2) (net_name "GND") (layer "In1.Cu") (hatch edge 0.5) (connect_pads (clearance 0.2)) (min_thickness 0.15) (fill yes (thermal_gap 0.2) (thermal_bridge_width 0.3)) (polygon (pts (xy 0.5 0.5) (xy 44.5 0.5) (xy 44.5 24.5) (xy 0.5 24.5)) ) ) ;; PWR pour on In2.Cu (internal power plane for VCC_3V3) (zone (net 1) (net_name "VCC_3V3") (layer "In2.Cu") (hatch edge 0.5) (connect_pads (clearance 0.2)) (min_thickness 0.15) (fill yes (thermal_gap 0.2) (thermal_bridge_width 0.3)) (polygon (pts (xy 0.5 0.5) (xy 44.5 0.5) (xy 44.5 24.5) (xy 0.5 24.5)) ) ) ;; ============== TRACKS (representative routing) ============== ;; FPGA SPI bus (MCU pins 21-25 to FPGA pins 2-4) (segment (start 18.75 7.75) (end 31.75 8.5) (width 0.15) (layer "F.Cu") (net 10)) (segment (start 19.25 7.75) (end 32.25 8.5) (width 0.15) (layer "F.Cu") (net 11)) (segment (start 20.75 7.75) (end 32.75 8.5) (width 0.15) (layer "F.Cu") (net 12)) (segment (start 21.25 7.75) (end 33.25 8.5) (width 0.15) (layer "F.Cu") (net 13)) (segment (start 21.75 7.75) (end 33.75 8.5) (width 0.15) (layer "F.Cu") (net 14)) ;; I2C1 bus (MCU pins 28-29 to bridge E1/E2) (segment (start 22.25 7.75) (end 31.8 3.4) (width 0.15) (layer "F.Cu") (net 20)) (segment (start 22.75 7.75) (end 32.2 3.4) (width 0.15) (layer "F.Cu") (net 21)) ;; UART4 (MCU pins 30-31 to BLE pins 4-3) (segment (start 24.25 9.25) (end 13 11) (width 0.15) (layer "F.Cu") (net 30)) (segment (start 24.25 9.75) (end 13 10) (width 0.15) (layer "F.Cu") (net 31)) ;; USB (MCU pins 33-34 to USB-C) (segment (start 24.25 10.75) (end 4 20.5) (width 0.15) (layer "F.Cu") (net 60)) (segment (start 24.25 11.25) (end 4 20.5) (width 0.15) (layer "F.Cu") (net 61)) ;; VBUS from USB-C to charger (segment (start 1 20.5) (end 38.75 4) (width 0.3) (layer "In2.Cu") (net 3)) ;; VBAT from charger to regulator (segment (start 41.25 4) (end 39.5 19.75) (width 0.3) (layer "In2.Cu") (net 4)) ;; VCC_3V3 from regulator to MCU (segment (start 40.5 19.75) (end 24.25 16) (width 0.3) (layer "In2.Cu") (net 1)) ;; Parallel bus (bridge to FPGA) (segment (start 37.8 3.4) (end 38.5 9.25) (width 0.15) (layer "F.Cu") (net 80)) (segment (start 38.2 3.4) (end 38.5 9.75) (width 0.15) (layer "F.Cu") (net 81)) (segment (start 37.8 3.0) (end 38.5 10.25) (width 0.15) (layer "F.Cu") (net 82)) (segment (start 38.2 3.0) (end 38.5 10.75) (width 0.15) (layer "F.Cu") (net 83)) (segment (start 37.8 2.6) (end 38.5 11.25) (width 0.15) (layer "F.Cu") (net 84)) ;; CSI-2 lanes (FPC to bridge) (segment (start 16 21) (end 31.8 2.2) (width 0.1) (layer "F.Cu") (net 70)) (segment (start 16.5 21) (end 32.2 2.2) (width 0.1) (layer "F.Cu") (net 71)) (segment (start 17 21) (end 31.8 2.6) (width 0.1) (layer "F.Cu") (net 72)) (segment (start 17.5 21) (end 32.2 2.6) (width 0.1) (layer "F.Cu") (net 73)) (segment (start 18 21) (end 31.8 3.0) (width 0.1) (layer "F.Cu") (net 74)) (segment (start 18.5 21) (end 32.2 3.0) (width 0.1) (layer "F.Cu") (net 75)) ;; SPI1 to NOR flash (segment (start 15.75 9.25) (end 1 15.555) (width 0.15) (layer "F.Cu") (net 40)) (segment (start 15.75 9.75) (end 1 20.635) (width 0.15) (layer "F.Cu") (net 41)) (segment (start 15.75 10.25) (end 1 16.825) (width 0.15) (layer "F.Cu") (net 42)) (segment (start 15.75 7.25) (end 1 15.555) (width 0.15) (layer "F.Cu") (net 43)) ;; SD card SPI (MCU to microSD) (segment (start 24.25 7.25) (end 35 21) (width 0.15) (layer "F.Cu") (net 50)) (segment (start 24.25 7.75) (end 36 21) (width 0.15) (layer "F.Cu") (net 51)) (segment (start 24.25 8.25) (end 37 21) (width 0.15) (layer "F.Cu") (net 52)) (segment (start 15.75 14.75) (end 35 21) (width 0.15) (layer "F.Cu") (net 53)) ;; LEDs (MCU to LED pads — would have LED components) (segment (start 15.75 4.75) (end 12 3) (width 0.15) (layer "F.Cu") (net 100)) (segment (start 15.75 5.25) (end 12 4) (width 0.15) (layer "F.Cu") (net 101)) ;; ============== DIMENSION TEXT ============== (gr_text "45mm x 25mm" (at 22.5 1.5) (layer "Cmts.User") (effects (font (size 0.8 0.8) (thickness 0.1)))) (gr_text "4-layer 1.2mm" (at 22.5 23.5) (layer "Cmts.User") (effects (font (size 0.8 0.8) (thickness 0.1)))) ) ;; End of PCB ;; Author: jayis1