(kicad_pcb (version 20240108) (generator "kicad-pcb-tools") (generator_version "7.0") (general (thickness 1.0) (legacy_teardrops no) ) (paper "A4") (title_block (title "Pulse-Reaper — TDR-Guided Non-Invasive Covert Tap for Twisted-Pair Copper Cables") (date "2026-08-17") (rev "1.0") (company "jayis1") (comment 1 "Author: jayis1") (comment 2 "License: CERN-OHL-S v2") (comment 3 "95x52mm, 8-layer, isolated clamp AFE + digital domain") ) (layers (0 "F.Cu" signal) (1 "In1.Cu" signal "GND") (2 "In2.Cu" signal "PWR") (3 "In3.Cu" signal "AGND") (4 "In4.Cu" signal "ISO_GND2") (5 "In5.Cu" signal "ISO_VCC2") (6 "In6.Cu" signal "SHIELD") (31 "B.Cu" signal) (32 "B.Adhes" user "B.Adhesive") (33 "F.Adhes" user "F.Adhesive") (34 "B.Paste" user) (35 "F.Paste" user) (36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen") (38 "B.Mask" user) (39 "F.Mask" user) (40 "Dwgs.User" user "User.Drawings") (41 "Cmts.User" user "User.Comments") (42 "Eco1.User" user "User.Eco1") (43 "Eco2.User" user "User.Eco2") (44 "Edge.Cuts" user) (45 "Margin" user) ) (setup (pad_to_mask_clearance 0.05) (aux_axis_origin 0 0) (grid_origin 0 0) (pcbplotparams (layerselection 0x00010fc_ffffffff) (plot_on_all_layers_selection 0x0000000_00000000) (disableapertmacros no) (usegerberextensions no) (usegerberattributes yes) (usegerberadvancedattributes yes) (creategerberjobfile yes) (dashed_line_dash_ratio 12.000000) (dashed_line_gap_ratio 12.000000) (svgprecision 4) (plotframeref no) (viasonmask no) (mode 1) (useauxorigin no) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) (pdf_front_fp_property_popups yes) (pdf_back_fp_property_popups yes) (dxfpolygonmode yes) (dxfimperialunits no) (dxfusepcbnewfont yes) (psnegative no) (psa4output no) (plotreference yes) (plotvalue no) (plotfptext yes) (plotinvisibletext no) (sketchpadsonfab no) (subtractmaskfromsilk no) (outputformat 1) (mirror no) (drillshape 0) (scaleselection 1) (outputdirectory "gerbers/") ) ) (net 0 "") (net 1 "GND") (net 2 "VDD_3V3") (net 3 "VBAT") (net 4 "VBUS") (net 5 "AGND") (net 6 "ISO_GND1") (net 7 "ISO_GND2") (net 8 "ISO_VCC2") (net 9 "VDD_1V2") (net 10 "SHIELD") (net 11 "FPGA_SPI_SCK") (net 12 "FPGA_SPI_MISO") (net 13 "FPGA_SPI_MOSI") (net 14 "FPGA_SPI_CS") (net 15 "FPGA_IRQ") (net 16 "FPGA_CDONE") (net 17 "FPGA_CRESET") (net 18 "BLE_TX") (net 19 "BLE_RX") (net 20 "BLE_CTS") (net 21 "BLE_RTS") (net 22 "BLE_RESET") (net 23 "OLED_SCL") (net 24 "OLED_SDA") (net 25 "NOR_CS") (net 26 "NOR_SCK") (net 27 "NOR_MISO") (net 28 "NOR_MOSI") (net 29 "SD_CLK") (net 30 "SD_CMD") (net 31 "SD_D0") (net 32 "SD_D1") (net 33 "SD_D2") (net 34 "SD_D3") (net 35 "SD_CD") (net 36 "USB_DM") (net 37 "USB_DP") (net 38 "USB_VBUS") (net 39 "CLAMP_CAP_P") (net 40 "CLAMP_CAP_N") (net 41 "CLAMP_IND_P") (net 42 "CLAMP_IND_N") (net 43 "CLAMP_TDR") (net 44 "CLAMP_JAW") (net 45 "AFE_GAIN0") (net 46 "AFE_GAIN1") (net 46 "AFE_OUT_P") (net 47 "AFE_OUT_N") (net 48 "ADC_D0") (net 49 "ADC_D1") (net 50 "ADC_D2") (net 51 "ADC_D3") (net 52 "ADC_D4") (net 53 "ADC_D5") (net 54 "ADC_D6") (net 55 "ADC_D7") (net 56 "ADC_D8") (net 57 "ADC_D9") (net 58 "ADC_CLK") (net 59 "TDR_PULSE") (net 60 "I2C_PM_SCL") (net 61 "I2C_PM_SDA") (net 62 "BTN_MODE") (net 63 "BTN_ACTION") (net 64 "LED_R") (net 65 "LED_G") (net_class "Default" "Default net class" (clearance 0.15) (trace_width 0.18) (via_dia 0.6) (via_drill 0.3) (uvia_dia 0.2) (uvia_drill 0.1) (add_net "") (add_net "GND") (add_net "VDD_3V3") (add_net "VBAT") (add_net "VBUS") (add_net "AGND") (add_net "ISO_GND1") (add_net "ISO_GND2") (add_net "ISO_VCC2") (add_net "VDD_1V2") (add_net "SHIELD") (add_net "FPGA_SPI_SCK") (add_net "FPGA_SPI_MISO") (add_net "FPGA_SPI_MOSI") (add_net "FPGA_SPI_CS") (add_net "FPGA_IRQ") (add_net "FPGA_CDONE") (add_net "FPGA_CRESET") (add_net "BLE_TX") (add_net "BLE_RX") (add_net "BLE_CTS") (add_net "BLE_RTS") (add_net "BLE_RESET") (add_net "OLED_SCL") (add_net "OLED_SDA") (add_net "NOR_CS") (add_net "NOR_SCK") (add_net "NOR_MISO") (add_net "NOR_MOSI") (add_net "SD_CLK") (add_net "SD_CMD") (add_net "SD_D0") (add_net "SD_D1") (add_net "SD_D2") (add_net "SD_D3") (add_net "SD_CD") (add_net "USB_DM") (add_net "USB_DP") (add_net "USB_VBUS") (add_net "CLAMP_CAP_P") (add_net "CLAMP_CAP_N") (add_net "CLAMP_IND_P") (add_net "CLAMP_IND_N") (add_net "CLAMP_TDR") (add_net "CLAMP_JAW") (add_net "AFE_GAIN0") (add_net "AFE_GAIN1") (add_net "AFE_OUT_P") (add_net "AFE_OUT_N") (add_net "ADC_D0") (add_net "ADC_D1") (add_net "ADC_D2") (add_net "ADC_D3") (add_net "ADC_D4") (add_net "ADC_D5") (add_net "ADC_D6") (add_net "ADC_D7") (add_net "ADC_D8") (add_net "ADC_D9") (add_net "ADC_CLK") (add_net "TDR_PULSE") (add_net "I2C_PM_SCL") (add_net "I2C_PM_SDA") (add_net "BTN_MODE") (add_net "BTN_ACTION") (add_net "LED_R") (add_net "LED_G") ) (net_class "PWR" "Power nets — 0.4mm trace" (clearance 0.2) (trace_width 0.4) (via_dia 0.8) (via_drill 0.4) (add_net "VBUS") (add_net "VBAT") (add_net "VDD_3V3") (add_net "VDD_1V2") (add_net "ISO_VCC2") ) (net_class "RF" "TDR pulse / high-speed ADC bus — 50 ohm" (clearance 0.18) (trace_width 0.25) (via_dia 0.6) (via_drill 0.3) (add_net "TDR_PULSE") (add_net "ADC_CLK") (add_net "AFE_OUT_P") (add_net "AFE_OUT_N") (add_net "CLAMP_CAP_P") (add_net "CLAMP_CAP_N") (add_net "CLAMP_TDR") ) ; ============================================================ ; BOARD OUTLINE (95 x 52 mm) ; ============================================================ (gr_line (start 0 0) (end 95 0) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 95 0) (end 95 52) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 95 52) (end 0 52) (layer "Edge.Cuts") (width 0.1)) (gr_line (start 0 52) (end 0 0) (layer "Edge.Cuts") (width 0.1)) ; ============================================================ ; FOOTPRINTS (key components) ; ============================================================ ; U1: STM32H743VIT6 (LQFP-100) at (47.5, 30) center of board (footprint "Package_QFP:LQFP-100_14x14mm_P0.5mm" (layer "F.Cu") (at 47.5 30) (property "Reference" "U1" (at 0 -9 0) (layer "F.SilkS")) (property "Value" "STM32H743VIT6" (at 0 9 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole rect (at -6.5 -7.75) (size 0.3 1.5) (drill 0.2) (layers *.cu *.mask) (net 2 "VDD_3V3")) (pad 11 thru_hole circle (at -6.5 -2.75) (size 0.3 1.5) (drill 0.2) (layers *.cu *.mask) (net 11 "FPGA_SPI_SCK")) (pad 12 thru_hole circle (at -6.5 -2.25) (size 0.3 1.5) (drill 0.2) (layers *.cu *.mask) (net 12 "FPGA_SPI_MISO")) (pad 14 thru_hole circle (at -6.5 -1.25) (size 0.3 1.5) (drill 0.2) (layers *.cu *.mask) (net 13 "FPGA_SPI_MOSI")) (pad 15 thru_hole circle (at -6.5 -0.75) (size 0.3 1.5) (drill 0.2) (layers *.cu *.mask) (net 14 "FPGA_SPI_CS")) (pad 103 thru_hole circle (at -4.75 -7.75) (size 0.3 1.5) (drill 0.2) (layers *.cu *.mask) (net 1 "GND")) (pad 21 thru_hole circle (at -6.5 1.25) (size 0.3 1.5) (drill 0.2) (layers *.cu *.mask) (net 18 "BLE_TX")) (pad 22 thru_hole circle (at -6.5 1.75) (size 0.3 1.5) (drill 0.2) (layers *.cu *.mask) (net 19 "BLE_RX")) ) ; U2: iCE40UP5K-SG48 (QFN-48) at (75, 20) (footprint "Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm" (layer "F.Cu") (at 75 20) (property "Reference" "U2" (at 0 -5.5 0) (layer "F.SilkS")) (property "Value" "iCE40UP5K-SG48" (at 0 5.5 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole circle (at -3.25 -3) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 9 "VDD_1V2")) (pad 25 thru_hole circle (at 3.25 3) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 1 "GND")) (pad 26 thru_hole circle (at 3.25 2.5) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 11 "FPGA_SPI_SCK")) (pad 27 thru_hole circle (at 3.25 2.0) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 13 "FPGA_SPI_MOSI")) (pad 28 thru_hole circle (at 3.25 1.5) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 12 "FPGA_SPI_MISO")) (pad 29 thru_hole circle (at 3.25 1.0) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 14 "FPGA_SPI_CS")) (pad 30 thru_hole circle (at 3.25 0.5) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 15 "FPGA_IRQ")) (pad 31 thru_hole circle (at 3.25 0.0) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 16 "FPGA_CDONE")) (pad 32 thru_hole circle (at 3.25 -0.5) (size 0.3 1.0) (drill 0.2) (layers *.cu *.mask) (net 17 "FPGA_CRESET")) ) ; U3: AD9203ARZ (TSSOP-28) at (75, 40) (footprint "Package_SO:TSSOP-28_4.4x9.7mm_P0.65mm" (layer "F.Cu") (at 75 40) (property "Reference" "U3" (at 0 -6 0) (layer "F.SilkS")) (property "Value" "AD9203ARZ" (at 0 6 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole rect (at -2.9 -4.875) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 5 "AGND")) (pad 2 thru_hole circle (at -2.9 -4.225) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 48 "ADC_D0")) (pad 3 thru_hole circle (at -2.9 -3.575) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 49 "ADC_D1")) (pad 10 thru_hole circle (at -2.9 -0.975) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 50 "ADC_D2")) (pad 11 thru_hole circle (at -2.9 -0.325) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 51 "ADC_D3")) ) ; U4: LMH5401IRM (VSSOP-8) at (20, 40) — on isolated side (footprint "Package_SO:VSSOP-8_3.0x3.0mm_P0.65mm" (layer "F.Cu") (at 20 40) (property "Reference" "U4" (at 0 -3.5 0) (layer "F.SilkS")) (property "Value" "LMH5401IRM" (at 0 3.5 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole rect (at -1.0 -1.5) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 8 "ISO_VCC2")) (pad 4 thru_hole circle (at -1.0 0.5) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 7 "ISO_GND2")) (pad 5 thru_hole circle (at 1.0 1.0) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 39 "CLAMP_CAP_P")) (pad 6 thru_hole circle (at 1.0 0.5) (size 0.4 1.0) (drill 0.2) (layers *.cu *.mask) (net 40 "CLAMP_CAP_N")) ) ; U5: ISO7741DW (SOIC-16W) at (40, 40) — isolation barrier (footprint "Package_SO:SOIC-16W_5.3x10.2mm_P1.27mm" (layer "F.Cu") (at 40 40) (property "Reference" "U5" (at 0 -6.5 0) (layer "F.SilkS")) (property "Value" "ISO7741DW" (at 0 6.5 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole rect (at -2.3 -4.445) (size 0.6 1.2) (drill 0.3) (layers *.cu *.mask) (net 2 "VDD_3V3")) (pad 2 thru_hole circle (at -2.3 -3.175) (size 0.6 1.2) (drill 0.3) (layers *.cu *.mask) (net 1 "GND")) (pad 7 thru_hole circle (at -2.3 3.175) (size 0.6 1.2) (drill 0.3) (layers *.cu *.mask) (net 45 "AFE_GAIN0")) (pad 8 thru_hole circle (at -2.3 4.445) (size 0.6 1.2) (drill 0.3) (layers *.cu *.mask) (net 46 "AFE_GAIN1")) (pad 9 thru_hole circle (at 2.3 4.445) (size 0.6 1.2) (drill 0.3) (layers *.cu *.mask) (net 8 "ISO_VCC2")) (pad 10 thru_hole circle (at 2.3 3.175) (size 0.6 1.2) (drill 0.3) (layers *.cu *.mask) (net 7 "ISO_GND2")) ) ; U6: nRF52840-M2 (NINA-B306) at (80, 45) (footprint "RF_Module:NINA-B3X" (layer "F.Cu") (at 80 45) (property "Reference" "U6" (at 0 -7 0) (layer "F.SilkS")) (property "Value" "NINA-B306" (at 0 7 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole rect (at -5 -3) (size 0.5 1.0) (drill 0.2) (layers *.cu *.mask) (net 2 "VDD_3V3")) (pad 2 thru_hole circle (at -5 -2) (size 0.5 1.0) (drill 0.2) (layers *.cu *.mask) (net 1 "GND")) (pad 3 thru_hole circle (at -5 -1) (size 0.5 1.0) (drill 0.2) (layers *.cu *.mask) (net 18 "BLE_TX")) (pad 4 thru_hole circle (at -5 0) (size 0.5 1.0) (drill 0.2) (layers *.cu *.mask) (net 19 "BLE_RX")) (pad 5 thru_hole circle (at -5 1) (size 0.5 1.0) (drill 0.2) (layers *.cu *.mask) (net 20 "BLE_CTS")) (pad 6 thru_hole circle (at -5 2) (size 0.5 1.0) (drill 0.2) (layers *.cu *.mask) (net 21 "BLE_RTS")) ) ; J1: USB-C 2.0 at (10, 5) (footprint "Connector_USB:USB_C_Receptacle_GCT_USB4105" (layer "F.Cu") (at 10 5) (property "Reference" "J1" (at 0 -5 0) (layer "F.SilkS")) (property "Value" "USB-C 2.0" (at 0 5 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad A1 thru_hole rect (at -4 -3) (size 0.8 1.5) (drill 0.4) (layers *.cu *.mask) (net 1 "GND")) (pad A4 thru_hole circle (at -3 -3) (size 0.8 1.5) (drill 0.4) (layers *.cu *.mask) (net 4 "VBUS")) (pad A6 thru_hole circle (at -1 -3) (size 0.8 1.5) (drill 0.4) (layers *.cu *.mask) (net 37 "USB_DP")) (pad A7 thru_hole circle (at 0 -3) (size 0.8 1.5) (drill 0.4) (layers *.cu *.mask) (net 36 "USB_DM")) ) ; J2: MicroSD at (90, 8) (footprint "Connector_Card:microSD_HC_Hinge" (layer "F.Cu") (at 90 8) (property "Reference" "J2" (at 0 -5 0) (layer "F.SilkS")) (property "Value" "MicroSD UHS-I" (at 0 5 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole rect (at -3 -2) (size 0.5 1.0) (drill 0.3) (layers *.cu *.mask) (net 34 "SD_D3")) (pad 2 thru_hole circle (at -3 -1) (size 0.5 1.0) (drill 0.3) (layers *.cu *.mask) (net 33 "SD_D2")) (pad 3 thru_hole circle (at -3 0) (size 0.5 1.0) (drill 0.3) (layers *.cu *.mask) (net 29 "SD_CLK")) (pad 4 thru_hole circle (at -3 1) (size 0.5 1.0) (drill 0.3) (layers *.cu *.mask) (net 2 "VDD_3V3")) ) ; J3: Clamp header (6-pin 2.54mm) at (5, 40) (footprint "Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical" (layer "F.Cu") (at 5 40) (property "Reference" "J3" (at 0 -4 0) (layer "F.SilkS")) (property "Value" "Clamp (off-board)" (at 0 8 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole rect (at 0 -6.35) (size 1.6 1.6) (drill 0.9) (layers *.cu *.mask) (net 39 "CLAMP_CAP_P")) (pad 2 thru_hole circle (at 0 -3.81) (size 1.6 1.6) (drill 0.9) (layers *.cu *.mask) (net 40 "CLAMP_CAP_N")) (pad 3 thru_hole circle (at 0 -1.27) (size 1.6 1.6) (drill 0.9) (layers *.cu *.mask) (net 41 "CLAMP_IND_P")) (pad 4 thru_hole circle (at 0 1.27) (size 1.6 1.6) (drill 0.9) (layers *.cu *.mask) (net 42 "CLAMP_IND_N")) (pad 5 thru_hole circle (at 0 3.81) (size 1.6 1.6) (drill 0.9) (layers *.cu *.mask) (net 43 "CLAMP_TDR")) (pad 6 thru_hole circle (at 0 6.35) (size 1.6 1.6) (drill 0.9) (layers *.cu *.mask) (net 44 "CLAMP_JAW")) ) ; SW1: Mode button at (88, 30) (footprint "Button_Switch_SMD:SW_SPST_B3SN_6.0x6.0mm" (layer "F.Cu") (at 88 30) (property "Reference" "SW1" (at 0 -4 0) (layer "F.SilkS")) (property "Value" "MODE" (at 0 4 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole circle (at -3 0) (size 1.5 1.5) (drill 0.7) (layers *.cu *.mask) (net 62 "BTN_MODE")) (pad 2 thru_hole circle (at 3 0) (size 1.5 1.5) (drill 0.7) (layers *.cu *.mask) (net 1 "GND")) ) ; D1: Status LED at (88, 42) (footprint "LED_SMD:LED_RGB_1210" (layer "F.Cu") (at 88 42) (property "Reference" "D1" (at 0 -3 0) (layer "F.SilkS")) (property "Value" "LED_RG" (at 0 3 0) (layer "F.Fab")) (property "Author" "jayis1" (at 0 0 0) (layer "Cmts.User")) (pad 1 thru_hole circle (at -1.5 0) (size 1.0 1.0) (drill 0.5) (layers *.cu *.mask) (net 64 "LED_R")) (pad 2 thru_hole circle (at 0 0) (size 1.0 1.0) (drill 0.5) (layers *.cu *.mask) (net 65 "LED_G")) (pad 3 thru_hole circle (at 1.5 0) (size 1.0 1.0) (drill 0.5) (layers *.cu *.mask) (net 1 "GND")) ) ; ============================================================ ; KEY TRACKS (representative subset) ; ============================================================ (segment (start 41 27.25) (end 71.75 20) (width 0.18) (layer "F.Cu") (net 11 "FPGA_SPI_SCK")) (segment (start 41 27.75) (end 71.75 20.5) (width 0.18) (layer "F.Cu") (net 12 "FPGA_SPI_MISO")) (segment (start 41 29.25) (end 71.75 21) (width 0.18) (layer "F.Cu") (net 13 "FPGA_SPI_MOSI")) (segment (start 41 29.75) (end 71.75 21.5) (width 0.18) (layer "F.Cu") (net 14 "FPGA_SPI_CS")) (segment (start 30 37) (end 40 37) (width 0.25) (layer "F.Cu") (net 39 "CLAMP_CAP_P")) (segment (start 30 40) (end 40 40) (width 0.25) (layer "F.Cu") (net 40 "CLAMP_CAP_N")) (segment (start 5 44) (end 38 44) (width 0.25) (layer "F.Cu") (net 43 "CLAMP_TDR")) (segment (start 47.5 31) (end 75 45) (width 0.18) (layer "F.Cu") (net 18 "BLE_TX")) (segment (start 47.5 31.5) (end 75 45) (width 0.18) (layer "F.Cu") (net 19 "BLE_RX")) ; ============================================================ ; VIAS (representative subset for layer transitions) ; ============================================================ (via (at 30 10) (size 0.6) (drill 0.3) (layers "F.Cu" "In1.Cu") (net 1 "GND")) (via (at 50 10) (size 0.6) (drill 0.3) (layers "F.Cu" "In2.Cu") (net 2 "VDD_3V3")) (via (at 80 10) (size 0.8) (drill 0.4) (layers "F.Cu" "In2.Cu") (net 4 "VBUS")) ; ============================================================ ; ZONES (copper pours) ; ============================================================ (zone (layer "F.Cu") (net 1 "GND") (polygon (pts (xy 0 0) (xy 95 0) (xy 95 52) (xy 0 52))) ) (zone (layer "B.Cu") (net 1 "GND") (polygon (pts (xy 0 0) (xy 95 0) (xy 95 52) (xy 0 52))) ) ; ============================================================ ; SILKSCREEN NOTES ; ============================================================ (gr_text "Pulse-Reaper v1.0" (at 47.5 3) (layer "F.SilkS") (size 1.5)) (gr_text "(c) jayis1 2026" (at 47.5 49) (layer "F.SilkS") (size 1.2)) (gr_text "ISOLATION BARRIER 5kV" (at 40 33) (layer "F.SilkS") (size 0.8)) )