(kicad_pcb (version 20210824) (generator pcbnew) (general (thickness 1.6) ) (paper "A4") (title_block (title "Tedium X8") (date "03/13/2020") (rev "20200313") (company "ShareBrained Technology, Inc.") (comment 1 "Copyright (C) 2020 Jared Boone") (comment 2 "Licensed under CERN-OHL-P v2") ) (layers (0 "F.Cu" signal) (1 "In1.Cu" signal) (2 "In2.Cu" signal) (31 "B.Cu" signal) (32 "B.Adhes" user "B.Adhesive") (33 "F.Adhes" user "F.Adhesive") (34 "B.Paste" user) (35 "F.Paste" user) (36 "B.SilkS" user "B.Silkscreen") (37 "F.SilkS" user "F.Silkscreen") (38 "B.Mask" user) (39 "F.Mask" user) (40 "Dwgs.User" user "User.Drawings") (41 "Cmts.User" user "User.Comments") (42 "Eco1.User" user "User.Eco1") (43 "Eco2.User" user "User.Eco2") (44 "Edge.Cuts" user) (45 "Margin" user) (46 "B.CrtYd" user "B.Courtyard") (47 "F.CrtYd" user "F.Courtyard") (48 "B.Fab" user) (49 "F.Fab" user) ) (setup (pad_to_mask_clearance 0.0508) (solder_mask_min_width 0.1016) (pcbplotparams (layerselection 0x00010fc_ffffffff) (disableapertmacros false) (usegerberextensions true) (usegerberattributes false) (usegerberadvancedattributes false) (creategerberjobfile false) (svguseinch false) (svgprecision 6) (excludeedgelayer true) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) (dxfpolygonmode true) (dxfimperialunits true) (dxfusepcbnewfont true) (psnegative false) (psa4output false) (plotreference true) (plotvalue false) (plotinvisibletext false) (sketchpadsonfab false) (subtractmaskfromsilk true) (outputformat 1) (mirror false) (drillshape 0) (scaleselection 1) (outputdirectory "gerber") ) ) (net 0 "") (net 1 "GND") (net 2 "/fpga_cfg/DONE") (net 3 "/fpga_cfg/TCK") (net 4 "/fpga_cfg/MOSI") (net 5 "/fpga_cfg/MISO") (net 6 "/fpga_cfg/TDO") (net 7 "/fpga_cfg/TDI") (net 8 "/fpga_cfg/TMS") (net 9 "Net-(R52-Pad1)") (net 10 "/framer/RTIP0") (net 11 "/framer/RRING0") (net 12 "/framer/TTIP0") (net 13 "/framer/TRING0") (net 14 "/framer/RTIP1") (net 15 "/framer/RRING1") (net 16 "/framer/TTIP1") (net 17 "/framer/TRING1") (net 18 "/framer/RTIP2") (net 19 "/framer/RRING2") (net 20 "/framer/TTIP2") (net 21 "/framer/TRING2") (net 22 "/framer/RTIP3") (net 23 "/framer/RRING3") (net 24 "/framer/TTIP3") (net 25 "/framer/TRING3") (net 26 "/framer/RTIP4") (net 27 "/framer/RRING4") (net 28 "/framer/TTIP4") (net 29 "/framer/TRING4") (net 30 "/framer/RTIP5") (net 31 "/framer/RRING5") (net 32 "/framer/TTIP5") (net 33 "/framer/TRING5") (net 34 "/framer/RTIP6") (net 35 "/framer/RRING6") (net 36 "/framer/TTIP6") (net 37 "/framer/TRING6") (net 38 "/framer/RTIP7") (net 39 "/framer/RRING7") (net 40 "/framer/TTIP7") (net 41 "/framer/TRING7") (net 42 "/framer/TDO") (net 43 "/framer/TDI") (net 44 "Net-(R16-Pad2)") (net 45 "Net-(R17-Pad2)") (net 46 "/framer/TMS") (net 47 "/framer/TCK") (net 48 "Net-(R54-Pad1)") (net 49 "/fpga_bank/WR#") (net 50 "/fpga_bank/RD#") (net 51 "/fpga_bank/CS#") (net 52 "/fpga_bank/E1OSCCLK") (net 53 "/fpga_bank/T1OSCCLK") (net 54 "/fpga_bank/FRM_RESET#") (net 55 "/fpga_bank/CLKREF") (net 56 "/fpga_bank/REQ1#") (net 57 "/fpga_bank/REQ0#") (net 58 "/fpga_bank/PCLK") (net 59 "/fpga_bank/RDY#") (net 60 "/fpga_bank/ALE") (net 61 "/fpga_bank/ACK0#") (net 62 "/fpga_bank/ACK1#") (net 63 "/fpga_bank/INT#") (net 64 "/fpga_bank/MCLKIN") (net 65 "Net-(D1-PadA)") (net 66 "Net-(D2-PadA)") (net 67 "/power/VCCAUX") (net 68 "/fpga_bank/D3") (net 69 "/fpga_bank/A11") (net 70 "/fpga_bank/A13") (net 71 "/fpga_bank/A12") (net 72 "/fpga_bank/TXSERCLK3") (net 73 "/fpga_bank/TXSER3") (net 74 "/fpga_bank/RXSERCLK3") (net 75 "/fpga_bank/TXSYNC3") (net 76 "/fpga_bank/RXSER3") (net 77 "/fpga_bank/TXMSYNC2") (net 78 "/fpga_bank/RXSYNC3") (net 79 "/fpga_bank/RXSCLK2") (net 80 "/fpga_bank/TXSERCLK2") (net 81 "/fpga_bank/TXSYNC2") (net 82 "/fpga_bank/RXSER2") (net 83 "/fpga_bank/TXSERCLK1") (net 84 "/fpga_bank/TXSYNC1") (net 85 "/fpga_bank/RXSYNC2") (net 86 "/fpga_bank/TXMSYNC1") (net 87 "/fpga_bank/RXSCLK0") (net 88 "/fpga_bank/RXSER1") (net 89 "/fpga_bank/RXSYNC1") (net 90 "/fpga_bank/RXCRCSYNC0") (net 91 "/fpga_bank/RXSERCLK0") (net 92 "/fpga_bank/RXSYNC0") (net 93 "/fpga_bank/RXSER0") (net 94 "/fpga_bank/RXCASYNC0") (net 95 "/fpga_bank/RXSERCLK1") (net 96 "/fpga_bank/A7") (net 97 "/fpga_bank/A2") (net 98 "/fpga_bank/A5") (net 99 "/fpga_bank/RXSER4") (net 100 "/fpga_bank/RXCRCSYNC4") (net 101 "/fpga_bank/RXSCLK4") (net 102 "/fpga_bank/RXSCLK5") (net 103 "/fpga_bank/TXSYNC4") (net 104 "/fpga_bank/TXSERCLK4") (net 105 "/fpga_bank/RXCASYNC4") (net 106 "/fpga_bank/TXMSYNC5") (net 107 "/fpga_bank/RXCASYNC5") (net 108 "/fpga_bank/RXCRCSYNC5") (net 109 "/fpga_bank/RXSERCLK7") (net 110 "/fpga_bank/TXSER6") (net 111 "/fpga_bank/RXSYNC6") (net 112 "/fpga_bank/RXSER6") (net 113 "/fpga_bank/TXSYNC7") (net 114 "/fpga_bank/TXSERCLK6") (net 115 "/fpga_bank/RXSYNC7") (net 116 "/fpga_bank/TXMSYNC6") (net 117 "/fpga_bank/RXCRCSYNC6") (net 118 "/fpga_bank/TXSER7") (net 119 "/fpga_bank/A10") (net 120 "/fpga_bank/D5") (net 121 "/fpga_bank/D4") (net 122 "/fpga_bank/PTYPE2") (net 123 "/fpga_bank/A8") (net 124 "/fpga_bank/A9") (net 125 "/fpga_bank/D2") (net 126 "/fpga_bank/A4") (net 127 "/fpga_bank/D1") (net 128 "/fpga_bank/A6") (net 129 "/fpga_bank/A1") (net 130 "/fpga_bank/PTYPE0") (net 131 "/fpga_bank/A0") (net 132 "/fpga_bank/D0") (net 133 "/fpga_bank/TXMSYNC4") (net 134 "/fpga_bank/RXSERCLK4") (net 135 "/fpga_bank/RXSERCLK2") (net 136 "/fpga_bank/TXSER2") (net 137 "/fpga_bank/RXCRCSYNC2") (net 138 "/fpga_bank/RXCASYNC2") (net 139 "/fpga_bank/RXCASYNC3") (net 140 "/fpga_bank/TXMSYNC3") (net 141 "/fpga_bank/D7") (net 142 "/fpga_bank/RXSYNC4") (net 143 "/fpga_bank/RXSERCLK5") (net 144 "/fpga_bank/A3") (net 145 "/fpga_bank/TXSER4") (net 146 "/fpga_bank/TXSYNC5") (net 147 "/fpga_bank/RXCRCSYNC3") (net 148 "/fpga_bank/A14") (net 149 "/fpga_bank/D6") (net 150 "/fpga_bank/RXSCLK3") (net 151 "/fpga_bank/TXMSYNC0") (net 152 "/fpga_bank/TXSER0") (net 153 "/fpga_bank/TXSERCLK0") (net 154 "/fpga_bank/TXSER1") (net 155 "/fpga_bank/TXSYNC0") (net 156 "/fpga_bank/RXCRCSYNC1") (net 157 "/fpga_bank/RXCASYNC1") (net 158 "/fpga_bank/RXSCLK1") (net 159 "/fpga_bank/RXSERCLK6") (net 160 "/fpga_bank/RXCASYNC6") (net 161 "/fpga_bank/TXSER5") (net 162 "/fpga_bank/TXSERCLK5") (net 163 "/fpga_bank/RXCASYNC7") (net 164 "/fpga_bank/RXSYNC5") (net 165 "/fpga_bank/TXMSYNC7") (net 166 "/fpga_bank/RXCRCSYNC7") (net 167 "/fpga_bank/RXSER7") (net 168 "/fpga_bank/TXSERCLK7") (net 169 "/fpga_bank/TXSYNC6") (net 170 "/fpga_bank/RXSCLK7") (net 171 "/fpga_bank/RXSCLK6") (net 172 "/fpga_bank/RXTSEL") (net 173 "/fpga_bank/RXSER5") (net 174 "/fpga_bank/TXON") (net 175 "/fpga_bank/8KEXTOSC") (net 176 "/power/V3P3_FRM_RX") (net 177 "/power/V1P8_FRM_PLL") (net 178 "/framer/TRST") (net 179 "Net-(C22-Pad2)") (net 180 "/regulator/V1P1_SW_IN") (net 181 "/regulator/V3P8_SW_IN") (net 182 "/regulator/V2P3_SW_IN") (net 183 "Net-(C23-Pad2)") (net 184 "/regulator/V3P8_SW_OUT") (net 185 "Net-(C24-Pad2)") (net 186 "/regulator/V2P3_SW_OUT") (net 187 "/regulator/V3P3_LDO_IN") (net 188 "/regulator/V2P5_LDO_IN") (net 189 "/regulator/V1P8_LDO_IN") (net 190 "Net-(C84-Pad1)") (net 191 "Net-(C85-Pad1)") (net 192 "Net-(D1-PadC)") (net 193 "/fpga_cfg/INITN") (net 194 "Net-(R26-Pad1)") (net 195 "/fpga_cfg/CFG1") (net 196 "/fpga_cfg/CSSPIN") (net 197 "/fpga_cfg/IO2") (net 198 "/fpga_cfg/IO3") (net 199 "/fpga_cfg/MCLK") (net 200 "Net-(C90-Pad2)") (net 201 "/fpga_cfg/FT_V1P8_LDO") (net 202 "Net-(C92-Pad1)") (net 203 "Net-(C93-Pad1)") (net 204 "/fpga_cfg/FT_EECS") (net 205 "Net-(R59-Pad1)") (net 206 "Net-(R60-Pad2)") (net 207 "/fpga_cfg/FT_EEDATA") (net 208 "/fpga_cfg/FT_EECLK") (net 209 "/fpga_cfg/FT_OSCI") (net 210 "Net-(R63-Pad1)") (net 211 "/fpga_cfg/FT_DM") (net 212 "/fpga_cfg/FT_DP") (net 213 "Net-(R66-Pad2)") (net 214 "/fpga_cfg/FT_RESET#") (net 215 "/fpga_cfg/FT_PWRSAV#") (net 216 "Net-(D3-PadA)") (net 217 "/fpga_cfg/JTAG_ACT") (net 218 "/fpga_cfg/ADBUS3") (net 219 "/fpga_cfg/ADBUS2") (net 220 "/fpga_cfg/ADBUS1") (net 221 "/fpga_cfg/ADBUS0") (net 222 "/fpga_cfg/FT_MOSI") (net 223 "/fpga_cfg/FT_MISO") (net 224 "/fpga_cfg/FT_CS") (net 225 "Net-(C127-Pad2)") (net 226 "Net-(R64-Pad1)") (net 227 "Net-(R65-Pad1)") (net 228 "/fpga_bank/ULPI_DM") (net 229 "/fpga_bank/ULPI_DP") (net 230 "Net-(R53-Pad1)") (net 231 "/fpga_bank/ULPI_REFCLK") (net 232 "Net-(R71-Pad2)") (net 233 "/fpga_bank/ULPI_RESETB") (net 234 "Net-(C119-Pad2)") (net 235 "/power/FPGA_V1P1") (net 236 "/power/FRAMER_V3P3") (net 237 "/power/FRAMER_V1P8") (net 238 "/power/FPGA_V2P5") (net 239 "+5V") (net 240 "Net-(R7-Pad1)") (net 241 "Net-(R9-Pad1)") (net 242 "Net-(R56-Pad2)") (net 243 "Net-(R57-Pad1)") (net 244 "Net-(R58-Pad2)") (net 245 "/regulator/V1P1_VREG") (net 246 "/regulator/V1P1_LL") (net 247 "/regulator/V1P1_VBST") (net 248 "/regulator/V1P1_VFB") (net 249 "/regulator/V1P1_PGOOD") (net 250 "/regulator/V1P1_EN") (net 251 "/regulator/V1P1_TRIP") (net 252 "/regulator/V1P1_MODE") (net 253 "Net-(Q2-Pad1)") (net 254 "/fpga_bank/ULPI_STP") (net 255 "/fpga_bank/ULPI_DIR") (net 256 "/fpga_bank/ULPI_NXT") (net 257 "/fpga_bank/ULPI_DATA0") (net 258 "/fpga_bank/ULPI_DATA1") (net 259 "/fpga_bank/ULPI_DATA2") (net 260 "/fpga_bank/ULPI_DATA3") (net 261 "/fpga_bank/ULPI_CLKOUT") (net 262 "/fpga_bank/ULPI_DATA4") (net 263 "/fpga_bank/ULPI_DATA5") (net 264 "/fpga_bank/ULPI_DATA6") (net 265 "/fpga_bank/ULPI_DATA7") (net 266 "/regulator/VRAW") (net 267 "/regulator/VRAW_FUSED") (net 268 "/fpga_bank/VBUS_ULPI") (net 269 "/fpga_cfg/VBUS_FT") (net 270 "Net-(P1-PadB5)") (net 271 "Net-(P1-PadA5)") (net 272 "Net-(P2-PadB5)") (net 273 "Net-(P2-PadA5)") (net 274 "/regulator/V3P8_SW") (net 275 "/regulator/V2P3_SW") (net 276 "/fpga_cfg/FT_SHIELD") (net 277 "/fpga_bank/ULPI_SHIELD") (net 278 "/fpga_bank/FT_SCLK") (net 279 "Net-(TP1-Pad1)") (net 280 "Net-(TP2-Pad1)") (net 281 "Net-(TP3-Pad1)") (net 282 "Net-(TP4-Pad1)") (net 283 "Net-(TP5-Pad1)") (net 284 "Net-(TP6-Pad1)") (net 285 "/fpga_bank/FPGA_N1") (net 286 "/fpga_bank/FPGA_P2") (net 287 "/fpga_bank/FPGA_C4") (net 288 "Net-(Q1-Pad1)") (net 289 "Net-(R34-Pad2)") (net 290 "/fpga_bank/PROGRAMN") (footprint "ipc_capc:IPC_CAPC100X50X55L25N" (layer "F.Cu") (tedit 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"/fpga_bank/RXSYNC4") (tstamp 65127507-c1ed-4f5b-a6b5-9b3c0a68ce3e)) (pad "C8" smd circle locked (at -6 2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 50f9c657-9457-4bdb-bc8d-834a26288d3a)) (pad "C9" smd circle locked (at -6 1.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 129 "/fpga_bank/A1") (tstamp 4c56ab96-5c07-4528-af22-cb84dc7ad3f4)) (pad "C10" smd circle locked (at -6 0.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 123 "/fpga_bank/A8") (tstamp ce21510b-ac90-44a3-b5d2-b0aa41590cff)) (pad "C11" smd circle locked (at -6 -0.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 124 "/fpga_bank/A9") (tstamp 80fc7502-f12b-4715-809c-0ea08a9938da)) (pad "C12" smd circle locked (at -6 -1.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 121 "/fpga_bank/D4") (tstamp a0cd0da4-ae88-48e6-b8e1-e8630c53c5a0)) (pad "C13" smd circle locked (at -6 -2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 72 "/fpga_bank/TXSERCLK3") (tstamp e6e92733-54f4-482c-b32c-e3fc8f866e77)) (pad "C14" smd circle locked (at -6 -2.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 51 "/fpga_bank/CS#") (tstamp b9f0cbc7-9da6-4b4c-b2fc-bfa05771749b)) (pad "C15" smd circle locked (at -6 -3.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 141 "/fpga_bank/D7") (tstamp cfa9561b-3715-4a48-b511-5b979760f088)) (pad "C16" smd circle locked (at -6 -4.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 139 "/fpga_bank/RXCASYNC3") (tstamp 398e476f-d595-40a3-8ec6-9cc178fd65e9)) (pad "C17" smd circle locked (at -6 -5.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 140 "/fpga_bank/TXMSYNC3") (tstamp 5d3155f2-4d69-4cd9-a9e6-96ad59a8fb0a)) (pad "C18" smd circle locked (at -6 -6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp bdfc19b4-2327-41e9-92ad-08a85919adb4)) (pad "C19" smd circle locked (at -6 -6.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 871f95e1-9dbb-4945-a204-f4abfc0b51f1)) (pad "C20" smd circle locked (at -6 -7.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 86 "/fpga_bank/TXMSYNC1") (tstamp b42f2b0f-0eec-4018-997a-0e3f16ec74de)) (pad "D1" smd circle locked (at -5.2 7.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 102 "/fpga_bank/RXSCLK5") (tstamp 680d940a-2b3e-4cd8-beaf-91fe7456a65d)) (pad "D2" smd circle locked (at -5.2 6.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 106 "/fpga_bank/TXMSYNC5") (tstamp 26d2c885-f1ba-40c4-8cdf-ff594a601780)) (pad "D3" smd circle locked (at -5.2 6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 145 "/fpga_bank/TXSER4") (tstamp e351174a-2066-4b14-b2c2-909547ade57c)) (pad "D4" smd circle locked (at -5.2 5.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 4d534ffe-944c-49b3-9726-c257ab53fd8c)) (pad "D5" smd circle locked (at -5.2 4.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 3111b5e1-d2dd-409d-9466-636e44a73c8b)) (pad "D6" smd circle locked (at -5.2 3.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a603df1a-aac0-4ee8-9cc7-20928f47ce76)) (pad "D7" smd circle locked (at -5.2 2.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 130 "/fpga_bank/PTYPE0") (tstamp 6b38139a-34b9-4bba-a2b9-c6c54ada6e62)) (pad "D8" smd circle locked (at -5.2 2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2cd319f0-c707-4682-99ed-d62b28f8df1b)) (pad "D9" smd circle locked (at -5.2 1.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 126 "/fpga_bank/A4") (tstamp aabb3b15-b789-4319-ac7f-d7cca87c9e8b)) (pad "D10" smd circle locked (at -5.2 0.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 127 "/fpga_bank/D1") (tstamp c5223f94-b6a9-4ec6-be26-a229466a97a7)) (pad "D11" smd circle locked (at -5.2 -0.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 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240feeef-65e5-4175-8de1-dfdea94ba881)) (pad "D18" smd circle locked (at -5.2 -6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 135 "/fpga_bank/RXSERCLK2") (tstamp 673560bb-60dc-41dd-b954-9049a8b5eae8)) (pad "D19" smd circle locked (at -5.2 -6.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 88 "/fpga_bank/RXSER1") (tstamp 52baa0bc-0e6f-48df-8241-43282f450845)) (pad "D20" smd circle locked (at -5.2 -7.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 89 "/fpga_bank/RXSYNC1") (tstamp 3574ff8e-e15e-4885-a114-cec95c7d11cb)) (pad "E1" smd circle locked (at -4.4 7.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 112 "/fpga_bank/RXSER6") (tstamp 4fbef701-9deb-47cb-a979-40fb15e246fa)) (pad "E2" smd circle locked (at -4.4 6.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 173 "/fpga_bank/RXSER5") (tstamp 468b7589-3ccc-4464-a4d7-b8635deee996)) (pad "E3" smd circle locked (at -4.4 6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 164 "/fpga_bank/RXSYNC5") (tstamp 6147e282-0944-4e65-b45f-78f304c47262)) (pad "E4" smd circle locked (at -4.4 5.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 146 "/fpga_bank/TXSYNC5") (tstamp 3809f624-203b-4c8a-b54c-e86340140fbc)) (pad "E5" smd circle locked (at -4.4 4.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 73d6508a-510f-4fdb-941d-fca14c29e659)) (pad "E6" smd circle locked (at -4.4 3.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 133 "/fpga_bank/TXMSYNC4") (tstamp c64370ad-a6eb-401a-8dae-048e5bb449fb)) (pad "E7" smd circle locked (at -4.4 2.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 134 "/fpga_bank/RXSERCLK4") (tstamp 2beff7d9-0334-482e-9449-dafe598768fb)) (pad "E8" smd circle locked (at -4.4 2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 132 "/fpga_bank/D0") (tstamp c182c2e0-9774-4225-bdb7-158d6846e3de)) (pad "E9" smd circle locked (at -4.4 1.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 131 "/fpga_bank/A0") (tstamp 20649df9-5dbf-4794-a640-841b6aba7967)) (pad "E10" smd circle locked (at -4.4 0.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 128 "/fpga_bank/A6") (tstamp 887d8f26-2999-47dd-b8e8-e2d91da5ff7e)) (pad "E11" smd circle locked (at -4.4 -0.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 125 "/fpga_bank/D2") (tstamp 9042f484-0c85-4379-beb5-a2791f74827b)) (pad "E12" smd circle locked (at -4.4 -1.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 74b44f58-7bf4-4454-bbaf-f14d6d1e6363)) (pad "E13" smd circle locked (at -4.4 -2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 8ae8b5b6-e319-4ad8-b250-cf4b4e3f53e4)) (pad "E14" smd circle locked (at -4.4 -2.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 120 "/fpga_bank/D5") (tstamp 780c83d2-b7dd-41d1-ab1e-4f7c092f0712)) (pad "E15" smd circle locked (at -4.4 -3.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 49 "/fpga_bank/WR#") (tstamp ec376b3c-7927-4cc8-ad04-27bcf18b41bd)) (pad "E16" smd circle locked (at -4.4 -4.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp cc77ecfa-2125-472c-8384-f1b3529a2e33)) (pad "E17" smd circle locked (at -4.4 -5.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 138 "/fpga_bank/RXCASYNC2") (tstamp 16945bc9-adaa-404c-b50e-89fa27ce50df)) (pad "E18" smd circle locked (at -4.4 -6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 137 "/fpga_bank/RXCRCSYNC2") (tstamp 58b19300-58fd-4617-824f-ec75cec73c31)) (pad "E19" smd circle locked (at -4.4 -6.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 87 "/fpga_bank/RXSCLK0") (tstamp 7f8dac48-4264-4639-87da-b0fa5183eac0)) (pad "E20" smd circle locked (at -4.4 -7.6 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 95 "/fpga_bank/RXSERCLK1") (tstamp 10517fd9-a27f-4b0c-acf3-c70f6cec39be)) (pad "F1" smd circle locked (at -3.6 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circle locked (at -1.2 2.8 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp c3c3cec6-2940-4627-a490-93808c2eeb99)) (pad "J8" smd circle locked (at -1.2 2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 235 "/power/FPGA_V1P1") (tstamp 0b9b23e4-1eb3-4be5-ab4f-51ec7830a88a)) (pad "J9" smd circle locked (at -1.2 1.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp ad8c1080-f18a-451d-be17-34f91f871ae2)) (pad "J10" smd circle locked (at -1.2 0.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 36fc63ad-a50a-4121-a031-f12ac4ca7c72)) (pad "J11" smd circle locked (at -1.2 -0.4 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 3dde0398-19b8-44f5-954f-2b2fe3dca7b3)) (pad "J12" smd circle locked (at -1.2 -1.2 180) (size 0.37 0.37) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 37ca4a00-bbc3-463e-8f77-47a882b1ca7b)) (pad "J13" smd circle locked (at -1.2 -2 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45887992-be54-413a-aecb-84b6d5eccac2)) (pad "D12" smd circle locked (at -4.5 -3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 158 "/fpga_bank/RXSCLK1") (tstamp c4363f0b-f6d5-454f-b464-708c4c4df9a2)) (pad "D13" smd circle locked (at -4.5 -4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 138 "/fpga_bank/RXCASYNC2") (tstamp b782e124-480c-42d7-98e2-944db8ff2050)) (pad "D14" smd circle locked (at -4.5 -5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 136 "/fpga_bank/TXSER2") (tstamp 8612fa85-f7bd-4526-bd33-b26883c704d7)) (pad "D15" smd circle locked (at -4.5 -6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 74 "/fpga_bank/RXSERCLK3") (tstamp 9aa980ea-6660-43ff-972d-32afd9c73023)) (pad "D16" smd circle locked (at -4.5 -7.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp b931529c-9a5c-4db7-9321-012b8339ed99)) (pad "E1" smd circle locked (at -3.5 7.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 15 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90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 236 "/power/FRAMER_V3P3") (tstamp 9759df47-5adc-4831-8f6c-13e4b894655f)) (pad "K5" smd circle locked (at 1.5 3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 236 "/power/FRAMER_V3P3") (tstamp d5d5dee8-ec69-4159-8214-f04716a61407)) (pad "K6" smd circle locked (at 1.5 2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 237 "/power/FRAMER_V1P8") (tstamp b8f02968-157a-4b60-aeef-d5f58c26576b)) (pad "K7" smd circle locked (at 1.5 1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp cd2dc2ff-e143-4cea-a0cd-a6e29800635e)) (pad "K8" smd circle locked (at 1.5 0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp d6f89a88-ba45-46e6-a367-1e8bf94ecc61)) (pad "K9" smd circle locked (at 1.5 -0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 9bc58b5a-35e0-42cc-88b0-d43d697db90d)) (pad "K10" smd circle locked (at 1.5 -1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 3ae33618-9d15-401f-a823-16e107091b42)) (pad "K11" smd circle locked (at 1.5 -2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 237 "/power/FRAMER_V1P8") (tstamp f49cd75f-4ac9-454d-ba92-7d7d9d3072e0)) (pad "K12" smd circle locked (at 1.5 -3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 125 "/fpga_bank/D2") (tstamp 634cda64-f51b-40a8-9de6-0fb95b706263)) (pad "K13" smd circle locked (at 1.5 -4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 126 "/fpga_bank/A4") (tstamp 498dafc8-4a57-43e5-8d2d-791f8424ce59)) (pad "K14" smd circle locked (at 1.5 -5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 128 "/fpga_bank/A6") (tstamp f5d975ad-81c5-422a-8a87-fa210d4c8132)) (pad "K15" smd circle locked (at 1.5 -6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 97 "/fpga_bank/A2") (tstamp 1a385e1a-95c1-4288-908e-4f1bdfd7bef8)) (pad "K16" smd circle locked (at 1.5 -7.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 98 "/fpga_bank/A5") (tstamp 1bf55789-bb84-4e28-86e3-34554592f187)) (pad "L1" smd circle locked (at 2.5 7.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 27 "/framer/RRING4") (tstamp 9a3f9e0a-655d-44c3-806b-ed5b9403fcde)) (pad "L2" smd circle locked (at 2.5 6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp eed4f9fa-66a0-4f60-ab28-cfb96dc3a893)) (pad "L3" smd circle locked (at 2.5 5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 32 "/framer/TTIP5") (tstamp 06be4d35-c8be-4029-9ce4-8f4f83ba0028)) (pad "L4" smd circle locked (at 2.5 4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 33 "/framer/TRING5") (tstamp 0ceef26d-24d2-4dfe-aed4-ecad2322fb74)) (pad "L5" smd circle locked (at 2.5 3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp ac38a94d-cf94-48a5-9b53-75cb76ec4dea)) (pad "L6" smd circle locked (at 2.5 2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 175 "/fpga_bank/8KEXTOSC") (tstamp 525db8e4-a45a-4319-a549-768100d9859b)) (pad "L7" smd circle locked (at 2.5 1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 237 "/power/FRAMER_V1P8") (tstamp b2c11a29-292e-4d16-95db-d40058f3c23b)) (pad "L8" smd circle locked (at 2.5 0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 237 "/power/FRAMER_V1P8") (tstamp 76808e4f-9add-49ba-8da1-3c602a44683c)) (pad "L9" smd circle locked (at 2.5 -0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 237 "/power/FRAMER_V1P8") (tstamp 1d95356f-2668-4b15-9a3c-ee0c9cb9dda7)) (pad "L10" smd circle locked (at 2.5 -1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 237 "/power/FRAMER_V1P8") (tstamp 982541e8-9ded-4dff-b068-c8a329f6c03b)) (pad "L11" smd circle locked (at 2.5 -2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 144 "/fpga_bank/A3") (tstamp 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"/framer/RTIP5") (tstamp 95560d1a-b05c-4bf1-84ca-edce04f2662d)) (pad "M2" smd circle locked (at 3.5 6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 176 "/power/V3P3_FRM_RX") (tstamp de66dc06-f96c-4c49-8a60-af514299b49b)) (pad "M3" smd circle locked (at 3.5 5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 36 "/framer/TTIP6") (tstamp d8bf24bc-94b9-459f-b5bf-88cd3ac4c3f6)) (pad "M4" smd circle locked (at 3.5 4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 37 "/framer/TRING6") (tstamp 650930bf-7177-4039-8bf9-9e7436690ea4)) (pad "M5" smd circle locked (at 3.5 3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 236 "/power/FRAMER_V3P3") (tstamp 307c430d-ac03-4761-8aaa-2a993e41705b)) (pad "M6" smd circle locked (at 3.5 2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 236 "/power/FRAMER_V3P3") (tstamp 0f4c724c-f506-4c1b-a567-7509f02e427e)) (pad "M7" smd circle locked (at 3.5 1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 170 "/fpga_bank/RXSCLK7") (tstamp 4e406a7e-12c6-4ce4-ae88-58feaa7652c8)) (pad "M8" smd circle locked (at 3.5 0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 163 "/fpga_bank/RXCASYNC7") (tstamp ae21ad0e-1c78-46d2-b0db-a118dc647621)) (pad "M9" smd circle locked (at 3.5 -0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 236 "/power/FRAMER_V3P3") (tstamp 5690756b-55ef-4cc2-a597-bf2f330e6b0f)) (pad "M10" smd circle locked (at 3.5 -1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 159 "/fpga_bank/RXSERCLK6") (tstamp 64b42c1f-2456-40c4-84d6-9e9ad9784346)) (pad "M11" smd circle locked (at 3.5 -2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 146 "/fpga_bank/TXSYNC5") (tstamp 4c67405f-f755-46f0-a4fe-3451da64611b)) (pad "M12" smd circle locked (at 3.5 -3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp b651ce91-4235-472f-9f02-20dfff999003)) (pad "M13" smd circle locked (at 3.5 -4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 130 "/fpga_bank/PTYPE0") (tstamp 2f716f91-c64b-49b5-ad23-de480dcfaf8f)) (pad "M14" smd circle locked (at 3.5 -5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 132 "/fpga_bank/D0") (tstamp 53b2aeeb-0ec9-474c-b2fb-a23ff7d08f4b)) (pad "M15" smd circle locked (at 3.5 -6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 62 "/fpga_bank/ACK1#") (tstamp e80766ba-8f70-4fe0-bda0-927400fe139b)) (pad "M16" smd circle locked (at 3.5 -7.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 58 "/fpga_bank/PCLK") (tstamp cd445e4b-7faa-40da-ad39-f3e012d2f594)) (pad "N1" smd circle locked (at 4.5 7.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 31 "/framer/RRING5") (tstamp ffd0d7bc-384f-415f-b9e5-4afbdced49a3)) (pad "N2" smd circle locked (at 4.5 6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 171a4e69-fba1-4c58-9222-23380ab87ea8)) (pad "N3" smd circle locked (at 4.5 5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 2465d092-74ec-4c8c-ad57-7af65de045ba)) (pad "N4" smd circle locked (at 4.5 4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 236 "/power/FRAMER_V3P3") (tstamp e5aaffee-1eb3-4cee-b734-ba3c85ad50a8)) (pad "N5" smd circle locked (at 4.5 3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 1 "GND") (tstamp 26efb0ca-7506-49a1-b5e1-598e54c0ba30)) (pad "N6" smd circle locked (at 4.5 2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 165 "/fpga_bank/TXMSYNC7") (tstamp ddb5be77-600b-4f14-a2aa-b88e21aade4a)) (pad "N7" smd circle locked (at 4.5 1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 166 "/fpga_bank/RXCRCSYNC7") (tstamp b6ad0b0b-d409-4239-99ea-db8dd87a7607)) (pad "N8" smd circle locked (at 4.5 0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 169 "/fpga_bank/TXSYNC6") (tstamp 71266576-c977-48b2-90f6-02bc77fbab80)) (pad "N9" smd circle locked (at 4.5 -0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 160 "/fpga_bank/RXCASYNC6") (tstamp 859e4834-8c2b-4313-8d09-840bf4f74241)) (pad "N10" smd circle locked (at 4.5 -1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 162 "/fpga_bank/TXSERCLK5") (tstamp 0989f4a1-453c-43ce-b563-5df46609433a)) (pad "N11" smd circle locked (at 4.5 -2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 164 "/fpga_bank/RXSYNC5") (tstamp 9eba23fb-88c2-4bce-bfc8-c3ba8b728aab)) (pad "N12" smd circle locked (at 4.5 -3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 145 "/fpga_bank/TXSER4") (tstamp 21ea476b-7ffe-4332-b54d-df4e1af60510)) (pad "N13" smd circle locked (at 4.5 -4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 142 "/fpga_bank/RXSYNC4") (tstamp c9befb27-0e2d-46dc-9182-fb7231ccadb6)) (pad "N14" smd circle locked (at 4.5 -5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 236 "/power/FRAMER_V3P3") (tstamp 9bcc53cb-161e-4c2d-a84f-55356c2555c4)) (pad "N15" smd circle locked (at 4.5 -6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 61 "/fpga_bank/ACK0#") (tstamp a63cbfd4-873d-4b7e-b21a-cc0034bf6d1e)) (pad "N16" smd circle locked (at 4.5 -7.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 57 "/fpga_bank/REQ0#") (tstamp 338b6064-7eb5-47b4-bce2-eeefe4d4b0e2)) (pad "P1" smd circle locked (at 5.5 7.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 34 "/framer/RTIP6") (tstamp 5b1a42c5-27dc-4460-af00-2655b0c41f30)) (pad "P2" smd circle locked (at 5.5 6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 176 "/power/V3P3_FRM_RX") (tstamp 5cc4a9df-78d2-4178-994d-afa3c7728f1f)) (pad "P3" smd circle locked (at 5.5 5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 40 "/framer/TTIP7") (tstamp ba50a014-b333-4da3-8375-d0d088b6cffd)) (pad "P4" smd circle locked (at 5.5 4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 41 "/framer/TRING7") (tstamp a1b43b89-e004-4a5c-8cdf-e6969f322ac7)) (pad "P5" smd circle locked (at 5.5 3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 118 "/fpga_bank/TXSER7") (tstamp 963d22cf-6d19-48f0-8b24-05071a556e0a)) (pad "P6" smd circle locked (at 5.5 2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 168 "/fpga_bank/TXSERCLK7") (tstamp dc57955d-ecaf-4504-9de5-9777f7a88994)) (pad "P7" smd circle locked (at 5.5 1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a013c303-c226-4146-bd9c-ae5e86088203)) (pad "P8" smd circle locked (at 5.5 0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 167 "/fpga_bank/RXSER7") (tstamp 5f051fc1-a984-4707-b68e-b04b866df816)) (pad "P9" smd circle locked (at 5.5 -0.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 171 "/fpga_bank/RXSCLK6") (tstamp 17131324-345f-433b-b6dc-eb447f061d99)) (pad "P10" smd circle locked (at 5.5 -1.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 161 "/fpga_bank/TXSER5") (tstamp 1ce2e678-9e5b-48fa-8cbb-21cb269b2907)) (pad "P11" smd circle locked (at 5.5 -2.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 173 "/fpga_bank/RXSER5") (tstamp c003edcf-dddc-412f-bf4b-5085cabf07e5)) (pad "P12" smd circle locked (at 5.5 -3.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp ccdcb066-1895-464b-a6cf-dfea12dbba67)) (pad "P13" smd circle locked (at 5.5 -4.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 133 "/fpga_bank/TXMSYNC4") (tstamp 12d70e89-99fb-4272-b3a4-6511da07e269)) (pad "P14" smd circle locked (at 5.5 -5.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 134 "/fpga_bank/RXSERCLK4") (tstamp 492317d9-1ebe-4d0d-b4c2-cc0768667aa0)) (pad "P15" smd circle locked (at 5.5 -6.5 90) (size 0.45 0.45) (layers "F.Cu" "F.Paste" "F.Mask") (net 99 "/fpga_bank/RXSER4") (tstamp e3a4eb3f-3f89-4572-a6bc-cf5f8d8c1c28)) (pad "P16" smd circle locked (at 5.5 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