# Buildsheet autogenerated by ravenadm tool -- Do not edit.

NAMEBASE=		iverilog
VERSION=		12.0
KEYWORDS=		cad
VARIANTS=		standard
SDESC[standard]=	Verilog simulation and synthesis tool
HOMEPAGE=		http://iverilog.icarus.com/
CONTACT=		Michael_Neumann[mneumann@ntecs.de]

DOWNLOAD_GROUPS=	main
SITES[main]=		GITHUB/steveicarus:iverilog:v12_0
DISTFILE[1]=		generated:main
DF_INDEX=		1
SPKGS[standard]=	single

OPTIONS_AVAILABLE=	none
OPTIONS_STANDARD=	none

BUILD_DEPENDS=		gperf:primary:standard

USES=			autoreconf:build bison gmake readline c++:single

LICENSE=		GPLv2+:single
LICENSE_TERMS=		single:{{WRKDIR}}/TERMS
LICENSE_FILE=		GPLv2+:{{WRKSRC}}/COPYING
LICENSE_AWK=		TERMS:"StringHeap.h"
LICENSE_SOURCE=		TERMS:{{WRKSRC}}/named.h
LICENSE_SCHEME=		solo

FPC_EQUIVALENT=		cad/iverilog

MUST_CONFIGURE=		gnu
CONFIGURE_ARGS=		--disable-suffix
CONFIGURE_ENV=		CXXCPP=cpp

INSTALL_REQ_TOOLCHAIN=	yes

pre-configure:
	cd ${WRKSRC} && ${SH} ./autoconf.sh

[FILE:724:descriptions/desc.single]
Icarus Verilog is a Verilog simulation and synthesis tool. It
operates as a compiler, compiling source code written in Verilog
(IEEE-1364) into some target format. For batch simulation, the
compiler can generate C++ code that is compiled and linked with
a run time library (called "vvm") then executed as a command to
run the simulation. For synthesis, the compiler generates netlists
in the desired format.

The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the
year 2000. This is a fairly large and complex standard, so it will
take some time for it to get there, but that's the goal.


[FILE:111:distinfo]
a68cb1ef7c017ef090ebedb2bc3e39ef90ecc70a3400afb4aa94303bc3beaa7d      2995096 steveicarus-iverilog-12_0.tar.gz


[FILE:686:manifests/plist.single]
bin/
 iverilog
 iverilog-vpi
 vvp
include/iverilog/
 _pli_types.h
 acc_user.h
 ivl_target.h
 sv_vpi_user.h
 veriuser.h
 vpi_user.h
lib/
 libveriuser.a
 libvpi.a
lib/ivl/
 blif-s.conf
 blif.conf
 blif.tgt
 cadpli.vpl
 ivl
 ivlpp
 null-s.conf
 null.conf
 null.tgt
 pcb-s.conf
 pcb.conf
 pcb.tgt
 sizer-s.conf
 sizer.conf
 sizer.tgt
 stub-s.conf
 stub.conf
 stub.tgt
 system.vpi
 v2005_math.vpi
 v2009.vpi
 va_math.vpi
 vhdl-s.conf
 vhdl.conf
 vhdl.tgt
 vhdl_sys.vpi
 vhdl_textio.vpi
 vhdlpp
 vlog95-s.conf
 vlog95.conf
 vlog95.tgt
 vpi_debug.vpi
 vvp-s.conf
 vvp.conf
 vvp.tgt
lib/ivl/include/
 constants.vams
 disciplines.vams
share/man/man1/
 iverilog-vpi.1.gz
 iverilog.1.gz
 vvp.1.gz