Yacht v1.1 (Yet Another Cycle Hunting Table) ------------------------------------------------------------------------------- Forewords : ------------------------------------------------------------------------------- This document is based on : - 9th Edition of M68000 8-16-32-bit Microporcessor User's Manual (Motorola, 1993) (laterly refered as M68000UM) - Programmer's Reference Manual Rev 1 (Motorola, 1992) (laterly refered as M68000PRM) - US Patent n°4,325,121 - Two level control store for microprogrammed data processor (Motorola, Apr, 13, 1982) (lately refered as USP4325121) - Error reports / question asked by users (see below) ------------------------------------------------------------------------------- Changes log : ------------------------------------------------------------------------------- v1 : intitial release v1.1 (this version) : - Lines #0042-#0056 : rewrote parts of the vocabulary section - Lines #0057-#0071 : added a general note section about this document - Lines #0166-#0173 : added a note on Program Counter addressing modes - THX Atarizoll & npomarede - http://atari-forum.com/viewtopic.php?t=26820 - Line #0347 : added missing BTST Dn,#data timing - THX flamewing - http://gendev.spritesmind.net/forum/viewtopic.php?t=2917 - Line #0625 : fixed a typo on (xxx).L timing for CLR, NEGX, NEG, NOT - THX byuu - http://gendev.spritesmind.net/forum/viewtopic.php?t=3040 - Line #1273 : fixed a copy / paste error on MULU / MULS #data,DN - THX TomH - http://www.atari-forum.com/viewtopic.php?t=36648 - Lines #0821-#0839, #0936, #0957 : coherency with exception section - THX TomH & ijor - http://www.atari-forum.com/viewtopic.php?t=36648 - Lines #1538-#1574 : fixed accurate exception timing - THX ijor - http://www.atari-forum.com/viewtopic.php?t=36648 ------------------------------------------------------------------------------- Vocabulary : ------------------------------------------------------------------------------- Clock Cycle : time between two adjacent pulses of the oscillator that sets the tempo of the processor. Microcycle : (in this document) indivisible CPU cycle of execution : takes 2 clock cycles. Bus Cycle : exept from the Read-Modify-Write Cycle that is only used by the TAS instruction, a bus cycle consists of eight states (if no wait cycle needed). Each state longs half a clock cycle so a full bus cycle is 4 clock cycles long in the best case. ------------------------------------------------------------------------------- General note : ------------------------------------------------------------------------------- This document is primary designed for programmers that need to know exactly how many clock cycles are used by their code, when things are read or written in memory and in which order. Consequently, the purpose of this document is to correct and explain the instruction execution times as written in M68000UM. So, as in section 8 of M68000UM, this document "lists instruction execution times in terms of external clock (CLK) periods. In this data, it is assumed that both memory read and write cycles consist of four clock periods. A longer memory cycle causes the generation of wait states that must be added to the total instruction times." ------------------------------------------------------------------------------- Rules of thumb : ------------------------------------------------------------------------------- 1) 68000 external data bus is 16 bit so any operation on a long word in memory will take at least 2 full bus cycles. 2) 68000 internal data bus is 32 bit so reading/writing word or long word from / to a register take the same time. 3) There are 3 math units. One 16 bit ALU and two 16 bit Address Units. The ALU was complex enough for the math instruction set while the AUs were only able to do address related math (add, subtract). So, The ALU is used in the execution of instructions whereas the AUs are used to calculate the effective address(es). And, of course, the 2 16 bit AUs worked together to make the 32 bit effective address calculations. Therefore, to do a simple 16 bit math instruction, the ALU can do the operation while the AUs perform address calculations during the same micro-cycle. 3a) 68000 ALU is 16 bits so any arithmetic or logic operation between 2 values take more cycles with long words values than with words values even if source and destination are registers. 3b) For arithmetic operations on an address register such as ADDA and SUBA, the whole 32 bits destination address register is used regardless of the operation size (.W or .L). As this arithmetic operation is done by the ALU and no the AUs and in regard of the previous rule (3a), the ALU will take longer to perform word sized operations on address registers than on data registers. 4a) in general case, the source operand is evaluated first then the destination operand is evaluated and, at last, the instruction is executed. These 3 steps can't be mixed. "addi.w #,-(An)" is a good exemple for this rule. 4b) there are some optimized instructions for which the previous rule doesn't apply, destination operand evaluation starts before the end of source operand evaluation. "abcd.b -(Ay),-(Ax)" is a good exemple for this rule. 5) As SP=A7 it seems obvious than (d16,An) and (d16,SP) always have the same timings. Same thing for (d8,An,Xn) and (d8,SP,Xn). ------------------------------------------------------------------------------- How to read the table : ------------------------------------------------------------------------------- Exec Time : ----------- This table use the same rules than the M68000UM for the exec times. So, data is shown as : n(r/w) where: n is the total number of clock periods r is the number of read cycles w is the number of write cycles. In addition, each exec time is spltted in two parts (when possible) : "instruction exec time" and "effective address exec time". The two exec times must be added in order to get the "real" exec time. Data Bus Usage : ---------------- Each following caracter describe the state of the data bus during a microcycle. n : nop : data bus is not used n- : nop with idle wait, no transfers occur during this microcycle (can last 2 microcycles instead of one ?). p : Program fetch; read from next consecutive location in program memory W : Write MSW onto data bus when using long word w : Write one word onto data bus (LSW if long word operation) R : Read MSW from data bus when using long word r : Read one word from data bus (LSW if long word operation) S : Push (write) MSW onto stack when using long word s : Push (write) one word onto stack (LSW if long word operation) U : Pop (read) MSW from stack when using long word u : Pop (read) one word from stack (LSW if long word operation) V : Fetch vector MSW (for exceptions) v : Fetch vector LSW (for exceptions) i : Vector number acquisition in an IACK Cycle (for Interrupt exception) F : Fetch SSP MSW (for /RESET exception) f : Fetch SSP LSW (for /RESET exception) DON'T TAKE CARE OF SPACES OR PIPES. Exemples : ---------- Note : in the following exemples 'n' caracter will be replace by '.' when the data bus is not used 1) MOVE.W -(An),Dn (line #347) : Takes 10 clock cycles (data bus read 2 times, written 0 times) Data bus usage : ..r.p 2) EORI.L #,-(An) (line #179) : Takes 30 clock cycles (data bus read 5 times, written 2 times) Data bus usage : .p.p..R.r.p.w.W Note on Program Counter addressing modes : ------------------------------------------ (d16,PC) and (d16,An) always behave the same. It's also true for (d8,PC,Xn) and (d8,An,Xn). So if you want to know the exact timing of an instruction with PC related effective address, once you ensured that addressing mode is correct for this instruction, please refer to the according An line. ******************************************************************************* OPERAND EFFECTIVE ADDRESS CALCULATION TIMES ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ------------------+-----------------+------------------------------------------ .B or .W : | | Dn | 0(0/0) | An | 0(0/0) | (An) | 4(1/0) | nr (An)+ | 4(1/0) | nr -(An) | 6(1/0) | n nr (d16,An) | 8(2/0) | np nr (d8,An,Xn) | 10(2/0) | n np nr (xxx).W | 8(2/0) | np nr (xxx).L | 12(3/0) | np np nr # | 4(1/0) | np .L : | | Dn | 0(0/0) | An | 0(0/0) | (An) | 8(2/0) | nR nr (An)+ | 8(2/0) | nR nr -(An) | 10(2/0) | n nR nr (d16,An) | 12(3/0) | np nR nr (d8,An,Xn) | 14(3/0) | n np nR nr (xxx).W | 12(3/0) | np nR nr (xxx).L | 16(4/0) | np np nR nr # | 8(2/0) | np np ******************************************************************************* Line 0000 : ADDI, ANDI, ANDI to CCR, BCHG, BCLR, BSET, BTST, CMPI, EORI, EORI to CCR, MOVEP, ORI, ORI to CCR, SUBI ******************************************************************************* ------------------------------------------------------------------------------- EORI, ORI, ANDI, | Exec Time | Data Bus Usage SUBI, ADDI | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ #, : | | | | .B or .W : | | | | Dn | 8(2/0) 0(0/0) | np | | np (An) | 12(2/1) 4(1/0) | np | nr | np nw (An)+ | 12(2/1) 4(1/0) | np | nr | np nw -(An) | 12(2/1) 6(1/0) | np | n nr | np nw (d16,An) | 12(2/1) 8(2/0) | np | np nr | np nw (d8,An,Xn) | 12(2/1) 10(2/0) | np | n np nr | np nw (xxx).W | 12(2/1) 8(2/0) | np | np nr | np nw (xxx).L | 12(2/1) 12(3/0) | np | np np nr | np nw .L : | | | Dn | 16(3/0) 0(0/0) | np np | | np nn (An) | 20(3/2) 8(2/0) | np np | nR nr | np nw nW (An)+ | 20(3/2) 8(2/0) | np np | nR nr | np nw nW -(An) | 20(3/2) 10(2/0) | np np | n nR nr | np nw nW (d16,An) | 20(3/2) 12(3/0) | np np | np nR nr | np nw nW (d8,An,Xn) | 20(3/2) 14(3/0) | np np | n np nR nr | np nw nW (xxx).W | 20(3/2) 12(3/0) | np np | np nR nr | np nw nW (xxx).L | 20(3/2) 16(4/0) | np np | np np nR nr | np nw nW NOTES : .M68000UM is probably wrong with instruction timming for ANDI.L #,Dn instruction. It reads "14(3/0)" but, according to USP4325121, this instruction is based on the same microwords than EORI.L #,Dn and ORI.L #,Dn that have a "16(3/0)" timming. In addition, evaluation on real hardware confirms the 16 cycles timing. ------------------------------------------------------------------------------- ORI, ANDI, EORI | Exec Time | Data Bus Usage to CCR, to SR | INSTR | 1st Operand | INSTR ------------------+-----------------+-------------+---------------------------- #,CCR | | | .B : | 20(3/0) | np | nn nn np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage CMPI | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+-------------+-------------- #, : | | | | .B or .W : | | | | Dn | 8(2/0) 0(0/0) | np | | np (An) | 8(2/0) 4(1/0) | np | nr | np (An)+ | 8(2/0) 4(1/0) | np | nr | np -(An) | 8(2/0) 6(1/0) | np | n nr | np (d16,An) | 8(2/0) 8(2/0) | np | np nr | np (d8,An,Xn) | 8(2/0) 10(2/0) | np | n np nr | np (xxx).W | 8(2/0) 8(2/0) | np | np nr | np (xxx).L | 8(2/0) 12(3/0) | np | np np nr | np .L : | | | | Dn | 14(3/0) 0(0/0) | np np | | np n (An) | 12(3/0) 8(2/0) | np np | nR nr | np (An)+ | 12(3/0) 8(2/0) | np np | nR nr | np -(An) | 12(3/0) 10(2/0) | np np | n nR nr | np (d16,An) | 12(3/0) 12(3/0) | np np | np nR nr | np (d8,An,Xn) | 12(3/0) 14(3/0) | np np | n np nR nr | np (xxx).W | 12(3/0) 12(3/0) | np np | np nR nr | np (xxx).L | 12(3/0) 16(4/0) | np np | np np nR nr | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage BCHG, BSET | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ Dn, : | | | | .B : | | | | (An) | 8(1/1) 4(1/0) | | nr | np nw (An)+ | 8(1/1) 4(1/0) | | nr | np nw -(An) | 8(1/1) 6(1/0) | | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | | np np nr | np nw Dn,Dm : | | | | .L : | | | | if Dn<16 | 6(1/0) 0(0/0) | | | np n if Dn>15 | 8(1/0) 0(0/0) | | | np nn #, : | | | | .B : | | | | (An) | 12(2/1) 4(1/0) | np | nr | np nw (An)+ | 12(2/1) 4(1/0) | np | nr | np nw -(An) | 12(2/1) 6(1/0) | np | n nr | np nw (d16,An) | 12(2/1) 8(2/0) | np | np nr | np nw (d8,An,Xn) | 12(2/1) 10(2/0) | np | n np nr | np nw (xxx).W | 12(2/1) 8(2/0) | np | np nr | np nw (xxx).L | 12(2/1) 12(3/0) | np | np np nr | np nw #,Dn : | | | | .L : | | | | if data<16 | 10(2/0) 0(0/0) | np | | np n if data>15 | 12(2/0) 0(0/0) | np | | np nn ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage BCLR | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ Dn, : | | | | .B : | | | | (An) | 8(1/1) 4(1/0) | | nr | np nw (An)+ | 8(1/1) 4(1/0) | | nr | np nw -(An) | 8(1/1) 6(1/0) | | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | | np np nr | np nw Dn,Dm : | | | | .L : | | | | if Dn<16 | 8(1/0) 0(0/0) | | | np nn if Dn>15 | 10(1/0) 0(0/0) | | | np nn n #, : | | | | .B : | | | | (An) | 12(2/1) 4(1/0) | np | nr | np nw (An)+ | 12(2/1) 4(1/0) | np | nr | np nw -(An) | 12(2/1) 6(1/0) | np | n nr | np nw (d16,An) | 12(2/1) 8(2/0) | np | np nr | np nw (d8,An,Xn) | 12(2/1) 10(2/0) | np | n np nr | np nw (xxx).W | 12(2/1) 8(2/0) | np | np nr | np nw (xxx).L | 12(2/1) 12(3/0) | np | np np nr | np nw #,Dn : | | | | .L : | | | | if data<16 | 12(2/0) 0(0/0) | np | | np nn if data>15 | 14(2/0) 0(0/0) | np | | np nn n ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage BTST | INSTR EA | 1st Operand | 2nd OP (ea) | INSTR ------------------+-----------------+-------------+---------------+------------ Dn, : | | | | .B : | | | | (An) | 4(1/0) 4(1/0) | | nr | np (An)+ | 4(1/0) 4(1/0) | | nr | np -(An) | 4(1/0) 6(1/0) | | n nr | np (d16,An) | 4(1/0) 8(2/0) | | np nr | np (d8,An,Xn) | 4(1/0) 10(2/0) | | n np nr | np (xxx).W | 4(1/0) 8(2/0) | | np nr | np (xxx).L | 4(1/0) 12(3/0) | | np np nr | np # | 6(1/0) 4(1/0) | | np | np n Dn,Dm : | | | | .L : | 6(1/0) 0(0/0) | | | np n #, : | | | | .B : | | | | (An) | 8(2/0) 4(1/0) | np | nr | np (An)+ | 8(2/0) 4(1/0) | np | nr | np -(An) | 8(2/0) 6(1/0) | np | n nr | np (d16,An) | 8(2/0) 8(2/0) | np | np nr | np (d8,An,Xn) | 8(2/0) 10(2/0) | np | n np nr | np (xxx).W | 8(2/0) 8(2/0) | np | np nr | np (xxx).L | 8(2/0) 12(3/0) | np | np np nr | np #,Dn : | | | | .L : | 10(2/0) 0(0/0) | np | | np n ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVEP | INSTR | INSTR ------------------+-----------------+------------------------------------------ Dx,(d16,Ay) : | | .W : | 16(2/2) | np nW nw np .L : | 24(2/4) | np nW nW nw nw np (d16,Ay),Dx : | | .W : | 16(4/0) | np nR nr np .L : | 24(6/0) | np nR nR nr nr np NOTES : .Read and write operations are done from the MSB to the LSB on 2 words if using ".w" (first read/write word at Ay+d16 then word at Ay+d16+2)and on 4 words if using ".l" (first read/write word at Ay+d16 then word at Ay+d16+2 then word at Ay+d16+4 and finally word at Ay+d16+6). ******************************************************************************* Line 0001 & Line 0010 & Line 0011 MOVE.B MOVE.L, MOVEA.L MOVE.W, MOVEA.W ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVE | INSTR | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- ,Dn : | | | .B or .W : | | | Dn | 4(1/0) | | np An | 4(1/0) | | np (An) | 8(2/0) | nr | np (An)+ | 8(2/0) | nr | np -(An) | 10(2/0) | n nr | np (d16,An) | 12(3/0) | np nr | np (d8,An,Xn) | 14(3/0) | n np nr | np (xxx).W | 12(3/0) | np nr | np (xxx).L | 16(4/0) | np np nr | np # | 8(2/0) | np | np .L : | | | Dn | 4(1/0) | | np An | 4(1/0) | | np (An) | 12(3/0) | nR nr | np (An)+ | 12(3/0) | nR nr | np -(An) | 14(3/0) | n nR nr | np (d16,An) | 16(4/0) | np nR nr | np (d8,An,Xn) | 18(4/0) | n np nR nr | np (xxx).W | 16(4/0) | np nR nr | np (xxx).L | 20(5/0) | np np nR nr | np # | 12(3/0) | np np | np ,(An) : | | | .B or .W : | | | Dn | 8(1/1) | | nw np An | 8(1/1) | | nw np (An) | 12(2/1) | nr | nw np (An)+ | 12(2/1) | nr | nw np -(An) | 14(2/1) | n nr | nw np (d16,An) | 16(3/1) | np nr | nw np (d8,An,Xn) | 18(3/1) | n np nr | nw np (xxx).W | 16(3/1) | np nr | nw np (xxx).L | 20(4/1) | np np nr | nw np # | 12(2/1) | np | nw np .L : | | | Dn | 12(1/2) | | nW nw np An | 12(1/2) | | nW nw np (An) | 20(3/2) | nR nr | nW nw np (An)+ | 20(3/2) | nR nr | nW nw np -(An) | 22(3/2) | n nR nr | nW nw np (d16,An) | 24(4/2) | np nR nr | nW nw np (d8,An,Xn) | 26(4/2) | n np nR nr | nW nw np (xxx).W | 24(4/2) | np nR nr | nW nw np (xxx).L | 28(5/2) | np np nR nr | nW nw np # | 20(3/2) | np np | nW nw np ,(An)+ : | | | .B or .W : | | | Dn | 8(1/1) | | nw np An | 8(1/1) | | nw np (An) | 12(2/1) | nr | nw np (An)+ | 12(2/1) | nr | nw np -(An) | 14(2/1) | n nr | nw np (d16,An) | 16(3/1) | np nr | nw np (d8,An,Xn) | 18(3/1) | n np nr | nw np (xxx).W | 16(3/1) | np nr | nw np (xxx).L | 20(4/1) | np np nr | nw np # | 12(2/1) | np | nw np .L : | | | Dn | 12(1/2) | | nW nw np An | 12(1/2) | | nW nw np (An) | 20(3/2) | nR nr | nW nw np (An)+ | 20(3/2) | nR nr | nW nw np -(An) | 22(3/2) | n nR nr | nW nw np (d16,An) | 24(4/2) | np nR nr | nW nw np (d8,An,Xn) | 26(4/2) | n np nR nr | nW nw np (xxx).W | 24(4/2) | np nR nr | nW nw np (xxx).L | 28(5/2) | np np nR nr | nW nw np # | 20(3/2) | np np | nW nw np ,-(An) : | | | .B or .W : | | | Dn | 8(1/1) | | np nw An | 8(1/1) | | np nw (An) | 12(2/1) | nr | np nw (An)+ | 12(2/1) | nr | np nw -(An) | 14(2/1) | n nr | np nw (d16,An) | 16(3/1) | np nr | np nw (d8,An,Xn) | 18(3/1) | n np nr | np nw (xxx).W | 16(3/1) | np nr | np nw (xxx).L | 20(4/1) | np np nr | np nw # | 12(2/1) | np | np nw .L : | | | Dn | 12(1/2) | | np nw nW An | 12(1/2) | | np nw nW (An) | 20(3/2) | nR nr | np nw nW (An)+ | 20(3/2) | nR nr | np nw nW -(An) | 22(3/2) | n nR nr | np nw nW (d16,An) | 24(4/2) | np nR nr | np nw nW (d8,An,Xn) | 26(4/2) | n np nR nr | np nw nW (xxx).W | 24(4/2) | np nR nr | np nw nW (xxx).L | 28(5/2) | np np nR nr | np nw nW # | 20(3/2) | np np | np nw nW ,(d16,An) : | | | .B or .W : | | | Dn | 12(2/1) | | np nw np An | 12(2/1) | | np nw np (An) | 16(3/1) | nr | np nw np (An)+ | 16(3/1) | nr | np nw np -(An) | 18(3/1) | n nr | np nw np (d16,An) | 20(4/1) | np nr | np nw np (d8,An,Xn) | 22(4/1) | n np nr | np nw np (xxx).W | 20(4/1) | np nr | np nw np (xxx).L | 24(5/1) | np np nr | np nw np # | 16(3/1) | np | np nw np .L : | | | Dn | 16(2/2) | | np nW nw np An | 16(2/2) | | np nW nw np (An) | 24(4/2) | nR nr | np nW nw np (An)+ | 24(4/2) | nR nr | np nW nw np -(An) | 26(4/2) | n nR nr | np nW nw np (d16,An) | 28(5/2) | np nR nr | np nW nw np (d8,An,Xn) | 30(5/2) | n np nR nr | np nW nw np (xxx).W | 28(5/2) | np nR nr | np nW nw np (xxx).L | 32(6/2) | np np nR nr | np nW nw np # | 24(4/2) | np np | np nW nw np ,(d8,An,Xn) : | | | .B or .W : | | | Dn | 14(2/1) | | n np nw np An | 14(2/1) | | n np nw np (An) | 18(3/1) | nr | n np nw np (An)+ | 18(3/1) | nr | n np nw np -(An) | 20(3/1) | n nr | n np nw np (d16,An) | 22(4/1) | np nr | n np nw np (d8,An,Xn) | 24(4/1) | n np nr | n np nw np (xxx).W | 22(4/1) | np nr | n np nw np (xxx).L | 26(5/1) | np np nr | n np nw np # | 18(3/1) | np | n np nw np .L : | | | Dn | 18(2/2) | | n np nW nw np An | 18(2/2) | | n np nW nw np (An) | 26(4/2) | nR nr | n np nW nw np (An)+ | 26(4/2) | nR nr | n np nW nw np -(An) | 28(4/2) | n nR nr | n np nW nw np (d16,An) | 30(5/2) | np nR nr | n np nW nw np (d8,An,Xn) | 32(5/2) | n np nR nr | n np nW nw np (xxx).W | 30(5/2) | np nR nr | n np nW nw np (xxx).L | 34(6/2) | np np nR nr | n np nW nw np # | 26(4/2) | np np | n np nW nw np ,(xxx).W : | | | .B or .W : | | | Dn | 12(2/1) | | np nw np An | 12(2/1) | | np nw np (An) | 16(3/1) | nr | np nw np (An)+ | 16(3/1) | nr | np nw np -(An) | 18(3/1) | n nr | np nw np (d16,An) | 20(4/1) | np nr | np nw np (d8,An,Xn) | 22(4/1) | n np nr | np nw np (xxx).W | 20(4/1) | np nr | np nw np (xxx).L | 24(5/1) | np np nr | np nw np # | 16(3/1) | np | np nw np .L : | | | Dn | 16(2/2) | | np nW nw np An | 16(2/2) | | np nW nw np (An) | 24(4/2) | nR nr | np nW nw np (An)+ | 24(4/2) | nR nr | np nW nw np -(An) | 26(4/2) | n nR nr | np nW nw np (d16,An) | 28(5/2) | np nR nr | np nW nw np (d8,An,Xn) | 30(5/2) | n np nR nr | np nW nw np (xxx).W | 28(5/2) | np nR nr | np nW nw np (xxx).L | 32(6/2) | np np nR nr | np nW nw np # | 24(4/2) | np np | np nW nw np ,(xxx).L : | | | .B or .W : | | | Dn | 16(3/1) | | np np nw np An | 16(3/1) | | np np nw np (An) | 20(4/1) | nr | np nw np np (An)+ | 20(4/1) | nr | np nw np np -(An) | 22(4/1) | n nr | np nw np np (d16,An) | 24(5/1) | np nr | np nw np np (d8,An,Xn) | 26(5/1) | n np nr | np nw np np (xxx).W | 24(5/1) | np nr | np nw np np (xxx).L | 28(6/1) | np np nr | np nw np np # | 20(4/1) | np | np np nw np .L : | | | Dn | 20(3/2) | | np np nW nw np An | 20(3/2) | | np np nW nw np (An) | 28(5/2) | nR nr | np nW nw np np (An)+ | 28(5/2) | nR nr | np nW nw np np -(An) | 30(5/2) | n nR nr | np nW nw np np (d16,An) | 32(6/2) | np nR nr | np nW nw np np (d8,An,Xn) | 34(6/2) | n np nR nr | np nW nw np np (xxx).W | 32(6/2) | np nR nr | np nW nw np np (xxx).L | 36(7/2) | np np nR nr | np nW nw np np # | 28(5/2) | np np | np np nW nw np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVEA | INSTR | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- ,An : | | | .W : | | | Dn | 4(1/0) | | np An | 4(1/0) | | np (An) | 8(2/0) | nr | np (An)+ | 8(2/0) | nr | np -(An) | 10(2/0) | n nr | np (d16,An) | 12(3/0) | np nr | np (d8,An,Xn) | 14(3/0) | n np nr | np (xxx).W | 12(3/0) | np nr | np (xxx).L | 16(4/0) | np np nr | np # | 8(2/0) | np | np .L : | | | Dn | 4(1/0) | | np An | 4(1/0) | | np (An) | 12(3/0) | nR nr | np (An)+ | 12(3/0) | nR nr | np -(An) | 14(3/0) | n nR nr | np (d16,An) | 16(4/0) | np nR nr | np (d8,An,Xn) | 18(4/0) | n np nR nr | np (xxx).W | 16(4/0) | np nR nr | np (xxx).L | 20(5/0) | np np nR nr | np # | 12(3/0) | np np | np ******************************************************************************* Line 0100 CHK, CLR, EXT, ILLEGAL, JMP, JSR, LEA , LINK, MV fr/to CCR/SR, MOVEM, NBCD, NEG, NEGX, NOP, NOT, PEA, RTR, RTS, SWAP, STOP, TAS, TRAP, TRAPV, TST, UNLK ******************************************************************************* ------------------------------------------------------------------------------- CLR, | Exec Time | Data Bus Usage NEGX, NEG, NOT | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw .L : | | | Dn | 6(1/0) 0(0/0) | | np n (An) | 12(1/2) 8(2/0) | nR nr | np nw nW (An)+ | 12(1/2) 8(2/0) | nR nr | np nw nW -(An) | 12(1/2) 10(2/0) | n nR nr | np nw nW (d16,An) | 12(1/2) 12(3/0) | np nR nr | np nw nW (d8,An,Xn) | 12(1/2) 14(3/0) | n np nR nr | np nw nW (xxx).W | 12(1/2) 12(3/0) | np nR nr | np nw nW (xxx).L | 12(1/2) 16(4/0) | np np nR nr | np nw nW ------------------------------------------------------------------------------- MOVE | Exec Time | Data Bus Usage from SR | INSTR EA | 2nd Op (ea) | INSTR ------------------+-----------------+---------------+-------------------------- SR, : | | | .W : | | | Dn | 6(1/0) 0(0/0) | | np n (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw ------------------------------------------------------------------------------- MOVE | Exec Time | Data Bus Usage to CCR, to SR | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- ,CCR : | | | .W : | | | Dn | 12(1/0) 0(0/0) | | nn np np (An) | 12(1/0) 4(1/0) | nr | nn np np (An)+ | 12(1/0) 4(1/0) | nr | nn np np -(An) | 12(1/0) 6(1/0) | n nr | nn np np (d16,An) | 12(1/0) 8(2/0) | np nr | nn np np (d8,An,Xn) | 12(1/0) 10(2/0) | n np nr | nn np np (xxx).W | 12(1/0) 8(2/0) | np nr | nn np np (xxx).L | 12(1/0) 12(3/0) | np np nr | nn np np # | 12(1/0) 4(1/0) | np | nn np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage NBCD | INSTR | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- : | | | .B : | | | Dn | 6(1/0) 0(0/0) | | np n (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage PEA | INSTR | INSTR ------------------+-----------------+------------------------------------------ : | | .L : | | (An) | 12(1/2) | np nS ns (d16,An) | 16(2/2) | np np nS ns (d8,An,Xn) | 20(2/2) | n np n np nS ns (xxx).W | 16(2/2) | np nS ns np (xxx).L | 20(3/2) | np np nS ns np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage SWAP | INSTR | INSTR ------------------+-----------------+------------------------------------------ Dn : | | .W : | 4(1/0) | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVEM | INSTR | INSTR ------------------+-----------------+------------------------------------------ M --> R | | .W | | (An) | 12+4m(3+m/0) | np (nr)* nr np (An)+ | 12+4m(3+m/0) | np (nr)* nr np (d16,An) | 16+4m(4+m/0) | np np (nr)* nr np (d8,An,Xn) | 18+4m(4+m/0) | np n np (nr)* nr np (xxx).W | 16+4m(4+m/0) | np np (nr)* nr np (xxx).L | 20+4m(5+m/0) | np np np (nr)* nr np .L | | (An) | 12+8m(3+2m/0) | np nR (nr nR)* np (An)+ | 12+8m(3+2m/0) | np nR (nr nR)* np (d16,An) | 16+8m(4+2m/0) | np np nR (nr nR)* np (d8,An,Xn) | 18+8m(4+2m/0) | np n np nR (nr nR)* np (xxx).W | 16+8m(4+2m/0) | np np nR (nr nR)* np (xxx).L | 20+8m(5+2m/0) | np np np nR (nr nR)* np R --> M | | .W | | (An) | 8+4m(2/m) | np (nw)* np -(An) | 8+4m(2/m) | np (nw)* np (d16,An) | 12+4m(3/m) | np np (nw)* np (d8,An,Xn) | 14+4m(3/m) | np n np (nw)* np (xxx).W | 12+4m(3/m) | np np (nw)* np (xxx).L | 16+4m(4/m) | np np np (nw)* np .L | | (An) | 8+8m(2/2m) | np (nW nw)* np -(An) | 8+8m(2/2m) | np (nw nW)* np (d16,An) | 12+8m(3/2m) | np np (nW nw)* np (d8,An,Xn) | 14+8m(3/2m) | np n np (nW nw)* np (xxx).W | 12+8m(3/2m) | np np (nW nw)* np (xxx).L | 16+8m(4/2m) | np np np (nW nw)* np NOTES : .'m' is the number of registers to move. .'(nr)*' should be replaced by m consecutive 'nr' .'(nw)*' should be replaced by m consecutive 'nw' .'(nR nr)*' should be replaced by m consecutive 'nR nr' .'(nW nw)*' (or '(nw nW)*') should be replaced by m consecutive 'nW nw' (or m consecutive 'nw nW'). .In M --> R mode, an extra bus read cycle occurs. This extra access can cause errors (for exemple if occuring beyond the bounds of physical memory). .In M --> R mode, MOVEM.W sign-extends words moved to data registers. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage EXT | INSTR | 1st Operand | INSTR ------------------+-----------------+---------------+-------------------------- Dn : | | | .W : | 4(1/0) | | np .L : | 4(1/0) | | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage TST | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np (An) | 4(1/0) 4(1/0) | nr | np (An)+ | 4(1/0) 4(1/0) | nr | np -(An) | 4(1/0) 6(1/0) | n nr | np (d16,An) | 4(1/0) 8(2/0) | np nr | np (d8,An,Xn) | 4(1/0) 10(2/0) | n np nr | np (xxx).W | 4(1/0) 8(2/0) | np nr | np (xxx).L | 4(1/0) 12(3/0) | np np nr | np .L | | | Dn | 4(1/0) 0(0/0) | | np (An) | 4(1/0) 8(2/0) | nR nr | np (An)+ | 4(1/0) 8(2/0) | nR nr | np -(An) | 4(1/0) 10(2/0) | n nR nr | np (d16,An) | 4(1/0) 12(3/0) | np nR nr | np (d8,An,Xn) | 4(1/0) 14(3/0) | n np nR nr | np (xxx).W | 4(1/0) 12(3/0) | np nR nr | np (xxx).L | 4(1/0) 16(4/0) | np np nR nr | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage TAS | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- : | | | .B : | | | Dn | 4(1/0) 0(0/0) | | np (An) | 10(1/1) 4(1/0) | nr | n nw np (An)+ | 10(1/1) 4(1/0) | nr | n nw np -(An) | 10(1/1) 6(1/0) | n nr | n nw np (d16,An) | 10(1/1) 8(2/0) | np nr | n nw np (d8,An,Xn) | 10(1/1) 10(2/0) | n np nr | n nw np (xxx).W | 10(1/1) 8(1/0) | | n nw np (xxx).L | 10(1/1) 12(2/0) | | n nw np NOTES : .M68000UM is probably wrong with instruction timming when is different from Dn. It reads "14(3/0)" but according to the same book the read-modify- write bus cycle used by this instruction is only 10 clock cycles long which seems coherent with the microwords decomposition in USP4325121. Last, evaluation on real hardware confirms the 10 cycles timing. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage CHK | INSTR EA | 1st OP (ea) | INSTR --------------+----------------+---------------+------------------------------- no trap : | | | ,Dn : | | / .W : | | / Dn |10(1/0) 0(0/0) | |np nn n (An) |10(1/0) 4(1/0) | nr |np nn n (An)+ |10(1/0) 4(1/0) | nr |np nn n -(An) |10(1/0) 6(1/0) |n nr |np nn n (d16,An) |10(1/0) 8(2/0) | np nr |np nn n (d8,An,Xn) |10(1/0) 10(2/0) |n np nr |np nn n (xxx).W |10(1/0) 8(2/0) | np nr |np nn n (xxx).L |10(1/0) 12(2/0) | np np nr |np nn n # |10(1/0) 4(1/0) | np |np nn n trap : | | | ,Dn : | | | .W : | | | Dn > Src : | | | Dn |38(5/3) 0(0/0) | |np nn ns ns nS nV nv np n np (An) |38(5/3) 4(1/0) | nr |np nn ns ns nS nV nv np n np (An)+ |38(5/3) 4(1/0) | nr |np nn ns ns nS nV nv np n np -(An) |38(5/3) 6(1/0) |n nr |np nn ns ns nS nV nv np n np (d16,An) |38(5/3) 8(2/0) | np nr |np nn ns ns nS nV nv np n np (d8,An,Xn)|38(5/3) 10(2/0) |n np nr |np nn ns ns nS nV nv np n np (xxx).W |38(5/3) 8(2/0) | np nr |np nn ns ns nS nV nv np n np (xxx).L |38(5/3) 12(2/0) | np np nr |np nn ns ns nS nV nv np n np # |38(5/3) 4(1/0) | np |np nn ns ns nS nV nv np n np Dn <0 : | | | Dn |40(5/3) 0(0/0) | |np n nn ns ns nS nV nv np n np (An) |40(5/3) 4(1/0) | nr |np n nn ns ns nS nV nv np n np (An)+ |40(5/3) 4(1/0) | nr |np n nn ns ns nS nV nv np n np -(An) |40(5/3) 6(1/0) |n nr |np n nn ns ns nS nV nv np n np (d16,An) |40(5/3) 8(2/0) | np nr |np n nn ns ns nS nV nv np n np (d8,An,Xn)|40(5/3) 10(2/0) |n np nr |np n nn ns ns nS nV nv np n np (xxx).W |40(5/3) 8(2/0) | np nr |np n nn ns ns nS nV nv np n np (xxx).L |40(5/3) 12(2/0) | np np nr |np n nn ns ns nS nV nv np n np # |40(5/3) 4(1/0) | np |np n nn ns ns nS nV nv np n np NOTES : . for more informations about the "trap" lines see exceptions section below. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage LEA | INSTR | INSTR ------------------+-----------------+------------------------------------------ ,An : | | .L : | | (An) | 4(1/0) | np (d16,An) | 8(2/0) | np np (d8,An,Xn) | 12(2/0) | n np n np (xxx).W | 8(2/0) | np np (xxx).L | 12(3/0) | np np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage JSR | INSTR | INSTR ------------------+-----------------+------------------------------------------ : | | (An) | 16(2/2) | np nS ns np (d16,An) | 18(2/2) | n np nS ns np (d8,An,Xn) | 22(2/2) | n nn np nS ns np (xxx).W | 18(2/2) | n np nS ns np (xxx).L | 20(3/2) | np np nS ns np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage JMP | INSTR | INSTR ------------------+-----------------+------------------------------------------ : | | (An) | 8(2/0) | np np (d16,An) | 10(2/0) | n np np (d8,An,Xn) | 14(2/0) | n nn np np (xxx).W | 10(2/0) | n np np (xxx).L | 12(3/0) | np np np NOTES : .M68000UM is probably wrong with bus read accesses for JMP (d8,An,Xn),Dn instruction. It reads "14(3/0)" but, according to USP4325121 and with a little common sense, 2 bus read accesses are far enough. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage MOVE USP | INSTR | INSTR ------------------+-----------------+------------------------------------------ An,USP : | 4(1/0) | np USP,An : | 4(1/0) | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage RESET | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 132(1/0) | nn (??-)* np NOTES : .(??)* is for 124 cycles when the CPU will asserts the /RSTO signal in order to reset all external devices. Normally, the CPU won't use the bus during these cycles. .RESET instruction have nothing to do with /RESET exception. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage NOP | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 4(1/0) | np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage STOP | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 4(0/0) | n NOTES : .At this point, there is no real clues of how the second microcyle of this * instruction is spent. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage RTE, RTR | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 20(5/0) | nU nu nu np np NOTES : .M68000UM is probably wrong with bus read accesses for RTR instruction. It reads "20(2/0)" but, according to USP4325121 and with a little common sense, 2 bus read accesses aren't enough for reading status register and program counter values from the stack and prefetching. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage RTS | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 16(4/0) | nU nu np np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage TRAPV | INSTR | INSTR ------------------+-----------------+------------------------------------------ no trap | 4(1/0) | np trap | 34(5/3) | np ns nS ns nV nv np n np NOTES : . for more informations about the "trap" line see exceptions section below. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage LINK | INSTR | 2nd Operand | INSTR ------------------+-----------------+---------------+-------------------------- An,# : | | .W : | 16(2/2) | np nS ns np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage UNLNK | INSTR | INSTR ------------------+-----------------+------------------------------------------ An : | 12(3/0) | nU nu np ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ILLEGAL, TRAP | INSTR | INSTR ------------------+-----------------+------------------------------------------ | 34(4/3) | nn ns ns nS nV nv np n np NOTES : .For more informations about this instruction see exceptions section below. ******************************************************************************* Line 0101 ADDQ, DBcc, Scc, SUBQ ******************************************************************************* ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage ADDQ, SUBQ | INSTR EA | 1st OP (ea) | INSTR ------------------+-----------------+---------------+-------------------------- #, : | | | .B or .W : | | | Dn | 4(1/0) 0(0/0) | | np An | 8(1/0) 0(0/0) | | np nn (An) | 8(1/1) 4(1/0) | nr | np nw (An)+ | 8(1/1) 4(1/0) | nr | np nw -(An) | 8(1/1) 6(1/0) | n nr | np nw (d16,An) | 8(1/1) 8(2/0) | np nr | np nw (d8,An,Xn) | 8(1/1) 10(2/0) | n np nr | np nw (xxx).W | 8(1/1) 8(2/0) | np nr | np nw (xxx).L | 8(1/1) 12(3/0) | np np nr | np nw .L : | | | Dn | 8(1/0) 0(0/0) | | np nn An | 8(1/0) 0(0/0) | | np nn (An) | 12(1/2) 8(2/0) | nR nr | np nw nW (An)+ | 12(1/2) 8(2/0) | nR nr | np nw nW -(An) | 12(1/2) 10(2/0) | n nR nr | np nw nW (d16,An) | 12(1/2) 12(3/0) | np nR nr | np nw nW (d8,An,Xn) | 12(1/2) 14(3/0) | n np nR nr | np nw nW (xxx).W | 12(1/2) 12(3/0) | np nR nr | np nw nW (xxx).L | 12(1/2) 16(4/0) | np np nR nr | np nw nW NOTES : .M68000UM is probably wrong with instruction timing for ADDQ.W #,An instruction. It reads "4(1/0)" but, according to USP4325121, this instruction is based on the same microwords than ADDQ.L #,Dn and ADDQ.L #,An that have a "8(3/0)" timing. That makes sense because of the calculation of a 32 bit address on 16 bits ALU. In addition, evaluation on real hardware confirms the 8 cycles timing and, last, it makes addq and subbq coherent in term of timing. ------------------------------------------------------------------------------- | Exec Time | Data Bus Usage DBcc | INSTR | INSTR ------------------+-----------------+------------------------------------------ Dn,