---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | Load F2 45 R3 | Mul F0 F2 F4 | Sub F8 F6 F2 | Div F10 F0 F6 | Add F6 F8 F2 | [reorder buffer] Entry Busy Instruction Stat Dest value head -> 1 No 2 No 3 No 4 No 5 No 6 No [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No Mult2 | No [register result status] F0 F2 F4 F6 F8 F10 Cycle 0 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 Load F2 45 R3 | Mul F0 F2 F4 | Sub F8 F6 F2 | Div F10 F0 F6 | Add F6 F8 F2 | [reorder buffer] Entry Busy Instruction Stat Dest value H/T -> 1 Yes LOAD F6 34 R2 ISSUE F6 2 No 3 No 4 No 5 No 6 No [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest 1/1 Load1 | Yes Load 200 34 #1 Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No Mult2 | No [register result status] F0 F2 F4 F6 F8 F10 Cycle 1 #1 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 Load F2 45 R3 | 2 Mul F0 F2 F4 | Sub F8 F6 F2 | Div F10 F0 F6 | Add F6 F8 F2 | [reorder buffer] Entry Busy Instruction Stat Dest value head -> 1 Yes LOAD F6 34 R2 EXEC F6 tail -> 2 Yes LOAD F2 45 R3 ISSUE F2 3 No 4 No 5 No 6 No [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest 0/1 Load1 | Yes Load 200 234 #1 1/1 Load2 | Yes Load 300 45 #2 Load3 | No Add1 | No Add2 | No Mult1 | No Mult2 | No [register result status] F0 F2 F4 F6 F8 F10 Cycle 2 #2 #1 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 Load F2 45 R3 | 2 3 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | Div F10 F0 F6 | Add F6 F8 F2 | [reorder buffer] Entry Busy Instruction Stat Dest value head -> 1 Yes LOAD F6 34 R2 WRITE F6 234 2 Yes LOAD F2 45 R3 EXEC F2 tail -> 3 Yes MUL F0 F2 F4 ISSUE F0 4 No 5 No 6 No [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No 0/1 Load2 | Yes Load 300 345 #2 Load3 | No Add1 | No Add2 | No 10/10 Mult1 | Yes Mul 0 #2 #3 Mult2 | No [register result status] F0 F2 F4 F6 F8 F10 Cycle 3 #3 #2 #1 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 Div F10 F0 F6 | Add F6 F8 F2 | [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 head -> 2 Yes LOAD F2 45 R3 WRITE F2 345 3 Yes MUL F0 F2 F4 ISSUE F0 tail -> 4 Yes SUB F8 F6 F2 ISSUE F8 5 No 6 No [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No 2/2 Add1 | Yes Sub 234 0 #4 Add2 | No 10/10 Mult1 | Yes Mul 0 0 #3 Mult2 | No [register result status] F0 F2 F4 F6 F8 F10 Cycle 4 #3 #2 #4 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 Div F10 F0 F6 | 5 Add F6 F8 F2 | [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 EXEC F8 tail -> 5 Yes DIV F10 F0 F6 ISSUE F10 6 No [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No 1/2 Add1 | Yes Sub 234 0 #4 Add2 | No 9/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 5 #3 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 6 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 EXEC F8 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 ISSUE F6 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No 0/2 Add1 | Yes Sub 234 0 #4 2/2 Add2 | Yes Add 345 #4 #6 8/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 6 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 ISSUE F6 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No 2/2 Add2 | Yes Add 0 345 #6 7/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 7 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 EXEC F6 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No 1/2 Add2 | Yes Add 0 345 #6 6/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 8 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 EXEC F6 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No 0/2 Add2 | Yes Add 0 345 #6 5/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 9 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No 4/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 10 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No 3/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 11 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No 2/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 12 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No 1/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 13 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 EXEC F0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No 0/10 Mult1 | Yes Mul 0 0 #3 40/40 Mult2 | Yes Div 234 #3 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 14 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 head -> 3 Yes MUL F0 F2 F4 WRITE F0 0 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 ISSUE F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 40/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 15 #3 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 head -> 4 Yes SUB F8 F6 F2 WRITE F8 234 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 39/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 16 #6 #4 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 38/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 17 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 37/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 18 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 36/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 19 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 35/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 20 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 34/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 21 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 33/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 22 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 32/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 23 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 31/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 24 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 30/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 25 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 29/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 26 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 28/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 27 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 27/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 28 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 26/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 29 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 25/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 30 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 24/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 31 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 23/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 32 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 22/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 33 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 21/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 34 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 20/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 35 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 19/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 36 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 18/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 37 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 17/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 38 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 16/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 39 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 15/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 40 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 14/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 41 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 13/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 42 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 12/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 43 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 11/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 44 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 10/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 45 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 9/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 46 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 8/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 47 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 7/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 48 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 6/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 49 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 5/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 50 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 4/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 51 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 3/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 52 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 2/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 53 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 1/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 54 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 55 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 EXEC F10 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No 0/40 Mult2 | Yes Div 0 234 #5 [register result status] F0 F2 F4 F6 F8 F10 Cycle 55 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 55 56 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 head -> 5 Yes DIV F10 F0 F6 WRITE F10 0.0 tail -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No Mult2 | No [register result status] F0 F2 F4 F6 F8 F10 Cycle 56 #6 #5 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 55 56 57 Add F6 F8 F2 | 6 9 10 [reorder buffer] Entry Busy Instruction Stat Dest value 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 5 No DIV F10 F0 F6 COMMIT F10 0.0 H/T -> 6 Yes ADD F6 F8 F2 WRITE F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No Mult2 | No [register result status] F0 F2 F4 F6 F8 F10 Cycle 57 #6 ---------------------------------------------------------------------- [instruction status] Op dest j k | Issue Exec Write Commit Load F6 34 R2 | 1 2 3 4 Load F2 45 R3 | 2 3 4 5 Mul F0 F2 F4 | 3 14 15 16 Sub F8 F6 F2 | 4 6 7 17 Div F10 F0 F6 | 5 55 56 57 Add F6 F8 F2 | 6 9 10 58 [reorder buffer] Entry Busy Instruction Stat Dest value head -> 1 No LOAD F6 34 R2 COMMIT F6 234 2 No LOAD F2 45 R3 COMMIT F2 345 3 No MUL F0 F2 F4 COMMIT F0 0 4 No SUB F8 F6 F2 COMMIT F8 234 5 No DIV F10 F0 F6 COMMIT F10 0.0 tail -> 6 No ADD F6 F8 F2 COMMIT F6 345 [reservation station] Time Name | Busy Op Vj Vk Qj Qk A Dest Load1 | No Load2 | No Load3 | No Add1 | No Add2 | No Mult1 | No Mult2 | No [register result status] F0 F2 F4 F6 F8 F10 Cycle 58