2f-formal Generic formal / compile-time tier — ABC EXDC remainder

The generic-formal page (the shared engine lives in pass/lec; the verify CLI's agent-loop objective is 2f-verify, LEC-specific work is 2f-lec). The compile-time tier is DONE except ABC EXDC: pass.formal mode=normal was re-based onto lec::prove_properties 2026-07-11 (compile profile: engine=bmc in-process, tiny bound, deterministic rlimit=budget_k×4096, timeout=0, ignore_assumes=true; mode=fast unchanged; prove.cpp RETAINED for fast/Hotmux/assumes/fallback), with the stateful verdict ladder: 1-induction proven ⇒ elide; BMC-from-reset refuted with refuted_at ≥ reset_hold ⇒ reachable CEX ⇒ deferred hard error; otherwise keep the runtime check + deferred warning. Tests lhd/tests/lhd_formal_rebase_test.sh.

Reset-exclusion is RESOLVED 2026-07-12 — record the trap. The sound part ships: the coarse BMC-window guard (pass_formal.cpp:504) + primary reset INPUT pinning in the induction rung (reset_negset gated on is_graph_input_pin). DO NOT resurrect the per-flop guard that pins a flop's own reset_pin/negreset inactive in the step — attempted and REVERTED as UNSOUND: reset_pin can carry a DESIGN-CONTROLLED derived signal (Pyrope reset_pin=ref <wire>, slang soft-reset nets, Yosys ARST/SRST/ALOAD/CLR), so pinning it drops REACHABLE mid-trace soft-reset states → false unbounded-Proven → set_proven silently ELIDES the runtime assert → miscompile; the step-vacuity base.isSat() guard does not catch it. Only a PRIMARY reset INPUT inherits the "no mid-trace reset" environment assumption. Same for reset-less power-on-initial flops. assert_always keeps Reset_policy::Include.

Pending — ABC EXDC don't-care network

Policy carried forward (unchanged)

Future / deferred (other pages)