/////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2004 Xilinx, Inc. All Rights Reserved.
//
// You may copy and modify these files for your own internal use solely with
// Xilinx programmable logic devices and  Xilinx EDK system or create IP
// modules solely for Xilinx programmable logic devices and Xilinx EDK system.
// No rights are granted to distribute any files unless they are distributed in
// Xilinx programmable logic devices.
//
/////////////////////////////////////////////////////////////////////////////////
#ifndef BL_ERRORS_H
#define BL_ERRORS_H

#define LD_MEM_WRITE_ERROR  1
#define LD_SREC_LINE_ERROR  2
#define SREC_PARSE_ERROR    3
#define SREC_CKSUM_ERROR    4

#endif /* BL_ERRORS_H */
