Printable Version
Overview Resources Used
1 | MicroBlaze
2 | Local Memory Bus (LMB) 1.0
1 | AXI Interconnect
1 | Block RAM (BRAM) Block
2 | LMB BRAM Controller
1 | AXI External Memory Controller (SRAM/Flash/Cellular RAM)
1 | Processor System Reset Module
1 | MicroBlaze Debug Module (MDM)
1 | Clock Generator
1 | AXI UART (Lite)
1 | AXI SPI Interface
| Specifics
Generated | Thu Jun 22 14:35:21 2017
EDK Version | 14.7
Device Family | spartan6
Device | xc6slx9tqg144-2
Block Diagram | TOP
External Ports | TOP
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
SHARED | RESET_N | I | 1 | RESET_N | RESET
Generic_External_Memory | Linear_Flash_data | IO | 0:7 | Linear_Flash_data |
Generic_External_Memory | Linear_Flash_ce_n | O | 1 | Linear_Flash_ce_n |
Generic_External_Memory | Linear_Flash_oe_n | O | 1 | Linear_Flash_oe_n |
Generic_External_Memory | Linear_Flash_we_n | O | 1 | Linear_Flash_we_n |
RS232_Uart_1 | RS232_Uart_1_sin | I | 1 | RS232_Uart_1_sin |
RS232_Uart_1 | RS232_Uart_1_sout | O | 1 | RS232_Uart_1_sout |
axi_spi_0 | axi_spi_0_SPISEL_pin | I | 1 | axi_spi_0_SPISEL |
axi_spi_0 | axi_spi_0_MISO_pin | IO | 1 | axi_spi_0_MISO |
axi_spi_0 | axi_spi_0_MOSI_pin | IO | 1 | axi_spi_0_MOSI |
axi_spi_0 | axi_spi_0_SCK_pin | IO | 1 | axi_spi_0_SCK |
axi_spi_0 | axi_spi_0_SS_pin | IO | 1 | axi_spi_0_SS |
clock_generator_0 | CLOCK | I | 1 | CLOCK | CLK
Unconnected | Linear_Flash_address | O | 0:18 | Linear_Flash_address |
Processors | TOP
microblaze_0 MicroBlaze The MicroBlaze 32 bit soft processor
IP Specs
Core | Version | Documentation
microblaze | 8.50.c | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MB_RESET | I | 1 | proc_sys_reset_0_MB_Reset
1 | CLK | I | 1 | clk_100_0000MHz
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
ILMB | MASTER | LMB | microblaze_0_ilmb | microblaze_0_i_bram_ctrl
DLMB | MASTER | LMB | microblaze_0_dlmb | microblaze_0_d_bram_ctrl
M_AXI_DP | MASTER | AXI | axi4lite_0 | 4 Peripherals.
M_AXI_IP | MASTER | AXI | axi4lite_0 | 4 Peripherals.
DEBUG | TARGET | XIL_MBDEBUG3 | microblaze_0_debug | debug_module
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SCO | 0
C_FREQ | 0
C_DATA_SIZE | 32
C_DYNAMIC_BUS_SIZING | 1
C_FAMILY | virtex5
C_INSTANCE | microblaze
C_AVOID_PRIMITIVES | 0
C_FAULT_TOLERANT | 0
C_ECC_USE_CE_EXCEPTION | 0
C_LOCKSTEP_SLAVE | 0
C_ENDIANNESS | 0
C_AREA_OPTIMIZED | 0
C_OPTIMIZATION | 0
C_INTERCONNECT | 2
C_STREAM_INTERCONNECT | 0
C_BASE_VECTORS | 0x00000000
C_DPLB_DWIDTH | 32
C_DPLB_NATIVE_DWIDTH | 32
C_DPLB_BURST_EN | 0
C_DPLB_P2P | 0
C_IPLB_DWIDTH | 32
C_IPLB_NATIVE_DWIDTH | 32
C_IPLB_BURST_EN | 0
C_IPLB_P2P | 0
C_M_AXI_DP_SUPPORTS_THREADS | 0
C_M_AXI_DP_THREAD_ID_WIDTH | 1
C_M_AXI_DP_SUPPORTS_READ | 1
C_M_AXI_DP_SUPPORTS_WRITE | 1
C_M_AXI_DP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DP_DATA_WIDTH | 32
C_M_AXI_DP_ADDR_WIDTH | 32
C_M_AXI_DP_PROTOCOL | AXI4LITE
C_M_AXI_DP_EXCLUSIVE_ACCESS | 0
C_INTERCONNECT_M_AXI_DP_READ_ISSUING | 1
C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING | 1
C_M_AXI_IP_SUPPORTS_THREADS | 0
C_M_AXI_IP_THREAD_ID_WIDTH | 1
C_M_AXI_IP_SUPPORTS_READ | 1
C_M_AXI_IP_SUPPORTS_WRITE | 0
C_M_AXI_IP_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IP_DATA_WIDTH | 32
C_M_AXI_IP_ADDR_WIDTH | 32
C_M_AXI_IP_PROTOCOL | AXI4LITE
C_INTERCONNECT_M_AXI_IP_READ_ISSUING | 1
C_D_AXI | 0
C_D_PLB | 0
C_D_LMB | 1
C_I_AXI | 0
C_I_PLB | 0
C_I_LMB | 1
C_USE_MSR_INSTR | 1
C_USE_PCMP_INSTR | 1
C_USE_BARREL | 1
C_USE_DIV | 0
C_USE_HW_MUL | 1
C_USE_FPU | 0
C_USE_REORDER_INSTR | 1
C_UNALIGNED_EXCEPTIONS | 0
C_ILL_OPCODE_EXCEPTION | 0
C_M_AXI_I_BUS_EXCEPTION | 0
C_M_AXI_D_BUS_EXCEPTION | 0
C_IPLB_BUS_EXCEPTION | 0
C_DPLB_BUS_EXCEPTION | 0
C_DIV_ZERO_EXCEPTION | 0
C_FPU_EXCEPTION | 0
C_FSL_EXCEPTION | 0
C_USE_STACK_PROTECTION | 0
C_PVR | 0
C_PVR_USER1 | 0x00
C_PVR_USER2 | 0x00000000
C_DEBUG_ENABLED | 1
C_NUMBER_OF_PC_BRK | 1
C_NUMBER_OF_RD_ADDR_BRK | 0
C_NUMBER_OF_WR_ADDR_BRK | 0
C_INTERRUPT_IS_EDGE | 0
C_EDGE_IS_POSITIVE | 1
C_RESET_MSR | 0x00000000
C_OPCODE_0x0_ILLEGAL | 0
C_FSL_LINKS | 0
C_FSL_DATA_SIZE | 32
C_USE_EXTENDED_FSL_INSTR | 0
C_M0_AXIS_PROTOCOL | GENERIC
C_S0_AXIS_PROTOCOL | GENERIC
C_M1_AXIS_PROTOCOL | GENERIC
C_S1_AXIS_PROTOCOL | GENERIC
C_M2_AXIS_PROTOCOL | GENERIC
C_S2_AXIS_PROTOCOL | GENERIC
C_M3_AXIS_PROTOCOL | GENERIC
C_S3_AXIS_PROTOCOL | GENERIC
C_M4_AXIS_PROTOCOL | GENERIC
C_S4_AXIS_PROTOCOL | GENERIC
C_M5_AXIS_PROTOCOL | GENERIC
C_S5_AXIS_PROTOCOL | GENERIC
C_M6_AXIS_PROTOCOL | GENERIC
C_S6_AXIS_PROTOCOL | GENERIC
C_M7_AXIS_PROTOCOL | GENERIC
C_S7_AXIS_PROTOCOL | GENERIC
C_M8_AXIS_PROTOCOL | GENERIC
C_S8_AXIS_PROTOCOL | GENERIC
C_M9_AXIS_PROTOCOL | GENERIC
C_S9_AXIS_PROTOCOL | GENERIC
C_M10_AXIS_PROTOCOL | GENERIC
C_S10_AXIS_PROTOCOL | GENERIC
C_M11_AXIS_PROTOCOL | GENERIC
C_S11_AXIS_PROTOCOL | GENERIC
C_M12_AXIS_PROTOCOL | GENERIC
C_S12_AXIS_PROTOCOL | GENERIC
C_M13_AXIS_PROTOCOL | GENERIC
C_S13_AXIS_PROTOCOL | GENERIC
C_M14_AXIS_PROTOCOL | GENERIC |  | Name | Value
C_S14_AXIS_PROTOCOL | GENERIC
C_M15_AXIS_PROTOCOL | GENERIC
C_S15_AXIS_PROTOCOL | GENERIC
C_M0_AXIS_DATA_WIDTH | 32
C_S0_AXIS_DATA_WIDTH | 32
C_M1_AXIS_DATA_WIDTH | 32
C_S1_AXIS_DATA_WIDTH | 32
C_M2_AXIS_DATA_WIDTH | 32
C_S2_AXIS_DATA_WIDTH | 32
C_M3_AXIS_DATA_WIDTH | 32
C_S3_AXIS_DATA_WIDTH | 32
C_M4_AXIS_DATA_WIDTH | 32
C_S4_AXIS_DATA_WIDTH | 32
C_M5_AXIS_DATA_WIDTH | 32
C_S5_AXIS_DATA_WIDTH | 32
C_M6_AXIS_DATA_WIDTH | 32
C_S6_AXIS_DATA_WIDTH | 32
C_M7_AXIS_DATA_WIDTH | 32
C_S7_AXIS_DATA_WIDTH | 32
C_M8_AXIS_DATA_WIDTH | 32
C_S8_AXIS_DATA_WIDTH | 32
C_M9_AXIS_DATA_WIDTH | 32
C_S9_AXIS_DATA_WIDTH | 32
C_M10_AXIS_DATA_WIDTH | 32
C_S10_AXIS_DATA_WIDTH | 32
C_M11_AXIS_DATA_WIDTH | 32
C_S11_AXIS_DATA_WIDTH | 32
C_M12_AXIS_DATA_WIDTH | 32
C_S12_AXIS_DATA_WIDTH | 32
C_M13_AXIS_DATA_WIDTH | 32
C_S13_AXIS_DATA_WIDTH | 32
C_M14_AXIS_DATA_WIDTH | 32
C_S14_AXIS_DATA_WIDTH | 32
C_M15_AXIS_DATA_WIDTH | 32
C_S15_AXIS_DATA_WIDTH | 32
C_ICACHE_BASEADDR | 0x00000000
C_ICACHE_HIGHADDR | 0x3FFFFFFF
C_USE_ICACHE | 0
C_ALLOW_ICACHE_WR | 1
C_ADDR_TAG_BITS | 17
C_CACHE_BYTE_SIZE | 8192
C_ICACHE_USE_FSL | 1
C_ICACHE_LINE_LEN | 4
C_ICACHE_ALWAYS_USED | 0
C_ICACHE_INTERFACE | 0
C_ICACHE_VICTIMS | 0
C_ICACHE_STREAMS | 0
C_ICACHE_FORCE_TAG_LUTRAM | 0
C_ICACHE_DATA_WIDTH | 0
C_M_AXI_IC_SUPPORTS_THREADS | 0
C_M_AXI_IC_THREAD_ID_WIDTH | 1
C_M_AXI_IC_SUPPORTS_READ | 1
C_M_AXI_IC_SUPPORTS_WRITE | 0
C_M_AXI_IC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_IC_DATA_WIDTH | 32
C_M_AXI_IC_ADDR_WIDTH | 32
C_M_AXI_IC_PROTOCOL | AXI4
C_M_AXI_IC_USER_VALUE | 0b11111
C_M_AXI_IC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_IC_AWUSER_WIDTH | 5
C_M_AXI_IC_ARUSER_WIDTH | 5
C_M_AXI_IC_WUSER_WIDTH | 1
C_M_AXI_IC_RUSER_WIDTH | 1
C_M_AXI_IC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_IC_READ_ISSUING | 2
C_DCACHE_BASEADDR | 0x00000000
C_DCACHE_HIGHADDR | 0x3FFFFFFF
C_USE_DCACHE | 0
C_ALLOW_DCACHE_WR | 1
C_DCACHE_ADDR_TAG | 17
C_DCACHE_BYTE_SIZE | 8192
C_DCACHE_USE_FSL | 1
C_DCACHE_LINE_LEN | 4
C_DCACHE_ALWAYS_USED | 0
C_DCACHE_INTERFACE | 0
C_DCACHE_USE_WRITEBACK | 0
C_DCACHE_VICTIMS | 0
C_DCACHE_FORCE_TAG_LUTRAM | 0
C_DCACHE_DATA_WIDTH | 0
C_M_AXI_DC_SUPPORTS_THREADS | 0
C_M_AXI_DC_THREAD_ID_WIDTH | 1
C_M_AXI_DC_SUPPORTS_READ | 1
C_M_AXI_DC_SUPPORTS_WRITE | 1
C_M_AXI_DC_SUPPORTS_NARROW_BURST | 0
C_M_AXI_DC_DATA_WIDTH | 32
C_M_AXI_DC_ADDR_WIDTH | 32
C_M_AXI_DC_PROTOCOL | AXI4
C_M_AXI_DC_EXCLUSIVE_ACCESS | 0
C_M_AXI_DC_USER_VALUE | 0b11111
C_M_AXI_DC_SUPPORTS_USER_SIGNALS | 1
C_M_AXI_DC_AWUSER_WIDTH | 5
C_M_AXI_DC_ARUSER_WIDTH | 5
C_M_AXI_DC_WUSER_WIDTH | 1
C_M_AXI_DC_RUSER_WIDTH | 1
C_M_AXI_DC_BUSER_WIDTH | 1
C_INTERCONNECT_M_AXI_DC_READ_ISSUING | 2
C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING | 32
C_USE_MMU | 0
C_MMU_DTLB_SIZE | 4
C_MMU_ITLB_SIZE | 2
C_MMU_TLB_ACCESS | 3
C_MMU_ZONES | 16
C_MMU_PRIVILEGED_INSTR | 0
C_USE_INTERRUPT | 0
C_USE_EXT_BRK | 0
C_USE_EXT_NM_BRK | 0
C_USE_BRANCH_TARGET_CACHE | 0
C_BRANCH_TARGET_CACHE_SIZE | 0
C_PC_WIDTH | 32
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Debuggers | TOP
debug_module MicroBlaze Debug Module (MDM) Debug module for MicroBlaze Soft Processor.
IP Specs
Core | Version | Documentation
mdm | 2.10.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | Debug_SYS_Rst | O | 1 | proc_sys_reset_0_MB_Debug_Sys_Rst
1 | S_AXI_ACLK | I | 1 | clk_100_0000MHz
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
MBDEBUG_0 | INITIATOR | XIL_MBDEBUG3 | microblaze_0_debug | microblaze_0
S_AXI | SLAVE | AXI | axi4lite_0 | 4 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_JTAG_CHAIN | 2
C_INTERCONNECT | 2
C_BASEADDR | 0x41400000
C_HIGHADDR | 0x4140FFFF
C_SPLB_AWIDTH | 32
C_SPLB_DWIDTH | 32
C_SPLB_P2P | 0
C_SPLB_MID_WIDTH | 3 |  | Name | Value
C_SPLB_NUM_MASTERS | 8
C_SPLB_NATIVE_DWIDTH | 32
C_SPLB_SUPPORT_BURSTS | 0
C_MB_DBG_PORTS | 1
C_USE_UART | 1
C_USE_BSCAN | 0
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Busses | TOP
axi4lite_0 AXI Interconnect AXI4 Memory-Mapped Interconnect
IP Specs
Core | Version | Documentation
axi_interconnect | 1.06.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | interconnect_aclk | I | 1 | clk_100_0000MHz
1 | INTERCONNECT_ARESETN | I | 1 | proc_sys_reset_0_Interconnect_aresetn
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | M_AXI_DP
microblaze_0 | MASTER | M_AXI_IP
debug_module | SLAVE | S_AXI
RS232_Uart_1 | SLAVE | S_AXI
Generic_External_Memory | SLAVE | S_AXI_MEM
axi_spi_0 | SLAVE | S_AXI
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | rtl
C_BASEFAMILY | rtl
C_NUM_SLAVE_SLOTS | 1
C_NUM_MASTER_SLOTS | 1
C_AXI_ID_WIDTH | 1
C_AXI_ADDR_WIDTH | 32
C_AXI_DATA_MAX_WIDTH | 32
C_S_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_M_AXI_DATA_WIDTH | 0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020
C_INTERCONNECT_DATA_WIDTH | 32
C_S_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_PROTOCOL | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_BASE_ADDR |
C_M_AXI_HIGH_ADDR |
C_S_AXI_BASE_ID | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_THREAD_ID_WIDTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_IS_INTERCONNECT | 0b0000000000000000
C_S_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_M_AXI_ACLK_RATIO | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_IS_ACLK_ASYNC | 0b0000000000000000
C_INTERCONNECT_ACLK_RATIO | 1
C_S_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_S_AXI_SUPPORTS_READ | 0b1111111111111111
C_M_AXI_SUPPORTS_WRITE | 0b1111111111111111
C_M_AXI_SUPPORTS_READ | 0b1111111111111111
C_AXI_SUPPORTS_USER_SIGNALS | 0
C_AXI_AWUSER_WIDTH | 1
C_AXI_ARUSER_WIDTH | 1
C_AXI_WUSER_WIDTH | 1
C_AXI_RUSER_WIDTH | 1
C_AXI_BUSER_WIDTH | 1
C_AXI_CONNECTIVITY | 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
C_S_AXI_SINGLE_THREAD | 0b0000000000000000
C_M_AXI_SUPPORTS_REORDERING | 0b1111111111111111
C_S_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_M_AXI_SUPPORTS_NARROW_BURST | 0b1111111111111111
C_S_AXI_WRITE_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_READ_ACCEPTANCE | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_M_AXI_WRITE_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001 |  | Name | Value
C_M_AXI_READ_ISSUING | 0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001
C_S_AXI_ARB_PRIORITY | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_SECURE | 0b0000000000000000
C_S_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_S_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_S_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_S_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_M_AXI_WRITE_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_WRITE_FIFO_TYPE | 0b1111111111111111
C_M_AXI_WRITE_FIFO_DELAY | 0b0000000000000000
C_M_AXI_READ_FIFO_DEPTH | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_READ_FIFO_TYPE | 0b1111111111111111
C_M_AXI_READ_FIFO_DELAY | 0b0000000000000000
C_S_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_S_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AW_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_AR_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_W_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_R_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_M_AXI_B_REGISTER | 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
C_INTERCONNECT_R_REGISTER | 0
C_INTERCONNECT_CONNECTIVITY_MODE | 0
C_USE_CTRL_PORT | 0
C_USE_INTERRUPT | 1
C_RANGE_CHECK | 2
C_S_AXI_CTRL_PROTOCOL | AXI4LITE
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_BASEADDR | 0xFFFFFFFF
C_HIGHADDR | 0x00000000
C_DEBUG | 0
C_S_AXI_DEBUG_SLOT | 0
C_M_AXI_DEBUG_SLOT | 0
C_MAX_DEBUG_THREADS | 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
microblaze_0_dlmb Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | SYS_RST | I | 1 | proc_sys_reset_0_BUS_STRUCT_RESET
1 | LMB_CLK | I | 1 | clk_100_0000MHz
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | DLMB
microblaze_0_d_bram_ctrl | SLAVE | SLMB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
microblaze_0_ilmb Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'
IP Specs
Core | Version | Documentation
lmb_v10 | 2.00.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | SYS_RST | I | 1 | proc_sys_reset_0_BUS_STRUCT_RESET
1 | LMB_CLK | I | 1 | clk_100_0000MHz
Bus Connections
INSTANCE | INTERFACE TYPE | INTERFACE NAME
microblaze_0 | MASTER | ILMB
microblaze_0_i_bram_ctrl | SLAVE | SLMB
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_LMB_NUM_SLAVES | 4
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_EXT_RESET_HIGH | 1 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Memorys | TOP
microblaze_0_bram_block Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.
IP Specs
Core | Version | Documentation
bram_block | 1.00.a | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
PORTA | TARGET | XIL_BRAM | microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block | microblaze_0_i_bram_ctrl
PORTB | TARGET | XIL_BRAM | microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block | microblaze_0_d_bram_ctrl
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_MEMSIZE | 2048
C_PORT_DWIDTH | 32
C_PORT_AWIDTH | 32
C_NUM_WE | 4
C_FAMILY | virtex2 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Memory Controllers | TOP
Generic_External_Memory AXI External Memory Controller (SRAM/Flash/Cellular RAM) AXI External Memory Controller (SRAM/Flash/Cellular RAM)
IP Specs
Core | Version | Documentation
axi_emc | 1.03.b | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_100_0000MHz
1 | RdClk | I | 1 | clk_100_0000MHz
2 | Mem_WEN | O | 1 | Linear_Flash_we_n
3 | Mem_OEN | O | 1 | Linear_Flash_oe_n
4 | Mem_DQ | IO | 1 | Linear_Flash_data
5 | Mem_CEN | O | 1 | Linear_Flash_ce_n
6 | Mem_A | O | 1 | 0b0000000000000 & Linear_Flash_address
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI_MEM | SLAVE | AXI | axi4lite_0 | 4 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_INSTANCE | axi_enc_inst
C_S_AXI_EN_REG | 0
C_S_AXI_REG_ADDR_WIDTH | 5
C_S_AXI_REG_DATA_WIDTH | 32
C_S_AXI_MEM_ID_WIDTH | 4
C_S_AXI_MEM_ADDR_WIDTH | 32
C_S_AXI_MEM_DATA_WIDTH | 32
C_S_AXI_MEM_PROTOCOL | axi4
C_S_AXI_REG_PROTOCOL | axi4
C_AXI_CLK_PERIOD_PS | 10000
C_LFLASH_PERIOD_PS | 20000
C_LINEAR_FLASH_SYNC_BURST | 0
C_NUM_BANKS_MEM | 1
C_INCLUDE_NEGEDGE_IOREGS | 0
C_MEM0_WIDTH | 8
C_MEM1_WIDTH | 32
C_MEM2_WIDTH | 32
C_MEM3_WIDTH | 32
C_INCLUDE_DATAWIDTH_MATCHING_0 | 1
C_INCLUDE_DATAWIDTH_MATCHING_1 | 0
C_INCLUDE_DATAWIDTH_MATCHING_2 | 0
C_INCLUDE_DATAWIDTH_MATCHING_3 | 0
C_MEM0_TYPE | 2
C_SYNCH_PIPEDELAY_0 | 2
C_PARITY_TYPE_MEM_0 | 0
C_TCEDV_PS_MEM_0 | 15000
C_TAVDV_PS_MEM_0 | 15000
C_TPACC_PS_FLASH_0 | 25000
C_THZCE_PS_MEM_0 | 7000
C_THZOE_PS_MEM_0 | 7000
C_TWC_PS_MEM_0 | 15000
C_TWP_PS_MEM_0 | 12000
C_TWPH_PS_MEM_0 | 12000
C_TLZWE_PS_MEM_0 | 0
C_WR_REC_TIME_MEM_0 | 100000
C_MEM1_TYPE | 0
C_SYNCH_PIPEDELAY_1 | 2
C_PARITY_TYPE_MEM_1 | 0
C_TCEDV_PS_MEM_1 | 15000
C_TAVDV_PS_MEM_1 | 15000
C_TPACC_PS_FLASH_1 | 25000
C_THZCE_PS_MEM_1 | 7000 |  | Name | Value
C_THZOE_PS_MEM_1 | 7000
C_TWC_PS_MEM_1 | 15000
C_TWP_PS_MEM_1 | 12000
C_TWPH_PS_MEM_1 | 12000
C_TLZWE_PS_MEM_1 | 0
C_WR_REC_TIME_MEM_1 | 100000
C_MEM2_TYPE | 0
C_SYNCH_PIPEDELAY_2 | 2
C_PARITY_TYPE_MEM_2 | 0
C_TCEDV_PS_MEM_2 | 15000
C_TAVDV_PS_MEM_2 | 15000
C_TPACC_PS_FLASH_2 | 25000
C_THZCE_PS_MEM_2 | 7000
C_THZOE_PS_MEM_2 | 7000
C_TWC_PS_MEM_2 | 15000
C_TWP_PS_MEM_2 | 12000
C_TWPH_PS_MEM_2 | 12000
C_TLZWE_PS_MEM_2 | 0
C_WR_REC_TIME_MEM_2 | 100000
C_MEM3_TYPE | 0
C_SYNCH_PIPEDELAY_3 | 2
C_PARITY_TYPE_MEM_3 | 0
C_TCEDV_PS_MEM_3 | 15000
C_TAVDV_PS_MEM_3 | 15000
C_TPACC_PS_FLASH_3 | 25000
C_THZCE_PS_MEM_3 | 7000
C_THZOE_PS_MEM_3 | 7000
C_TWC_PS_MEM_3 | 15000
C_TWP_PS_MEM_3 | 12000
C_TWPH_PS_MEM_3 | 12000
C_TLZWE_PS_MEM_3 | 0
C_WR_REC_TIME_MEM_3 | 100000
C_MAX_MEM_WIDTH | 8
C_S_AXI_REG_BASEADDR | 0xFFFFFFFF
C_S_AXI_REG_HIGHADDR | 0x00000000
C_S_AXI_MEM0_BASEADDR | 0x41480000
C_S_AXI_MEM0_HIGHADDR | 0x414FFFFF
C_S_AXI_MEM1_BASEADDR | 0xFFFFFFFF
C_S_AXI_MEM1_HIGHADDR | 0x00000000
C_S_AXI_MEM2_BASEADDR | 0xFFFFFFFF
C_S_AXI_MEM2_HIGHADDR | 0x00000000
C_S_AXI_MEM3_BASEADDR | 0xFFFFFFFF
C_S_AXI_MEM3_HIGHADDR | 0x00000000 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
microblaze_0_d_bram_ctrl LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
IP Specs
Core | Version | Documentation
lmb_bram_if_cntlr | 3.10.c | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
BRAM_PORT | INITIATOR | XIL_BRAM | microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block | microblaze_0_bram_block
SLMB | SLAVE | LMB | microblaze_0_dlmb | microblaze_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x00003FFF
C_FAMILY | virtex5
C_MASK | 0x00800000
C_MASK1 | 0x00800000
C_MASK2 | 0x00800000
C_MASK3 | 0x00800000
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_ECC | 0
C_INTERCONNECT | 0
C_FAULT_INJECT | 0
C_CE_FAILING_REGISTERS | 0
C_UE_FAILING_REGISTERS | 0
C_ECC_STATUS_REGISTERS | 0
C_ECC_ONOFF_REGISTER | 0
C_ECC_ONOFF_RESET_VALUE | 1
C_CE_COUNTER_WIDTH | 0 |  | Name | Value
C_WRITE_ACCESS | 2
C_NUM_LMB | 1
C_SPLB_CTRL_BASEADDR | 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR | 0x00000000
C_SPLB_CTRL_AWIDTH | 32
C_SPLB_CTRL_DWIDTH | 32
C_SPLB_CTRL_P2P | 0
C_SPLB_CTRL_MID_WIDTH | 1
C_SPLB_CTRL_NUM_MASTERS | 1
C_SPLB_CTRL_SUPPORT_BURSTS | 0
C_SPLB_CTRL_NATIVE_DWIDTH | 32
C_SPLB_CTRL_CLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
microblaze_0_i_bram_ctrl LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus
IP Specs
Core | Version | Documentation
lmb_bram_if_cntlr | 3.10.c | IP
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
BRAM_PORT | INITIATOR | XIL_BRAM | microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block | microblaze_0_bram_block
SLMB | SLAVE | LMB | microblaze_0_ilmb | microblaze_0
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_BASEADDR | 0x00000000
C_HIGHADDR | 0x00003FFF
C_FAMILY | virtex5
C_MASK | 0x00800000
C_MASK1 | 0x00800000
C_MASK2 | 0x00800000
C_MASK3 | 0x00800000
C_LMB_AWIDTH | 32
C_LMB_DWIDTH | 32
C_ECC | 0
C_INTERCONNECT | 0
C_FAULT_INJECT | 0
C_CE_FAILING_REGISTERS | 0
C_UE_FAILING_REGISTERS | 0
C_ECC_STATUS_REGISTERS | 0
C_ECC_ONOFF_REGISTER | 0
C_ECC_ONOFF_RESET_VALUE | 1
C_CE_COUNTER_WIDTH | 0 |  | Name | Value
C_WRITE_ACCESS | 2
C_NUM_LMB | 1
C_SPLB_CTRL_BASEADDR | 0xFFFFFFFF
C_SPLB_CTRL_HIGHADDR | 0x00000000
C_SPLB_CTRL_AWIDTH | 32
C_SPLB_CTRL_DWIDTH | 32
C_SPLB_CTRL_P2P | 0
C_SPLB_CTRL_MID_WIDTH | 1
C_SPLB_CTRL_NUM_MASTERS | 1
C_SPLB_CTRL_SUPPORT_BURSTS | 0
C_SPLB_CTRL_NATIVE_DWIDTH | 32
C_SPLB_CTRL_CLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_ACLK_FREQ_HZ | 100000000
C_S_AXI_CTRL_BASEADDR | 0xFFFFFFFF
C_S_AXI_CTRL_HIGHADDR | 0x00000000
C_S_AXI_CTRL_ADDR_WIDTH | 32
C_S_AXI_CTRL_DATA_WIDTH | 32
C_S_AXI_CTRL_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Peripherals | TOP
RS232_Uart_1 AXI UART (Lite) Generic UART (Universal Asynchronous Receiver/Transmitter) for AXI.
IP Specs
Core | Version | Documentation
axi_uartlite | 1.02.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_100_0000MHz
1 | TX | O | 1 | RS232_Uart_1_sout
2 | RX | I | 1 | RS232_Uart_1_sin
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 4 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_INSTANCE | axi_uartlite_inst
C_S_AXI_ACLK_FREQ_HZ | 100000000
C_BASEADDR | 0x40600000
C_HIGHADDR | 0x4060FFFF
C_S_AXI_ADDR_WIDTH | 4 |  | Name | Value
C_S_AXI_DATA_WIDTH | 32
C_BAUDRATE | 9600
C_DATA_BITS | 8
C_USE_PARITY | 0
C_ODD_PARITY | 1
C_S_AXI_PROTOCOL | AXI4LITE Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
axi_spi_0 AXI SPI Interface AXI to Motorola Serial Peripheral Interface (SPI) adapter
IP Specs
Core | Version | Documentation
axi_spi | 1.02.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | S_AXI_ACLK | I | 1 | clk_100_0000MHz
1 | SPISEL | I | 1 | axi_spi_0_SPISEL
2 | SCK | IO | 1 | axi_spi_0_SCK
3 | MISO | IO | 1 | axi_spi_0_MISO
4 | MOSI | IO | 1 | axi_spi_0_MOSI
5 | SS | IO | 1 | axi_spi_0_SS
Bus Interfaces
NAME | TYPE | BUSSTD | BUS | Connected To
S_AXI | SLAVE | AXI | axi4lite_0 | 4 Peripherals.
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_BASEADDR | 0x40A00000
C_HIGHADDR | 0x40A0FFFF
C_S_AXI_ADDR_WIDTH | 32
C_S_AXI_DATA_WIDTH | 32
C_FIFO_EXIST | 1 |  | Name | Value
C_SCK_RATIO | 32
C_NUM_SS_BITS | 1
C_NUM_TRANSFER_BITS | 8
C_S_AXI_PROTOCOL | AXI4LITE
C_INSTANCE | axi_spi_inst
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
IP | TOP
clock_generator_0 Clock Generator Clock generator for processor system.
IP Specs
Core | Version | Documentation
clock_generator | 4.03.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | LOCKED | O | 1 | proc_sys_reset_0_Dcm_locked
1 | CLKOUT0 | O | 1 | clk_100_0000MHz
2 | RST | I | 1 | RESET_N
3 | CLKIN | I | 1 | CLOCK
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_FAMILY | virtex6
C_DEVICE | NOT_SET
C_PACKAGE | NOT_SET
C_SPEEDGRADE | NOT_SET
C_CLKIN_FREQ | 24000000
C_CLKOUT0_FREQ | 100000000
C_CLKOUT0_PHASE | 0
C_CLKOUT0_GROUP | NONE
C_CLKOUT0_BUF | TRUE
C_CLKOUT0_VARIABLE_PHASE | FALSE
C_CLKOUT1_FREQ | 0
C_CLKOUT1_PHASE | 0
C_CLKOUT1_GROUP | NONE
C_CLKOUT1_BUF | TRUE
C_CLKOUT1_VARIABLE_PHASE | FALSE
C_CLKOUT2_FREQ | 0
C_CLKOUT2_PHASE | 0
C_CLKOUT2_GROUP | NONE
C_CLKOUT2_BUF | TRUE
C_CLKOUT2_VARIABLE_PHASE | FALSE
C_CLKOUT3_FREQ | 0
C_CLKOUT3_PHASE | 0
C_CLKOUT3_GROUP | NONE
C_CLKOUT3_BUF | TRUE
C_CLKOUT3_VARIABLE_PHASE | FALSE
C_CLKOUT4_FREQ | 0
C_CLKOUT4_PHASE | 0
C_CLKOUT4_GROUP | NONE
C_CLKOUT4_BUF | TRUE
C_CLKOUT4_VARIABLE_PHASE | FALSE
C_CLKOUT5_FREQ | 0
C_CLKOUT5_PHASE | 0
C_CLKOUT5_GROUP | NONE
C_CLKOUT5_BUF | TRUE
C_CLKOUT5_VARIABLE_PHASE | FALSE
C_CLKOUT6_FREQ | 0
C_CLKOUT6_PHASE | 0
C_CLKOUT6_GROUP | NONE
C_CLKOUT6_BUF | TRUE
C_CLKOUT6_VARIABLE_PHASE | FALSE
C_CLKOUT7_FREQ | 0
C_CLKOUT7_PHASE | 0
C_CLKOUT7_GROUP | NONE
C_CLKOUT7_BUF | TRUE
C_CLKOUT7_VARIABLE_PHASE | FALSE
C_CLKOUT8_FREQ | 0
C_CLKOUT8_PHASE | 0
C_CLKOUT8_GROUP | NONE
C_CLKOUT8_BUF | TRUE
C_CLKOUT8_VARIABLE_PHASE | FALSE
C_CLKOUT9_FREQ | 0
C_CLKOUT9_PHASE | 0
C_CLKOUT9_GROUP | NONE
C_CLKOUT9_BUF | TRUE
C_CLKOUT9_VARIABLE_PHASE | FALSE
C_CLKOUT10_FREQ | 0 |  | Name | Value
C_CLKOUT10_PHASE | 0
C_CLKOUT10_GROUP | NONE
C_CLKOUT10_BUF | TRUE
C_CLKOUT10_VARIABLE_PHASE | FALSE
C_CLKOUT11_FREQ | 0
C_CLKOUT11_PHASE | 0
C_CLKOUT11_GROUP | NONE
C_CLKOUT11_BUF | TRUE
C_CLKOUT11_VARIABLE_PHASE | FALSE
C_CLKOUT12_FREQ | 0
C_CLKOUT12_PHASE | 0
C_CLKOUT12_GROUP | NONE
C_CLKOUT12_BUF | TRUE
C_CLKOUT12_VARIABLE_PHASE | FALSE
C_CLKOUT13_FREQ | 0
C_CLKOUT13_PHASE | 0
C_CLKOUT13_GROUP | NONE
C_CLKOUT13_BUF | TRUE
C_CLKOUT13_VARIABLE_PHASE | FALSE
C_CLKOUT14_FREQ | 0
C_CLKOUT14_PHASE | 0
C_CLKOUT14_GROUP | NONE
C_CLKOUT14_BUF | TRUE
C_CLKOUT14_VARIABLE_PHASE | FALSE
C_CLKOUT15_FREQ | 0
C_CLKOUT15_PHASE | 0
C_CLKOUT15_GROUP | NONE
C_CLKOUT15_BUF | TRUE
C_CLKOUT15_VARIABLE_PHASE | FALSE
C_CLKFBIN_FREQ | 0
C_CLKFBIN_DESKEW | NONE
C_CLKFBOUT_FREQ | 0
C_CLKFBOUT_PHASE | 0
C_CLKFBOUT_GROUP | NONE
C_CLKFBOUT_BUF | TRUE
C_PSDONE_GROUP | NONE
C_EXT_RESET_HIGH | 0
C_CLK_PRIMITIVE_FEEDBACK_BUF | FALSE
C_CLKOUT0_DUTY_CYCLE | 0.500000
C_CLKOUT1_DUTY_CYCLE | 0.500000
C_CLKOUT2_DUTY_CYCLE | 0.500000
C_CLKOUT3_DUTY_CYCLE | 0.500000
C_CLKOUT4_DUTY_CYCLE | 0.500000
C_CLKOUT5_DUTY_CYCLE | 0.500000
C_CLKOUT6_DUTY_CYCLE | 0.500000
C_CLKOUT7_DUTY_CYCLE | 0.500000
C_CLKOUT8_DUTY_CYCLE | 0.500000
C_CLKOUT9_DUTY_CYCLE | 0.500000
C_CLKOUT10_DUTY_CYCLE | 0.500000
C_CLKOUT11_DUTY_CYCLE | 0.500000
C_CLKOUT12_DUTY_CYCLE | 0.500000
C_CLKOUT13_DUTY_CYCLE | 0.500000
C_CLKOUT14_DUTY_CYCLE | 0.500000
C_CLKOUT15_DUTY_CYCLE | 0.500000
C_CLK_GEN | UPDATE
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
proc_sys_reset_0 Processor System Reset Module Reset management module
IP Specs
Core | Version | Documentation
proc_sys_reset | 3.00.a | IP
| PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# | NAME | DIR | [LSB:MSB] | SIGNAL
0 | MB_Debug_Sys_Rst | I | 1 | proc_sys_reset_0_MB_Debug_Sys_Rst
1 | Dcm_locked | I | 1 | proc_sys_reset_0_Dcm_locked
2 | MB_Reset | O | 1 | proc_sys_reset_0_MB_Reset
3 | Slowest_sync_clk | I | 1 | clk_100_0000MHz
4 | Interconnect_aresetn | O | 1 | proc_sys_reset_0_Interconnect_aresetn
5 | Ext_Reset_In | I | 1 | RESET_N
6 | BUS_STRUCT_RESET | O | 1 | proc_sys_reset_0_BUS_STRUCT_RESET
Parameters
These are the current parameter settings for this module. Parameters marked with yellow indicate parameters set by the user. Parameters marked with blue indicate parameters set by the system.
Name | Value
C_SUBFAMILY | lx
C_EXT_RST_WIDTH | 4
C_AUX_RST_WIDTH | 4
C_EXT_RESET_HIGH | 0
C_AUX_RESET_HIGH | 1
C_NUM_BUS_RST | 1
C_NUM_PERP_RST | 1
C_NUM_INTERCONNECT_ARESETN | 1
C_NUM_PERP_ARESETN | 1
C_FAMILY | virtex5 Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.
Timing Information | TOP Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.