| Rule Violations |
Count |
| Component Clearance Constraint ( Horizontal Gap = -1mm, Vertical Gap = 0.254mm ) (InComponent('R107') or InComponent('R113') or InComponent('R114') or InComponent('R115') or InComponent('R116') or InComponent('R117') or InComponent('R118')),(InComponent('R107') or InComponent('R113') or InComponent('R114') or InComponent('R115') or InComponent('R116') or InComponent('R117') or InComponent('R118')) |
0 |
| Short-Circuit Constraint (Allowed=Yes) (InComponent('IC8') and IsComponentPad and ((Name='IC8-H14') or (Name='IC8-C10') or (Name='IC8-A11') or (Name='IC8-A12') )),(All) |
0 |
| Width Constraint (Min=0.1mm) (Max=10mm) (Preferred=0.2mm) (All) |
0 |
| Component Clearance Constraint ( Horizontal Gap = -1mm, Vertical Gap = Infinite ) (InComponent('IC9')),(InComponent('IC10')) |
0 |
| Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.3mm) (Prefered=0.2mm) and Width Constraints (Min=0.1mm) (Max=0.3mm) (Prefered=0.2mm) (InNetClass('RX_RF')) |
0 |
| Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.3mm) (Prefered=0.2mm) and Width Constraints (Min=0.1mm) (Max=0.3mm) (Prefered=0.2mm) (InNetClass('TX_RF')) |
0 |
| Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.3mm) (Prefered=0.1mm) and Width Constraints (Min=0.2mm) (Max=0.2mm) (Prefered=0.2mm) (InNetClass('FX3_DATA')) |
0 |
| Matched Lengths(Tolerance=0.5mm) (InNetClass('LMS_PORT2')) |
0 |
| Matched Lengths(Tolerance=0.5mm) (InNetClass('LMS_PORT1')) |
0 |
| Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.2mm) (Prefered=0.1mm) and Width Constraints (Min=0.1mm) (Max=0.4mm) (Prefered=0.1mm) (InNetClass('DDR2_1_CK') or InNetClass('DDR2_1_CK')) |
0 |
| Modified Polygon (Allow modified: No), (Allow shelved: No) |
0 |
| Height Constraint (Min=0mm) (Max=2.67mm) (Prefered=2.67mm) (OnBottomLayer) |
0 |
| Component Clearance Constraint ( Horizontal Gap = 0.01mm, Vertical Gap = 0.254mm ) (All),(All) |
0 |
| Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.3mm) (Prefered=0.1mm) and Width Constraints (Min=0.1mm) (Max=0.5mm) (Prefered=0.2mm) (All) |
0 |
| Height Constraint (Min=0mm) (Max=14.47mm) (Prefered=14.47mm) (OnTopLayer) |
0 |
| Hole Size Constraint (Min=0.2mm) (Max=10mm) (All) |
0 |
| Pads and Vias to follow the Drill pairs settings |
0 |
| Routing Via (MinHoleWidth=0.2mm) (MaxHoleWidth=4.5mm) (PreferredHoleWidth=0.2mm) (MinWidth=0.31mm) (MaxWidth=5mm) (PreferedWidth=0.4mm) (All) |
0 |
| Width Constraint (Min=0.1mm) (Max=5mm) (Preferred=0.2mm) (All) |
0 |
| Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) |
0 |
| Un-Routed Net Constraint ( (All) ) |
0 |
| Short-Circuit Constraint (Allowed=No) (All),(All) |
0 |
| Clearance Constraint (Gap=0.1mm) (All),(All) |
0 |
| Routing Layers(All) |
0 |
| Hole To Hole Clearance (Gap=0.15mm) (All),(All) |
0 |
| Net Antennae (Tolerance=0mm) (All) |
0 |
| Matched Lengths(Tolerance=0.5mm) (InNetClass('DDR2_2_DQ[0..15]')) |
0 |
| Matched Lengths(Tolerance=0.5mm) (InNetClass('DDR2_2_A[0..12]')) |
0 |
| Matched Lengths(Tolerance=0.5mm) (InNetClass('DDR2_1_DQ[0..15]')) |
0 |
| Matched Lengths(Tolerance=0.5mm) (InNetClass('DDR2_1_A[0..12]')) |
0 |
| Differential Pairs Uncoupled Length using the Gap Constraints (Min=0.1mm) (Max=0.2mm) (Prefered=0.1mm) and Width Constraints (Min=0.1mm) (Max=0.4mm) (Prefered=0.1mm) (InNet('FX3_XTAL_N') or InNet('FX3_XTAL_P')) |
0 |
| Total |
0 |
