/** * Thunderbolt For Alpine Ridge * Large parts (link training and enumeration) * taken from decompiled Mac AML. * Note: USB/CIO RTD3 power management largly * missing due to lack of GPIO pins. * * Copyright (c) 2019 osy86 */ #ifndef SSDT_NAME #define SSDT_NAME "TbtOnPCH" #endif DefinitionBlock ("", "SSDT", 2, "OSY86 ", SSDT_NAME, 0x00001000) { #ifndef TARGET #error "Must define TARGET" #endif #define XSTR(x) #x #define STR(x) XSTR(x) #include STR(SSDT-TbtOnPCH-TARGET.asl) /* Support methods */ External (DTGP, MethodObj) External (OSDW, MethodObj) // OS Is Darwin? External (\RMDT.P1, MethodObj) // Debug printing External (\RMDT.P2, MethodObj) // Debug printing External (\RMDT.P3, MethodObj) // Debug printing Scope (\_GPE) { Method (TBT_HOTPLUG_GPE, 0, NotSerialized) // _Exx: Edge-Triggered GPE { TBT_ROOT.DBG1 ("Hot plug event") If (!TBT_ROOT.OHPE ()) { Return } #ifndef NO_WINDOWS_SUPPORT If (!OSDW ()) { If (TBT_ROOT.POC0 == One) { Return } Sleep (400) If (TBT_ROOT.WTLT () == One) { TBT_ROOT.ICMS () } Else // force power off { //\_SB.SGOV (0x01070004, Zero) //\_SB.SGDO (0x01070004) } If (TBT_ROOT.UPMB) { TBT_ROOT.UPMB = Zero Sleep (One) } TBT_ROOT.CMPE () } /* ElseIf (\_SB.GGII (0x01070015) == One) { \_SB.SGII (0x01070015, Zero) } Else { \_SB.SGII (0x01070015, One) } */ Else { TBT_ROOT.UPSB.AMPE () } #else // NO_WINDOWS_SUPPORT TBT_ROOT.UPSB.AMPE () #endif TBT_ROOT.DBG1 ("End hotplug handler") } } Name(U2OP, TBT_HAS_COMPANION) // use companion controller Scope (TBT_ROOT) { // Use https://github.com/RehabMan/OS-X-ACPI-Debug // to see debug messages Method (DBG1, 1, NotSerialized) { If (CondRefOf (\RMDT.P1)) { \RMDT.P1 (Arg0) } } Method (DBG2, 2, NotSerialized) { If (CondRefOf (\RMDT.P2)) { \RMDT.P2 (Arg0, Arg1) } } Method (DBG3, 3, NotSerialized) { If (CondRefOf (\RMDT.P3)) { \RMDT.P3 (Arg0, Arg1, Arg2) } } #ifndef NO_WINDOWS_SUPPORT #include "SSDT-TbtOnPCH-Boot.asl" #endif Name (IIP3, Zero) Name (PRSR, Zero) Name (PCIA, One) /** * Bring up PCI link * Train downstream link */ Method (PCEU, 0, Serialized) { TBT_ROOT.PRSR = Zero If (TBT_ROOT.PSTA != Zero) { TBT_ROOT.PRSR = One TBT_ROOT.PSTA = Zero } If (TBT_ROOT.LDXX == One) { TBT_ROOT.PRSR = One TBT_ROOT.LDXX = Zero } } /** * Bring down PCI link */ Method (PCDA, 0, Serialized) { If (TBT_ROOT.POFF () != Zero) { TBT_ROOT.PCIA = Zero TBT_ROOT.PSTA = 0x03 TBT_ROOT.LDXX = One Local5 = (Timer + 10000000) While (Timer <= Local5) { If (TBT_ROOT.LACR == One) { If (TBT_ROOT.LACT == Zero) { Break } } ElseIf (TBT_ROOT.UPSB.AVND == 0xFFFFFFFF) { Break } Sleep (10) } TBT_ROOT.GPCI = Zero TBT_ROOT.UGIO () } Else { } TBT_ROOT.IIP3 = One } /** * Returns true if both TB and TB-USB are idle */ Method (POFF, 0, Serialized) { Return ((!TBT_ROOT.RTBT && !TBT_ROOT.RUSB)) } Name (GPCI, One) Name (GNHI, One) Name (GXCI, One) Name (RTBT, One) Name (RUSB, One) Name (CTPD, Zero) /** * Send power down ack to CP */ Method (CTBT, 0, Serialized) { //If ((GGDV (0x01070004) == One) && (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF)) If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) { Local2 = TBT_ROOT.UPSB.CRMW (0x3C, Zero, 0x02, 0x04000000, 0x04000000) If (Local2 == Zero) { TBT_ROOT.CTPD = One } } } /** * Toggle controller power * Power controllers either up or down depending on the request. * On Macs, there's two GPIO signals for controlling TB and XHC * separately. If such signals exist, we need to find it. Otherwise * we lose the power saving capabilities. * Returns if controller is powered up */ Method (UGIO, 0, Serialized) { // Which controller is requested to be on? Local0 = (TBT_ROOT.GNHI || TBT_ROOT.RTBT) // TBT Local1 = (TBT_ROOT.GXCI || TBT_ROOT.RUSB) // USB DBG3 ("UGIO", Local0, Local1) If (TBT_ROOT.GPCI != Zero) { // if neither are requested to be on but the NHI controller // needs to be up, then we go ahead and power it on anyways If ((Local0 == Zero) && (Local1 == Zero)) { Local0 = One Local1 = One } } Local2 = Zero /** * Force power to CIO */ If (Local0 != Zero) { // TODO: check if CIO power is forced //If (GGDV (0x01070004) == Zero) If (Zero) { // TODO: force CIO power //SGDI (0x01070004) Local2 = One TBT_ROOT.CTPD = Zero } } /** * Force power to USB */ If (Local1 != Zero) { // TODO: check if USB power is forced //If (GGDV (0x01070007) == Zero) If (Zero) { // TODO: force USB power //SGDI (0x01070007) Local2 = One } } // if we did power on If (Local2 != Zero) { Sleep (500) } Local3 = Zero /** * Disable force power to CIO */ If (Local0 == Zero) { // TODO: check if CIO power is off //If (GGDV (0x01070004) == One) If (Zero) { TBT_ROOT.CTBT () If (TBT_ROOT.CTPD != Zero) { // TODO: force power off CIO //SGOV (0x01070004, Zero) //SGDO (0x01070004) Local3 = One } } } /** * Disable force power to USB */ If (Local1 == Zero) { //If (GGDV (0x01070007) == One) If (Zero) { // TODO: force power off USB //SGOV (0x01070007, Zero) //SGDO (0x01070007) Local3 = One } } // if we did power down, wait for things to settle If (Local3 != Zero) { Sleep (100) } DBG3 ("UGIO finish", Local2, Local3) Return (Local2) } Method (_PS0, 0, Serialized) // _PS0: Power State 0 { If (OSDW ()) { PCEU () } } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { If (OSDW ()) { If (TBT_ROOT.POFF () != Zero) { TBT_ROOT.CTBT () } PCDA () } } Method (UTLK, 2, Serialized) { Local0 = Zero // if CIO force power is zero //If ((GGOV (0x01070004) == Zero) && (GGDV (0x01070004) == Zero)) If (Zero) { TBT_ROOT.PSTA = Zero While (One) { If (TBT_ROOT.LDXX == One) { TBT_ROOT.LDXX = Zero } // here, we force CIO power on //SGDI (0x01070004) Local1 = Zero Local2 = (Timer + 10000000) While (Timer <= Local2) { If (TBT_ROOT.LACR == Zero) { If (TBT_ROOT.LTRN != One) { Break } } ElseIf ((TBT_ROOT.LTRN != One) && (TBT_ROOT.LACT == One)) { Break } Sleep (10) } Sleep (Arg1) While (Timer <= Local2) { If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) { Local1 = One Break } Sleep (10) } If (Local1 == One) { TBT_ROOT.MABT = One Break } If (Local0 == 0x04) { Break } Local0++ // CIO force power back to 0 //SGOV (0x01070004, Zero) //SGDO (0x01070004) Sleep (1000) } } } OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (HD94, PCI_Config, 0x0D94, 0x08) Field (HD94, ByteAcc, NoLock, Preserve) { Offset (0x04), PLEQ, 1, Offset (0x08) } OperationRegion (A1E1, PCI_Config, 0x40, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDXX, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0xA0, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (UPSB) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) // visible for everyone } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } /** * Enable downstream link */ Method (PCED, 0, Serialized) { TBT_ROOT.GPCI = One // power up the controller If (TBT_ROOT.UGIO () != Zero) { TBT_ROOT.PRSR = One } Local0 = Zero Local1 = Zero If (Local1 == Zero) { If (TBT_ROOT.IIP3 != Zero) { TBT_ROOT.PRSR = One Local0 = One TBT_ROOT.LDXX = One } } Local5 = (Timer + 10000000) If (TBT_ROOT.PRSR != Zero) { Sleep (30) If ((Local0 != Zero) || (Local1 != Zero)) { TBT_ROOT.TSPD = One If (Local1 != Zero) {} ElseIf (Local0 != Zero) { TBT_ROOT.LDXX = Zero } While (Timer <= Local5) { If (TBT_ROOT.LACR == Zero) { If (TBT_ROOT.LTRN != One) { Break } } ElseIf ((TBT_ROOT.LTRN != One) && (TBT_ROOT.LACT == One)) { Break } Sleep (10) } Sleep (120) While (Timer <= Local5) { If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) { Break } Sleep (10) } TBT_ROOT.TSPD = 0x03 TBT_ROOT.LRTN = One } Local5 = (Timer + 10000000) While (Timer <= Local5) { If (TBT_ROOT.LACR == Zero) { If (TBT_ROOT.LTRN != One) { Break } } ElseIf ((TBT_ROOT.LTRN != One) && (TBT_ROOT.LACT == One)) { Break } Sleep (10) } Sleep (250) } TBT_ROOT.PRSR = Zero While (Timer <= Local5) { If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) { Break } Sleep (10) } If (TBT_ROOT.CSPD != 0x03) { If (TBT_ROOT.SSPD == 0x03) { If (TBT_ROOT.UPSB.SSPD == 0x03) { If (TBT_ROOT.TSPD != 0x03) { TBT_ROOT.TSPD = 0x03 } If (TBT_ROOT.UPSB.TSPD != 0x03) { TBT_ROOT.UPSB.TSPD = 0x03 } TBT_ROOT.LRTN = One Local2 = (Timer + 10000000) While (Timer <= Local2) { If (TBT_ROOT.LACR == Zero) { If ((TBT_ROOT.LTRN != One) && (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF)) { TBT_ROOT.PCIA = One Local1 = One Break } } ElseIf (((TBT_ROOT.LTRN != One) && (TBT_ROOT.LACT == One)) && (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF)) { TBT_ROOT.PCIA = One Local1 = One Break } Sleep (10) } } Else { TBT_ROOT.PCIA = One } } Else { TBT_ROOT.PCIA = One } } Else { TBT_ROOT.PCIA = One } TBT_ROOT.IIP3 = Zero } /** * Hotplug notify * Called by ACPI */ Method (AMPE, 0, Serialized) { Notify (TBT_ROOT.UPSB.DSB0.NHI0, Zero) // Bus Check } /** * Hotplug notify * MUST called by NHI driver indicating cable plug-in * This passes the message to the XHC driver */ Method (UMPE, 0, Serialized) { Notify (TBT_ROOT.UPSB.DSB2.XHC2, Zero) // Bus Check #ifdef XHC_ROOT Notify (XHC_ROOT, Zero) // Bus Check #endif } Name (MDUV, One) // plug status /** * Cable status callback * Called from NHI driver on hotplug */ Method (MUST, 1, Serialized) { DBG2 ("MUST", Arg0) If (OSDW ()) { If (MDUV != Arg0) { MDUV = Arg0 UMPE () } } Return (Zero) } Method (_PS0, 0, Serialized) // _PS0: Power State 0 { If (OSDW ()) { PCED () // enable downlink // some magical commands to CIO #ifdef THUNDERBOLT_TITAN_RIDGE TBT_ROOT.UPSB.CRMW (0x0150, Zero, 0x02, 0x04000000, 0x04000000) TBT_ROOT.UPSB.CRMW (0x0250, Zero, 0x02, 0x04000000, 0x04000000) #else TBT_ROOT.UPSB.CRMW (0x013E, Zero, 0x02, 0x0200, 0x0200) TBT_ROOT.UPSB.CRMW (0x023E, Zero, 0x02, 0x0200, 0x0200) #endif } } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { #ifndef NO_WINDOWS_SUPPORT If (!OSDW ()) { If (TBT_ROOT.UPCK () == Zero) { TBT_ROOT.UTLK (One, 1000) } TBT_ROOT.TBTC (0x05) } #endif } OperationRegion (H548, PCI_Config, 0x0548, 0x20) Field (H548, DWordAcc, Lock, Preserve) { T2PC, 32, PC2T, 32 } OperationRegion (H530, PCI_Config, 0x0530, 0x0C) Field (H530, DWordAcc, Lock, Preserve) { DWIX, 13, PORT, 6, SPCE, 2, CMD0, 1, CMD1, 1, CMD2, 1, , 6, PROG, 1, TMOT, 1, WDAT, 32, RDAT, 32 } /** * CIO write */ Method (CIOW, 4, Serialized) { WDAT = Arg3 DWIX = Arg0 PORT = Arg1 SPCE = Arg2 CMD0 = One CMD1 = Zero CMD2 = Zero TMOT = Zero PROG = One Local1 = One Local0 = 0x2710 While (Zero < Local0) { If (PROG == Zero) { Local1 = Zero Break } Stall (0x19) Local0-- } If (Local1 == Zero) { Local1 = TMOT /* \_SB_.PCI0.RP05.UPSB.TMOT */ } Return (Local1) } /** * CIO read */ Method (CIOR, 3, Serialized) { RDAT = Zero DWIX = Arg0 PORT = Arg1 SPCE = Arg2 CMD0 = Zero CMD1 = Zero CMD2 = Zero TMOT = Zero PROG = One Local1 = One Local0 = 0x2710 While (Zero < Local0) { If (PROG == Zero) { Local1 = Zero Break } Stall (0x19) Local0-- } If (Local1 == Zero) { Local1 = TMOT /* \_SB_.PCI0.RP05.UPSB.TMOT */ } If (Local1 == Zero) { Return (Package (0x02) { Zero, RDAT }) } Else { Return (Package (0x02) { One, RDAT }) } } /** * CIO Read Modify Write */ Method (CRMW, 5, Serialized) { Local1 = One //If (((GGDV (0x01070004) == One) || (GGDV (0x01070007) == One)) && If (TBT_ROOT.UPSB.AVND != 0xFFFFFFFF) { Local3 = Zero While (Local3 <= 0x04) { Local2 = CIOR (Arg0, Arg1, Arg2) If (DerefOf (Local2 [Zero]) == Zero) { Local2 = DerefOf (Local2 [One]) Local2 &= ~Arg4 Local2 |= Arg3 Local2 = CIOW (Arg0, Arg1, Arg2, Local2) If (Local2 == Zero) { Local2 = CIOR (Arg0, Arg1, Arg2) If (DerefOf (Local2 [Zero]) == Zero) { Local2 = DerefOf (Local2 [One]) Local2 &= Arg4 If (Local2 == Arg3) { Local1 = Zero Break } } } } Local3++ Sleep (100) } } DBG3 ("CRMW", Arg0, Local1) Return (Local1) } /** * Not used anywhere AFAIK */ Method (LSTX, 2, Serialized) { If (T2PC != 0xFFFFFFFF) { Local0 = Zero If ((T2PC & One) && One) { Local0 = One } If (Local0 == Zero) { Local1 = 0x2710 While (Zero < Local1) { If (T2PC == Zero) { Break } Stall (0x19) Local1-- } If (Zero == Local1) { Local0 = One } } If (Local0 == Zero) { Local1 = One Local1 |= 0x14 Local1 |= (Arg0 << 0x08) Local1 |= (Arg1 << 0x0C) Local1 |= 0x00400000 PC2T = Local1 } If (Local0 == Zero) { Local1 = 0x2710 While (Zero < Local1) { If (T2PC == 0x15) { Break } Stall (0x19) Local1-- } If (Zero == Local1) { Local0 = One } } PC2T = Zero } } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Name (IIP3, Zero) Name (PRSR, Zero) Name (PCIA, One) Method (PCEU, 0, Serialized) { TBT_ROOT.UPSB.DSB0.PRSR = Zero If (TBT_ROOT.UPSB.DSB0.PSTA != Zero) { TBT_ROOT.UPSB.DSB0.PRSR = One TBT_ROOT.UPSB.DSB0.PSTA = Zero } If (TBT_ROOT.UPSB.DSB0.LDIS == One) { TBT_ROOT.UPSB.DSB0.PRSR = One TBT_ROOT.UPSB.DSB0.LDIS = Zero } } Method (PCDA, 0, Serialized) { If (TBT_ROOT.UPSB.DSB0.POFF () != Zero) { TBT_ROOT.UPSB.DSB0.PCIA = Zero TBT_ROOT.UPSB.DSB0.PSTA = 0x03 TBT_ROOT.UPSB.DSB0.LDIS = One Local5 = (Timer + 10000000) While (Timer <= Local5) { If (TBT_ROOT.UPSB.DSB0.LACR == One) { If (TBT_ROOT.UPSB.DSB0.LACT == Zero) { Break } } ElseIf (TBT_ROOT.UPSB.DSB0.NHI0.AVND == 0xFFFFFFFF) { Break } Sleep (10) } TBT_ROOT.GNHI = Zero TBT_ROOT.UGIO () } Else { } TBT_ROOT.UPSB.DSB0.IIP3 = One } Method (POFF, 0, Serialized) { Return (!TBT_ROOT.RTBT) } Method (_PS0, 0, Serialized) // _PS0: Power State 0 { If (OSDW ()) { PCEU () } } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { If (OSDW ()) { PCDA () } } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (OSDW ()) { If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) { Local0 = Package (0x02) { "PCIHotplugCapable", Zero } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Return (Zero) } Device (NHI0) { Name (_ADR, Zero) // _ADR: Address Name (_STR, Unicode ("Thunderbolt")) // _STR: Description String /** * Enable downstream link */ Method (PCED, 0, Serialized) { TBT_ROOT.GNHI = One // we should not need to force power since // UPSX init should already have done so! If (TBT_ROOT.UGIO () != Zero) { TBT_ROOT.UPSB.DSB0.PRSR = One } // Do some link training Local0 = Zero Local1 = Zero Local5 = (Timer + 10000000) If (TBT_ROOT.UPSB.DSB0.PRSR != Zero) { Local5 = (Timer + 10000000) While (Timer <= Local5) { If (TBT_ROOT.UPSB.DSB0.LACR == Zero) { If (TBT_ROOT.UPSB.DSB0.LTRN != One) { Break } } ElseIf ((TBT_ROOT.UPSB.DSB0.LTRN != One) && (TBT_ROOT.UPSB.DSB0.LACT == One)) { Break } Sleep (10) } Sleep (150) } TBT_ROOT.UPSB.DSB0.PRSR = Zero While (Timer <= Local5) { If (TBT_ROOT.UPSB.DSB0.NHI0.AVND != 0xFFFFFFFF) { TBT_ROOT.UPSB.DSB0.PCIA = One Break } Sleep (10) } TBT_ROOT.UPSB.DSB0.IIP3 = Zero } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x10), BAR1, 32, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } /** * Run Time Power Check * Called by NHI driver when link is idle. * Once both XHC and NHI idle, we can power down. */ Method (RTPC, 1, Serialized) { If (OSDW ()) { If (Arg0 <= One) { TBT_ROOT.RTBT = Arg0 } } Return (Zero) } /** * Cable detection callback * Called by NHI driver on hotplug */ Method (MUST, 1, Serialized) { Return (TBT_ROOT.UPSB.MUST (Arg0)) } Method (_PS0, 0, Serialized) // _PS0: Power State 0 { If (OSDW ()) { PCED () TBT_ROOT.CTBT () } } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (OSDW ()) { Local0 = Package (0x03) { "power-save", One, Buffer (One) { 0x00 /* . */ } } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Return (Zero) } /** * Late sleep force power * NHI driver sends a sleep cmd to TB controller * But we might be sleeping at this time. So this will * force the power on right before sleep. */ Method (SXFP, 1, Serialized) { DBG2 ("SXFP", Arg0) If (Arg0 == Zero) { //If (GGDV (0x01070007) == One) //{ // SGOV (0x01070007, Zero) // SGDO (0x01070007) // Sleep (0x64) //} //SGOV (0x01070004, Zero) //SGDO (0x01070004) } } } } Device (DSB1) { Name (_ADR, 0x00010000) // _ADR: Address Name (_SUN, One) // _SUN: Slot User Number OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB3.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB4.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB1.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB2) { Name (_ADR, 0x00020000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB2.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Name (IIP3, Zero) Name (PRSR, Zero) Name (PCIA, One) /** * Enable upstream link */ Method (PCEU, 0, Serialized) { TBT_ROOT.UPSB.DSB2.PRSR = Zero If (TBT_ROOT.UPSB.DSB2.PSTA != Zero) { TBT_ROOT.UPSB.DSB2.PRSR = One TBT_ROOT.UPSB.DSB2.PSTA = Zero } If (TBT_ROOT.UPSB.DSB2.LDIS == One) { TBT_ROOT.UPSB.DSB2.PRSR = One TBT_ROOT.UPSB.DSB2.LDIS = Zero } } /** * PCI disable link */ Method (PCDA, 0, Serialized) { If (TBT_ROOT.UPSB.DSB2.POFF () != Zero) { TBT_ROOT.UPSB.DSB2.PCIA = Zero TBT_ROOT.UPSB.DSB2.PSTA = 0x03 TBT_ROOT.UPSB.DSB2.LDIS = One Local5 = (Timer + 10000000) While (Timer <= Local5) { If (TBT_ROOT.UPSB.DSB2.LACR == One) { If (TBT_ROOT.UPSB.DSB2.LACT == Zero) { Break } } ElseIf (TBT_ROOT.UPSB.DSB2.XHC2.AVND == 0xFFFFFFFF) { Break } Sleep (10) } TBT_ROOT.GXCI = Zero TBT_ROOT.UGIO () // power down if needed } Else { } TBT_ROOT.UPSB.DSB2.IIP3 = One } /** * Is power saving requested? */ Method (POFF, 0, Serialized) { Return (!TBT_ROOT.RUSB) } Method (_PS0, 0, Serialized) // _PS0: Power State 0 { If (OSDW ()) { PCEU () } } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { If (OSDW ()) { PCDA () } } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (OSDW ()) { If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) { Local0 = Package (0x02) { "PCIHotplugCapable", Zero } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Return (Zero) } Device (XHC2) { Name (_ADR, Zero) // _ADR: Address Name (SDPC, Zero) OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } /** * PCI Enable downstream */ Method (PCED, 0, Serialized) { TBT_ROOT.GXCI = One // this powers up both TBT and USB when needed If (TBT_ROOT.UGIO () != Zero) { TBT_ROOT.UPSB.DSB2.PRSR = One } // Do some link training Local0 = Zero Local1 = Zero Local5 = (Timer + 10000000) If (TBT_ROOT.UPSB.DSB2.PRSR != Zero) { Local5 = (Timer + 10000000) While (Timer <= Local5) { If (TBT_ROOT.UPSB.DSB2.LACR == Zero) { If (TBT_ROOT.UPSB.DSB2.LTRN != One) { Break } } ElseIf ((TBT_ROOT.UPSB.DSB2.LTRN != One) && (TBT_ROOT.UPSB.DSB2.LACT == One)) { Break } Sleep (10) } Sleep (150) } TBT_ROOT.UPSB.DSB2.PRSR = Zero While (Timer <= Local5) { If (TBT_ROOT.UPSB.DSB2.XHC2.AVND != 0xFFFFFFFF) { TBT_ROOT.UPSB.DSB2.PCIA = One Break } Sleep (10) } TBT_ROOT.UPSB.DSB2.IIP3 = Zero } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (U2OP == One) { Local0 = Package (0x06) { "USBBusNumber", Zero, "AAPL,xhci-clock-id", One, "UsbCompanionControllerPresent", One } } Else { Local0 = Package (0x04) { "USBBusNumber", Zero, "AAPL,xhci-clock-id", One } } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } Name (HS, Package (0x01) { "XHC" }) Name (FS, Package (0x01) { "XHC" }) Name (LS, Package (0x01) { "XHC" }) Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake { If (OSDW ()) { Return (Package (0x02) { 0x6D, 0x04 }) } Else { Return (Package (0x02) { 0x6D, 0x03 }) } } Method (_PS0, 0, Serialized) // _PS0: Power State 0 { If (OSDW ()) { PCED () } } Method (_PS3, 0, Serialized) // _PS3: Power State 3 { } /** * Run Time Power Check * Called by XHC driver when idle */ Method (RTPC, 1, Serialized) { If (OSDW ()) { If (Arg0 <= One) { TBT_ROOT.RUSB = Arg0 } } Return (Zero) } /** * USB cable check * Called by XHC driver to check cable status * Used as idle hint. */ Method (MODU, 0, Serialized) { Return (TBT_ROOT.UPSB.MDUV) } Device (RHUB) { Name (_ADR, Zero) // _ADR: Address Device (SSP1) { Name (_ADR, 0x03) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { ToPLD ( PLD_Revision = 0x1, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x1, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "UPPER", PLD_HorizontalPosition = "LEFT", PLD_Shape = "UNKNOWN", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0) }) Name (HS, Package (0x02) { "XHC", TBT_USB_PORT_1_COMPANION }) Name (FS, Package (0x02) { "XHC", TBT_USB_PORT_1_COMPANION }) Name (LS, Package (0x02) { "XHC", TBT_USB_PORT_1_COMPANION }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (U2OP == One) { Local0 = Package (0x0A) { "UsbCPortNumber", 0x03, "UsbPowerSource", 0x03, "kUSBWakePortCurrentLimit", 0x0BB8, "kUSBSleepPortCurrentLimit", 0x0BB8, "UsbCompanionPortPresent", One } } Else { Local0 = Package (0x08) { "UsbCPortNumber", 0x03, "UsbPowerSource", 0x03, "kUSBWakePortCurrentLimit", 0x0BB8, "kUSBSleepPortCurrentLimit", 0x0BB8 } } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Device (SSP2) { Name (_ADR, 0x04) // _ADR: Address Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, Package (0x01) // _PLD: Physical Location of Device { ToPLD ( PLD_Revision = 0x1, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x1, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "UPPER", PLD_HorizontalPosition = "LEFT", PLD_Shape = "UNKNOWN", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0) }) Name (HS, Package (0x02) { "XHC", TBT_USB_PORT_2_COMPANION }) Name (FS, Package (0x02) { "XHC", TBT_USB_PORT_2_COMPANION }) Name (LS, Package (0x02) { "XHC", TBT_USB_PORT_2_COMPANION }) Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (U2OP == One) { Local0 = Package (0x0A) { "UsbCPortNumber", 0x04, "UsbPowerSource", 0x04, "kUSBWakePortCurrentLimit", 0x0BB8, "kUSBSleepPortCurrentLimit", 0x0BB8, "UsbCompanionPortPresent", One } } Else { Local0 = Package (0x0A) { "UsbCPortNumber", 0x04, "UsbPowerSource", 0x04, "kUSBWakePortCurrentLimit", 0x0BB8, "kUSBSleepPortCurrentLimit", 0x0BB8, "UsbCompanionPortPresent", Zero } } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address Name (_SUN, 0x02) // _SUN: Slot User Number OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } OperationRegion (A1E1, PCI_Config, 0xC0, 0x40) Field (A1E1, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), Offset (0x08), Offset (0x0A), , 5, TPEN, 1, Offset (0x0C), SSPD, 4, , 16, LACR, 1, Offset (0x10), , 4, LDIS, 1, LRTN, 1, Offset (0x12), CSPD, 4, CWDT, 6, , 1, LTRN, 1, , 1, LACT, 1, Offset (0x14), Offset (0x30), TSPD, 4 } OperationRegion (A1E2, PCI_Config, 0x80, 0x08) Field (A1E2, ByteAcc, NoLock, Preserve) { Offset (0x01), Offset (0x02), Offset (0x04), PSTA, 2 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB3.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (UPS0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (ARE0, PCI_Config, Zero, 0x04) Field (ARE0, ByteAcc, NoLock, Preserve) { AVND, 16 } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DSB0) { Name (_ADR, Zero) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1, Offset (0x3E), , 6, SBRS, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB0.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB3) { Name (_ADR, 0x00030000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB3.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB4) { Name (_ADR, 0x00040000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB4.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } Device (DEV0) { Name (_ADR, Zero) // _ADR: Address Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB4.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Device (DSB5) { Name (_ADR, 0x00050000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB5.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } Device (DSB6) { Name (_ADR, 0x00060000) // _ADR: Address OperationRegion (A1E0, PCI_Config, Zero, 0x40) Field (A1E0, ByteAcc, NoLock, Preserve) { AVND, 32, BMIE, 3, Offset (0x18), PRIB, 8, SECB, 8, SUBB, 8, Offset (0x1E), , 13, MABT, 1 } Method (_BBN, 0, NotSerialized) // _BBN: BIOS Bus Number { Return (SECB) /* \_SB_.PCI0.RP05.UPSB.DSB4.UPS0.DSB6.SECB */ } Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Method (_RMV, 0, NotSerialized) // _RMV: Removal Status { If (OSDW ()) { Return (One) } Return (Zero) } } } } Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method { If (OSDW ()) { If (Arg0 == ToUUID ("a0b5b7c6-1318-441c-b0c9-fe695eaf949b")) { Local0 = Package (0x02) { "PCI-Thunderbolt", One } DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) Return (Local0) } } Return (Zero) } } } }