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LDA STA PHA PLA ASL ASR TXA TAX INX DEX ADD SUB AND OR XOR CMP RTS JNZ JZ JSR JMP
IMP0x00x80x100x180x200x280x300x380x400x480x500x580x600x680x700x780x800x880x900x980xa0
IMM0x10x90x110x190x210x290x310x390x410x490x510x590x610x690x710x790x810x890x910x990xa1
ABS0x20xa0x120x1a0x220x2a0x320x3a0x420x4a0x520x5a0x620x6a0x720x7a0x820x8a0x920x9a0xa2
REL0x30xb0x130x1b0x230x2b0x330x3b0x430x4b0x530x5b0x630x6b0x730x7b0x830x8b0x930x9b0xa3
IDX0x40xc0x140x1c0x240x2c0x340x3c0x440x4c0x540x5c0x640x6c0x740x7c0x840x8c0x940x9c0xa4
" ], "text/plain": [ "" ] }, "execution_count": 1, "metadata": {}, "output_type": "execute_result" } ], "source": [ "# OPCODES\n", "# instruction: 00000---\n", "# addressing mode: -----000\n", "from collections import namedtuple\n", "\n", "Adm = namedtuple('Adm', ['IMP', 'IMM', 'ABS', 'REL', 'IDX'])\n", "Opc = namedtuple('Opc', [\n", " 'LDA', 'STA', 'PHA', 'PLA', 'ASL', 'ASR', 'TXA', 'TAX',\n", " 'INX', 'DEX', 'ADD', 'SUB', 'AND', 'OR', 'XOR', 'CMP',\n", " 'RTS', 'JNZ', 'JZ', 'JSR', 'JMP'\n", "])\n", "opc = Opc(*range(21))\n", "adm = Adm(*range(5))\n", " \n", "import pandas as pd\n", "import numpy as np\n", "\n", "df = pd.DataFrame(columns=[*opc._asdict()])\n", "for n,i in adm._asdict().items():\n", " df.loc[n] = (np.left_shift(pd.Series(opc._asdict()),3) + i).apply(hex)\n", "\n", "allowed = [0x1, 0x2, 0x4, 0xa, 0xc, 0x10, 0x18, 0x21, 0x29, 0x30, 0x38, 0x40, 0x48, 0x51, 0x59, 0x61, 0x69, 0x71, 0x79, 0x80, 0x8b, 0x93, 0x9a, 0xa2]\n", "df.style.applymap(lambda v: 'background-color: #f55' if not int(v, 16) in allowed else 'background-color: #5f5')\n" ] }, { "cell_type": "code", "execution_count": 2, "metadata": {}, "outputs": [], "source": [ "# ROM source\n", "src = \"\"\"\n", "; testing some basic instructions\n", "lda #$0\n", "tax\n", "_1:\n", "sta range,x\n", "inx\n", "txa\n", "cmp #$10\n", "jnz _1\n", "at $100\n", "range db $0\n", "\n", "\"\"\"" ] }, { "cell_type": "code", "execution_count": 3, "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "Compiled ROM: 01 00 38 0c 00 01 40 30 79 10 8b f8 00 " ] } ], "source": [ "# Assembler\n", "\n", "from pyparsing import *\n", "\n", "class Parser():\n", "\n", " pos = 0\n", " labels = {}\n", " binary = []\n", "\n", " def setOrig(self, tokens):\n", " self.pos = int(tokens.adr, 16)\n", "\n", " def setLabel(self, tokens):\n", " self.labels[tokens.lbl[0]] = self.pos-1\n", "\n", " def setRef(self, tokens):\n", " self.labels[tokens.lbl] = self.pos\n", " if tokens.size == 'db':\n", " self.binary.append(int(tokens.val, 16))\n", " self.pos += 1\n", " else:\n", " self.binary.append(int(tokens.val, 16) & 0xff)\n", " self.binary.append(int(tokens.val, 16) >> 8)\n", " self.pos += 2\n", "\n", " def setOp(self, tokens):\n", " c = getattr(opc, tokens.op) << 3\n", " if tokens.op == 'LDA':\n", " if tokens.am == '#$':\n", " c = c | adm.IMM\n", " self.pos += 2\n", " self.binary.append(c)\n", " self.binary.append(int(tokens.val, 16))\n", " elif tokens.am == '$':\n", " c |= adm.IDX if tokens.idx else adm.ABS\n", " self.pos += 3\n", " self.binary.append(c)\n", " l = int(tokens.val, 16) & 0xff\n", " h = int(tokens.val, 16) >> 8\n", " self.binary.append(h)\n", " self.binary.append(l)\n", " elif tokens.lbl:\n", " c |= adm.IDX if tokens.idx else adm.ABS\n", " self.pos += 3\n", " self.binary.append(c)\n", " self.binary.append(tokens.lbl)\n", " elif tokens.op == 'STA':\n", " c |= adm.IDX if tokens.idx else adm.ABS\n", " if tokens.am == '$':\n", " self.pos += 3\n", " self.binary.append(c)\n", " l = int(tokens.val, 16) & 0xff\n", " h = int(tokens.val, 16) >> 8\n", " self.binary.append(h)\n", " self.binary.append(l)\n", " elif tokens.lbl:\n", " self.pos += 3\n", " self.binary.append(c)\n", " self.binary.append(tokens.lbl[0])\n", " elif tokens.op in ['TAX', 'TXA', 'PHA', 'PLA', 'RTS', 'ASL', 'ASR', 'INX', 'DEX']:\n", " c = c | adm.IMP\n", " self.pos += 1\n", " self.binary.append(c)\n", " elif tokens.op in ['ADD', 'SUB', 'AND', 'OR', 'XOR', 'CMP']:\n", " c = c | adm.IMM\n", " self.pos += 2\n", " self.binary.append(c)\n", " self.binary.append(int(tokens.val, 16))\n", " elif tokens.op in ['JNZ', 'JZ']:\n", " c = c | adm.REL\n", " self.pos += 2\n", " self.binary.append(c)\n", " self.binary.append(tokens.lbl[0])\n", " elif tokens.op in ['JSR', 'JMP']:\n", " c = c | adm.ABS\n", " self.pos += 3\n", " self.binary.append(c)\n", " self.binary.append(tokens.lbl[0])\n", " \n", " def parse(self, src):\n", " \n", " op = oneOf(' '.join(opc._asdict()), caseless=True)\n", " org = (Word('atAT') + '$' + Word(hexnums)('adr')).setParseAction(self.setOrig)\n", " val = Word('#$')('am') + Word(hexnums)('val')\n", " lbl = (~op + Word(alphanums + '_'))('lbl')\n", " prm = (val|lbl) + ~Literal(':') + Optional(Word(', x'))('idx')\n", " label = (lbl + ':').setParseAction(self.setLabel)\n", " comment = ';' + restOfLine\n", " instruction = (op('op') + Optional(prm('prm'))).setParseAction(self.setOp)\n", " ref = (Word(alphanums + '_')('lbl') + oneOf('db dw')('size') + '$' + Word(hexnums)('val')).setParseAction(self.setRef)\n", " asm = OneOrMore(org | label | instruction | comment | ref)\n", "\n", " asm.parseString(src, parseAll=True)\n", "\n", " for i,b in enumerate(self.binary):\n", " if not isinstance(b, int):\n", " if b in self.labels.keys():\n", " if self.binary[i-1] in [0x8b, 0x93]: #todo extract addressing mode\n", " self.binary[i] = self.labels[b] - i + 1\n", " else:\n", " self.binary[i] = self.labels[b] & 0xff\n", " self.binary.insert(i+1, self.labels[b] >> 8)\n", " else:\n", " print('unresolved', b)\n", "\n", " return tuple(self.binary)\n", "\n", "rom = Parser().parse(src)\n", "\n", "print('Compiled ROM: ', end='')\n", "for b in rom:\n", " if b < 0: b = 0x100 + b\n", " print(f'{b:02x}', end=' ')\n" ] }, { "cell_type": "code", "execution_count": 4, "metadata": {}, "outputs": [], "source": [ "# RAM & CPU\n", "\n", "from myhdl import *\n", "\n", "\n", "# 2k RAM + ROM\n", "@block\n", "def mem(clk, adr, we, di, do):\n", " \n", " ram = [Signal(intbv(0)[8:]) for i in range(0x2000)] # 8k\n", "\n", " @always(clk.posedge)\n", " def logic():\n", " if we:\n", " ram[adr.val].next = di\n", " else:\n", " if adr < len(rom):\n", " do.next = rom[adr.val]\n", " else:\n", " do.next = ram[adr.val]\n", " \n", " return logic\n", "\n", "\n", "@block\n", "def processor(clk, rst, di, do, adr, we):\n", "\n", " \"\"\"\n", " IR = instruction register\n", " IM = immediate value\n", " RX = X register\n", " RW = W register used for status flags\n", " SR = status register\n", " AM = addressing mode\n", " SP = stack pointer\n", " \"\"\"\n", " \n", " (F1, F2, D, E, M1, M2) = range(0,6)\n", " #s = enum('F1', 'F2', 'D', 'E', 'M1', 'M2')\n", " pc = Signal(modbv(0)[11:])\n", " cyc = Signal(modbv(0)[3:])\n", " ir, im, ra, rx, rw, sr, am = (Signal(modbv(0)[8:]) for i in range(7))\n", " sp = Signal(modbv(0xff)[8:])\n", "\n", " @always(clk.posedge)\n", " def logic():\n", " \n", " if rst:\n", "# rst.next = 0\n", " pc.next = 0\n", " adr.next = 0\n", " \n", " elif cyc == F1:\n", " adr.next = pc + 1\n", " pc.next = pc + 1\n", " cyc.next = F2\n", " \n", " elif cyc == F2:\n", " adr.next = pc + 1\n", " ir.next = do\n", " cyc.next = D\n", " \n", " elif cyc == D:\n", " im.next = do\n", " am.next = ir & 7\n", " ir.next = (ir >> 3) & 0x1f\n", " if (ir >> 3) == opc.RTS: # rts\n", " adr.next = sp + 1\n", " sp.next = sp + 1 \n", " cyc.next = E\n", " \n", " elif cyc == E:\n", " if ir == opc.LDA: # lda\n", " if am == adm.IMM:\n", " ra.next = im\n", " pc.next = pc + 1\n", " elif am == adm.ABS:\n", " adr.next = (do << 8) | im\n", " pc.next = pc + 2\n", " elif am == adm.IDX:\n", " adr.next = (do << 8) | im + rx\n", " pc.next = pc + 2\n", " elif ir == opc.STA: # sta\n", " if am == adm.ABS:\n", " adr.next = (do << 8) | im\n", " we.next = 1\n", " di.next = ra\n", " pc.next = pc + 2\n", " elif am == adm.IDX:\n", " adr.next = (do << 8) | im + rx\n", " we.next = 1\n", " di.next = ra\n", " pc.next = pc + 2\n", " elif ir == opc.TAX: # tax\n", " rx.next = ra\n", " rw.next = 1\n", " elif ir == opc.TXA: # txa\n", " ra.next = rx\n", " elif ir == opc.ADD: # add im\n", " ra.next = ra + im\n", " pc.next = pc + 1\n", " elif ir == opc.SUB: # sub im\n", " ra.next = ra - im\n", " pc.next = pc + 1\n", " elif ir == opc.AND: # and im\n", " ra.next = ra & im\n", " pc.next = pc + 1\n", " elif ir == opc.OR: # or im\n", " ra.next = ra | im\n", " pc.next = pc + 1\n", " elif ir == opc.XOR: # xor im\n", " ra.next = ra ^ im\n", " pc.next = pc + 1\n", " elif ir == opc.ASL: # asl im\n", " ra.next = ra << im\n", " elif ir == opc.ASR: # asr im\n", " ra.next = ra >> im\n", " elif ir == opc.JNZ: # jnz rel\n", " if sr[6] == 0:\n", " pc.next = pc + im.signed()\n", " else:\n", " pc.next = pc + 1\n", " elif ir == opc.JZ: # jz rel\n", " if sr[6] != 0:\n", " pc.next = pc + im.signed()\n", " else:\n", " pc.next = pc + 1\n", " elif ir == opc.INX: # inx\n", " rx.next = rx + 1\n", " rw.next = 1\n", " elif ir == opc.DEX: # dex\n", " rx.next = rx - 1\n", " rw.next = 1\n", " elif ir == opc.PHA: # pha\n", " adr.next = sp\n", " sp.next = sp - 1\n", " di.next = ra\n", " we.next = 1\n", " elif ir == opc.PLA: # pla\n", " sp.next = sp + 1\n", " adr.next = sp + 1\n", " elif ir == opc.CMP: # cmp im\n", " rw.next = 2\n", " sr.next = concat((ra-im)>=0x80, (ra-im)==0, sr[6:0])\n", " pc.next = pc + 1\n", " elif ir == opc.JSR: # jsr abs\n", " adr.next = sp\n", " sp.next = sp - 1\n", " di.next = (pc + 2) >> 8\n", " we.next = 1\n", " elif ir == opc.RTS: # rts\n", " adr.next = sp + 1\n", " sp.next = sp + 1\n", " elif ir == opc.JMP: # jmp abs\n", " pc.next = (do << 8) | im\n", " cyc.next = M1\n", " \n", " elif cyc == M1:\n", " if (ir == opc.PLA) or (ir == opc.LDA and am == adm.ABS or am == adm.IDX):\n", " ra.next = do\n", " elif ir == opc.JSR:\n", " adr.next = sp\n", " sp.next = sp - 1\n", " di.next = (pc + 2) & 0xff\n", " we.next = 1\n", " pc.next = (do << 8) | im\n", " elif ir == opc.RTS:\n", " pc.next = do\n", " else:\n", " we.next = 0\n", " adr.next = pc\n", " cyc.next = M2\n", " \n", " elif cyc == M2:\n", " if ir == 0x11:\n", " ra.next = do\n", " sr.next = concat(do>=0x80, do==0, sr[6:0])\n", " elif rw == 0:\n", " sr.next = concat(ra>=0x80, ra==0, sr[6:0])\n", " elif rw == 1:\n", " sr.next = concat(rx>=0x80, rx==0, sr[6:0])\n", " if ir == 0x17:\n", " pc.next = (do << 8) | (pc & 0xff)\n", " adr.next = (do << 8) | (pc & 0xff)\n", " else:\n", " adr.next = pc\n", " we.next = 0\n", " rw.next = 0\n", " cyc.next = F1\n", " \n", " return logic" ] }, { "cell_type": "code", "execution_count": 5, "metadata": { "scrolled": false, "slideshow": { "slide_type": "-" } }, "outputs": [ { "name": "stderr", "output_type": "stream", "text": [ ": Simulated 1800 timesteps\n" ] } ], "source": [ "@block\n", "def sim():\n", " \n", " clk = Signal(bool(0))\n", " rst = Signal(bool(1))\n", " we = Signal(bool(0))\n", " adr = Signal(modbv(0)[16:])\n", " di = Signal(modbv(0)[8:])\n", " do = Signal(modbv(0)[8:])\n", " mi = mem(clk, adr, we, di, do)\n", " cpu = processor(clk, rst, di, do, adr, we)\n", " \n", " mi.convert(hdl='Verilog')\n", " cpu.convert(hdl='Verilog')\n", " \n", " @always(delay(2))\n", " def stimulus():\n", " clk.next = not clk\n", " if rst: rst.next = 0\n", "\n", " return stimulus, mi, cpu\n", "\n", "\n", "tb = sim()\n", "tb.config_sim(\n", " trace=True,\n", " tracebackup=False,\n", " filename='dump'\n", ")\n", "tb.run_sim(1800)\n" ] }, { "cell_type": "code", "execution_count": 6, "metadata": {}, "outputs": [], "source": [ "tb.quit_sim()" ] }, { "cell_type": "code", "execution_count": 7, "metadata": { "scrolled": true }, "outputs": [ { "data": { "text/html": [ "\n", "
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" ], "text/plain": [ "" ] }, "execution_count": 7, "metadata": {}, "output_type": "execute_result" } ], "source": [ "from IPython.display import HTML\n", "from Verilog_VCD import Verilog_VCD as vcd\n", "dump = vcd.parse_vcd('./dump.vcd')\n", "\n", "# make some signals more readable\n", "resolvers = {\n", " 'ir': lambda v: opc._fields[int(v,2)] if len(opc)>=int(v,2) else str(hex(int(v,2))),\n", " 'cyc': lambda v: (['F1','F2','D','E','M1','M2'][int(v,2)],['#faa','#faa','#aaf','#faf','#0f0','#0f0'][int(v,2)])\n", "}\n", "\n", "selection = ['ra', 'rx', 'pc', 'ir', 'di', 'adr', 'clk', 'cyc', 'rst']\n", "waves = ''\n", "names = ''\n", "ticks = ''\n", "start = min([d[1]['tv'][-1][0] for d in dump.items()])\n", "stop = max([d[1]['tv'][-1][0] for d in dump.items()])\n", "for i in range(start,stop): ticks += f'{i}'\n", "for n,d in dump.items():\n", " name = d['nets'][0]['name']\n", " size = d['nets'][0]['size']\n", " if name in selection:\n", " wave = ''\n", " pv = d['tv'][0][1]\n", " pc = 'white'\n", " for i in range(start, stop):\n", " if len(d['tv']):\n", " t,v = d['tv'][0]\n", " else: t = -1\n", " if int(size) == 1:\n", " cls = ''\n", " if i == t:\n", " del d['tv'][0]\n", " cls = 'bc' if pv != v else ''\n", " pv = v\n", " else:\n", " v = pv\n", " if int(v) == 1:\n", " wave += f''\n", " else:\n", " wave += f''\n", " else:\n", " c = pc\n", " if i == t:\n", " del d['tv'][0]\n", " if name in resolvers:\n", " v = resolvers[name](v)\n", " if isinstance(v, tuple): v,c = v\n", " pc = c\n", " else:\n", " v = str(hex(int(v, 2)))\n", " wave += f'{v}'\n", " else:\n", " wave += f''\n", "\n", " names += f'{name}'\n", " waves += wave + '
'\n", "\n", "css = \"\"\"\n", "\"\"\"\n", "HTML(\n", " css\n", " + '
' + ticks + '
'\n", " + '
' + names + '
'\n", " + '
' + waves + '
'\n", ")\n" ] }, { "cell_type": "code", "execution_count": null, "metadata": {}, "outputs": [], "source": [] } ], "metadata": { "celltoolbar": "Raw Cell Format", "kernelspec": { "display_name": "Python 3", "language": "python", "name": "python3" }, "language_info": { "codemirror_mode": { "name": "ipython", "version": 3 }, "file_extension": ".py", "mimetype": "text/x-python", "name": "python", "nbconvert_exporter": "python", "pygments_lexer": "ipython3", "version": "3.7.2" } }, "nbformat": 4, "nbformat_minor": 2 }