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	(generator_version "10.0")
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	)
	(paper "A4")
	(title_block
		(title "Plane Watcher (JLC04161H-7628 Stackup)")
		(date "2026-07-31")
		(rev "prototype 1.3")
		(company "plane.watch")
		(comment 1 "No warranty; see LICENSE.")
		(comment 2 "Source: https://github.com/plane-watch/hardware.")
		(comment 3 "Licensed under CERN-OHL-S-2.0.")
		(comment 4 "Copyright (C) 2026 plane.watch team and contributors.")
	)
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			(net "/FPGA_Y18")
			(pinfunction "Pin_17_17")
			(pintype "passive")
			(uuid "ed3aeae0-582e-4c42-bb63-753e2d8430fd")
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		(pad "18" thru_hole circle
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			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_AA18")
			(pinfunction "Pin_18_18")
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		(pad "19" thru_hole circle
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			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_AB14")
			(pinfunction "Pin_19_19")
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		(pad "20" thru_hole circle
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			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_AB15")
			(pinfunction "Pin_20_20")
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		(pad "21" thru_hole circle
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			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_Y13")
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			(drill 1)
			(layers "*.Cu" "*.Mask")
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			(net "/FPGA_AA13")
			(pinfunction "Pin_22_22")
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		(pad "23" thru_hole circle
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			(drill 1)
			(layers "*.Cu" "*.Mask")
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			(drill 1)
			(layers "*.Cu" "*.Mask")
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			(pinfunction "Pin_24_24")
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			(layers "*.Cu" "*.Mask")
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			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_E18")
			(pinfunction "Pin_9_9")
			(pintype "passive+no_connect")
			(uuid "e720b1ec-91b0-4b99-bc2d-75f31d52d406")
		)
		(pad "10" thru_hole circle
			(at 2.54 10.16 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_F18")
			(pinfunction "Pin_10_10")
			(pintype "passive+no_connect")
			(uuid "f2ab752a-81be-4427-ab56-c3710e085ac9")
		)
		(pad "11" thru_hole circle
			(at 0 12.7 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_F17")
			(pinfunction "Pin_11_11")
			(pintype "passive+no_connect")
			(uuid "ceff0c4a-7a32-4af7-be53-e1048a3c8ef9")
		)
		(pad "12" thru_hole circle
			(at 2.54 12.7 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_G17")
			(pinfunction "Pin_12_12")
			(pintype "passive+no_connect")
			(uuid "eeb583c4-e993-4cb1-a8de-ffbe0350fb52")
		)
		(pad "13" thru_hole circle
			(at 0 15.24 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_C17")
			(pinfunction "Pin_13_13")
			(pintype "passive+no_connect")
			(uuid "174a6e10-cf02-410e-b00c-d3429cac964f")
		)
		(pad "14" thru_hole circle
			(at 2.54 15.24 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_C18")
			(pinfunction "Pin_14_14")
			(pintype "passive+no_connect")
			(uuid "552c4604-7862-4006-b9ba-43e0e20e06f5")
		)
		(pad "15" thru_hole circle
			(at 0 17.78 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_G19")
			(pinfunction "Pin_15_15")
			(pintype "passive+no_connect")
			(uuid "f6538a10-fd81-444e-8a0f-625c799e13ee")
		)
		(pad "16" thru_hole circle
			(at 2.54 17.78 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_F19")
			(pinfunction "Pin_16_16")
			(pintype "passive+no_connect")
			(uuid "57b5b729-c757-41aa-9443-7a305c40518e")
		)
		(pad "17" thru_hole circle
			(at 0 20.32 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_E20")
			(pinfunction "Pin_17_17")
			(pintype "passive+no_connect")
			(uuid "1f75db91-dde0-4c0b-bbd2-976caadd61a0")
		)
		(pad "18" thru_hole circle
			(at 2.54 20.32 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_E19")
			(pinfunction "Pin_18_18")
			(pintype "passive+no_connect")
			(uuid "b404b546-2ece-4a08-908b-178a17955767")
		)
		(pad "19" thru_hole circle
			(at 0 22.86 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_D22")
			(pinfunction "Pin_19_19")
			(pintype "passive+no_connect")
			(uuid "42ee845c-c8de-4fc2-97ae-4a01e101f7c4")
		)
		(pad "20" thru_hole circle
			(at 2.54 22.86 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_C22")
			(pinfunction "Pin_20_20")
			(pintype "passive+no_connect")
			(uuid "0e7df474-3852-493b-bad2-376132eaefdc")
		)
		(pad "21" thru_hole circle
			(at 0 25.4 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_B22")
			(pinfunction "Pin_21_21")
			(pintype "passive+no_connect")
			(uuid "42ddeb0d-be64-4a02-a5b1-5384ea1060d9")
		)
		(pad "22" thru_hole circle
			(at 2.54 25.4 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_B21")
			(pinfunction "Pin_22_22")
			(pintype "passive+no_connect")
			(uuid "e136eb95-5363-4308-b04e-cbeafc53c116")
		)
		(pad "23" thru_hole circle
			(at 0 27.94 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_B17")
			(pinfunction "Pin_23_23")
			(pintype "passive+no_connect")
			(uuid "9b366f62-de1f-46f7-8b46-7a459804ba1b")
		)
		(pad "24" thru_hole circle
			(at 2.54 27.94 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_B16")
			(pinfunction "Pin_24_24")
			(pintype "passive+no_connect")
			(uuid "4ce0f75d-1150-4213-8192-be89727e787e")
		)
		(pad "25" thru_hole circle
			(at 0 30.48 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_A17")
			(pinfunction "Pin_25_25")
			(pintype "passive+no_connect")
			(uuid "fbc12d23-75f3-4939-b0e5-d8cec794f1e1")
		)
		(pad "26" thru_hole circle
			(at 2.54 30.48 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_A16")
			(pinfunction "Pin_26_26")
			(pintype "passive+no_connect")
			(uuid "3d6074cb-8f36-4adc-8bea-905782ace240")
		)
		(pad "27" thru_hole circle
			(at 0 33.02 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_D20")
			(pinfunction "Pin_27_27")
			(pintype "passive+no_connect")
			(uuid "1dfc228a-34ba-494b-9fc5-10a6bb3f23d5")
		)
		(pad "28" thru_hole circle
			(at 2.54 33.02 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_C20")
			(pinfunction "Pin_28_28")
			(pintype "passive+no_connect")
			(uuid "25516344-10a7-4379-9804-a14605a756f3")
		)
		(pad "29" thru_hole circle
			(at 0 35.56 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_B15")
			(pinfunction "Pin_29_29")
			(pintype "passive+no_connect")
			(uuid "c5d612ce-0651-4b2f-8af0-89fbc4d45de6")
		)
		(pad "30" thru_hole circle
			(at 2.54 35.56 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_C15")
			(pinfunction "Pin_30_30")
			(pintype "passive+no_connect")
			(uuid "a5650bac-426b-4158-9c94-a494b00968b2")
		)
		(pad "31" thru_hole circle
			(at 0 38.1 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_D17")
			(pinfunction "Pin_31_31")
			(pintype "passive+no_connect")
			(uuid "dd3fff7e-6b74-4794-98c1-0453fd0e636b")
		)
		(pad "32" thru_hole circle
			(at 2.54 38.1 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_D16")
			(pinfunction "Pin_32_32")
			(pintype "passive+no_connect")
			(uuid "966946c0-5c96-4e6a-94d7-b93f70f9bf79")
		)
		(pad "33" thru_hole circle
			(at 0 40.64 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_D15")
			(pinfunction "Pin_33_33")
			(pintype "passive")
			(uuid "70b5ba36-7226-44ac-bce0-bcd84610af3f")
		)
		(pad "34" thru_hole circle
			(at 2.54 40.64 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_E15")
			(pinfunction "Pin_34_34")
			(pintype "passive")
			(uuid "276f4386-4849-40ed-ac82-d2f36df893dd")
		)
		(pad "35" thru_hole circle
			(at 0 43.18 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_D18")
			(pinfunction "Pin_35_35")
			(pintype "passive")
			(uuid "9b860a07-c4b6-4e57-b125-c700cd6e7e0a")
		)
		(pad "36" thru_hole circle
			(at 2.54 43.18 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_C19")
			(pinfunction "Pin_36_36")
			(pintype "passive")
			(uuid "cc2c2b9f-d8b7-4e9c-88c4-32cff91ad606")
		)
		(pad "37" thru_hole circle
			(at 0 45.72 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_E16")
			(pinfunction "Pin_37_37")
			(pintype "passive")
			(uuid "ebf8b4c5-df1a-4c0c-8ede-ecff5139f7b7")
		)
		(pad "38" thru_hole circle
			(at 2.54 45.72 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_F16")
			(pinfunction "Pin_38_38")
			(pintype "passive")
			(uuid "459d9ee1-f78a-4a49-97ed-a3a4fc9b6cd4")
		)
		(pad "39" thru_hole circle
			(at 0 48.26 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA Headers Bank 35/FPGA_G15")
			(pinfunction "Pin_39_39")
			(pintype "passive+no_connect")
			(uuid "32b945db-8b90-4fb8-9fae-be81c0472372")
		)
		(pad "40" thru_hole circle
			(at 2.54 48.26 90)
			(size 1.7 1.7)
			(drill 1)
			(layers "*.Cu" "*.Mask")
			(remove_unused_layers no)
			(net "/FPGA_G16")
			(pinfunction "Pin_40_40")
			(pintype "passive")
			(uuid "10f6a5a2-a235-492d-9e8b-79e3bea795e8")
		)
		(embedded_fonts no)
		(model "${KICAD10_3DMODEL_DIR}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x20_P2.54mm_Vertical.step"
			(offset
				(xyz 0 0 0)
			)
			(scale
				(xyz 1 1 1)
			)
			(rotate
				(xyz 0 0 0)
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	)
	(footprint "Resistor_SMD:R_0402_1005Metric"
		(layer "F.Cu")
		(uuid "b3ff85cd-c0d5-4b8e-aea6-9d6adc61d78b")
		(at 168.4932 81.048841 -90)
		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)")
		(tags "resistor")
		(property "Reference" "R1"
			(at -1.42 0.015 0)
			(layer "F.SilkS")
			(hide yes)
			(uuid "7a6d44c8-0fb1-4a58-b5e0-6c2767ccefa6")
			(effects
				(font
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		)
		(property "Value" "10kΩ"
			(at 0 1.17 90)
			(layer "F.Fab")
			(uuid "8a844af7-6188-4826-9a30-bdb5f07104ff")
			(effects
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		(property "Datasheet" "https://www.yageogroup.com/component-documentation/download/specsheet/RC0402FR-0710KL"
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			(layer "F.Fab")
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			(uuid "9c20f7cd-fb54-45c6-a5c3-7184bb0b68e9")
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		(property "Description" "10 kOhms ±0.1% 0.063W, 1/16W Chip Resistor 0402 (1005 Metric) Automotive AEC-Q200 Thin Film"
			(at 0 0 90)
			(layer "F.Fab")
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			(uuid "ef044ab0-7758-4c6f-89e1-c92938ddc021")
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		(property "Purpose" "Pulls the LT3045 open-collector power-good output up to 3V3."
			(at 0 0 90)
			(unlocked yes)
			(layer "F.Fab")
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			(uuid "22221622-0c2c-4718-ba6b-47d7024a782d")
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		(property "Manufacturer" "Panasonic Industry"
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			(uuid "b9efaae6-fb4e-4caa-884e-8518e5f44a46")
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		(property ki_fp_filters "R_*")
		(path "/4120177b-abe4-4f17-a23f-98e54a21beab")
		(sheetname "/")
		(sheetfile "planewatcher.kicad_sch")
		(units
			(unit
				(name "A")
				(pins "1" "2")
			)
		)
		(attr smd)
		(duplicate_pad_numbers_are_jumpers no)
		(fp_line
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			(fill no)
			(layer "F.Fab")
			(uuid "6aba1554-c162-4008-ba44-bc7dc4fd040b")
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		(fp_text user "${REFERENCE}"
			(at 0 0 90)
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			(uuid "b4146274-fde9-4f72-98dc-186c44764e8c")
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		(pad "1" smd roundrect
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			(size 0.54 0.64)
			(layers "F.Cu" "F.Mask" "F.Paste")
			(roundrect_rratio 0.25)
			(net "/FPGA_3V3_BNK33")
			(pintype "passive")
			(uuid "c709b090-d8e4-48a4-b385-d0a9fdb93ec7")
		)
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			(size 0.54 0.64)
			(layers "F.Cu" "F.Mask" "F.Paste")
			(roundrect_rratio 0.25)
			(net "/PWR_GOOD")
			(pintype "passive")
			(uuid "fde23eb0-3551-4fef-902b-ec3a3f36d81f")
		)
		(embedded_fonts no)
		(model "${KICAD10_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.step"
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			)
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			)
			(rotate
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		)
	)
	(footprint "Resistor_SMD:R_0402_1005Metric"
		(layer "F.Cu")
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