RESET D3 D4 D0 D1 D2 GND VCC Dimitris Platis dimitris@platis.solutions VCC GND 1 Dimitris Platis dimitris@platis.solutions Website: platis.solutions Tel: 7777777785555 GitHub: platisd ATtiny85 VCC GND <h3>SparkFun Electronics' preferred foot prints</h3> In this library you'll find all manner of digital ICs- microcontrollers, memory chips, logic chips, FPGAs, etc. We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com. Licensing: Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/ You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage. Fits EIAJ packages (wide version of the SOIC-8). >VALUE >NAME Pin Header Connectors <author>Created by librarian@cadsoft.de</author> PIN HEADER >NAME >VALUE PIN HEADER >NAME >VALUE PIN HEADER >NAME >VALUE PIN HEADER >NAME >VALUE EAGLE Design Rules Die Standard-Design-Rules sind so gewählt, dass sie für die meisten Anwendungen passen. Sollte ihre Platine besondere Anforderungen haben, treffen Sie die erforderlichen Einstellungen hier und speichern die Design Rules unter einem neuen Namen ab. EAGLE Design Rules The default Design Rules have been set to cover a wide range of applications. Your particular design may have different requirements, so please make the necessary adjustments and save your customized design rules under a new name. Seeed Studio EAGLE Design Rules Since Version 6.2.2 text objects can contain more than one line, which will not be processed correctly with this version.