8 Raspberry Pi RP2040 Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n \n SPDX-License-Identifier: BSD-3-Clause 0.1 32 CM0PLUS r0p1 little true false 2 false 26 0 0x0020 registers 0x14000000 QSPI flash execute-in-place block XIP_IRQ 6 XIP_CTRL 0x0000 Cache control read-write [3:3] When 1, the cache memories are powered down. They retain state,\n but can not be accessed. This reduces static power dissipation.\n Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n be enabled when powered down.\n Cache-as-SRAM accesses will produce a bus error response when\n the cache is powered down. POWER_DOWN read-write [1:1] When 1, writes to any alias other than 0x0 (caching, allocating)\n will produce a bus fault. When 0, these writes are silently ignored.\n In either case, writes to the 0x0 alias will deallocate on tag match,\n as usual. ERR_BADWRITE read-write [0:0] When 1, enable the cache. When the cache is disabled, all XIP accesses\n will go straight to the flash, without querying the cache. When enabled,\n cacheable XIP accesses will query the cache, and the flash will\n not be accessed if the tag matches and the valid bit is set.\n\n If the cache is enabled, cache-as-SRAM accesses have no effect on the\n cache data RAM, and will produce a bus error response. EN CTRL 0x00000003 0x0004 Cache Flush control read-write [0:0] Write 1 to flush the cache. This clears the tag memory, but\n the data memory retains its contents. (This means cache-as-SRAM\n contents is not affected by flush or reset.)\n Reading will hold the bus (stall the processor) until the flush\n completes. Alternatively STAT can be polled until completion. clear FLUSH FLUSH 0x00000000 0x0008 Cache Status read-only [2:2] When 1, indicates the XIP streaming FIFO is completely full.\n The streaming FIFO is 2 entries deep, so the full and empty\n flag allow its level to be ascertained. FIFO_FULL read-only [1:1] When 1, indicates the XIP streaming FIFO is completely empty. FIFO_EMPTY read-only [0:0] Reads as 0 while a cache flush is in progress, and 1 otherwise.\n The cache is flushed whenever the XIP block is reset, and also\n when requested via the FLUSH register. FLUSH_READY STAT 0x00000002 read-write 0x000c Cache Hit counter\n A 32 bit saturating counter that increments upon each cache hit,\n i.e. when an XIP access is serviced directly from cached data.\n Write any value to clear. oneToClear CTR_HIT 0x00000000 read-write 0x0010 Cache Access counter\n A 32 bit saturating counter that increments upon each XIP access,\n whether the cache is hit or not. This includes noncacheable accesses.\n Write any value to clear. oneToClear CTR_ACC 0x00000000 0x0014 FIFO stream address read-write [31:2] The address of the next word to be streamed from flash to the streaming FIFO.\n Increments automatically after each flash access.\n Write the initial access address here before starting a streaming read. STREAM_ADDR STREAM_ADDR 0x00000000 0x0018 FIFO stream control read-write [21:0] Write a nonzero value to start a streaming read. This will then\n progress in the background, using flash idle cycles to transfer\n a linear data block from flash to the streaming FIFO.\n Decrements automatically (1 at a time) as the stream\n progresses, and halts on reaching 0.\n Write 0 to halt an in-progress stream, and discard any in-flight\n read, so that a new stream can immediately be started (after\n draining the FIFO and reinitialising STREAM_ADDR) STREAM_CTR STREAM_CTR 0x00000000 read-only 0x001c FIFO stream data\n Streamed data is buffered here, for retrieval by the system DMA.\n This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n the DMA to bus stalls caused by other XIP traffic. STREAM_FIFO 0x00000000 32 1 0 0x0100 registers 0x18000000 DW_apb_ssi has the following features:\n * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\n * APB3 and APB4 protocol support.\n * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\n * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\n * Programmable Dual/Quad/Octal SPI support in Master Mode.\n * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\n * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\n * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\n * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\n * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\n * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\n * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\n * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\n * Programmable features:\n - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\n - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\n - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\n * Configured features:\n - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n - 1 slave select output.\n - Hardware slave-select – Dedicated hardware slave-select line.\n - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\n - Interrupt polarity – active high interrupt lines.\n - Serial clock polarity – low serial-clock polarity directly after reset.\n - Serial clock phase – capture on first edge of serial-clock directly after reset. XIP_SSI 0x0000 Control register 0 read-write [24:24] Slave select toggle enable SSTE read-write [22:21] SPI frame format Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex STD 0 Dual-SPI frame format; two bits per SCK, half-duplex DUAL 1 Quad-SPI frame format; four bits per SCK, half-duplex QUAD 2 SPI_FRF read-write [20:16] Data frame size in 32b transfer mode\n Value of n -> n+1 clocks per frame. DFS_32 read-write [15:12] Control frame size\n Value of n -> n+1 clocks per frame. CFS read-write [11:11] Shift register loop (test mode) SRL read-write [10:10] Slave output enable SLV_OE read-write [9:8] Transfer mode Both transmit and receive TX_AND_RX 0 Transmit only (not for FRF == 0, standard SPI mode) TX_ONLY 1 Receive only (not for FRF == 0, standard SPI mode) RX_ONLY 2 EEPROM read mode (TX then RX; RX starts after control data TX'd) EEPROM_READ 3 TMOD read-write [7:7] Serial clock polarity SCPOL read-write [6:6] Serial clock phase SCPH read-write [5:4] Frame format FRF read-write [3:0] Data frame size DFS CTRLR0 0x00000000 0x0004 Master Control register 1 read-write [15:0] Number of data frames NDF CTRLR1 0x00000000 0x0008 SSI Enable read-write [0:0] SSI enable SSI_EN SSIENR 0x00000000 0x000c Microwire Control read-write [2:2] Microwire handshaking MHS read-write [1:1] Microwire control MDD read-write [0:0] Microwire transfer mode MWMOD MWCR 0x00000000 0x0010 Slave enable read-write [0:0] For each bit:\n 0 -> slave not selected\n 1 -> slave selected SER SER 0x00000000 0x0014 Baud rate read-write [15:0] SSI clock divider SCKDV BAUDR 0x00000000 0x0018 TX FIFO threshold level read-write [7:0] Transmit FIFO threshold TFT TXFTLR 0x00000000 0x001c RX FIFO threshold level read-write [7:0] Receive FIFO threshold RFT RXFTLR 0x00000000 0x0020 TX FIFO level read-only [7:0] Transmit FIFO level TFTFL TXFLR 0x00000000 0x0024 RX FIFO level read-only [7:0] Receive FIFO level RXTFL RXFLR 0x00000000 0x0028 Status register read-only [6:6] Data collision error DCOL read-only [5:5] Transmission error TXE read-only [4:4] Receive FIFO full RFF read-only [3:3] Receive FIFO not empty RFNE read-only [2:2] Transmit FIFO empty TFE read-only [1:1] Transmit FIFO not full TFNF read-only [0:0] SSI busy flag BUSY SR 0x00000000 0x002c Interrupt mask read-write [5:5] Multi-master contention interrupt mask MSTIM read-write [4:4] Receive FIFO full interrupt mask RXFIM read-write [3:3] Receive FIFO overflow interrupt mask RXOIM read-write [2:2] Receive FIFO underflow interrupt mask RXUIM read-write [1:1] Transmit FIFO overflow interrupt mask TXOIM read-write [0:0] Transmit FIFO empty interrupt mask TXEIM IMR 0x00000000 0x0030 Interrupt status read-only [5:5] Multi-master contention interrupt status MSTIS read-only [4:4] Receive FIFO full interrupt status RXFIS read-only [3:3] Receive FIFO overflow interrupt status RXOIS read-only [2:2] Receive FIFO underflow interrupt status RXUIS read-only [1:1] Transmit FIFO overflow interrupt status TXOIS read-only [0:0] Transmit FIFO empty interrupt status TXEIS ISR 0x00000000 0x0034 Raw interrupt status read-only [5:5] Multi-master contention raw interrupt status MSTIR read-only [4:4] Receive FIFO full raw interrupt status RXFIR read-only [3:3] Receive FIFO overflow raw interrupt status RXOIR read-only [2:2] Receive FIFO underflow raw interrupt status RXUIR read-only [1:1] Transmit FIFO overflow raw interrupt status TXOIR read-only [0:0] Transmit FIFO empty raw interrupt status TXEIR RISR 0x00000000 0x0038 TX FIFO overflow interrupt clear read-only [0:0] Clear-on-read transmit FIFO overflow interrupt TXOICR TXOICR 0x00000000 0x003c RX FIFO overflow interrupt clear read-only [0:0] Clear-on-read receive FIFO overflow interrupt RXOICR RXOICR 0x00000000 0x0040 RX FIFO underflow interrupt clear read-only [0:0] Clear-on-read receive FIFO underflow interrupt RXUICR RXUICR 0x00000000 0x0044 Multi-master interrupt clear read-only [0:0] Clear-on-read multi-master contention interrupt MSTICR MSTICR 0x00000000 0x0048 Interrupt clear read-only [0:0] Clear-on-read all active interrupts ICR ICR 0x00000000 0x004c DMA control read-write [1:1] Transmit DMA enable TDMAE read-write [0:0] Receive DMA enable RDMAE DMACR 0x00000000 0x0050 DMA TX data level read-write [7:0] Transmit data watermark level DMATDL DMATDLR 0x00000000 0x0054 DMA RX data level read-write [7:0] Receive data watermark level (DMARDLR+1) DMARDL DMARDLR 0x00000000 0x0058 Identification register read-only [31:0] Peripheral dentification code IDCODE IDR 0x51535049 0x005c Version ID read-only [31:0] SNPS component version (format X.YY) SSI_COMP_VERSION SSI_VERSION_ID 0x3430312a 0x0060 Data Register 0 (of 36) read-write [31:0] First data register of 36 DR DR0 0x00000000 0x00f0 RX sample delay read-write [7:0] RXD sample delay (in SCLK cycles) RSD RX_SAMPLE_DLY 0x00000000 0x00f4 SPI control read-write [31:24] SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) XIP_CMD read-write [18:18] Read data strobe enable SPI_RXDS_EN read-write [17:17] Instruction DDR transfer enable INST_DDR_EN read-write [16:16] SPI DDR transfer enable SPI_DDR_EN read-write [15:11] Wait cycles between control frame transmit and data reception (in SCLK cycles) WAIT_CYCLES read-write [9:8] Instruction length (0/4/8/16b) No instruction NONE 0 4-bit instruction 4B 1 8-bit instruction 8B 2 16-bit instruction 16B 3 INST_L read-write [5:2] Address length (0b-60b in 4b increments) ADDR_L read-write [1:0] Address and instruction transfer format Command and address both in standard SPI frame format 1C1A 0 Command in standard SPI format, address in format specified by FRF 1C2A 1 Command and address both in format specified by FRF (e.g. Dual-SPI) 2C2A 2 TRANS_TYPE SPI_CTRLR0 0x03000000 0x00f8 TX drive edge read-write [7:0] TXD drive edge TDE TXD_DRIVE_EDGE 0x00000000 32 1 0 0x1000 registers 0x40000000 SYSINFO 0x0000 JEDEC JEP-106 compliant chip identifier. read-only [31:28] REVISION read-only [27:12] PART read-only [11:0] MANUFACTURER CHIP_ID 0x00000000 0x0004 Platform register. Allows software to know what environment it is running in. read-only [1:1] ASIC read-only [0:0] FPGA PLATFORM 0x00000000 read-only 0x0040 Git hash of the chip source. Used to identify chip version. GITREF_RP2040 0x00000000 32 1 0 0x1000 registers 0x40004000 Register block for various chip control signals SYSCFG read-write 0x0000 Processor core 0 NMI source mask\n Set a bit high to enable NMI from that IRQ PROC0_NMI_MASK 0x00000000 read-write 0x0004 Processor core 1 NMI source mask\n Set a bit high to enable NMI from that IRQ PROC1_NMI_MASK 0x00000000 0x0008 Configuration for processors read-write [31:28] Configure proc1 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP PROC1_DAP_INSTID read-write [27:24] Configure proc0 DAP instance ID.\n Recommend that this is NOT changed until you require debug access in multi-chip environment\n WARNING: do not set to 15 as this is reserved for RescueDP PROC0_DAP_INSTID read-only [1:1] Indication that proc1 has halted PROC1_HALTED read-only [0:0] Indication that proc0 has halted PROC0_HALTED PROC_CONFIG 0x10000000 0x000c For each bit, if 1, bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO. The input synchronizers should\n generally be unbypassed, to avoid injecting metastabilities into processors.\n If you're feeling brave, you can bypass to save two cycles of input\n latency. This register applies to GPIO 0...29. read-write [29:0] PROC_IN_SYNC_BYPASS PROC_IN_SYNC_BYPASS 0x00000000 0x0010 For each bit, if 1, bypass the input synchronizer between that GPIO\n and the GPIO input register in the SIO. The input synchronizers should\n generally be unbypassed, to avoid injecting metastabilities into processors.\n If you're feeling brave, you can bypass to save two cycles of input\n latency. This register applies to GPIO 30...35 (the QSPI IOs). read-write [5:0] PROC_IN_SYNC_BYPASS_HI PROC_IN_SYNC_BYPASS_HI 0x00000000 0x0014 Directly control the SWD debug port of either processor read-write [7:7] Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. PROC1_ATTACH read-write [6:6] Directly drive processor 1 SWCLK, if PROC1_ATTACH is set PROC1_SWCLK read-write [5:5] Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set PROC1_SWDI read-only [4:4] Observe the value of processor 1 SWDIO output. PROC1_SWDO read-write [3:3] Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. PROC0_ATTACH read-write [2:2] Directly drive processor 0 SWCLK, if PROC0_ATTACH is set PROC0_SWCLK read-write [1:1] Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set PROC0_SWDI read-only [0:0] Observe the value of processor 0 SWDIO output. PROC0_SWDO DBGFORCE 0x00000066 0x0018 Control power downs to memories. Set high to power down memories.\n Use with extreme caution read-write [7:7] ROM read-write [6:6] USB read-write [5:5] SRAM5 read-write [4:4] SRAM4 read-write [3:3] SRAM3 read-write [2:2] SRAM2 read-write [1:1] SRAM1 read-write [0:0] SRAM0 MEMPOWERDOWN 0x00000000 32 1 0 0x1000 registers 0x40008000 CLOCKS_IRQ 17 CLOCKS 0x0000 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [12:12] Enables duty cycle correction for odd divisors DC50 read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [8:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 AUXSRC CLK_GPOUT0_CTRL 0x00000000 0x0004 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_GPOUT0_DIV 0x00000100 read-only 0x0008 Indicates which src is currently selected (one-hot) CLK_GPOUT0_SELECTED 0x00000001 0x000c Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [12:12] Enables duty cycle correction for odd divisors DC50 read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [8:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 AUXSRC CLK_GPOUT1_CTRL 0x00000000 0x0010 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_GPOUT1_DIV 0x00000100 read-only 0x0014 Indicates which src is currently selected (one-hot) CLK_GPOUT1_SELECTED 0x00000001 0x0018 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [12:12] Enables duty cycle correction for odd divisors DC50 read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [8:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc_ph 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 AUXSRC CLK_GPOUT2_CTRL 0x00000000 0x001c Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_GPOUT2_DIV 0x00000100 read-only 0x0020 Indicates which src is currently selected (one-hot) CLK_GPOUT2_SELECTED 0x00000001 0x0024 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [12:12] Enables duty cycle correction for odd divisors DC50 read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [8:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc_ph 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 AUXSRC CLK_GPOUT3_CTRL 0x00000000 0x0028 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_GPOUT3_DIV 0x00000100 read-only 0x002c Indicates which src is currently selected (one-hot) CLK_GPOUT3_SELECTED 0x00000001 0x0030 Clock control, can be changed on-the-fly (except for auxsrc) read-write [6:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_usb 0 clksrc_gpin0 1 clksrc_gpin1 2 AUXSRC read-write [1:0] Selects the clock source glitchlessly, can be changed on-the-fly rosc_clksrc_ph 0 clksrc_clk_ref_aux 1 xosc_clksrc 2 SRC CLK_REF_CTRL 0x00000000 0x0034 Clock divisor, can be changed on-the-fly read-write [9:8] Integer component of the divisor, 0 -> divide by 2^16 INT CLK_REF_DIV 0x00000100 read-only 0x0038 Indicates which src is currently selected (one-hot) CLK_REF_SELECTED 0x00000001 0x003c Clock control, can be changed on-the-fly (except for auxsrc) read-write [7:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_sys 0 clksrc_pll_usb 1 rosc_clksrc 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 AUXSRC read-write [0:0] Selects the clock source glitchlessly, can be changed on-the-fly clk_ref 0 clksrc_clk_sys_aux 1 SRC CLK_SYS_CTRL 0x00000000 0x0040 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_SYS_DIV 0x00000100 read-only 0x0044 Indicates which src is currently selected (one-hot) CLK_SYS_SELECTED 0x00000001 0x0048 Clock control, can be changed on-the-fly (except for auxsrc) read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [7:5] Selects the auxiliary clock source, will glitch when switching clk_sys 0 clksrc_pll_sys 1 clksrc_pll_usb 2 rosc_clksrc_ph 3 xosc_clksrc 4 clksrc_gpin0 5 clksrc_gpin1 6 AUXSRC CLK_PERI_CTRL 0x00000000 read-only 0x0050 Indicates which src is currently selected (one-hot) CLK_PERI_SELECTED 0x00000001 0x0054 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [7:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 AUXSRC CLK_USB_CTRL 0x00000000 0x0058 Clock divisor, can be changed on-the-fly read-write [9:8] Integer component of the divisor, 0 -> divide by 2^16 INT CLK_USB_DIV 0x00000100 read-only 0x005c Indicates which src is currently selected (one-hot) CLK_USB_SELECTED 0x00000001 0x0060 Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [7:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 AUXSRC CLK_ADC_CTRL 0x00000000 0x0064 Clock divisor, can be changed on-the-fly read-write [9:8] Integer component of the divisor, 0 -> divide by 2^16 INT CLK_ADC_DIV 0x00000100 read-only 0x0068 Indicates which src is currently selected (one-hot) CLK_ADC_SELECTED 0x00000001 0x006c Clock control, can be changed on-the-fly (except for auxsrc) read-write [20:20] An edge on this signal shifts the phase of the output by 1 cycle of the input clock\n This can be done at any time NUDGE read-write [17:16] This delays the enable signal by up to 3 cycles of the input clock\n This must be set before the clock is enabled to have any effect PHASE read-write [11:11] Starts and stops the clock generator cleanly ENABLE read-write [10:10] Asynchronously kills the clock generator KILL read-write [7:5] Selects the auxiliary clock source, will glitch when switching clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 AUXSRC CLK_RTC_CTRL 0x00000000 0x0070 Clock divisor, can be changed on-the-fly read-write [31:8] Integer component of the divisor, 0 -> divide by 2^16 INT read-write [7:0] Fractional component of the divisor FRAC CLK_RTC_DIV 0x00000100 read-only 0x0074 Indicates which src is currently selected (one-hot) CLK_RTC_SELECTED 0x00000001 0x0078 read-write [16:16] For clearing the resus after the fault that triggered it has been corrected CLEAR read-write [12:12] Force a resus, for test purposes only FRCE read-write [8:8] Enable resus ENABLE read-write [7:0] This is expressed as a number of clk_ref cycles\n and must be >= 2x clk_ref_freq/min_clk_tst_freq TIMEOUT CLK_SYS_RESUS_CTRL 0x000000ff 0x007c read-only [0:0] Clock has been resuscitated, correct the error then send ctrl_clear=1 RESUSSED CLK_SYS_RESUS_STATUS 0x00000000 0x0080 Reference clock frequency in kHz read-write [19:0] FC0_REF_KHZ FC0_REF_KHZ 0x00000000 0x0084 Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags read-write [24:0] FC0_MIN_KHZ FC0_MIN_KHZ 0x00000000 0x0088 Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags read-write [24:0] FC0_MAX_KHZ FC0_MAX_KHZ 0x01ffffff 0x008c Delays the start of frequency counting to allow the mux to settle\n Delay is measured in multiples of the reference clock period read-write [2:0] FC0_DELAY FC0_DELAY 0x00000001 0x0090 The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n The default gives a test interval of 250us read-write [3:0] FC0_INTERVAL FC0_INTERVAL 0x00000008 0x0094 Clock sent to frequency counter, set to 0 when not required\n Writing to this register initiates the frequency count read-write [7:0] NULL 0 pll_sys_clksrc_primary 1 pll_usb_clksrc_primary 2 rosc_clksrc 3 rosc_clksrc_ph 4 xosc_clksrc 5 clksrc_gpin0 6 clksrc_gpin1 7 clk_ref 8 clk_sys 9 clk_peri 10 clk_usb 11 clk_adc 12 clk_rtc 13 FC0_SRC FC0_SRC 0x00000000 0x0098 Frequency counter status read-only [28:28] Test clock stopped during test DIED read-only [24:24] Test clock faster than expected, only valid when status_done=1 FAST read-only [20:20] Test clock slower than expected, only valid when status_done=1 SLOW read-only [16:16] Test failed FAIL read-only [12:12] Waiting for test clock to start WAITING read-only [8:8] Test running RUNNING read-only [4:4] Test complete DONE read-only [0:0] Test passed PASS FC0_STATUS 0x00000000 0x009c Result of frequency measurement, only valid when status_done=1 read-only [29:5] KHZ read-only [4:0] FRAC FC0_RESULT 0x00000000 0x00a0 enable clock in wake mode read-write [31:31] clk_sys_sram3 read-write [30:30] clk_sys_sram2 read-write [29:29] clk_sys_sram1 read-write [28:28] clk_sys_sram0 read-write [27:27] clk_sys_spi1 read-write [26:26] clk_peri_spi1 read-write [25:25] clk_sys_spi0 read-write [24:24] clk_peri_spi0 read-write [23:23] clk_sys_sio read-write [22:22] clk_sys_rtc read-write [21:21] clk_rtc_rtc read-write [20:20] clk_sys_rosc read-write [19:19] clk_sys_rom read-write [18:18] clk_sys_resets read-write [17:17] clk_sys_pwm read-write [16:16] clk_sys_psm read-write [15:15] clk_sys_pll_usb read-write [14:14] clk_sys_pll_sys read-write [13:13] clk_sys_pio1 read-write [12:12] clk_sys_pio0 read-write [11:11] clk_sys_pads read-write [10:10] clk_sys_vreg_and_chip_reset read-write [9:9] clk_sys_jtag read-write [8:8] clk_sys_io read-write [7:7] clk_sys_i2c1 read-write [6:6] clk_sys_i2c0 read-write [5:5] clk_sys_dma read-write [4:4] clk_sys_busfabric read-write [3:3] clk_sys_busctrl read-write [2:2] clk_sys_adc read-write [1:1] clk_adc_adc read-write [0:0] clk_sys_clocks WAKE_EN0 0xffffffff 0x00a4 enable clock in wake mode read-write [14:14] clk_sys_xosc read-write [13:13] clk_sys_xip read-write [12:12] clk_sys_watchdog read-write [11:11] clk_usb_usbctrl read-write [10:10] clk_sys_usbctrl read-write [9:9] clk_sys_uart1 read-write [8:8] clk_peri_uart1 read-write [7:7] clk_sys_uart0 read-write [6:6] clk_peri_uart0 read-write [5:5] clk_sys_timer read-write [4:4] clk_sys_tbman read-write [3:3] clk_sys_sysinfo read-write [2:2] clk_sys_syscfg read-write [1:1] clk_sys_sram5 read-write [0:0] clk_sys_sram4 WAKE_EN1 0x00007fff 0x00a8 enable clock in sleep mode read-write [31:31] clk_sys_sram3 read-write [30:30] clk_sys_sram2 read-write [29:29] clk_sys_sram1 read-write [28:28] clk_sys_sram0 read-write [27:27] clk_sys_spi1 read-write [26:26] clk_peri_spi1 read-write [25:25] clk_sys_spi0 read-write [24:24] clk_peri_spi0 read-write [23:23] clk_sys_sio read-write [22:22] clk_sys_rtc read-write [21:21] clk_rtc_rtc read-write [20:20] clk_sys_rosc read-write [19:19] clk_sys_rom read-write [18:18] clk_sys_resets read-write [17:17] clk_sys_pwm read-write [16:16] clk_sys_psm read-write [15:15] clk_sys_pll_usb read-write [14:14] clk_sys_pll_sys read-write [13:13] clk_sys_pio1 read-write [12:12] clk_sys_pio0 read-write [11:11] clk_sys_pads read-write [10:10] clk_sys_vreg_and_chip_reset read-write [9:9] clk_sys_jtag read-write [8:8] clk_sys_io read-write [7:7] clk_sys_i2c1 read-write [6:6] clk_sys_i2c0 read-write [5:5] clk_sys_dma read-write [4:4] clk_sys_busfabric read-write [3:3] clk_sys_busctrl read-write [2:2] clk_sys_adc read-write [1:1] clk_adc_adc read-write [0:0] clk_sys_clocks SLEEP_EN0 0xffffffff 0x00ac enable clock in sleep mode read-write [14:14] clk_sys_xosc read-write [13:13] clk_sys_xip read-write [12:12] clk_sys_watchdog read-write [11:11] clk_usb_usbctrl read-write [10:10] clk_sys_usbctrl read-write [9:9] clk_sys_uart1 read-write [8:8] clk_peri_uart1 read-write [7:7] clk_sys_uart0 read-write [6:6] clk_peri_uart0 read-write [5:5] clk_sys_timer read-write [4:4] clk_sys_tbman read-write [3:3] clk_sys_sysinfo read-write [2:2] clk_sys_syscfg read-write [1:1] clk_sys_sram5 read-write [0:0] clk_sys_sram4 SLEEP_EN1 0x00007fff 0x00b0 indicates the state of the clock enable read-only [31:31] clk_sys_sram3 read-only [30:30] clk_sys_sram2 read-only [29:29] clk_sys_sram1 read-only [28:28] clk_sys_sram0 read-only [27:27] clk_sys_spi1 read-only [26:26] clk_peri_spi1 read-only [25:25] clk_sys_spi0 read-only [24:24] clk_peri_spi0 read-only [23:23] clk_sys_sio read-only [22:22] clk_sys_rtc read-only [21:21] clk_rtc_rtc read-only [20:20] clk_sys_rosc read-only [19:19] clk_sys_rom read-only [18:18] clk_sys_resets read-only [17:17] clk_sys_pwm read-only [16:16] clk_sys_psm read-only [15:15] clk_sys_pll_usb read-only [14:14] clk_sys_pll_sys read-only [13:13] clk_sys_pio1 read-only [12:12] clk_sys_pio0 read-only [11:11] clk_sys_pads read-only [10:10] clk_sys_vreg_and_chip_reset read-only [9:9] clk_sys_jtag read-only [8:8] clk_sys_io read-only [7:7] clk_sys_i2c1 read-only [6:6] clk_sys_i2c0 read-only [5:5] clk_sys_dma read-only [4:4] clk_sys_busfabric read-only [3:3] clk_sys_busctrl read-only [2:2] clk_sys_adc read-only [1:1] clk_adc_adc read-only [0:0] clk_sys_clocks ENABLED0 0x00000000 0x00b4 indicates the state of the clock enable read-only [14:14] clk_sys_xosc read-only [13:13] clk_sys_xip read-only [12:12] clk_sys_watchdog read-only [11:11] clk_usb_usbctrl read-only [10:10] clk_sys_usbctrl read-only [9:9] clk_sys_uart1 read-only [8:8] clk_peri_uart1 read-only [7:7] clk_sys_uart0 read-only [6:6] clk_peri_uart0 read-only [5:5] clk_sys_timer read-only [4:4] clk_sys_tbman read-only [3:3] clk_sys_sysinfo read-only [2:2] clk_sys_syscfg read-only [1:1] clk_sys_sram5 read-only [0:0] clk_sys_sram4 ENABLED1 0x00000000 0x00b8 Raw Interrupts read-only [0:0] CLK_SYS_RESUS INTR 0x00000000 0x00bc Interrupt Enable read-write [0:0] CLK_SYS_RESUS INTE 0x00000000 0x00c0 Interrupt Force read-write [0:0] CLK_SYS_RESUS INTF 0x00000000 0x00c4 Interrupt status after masking & forcing read-only [0:0] CLK_SYS_RESUS INTS 0x00000000 32 1 0 0x1000 registers 0x4000c000 RESETS 0x0000 Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. read-write [24:24] usbctrl read-write [23:23] uart1 read-write [22:22] uart0 read-write [21:21] timer read-write [20:20] tbman read-write [19:19] sysinfo read-write [18:18] syscfg read-write [17:17] spi1 read-write [16:16] spi0 read-write [15:15] rtc read-write [14:14] pwm read-write [13:13] pll_usb read-write [12:12] pll_sys read-write [11:11] pio1 read-write [10:10] pio0 read-write [9:9] pads_qspi read-write [8:8] pads_bank0 read-write [7:7] jtag read-write [6:6] io_qspi read-write [5:5] io_bank0 read-write [4:4] i2c1 read-write [3:3] i2c0 read-write [2:2] dma read-write [1:1] busctrl read-write [0:0] adc RESET 0x01ffffff 0x0004 Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. read-write [24:24] usbctrl read-write [23:23] uart1 read-write [22:22] uart0 read-write [21:21] timer read-write [20:20] tbman read-write [19:19] sysinfo read-write [18:18] syscfg read-write [17:17] spi1 read-write [16:16] spi0 read-write [15:15] rtc read-write [14:14] pwm read-write [13:13] pll_usb read-write [12:12] pll_sys read-write [11:11] pio1 read-write [10:10] pio0 read-write [9:9] pads_qspi read-write [8:8] pads_bank0 read-write [7:7] jtag read-write [6:6] io_qspi read-write [5:5] io_bank0 read-write [4:4] i2c1 read-write [3:3] i2c0 read-write [2:2] dma read-write [1:1] busctrl read-write [0:0] adc WDSEL 0x00000000 0x0008 Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. read-only [24:24] usbctrl read-only [23:23] uart1 read-only [22:22] uart0 read-only [21:21] timer read-only [20:20] tbman read-only [19:19] sysinfo read-only [18:18] syscfg read-only [17:17] spi1 read-only [16:16] spi0 read-only [15:15] rtc read-only [14:14] pwm read-only [13:13] pll_usb read-only [12:12] pll_sys read-only [11:11] pio1 read-only [10:10] pio0 read-only [9:9] pads_qspi read-only [8:8] pads_bank0 read-only [7:7] jtag read-only [6:6] io_qspi read-only [5:5] io_bank0 read-only [4:4] i2c1 read-only [3:3] i2c0 read-only [2:2] dma read-only [1:1] busctrl read-only [0:0] adc RESET_DONE 0x00000000 32 1 0 0x1000 registers 0x40010000 PSM 0x0000 Force block out of reset (i.e. power it on) read-write [16:16] proc1 read-write [15:15] proc0 read-write [14:14] sio read-write [13:13] vreg_and_chip_reset read-write [12:12] xip read-write [11:11] sram5 read-write [10:10] sram4 read-write [9:9] sram3 read-write [8:8] sram2 read-write [7:7] sram1 read-write [6:6] sram0 read-write [5:5] rom read-write [4:4] busfabric read-write [3:3] resets read-write [2:2] clocks read-write [1:1] xosc read-write [0:0] rosc FRCE_ON 0x00000000 0x0004 Force into reset (i.e. power it off) read-write [16:16] proc1 read-write [15:15] proc0 read-write [14:14] sio read-write [13:13] vreg_and_chip_reset read-write [12:12] xip read-write [11:11] sram5 read-write [10:10] sram4 read-write [9:9] sram3 read-write [8:8] sram2 read-write [7:7] sram1 read-write [6:6] sram0 read-write [5:5] rom read-write [4:4] busfabric read-write [3:3] resets read-write [2:2] clocks read-write [1:1] xosc read-write [0:0] rosc FRCE_OFF 0x00000000 0x0008 Set to 1 if this peripheral should be reset when the watchdog fires. read-write [16:16] proc1 read-write [15:15] proc0 read-write [14:14] sio read-write [13:13] vreg_and_chip_reset read-write [12:12] xip read-write [11:11] sram5 read-write [10:10] sram4 read-write [9:9] sram3 read-write [8:8] sram2 read-write [7:7] sram1 read-write [6:6] sram0 read-write [5:5] rom read-write [4:4] busfabric read-write [3:3] resets read-write [2:2] clocks read-write [1:1] xosc read-write [0:0] rosc WDSEL 0x00000000 0x000c Indicates the peripheral's registers are ready to access. read-only [16:16] proc1 read-only [15:15] proc0 read-only [14:14] sio read-only [13:13] vreg_and_chip_reset read-only [12:12] xip read-only [11:11] sram5 read-only [10:10] sram4 read-only [9:9] sram3 read-only [8:8] sram2 read-only [7:7] sram1 read-only [6:6] sram0 read-only [5:5] rom read-only [4:4] busfabric read-only [3:3] resets read-only [2:2] clocks read-only [1:1] xosc read-only [0:0] rosc DONE 0x00000000 32 1 0 0x1000 registers 0x40014000 IO_IRQ_BANK0 13 IO_BANK0 0x0000 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO0_STATUS 0x00000000 0x0004 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL jtag_tck 0 spi0_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_0 4 sio_0 5 pio0_0 6 pio1_0 7 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO0_CTRL 0x0000001f 0x0008 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO1_STATUS 0x00000000 0x000c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL jtag_tms 0 spi0_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_0 4 sio_1 5 pio0_1 6 pio1_1 7 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO1_CTRL 0x0000001f 0x0010 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO2_STATUS 0x00000000 0x0014 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL jtag_tdi 0 spi0_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_1 4 sio_2 5 pio0_2 6 pio1_2 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO2_CTRL 0x0000001f 0x0018 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO3_STATUS 0x00000000 0x001c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL jtag_tdo 0 spi0_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_1 4 sio_3 5 pio0_3 6 pio1_3 7 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO3_CTRL 0x0000001f 0x0020 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO4_STATUS 0x00000000 0x0024 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_2 4 sio_4 5 pio0_4 6 pio1_4 7 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO4_CTRL 0x0000001f 0x0028 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO5_STATUS 0x00000000 0x002c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_2 4 sio_5 5 pio0_5 6 pio1_5 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO5_CTRL 0x0000001f 0x0030 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO6_STATUS 0x00000000 0x0034 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_3 4 sio_6 5 pio0_6 6 pio1_6 7 usb_muxing_extphy_softcon 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO6_CTRL 0x0000001f 0x0038 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO7_STATUS 0x00000000 0x003c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_3 4 sio_7 5 pio0_7 6 pio1_7 7 usb_muxing_extphy_oe_n 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO7_CTRL 0x0000001f 0x0040 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO8_STATUS 0x00000000 0x0044 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_4 4 sio_8 5 pio0_8 6 pio1_8 7 usb_muxing_extphy_rcv 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO8_CTRL 0x0000001f 0x0048 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO9_STATUS 0x00000000 0x004c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_4 4 sio_9 5 pio0_9 6 pio1_9 7 usb_muxing_extphy_vp 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO9_CTRL 0x0000001f 0x0050 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO10_STATUS 0x00000000 0x0054 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_5 4 sio_10 5 pio0_10 6 pio1_10 7 usb_muxing_extphy_vm 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO10_CTRL 0x0000001f 0x0058 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO11_STATUS 0x00000000 0x005c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_5 4 sio_11 5 pio0_11 6 pio1_11 7 usb_muxing_extphy_suspnd 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO11_CTRL 0x0000001f 0x0060 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO12_STATUS 0x00000000 0x0064 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_6 4 sio_12 5 pio0_12 6 pio1_12 7 usb_muxing_extphy_speed 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO12_CTRL 0x0000001f 0x0068 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO13_STATUS 0x00000000 0x006c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_6 4 sio_13 5 pio0_13 6 pio1_13 7 usb_muxing_extphy_vpo 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO13_CTRL 0x0000001f 0x0070 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO14_STATUS 0x00000000 0x0074 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_7 4 sio_14 5 pio0_14 6 pio1_14 7 usb_muxing_extphy_vmo 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO14_CTRL 0x0000001f 0x0078 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO15_STATUS 0x00000000 0x007c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_7 4 sio_15 5 pio0_15 6 pio1_15 7 usb_muxing_digital_dp 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO15_CTRL 0x0000001f 0x0080 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO16_STATUS 0x00000000 0x0084 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_0 4 sio_16 5 pio0_16 6 pio1_16 7 usb_muxing_digital_dm 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO16_CTRL 0x0000001f 0x0088 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO17_STATUS 0x00000000 0x008c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_0 4 sio_17 5 pio0_17 6 pio1_17 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO17_CTRL 0x0000001f 0x0090 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO18_STATUS 0x00000000 0x0094 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_1 4 sio_18 5 pio0_18 6 pio1_18 7 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO18_CTRL 0x0000001f 0x0098 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO19_STATUS 0x00000000 0x009c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_1 4 sio_19 5 pio0_19 6 pio1_19 7 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO19_CTRL 0x0000001f 0x00a0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO20_STATUS 0x00000000 0x00a4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_2 4 sio_20 5 pio0_20 6 pio1_20 7 clocks_gpin_0 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO20_CTRL 0x0000001f 0x00a8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO21_STATUS 0x00000000 0x00ac GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_2 4 sio_21 5 pio0_21 6 pio1_21 7 clocks_gpout_0 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO21_CTRL 0x0000001f 0x00b0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO22_STATUS 0x00000000 0x00b4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_3 4 sio_22 5 pio0_22 6 pio1_22 7 clocks_gpin_1 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO22_CTRL 0x0000001f 0x00b8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO23_STATUS 0x00000000 0x00bc GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi0_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_3 4 sio_23 5 pio0_23 6 pio1_23 7 clocks_gpout_1 8 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO23_CTRL 0x0000001f 0x00c0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO24_STATUS 0x00000000 0x00c4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_4 4 sio_24 5 pio0_24 6 pio1_24 7 clocks_gpout_2 8 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO24_CTRL 0x0000001f 0x00c8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO25_STATUS 0x00000000 0x00cc GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_4 4 sio_25 5 pio0_25 6 pio1_25 7 clocks_gpout_3 8 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO25_CTRL 0x0000001f 0x00d0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO26_STATUS 0x00000000 0x00d4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_5 4 sio_26 5 pio0_26 6 pio1_26 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO26_CTRL 0x0000001f 0x00d8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO27_STATUS 0x00000000 0x00dc GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_5 4 sio_27 5 pio0_27 6 pio1_27 7 usb_muxing_overcurr_detect 9 null 31 FUNCSEL GPIO27_CTRL 0x0000001f 0x00e0 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO28_STATUS 0x00000000 0x00e4 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_6 4 sio_28 5 pio0_28 6 pio1_28 7 usb_muxing_vbus_detect 9 null 31 FUNCSEL GPIO28_CTRL 0x0000001f 0x00e8 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO29_STATUS 0x00000000 0x00ec GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL spi1_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_6 4 sio_29 5 pio0_29 6 pio1_29 7 usb_muxing_vbus_en 9 null 31 FUNCSEL GPIO29_CTRL 0x0000001f 0x00f0 Raw Interrupts read-write [31:31] oneToClear GPIO7_EDGE_HIGH read-write [30:30] oneToClear GPIO7_EDGE_LOW read-only [29:29] GPIO7_LEVEL_HIGH read-only [28:28] GPIO7_LEVEL_LOW read-write [27:27] oneToClear GPIO6_EDGE_HIGH read-write [26:26] oneToClear GPIO6_EDGE_LOW read-only [25:25] GPIO6_LEVEL_HIGH read-only [24:24] GPIO6_LEVEL_LOW read-write [23:23] oneToClear GPIO5_EDGE_HIGH read-write [22:22] oneToClear GPIO5_EDGE_LOW read-only [21:21] GPIO5_LEVEL_HIGH read-only [20:20] GPIO5_LEVEL_LOW read-write [19:19] oneToClear GPIO4_EDGE_HIGH read-write [18:18] oneToClear GPIO4_EDGE_LOW read-only [17:17] GPIO4_LEVEL_HIGH read-only [16:16] GPIO4_LEVEL_LOW read-write [15:15] oneToClear GPIO3_EDGE_HIGH read-write [14:14] oneToClear GPIO3_EDGE_LOW read-only [13:13] GPIO3_LEVEL_HIGH read-only [12:12] GPIO3_LEVEL_LOW read-write [11:11] oneToClear GPIO2_EDGE_HIGH read-write [10:10] oneToClear GPIO2_EDGE_LOW read-only [9:9] GPIO2_LEVEL_HIGH read-only [8:8] GPIO2_LEVEL_LOW read-write [7:7] oneToClear GPIO1_EDGE_HIGH read-write [6:6] oneToClear GPIO1_EDGE_LOW read-only [5:5] GPIO1_LEVEL_HIGH read-only [4:4] GPIO1_LEVEL_LOW read-write [3:3] oneToClear GPIO0_EDGE_HIGH read-write [2:2] oneToClear GPIO0_EDGE_LOW read-only [1:1] GPIO0_LEVEL_HIGH read-only [0:0] GPIO0_LEVEL_LOW INTR0 0x00000000 0x00f4 Raw Interrupts read-write [31:31] oneToClear GPIO15_EDGE_HIGH read-write [30:30] oneToClear GPIO15_EDGE_LOW read-only [29:29] GPIO15_LEVEL_HIGH read-only [28:28] GPIO15_LEVEL_LOW read-write [27:27] oneToClear GPIO14_EDGE_HIGH read-write [26:26] oneToClear GPIO14_EDGE_LOW read-only [25:25] GPIO14_LEVEL_HIGH read-only [24:24] GPIO14_LEVEL_LOW read-write [23:23] oneToClear GPIO13_EDGE_HIGH read-write [22:22] oneToClear GPIO13_EDGE_LOW read-only [21:21] GPIO13_LEVEL_HIGH read-only [20:20] GPIO13_LEVEL_LOW read-write [19:19] oneToClear GPIO12_EDGE_HIGH read-write [18:18] oneToClear GPIO12_EDGE_LOW read-only [17:17] GPIO12_LEVEL_HIGH read-only [16:16] GPIO12_LEVEL_LOW read-write [15:15] oneToClear GPIO11_EDGE_HIGH read-write [14:14] oneToClear GPIO11_EDGE_LOW read-only [13:13] GPIO11_LEVEL_HIGH read-only [12:12] GPIO11_LEVEL_LOW read-write [11:11] oneToClear GPIO10_EDGE_HIGH read-write [10:10] oneToClear GPIO10_EDGE_LOW read-only [9:9] GPIO10_LEVEL_HIGH read-only [8:8] GPIO10_LEVEL_LOW read-write [7:7] oneToClear GPIO9_EDGE_HIGH read-write [6:6] oneToClear GPIO9_EDGE_LOW read-only [5:5] GPIO9_LEVEL_HIGH read-only [4:4] GPIO9_LEVEL_LOW read-write [3:3] oneToClear GPIO8_EDGE_HIGH read-write [2:2] oneToClear GPIO8_EDGE_LOW read-only [1:1] GPIO8_LEVEL_HIGH read-only [0:0] GPIO8_LEVEL_LOW INTR1 0x00000000 0x00f8 Raw Interrupts read-write [31:31] oneToClear GPIO23_EDGE_HIGH read-write [30:30] oneToClear GPIO23_EDGE_LOW read-only [29:29] GPIO23_LEVEL_HIGH read-only [28:28] GPIO23_LEVEL_LOW read-write [27:27] oneToClear GPIO22_EDGE_HIGH read-write [26:26] oneToClear GPIO22_EDGE_LOW read-only [25:25] GPIO22_LEVEL_HIGH read-only [24:24] GPIO22_LEVEL_LOW read-write [23:23] oneToClear GPIO21_EDGE_HIGH read-write [22:22] oneToClear GPIO21_EDGE_LOW read-only [21:21] GPIO21_LEVEL_HIGH read-only [20:20] GPIO21_LEVEL_LOW read-write [19:19] oneToClear GPIO20_EDGE_HIGH read-write [18:18] oneToClear GPIO20_EDGE_LOW read-only [17:17] GPIO20_LEVEL_HIGH read-only [16:16] GPIO20_LEVEL_LOW read-write [15:15] oneToClear GPIO19_EDGE_HIGH read-write [14:14] oneToClear GPIO19_EDGE_LOW read-only [13:13] GPIO19_LEVEL_HIGH read-only [12:12] GPIO19_LEVEL_LOW read-write [11:11] oneToClear GPIO18_EDGE_HIGH read-write [10:10] oneToClear GPIO18_EDGE_LOW read-only [9:9] GPIO18_LEVEL_HIGH read-only [8:8] GPIO18_LEVEL_LOW read-write [7:7] oneToClear GPIO17_EDGE_HIGH read-write [6:6] oneToClear GPIO17_EDGE_LOW read-only [5:5] GPIO17_LEVEL_HIGH read-only [4:4] GPIO17_LEVEL_LOW read-write [3:3] oneToClear GPIO16_EDGE_HIGH read-write [2:2] oneToClear GPIO16_EDGE_LOW read-only [1:1] GPIO16_LEVEL_HIGH read-only [0:0] GPIO16_LEVEL_LOW INTR2 0x00000000 0x00fc Raw Interrupts read-write [23:23] oneToClear GPIO29_EDGE_HIGH read-write [22:22] oneToClear GPIO29_EDGE_LOW read-only [21:21] GPIO29_LEVEL_HIGH read-only [20:20] GPIO29_LEVEL_LOW read-write [19:19] oneToClear GPIO28_EDGE_HIGH read-write [18:18] oneToClear GPIO28_EDGE_LOW read-only [17:17] GPIO28_LEVEL_HIGH read-only [16:16] GPIO28_LEVEL_LOW read-write [15:15] oneToClear GPIO27_EDGE_HIGH read-write [14:14] oneToClear GPIO27_EDGE_LOW read-only [13:13] GPIO27_LEVEL_HIGH read-only [12:12] GPIO27_LEVEL_LOW read-write [11:11] oneToClear GPIO26_EDGE_HIGH read-write [10:10] oneToClear GPIO26_EDGE_LOW read-only [9:9] GPIO26_LEVEL_HIGH read-only [8:8] GPIO26_LEVEL_LOW read-write [7:7] oneToClear GPIO25_EDGE_HIGH read-write [6:6] oneToClear GPIO25_EDGE_LOW read-only [5:5] GPIO25_LEVEL_HIGH read-only [4:4] GPIO25_LEVEL_LOW read-write [3:3] oneToClear GPIO24_EDGE_HIGH read-write [2:2] oneToClear GPIO24_EDGE_LOW read-only [1:1] GPIO24_LEVEL_HIGH read-only [0:0] GPIO24_LEVEL_LOW INTR3 0x00000000 0x0100 Interrupt Enable for proc0 read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW PROC0_INTE0 0x00000000 0x0104 Interrupt Enable for proc0 read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW PROC0_INTE1 0x00000000 0x0108 Interrupt Enable for proc0 read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW PROC0_INTE2 0x00000000 0x010c Interrupt Enable for proc0 read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW PROC0_INTE3 0x00000000 0x0110 Interrupt Force for proc0 read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW PROC0_INTF0 0x00000000 0x0114 Interrupt Force for proc0 read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW PROC0_INTF1 0x00000000 0x0118 Interrupt Force for proc0 read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW PROC0_INTF2 0x00000000 0x011c Interrupt Force for proc0 read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW PROC0_INTF3 0x00000000 0x0120 Interrupt status after masking & forcing for proc0 read-only [31:31] GPIO7_EDGE_HIGH read-only [30:30] GPIO7_EDGE_LOW read-only [29:29] GPIO7_LEVEL_HIGH read-only [28:28] GPIO7_LEVEL_LOW read-only [27:27] GPIO6_EDGE_HIGH read-only [26:26] GPIO6_EDGE_LOW read-only [25:25] GPIO6_LEVEL_HIGH read-only [24:24] GPIO6_LEVEL_LOW read-only [23:23] GPIO5_EDGE_HIGH read-only [22:22] GPIO5_EDGE_LOW read-only [21:21] GPIO5_LEVEL_HIGH read-only [20:20] GPIO5_LEVEL_LOW read-only [19:19] GPIO4_EDGE_HIGH read-only [18:18] GPIO4_EDGE_LOW read-only [17:17] GPIO4_LEVEL_HIGH read-only [16:16] GPIO4_LEVEL_LOW read-only [15:15] GPIO3_EDGE_HIGH read-only [14:14] GPIO3_EDGE_LOW read-only [13:13] GPIO3_LEVEL_HIGH read-only [12:12] GPIO3_LEVEL_LOW read-only [11:11] GPIO2_EDGE_HIGH read-only [10:10] GPIO2_EDGE_LOW read-only [9:9] GPIO2_LEVEL_HIGH read-only [8:8] GPIO2_LEVEL_LOW read-only [7:7] GPIO1_EDGE_HIGH read-only [6:6] GPIO1_EDGE_LOW read-only [5:5] GPIO1_LEVEL_HIGH read-only [4:4] GPIO1_LEVEL_LOW read-only [3:3] GPIO0_EDGE_HIGH read-only [2:2] GPIO0_EDGE_LOW read-only [1:1] GPIO0_LEVEL_HIGH read-only [0:0] GPIO0_LEVEL_LOW PROC0_INTS0 0x00000000 0x0124 Interrupt status after masking & forcing for proc0 read-only [31:31] GPIO15_EDGE_HIGH read-only [30:30] GPIO15_EDGE_LOW read-only [29:29] GPIO15_LEVEL_HIGH read-only [28:28] GPIO15_LEVEL_LOW read-only [27:27] GPIO14_EDGE_HIGH read-only [26:26] GPIO14_EDGE_LOW read-only [25:25] GPIO14_LEVEL_HIGH read-only [24:24] GPIO14_LEVEL_LOW read-only [23:23] GPIO13_EDGE_HIGH read-only [22:22] GPIO13_EDGE_LOW read-only [21:21] GPIO13_LEVEL_HIGH read-only [20:20] GPIO13_LEVEL_LOW read-only [19:19] GPIO12_EDGE_HIGH read-only [18:18] GPIO12_EDGE_LOW read-only [17:17] GPIO12_LEVEL_HIGH read-only [16:16] GPIO12_LEVEL_LOW read-only [15:15] GPIO11_EDGE_HIGH read-only [14:14] GPIO11_EDGE_LOW read-only [13:13] GPIO11_LEVEL_HIGH read-only [12:12] GPIO11_LEVEL_LOW read-only [11:11] GPIO10_EDGE_HIGH read-only [10:10] GPIO10_EDGE_LOW read-only [9:9] GPIO10_LEVEL_HIGH read-only [8:8] GPIO10_LEVEL_LOW read-only [7:7] GPIO9_EDGE_HIGH read-only [6:6] GPIO9_EDGE_LOW read-only [5:5] GPIO9_LEVEL_HIGH read-only [4:4] GPIO9_LEVEL_LOW read-only [3:3] GPIO8_EDGE_HIGH read-only [2:2] GPIO8_EDGE_LOW read-only [1:1] GPIO8_LEVEL_HIGH read-only [0:0] GPIO8_LEVEL_LOW PROC0_INTS1 0x00000000 0x0128 Interrupt status after masking & forcing for proc0 read-only [31:31] GPIO23_EDGE_HIGH read-only [30:30] GPIO23_EDGE_LOW read-only [29:29] GPIO23_LEVEL_HIGH read-only [28:28] GPIO23_LEVEL_LOW read-only [27:27] GPIO22_EDGE_HIGH read-only [26:26] GPIO22_EDGE_LOW read-only [25:25] GPIO22_LEVEL_HIGH read-only [24:24] GPIO22_LEVEL_LOW read-only [23:23] GPIO21_EDGE_HIGH read-only [22:22] GPIO21_EDGE_LOW read-only [21:21] GPIO21_LEVEL_HIGH read-only [20:20] GPIO21_LEVEL_LOW read-only [19:19] GPIO20_EDGE_HIGH read-only [18:18] GPIO20_EDGE_LOW read-only [17:17] GPIO20_LEVEL_HIGH read-only [16:16] GPIO20_LEVEL_LOW read-only [15:15] GPIO19_EDGE_HIGH read-only [14:14] GPIO19_EDGE_LOW read-only [13:13] GPIO19_LEVEL_HIGH read-only [12:12] GPIO19_LEVEL_LOW read-only [11:11] GPIO18_EDGE_HIGH read-only [10:10] GPIO18_EDGE_LOW read-only [9:9] GPIO18_LEVEL_HIGH read-only [8:8] GPIO18_LEVEL_LOW read-only [7:7] GPIO17_EDGE_HIGH read-only [6:6] GPIO17_EDGE_LOW read-only [5:5] GPIO17_LEVEL_HIGH read-only [4:4] GPIO17_LEVEL_LOW read-only [3:3] GPIO16_EDGE_HIGH read-only [2:2] GPIO16_EDGE_LOW read-only [1:1] GPIO16_LEVEL_HIGH read-only [0:0] GPIO16_LEVEL_LOW PROC0_INTS2 0x00000000 0x012c Interrupt status after masking & forcing for proc0 read-only [23:23] GPIO29_EDGE_HIGH read-only [22:22] GPIO29_EDGE_LOW read-only [21:21] GPIO29_LEVEL_HIGH read-only [20:20] GPIO29_LEVEL_LOW read-only [19:19] GPIO28_EDGE_HIGH read-only [18:18] GPIO28_EDGE_LOW read-only [17:17] GPIO28_LEVEL_HIGH read-only [16:16] GPIO28_LEVEL_LOW read-only [15:15] GPIO27_EDGE_HIGH read-only [14:14] GPIO27_EDGE_LOW read-only [13:13] GPIO27_LEVEL_HIGH read-only [12:12] GPIO27_LEVEL_LOW read-only [11:11] GPIO26_EDGE_HIGH read-only [10:10] GPIO26_EDGE_LOW read-only [9:9] GPIO26_LEVEL_HIGH read-only [8:8] GPIO26_LEVEL_LOW read-only [7:7] GPIO25_EDGE_HIGH read-only [6:6] GPIO25_EDGE_LOW read-only [5:5] GPIO25_LEVEL_HIGH read-only [4:4] GPIO25_LEVEL_LOW read-only [3:3] GPIO24_EDGE_HIGH read-only [2:2] GPIO24_EDGE_LOW read-only [1:1] GPIO24_LEVEL_HIGH read-only [0:0] GPIO24_LEVEL_LOW PROC0_INTS3 0x00000000 0x0130 Interrupt Enable for proc1 read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW PROC1_INTE0 0x00000000 0x0134 Interrupt Enable for proc1 read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW PROC1_INTE1 0x00000000 0x0138 Interrupt Enable for proc1 read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW PROC1_INTE2 0x00000000 0x013c Interrupt Enable for proc1 read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW PROC1_INTE3 0x00000000 0x0140 Interrupt Force for proc1 read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW PROC1_INTF0 0x00000000 0x0144 Interrupt Force for proc1 read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW PROC1_INTF1 0x00000000 0x0148 Interrupt Force for proc1 read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW PROC1_INTF2 0x00000000 0x014c Interrupt Force for proc1 read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW PROC1_INTF3 0x00000000 0x0150 Interrupt status after masking & forcing for proc1 read-only [31:31] GPIO7_EDGE_HIGH read-only [30:30] GPIO7_EDGE_LOW read-only [29:29] GPIO7_LEVEL_HIGH read-only [28:28] GPIO7_LEVEL_LOW read-only [27:27] GPIO6_EDGE_HIGH read-only [26:26] GPIO6_EDGE_LOW read-only [25:25] GPIO6_LEVEL_HIGH read-only [24:24] GPIO6_LEVEL_LOW read-only [23:23] GPIO5_EDGE_HIGH read-only [22:22] GPIO5_EDGE_LOW read-only [21:21] GPIO5_LEVEL_HIGH read-only [20:20] GPIO5_LEVEL_LOW read-only [19:19] GPIO4_EDGE_HIGH read-only [18:18] GPIO4_EDGE_LOW read-only [17:17] GPIO4_LEVEL_HIGH read-only [16:16] GPIO4_LEVEL_LOW read-only [15:15] GPIO3_EDGE_HIGH read-only [14:14] GPIO3_EDGE_LOW read-only [13:13] GPIO3_LEVEL_HIGH read-only [12:12] GPIO3_LEVEL_LOW read-only [11:11] GPIO2_EDGE_HIGH read-only [10:10] GPIO2_EDGE_LOW read-only [9:9] GPIO2_LEVEL_HIGH read-only [8:8] GPIO2_LEVEL_LOW read-only [7:7] GPIO1_EDGE_HIGH read-only [6:6] GPIO1_EDGE_LOW read-only [5:5] GPIO1_LEVEL_HIGH read-only [4:4] GPIO1_LEVEL_LOW read-only [3:3] GPIO0_EDGE_HIGH read-only [2:2] GPIO0_EDGE_LOW read-only [1:1] GPIO0_LEVEL_HIGH read-only [0:0] GPIO0_LEVEL_LOW PROC1_INTS0 0x00000000 0x0154 Interrupt status after masking & forcing for proc1 read-only [31:31] GPIO15_EDGE_HIGH read-only [30:30] GPIO15_EDGE_LOW read-only [29:29] GPIO15_LEVEL_HIGH read-only [28:28] GPIO15_LEVEL_LOW read-only [27:27] GPIO14_EDGE_HIGH read-only [26:26] GPIO14_EDGE_LOW read-only [25:25] GPIO14_LEVEL_HIGH read-only [24:24] GPIO14_LEVEL_LOW read-only [23:23] GPIO13_EDGE_HIGH read-only [22:22] GPIO13_EDGE_LOW read-only [21:21] GPIO13_LEVEL_HIGH read-only [20:20] GPIO13_LEVEL_LOW read-only [19:19] GPIO12_EDGE_HIGH read-only [18:18] GPIO12_EDGE_LOW read-only [17:17] GPIO12_LEVEL_HIGH read-only [16:16] GPIO12_LEVEL_LOW read-only [15:15] GPIO11_EDGE_HIGH read-only [14:14] GPIO11_EDGE_LOW read-only [13:13] GPIO11_LEVEL_HIGH read-only [12:12] GPIO11_LEVEL_LOW read-only [11:11] GPIO10_EDGE_HIGH read-only [10:10] GPIO10_EDGE_LOW read-only [9:9] GPIO10_LEVEL_HIGH read-only [8:8] GPIO10_LEVEL_LOW read-only [7:7] GPIO9_EDGE_HIGH read-only [6:6] GPIO9_EDGE_LOW read-only [5:5] GPIO9_LEVEL_HIGH read-only [4:4] GPIO9_LEVEL_LOW read-only [3:3] GPIO8_EDGE_HIGH read-only [2:2] GPIO8_EDGE_LOW read-only [1:1] GPIO8_LEVEL_HIGH read-only [0:0] GPIO8_LEVEL_LOW PROC1_INTS1 0x00000000 0x0158 Interrupt status after masking & forcing for proc1 read-only [31:31] GPIO23_EDGE_HIGH read-only [30:30] GPIO23_EDGE_LOW read-only [29:29] GPIO23_LEVEL_HIGH read-only [28:28] GPIO23_LEVEL_LOW read-only [27:27] GPIO22_EDGE_HIGH read-only [26:26] GPIO22_EDGE_LOW read-only [25:25] GPIO22_LEVEL_HIGH read-only [24:24] GPIO22_LEVEL_LOW read-only [23:23] GPIO21_EDGE_HIGH read-only [22:22] GPIO21_EDGE_LOW read-only [21:21] GPIO21_LEVEL_HIGH read-only [20:20] GPIO21_LEVEL_LOW read-only [19:19] GPIO20_EDGE_HIGH read-only [18:18] GPIO20_EDGE_LOW read-only [17:17] GPIO20_LEVEL_HIGH read-only [16:16] GPIO20_LEVEL_LOW read-only [15:15] GPIO19_EDGE_HIGH read-only [14:14] GPIO19_EDGE_LOW read-only [13:13] GPIO19_LEVEL_HIGH read-only [12:12] GPIO19_LEVEL_LOW read-only [11:11] GPIO18_EDGE_HIGH read-only [10:10] GPIO18_EDGE_LOW read-only [9:9] GPIO18_LEVEL_HIGH read-only [8:8] GPIO18_LEVEL_LOW read-only [7:7] GPIO17_EDGE_HIGH read-only [6:6] GPIO17_EDGE_LOW read-only [5:5] GPIO17_LEVEL_HIGH read-only [4:4] GPIO17_LEVEL_LOW read-only [3:3] GPIO16_EDGE_HIGH read-only [2:2] GPIO16_EDGE_LOW read-only [1:1] GPIO16_LEVEL_HIGH read-only [0:0] GPIO16_LEVEL_LOW PROC1_INTS2 0x00000000 0x015c Interrupt status after masking & forcing for proc1 read-only [23:23] GPIO29_EDGE_HIGH read-only [22:22] GPIO29_EDGE_LOW read-only [21:21] GPIO29_LEVEL_HIGH read-only [20:20] GPIO29_LEVEL_LOW read-only [19:19] GPIO28_EDGE_HIGH read-only [18:18] GPIO28_EDGE_LOW read-only [17:17] GPIO28_LEVEL_HIGH read-only [16:16] GPIO28_LEVEL_LOW read-only [15:15] GPIO27_EDGE_HIGH read-only [14:14] GPIO27_EDGE_LOW read-only [13:13] GPIO27_LEVEL_HIGH read-only [12:12] GPIO27_LEVEL_LOW read-only [11:11] GPIO26_EDGE_HIGH read-only [10:10] GPIO26_EDGE_LOW read-only [9:9] GPIO26_LEVEL_HIGH read-only [8:8] GPIO26_LEVEL_LOW read-only [7:7] GPIO25_EDGE_HIGH read-only [6:6] GPIO25_EDGE_LOW read-only [5:5] GPIO25_LEVEL_HIGH read-only [4:4] GPIO25_LEVEL_LOW read-only [3:3] GPIO24_EDGE_HIGH read-only [2:2] GPIO24_EDGE_LOW read-only [1:1] GPIO24_LEVEL_HIGH read-only [0:0] GPIO24_LEVEL_LOW PROC1_INTS3 0x00000000 0x0160 Interrupt Enable for dormant_wake read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW DORMANT_WAKE_INTE0 0x00000000 0x0164 Interrupt Enable for dormant_wake read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW DORMANT_WAKE_INTE1 0x00000000 0x0168 Interrupt Enable for dormant_wake read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW DORMANT_WAKE_INTE2 0x00000000 0x016c Interrupt Enable for dormant_wake read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW DORMANT_WAKE_INTE3 0x00000000 0x0170 Interrupt Force for dormant_wake read-write [31:31] GPIO7_EDGE_HIGH read-write [30:30] GPIO7_EDGE_LOW read-write [29:29] GPIO7_LEVEL_HIGH read-write [28:28] GPIO7_LEVEL_LOW read-write [27:27] GPIO6_EDGE_HIGH read-write [26:26] GPIO6_EDGE_LOW read-write [25:25] GPIO6_LEVEL_HIGH read-write [24:24] GPIO6_LEVEL_LOW read-write [23:23] GPIO5_EDGE_HIGH read-write [22:22] GPIO5_EDGE_LOW read-write [21:21] GPIO5_LEVEL_HIGH read-write [20:20] GPIO5_LEVEL_LOW read-write [19:19] GPIO4_EDGE_HIGH read-write [18:18] GPIO4_EDGE_LOW read-write [17:17] GPIO4_LEVEL_HIGH read-write [16:16] GPIO4_LEVEL_LOW read-write [15:15] GPIO3_EDGE_HIGH read-write [14:14] GPIO3_EDGE_LOW read-write [13:13] GPIO3_LEVEL_HIGH read-write [12:12] GPIO3_LEVEL_LOW read-write [11:11] GPIO2_EDGE_HIGH read-write [10:10] GPIO2_EDGE_LOW read-write [9:9] GPIO2_LEVEL_HIGH read-write [8:8] GPIO2_LEVEL_LOW read-write [7:7] GPIO1_EDGE_HIGH read-write [6:6] GPIO1_EDGE_LOW read-write [5:5] GPIO1_LEVEL_HIGH read-write [4:4] GPIO1_LEVEL_LOW read-write [3:3] GPIO0_EDGE_HIGH read-write [2:2] GPIO0_EDGE_LOW read-write [1:1] GPIO0_LEVEL_HIGH read-write [0:0] GPIO0_LEVEL_LOW DORMANT_WAKE_INTF0 0x00000000 0x0174 Interrupt Force for dormant_wake read-write [31:31] GPIO15_EDGE_HIGH read-write [30:30] GPIO15_EDGE_LOW read-write [29:29] GPIO15_LEVEL_HIGH read-write [28:28] GPIO15_LEVEL_LOW read-write [27:27] GPIO14_EDGE_HIGH read-write [26:26] GPIO14_EDGE_LOW read-write [25:25] GPIO14_LEVEL_HIGH read-write [24:24] GPIO14_LEVEL_LOW read-write [23:23] GPIO13_EDGE_HIGH read-write [22:22] GPIO13_EDGE_LOW read-write [21:21] GPIO13_LEVEL_HIGH read-write [20:20] GPIO13_LEVEL_LOW read-write [19:19] GPIO12_EDGE_HIGH read-write [18:18] GPIO12_EDGE_LOW read-write [17:17] GPIO12_LEVEL_HIGH read-write [16:16] GPIO12_LEVEL_LOW read-write [15:15] GPIO11_EDGE_HIGH read-write [14:14] GPIO11_EDGE_LOW read-write [13:13] GPIO11_LEVEL_HIGH read-write [12:12] GPIO11_LEVEL_LOW read-write [11:11] GPIO10_EDGE_HIGH read-write [10:10] GPIO10_EDGE_LOW read-write [9:9] GPIO10_LEVEL_HIGH read-write [8:8] GPIO10_LEVEL_LOW read-write [7:7] GPIO9_EDGE_HIGH read-write [6:6] GPIO9_EDGE_LOW read-write [5:5] GPIO9_LEVEL_HIGH read-write [4:4] GPIO9_LEVEL_LOW read-write [3:3] GPIO8_EDGE_HIGH read-write [2:2] GPIO8_EDGE_LOW read-write [1:1] GPIO8_LEVEL_HIGH read-write [0:0] GPIO8_LEVEL_LOW DORMANT_WAKE_INTF1 0x00000000 0x0178 Interrupt Force for dormant_wake read-write [31:31] GPIO23_EDGE_HIGH read-write [30:30] GPIO23_EDGE_LOW read-write [29:29] GPIO23_LEVEL_HIGH read-write [28:28] GPIO23_LEVEL_LOW read-write [27:27] GPIO22_EDGE_HIGH read-write [26:26] GPIO22_EDGE_LOW read-write [25:25] GPIO22_LEVEL_HIGH read-write [24:24] GPIO22_LEVEL_LOW read-write [23:23] GPIO21_EDGE_HIGH read-write [22:22] GPIO21_EDGE_LOW read-write [21:21] GPIO21_LEVEL_HIGH read-write [20:20] GPIO21_LEVEL_LOW read-write [19:19] GPIO20_EDGE_HIGH read-write [18:18] GPIO20_EDGE_LOW read-write [17:17] GPIO20_LEVEL_HIGH read-write [16:16] GPIO20_LEVEL_LOW read-write [15:15] GPIO19_EDGE_HIGH read-write [14:14] GPIO19_EDGE_LOW read-write [13:13] GPIO19_LEVEL_HIGH read-write [12:12] GPIO19_LEVEL_LOW read-write [11:11] GPIO18_EDGE_HIGH read-write [10:10] GPIO18_EDGE_LOW read-write [9:9] GPIO18_LEVEL_HIGH read-write [8:8] GPIO18_LEVEL_LOW read-write [7:7] GPIO17_EDGE_HIGH read-write [6:6] GPIO17_EDGE_LOW read-write [5:5] GPIO17_LEVEL_HIGH read-write [4:4] GPIO17_LEVEL_LOW read-write [3:3] GPIO16_EDGE_HIGH read-write [2:2] GPIO16_EDGE_LOW read-write [1:1] GPIO16_LEVEL_HIGH read-write [0:0] GPIO16_LEVEL_LOW DORMANT_WAKE_INTF2 0x00000000 0x017c Interrupt Force for dormant_wake read-write [23:23] GPIO29_EDGE_HIGH read-write [22:22] GPIO29_EDGE_LOW read-write [21:21] GPIO29_LEVEL_HIGH read-write [20:20] GPIO29_LEVEL_LOW read-write [19:19] GPIO28_EDGE_HIGH read-write [18:18] GPIO28_EDGE_LOW read-write [17:17] GPIO28_LEVEL_HIGH read-write [16:16] GPIO28_LEVEL_LOW read-write [15:15] GPIO27_EDGE_HIGH read-write [14:14] GPIO27_EDGE_LOW read-write [13:13] GPIO27_LEVEL_HIGH read-write [12:12] GPIO27_LEVEL_LOW read-write [11:11] GPIO26_EDGE_HIGH read-write [10:10] GPIO26_EDGE_LOW read-write [9:9] GPIO26_LEVEL_HIGH read-write [8:8] GPIO26_LEVEL_LOW read-write [7:7] GPIO25_EDGE_HIGH read-write [6:6] GPIO25_EDGE_LOW read-write [5:5] GPIO25_LEVEL_HIGH read-write [4:4] GPIO25_LEVEL_LOW read-write [3:3] GPIO24_EDGE_HIGH read-write [2:2] GPIO24_EDGE_LOW read-write [1:1] GPIO24_LEVEL_HIGH read-write [0:0] GPIO24_LEVEL_LOW DORMANT_WAKE_INTF3 0x00000000 0x0180 Interrupt status after masking & forcing for dormant_wake read-only [31:31] GPIO7_EDGE_HIGH read-only [30:30] GPIO7_EDGE_LOW read-only [29:29] GPIO7_LEVEL_HIGH read-only [28:28] GPIO7_LEVEL_LOW read-only [27:27] GPIO6_EDGE_HIGH read-only [26:26] GPIO6_EDGE_LOW read-only [25:25] GPIO6_LEVEL_HIGH read-only [24:24] GPIO6_LEVEL_LOW read-only [23:23] GPIO5_EDGE_HIGH read-only [22:22] GPIO5_EDGE_LOW read-only [21:21] GPIO5_LEVEL_HIGH read-only [20:20] GPIO5_LEVEL_LOW read-only [19:19] GPIO4_EDGE_HIGH read-only [18:18] GPIO4_EDGE_LOW read-only [17:17] GPIO4_LEVEL_HIGH read-only [16:16] GPIO4_LEVEL_LOW read-only [15:15] GPIO3_EDGE_HIGH read-only [14:14] GPIO3_EDGE_LOW read-only [13:13] GPIO3_LEVEL_HIGH read-only [12:12] GPIO3_LEVEL_LOW read-only [11:11] GPIO2_EDGE_HIGH read-only [10:10] GPIO2_EDGE_LOW read-only [9:9] GPIO2_LEVEL_HIGH read-only [8:8] GPIO2_LEVEL_LOW read-only [7:7] GPIO1_EDGE_HIGH read-only [6:6] GPIO1_EDGE_LOW read-only [5:5] GPIO1_LEVEL_HIGH read-only [4:4] GPIO1_LEVEL_LOW read-only [3:3] GPIO0_EDGE_HIGH read-only [2:2] GPIO0_EDGE_LOW read-only [1:1] GPIO0_LEVEL_HIGH read-only [0:0] GPIO0_LEVEL_LOW DORMANT_WAKE_INTS0 0x00000000 0x0184 Interrupt status after masking & forcing for dormant_wake read-only [31:31] GPIO15_EDGE_HIGH read-only [30:30] GPIO15_EDGE_LOW read-only [29:29] GPIO15_LEVEL_HIGH read-only [28:28] GPIO15_LEVEL_LOW read-only [27:27] GPIO14_EDGE_HIGH read-only [26:26] GPIO14_EDGE_LOW read-only [25:25] GPIO14_LEVEL_HIGH read-only [24:24] GPIO14_LEVEL_LOW read-only [23:23] GPIO13_EDGE_HIGH read-only [22:22] GPIO13_EDGE_LOW read-only [21:21] GPIO13_LEVEL_HIGH read-only [20:20] GPIO13_LEVEL_LOW read-only [19:19] GPIO12_EDGE_HIGH read-only [18:18] GPIO12_EDGE_LOW read-only [17:17] GPIO12_LEVEL_HIGH read-only [16:16] GPIO12_LEVEL_LOW read-only [15:15] GPIO11_EDGE_HIGH read-only [14:14] GPIO11_EDGE_LOW read-only [13:13] GPIO11_LEVEL_HIGH read-only [12:12] GPIO11_LEVEL_LOW read-only [11:11] GPIO10_EDGE_HIGH read-only [10:10] GPIO10_EDGE_LOW read-only [9:9] GPIO10_LEVEL_HIGH read-only [8:8] GPIO10_LEVEL_LOW read-only [7:7] GPIO9_EDGE_HIGH read-only [6:6] GPIO9_EDGE_LOW read-only [5:5] GPIO9_LEVEL_HIGH read-only [4:4] GPIO9_LEVEL_LOW read-only [3:3] GPIO8_EDGE_HIGH read-only [2:2] GPIO8_EDGE_LOW read-only [1:1] GPIO8_LEVEL_HIGH read-only [0:0] GPIO8_LEVEL_LOW DORMANT_WAKE_INTS1 0x00000000 0x0188 Interrupt status after masking & forcing for dormant_wake read-only [31:31] GPIO23_EDGE_HIGH read-only [30:30] GPIO23_EDGE_LOW read-only [29:29] GPIO23_LEVEL_HIGH read-only [28:28] GPIO23_LEVEL_LOW read-only [27:27] GPIO22_EDGE_HIGH read-only [26:26] GPIO22_EDGE_LOW read-only [25:25] GPIO22_LEVEL_HIGH read-only [24:24] GPIO22_LEVEL_LOW read-only [23:23] GPIO21_EDGE_HIGH read-only [22:22] GPIO21_EDGE_LOW read-only [21:21] GPIO21_LEVEL_HIGH read-only [20:20] GPIO21_LEVEL_LOW read-only [19:19] GPIO20_EDGE_HIGH read-only [18:18] GPIO20_EDGE_LOW read-only [17:17] GPIO20_LEVEL_HIGH read-only [16:16] GPIO20_LEVEL_LOW read-only [15:15] GPIO19_EDGE_HIGH read-only [14:14] GPIO19_EDGE_LOW read-only [13:13] GPIO19_LEVEL_HIGH read-only [12:12] GPIO19_LEVEL_LOW read-only [11:11] GPIO18_EDGE_HIGH read-only [10:10] GPIO18_EDGE_LOW read-only [9:9] GPIO18_LEVEL_HIGH read-only [8:8] GPIO18_LEVEL_LOW read-only [7:7] GPIO17_EDGE_HIGH read-only [6:6] GPIO17_EDGE_LOW read-only [5:5] GPIO17_LEVEL_HIGH read-only [4:4] GPIO17_LEVEL_LOW read-only [3:3] GPIO16_EDGE_HIGH read-only [2:2] GPIO16_EDGE_LOW read-only [1:1] GPIO16_LEVEL_HIGH read-only [0:0] GPIO16_LEVEL_LOW DORMANT_WAKE_INTS2 0x00000000 0x018c Interrupt status after masking & forcing for dormant_wake read-only [23:23] GPIO29_EDGE_HIGH read-only [22:22] GPIO29_EDGE_LOW read-only [21:21] GPIO29_LEVEL_HIGH read-only [20:20] GPIO29_LEVEL_LOW read-only [19:19] GPIO28_EDGE_HIGH read-only [18:18] GPIO28_EDGE_LOW read-only [17:17] GPIO28_LEVEL_HIGH read-only [16:16] GPIO28_LEVEL_LOW read-only [15:15] GPIO27_EDGE_HIGH read-only [14:14] GPIO27_EDGE_LOW read-only [13:13] GPIO27_LEVEL_HIGH read-only [12:12] GPIO27_LEVEL_LOW read-only [11:11] GPIO26_EDGE_HIGH read-only [10:10] GPIO26_EDGE_LOW read-only [9:9] GPIO26_LEVEL_HIGH read-only [8:8] GPIO26_LEVEL_LOW read-only [7:7] GPIO25_EDGE_HIGH read-only [6:6] GPIO25_EDGE_LOW read-only [5:5] GPIO25_LEVEL_HIGH read-only [4:4] GPIO25_LEVEL_LOW read-only [3:3] GPIO24_EDGE_HIGH read-only [2:2] GPIO24_EDGE_LOW read-only [1:1] GPIO24_LEVEL_HIGH read-only [0:0] GPIO24_LEVEL_LOW DORMANT_WAKE_INTS3 0x00000000 32 1 0 0x1000 registers 0x40018000 IO_IRQ_QSPI 14 IO_QSPI 0x0000 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SCLK_STATUS 0x00000000 0x0004 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sclk 0 sio_30 5 null 31 FUNCSEL GPIO_QSPI_SCLK_CTRL 0x0000001f 0x0008 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SS_STATUS 0x00000000 0x000c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_ss_n 0 sio_31 5 null 31 FUNCSEL GPIO_QSPI_SS_CTRL 0x0000001f 0x0010 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SD0_STATUS 0x00000000 0x0014 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sd0 0 sio_32 5 null 31 FUNCSEL GPIO_QSPI_SD0_CTRL 0x0000001f 0x0018 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SD1_STATUS 0x00000000 0x001c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sd1 0 sio_33 5 null 31 FUNCSEL GPIO_QSPI_SD1_CTRL 0x0000001f 0x0020 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SD2_STATUS 0x00000000 0x0024 GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sd2 0 sio_34 5 null 31 FUNCSEL GPIO_QSPI_SD2_CTRL 0x0000001f 0x0028 GPIO status read-only [26:26] interrupt to processors, after override is applied IRQTOPROC read-only [24:24] interrupt from pad before override is applied IRQFROMPAD read-only [19:19] input signal to peripheral, after override is applied INTOPERI read-only [17:17] input signal from pad, before override is applied INFROMPAD read-only [13:13] output enable to pad after register override is applied OETOPAD read-only [12:12] output enable from selected peripheral, before register override is applied OEFROMPERI read-only [9:9] output signal to pad after register override is applied OUTTOPAD read-only [8:8] output signal from selected peripheral, before register override is applied OUTFROMPERI GPIO_QSPI_SD3_STATUS 0x00000000 0x002c GPIO control including function select and overrides. read-write [29:28] don't invert the interrupt NORMAL 0 invert the interrupt INVERT 1 drive interrupt low LOW 2 drive interrupt high HIGH 3 IRQOVER read-write [17:16] don't invert the peri input NORMAL 0 invert the peri input INVERT 1 drive peri input low LOW 2 drive peri input high HIGH 3 INOVER read-write [13:12] drive output enable from peripheral signal selected by funcsel NORMAL 0 drive output enable from inverse of peripheral signal selected by funcsel INVERT 1 disable output DISABLE 2 enable output ENABLE 3 OEOVER read-write [9:8] drive output from peripheral signal selected by funcsel NORMAL 0 drive output from inverse of peripheral signal selected by funcsel INVERT 1 drive output low LOW 2 drive output high HIGH 3 OUTOVER read-write [4:0] 0-31 -> selects pin function according to the gpio table\n 31 == NULL xip_sd3 0 sio_35 5 null 31 FUNCSEL GPIO_QSPI_SD3_CTRL 0x0000001f 0x0030 Raw Interrupts read-write [23:23] oneToClear GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] oneToClear GPIO_QSPI_SD3_EDGE_LOW read-only [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-only [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] oneToClear GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] oneToClear GPIO_QSPI_SD2_EDGE_LOW read-only [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-only [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] oneToClear GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] oneToClear GPIO_QSPI_SD1_EDGE_LOW read-only [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-only [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] oneToClear GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] oneToClear GPIO_QSPI_SD0_EDGE_LOW read-only [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-only [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] oneToClear GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] oneToClear GPIO_QSPI_SS_EDGE_LOW read-only [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-only [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] oneToClear GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] oneToClear GPIO_QSPI_SCLK_EDGE_LOW read-only [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-only [0:0] GPIO_QSPI_SCLK_LEVEL_LOW INTR 0x00000000 0x0034 Interrupt Enable for proc0 read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC0_INTE 0x00000000 0x0038 Interrupt Force for proc0 read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC0_INTF 0x00000000 0x003c Interrupt status after masking & forcing for proc0 read-only [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-only [22:22] GPIO_QSPI_SD3_EDGE_LOW read-only [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-only [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-only [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-only [18:18] GPIO_QSPI_SD2_EDGE_LOW read-only [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-only [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-only [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-only [14:14] GPIO_QSPI_SD1_EDGE_LOW read-only [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-only [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-only [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-only [10:10] GPIO_QSPI_SD0_EDGE_LOW read-only [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-only [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-only [7:7] GPIO_QSPI_SS_EDGE_HIGH read-only [6:6] GPIO_QSPI_SS_EDGE_LOW read-only [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-only [4:4] GPIO_QSPI_SS_LEVEL_LOW read-only [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-only [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-only [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-only [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC0_INTS 0x00000000 0x0040 Interrupt Enable for proc1 read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC1_INTE 0x00000000 0x0044 Interrupt Force for proc1 read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC1_INTF 0x00000000 0x0048 Interrupt status after masking & forcing for proc1 read-only [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-only [22:22] GPIO_QSPI_SD3_EDGE_LOW read-only [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-only [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-only [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-only [18:18] GPIO_QSPI_SD2_EDGE_LOW read-only [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-only [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-only [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-only [14:14] GPIO_QSPI_SD1_EDGE_LOW read-only [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-only [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-only [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-only [10:10] GPIO_QSPI_SD0_EDGE_LOW read-only [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-only [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-only [7:7] GPIO_QSPI_SS_EDGE_HIGH read-only [6:6] GPIO_QSPI_SS_EDGE_LOW read-only [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-only [4:4] GPIO_QSPI_SS_LEVEL_LOW read-only [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-only [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-only [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-only [0:0] GPIO_QSPI_SCLK_LEVEL_LOW PROC1_INTS 0x00000000 0x004c Interrupt Enable for dormant_wake read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW DORMANT_WAKE_INTE 0x00000000 0x0050 Interrupt Force for dormant_wake read-write [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-write [22:22] GPIO_QSPI_SD3_EDGE_LOW read-write [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-write [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-write [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-write [18:18] GPIO_QSPI_SD2_EDGE_LOW read-write [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-write [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-write [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-write [14:14] GPIO_QSPI_SD1_EDGE_LOW read-write [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-write [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-write [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-write [10:10] GPIO_QSPI_SD0_EDGE_LOW read-write [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-write [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-write [7:7] GPIO_QSPI_SS_EDGE_HIGH read-write [6:6] GPIO_QSPI_SS_EDGE_LOW read-write [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-write [4:4] GPIO_QSPI_SS_LEVEL_LOW read-write [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-write [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-write [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-write [0:0] GPIO_QSPI_SCLK_LEVEL_LOW DORMANT_WAKE_INTF 0x00000000 0x0054 Interrupt status after masking & forcing for dormant_wake read-only [23:23] GPIO_QSPI_SD3_EDGE_HIGH read-only [22:22] GPIO_QSPI_SD3_EDGE_LOW read-only [21:21] GPIO_QSPI_SD3_LEVEL_HIGH read-only [20:20] GPIO_QSPI_SD3_LEVEL_LOW read-only [19:19] GPIO_QSPI_SD2_EDGE_HIGH read-only [18:18] GPIO_QSPI_SD2_EDGE_LOW read-only [17:17] GPIO_QSPI_SD2_LEVEL_HIGH read-only [16:16] GPIO_QSPI_SD2_LEVEL_LOW read-only [15:15] GPIO_QSPI_SD1_EDGE_HIGH read-only [14:14] GPIO_QSPI_SD1_EDGE_LOW read-only [13:13] GPIO_QSPI_SD1_LEVEL_HIGH read-only [12:12] GPIO_QSPI_SD1_LEVEL_LOW read-only [11:11] GPIO_QSPI_SD0_EDGE_HIGH read-only [10:10] GPIO_QSPI_SD0_EDGE_LOW read-only [9:9] GPIO_QSPI_SD0_LEVEL_HIGH read-only [8:8] GPIO_QSPI_SD0_LEVEL_LOW read-only [7:7] GPIO_QSPI_SS_EDGE_HIGH read-only [6:6] GPIO_QSPI_SS_EDGE_LOW read-only [5:5] GPIO_QSPI_SS_LEVEL_HIGH read-only [4:4] GPIO_QSPI_SS_LEVEL_LOW read-only [3:3] GPIO_QSPI_SCLK_EDGE_HIGH read-only [2:2] GPIO_QSPI_SCLK_EDGE_LOW read-only [1:1] GPIO_QSPI_SCLK_LEVEL_HIGH read-only [0:0] GPIO_QSPI_SCLK_LEVEL_LOW DORMANT_WAKE_INTS 0x00000000 32 1 0 0x1000 registers 0x4001c000 PADS_BANK0 0x0000 Voltage select. Per bank control read-write [0:0] Set voltage to 3.3V (DVDD >= 2V5) 3v3 0 Set voltage to 1.8V (DVDD <= 1V8) 1v8 1 VOLTAGE_SELECT VOLTAGE_SELECT 0x00000000 0x0004 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO0 0x00000056 0x0008 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO1 0x00000056 0x000c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO2 0x00000056 0x0010 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO3 0x00000056 0x0014 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO4 0x00000056 0x0018 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO5 0x00000056 0x001c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO6 0x00000056 0x0020 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO7 0x00000056 0x0024 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO8 0x00000056 0x0028 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO9 0x00000056 0x002c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO10 0x00000056 0x0030 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO11 0x00000056 0x0034 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO12 0x00000056 0x0038 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO13 0x00000056 0x003c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO14 0x00000056 0x0040 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO15 0x00000056 0x0044 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO16 0x00000056 0x0048 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO17 0x00000056 0x004c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO18 0x00000056 0x0050 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO19 0x00000056 0x0054 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO20 0x00000056 0x0058 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO21 0x00000056 0x005c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO22 0x00000056 0x0060 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO23 0x00000056 0x0064 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO24 0x00000056 0x0068 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO25 0x00000056 0x006c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO26 0x00000056 0x0070 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO27 0x00000056 0x0074 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO28 0x00000056 0x0078 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO29 0x00000056 0x007c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST SWCLK 0x000000da 0x0080 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST SWD 0x0000005a 32 1 0 0x1000 registers 0x40020000 PADS_QSPI 0x0000 Voltage select. Per bank control read-write [0:0] Set voltage to 3.3V (DVDD >= 2V5) 3v3 0 Set voltage to 1.8V (DVDD <= 1V8) 1v8 1 VOLTAGE_SELECT VOLTAGE_SELECT 0x00000000 0x0004 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SCLK 0x00000056 0x0008 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SD0 0x00000052 0x000c Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SD1 0x00000052 0x0010 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SD2 0x00000052 0x0014 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SD3 0x00000052 0x0018 Pad control register read-write [7:7] Output disable. Has priority over output enable from peripherals OD read-write [6:6] Input enable IE read-write [5:4] Drive strength. 2mA 0 4mA 1 8mA 2 12mA 3 DRIVE read-write [3:3] Pull up enable PUE read-write [2:2] Pull down enable PDE read-write [1:1] Enable schmitt trigger SCHMITT read-write [0:0] Slew rate control. 1 = Fast, 0 = Slow SLEWFAST GPIO_QSPI_SS 0x0000005a 32 1 0 0x1000 registers 0x40024000 Controls the crystal oscillator XOSC 0x0000 Crystal Oscillator Control read-write [23:12] On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\n If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\n The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. DISABLE 3358 ENABLE 4011 ENABLE read-write [11:0] Frequency range. This resets to 0xAA0 and cannot be changed. 1_15MHZ 2720 RESERVED_1 2721 RESERVED_2 2722 RESERVED_3 2723 FREQ_RANGE CTRL 0x00000000 0x0004 Crystal Oscillator Status read-only [31:31] Oscillator is running and stable STABLE read-write [24:24] An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT oneToClear BADWRITE read-only [12:12] Oscillator is enabled but not necessarily running and stable, resets to 0 ENABLED read-only [1:0] The current frequency range setting, always reads 0 1_15MHZ 0 RESERVED_1 1 RESERVED_2 2 RESERVED_3 3 FREQ_RANGE STATUS 0x00000000 read-write 0x0008 Crystal Oscillator pause control\n This is used to save power by pausing the XOSC\n On power-up this field is initialised to WAKE\n An invalid write will also select WAKE\n WARNING: stop the PLLs before selecting dormant mode\n WARNING: setup the irq before selecting dormant mode DORMANT 0x00000000 0x000c Controls the startup delay read-write [20:20] Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly X4 read-write [13:0] in multiples of 256*xtal_period DELAY STARTUP 0x00000000 0x001c A down counter running at the xosc frequency which counts to zero and stops.\n To start the counter write a non-zero value.\n Can be used for short software pauses when setting up time sensitive hardware. read-write [7:0] COUNT COUNT 0x00000000 32 1 0 0x1000 registers 0x40028000 PLL_SYS 0x0000 Control and Status\n GENERAL CONSTRAINTS:\n Reference clock frequency min=5MHz, max=800MHz\n Feedback divider min=16, max=320\n VCO frequency min=400MHz, max=1600MHz read-only [31:31] PLL is locked LOCK read-write [8:8] Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. BYPASS read-write [5:0] Divides the PLL input reference clock.\n Behaviour is undefined for div=0.\n PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. REFDIV CS 0x00000001 0x0004 Controls the PLL power modes. read-write [5:5] PLL VCO powerdown\n To save power set high when PLL output not required or bypass=1. VCOPD read-write [3:3] PLL post divider powerdown\n To save power set high when PLL output not required or bypass=1. POSTDIVPD read-write [2:2] PLL DSM powerdown\n Nothing is achieved by setting this low. DSMPD read-write [0:0] PLL powerdown\n To save power set high when PLL output not required. PD PWR 0x0000002d 0x0008 Feedback divisor\n (note: this PLL does not support fractional division) read-write [11:0] see ctrl reg description for constraints FBDIV_INT FBDIV_INT 0x00000000 0x000c Controls the PLL post dividers for the primary output\n (note: this PLL does not have a secondary output)\n the primary output is driven from VCO divided by postdiv1*postdiv2 read-write [18:16] divide by 1-7 POSTDIV1 read-write [14:12] divide by 1-7 POSTDIV2 PRIM 0x00077000 32 1 0x4002c000 PLL_USB 0 0x1000 registers 0x40030000 Register block for busfabric control signals and performance counters BUSCTRL 0x0000 Set the priority of each master for bus arbitration. read-write [12:12] 0 - low priority, 1 - high priority DMA_W read-write [8:8] 0 - low priority, 1 - high priority DMA_R read-write [4:4] 0 - low priority, 1 - high priority PROC1 read-write [0:0] 0 - low priority, 1 - high priority PROC0 BUS_PRIORITY 0x00000000 0x0004 Bus priority acknowledge read-only [0:0] Goes to 1 once all arbiters have registered the new global priority levels.\n Arbiters update their local priority when servicing a new nonsequential access.\n In normal circumstances this will happen almost immediately. BUS_PRIORITY_ACK BUS_PRIORITY_ACK 0x00000000 0x0008 Bus fabric performance counter 0 read-write [23:0] Busfabric saturating performance counter 0\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL0 oneToClear PERFCTR0 PERFCTR0 0x00000000 0x000c Bus fabric performance event select for PERFCTR0 read-write [4:0] Select a performance event for PERFCTR0 PERFSEL0 PERFSEL0 0x0000001f 0x0010 Bus fabric performance counter 1 read-write [23:0] Busfabric saturating performance counter 1\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL1 oneToClear PERFCTR1 PERFCTR1 0x00000000 0x0014 Bus fabric performance event select for PERFCTR1 read-write [4:0] Select a performance event for PERFCTR1 PERFSEL1 PERFSEL1 0x0000001f 0x0018 Bus fabric performance counter 2 read-write [23:0] Busfabric saturating performance counter 2\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL2 oneToClear PERFCTR2 PERFCTR2 0x00000000 0x001c Bus fabric performance event select for PERFCTR2 read-write [4:0] Select a performance event for PERFCTR2 PERFSEL2 PERFSEL2 0x0000001f 0x0020 Bus fabric performance counter 3 read-write [23:0] Busfabric saturating performance counter 3\n Count some event signal from the busfabric arbiters.\n Write any value to clear. Select an event to count using PERFSEL3 oneToClear PERFCTR3 PERFCTR3 0x00000000 0x0024 Bus fabric performance event select for PERFCTR3 read-write [4:0] Select a performance event for PERFCTR3 PERFSEL3 PERFSEL3 0x0000001f 32 1 0 0x1000 registers 0x40034000 UART0_IRQ 20 UART0 0x0000 Data Register, UARTDR read-only [11:11] Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. OE read-only [10:10] Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. BE read-only [9:9] Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. PE read-only [8:8] Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. FE read-write [7:0] Receive (read) data character. Transmit (write) data character. DATA UARTDR 0x00000000 0x0004 Receive Status Register/Error Clear Register, UARTRSR/UARTECR read-write [3:3] Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. oneToClear OE read-write [2:2] Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. oneToClear BE read-write [1:1] Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. oneToClear PE read-write [0:0] Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. oneToClear FE UARTRSR 0x00000000 0x0018 Flag Register, UARTFR read-only [8:8] Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. RI read-only [7:7] Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. TXFE read-only [6:6] Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. RXFF read-only [5:5] Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. TXFF read-only [4:4] Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. RXFE read-only [3:3] UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. BUSY read-only [2:2] Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. DCD read-only [1:1] Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. DSR read-only [0:0] Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. CTS UARTFR 0x00000090 0x0020 IrDA Low-Power Counter Register, UARTILPR read-write [7:0] 8-bit low-power divisor value. These bits are cleared to 0 at reset. ILPDVSR UARTILPR 0x00000000 0x0024 Integer Baud Rate Register, UARTIBRD read-write [15:0] The integer baud rate divisor. These bits are cleared to 0 on reset. BAUD_DIVINT UARTIBRD 0x00000000 0x0028 Fractional Baud Rate Register, UARTFBRD read-write [5:0] The fractional baud rate divisor. These bits are cleared to 0 on reset. BAUD_DIVFRAC UARTFBRD 0x00000000 0x002c Line Control Register, UARTLCR_H read-write [7:7] Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. SPS read-write [6:5] Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. WLEN read-write [4:4] Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). FEN read-write [3:3] Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. STP2 read-write [2:2] Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. EPS read-write [1:1] Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. PEN read-write [0:0] Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. BRK UARTLCR_H 0x00000000 0x0030 Control Register, UARTCR read-write [15:15] CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. CTSEN read-write [14:14] RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. RTSEN read-write [13:13] This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). OUT2 read-write [12:12] This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). OUT1 read-write [11:11] Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. RTS read-write [10:10] Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. DTR read-write [9:9] Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. RXE read-write [8:8] Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. TXE read-write [7:7] Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. LBE read-write [2:2] SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. SIRLP read-write [1:1] SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. SIREN read-write [0:0] UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. UARTEN UARTCR 0x00000300 0x0034 Interrupt FIFO Level Select Register, UARTIFLS read-write [5:3] Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. RXIFLSEL read-write [2:0] Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. TXIFLSEL UARTIFLS 0x00000012 0x0038 Interrupt Mask Set/Clear Register, UARTIMSC read-write [10:10] Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. OEIM read-write [9:9] Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. BEIM read-write [8:8] Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. PEIM read-write [7:7] Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. FEIM read-write [6:6] Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. RTIM read-write [5:5] Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. TXIM read-write [4:4] Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. RXIM read-write [3:3] nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. DSRMIM read-write [2:2] nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. DCDMIM read-write [1:1] nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. CTSMIM read-write [0:0] nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. RIMIM UARTIMSC 0x00000000 0x003c Raw Interrupt Status Register, UARTRIS read-only [10:10] Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. OERIS read-only [9:9] Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. BERIS read-only [8:8] Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. PERIS read-only [7:7] Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. FERIS read-only [6:6] Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a RTRIS read-only [5:5] Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. TXRIS read-only [4:4] Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. RXRIS read-only [3:3] nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. DSRRMIS read-only [2:2] nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. DCDRMIS read-only [1:1] nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. CTSRMIS read-only [0:0] nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. RIRMIS UARTRIS 0x00000000 0x0040 Masked Interrupt Status Register, UARTMIS read-only [10:10] Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. OEMIS read-only [9:9] Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. BEMIS read-only [8:8] Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. PEMIS read-only [7:7] Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. FEMIS read-only [6:6] Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. RTMIS read-only [5:5] Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. TXMIS read-only [4:4] Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. RXMIS read-only [3:3] nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. DSRMMIS read-only [2:2] nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. DCDMMIS read-only [1:1] nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. CTSMMIS read-only [0:0] nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. RIMMIS UARTMIS 0x00000000 0x0044 Interrupt Clear Register, UARTICR read-write [10:10] Overrun error interrupt clear. Clears the UARTOEINTR interrupt. oneToClear OEIC read-write [9:9] Break error interrupt clear. Clears the UARTBEINTR interrupt. oneToClear BEIC read-write [8:8] Parity error interrupt clear. Clears the UARTPEINTR interrupt. oneToClear PEIC read-write [7:7] Framing error interrupt clear. Clears the UARTFEINTR interrupt. oneToClear FEIC read-write [6:6] Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. oneToClear RTIC read-write [5:5] Transmit interrupt clear. Clears the UARTTXINTR interrupt. oneToClear TXIC read-write [4:4] Receive interrupt clear. Clears the UARTRXINTR interrupt. oneToClear RXIC read-write [3:3] nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. oneToClear DSRMIC read-write [2:2] nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. oneToClear DCDMIC read-write [1:1] nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. oneToClear CTSMIC read-write [0:0] nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. oneToClear RIMIC UARTICR 0x00000000 0x0048 DMA Control Register, UARTDMACR read-write [2:2] DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. DMAONERR read-write [1:1] Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. TXDMAE read-write [0:0] Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. RXDMAE UARTDMACR 0x00000000 0x0fe0 UARTPeriphID0 Register read-only [7:0] These bits read back as 0x11 PARTNUMBER0 UARTPERIPHID0 0x00000011 0x0fe4 UARTPeriphID1 Register read-only [7:4] These bits read back as 0x1 DESIGNER0 read-only [3:0] These bits read back as 0x0 PARTNUMBER1 UARTPERIPHID1 0x00000010 0x0fe8 UARTPeriphID2 Register read-only [7:4] This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 REVISION read-only [3:0] These bits read back as 0x4 DESIGNER1 UARTPERIPHID2 0x00000034 0x0fec UARTPeriphID3 Register read-only [7:0] These bits read back as 0x00 CONFIGURATION UARTPERIPHID3 0x00000000 0x0ff0 UARTPCellID0 Register read-only [7:0] These bits read back as 0x0D UARTPCELLID0 UARTPCELLID0 0x0000000d 0x0ff4 UARTPCellID1 Register read-only [7:0] These bits read back as 0xF0 UARTPCELLID1 UARTPCELLID1 0x000000f0 0x0ff8 UARTPCellID2 Register read-only [7:0] These bits read back as 0x05 UARTPCELLID2 UARTPCELLID2 0x00000005 0x0ffc UARTPCellID3 Register read-only [7:0] These bits read back as 0xB1 UARTPCELLID3 UARTPCELLID3 0x000000b1 32 1 0x40038000 UART1_IRQ 21 UART1 0 0x1000 registers 0x4003c000 SPI0_IRQ 18 SPI0 0x0000 Control register 0, SSPCR0 on page 3-4 read-write [15:8] Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. SCR read-write [7:7] SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. SPH read-write [6:6] SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. SPO read-write [5:4] Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. FRF read-write [3:0] Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. DSS SSPCR0 0x00000000 0x0004 Control register 1, SSPCR1 on page 3-5 read-write [3:3] Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. SOD read-write [2:2] Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. MS read-write [1:1] Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. SSE read-write [0:0] Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. LBM SSPCR1 0x00000000 0x0008 Data register, SSPDR on page 3-6 read-write [15:0] Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. DATA SSPDR 0x00000000 0x000c Status register, SSPSR on page 3-7 read-only [4:4] PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. BSY read-only [3:3] Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. RFF read-only [2:2] Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. RNE read-only [1:1] Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. TNF read-only [0:0] Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. TFE SSPSR 0x00000003 0x0010 Clock prescale register, SSPCPSR on page 3-8 read-write [7:0] Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. CPSDVSR SSPCPSR 0x00000000 0x0014 Interrupt mask set or clear register, SSPIMSC on page 3-9 read-write [3:3] Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. TXIM read-write [2:2] Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. RXIM read-write [1:1] Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. RTIM read-write [0:0] Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. RORIM SSPIMSC 0x00000000 0x0018 Raw interrupt status register, SSPRIS on page 3-10 read-only [3:3] Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt TXRIS read-only [2:2] Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt RXRIS read-only [1:1] Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt RTRIS read-only [0:0] Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt RORRIS SSPRIS 0x00000008 0x001c Masked interrupt status register, SSPMIS on page 3-11 read-only [3:3] Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt TXMIS read-only [2:2] Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt RXMIS read-only [1:1] Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt RTMIS read-only [0:0] Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt RORMIS SSPMIS 0x00000000 0x0020 Interrupt clear register, SSPICR on page 3-11 read-write [1:1] Clears the SSPRTINTR interrupt oneToClear RTIC read-write [0:0] Clears the SSPRORINTR interrupt oneToClear RORIC SSPICR 0x00000000 0x0024 DMA control register, SSPDMACR on page 3-12 read-write [1:1] Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. TXDMAE read-write [0:0] Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. RXDMAE SSPDMACR 0x00000000 0x0fe0 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 read-only [7:0] These bits read back as 0x22 PARTNUMBER0 SSPPERIPHID0 0x00000022 0x0fe4 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 read-only [7:4] These bits read back as 0x1 DESIGNER0 read-only [3:0] These bits read back as 0x0 PARTNUMBER1 SSPPERIPHID1 0x00000010 0x0fe8 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 read-only [7:4] These bits return the peripheral revision REVISION read-only [3:0] These bits read back as 0x4 DESIGNER1 SSPPERIPHID2 0x00000034 0x0fec Peripheral identification registers, SSPPeriphID0-3 on page 3-13 read-only [7:0] These bits read back as 0x00 CONFIGURATION SSPPERIPHID3 0x00000000 0x0ff0 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 read-only [7:0] These bits read back as 0x0D SSPPCELLID0 SSPPCELLID0 0x0000000d 0x0ff4 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 read-only [7:0] These bits read back as 0xF0 SSPPCELLID1 SSPPCELLID1 0x000000f0 0x0ff8 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 read-only [7:0] These bits read back as 0x05 SSPPCELLID2 SSPPCELLID2 0x00000005 0x0ffc PrimeCell identification registers, SSPPCellID0-3 on page 3-16 read-only [7:0] These bits read back as 0xB1 SSPPCELLID3 SSPPCELLID3 0x000000b1 32 1 0x40040000 SPI1_IRQ 19 SPI1 0 0x0100 registers 0x40044000 DW_apb_i2c address block I2C0_IRQ 23 I2C0 0x0000 I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. read-only [10:10] Master issues the STOP_DET interrupt irrespective of whether master is active or not STOP_DET_IF_MASTER_ACTIVE read-write [9:9] This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\n\n Reset value: 0x0. Overflow when RX_FIFO is full DISABLED 0 Hold bus when RX_FIFO is full ENABLED 1 RX_FIFO_FULL_HLD_CTRL read-write [8:8] This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0. Default behaviour of TX_EMPTY interrupt DISABLED 0 Controlled generation of TX_EMPTY interrupt ENABLED 1 TX_EMPTY_CTRL read-write [7:7] In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\n\n NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). slave issues STOP_DET intr always DISABLED 0 slave issues STOP_DET intr only if addressed ENABLED 1 STOP_DET_IFADDRESSED read-write [6:6] This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\n\n If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\n\n NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. Slave mode is enabled SLAVE_ENABLED 0 Slave mode is disabled SLAVE_DISABLED 1 IC_SLAVE_DISABLE read-write [5:5] Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n Reset value: ENABLED Master restart disabled DISABLED 0 Master restart enabled ENABLED 1 IC_RESTART_EN read-write [4:4] Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing Master 7Bit addressing mode ADDR_7BITS 0 Master 10Bit addressing mode ADDR_10BITS 1 IC_10BITADDR_MASTER read-write [3:3] When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. Slave 7Bit addressing ADDR_7BITS 0 Slave 10Bit addressing ADDR_10BITS 1 IC_10BITADDR_SLAVE read-write [2:1] These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\n\n This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\n\n 1: standard mode (100 kbit/s)\n\n 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n 3: high speed mode (3.4 Mbit/s)\n\n Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 Standard Speed mode of operation STANDARD 1 Fast or Fast Plus mode of operation FAST 2 High Speed mode of operation HIGH 3 SPEED read-write [0:0] This bit controls whether the DW_apb_i2c master is enabled.\n\n NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. Master mode is disabled DISABLED 0 Master mode is enabled ENABLED 1 MASTER_MODE IC_CON 0x00000065 0x0004 I2C Target Address Register\n\n This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\n\n Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. read-write [11:11] This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 Disables programming of GENERAL_CALL or START_BYTE transmission DISABLED 0 Enables programming of GENERAL_CALL or START_BYTE transmission ENABLED 1 SPECIAL read-write [10:10] If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 GENERAL_CALL byte transmission GENERAL_CALL 0 START byte transmission START_BYTE 1 GC_OR_START read-write [9:0] This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\n\n If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. IC_TAR IC_TAR 0x00000055 0x0008 I2C Slave Address Register read-write [9:0] The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\n\n This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. IC_SAR IC_SAR 0x00000055 0x0010 I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\n\n The size of the register changes as follows:\n\n Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. read-only [11:11] Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\n\n Reset value : 0x0\n\n NOTE: In case of APB_DATA_WIDTH=8,\n\n 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\n\n 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\n\n 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. Sequential data byte received INACTIVE 0 Non sequential data byte received ACTIVE 1 FIRST_DATA_BYTE read-write [10:10] This bit controls whether a RESTART is issued before the byte is sent or received.\n\n 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\n\n Reset value: 0x0 Don't Issue RESTART before this command DISABLE 0 Issue RESTART before this command ENABLE 1 clear RESTART read-write [9:9] This bit controls whether a STOP is issued after the byte is sent or received.\n\n - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 Don't Issue STOP after this command DISABLE 0 Issue STOP after this command ENABLE 1 clear STOP read-write [8:8] This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\n\n When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\n\n When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n Reset value: 0x0 Master Write Command WRITE 0 Master Read Command READ 1 clear CMD read-write [7:0] This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\n\n Reset value: 0x0 DAT IC_DATA_CMD 0x00000000 0x0014 Standard Speed I2C Clock SCL High Count Register read-write [15:0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\n\n NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. IC_SS_SCL_HCNT IC_SS_SCL_HCNT 0x00000028 0x0018 Standard Speed I2C Clock SCL Low Count Register read-write [15:0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\n\n This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. IC_SS_SCL_LCNT IC_SS_SCL_LCNT 0x0000002f 0x001c Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register read-write [15:0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. IC_FS_SCL_HCNT IC_FS_SCL_HCNT 0x00000006 0x0020 Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register read-write [15:0] This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\n\n This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\n\n This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\n\n The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. IC_FS_SCL_LCNT IC_FS_SCL_LCNT 0x0000000d 0x002c I2C Interrupt Status Register\n\n Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. read-only [13:13] See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit.\n\n Reset value: 0x0 R_MASTER_ON_HOLD interrupt is inactive INACTIVE 0 R_MASTER_ON_HOLD interrupt is active ACTIVE 1 R_MASTER_ON_HOLD read-only [12:12] See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n Reset value: 0x0 R_RESTART_DET interrupt is inactive INACTIVE 0 R_RESTART_DET interrupt is active ACTIVE 1 R_RESTART_DET read-only [11:11] See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n Reset value: 0x0 R_GEN_CALL interrupt is inactive INACTIVE 0 R_GEN_CALL interrupt is active ACTIVE 1 R_GEN_CALL read-only [10:10] See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n Reset value: 0x0 R_START_DET interrupt is inactive INACTIVE 0 R_START_DET interrupt is active ACTIVE 1 R_START_DET read-only [9:9] See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n Reset value: 0x0 R_STOP_DET interrupt is inactive INACTIVE 0 R_STOP_DET interrupt is active ACTIVE 1 R_STOP_DET read-only [8:8] See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n Reset value: 0x0 R_ACTIVITY interrupt is inactive INACTIVE 0 R_ACTIVITY interrupt is active ACTIVE 1 R_ACTIVITY read-only [7:7] See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n Reset value: 0x0 R_RX_DONE interrupt is inactive INACTIVE 0 R_RX_DONE interrupt is active ACTIVE 1 R_RX_DONE read-only [6:6] See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n Reset value: 0x0 R_TX_ABRT interrupt is inactive INACTIVE 0 R_TX_ABRT interrupt is active ACTIVE 1 R_TX_ABRT read-only [5:5] See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n Reset value: 0x0 R_RD_REQ interrupt is inactive INACTIVE 0 R_RD_REQ interrupt is active ACTIVE 1 R_RD_REQ read-only [4:4] See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n Reset value: 0x0 R_TX_EMPTY interrupt is inactive INACTIVE 0 R_TX_EMPTY interrupt is active ACTIVE 1 R_TX_EMPTY read-only [3:3] See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n Reset value: 0x0 R_TX_OVER interrupt is inactive INACTIVE 0 R_TX_OVER interrupt is active ACTIVE 1 R_TX_OVER read-only [2:2] See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n Reset value: 0x0 R_RX_FULL interrupt is inactive INACTIVE 0 R_RX_FULL interrupt is active ACTIVE 1 R_RX_FULL read-only [1:1] See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n Reset value: 0x0 R_RX_OVER interrupt is inactive INACTIVE 0 R_RX_OVER interrupt is active ACTIVE 1 R_RX_OVER read-only [0:0] See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n Reset value: 0x0 RX_UNDER interrupt is inactive INACTIVE 0 RX_UNDER interrupt is active ACTIVE 1 R_RX_UNDER IC_INTR_STAT 0x00000000 0x0030 I2C Interrupt Mask Register.\n\n These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. read-only [13:13] This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 MASTER_ON_HOLD interrupt is masked ENABLED 0 MASTER_ON_HOLD interrupt is unmasked DISABLED 1 M_MASTER_ON_HOLD_READ_ONLY read-write [12:12] This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 RESTART_DET interrupt is masked ENABLED 0 RESTART_DET interrupt is unmasked DISABLED 1 M_RESTART_DET read-write [11:11] This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 GEN_CALL interrupt is masked ENABLED 0 GEN_CALL interrupt is unmasked DISABLED 1 M_GEN_CALL read-write [10:10] This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 START_DET interrupt is masked ENABLED 0 START_DET interrupt is unmasked DISABLED 1 M_START_DET read-write [9:9] This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 STOP_DET interrupt is masked ENABLED 0 STOP_DET interrupt is unmasked DISABLED 1 M_STOP_DET read-write [8:8] This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x0 ACTIVITY interrupt is masked ENABLED 0 ACTIVITY interrupt is unmasked DISABLED 1 M_ACTIVITY read-write [7:7] This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RX_DONE interrupt is masked ENABLED 0 RX_DONE interrupt is unmasked DISABLED 1 M_RX_DONE read-write [6:6] This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 TX_ABORT interrupt is masked ENABLED 0 TX_ABORT interrupt is unmasked DISABLED 1 M_TX_ABRT read-write [5:5] This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RD_REQ interrupt is masked ENABLED 0 RD_REQ interrupt is unmasked DISABLED 1 M_RD_REQ read-write [4:4] This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 TX_EMPTY interrupt is masked ENABLED 0 TX_EMPTY interrupt is unmasked DISABLED 1 M_TX_EMPTY read-write [3:3] This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 TX_OVER interrupt is masked ENABLED 0 TX_OVER interrupt is unmasked DISABLED 1 M_TX_OVER read-write [2:2] This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RX_FULL interrupt is masked ENABLED 0 RX_FULL interrupt is unmasked DISABLED 1 M_RX_FULL read-write [1:1] This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RX_OVER interrupt is masked ENABLED 0 RX_OVER interrupt is unmasked DISABLED 1 M_RX_OVER read-write [0:0] This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n Reset value: 0x1 RX_UNDER interrupt is masked ENABLED 0 RX_UNDER interrupt is unmasked DISABLED 1 M_RX_UNDER IC_INTR_MASK 0x000008ff 0x0034 I2C Raw Interrupt Status Register\n\n Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. read-only [13:13] Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.\n\n Reset value: 0x0 MASTER_ON_HOLD interrupt is inactive INACTIVE 0 MASTER_ON_HOLD interrupt is active ACTIVE 1 MASTER_ON_HOLD read-only [12:12] Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\n\n Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\n\n Reset value: 0x0 RESTART_DET interrupt is inactive INACTIVE 0 RESTART_DET interrupt is active ACTIVE 1 RESTART_DET read-only [11:11] Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\n\n Reset value: 0x0 GEN_CALL interrupt is inactive INACTIVE 0 GEN_CALL interrupt is active ACTIVE 1 GEN_CALL read-only [10:10] Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n Reset value: 0x0 START_DET interrupt is inactive INACTIVE 0 START_DET interrupt is active ACTIVE 1 START_DET read-only [9:9] Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 STOP_DET interrupt is inactive INACTIVE 0 STOP_DET interrupt is active ACTIVE 1 STOP_DET read-only [8:8] This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\n\n Reset value: 0x0 RAW_INTR_ACTIVITY interrupt is inactive INACTIVE 0 RAW_INTR_ACTIVITY interrupt is active ACTIVE 1 ACTIVITY read-only [7:7] When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\n\n Reset value: 0x0 RX_DONE interrupt is inactive INACTIVE 0 RX_DONE interrupt is active ACTIVE 1 RX_DONE read-only [6:6] This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\n\n Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\n\n Reset value: 0x0 TX_ABRT interrupt is inactive INACTIVE 0 TX_ABRT interrupt is active ACTIVE 1 TX_ABRT read-only [5:5] This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\n\n Reset value: 0x0 RD_REQ interrupt is inactive INACTIVE 0 RD_REQ interrupt is active ACTIVE 1 RD_REQ read-only [4:4] The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\n\n Reset value: 0x0. TX_EMPTY interrupt is inactive INACTIVE 0 TX_EMPTY interrupt is active ACTIVE 1 TX_EMPTY read-only [3:3] Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Reset value: 0x0 TX_OVER interrupt is inactive INACTIVE 0 TX_OVER interrupt is active ACTIVE 1 TX_OVER read-only [2:2] Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\n\n Reset value: 0x0 RX_FULL interrupt is inactive INACTIVE 0 RX_FULL interrupt is active ACTIVE 1 RX_FULL read-only [1:1] Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\n\n Reset value: 0x0 RX_OVER interrupt is inactive INACTIVE 0 RX_OVER interrupt is active ACTIVE 1 RX_OVER read-only [0:0] Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n Reset value: 0x0 RX_UNDER interrupt is inactive INACTIVE 0 RX_UNDER interrupt is active ACTIVE 1 RX_UNDER IC_RAW_INTR_STAT 0x00000000 0x0038 I2C Receive FIFO Threshold Register read-write [7:0] Receive FIFO Threshold Level.\n\n Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. RX_TL IC_RX_TL 0x00000000 0x003c I2C Transmit FIFO Threshold Register read-write [7:0] Transmit FIFO Threshold Level.\n\n Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. TX_TL IC_TX_TL 0x00000000 0x0040 Clear Combined and Individual Interrupt Register read-only [0:0] Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n Reset value: 0x0 CLR_INTR IC_CLR_INTR 0x00000000 0x0044 Clear RX_UNDER Interrupt Register read-only [0:0] Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RX_UNDER IC_CLR_RX_UNDER 0x00000000 0x0048 Clear RX_OVER Interrupt Register read-only [0:0] Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RX_OVER IC_CLR_RX_OVER 0x00000000 0x004c Clear TX_OVER Interrupt Register read-only [0:0] Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_TX_OVER IC_CLR_TX_OVER 0x00000000 0x0050 Clear RD_REQ Interrupt Register read-only [0:0] Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RD_REQ IC_CLR_RD_REQ 0x00000000 0x0054 Clear TX_ABRT Interrupt Register read-only [0:0] Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n Reset value: 0x0 CLR_TX_ABRT IC_CLR_TX_ABRT 0x00000000 0x0058 Clear RX_DONE Interrupt Register read-only [0:0] Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RX_DONE IC_CLR_RX_DONE 0x00000000 0x005c Clear ACTIVITY Interrupt Register read-only [0:0] Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_ACTIVITY IC_CLR_ACTIVITY 0x00000000 0x0060 Clear STOP_DET Interrupt Register read-only [0:0] Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_STOP_DET IC_CLR_STOP_DET 0x00000000 0x0064 Clear START_DET Interrupt Register read-only [0:0] Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_START_DET IC_CLR_START_DET 0x00000000 0x0068 Clear GEN_CALL Interrupt Register read-only [0:0] Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_GEN_CALL IC_CLR_GEN_CALL 0x00000000 0x006c I2C Enable Register read-write [2:2] In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT Tx Command execution not blocked NOT_BLOCKED 0 Tx Command execution blocked BLOCKED 1 TX_CMD_BLOCK read-write [1:1] When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\n\n For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\n\n Reset value: 0x0 ABORT operation not in progress DISABLE 0 ABORT operation in progress ENABLED 1 ABORT read-write [0:0] Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\n\n When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\n\n In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\n\n Reset value: 0x0 I2C is disabled DISABLED 0 I2C is enabled ENABLED 1 ENABLE IC_ENABLE 0x00000000 0x0070 I2C Status Register\n\n This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\n\n When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 read-only [6:6] Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 Slave is idle IDLE 0 Slave not idle ACTIVE 1 SLV_ACTIVITY read-only [5:5] Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n Reset value: 0x0 Master is idle IDLE 0 Master not idle ACTIVE 1 MST_ACTIVITY read-only [4:4] Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 Rx FIFO not full NOT_FULL 0 Rx FIFO is full FULL 1 RFF read-only [3:3] Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 Rx FIFO is empty EMPTY 0 Rx FIFO not empty NOT_EMPTY 1 RFNE read-only [2:2] Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 Tx FIFO not empty NON_EMPTY 0 Tx FIFO is empty EMPTY 1 TFE read-only [1:1] Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 Tx FIFO is full FULL 0 Tx FIFO not full NOT_FULL 1 TFNF read-only [0:0] I2C Activity Status. Reset value: 0x0 I2C is idle INACTIVE 0 I2C is active ACTIVE 1 ACTIVITY IC_STATUS 0x00000006 0x0074 I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. read-only [4:0] Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\n\n Reset value: 0x0 TXFLR IC_TXFLR 0x00000000 0x0078 I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. read-only [4:0] Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\n\n Reset value: 0x0 RXFLR IC_RXFLR 0x00000000 0x007c I2C SDA Hold Time Length Register\n\n The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n Writes to this register succeed only when IC_ENABLE[0]=0.\n\n The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode one cycle in master mode, seven cycles in slave mode for the value to be implemented.\n\n The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. read-write [23:16] Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\n\n Reset value: IC_DEFAULT_SDA_HOLD[23:16]. IC_SDA_RX_HOLD read-write [15:0] Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\n\n Reset value: IC_DEFAULT_SDA_HOLD[15:0]. IC_SDA_TX_HOLD IC_SDA_HOLD 0x00000001 0x0080 I2C Transmit Abort Source Register\n\n This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\n\n Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. read-only [31:23] This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter TX_FLUSH_CNT read-only [16:16] This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter Transfer abort detected by master- scenario not present ABRT_USER_ABRT_VOID 0 Transfer abort detected by master ABRT_USER_ABRT_GENERATED 1 ABRT_USER_ABRT read-only [15:15] 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter Slave trying to transmit to remote master in read mode- scenario not present ABRT_SLVRD_INTX_VOID 0 Slave trying to transmit to remote master in read mode ABRT_SLVRD_INTX_GENERATED 1 ABRT_SLVRD_INTX read-only [14:14] This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter Slave lost arbitration to remote master- scenario not present ABRT_SLV_ARBLOST_VOID 0 Slave lost arbitration to remote master ABRT_SLV_ARBLOST_GENERATED 1 ABRT_SLV_ARBLOST read-only [13:13] This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Slave-Transmitter Slave flushes existing data in TX-FIFO upon getting read command- scenario not present ABRT_SLVFLUSH_TXFIFO_VOID 0 Slave flushes existing data in TX-FIFO upon getting read command ABRT_SLVFLUSH_TXFIFO_GENERATED 1 ABRT_SLVFLUSH_TXFIFO read-only [12:12] This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter Master or Slave-Transmitter lost arbitration- scenario not present ABRT_LOST_VOID 0 Master or Slave-Transmitter lost arbitration ABRT_LOST_GENERATED 1 ARB_LOST read-only [11:11] This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver User initiating master operation when MASTER disabled- scenario not present ABRT_MASTER_DIS_VOID 0 User initiating master operation when MASTER disabled ABRT_MASTER_DIS_GENERATED 1 ABRT_MASTER_DIS read-only [10:10] This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Receiver Master not trying to read in 10Bit addressing mode when RESTART disabled ABRT_10B_RD_VOID 0 Master trying to read in 10Bit addressing mode when RESTART disabled ABRT_10B_RD_GENERATED 1 ABRT_10B_RD_NORSTRT read-only [9:9] To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master User trying to send START byte when RESTART disabled- scenario not present ABRT_SBYTE_NORSTRT_VOID 0 User trying to send START byte when RESTART disabled ABRT_SBYTE_NORSTRT_GENERATED 1 ABRT_SBYTE_NORSTRT read-only [8:8] This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver User trying to switch Master to HS mode when RESTART disabled- scenario not present ABRT_HS_NORSTRT_VOID 0 User trying to switch Master to HS mode when RESTART disabled ABRT_HS_NORSTRT_GENERATED 1 ABRT_HS_NORSTRT read-only [7:7] This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master ACK detected for START byte- scenario not present ABRT_SBYTE_ACKDET_VOID 0 ACK detected for START byte ABRT_SBYTE_ACKDET_GENERATED 1 ABRT_SBYTE_ACKDET read-only [6:6] This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master HS Master code ACKed in HS Mode- scenario not present ABRT_HS_ACK_VOID 0 HS Master code ACKed in HS Mode ABRT_HS_ACK_GENERATED 1 ABRT_HS_ACKDET read-only [5:5] This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter GCALL is followed by read from bus-scenario not present ABRT_GCALL_READ_VOID 0 GCALL is followed by read from bus ABRT_GCALL_READ_GENERATED 1 ABRT_GCALL_READ read-only [4:4] This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter GCALL not ACKed by any slave-scenario not present ABRT_GCALL_NOACK_VOID 0 GCALL not ACKed by any slave ABRT_GCALL_NOACK_GENERATED 1 ABRT_GCALL_NOACK read-only [3:3] This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter Transmitted data non-ACKed by addressed slave-scenario not present ABRT_TXDATA_NOACK_VOID 0 Transmitted data not ACKed by addressed slave ABRT_TXDATA_NOACK_GENERATED 1 ABRT_TXDATA_NOACK read-only [2:2] This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver This abort is not generated INACTIVE 0 Byte 2 of 10Bit Address not ACKed by any slave ACTIVE 1 ABRT_10ADDR2_NOACK read-only [1:1] This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver This abort is not generated INACTIVE 0 Byte 1 of 10Bit Address not ACKed by any slave ACTIVE 1 ABRT_10ADDR1_NOACK read-only [0:0] This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\n\n Reset value: 0x0\n\n Role of DW_apb_i2c: Master-Transmitter or Master-Receiver This abort is not generated INACTIVE 0 This abort is generated because of NOACK for 7-bit address ACTIVE 1 ABRT_7B_ADDR_NOACK IC_TX_ABRT_SOURCE 0x00000000 0x0084 Generate Slave Data NACK Register\n\n The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\n\n A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. read-write [0:0] Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\n\n When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 Slave receiver generates NACK normally DISABLED 0 Slave receiver generates NACK upon data reception only ENABLED 1 NACK IC_SLV_DATA_NACK_ONLY 0x00000000 0x0088 DMA Control Register\n\n The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. read-write [1:1] Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 transmit FIFO DMA channel disabled DISABLED 0 Transmit FIFO DMA channel enabled ENABLED 1 TDMAE read-write [0:0] Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 Receive FIFO DMA channel disabled DISABLED 0 Receive FIFO DMA channel enabled ENABLED 1 RDMAE IC_DMA_CR 0x00000000 0x008c DMA Transmit Data Level Register read-write [3:0] Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n Reset value: 0x0 DMATDL IC_DMA_TDLR 0x00000000 0x0090 I2C Receive Data Level Register read-write [3:0] Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\n\n Reset value: 0x0 DMARDL IC_DMA_RDLR 0x00000000 0x0094 I2C SDA Setup Register\n\n This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\n\n Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. read-write [7:0] SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. SDA_SETUP IC_SDA_SETUP 0x00000064 0x0098 I2C ACK General Call Register\n\n The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\n\n This register is applicable only when the DW_apb_i2c is in slave mode. read-write [0:0] ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). Generate NACK for a General Call DISABLED 0 Generate ACK for a General Call ENABLED 1 ACK_GEN_CALL IC_ACK_GENERAL_CALL 0x00000001 0x009c I2C Enable Status Register\n\n The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\n\n If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\n\n If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\n\n Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. read-only [2:2] Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\n\n Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\n\n When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\n\n Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n Reset value: 0x0 Slave RX Data is not lost INACTIVE 0 Slave RX Data is lost ACTIVE 1 SLV_RX_DATA_LOST read-only [1:1] Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\n\n (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\n\n OR,\n\n (b) address and data bytes of the Slave-Receiver operation from a remote master.\n\n When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\n\n Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\n\n When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\n\n Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n Reset value: 0x0 Slave is disabled when it is idle INACTIVE 0 Slave is disabled when it is active ACTIVE 1 SLV_DISABLED_WHILE_BUSY read-only [0:0] ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n Reset value: 0x0 I2C disabled DISABLED 0 I2C enabled ENABLED 1 IC_EN IC_ENABLE_STATUS 0x00000000 0x00a0 I2C SS, FS or FM+ spike suppression limit\n\n This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. read-write [7:0] This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. IC_FS_SPKLEN IC_FS_SPKLEN 0x00000007 0x00a8 Clear RESTART_DET Interrupt Register read-only [0:0] Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\n\n Reset value: 0x0 CLR_RESTART_DET IC_CLR_RESTART_DET 0x00000000 0x00f4 Component Parameter Register 1\n\n Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters read-only [23:16] TX Buffer Depth = 16 TX_BUFFER_DEPTH read-only [15:8] RX Buffer Depth = 16 RX_BUFFER_DEPTH read-only [7:7] Encoded parameters not visible ADD_ENCODED_PARAMS read-only [6:6] DMA handshaking signals are enabled HAS_DMA read-only [5:5] COMBINED Interrupt outputs INTR_IO read-only [4:4] Programmable count values for each mode. HC_COUNT_VALUES read-only [3:2] MAX SPEED MODE = FAST MODE MAX_SPEED_MODE read-only [1:0] APB data bus width is 32 bits APB_DATA_WIDTH IC_COMP_PARAM_1 0x00000000 0x00f8 I2C Component Version Register read-only [31:0] IC_COMP_VERSION IC_COMP_VERSION 0x3230312a 0x00fc I2C Component Type Register read-only [31:0] Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. IC_COMP_TYPE IC_COMP_TYPE 0x44570140 32 1 0x40048000 I2C1_IRQ 24 I2C1 0 0x1000 registers 0x4004c000 Control and data interface to SAR ADC ADC_IRQ_FIFO 22 ADC 0x0000 ADC Control and Status read-write [20:16] Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\n The first channel to be sampled will be the one currently indicated by AINSEL.\n AINSEL will be updated after each conversion with the newly-selected channel. RROBIN read-write [14:12] Select analog mux input. Updated automatically in round-robin mode. AINSEL read-write [10:10] Some past ADC conversion encountered an error. Write 1 to clear. oneToClear ERR_STICKY read-only [9:9] The most recent ADC conversion encountered an error; result is undefined or noisy. ERR read-only [8:8] 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\n 0 whilst conversion in progress. READY read-write [3:3] Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. START_MANY read-write [2:2] Start a single conversion. Self-clearing. Ignored if start_many is asserted. clear START_ONCE read-write [1:1] Power on temperature sensor. 1 - enabled. 0 - disabled. TS_EN read-write [0:0] Power on ADC and enable its clock.\n 1 - enabled. 0 - disabled. EN CS 0x00000000 0x0004 Result of most recent ADC conversion read-only [11:0] RESULT RESULT 0x00000000 0x0008 FIFO control and status read-write [27:24] DREQ/IRQ asserted when level >= threshold THRESH read-only [19:16] The number of conversion results currently waiting in the FIFO LEVEL read-write [11:11] 1 if the FIFO has been overflowed. Write 1 to clear. oneToClear OVER read-write [10:10] 1 if the FIFO has been underflowed. Write 1 to clear. oneToClear UNDER read-only [9:9] FULL read-only [8:8] EMPTY read-write [3:3] If 1: assert DMA requests when FIFO contains data DREQ_EN read-write [2:2] If 1: conversion error bit appears in the FIFO alongside the result ERR read-write [1:1] If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. SHIFT read-write [0:0] If 1: write result to the FIFO after each conversion. EN FCS 0x00000000 0x000c Conversion result FIFO read-only [15:15] 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. ERR read-only [11:0] VAL FIFO 0x00000000 0x0010 Clock divider. If non-zero, CS_START_MANY will start conversions\n at regular intervals rather than back-to-back.\n The divider is reset when either of these fields are written.\n Total period is 1 + INT + FRAC / 256 read-write [23:8] Integer part of clock divisor. INT read-write [7:0] Fractional part of clock divisor. First-order delta-sigma. FRAC DIV 0x00000000 0x0014 Raw Interrupts read-only [0:0] Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field. FIFO INTR 0x00000000 0x0018 Interrupt Enable read-write [0:0] Triggered when the sample FIFO reaches a certain level.\n This level can be programmed via the FCS_THRESH field. FIFO INTE 0x00000000 0x001c Interrupt Force