Raspberry Pi RP2040 RP 0.1 Dual-core Arm Cortex-M0+ processor, flexible clock running up to 133 MHz 264KB on-chip SRAM 2 x UART, 2 x SPI controllers, 2 x I2C controllers, 16 x PWM channels 1 x USB 1.1 controller and PHY, with host and device support 8 x Programmable I/O (PIO) state machines for custom peripheral support Supported input power 1.8-5.5V DC Operating temperature -20C to +85C Drag-and-drop programming using mass storage over USB Low-power sleep and dormant modes Accurate on-chip clock Temperature sensor Accelerated integer and floating-point libraries on-chip 32 32 0xffffffff 0x00000000 read-write Copyright (c) 2024 Raspberry Pi Ltd. SPDX-License-Identifier: BSD-3-Clause CM0PLUS r0p1 little true false 1 2 false 26 8 RESETS 0x4000c000 0 12 registers RESET 0x00000000 Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted. 0x01ffffff USBCTRL [24:24] read-write UART1 [23:23] read-write UART0 [22:22] read-write TIMER [21:21] read-write TBMAN [20:20] read-write SYSINFO [19:19] read-write SYSCFG [18:18] read-write SPI1 [17:17] read-write SPI0 [16:16] read-write RTC [15:15] read-write PWM [14:14] read-write PLL_USB [13:13] read-write PLL_SYS [12:12] read-write PIO1 [11:11] read-write PIO0 [10:10] read-write PADS_QSPI [9:9] read-write PADS_BANK0 [8:8] read-write JTAG [7:7] read-write IO_QSPI [6:6] read-write IO_BANK0 [5:5] read-write I2C1 [4:4] read-write I2C0 [3:3] read-write DMA [2:2] read-write BUSCTRL [1:1] read-write ADC [0:0] read-write WDSEL 0x00000004 Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires. 0x00000000 USBCTRL [24:24] read-write UART1 [23:23] read-write UART0 [22:22] read-write TIMER [21:21] read-write TBMAN [20:20] read-write SYSINFO [19:19] read-write SYSCFG [18:18] read-write SPI1 [17:17] read-write SPI0 [16:16] read-write RTC [15:15] read-write PWM [14:14] read-write PLL_USB [13:13] read-write PLL_SYS [12:12] read-write PIO1 [11:11] read-write PIO0 [10:10] read-write PADS_QSPI [9:9] read-write PADS_BANK0 [8:8] read-write JTAG [7:7] read-write IO_QSPI [6:6] read-write IO_BANK0 [5:5] read-write I2C1 [4:4] read-write I2C0 [3:3] read-write DMA [2:2] read-write BUSCTRL [1:1] read-write ADC [0:0] read-write RESET_DONE 0x00000008 Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed. 0x00000000 USBCTRL [24:24] read-only UART1 [23:23] read-only UART0 [22:22] read-only TIMER [21:21] read-only TBMAN [20:20] read-only SYSINFO [19:19] read-only SYSCFG [18:18] read-only SPI1 [17:17] read-only SPI0 [16:16] read-only RTC [15:15] read-only PWM [14:14] read-only PLL_USB [13:13] read-only PLL_SYS [12:12] read-only PIO1 [11:11] read-only PIO0 [10:10] read-only PADS_QSPI [9:9] read-only PADS_BANK0 [8:8] read-only JTAG [7:7] read-only IO_QSPI [6:6] read-only IO_BANK0 [5:5] read-only I2C1 [4:4] read-only I2C0 [3:3] read-only DMA [2:2] read-only BUSCTRL [1:1] read-only ADC [0:0] read-only PSM 0x40010000 0 16 registers FRCE_ON 0x00000000 Force block out of reset (i.e. power it on) 0x00000000 PROC1 [16:16] read-write PROC0 [15:15] read-write SIO [14:14] read-write VREG_AND_CHIP_RESET [13:13] read-write XIP [12:12] read-write SRAM5 [11:11] read-write SRAM4 [10:10] read-write SRAM3 [9:9] read-write SRAM2 [8:8] read-write SRAM1 [7:7] read-write SRAM0 [6:6] read-write ROM [5:5] read-write BUSFABRIC [4:4] read-write RESETS [3:3] read-write CLOCKS [2:2] read-write XOSC [1:1] read-write ROSC [0:0] read-write FRCE_OFF 0x00000004 Force into reset (i.e. power it off) 0x00000000 PROC1 [16:16] read-write PROC0 [15:15] read-write SIO [14:14] read-write VREG_AND_CHIP_RESET [13:13] read-write XIP [12:12] read-write SRAM5 [11:11] read-write SRAM4 [10:10] read-write SRAM3 [9:9] read-write SRAM2 [8:8] read-write SRAM1 [7:7] read-write SRAM0 [6:6] read-write ROM [5:5] read-write BUSFABRIC [4:4] read-write RESETS [3:3] read-write CLOCKS [2:2] read-write XOSC [1:1] read-write ROSC [0:0] read-write WDSEL 0x00000008 Set to 1 if this peripheral should be reset when the watchdog fires. 0x00000000 PROC1 [16:16] read-write PROC0 [15:15] read-write SIO [14:14] read-write VREG_AND_CHIP_RESET [13:13] read-write XIP [12:12] read-write SRAM5 [11:11] read-write SRAM4 [10:10] read-write SRAM3 [9:9] read-write SRAM2 [8:8] read-write SRAM1 [7:7] read-write SRAM0 [6:6] read-write ROM [5:5] read-write BUSFABRIC [4:4] read-write RESETS [3:3] read-write CLOCKS [2:2] read-write XOSC [1:1] read-write ROSC [0:0] read-write DONE 0x0000000c Indicates the peripheral's registers are ready to access. 0x00000000 PROC1 [16:16] read-only PROC0 [15:15] read-only SIO [14:14] read-only VREG_AND_CHIP_RESET [13:13] read-only XIP [12:12] read-only SRAM5 [11:11] read-only SRAM4 [10:10] read-only SRAM3 [9:9] read-only SRAM2 [8:8] read-only SRAM1 [7:7] read-only SRAM0 [6:6] read-only ROM [5:5] read-only BUSFABRIC [4:4] read-only RESETS [3:3] read-only CLOCKS [2:2] read-only XOSC [1:1] read-only ROSC [0:0] read-only CLOCKS 0x40008000 0 200 registers CLOCKS_IRQ 17 CLK_GPOUT0_CTRL 0x00000000 Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write DC50 Enables duty cycle correction for odd divisors [12:12] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [8:5] read-write clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 CLK_GPOUT0_DIV 0x00000004 Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [31:8] read-write FRAC Fractional component of the divisor [7:0] read-write CLK_GPOUT0_SELECTED 0x00000008 Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_GPOUT0_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [31:0] read-only CLK_GPOUT1_CTRL 0x0000000c Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write DC50 Enables duty cycle correction for odd divisors [12:12] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [8:5] read-write clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 CLK_GPOUT1_DIV 0x00000010 Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [31:8] read-write FRAC Fractional component of the divisor [7:0] read-write CLK_GPOUT1_SELECTED 0x00000014 Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_GPOUT1_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [31:0] read-only CLK_GPOUT2_CTRL 0x00000018 Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write DC50 Enables duty cycle correction for odd divisors [12:12] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [8:5] read-write clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc_ph 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 CLK_GPOUT2_DIV 0x0000001c Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [31:8] read-write FRAC Fractional component of the divisor [7:0] read-write CLK_GPOUT2_SELECTED 0x00000020 Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_GPOUT2_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [31:0] read-only CLK_GPOUT3_CTRL 0x00000024 Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write DC50 Enables duty cycle correction for odd divisors [12:12] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [8:5] read-write clksrc_pll_sys 0 clksrc_gpin0 1 clksrc_gpin1 2 clksrc_pll_usb 3 rosc_clksrc_ph 4 xosc_clksrc 5 clk_sys 6 clk_usb 7 clk_adc 8 clk_rtc 9 clk_ref 10 CLK_GPOUT3_DIV 0x00000028 Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [31:8] read-write FRAC Fractional component of the divisor [7:0] read-write CLK_GPOUT3_SELECTED 0x0000002c Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_GPOUT3_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [31:0] read-only CLK_REF_CTRL 0x00000030 Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 AUXSRC Selects the auxiliary clock source, will glitch when switching [6:5] read-write clksrc_pll_usb 0 clksrc_gpin0 1 clksrc_gpin1 2 SRC Selects the clock source glitchlessly, can be changed on-the-fly [1:0] read-write rosc_clksrc_ph 0 clksrc_clk_ref_aux 1 xosc_clksrc 2 CLK_REF_DIV 0x00000034 Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [9:8] read-write CLK_REF_SELECTED 0x00000038 Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_REF_SELECTED The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. [31:0] read-only CLK_SYS_CTRL 0x0000003c Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clksrc_pll_sys 0 clksrc_pll_usb 1 rosc_clksrc 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 SRC Selects the clock source glitchlessly, can be changed on-the-fly [0:0] read-write clk_ref 0 clksrc_clk_sys_aux 1 CLK_SYS_DIV 0x00000040 Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [31:8] read-write FRAC Fractional component of the divisor [7:0] read-write CLK_SYS_SELECTED 0x00000044 Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_SYS_SELECTED The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s. [31:0] read-only CLK_PERI_CTRL 0x00000048 Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clk_sys 0 clksrc_pll_sys 1 clksrc_pll_usb 2 rosc_clksrc_ph 3 xosc_clksrc 4 clksrc_gpin0 5 clksrc_gpin1 6 CLK_PERI_DIV 0x0000004c Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [31:8] read-write FRAC Fractional component of the divisor [7:0] read-write CLK_PERI_SELECTED 0x00000050 Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_PERI_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [31:0] read-only CLK_USB_CTRL 0x00000054 Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 CLK_USB_DIV 0x00000058 Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [9:8] read-write CLK_USB_SELECTED 0x0000005c Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_USB_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [31:0] read-only CLK_ADC_CTRL 0x00000060 Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 CLK_ADC_DIV 0x00000064 Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [9:8] read-write CLK_ADC_SELECTED 0x00000068 Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_ADC_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [31:0] read-only CLK_RTC_CTRL 0x0000006c Clock control, can be changed on-the-fly (except for auxsrc) 0x00000000 NUDGE An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time [20:20] read-write PHASE This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect [17:16] read-write ENABLE Starts and stops the clock generator cleanly [11:11] read-write KILL Asynchronously kills the clock generator [10:10] read-write AUXSRC Selects the auxiliary clock source, will glitch when switching [7:5] read-write clksrc_pll_usb 0 clksrc_pll_sys 1 rosc_clksrc_ph 2 xosc_clksrc 3 clksrc_gpin0 4 clksrc_gpin1 5 CLK_RTC_DIV 0x00000070 Clock divisor, can be changed on-the-fly 0x00000100 INT Integer component of the divisor, 0 -> divide by 2^16 [31:8] read-write FRAC Fractional component of the divisor [7:0] read-write CLK_RTC_SELECTED 0x00000074 Indicates which SRC is currently selected by the glitchless mux (one-hot). 0x00000001 CLK_RTC_SELECTED This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1. [31:0] read-only CLK_SYS_RESUS_CTRL 0x00000078 0x000000ff CLEAR For clearing the resus after the fault that triggered it has been corrected [16:16] read-write FRCE Force a resus, for test purposes only [12:12] read-write ENABLE Enable resus [8:8] read-write TIMEOUT This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq [7:0] read-write CLK_SYS_RESUS_STATUS 0x0000007c 0x00000000 RESUSSED Clock has been resuscitated, correct the error then send ctrl_clear=1 [0:0] read-only FC0_REF_KHZ 0x00000080 Reference clock frequency in kHz 0x00000000 FC0_REF_KHZ [19:0] read-write FC0_MIN_KHZ 0x00000084 Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags 0x00000000 FC0_MIN_KHZ [24:0] read-write FC0_MAX_KHZ 0x00000088 Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags 0x01ffffff FC0_MAX_KHZ [24:0] read-write FC0_DELAY 0x0000008c Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period 0x00000001 FC0_DELAY [2:0] read-write FC0_INTERVAL 0x00000090 The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us 0x00000008 FC0_INTERVAL [3:0] read-write FC0_SRC 0x00000094 Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count 0x00000000 FC0_SRC [7:0] read-write NULL 0 pll_sys_clksrc_primary 1 pll_usb_clksrc_primary 2 rosc_clksrc 3 rosc_clksrc_ph 4 xosc_clksrc 5 clksrc_gpin0 6 clksrc_gpin1 7 clk_ref 8 clk_sys 9 clk_peri 10 clk_usb 11 clk_adc 12 clk_rtc 13 FC0_STATUS 0x00000098 Frequency counter status 0x00000000 DIED Test clock stopped during test [28:28] read-only FAST Test clock faster than expected, only valid when status_done=1 [24:24] read-only SLOW Test clock slower than expected, only valid when status_done=1 [20:20] read-only FAIL Test failed [16:16] read-only WAITING Waiting for test clock to start [12:12] read-only RUNNING Test running [8:8] read-only DONE Test complete [4:4] read-only PASS Test passed [0:0] read-only FC0_RESULT 0x0000009c Result of frequency measurement, only valid when status_done=1 0x00000000 KHZ [29:5] read-only FRAC [4:0] read-only WAKE_EN0 0x000000a0 enable clock in wake mode 0xffffffff CLK_SYS_SRAM3 [31:31] read-write CLK_SYS_SRAM2 [30:30] read-write CLK_SYS_SRAM1 [29:29] read-write CLK_SYS_SRAM0 [28:28] read-write CLK_SYS_SPI1 [27:27] read-write CLK_PERI_SPI1 [26:26] read-write CLK_SYS_SPI0 [25:25] read-write CLK_PERI_SPI0 [24:24] read-write CLK_SYS_SIO [23:23] read-write CLK_SYS_RTC [22:22] read-write CLK_RTC_RTC [21:21] read-write CLK_SYS_ROSC [20:20] read-write CLK_SYS_ROM [19:19] read-write CLK_SYS_RESETS [18:18] read-write CLK_SYS_PWM [17:17] read-write CLK_SYS_PSM [16:16] read-write CLK_SYS_PLL_USB [15:15] read-write CLK_SYS_PLL_SYS [14:14] read-write CLK_SYS_PIO1 [13:13] read-write CLK_SYS_PIO0 [12:12] read-write CLK_SYS_PADS [11:11] read-write CLK_SYS_VREG_AND_CHIP_RESET [10:10] read-write CLK_SYS_JTAG [9:9] read-write CLK_SYS_IO [8:8] read-write CLK_SYS_I2C1 [7:7] read-write CLK_SYS_I2C0 [6:6] read-write CLK_SYS_DMA [5:5] read-write CLK_SYS_BUSFABRIC [4:4] read-write CLK_SYS_BUSCTRL [3:3] read-write CLK_SYS_ADC [2:2] read-write CLK_ADC_ADC [1:1] read-write CLK_SYS_CLOCKS [0:0] read-write WAKE_EN1 0x000000a4 enable clock in wake mode 0x00007fff CLK_SYS_XOSC [14:14] read-write CLK_SYS_XIP [13:13] read-write CLK_SYS_WATCHDOG [12:12] read-write CLK_USB_USBCTRL [11:11] read-write CLK_SYS_USBCTRL [10:10] read-write CLK_SYS_UART1 [9:9] read-write CLK_PERI_UART1 [8:8] read-write CLK_SYS_UART0 [7:7] read-write CLK_PERI_UART0 [6:6] read-write CLK_SYS_TIMER [5:5] read-write CLK_SYS_TBMAN [4:4] read-write CLK_SYS_SYSINFO [3:3] read-write CLK_SYS_SYSCFG [2:2] read-write CLK_SYS_SRAM5 [1:1] read-write CLK_SYS_SRAM4 [0:0] read-write SLEEP_EN0 0x000000a8 enable clock in sleep mode 0xffffffff CLK_SYS_SRAM3 [31:31] read-write CLK_SYS_SRAM2 [30:30] read-write CLK_SYS_SRAM1 [29:29] read-write CLK_SYS_SRAM0 [28:28] read-write CLK_SYS_SPI1 [27:27] read-write CLK_PERI_SPI1 [26:26] read-write CLK_SYS_SPI0 [25:25] read-write CLK_PERI_SPI0 [24:24] read-write CLK_SYS_SIO [23:23] read-write CLK_SYS_RTC [22:22] read-write CLK_RTC_RTC [21:21] read-write CLK_SYS_ROSC [20:20] read-write CLK_SYS_ROM [19:19] read-write CLK_SYS_RESETS [18:18] read-write CLK_SYS_PWM [17:17] read-write CLK_SYS_PSM [16:16] read-write CLK_SYS_PLL_USB [15:15] read-write CLK_SYS_PLL_SYS [14:14] read-write CLK_SYS_PIO1 [13:13] read-write CLK_SYS_PIO0 [12:12] read-write CLK_SYS_PADS [11:11] read-write CLK_SYS_VREG_AND_CHIP_RESET [10:10] read-write CLK_SYS_JTAG [9:9] read-write CLK_SYS_IO [8:8] read-write CLK_SYS_I2C1 [7:7] read-write CLK_SYS_I2C0 [6:6] read-write CLK_SYS_DMA [5:5] read-write CLK_SYS_BUSFABRIC [4:4] read-write CLK_SYS_BUSCTRL [3:3] read-write CLK_SYS_ADC [2:2] read-write CLK_ADC_ADC [1:1] read-write CLK_SYS_CLOCKS [0:0] read-write SLEEP_EN1 0x000000ac enable clock in sleep mode 0x00007fff CLK_SYS_XOSC [14:14] read-write CLK_SYS_XIP [13:13] read-write CLK_SYS_WATCHDOG [12:12] read-write CLK_USB_USBCTRL [11:11] read-write CLK_SYS_USBCTRL [10:10] read-write CLK_SYS_UART1 [9:9] read-write CLK_PERI_UART1 [8:8] read-write CLK_SYS_UART0 [7:7] read-write CLK_PERI_UART0 [6:6] read-write CLK_SYS_TIMER [5:5] read-write CLK_SYS_TBMAN [4:4] read-write CLK_SYS_SYSINFO [3:3] read-write CLK_SYS_SYSCFG [2:2] read-write CLK_SYS_SRAM5 [1:1] read-write CLK_SYS_SRAM4 [0:0] read-write ENABLED0 0x000000b0 indicates the state of the clock enable 0x00000000 CLK_SYS_SRAM3 [31:31] read-only CLK_SYS_SRAM2 [30:30] read-only CLK_SYS_SRAM1 [29:29] read-only CLK_SYS_SRAM0 [28:28] read-only CLK_SYS_SPI1 [27:27] read-only CLK_PERI_SPI1 [26:26] read-only CLK_SYS_SPI0 [25:25] read-only CLK_PERI_SPI0 [24:24] read-only CLK_SYS_SIO [23:23] read-only CLK_SYS_RTC [22:22] read-only CLK_RTC_RTC [21:21] read-only CLK_SYS_ROSC [20:20] read-only CLK_SYS_ROM [19:19] read-only CLK_SYS_RESETS [18:18] read-only CLK_SYS_PWM [17:17] read-only CLK_SYS_PSM [16:16] read-only CLK_SYS_PLL_USB [15:15] read-only CLK_SYS_PLL_SYS [14:14] read-only CLK_SYS_PIO1 [13:13] read-only CLK_SYS_PIO0 [12:12] read-only CLK_SYS_PADS [11:11] read-only CLK_SYS_VREG_AND_CHIP_RESET [10:10] read-only CLK_SYS_JTAG [9:9] read-only CLK_SYS_IO [8:8] read-only CLK_SYS_I2C1 [7:7] read-only CLK_SYS_I2C0 [6:6] read-only CLK_SYS_DMA [5:5] read-only CLK_SYS_BUSFABRIC [4:4] read-only CLK_SYS_BUSCTRL [3:3] read-only CLK_SYS_ADC [2:2] read-only CLK_ADC_ADC [1:1] read-only CLK_SYS_CLOCKS [0:0] read-only ENABLED1 0x000000b4 indicates the state of the clock enable 0x00000000 CLK_SYS_XOSC [14:14] read-only CLK_SYS_XIP [13:13] read-only CLK_SYS_WATCHDOG [12:12] read-only CLK_USB_USBCTRL [11:11] read-only CLK_SYS_USBCTRL [10:10] read-only CLK_SYS_UART1 [9:9] read-only CLK_PERI_UART1 [8:8] read-only CLK_SYS_UART0 [7:7] read-only CLK_PERI_UART0 [6:6] read-only CLK_SYS_TIMER [5:5] read-only CLK_SYS_TBMAN [4:4] read-only CLK_SYS_SYSINFO [3:3] read-only CLK_SYS_SYSCFG [2:2] read-only CLK_SYS_SRAM5 [1:1] read-only CLK_SYS_SRAM4 [0:0] read-only INTR 0x000000b8 Raw Interrupts 0x00000000 CLK_SYS_RESUS [0:0] read-only INTE 0x000000bc Interrupt Enable 0x00000000 CLK_SYS_RESUS [0:0] read-write INTF 0x000000c0 Interrupt Force 0x00000000 CLK_SYS_RESUS [0:0] read-write INTS 0x000000c4 Interrupt status after masking & forcing 0x00000000 CLK_SYS_RESUS [0:0] read-only PADS_BANK0 0x4001c000 0 132 registers VOLTAGE_SELECT 0x00000000 Voltage select. Per bank control 0x00000000 VOLTAGE_SELECT [0:0] read-write 3v3 0 Set voltage to 3.3V (DVDD >= 2V5) 1v8 1 Set voltage to 1.8V (DVDD <= 1V8) GPIO0 0x00000004 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO1 0x00000008 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO2 0x0000000c Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO3 0x00000010 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO4 0x00000014 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO5 0x00000018 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO6 0x0000001c Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO7 0x00000020 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO8 0x00000024 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO9 0x00000028 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO10 0x0000002c Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO11 0x00000030 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO12 0x00000034 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO13 0x00000038 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO14 0x0000003c Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO15 0x00000040 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO16 0x00000044 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO17 0x00000048 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO18 0x0000004c Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO19 0x00000050 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO20 0x00000054 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO21 0x00000058 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO22 0x0000005c Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO23 0x00000060 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO24 0x00000064 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO25 0x00000068 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO26 0x0000006c Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO27 0x00000070 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO28 0x00000074 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO29 0x00000078 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write SWCLK 0x0000007c Pad control register 0x000000da OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write SWD 0x00000080 Pad control register 0x0000005a OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write PADS_QSPI 0x40020000 0 28 registers VOLTAGE_SELECT 0x00000000 Voltage select. Per bank control 0x00000000 VOLTAGE_SELECT [0:0] read-write 3v3 0 Set voltage to 3.3V (DVDD >= 2V5) 1v8 1 Set voltage to 1.8V (DVDD <= 1V8) GPIO_QSPI_SCLK 0x00000004 Pad control register 0x00000056 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SD0 0x00000008 Pad control register 0x00000052 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SD1 0x0000000c Pad control register 0x00000052 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SD2 0x00000010 Pad control register 0x00000052 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SD3 0x00000014 Pad control register 0x00000052 OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write GPIO_QSPI_SS 0x00000018 Pad control register 0x0000005a OD Output disable. Has priority over output enable from peripherals [7:7] read-write IE Input enable [6:6] read-write DRIVE Drive strength. [5:4] read-write 2mA 0 4mA 1 8mA 2 12mA 3 PUE Pull up enable [3:3] read-write PDE Pull down enable [2:2] read-write SCHMITT Enable schmitt trigger [1:1] read-write SLEWFAST Slew rate control. 1 = Fast, 0 = Slow [0:0] read-write IO_QSPI 0x40018000 0 88 registers IO_IRQ_QSPI 14 GPIO_QSPI_SCLK_STATUS 0x00000000 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO_QSPI_SCLK_CTRL 0x00000004 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write xip_sclk 0 sio_30 5 null 31 GPIO_QSPI_SS_STATUS 0x00000008 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO_QSPI_SS_CTRL 0x0000000c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write xip_ss_n 0 sio_31 5 null 31 GPIO_QSPI_SD0_STATUS 0x00000010 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO_QSPI_SD0_CTRL 0x00000014 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write xip_sd0 0 sio_32 5 null 31 GPIO_QSPI_SD1_STATUS 0x00000018 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO_QSPI_SD1_CTRL 0x0000001c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write xip_sd1 0 sio_33 5 null 31 GPIO_QSPI_SD2_STATUS 0x00000020 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO_QSPI_SD2_CTRL 0x00000024 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write xip_sd2 0 sio_34 5 null 31 GPIO_QSPI_SD3_STATUS 0x00000028 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO_QSPI_SD3_CTRL 0x0000002c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write xip_sd3 0 sio_35 5 null 31 INTR 0x00000030 Raw Interrupts 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write oneToClear GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write oneToClear GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-only GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-only GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write oneToClear GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write oneToClear GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-only GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-only GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write oneToClear GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write oneToClear GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-only GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-only GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write oneToClear GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write oneToClear GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-only GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-only GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write oneToClear GPIO_QSPI_SS_EDGE_LOW [6:6] read-write oneToClear GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-only GPIO_QSPI_SS_LEVEL_LOW [4:4] read-only GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write oneToClear GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write oneToClear GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-only GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-only PROC0_INTE 0x00000034 Interrupt Enable for proc0 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write GPIO_QSPI_SS_EDGE_LOW [6:6] read-write GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write PROC0_INTF 0x00000038 Interrupt Force for proc0 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write GPIO_QSPI_SS_EDGE_LOW [6:6] read-write GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write PROC0_INTS 0x0000003c Interrupt status after masking & forcing for proc0 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-only GPIO_QSPI_SD3_EDGE_LOW [22:22] read-only GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-only GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-only GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-only GPIO_QSPI_SD2_EDGE_LOW [18:18] read-only GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-only GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-only GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-only GPIO_QSPI_SD1_EDGE_LOW [14:14] read-only GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-only GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-only GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-only GPIO_QSPI_SD0_EDGE_LOW [10:10] read-only GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-only GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-only GPIO_QSPI_SS_EDGE_HIGH [7:7] read-only GPIO_QSPI_SS_EDGE_LOW [6:6] read-only GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-only GPIO_QSPI_SS_LEVEL_LOW [4:4] read-only GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-only GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-only GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-only GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-only PROC1_INTE 0x00000040 Interrupt Enable for proc1 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write GPIO_QSPI_SS_EDGE_LOW [6:6] read-write GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write PROC1_INTF 0x00000044 Interrupt Force for proc1 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write GPIO_QSPI_SS_EDGE_LOW [6:6] read-write GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write PROC1_INTS 0x00000048 Interrupt status after masking & forcing for proc1 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-only GPIO_QSPI_SD3_EDGE_LOW [22:22] read-only GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-only GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-only GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-only GPIO_QSPI_SD2_EDGE_LOW [18:18] read-only GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-only GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-only GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-only GPIO_QSPI_SD1_EDGE_LOW [14:14] read-only GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-only GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-only GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-only GPIO_QSPI_SD0_EDGE_LOW [10:10] read-only GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-only GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-only GPIO_QSPI_SS_EDGE_HIGH [7:7] read-only GPIO_QSPI_SS_EDGE_LOW [6:6] read-only GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-only GPIO_QSPI_SS_LEVEL_LOW [4:4] read-only GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-only GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-only GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-only GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-only DORMANT_WAKE_INTE 0x0000004c Interrupt Enable for dormant_wake 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write GPIO_QSPI_SS_EDGE_LOW [6:6] read-write GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTF 0x00000050 Interrupt Force for dormant_wake 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-write GPIO_QSPI_SD3_EDGE_LOW [22:22] read-write GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-write GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-write GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-write GPIO_QSPI_SD2_EDGE_LOW [18:18] read-write GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-write GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-write GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-write GPIO_QSPI_SD1_EDGE_LOW [14:14] read-write GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-write GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-write GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-write GPIO_QSPI_SD0_EDGE_LOW [10:10] read-write GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-write GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-write GPIO_QSPI_SS_EDGE_HIGH [7:7] read-write GPIO_QSPI_SS_EDGE_LOW [6:6] read-write GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-write GPIO_QSPI_SS_LEVEL_LOW [4:4] read-write GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-write GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-write GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-write GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTS 0x00000054 Interrupt status after masking & forcing for dormant_wake 0x00000000 GPIO_QSPI_SD3_EDGE_HIGH [23:23] read-only GPIO_QSPI_SD3_EDGE_LOW [22:22] read-only GPIO_QSPI_SD3_LEVEL_HIGH [21:21] read-only GPIO_QSPI_SD3_LEVEL_LOW [20:20] read-only GPIO_QSPI_SD2_EDGE_HIGH [19:19] read-only GPIO_QSPI_SD2_EDGE_LOW [18:18] read-only GPIO_QSPI_SD2_LEVEL_HIGH [17:17] read-only GPIO_QSPI_SD2_LEVEL_LOW [16:16] read-only GPIO_QSPI_SD1_EDGE_HIGH [15:15] read-only GPIO_QSPI_SD1_EDGE_LOW [14:14] read-only GPIO_QSPI_SD1_LEVEL_HIGH [13:13] read-only GPIO_QSPI_SD1_LEVEL_LOW [12:12] read-only GPIO_QSPI_SD0_EDGE_HIGH [11:11] read-only GPIO_QSPI_SD0_EDGE_LOW [10:10] read-only GPIO_QSPI_SD0_LEVEL_HIGH [9:9] read-only GPIO_QSPI_SD0_LEVEL_LOW [8:8] read-only GPIO_QSPI_SS_EDGE_HIGH [7:7] read-only GPIO_QSPI_SS_EDGE_LOW [6:6] read-only GPIO_QSPI_SS_LEVEL_HIGH [5:5] read-only GPIO_QSPI_SS_LEVEL_LOW [4:4] read-only GPIO_QSPI_SCLK_EDGE_HIGH [3:3] read-only GPIO_QSPI_SCLK_EDGE_LOW [2:2] read-only GPIO_QSPI_SCLK_LEVEL_HIGH [1:1] read-only GPIO_QSPI_SCLK_LEVEL_LOW [0:0] read-only IO_BANK0 0x40014000 0 400 registers IO_IRQ_BANK0 13 GPIO0_STATUS 0x00000000 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO0_CTRL 0x00000004 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write jtag_tck 0 spi0_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_0 4 sio_0 5 pio0_0 6 pio1_0 7 usb_muxing_overcurr_detect 9 null 31 GPIO1_STATUS 0x00000008 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO1_CTRL 0x0000000c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write jtag_tms 0 spi0_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_0 4 sio_1 5 pio0_1 6 pio1_1 7 usb_muxing_vbus_detect 9 null 31 GPIO2_STATUS 0x00000010 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO2_CTRL 0x00000014 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write jtag_tdi 0 spi0_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_1 4 sio_2 5 pio0_2 6 pio1_2 7 usb_muxing_vbus_en 9 null 31 GPIO3_STATUS 0x00000018 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO3_CTRL 0x0000001c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write jtag_tdo 0 spi0_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_1 4 sio_3 5 pio0_3 6 pio1_3 7 usb_muxing_overcurr_detect 9 null 31 GPIO4_STATUS 0x00000020 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO4_CTRL 0x00000024 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_2 4 sio_4 5 pio0_4 6 pio1_4 7 usb_muxing_vbus_detect 9 null 31 GPIO5_STATUS 0x00000028 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO5_CTRL 0x0000002c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_2 4 sio_5 5 pio0_5 6 pio1_5 7 usb_muxing_vbus_en 9 null 31 GPIO6_STATUS 0x00000030 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO6_CTRL 0x00000034 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_3 4 sio_6 5 pio0_6 6 pio1_6 7 usb_muxing_extphy_softcon 8 usb_muxing_overcurr_detect 9 null 31 GPIO7_STATUS 0x00000038 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO7_CTRL 0x0000003c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_3 4 sio_7 5 pio0_7 6 pio1_7 7 usb_muxing_extphy_oe_n 8 usb_muxing_vbus_detect 9 null 31 GPIO8_STATUS 0x00000040 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO8_CTRL 0x00000044 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_4 4 sio_8 5 pio0_8 6 pio1_8 7 usb_muxing_extphy_rcv 8 usb_muxing_vbus_en 9 null 31 GPIO9_STATUS 0x00000048 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO9_CTRL 0x0000004c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_4 4 sio_9 5 pio0_9 6 pio1_9 7 usb_muxing_extphy_vp 8 usb_muxing_overcurr_detect 9 null 31 GPIO10_STATUS 0x00000050 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO10_CTRL 0x00000054 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_5 4 sio_10 5 pio0_10 6 pio1_10 7 usb_muxing_extphy_vm 8 usb_muxing_vbus_detect 9 null 31 GPIO11_STATUS 0x00000058 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO11_CTRL 0x0000005c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_5 4 sio_11 5 pio0_11 6 pio1_11 7 usb_muxing_extphy_suspnd 8 usb_muxing_vbus_en 9 null 31 GPIO12_STATUS 0x00000060 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO12_CTRL 0x00000064 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_6 4 sio_12 5 pio0_12 6 pio1_12 7 usb_muxing_extphy_speed 8 usb_muxing_overcurr_detect 9 null 31 GPIO13_STATUS 0x00000068 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO13_CTRL 0x0000006c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_6 4 sio_13 5 pio0_13 6 pio1_13 7 usb_muxing_extphy_vpo 8 usb_muxing_vbus_detect 9 null 31 GPIO14_STATUS 0x00000070 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO14_CTRL 0x00000074 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_7 4 sio_14 5 pio0_14 6 pio1_14 7 usb_muxing_extphy_vmo 8 usb_muxing_vbus_en 9 null 31 GPIO15_STATUS 0x00000078 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO15_CTRL 0x0000007c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_7 4 sio_15 5 pio0_15 6 pio1_15 7 usb_muxing_digital_dp 8 usb_muxing_overcurr_detect 9 null 31 GPIO16_STATUS 0x00000080 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO16_CTRL 0x00000084 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_0 4 sio_16 5 pio0_16 6 pio1_16 7 usb_muxing_digital_dm 8 usb_muxing_vbus_detect 9 null 31 GPIO17_STATUS 0x00000088 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO17_CTRL 0x0000008c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_0 4 sio_17 5 pio0_17 6 pio1_17 7 usb_muxing_vbus_en 9 null 31 GPIO18_STATUS 0x00000090 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO18_CTRL 0x00000094 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_sclk 1 uart0_cts 2 i2c1_sda 3 pwm_a_1 4 sio_18 5 pio0_18 6 pio1_18 7 usb_muxing_overcurr_detect 9 null 31 GPIO19_STATUS 0x00000098 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO19_CTRL 0x0000009c GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_tx 1 uart0_rts 2 i2c1_scl 3 pwm_b_1 4 sio_19 5 pio0_19 6 pio1_19 7 usb_muxing_vbus_detect 9 null 31 GPIO20_STATUS 0x000000a0 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO20_CTRL 0x000000a4 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_2 4 sio_20 5 pio0_20 6 pio1_20 7 clocks_gpin_0 8 usb_muxing_vbus_en 9 null 31 GPIO21_STATUS 0x000000a8 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO21_CTRL 0x000000ac GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_2 4 sio_21 5 pio0_21 6 pio1_21 7 clocks_gpout_0 8 usb_muxing_overcurr_detect 9 null 31 GPIO22_STATUS 0x000000b0 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO22_CTRL 0x000000b4 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_3 4 sio_22 5 pio0_22 6 pio1_22 7 clocks_gpin_1 8 usb_muxing_vbus_detect 9 null 31 GPIO23_STATUS 0x000000b8 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO23_CTRL 0x000000bc GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi0_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_3 4 sio_23 5 pio0_23 6 pio1_23 7 clocks_gpout_1 8 usb_muxing_vbus_en 9 null 31 GPIO24_STATUS 0x000000c0 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO24_CTRL 0x000000c4 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_rx 1 uart1_tx 2 i2c0_sda 3 pwm_a_4 4 sio_24 5 pio0_24 6 pio1_24 7 clocks_gpout_2 8 usb_muxing_overcurr_detect 9 null 31 GPIO25_STATUS 0x000000c8 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO25_CTRL 0x000000cc GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_ss_n 1 uart1_rx 2 i2c0_scl 3 pwm_b_4 4 sio_25 5 pio0_25 6 pio1_25 7 clocks_gpout_3 8 usb_muxing_vbus_detect 9 null 31 GPIO26_STATUS 0x000000d0 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO26_CTRL 0x000000d4 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_sclk 1 uart1_cts 2 i2c1_sda 3 pwm_a_5 4 sio_26 5 pio0_26 6 pio1_26 7 usb_muxing_vbus_en 9 null 31 GPIO27_STATUS 0x000000d8 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO27_CTRL 0x000000dc GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_tx 1 uart1_rts 2 i2c1_scl 3 pwm_b_5 4 sio_27 5 pio0_27 6 pio1_27 7 usb_muxing_overcurr_detect 9 null 31 GPIO28_STATUS 0x000000e0 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO28_CTRL 0x000000e4 GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_rx 1 uart0_tx 2 i2c0_sda 3 pwm_a_6 4 sio_28 5 pio0_28 6 pio1_28 7 usb_muxing_vbus_detect 9 null 31 GPIO29_STATUS 0x000000e8 GPIO status 0x00000000 IRQTOPROC interrupt to processors, after override is applied [26:26] read-only IRQFROMPAD interrupt from pad before override is applied [24:24] read-only INTOPERI input signal to peripheral, after override is applied [19:19] read-only INFROMPAD input signal from pad, before override is applied [17:17] read-only OETOPAD output enable to pad after register override is applied [13:13] read-only OEFROMPERI output enable from selected peripheral, before register override is applied [12:12] read-only OUTTOPAD output signal to pad after register override is applied [9:9] read-only OUTFROMPERI output signal from selected peripheral, before register override is applied [8:8] read-only GPIO29_CTRL 0x000000ec GPIO control including function select and overrides. 0x0000001f IRQOVER [29:28] read-write NORMAL 0 don't invert the interrupt INVERT 1 invert the interrupt LOW 2 drive interrupt low HIGH 3 drive interrupt high INOVER [17:16] read-write NORMAL 0 don't invert the peri input INVERT 1 invert the peri input LOW 2 drive peri input low HIGH 3 drive peri input high OEOVER [13:12] read-write NORMAL 0 drive output enable from peripheral signal selected by funcsel INVERT 1 drive output enable from inverse of peripheral signal selected by funcsel DISABLE 2 disable output ENABLE 3 enable output OUTOVER [9:8] read-write NORMAL 0 drive output from peripheral signal selected by funcsel INVERT 1 drive output from inverse of peripheral signal selected by funcsel LOW 2 drive output low HIGH 3 drive output high FUNCSEL 0-31 -> selects pin function according to the gpio table 31 == NULL [4:0] read-write spi1_ss_n 1 uart0_rx 2 i2c0_scl 3 pwm_b_6 4 sio_29 5 pio0_29 6 pio1_29 7 usb_muxing_vbus_en 9 null 31 INTR0 0x000000f0 Raw Interrupts 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write oneToClear GPIO7_EDGE_LOW [30:30] read-write oneToClear GPIO7_LEVEL_HIGH [29:29] read-only GPIO7_LEVEL_LOW [28:28] read-only GPIO6_EDGE_HIGH [27:27] read-write oneToClear GPIO6_EDGE_LOW [26:26] read-write oneToClear GPIO6_LEVEL_HIGH [25:25] read-only GPIO6_LEVEL_LOW [24:24] read-only GPIO5_EDGE_HIGH [23:23] read-write oneToClear GPIO5_EDGE_LOW [22:22] read-write oneToClear GPIO5_LEVEL_HIGH [21:21] read-only GPIO5_LEVEL_LOW [20:20] read-only GPIO4_EDGE_HIGH [19:19] read-write oneToClear GPIO4_EDGE_LOW [18:18] read-write oneToClear GPIO4_LEVEL_HIGH [17:17] read-only GPIO4_LEVEL_LOW [16:16] read-only GPIO3_EDGE_HIGH [15:15] read-write oneToClear GPIO3_EDGE_LOW [14:14] read-write oneToClear GPIO3_LEVEL_HIGH [13:13] read-only GPIO3_LEVEL_LOW [12:12] read-only GPIO2_EDGE_HIGH [11:11] read-write oneToClear GPIO2_EDGE_LOW [10:10] read-write oneToClear GPIO2_LEVEL_HIGH [9:9] read-only GPIO2_LEVEL_LOW [8:8] read-only GPIO1_EDGE_HIGH [7:7] read-write oneToClear GPIO1_EDGE_LOW [6:6] read-write oneToClear GPIO1_LEVEL_HIGH [5:5] read-only GPIO1_LEVEL_LOW [4:4] read-only GPIO0_EDGE_HIGH [3:3] read-write oneToClear GPIO0_EDGE_LOW [2:2] read-write oneToClear GPIO0_LEVEL_HIGH [1:1] read-only GPIO0_LEVEL_LOW [0:0] read-only INTR1 0x000000f4 Raw Interrupts 0x00000000 GPIO15_EDGE_HIGH [31:31] read-write oneToClear GPIO15_EDGE_LOW [30:30] read-write oneToClear GPIO15_LEVEL_HIGH [29:29] read-only GPIO15_LEVEL_LOW [28:28] read-only GPIO14_EDGE_HIGH [27:27] read-write oneToClear GPIO14_EDGE_LOW [26:26] read-write oneToClear GPIO14_LEVEL_HIGH [25:25] read-only GPIO14_LEVEL_LOW [24:24] read-only GPIO13_EDGE_HIGH [23:23] read-write oneToClear GPIO13_EDGE_LOW [22:22] read-write oneToClear GPIO13_LEVEL_HIGH [21:21] read-only GPIO13_LEVEL_LOW [20:20] read-only GPIO12_EDGE_HIGH [19:19] read-write oneToClear GPIO12_EDGE_LOW [18:18] read-write oneToClear GPIO12_LEVEL_HIGH [17:17] read-only GPIO12_LEVEL_LOW [16:16] read-only GPIO11_EDGE_HIGH [15:15] read-write oneToClear GPIO11_EDGE_LOW [14:14] read-write oneToClear GPIO11_LEVEL_HIGH [13:13] read-only GPIO11_LEVEL_LOW [12:12] read-only GPIO10_EDGE_HIGH [11:11] read-write oneToClear GPIO10_EDGE_LOW [10:10] read-write oneToClear GPIO10_LEVEL_HIGH [9:9] read-only GPIO10_LEVEL_LOW [8:8] read-only GPIO9_EDGE_HIGH [7:7] read-write oneToClear GPIO9_EDGE_LOW [6:6] read-write oneToClear GPIO9_LEVEL_HIGH [5:5] read-only GPIO9_LEVEL_LOW [4:4] read-only GPIO8_EDGE_HIGH [3:3] read-write oneToClear GPIO8_EDGE_LOW [2:2] read-write oneToClear GPIO8_LEVEL_HIGH [1:1] read-only GPIO8_LEVEL_LOW [0:0] read-only INTR2 0x000000f8 Raw Interrupts 0x00000000 GPIO23_EDGE_HIGH [31:31] read-write oneToClear GPIO23_EDGE_LOW [30:30] read-write oneToClear GPIO23_LEVEL_HIGH [29:29] read-only GPIO23_LEVEL_LOW [28:28] read-only GPIO22_EDGE_HIGH [27:27] read-write oneToClear GPIO22_EDGE_LOW [26:26] read-write oneToClear GPIO22_LEVEL_HIGH [25:25] read-only GPIO22_LEVEL_LOW [24:24] read-only GPIO21_EDGE_HIGH [23:23] read-write oneToClear GPIO21_EDGE_LOW [22:22] read-write oneToClear GPIO21_LEVEL_HIGH [21:21] read-only GPIO21_LEVEL_LOW [20:20] read-only GPIO20_EDGE_HIGH [19:19] read-write oneToClear GPIO20_EDGE_LOW [18:18] read-write oneToClear GPIO20_LEVEL_HIGH [17:17] read-only GPIO20_LEVEL_LOW [16:16] read-only GPIO19_EDGE_HIGH [15:15] read-write oneToClear GPIO19_EDGE_LOW [14:14] read-write oneToClear GPIO19_LEVEL_HIGH [13:13] read-only GPIO19_LEVEL_LOW [12:12] read-only GPIO18_EDGE_HIGH [11:11] read-write oneToClear GPIO18_EDGE_LOW [10:10] read-write oneToClear GPIO18_LEVEL_HIGH [9:9] read-only GPIO18_LEVEL_LOW [8:8] read-only GPIO17_EDGE_HIGH [7:7] read-write oneToClear GPIO17_EDGE_LOW [6:6] read-write oneToClear GPIO17_LEVEL_HIGH [5:5] read-only GPIO17_LEVEL_LOW [4:4] read-only GPIO16_EDGE_HIGH [3:3] read-write oneToClear GPIO16_EDGE_LOW [2:2] read-write oneToClear GPIO16_LEVEL_HIGH [1:1] read-only GPIO16_LEVEL_LOW [0:0] read-only INTR3 0x000000fc Raw Interrupts 0x00000000 GPIO29_EDGE_HIGH [23:23] read-write oneToClear GPIO29_EDGE_LOW [22:22] read-write oneToClear GPIO29_LEVEL_HIGH [21:21] read-only GPIO29_LEVEL_LOW [20:20] read-only GPIO28_EDGE_HIGH [19:19] read-write oneToClear GPIO28_EDGE_LOW [18:18] read-write oneToClear GPIO28_LEVEL_HIGH [17:17] read-only GPIO28_LEVEL_LOW [16:16] read-only GPIO27_EDGE_HIGH [15:15] read-write oneToClear GPIO27_EDGE_LOW [14:14] read-write oneToClear GPIO27_LEVEL_HIGH [13:13] read-only GPIO27_LEVEL_LOW [12:12] read-only GPIO26_EDGE_HIGH [11:11] read-write oneToClear GPIO26_EDGE_LOW [10:10] read-write oneToClear GPIO26_LEVEL_HIGH [9:9] read-only GPIO26_LEVEL_LOW [8:8] read-only GPIO25_EDGE_HIGH [7:7] read-write oneToClear GPIO25_EDGE_LOW [6:6] read-write oneToClear GPIO25_LEVEL_HIGH [5:5] read-only GPIO25_LEVEL_LOW [4:4] read-only GPIO24_EDGE_HIGH [3:3] read-write oneToClear GPIO24_EDGE_LOW [2:2] read-write oneToClear GPIO24_LEVEL_HIGH [1:1] read-only GPIO24_LEVEL_LOW [0:0] read-only PROC0_INTE0 0x00000100 Interrupt Enable for proc0 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write PROC0_INTE1 0x00000104 Interrupt Enable for proc0 0x00000000 GPIO15_EDGE_HIGH [31:31] read-write GPIO15_EDGE_LOW [30:30] read-write GPIO15_LEVEL_HIGH [29:29] read-write GPIO15_LEVEL_LOW [28:28] read-write GPIO14_EDGE_HIGH [27:27] read-write GPIO14_EDGE_LOW [26:26] read-write GPIO14_LEVEL_HIGH [25:25] read-write GPIO14_LEVEL_LOW [24:24] read-write GPIO13_EDGE_HIGH [23:23] read-write GPIO13_EDGE_LOW [22:22] read-write GPIO13_LEVEL_HIGH [21:21] read-write GPIO13_LEVEL_LOW [20:20] read-write GPIO12_EDGE_HIGH [19:19] read-write GPIO12_EDGE_LOW [18:18] read-write GPIO12_LEVEL_HIGH [17:17] read-write GPIO12_LEVEL_LOW [16:16] read-write GPIO11_EDGE_HIGH [15:15] read-write GPIO11_EDGE_LOW [14:14] read-write GPIO11_LEVEL_HIGH [13:13] read-write GPIO11_LEVEL_LOW [12:12] read-write GPIO10_EDGE_HIGH [11:11] read-write GPIO10_EDGE_LOW [10:10] read-write GPIO10_LEVEL_HIGH [9:9] read-write GPIO10_LEVEL_LOW [8:8] read-write GPIO9_EDGE_HIGH [7:7] read-write GPIO9_EDGE_LOW [6:6] read-write GPIO9_LEVEL_HIGH [5:5] read-write GPIO9_LEVEL_LOW [4:4] read-write GPIO8_EDGE_HIGH [3:3] read-write GPIO8_EDGE_LOW [2:2] read-write GPIO8_LEVEL_HIGH [1:1] read-write GPIO8_LEVEL_LOW [0:0] read-write PROC0_INTE2 0x00000108 Interrupt Enable for proc0 0x00000000 GPIO23_EDGE_HIGH [31:31] read-write GPIO23_EDGE_LOW [30:30] read-write GPIO23_LEVEL_HIGH [29:29] read-write GPIO23_LEVEL_LOW [28:28] read-write GPIO22_EDGE_HIGH [27:27] read-write GPIO22_EDGE_LOW [26:26] read-write GPIO22_LEVEL_HIGH [25:25] read-write GPIO22_LEVEL_LOW [24:24] read-write GPIO21_EDGE_HIGH [23:23] read-write GPIO21_EDGE_LOW [22:22] read-write GPIO21_LEVEL_HIGH [21:21] read-write GPIO21_LEVEL_LOW [20:20] read-write GPIO20_EDGE_HIGH [19:19] read-write GPIO20_EDGE_LOW [18:18] read-write GPIO20_LEVEL_HIGH [17:17] read-write GPIO20_LEVEL_LOW [16:16] read-write GPIO19_EDGE_HIGH [15:15] read-write GPIO19_EDGE_LOW [14:14] read-write GPIO19_LEVEL_HIGH [13:13] read-write GPIO19_LEVEL_LOW [12:12] read-write GPIO18_EDGE_HIGH [11:11] read-write GPIO18_EDGE_LOW [10:10] read-write GPIO18_LEVEL_HIGH [9:9] read-write GPIO18_LEVEL_LOW [8:8] read-write GPIO17_EDGE_HIGH [7:7] read-write GPIO17_EDGE_LOW [6:6] read-write GPIO17_LEVEL_HIGH [5:5] read-write GPIO17_LEVEL_LOW [4:4] read-write GPIO16_EDGE_HIGH [3:3] read-write GPIO16_EDGE_LOW [2:2] read-write GPIO16_LEVEL_HIGH [1:1] read-write GPIO16_LEVEL_LOW [0:0] read-write PROC0_INTE3 0x0000010c Interrupt Enable for proc0 0x00000000 GPIO29_EDGE_HIGH [23:23] read-write GPIO29_EDGE_LOW [22:22] read-write GPIO29_LEVEL_HIGH [21:21] read-write GPIO29_LEVEL_LOW [20:20] read-write GPIO28_EDGE_HIGH [19:19] read-write GPIO28_EDGE_LOW [18:18] read-write GPIO28_LEVEL_HIGH [17:17] read-write GPIO28_LEVEL_LOW [16:16] read-write GPIO27_EDGE_HIGH [15:15] read-write GPIO27_EDGE_LOW [14:14] read-write GPIO27_LEVEL_HIGH [13:13] read-write GPIO27_LEVEL_LOW [12:12] read-write GPIO26_EDGE_HIGH [11:11] read-write GPIO26_EDGE_LOW [10:10] read-write GPIO26_LEVEL_HIGH [9:9] read-write GPIO26_LEVEL_LOW [8:8] read-write GPIO25_EDGE_HIGH [7:7] read-write GPIO25_EDGE_LOW [6:6] read-write GPIO25_LEVEL_HIGH [5:5] read-write GPIO25_LEVEL_LOW [4:4] read-write GPIO24_EDGE_HIGH [3:3] read-write GPIO24_EDGE_LOW [2:2] read-write GPIO24_LEVEL_HIGH [1:1] read-write GPIO24_LEVEL_LOW [0:0] read-write PROC0_INTF0 0x00000110 Interrupt Force for proc0 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write PROC0_INTF1 0x00000114 Interrupt Force for proc0 0x00000000 GPIO15_EDGE_HIGH [31:31] read-write GPIO15_EDGE_LOW [30:30] read-write GPIO15_LEVEL_HIGH [29:29] read-write GPIO15_LEVEL_LOW [28:28] read-write GPIO14_EDGE_HIGH [27:27] read-write GPIO14_EDGE_LOW [26:26] read-write GPIO14_LEVEL_HIGH [25:25] read-write GPIO14_LEVEL_LOW [24:24] read-write GPIO13_EDGE_HIGH [23:23] read-write GPIO13_EDGE_LOW [22:22] read-write GPIO13_LEVEL_HIGH [21:21] read-write GPIO13_LEVEL_LOW [20:20] read-write GPIO12_EDGE_HIGH [19:19] read-write GPIO12_EDGE_LOW [18:18] read-write GPIO12_LEVEL_HIGH [17:17] read-write GPIO12_LEVEL_LOW [16:16] read-write GPIO11_EDGE_HIGH [15:15] read-write GPIO11_EDGE_LOW [14:14] read-write GPIO11_LEVEL_HIGH [13:13] read-write GPIO11_LEVEL_LOW [12:12] read-write GPIO10_EDGE_HIGH [11:11] read-write GPIO10_EDGE_LOW [10:10] read-write GPIO10_LEVEL_HIGH [9:9] read-write GPIO10_LEVEL_LOW [8:8] read-write GPIO9_EDGE_HIGH [7:7] read-write GPIO9_EDGE_LOW [6:6] read-write GPIO9_LEVEL_HIGH [5:5] read-write GPIO9_LEVEL_LOW [4:4] read-write GPIO8_EDGE_HIGH [3:3] read-write GPIO8_EDGE_LOW [2:2] read-write GPIO8_LEVEL_HIGH [1:1] read-write GPIO8_LEVEL_LOW [0:0] read-write PROC0_INTF2 0x00000118 Interrupt Force for proc0 0x00000000 GPIO23_EDGE_HIGH [31:31] read-write GPIO23_EDGE_LOW [30:30] read-write GPIO23_LEVEL_HIGH [29:29] read-write GPIO23_LEVEL_LOW [28:28] read-write GPIO22_EDGE_HIGH [27:27] read-write GPIO22_EDGE_LOW [26:26] read-write GPIO22_LEVEL_HIGH [25:25] read-write GPIO22_LEVEL_LOW [24:24] read-write GPIO21_EDGE_HIGH [23:23] read-write GPIO21_EDGE_LOW [22:22] read-write GPIO21_LEVEL_HIGH [21:21] read-write GPIO21_LEVEL_LOW [20:20] read-write GPIO20_EDGE_HIGH [19:19] read-write GPIO20_EDGE_LOW [18:18] read-write GPIO20_LEVEL_HIGH [17:17] read-write GPIO20_LEVEL_LOW [16:16] read-write GPIO19_EDGE_HIGH [15:15] read-write GPIO19_EDGE_LOW [14:14] read-write GPIO19_LEVEL_HIGH [13:13] read-write GPIO19_LEVEL_LOW [12:12] read-write GPIO18_EDGE_HIGH [11:11] read-write GPIO18_EDGE_LOW [10:10] read-write GPIO18_LEVEL_HIGH [9:9] read-write GPIO18_LEVEL_LOW [8:8] read-write GPIO17_EDGE_HIGH [7:7] read-write GPIO17_EDGE_LOW [6:6] read-write GPIO17_LEVEL_HIGH [5:5] read-write GPIO17_LEVEL_LOW [4:4] read-write GPIO16_EDGE_HIGH [3:3] read-write GPIO16_EDGE_LOW [2:2] read-write GPIO16_LEVEL_HIGH [1:1] read-write GPIO16_LEVEL_LOW [0:0] read-write PROC0_INTF3 0x0000011c Interrupt Force for proc0 0x00000000 GPIO29_EDGE_HIGH [23:23] read-write GPIO29_EDGE_LOW [22:22] read-write GPIO29_LEVEL_HIGH [21:21] read-write GPIO29_LEVEL_LOW [20:20] read-write GPIO28_EDGE_HIGH [19:19] read-write GPIO28_EDGE_LOW [18:18] read-write GPIO28_LEVEL_HIGH [17:17] read-write GPIO28_LEVEL_LOW [16:16] read-write GPIO27_EDGE_HIGH [15:15] read-write GPIO27_EDGE_LOW [14:14] read-write GPIO27_LEVEL_HIGH [13:13] read-write GPIO27_LEVEL_LOW [12:12] read-write GPIO26_EDGE_HIGH [11:11] read-write GPIO26_EDGE_LOW [10:10] read-write GPIO26_LEVEL_HIGH [9:9] read-write GPIO26_LEVEL_LOW [8:8] read-write GPIO25_EDGE_HIGH [7:7] read-write GPIO25_EDGE_LOW [6:6] read-write GPIO25_LEVEL_HIGH [5:5] read-write GPIO25_LEVEL_LOW [4:4] read-write GPIO24_EDGE_HIGH [3:3] read-write GPIO24_EDGE_LOW [2:2] read-write GPIO24_LEVEL_HIGH [1:1] read-write GPIO24_LEVEL_LOW [0:0] read-write PROC0_INTS0 0x00000120 Interrupt status after masking & forcing for proc0 0x00000000 GPIO7_EDGE_HIGH [31:31] read-only GPIO7_EDGE_LOW [30:30] read-only GPIO7_LEVEL_HIGH [29:29] read-only GPIO7_LEVEL_LOW [28:28] read-only GPIO6_EDGE_HIGH [27:27] read-only GPIO6_EDGE_LOW [26:26] read-only GPIO6_LEVEL_HIGH [25:25] read-only GPIO6_LEVEL_LOW [24:24] read-only GPIO5_EDGE_HIGH [23:23] read-only GPIO5_EDGE_LOW [22:22] read-only GPIO5_LEVEL_HIGH [21:21] read-only GPIO5_LEVEL_LOW [20:20] read-only GPIO4_EDGE_HIGH [19:19] read-only GPIO4_EDGE_LOW [18:18] read-only GPIO4_LEVEL_HIGH [17:17] read-only GPIO4_LEVEL_LOW [16:16] read-only GPIO3_EDGE_HIGH [15:15] read-only GPIO3_EDGE_LOW [14:14] read-only GPIO3_LEVEL_HIGH [13:13] read-only GPIO3_LEVEL_LOW [12:12] read-only GPIO2_EDGE_HIGH [11:11] read-only GPIO2_EDGE_LOW [10:10] read-only GPIO2_LEVEL_HIGH [9:9] read-only GPIO2_LEVEL_LOW [8:8] read-only GPIO1_EDGE_HIGH [7:7] read-only GPIO1_EDGE_LOW [6:6] read-only GPIO1_LEVEL_HIGH [5:5] read-only GPIO1_LEVEL_LOW [4:4] read-only GPIO0_EDGE_HIGH [3:3] read-only GPIO0_EDGE_LOW [2:2] read-only GPIO0_LEVEL_HIGH [1:1] read-only GPIO0_LEVEL_LOW [0:0] read-only PROC0_INTS1 0x00000124 Interrupt status after masking & forcing for proc0 0x00000000 GPIO15_EDGE_HIGH [31:31] read-only GPIO15_EDGE_LOW [30:30] read-only GPIO15_LEVEL_HIGH [29:29] read-only GPIO15_LEVEL_LOW [28:28] read-only GPIO14_EDGE_HIGH [27:27] read-only GPIO14_EDGE_LOW [26:26] read-only GPIO14_LEVEL_HIGH [25:25] read-only GPIO14_LEVEL_LOW [24:24] read-only GPIO13_EDGE_HIGH [23:23] read-only GPIO13_EDGE_LOW [22:22] read-only GPIO13_LEVEL_HIGH [21:21] read-only GPIO13_LEVEL_LOW [20:20] read-only GPIO12_EDGE_HIGH [19:19] read-only GPIO12_EDGE_LOW [18:18] read-only GPIO12_LEVEL_HIGH [17:17] read-only GPIO12_LEVEL_LOW [16:16] read-only GPIO11_EDGE_HIGH [15:15] read-only GPIO11_EDGE_LOW [14:14] read-only GPIO11_LEVEL_HIGH [13:13] read-only GPIO11_LEVEL_LOW [12:12] read-only GPIO10_EDGE_HIGH [11:11] read-only GPIO10_EDGE_LOW [10:10] read-only GPIO10_LEVEL_HIGH [9:9] read-only GPIO10_LEVEL_LOW [8:8] read-only GPIO9_EDGE_HIGH [7:7] read-only GPIO9_EDGE_LOW [6:6] read-only GPIO9_LEVEL_HIGH [5:5] read-only GPIO9_LEVEL_LOW [4:4] read-only GPIO8_EDGE_HIGH [3:3] read-only GPIO8_EDGE_LOW [2:2] read-only GPIO8_LEVEL_HIGH [1:1] read-only GPIO8_LEVEL_LOW [0:0] read-only PROC0_INTS2 0x00000128 Interrupt status after masking & forcing for proc0 0x00000000 GPIO23_EDGE_HIGH [31:31] read-only GPIO23_EDGE_LOW [30:30] read-only GPIO23_LEVEL_HIGH [29:29] read-only GPIO23_LEVEL_LOW [28:28] read-only GPIO22_EDGE_HIGH [27:27] read-only GPIO22_EDGE_LOW [26:26] read-only GPIO22_LEVEL_HIGH [25:25] read-only GPIO22_LEVEL_LOW [24:24] read-only GPIO21_EDGE_HIGH [23:23] read-only GPIO21_EDGE_LOW [22:22] read-only GPIO21_LEVEL_HIGH [21:21] read-only GPIO21_LEVEL_LOW [20:20] read-only GPIO20_EDGE_HIGH [19:19] read-only GPIO20_EDGE_LOW [18:18] read-only GPIO20_LEVEL_HIGH [17:17] read-only GPIO20_LEVEL_LOW [16:16] read-only GPIO19_EDGE_HIGH [15:15] read-only GPIO19_EDGE_LOW [14:14] read-only GPIO19_LEVEL_HIGH [13:13] read-only GPIO19_LEVEL_LOW [12:12] read-only GPIO18_EDGE_HIGH [11:11] read-only GPIO18_EDGE_LOW [10:10] read-only GPIO18_LEVEL_HIGH [9:9] read-only GPIO18_LEVEL_LOW [8:8] read-only GPIO17_EDGE_HIGH [7:7] read-only GPIO17_EDGE_LOW [6:6] read-only GPIO17_LEVEL_HIGH [5:5] read-only GPIO17_LEVEL_LOW [4:4] read-only GPIO16_EDGE_HIGH [3:3] read-only GPIO16_EDGE_LOW [2:2] read-only GPIO16_LEVEL_HIGH [1:1] read-only GPIO16_LEVEL_LOW [0:0] read-only PROC0_INTS3 0x0000012c Interrupt status after masking & forcing for proc0 0x00000000 GPIO29_EDGE_HIGH [23:23] read-only GPIO29_EDGE_LOW [22:22] read-only GPIO29_LEVEL_HIGH [21:21] read-only GPIO29_LEVEL_LOW [20:20] read-only GPIO28_EDGE_HIGH [19:19] read-only GPIO28_EDGE_LOW [18:18] read-only GPIO28_LEVEL_HIGH [17:17] read-only GPIO28_LEVEL_LOW [16:16] read-only GPIO27_EDGE_HIGH [15:15] read-only GPIO27_EDGE_LOW [14:14] read-only GPIO27_LEVEL_HIGH [13:13] read-only GPIO27_LEVEL_LOW [12:12] read-only GPIO26_EDGE_HIGH [11:11] read-only GPIO26_EDGE_LOW [10:10] read-only GPIO26_LEVEL_HIGH [9:9] read-only GPIO26_LEVEL_LOW [8:8] read-only GPIO25_EDGE_HIGH [7:7] read-only GPIO25_EDGE_LOW [6:6] read-only GPIO25_LEVEL_HIGH [5:5] read-only GPIO25_LEVEL_LOW [4:4] read-only GPIO24_EDGE_HIGH [3:3] read-only GPIO24_EDGE_LOW [2:2] read-only GPIO24_LEVEL_HIGH [1:1] read-only GPIO24_LEVEL_LOW [0:0] read-only PROC1_INTE0 0x00000130 Interrupt Enable for proc1 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write PROC1_INTE1 0x00000134 Interrupt Enable for proc1 0x00000000 GPIO15_EDGE_HIGH [31:31] read-write GPIO15_EDGE_LOW [30:30] read-write GPIO15_LEVEL_HIGH [29:29] read-write GPIO15_LEVEL_LOW [28:28] read-write GPIO14_EDGE_HIGH [27:27] read-write GPIO14_EDGE_LOW [26:26] read-write GPIO14_LEVEL_HIGH [25:25] read-write GPIO14_LEVEL_LOW [24:24] read-write GPIO13_EDGE_HIGH [23:23] read-write GPIO13_EDGE_LOW [22:22] read-write GPIO13_LEVEL_HIGH [21:21] read-write GPIO13_LEVEL_LOW [20:20] read-write GPIO12_EDGE_HIGH [19:19] read-write GPIO12_EDGE_LOW [18:18] read-write GPIO12_LEVEL_HIGH [17:17] read-write GPIO12_LEVEL_LOW [16:16] read-write GPIO11_EDGE_HIGH [15:15] read-write GPIO11_EDGE_LOW [14:14] read-write GPIO11_LEVEL_HIGH [13:13] read-write GPIO11_LEVEL_LOW [12:12] read-write GPIO10_EDGE_HIGH [11:11] read-write GPIO10_EDGE_LOW [10:10] read-write GPIO10_LEVEL_HIGH [9:9] read-write GPIO10_LEVEL_LOW [8:8] read-write GPIO9_EDGE_HIGH [7:7] read-write GPIO9_EDGE_LOW [6:6] read-write GPIO9_LEVEL_HIGH [5:5] read-write GPIO9_LEVEL_LOW [4:4] read-write GPIO8_EDGE_HIGH [3:3] read-write GPIO8_EDGE_LOW [2:2] read-write GPIO8_LEVEL_HIGH [1:1] read-write GPIO8_LEVEL_LOW [0:0] read-write PROC1_INTE2 0x00000138 Interrupt Enable for proc1 0x00000000 GPIO23_EDGE_HIGH [31:31] read-write GPIO23_EDGE_LOW [30:30] read-write GPIO23_LEVEL_HIGH [29:29] read-write GPIO23_LEVEL_LOW [28:28] read-write GPIO22_EDGE_HIGH [27:27] read-write GPIO22_EDGE_LOW [26:26] read-write GPIO22_LEVEL_HIGH [25:25] read-write GPIO22_LEVEL_LOW [24:24] read-write GPIO21_EDGE_HIGH [23:23] read-write GPIO21_EDGE_LOW [22:22] read-write GPIO21_LEVEL_HIGH [21:21] read-write GPIO21_LEVEL_LOW [20:20] read-write GPIO20_EDGE_HIGH [19:19] read-write GPIO20_EDGE_LOW [18:18] read-write GPIO20_LEVEL_HIGH [17:17] read-write GPIO20_LEVEL_LOW [16:16] read-write GPIO19_EDGE_HIGH [15:15] read-write GPIO19_EDGE_LOW [14:14] read-write GPIO19_LEVEL_HIGH [13:13] read-write GPIO19_LEVEL_LOW [12:12] read-write GPIO18_EDGE_HIGH [11:11] read-write GPIO18_EDGE_LOW [10:10] read-write GPIO18_LEVEL_HIGH [9:9] read-write GPIO18_LEVEL_LOW [8:8] read-write GPIO17_EDGE_HIGH [7:7] read-write GPIO17_EDGE_LOW [6:6] read-write GPIO17_LEVEL_HIGH [5:5] read-write GPIO17_LEVEL_LOW [4:4] read-write GPIO16_EDGE_HIGH [3:3] read-write GPIO16_EDGE_LOW [2:2] read-write GPIO16_LEVEL_HIGH [1:1] read-write GPIO16_LEVEL_LOW [0:0] read-write PROC1_INTE3 0x0000013c Interrupt Enable for proc1 0x00000000 GPIO29_EDGE_HIGH [23:23] read-write GPIO29_EDGE_LOW [22:22] read-write GPIO29_LEVEL_HIGH [21:21] read-write GPIO29_LEVEL_LOW [20:20] read-write GPIO28_EDGE_HIGH [19:19] read-write GPIO28_EDGE_LOW [18:18] read-write GPIO28_LEVEL_HIGH [17:17] read-write GPIO28_LEVEL_LOW [16:16] read-write GPIO27_EDGE_HIGH [15:15] read-write GPIO27_EDGE_LOW [14:14] read-write GPIO27_LEVEL_HIGH [13:13] read-write GPIO27_LEVEL_LOW [12:12] read-write GPIO26_EDGE_HIGH [11:11] read-write GPIO26_EDGE_LOW [10:10] read-write GPIO26_LEVEL_HIGH [9:9] read-write GPIO26_LEVEL_LOW [8:8] read-write GPIO25_EDGE_HIGH [7:7] read-write GPIO25_EDGE_LOW [6:6] read-write GPIO25_LEVEL_HIGH [5:5] read-write GPIO25_LEVEL_LOW [4:4] read-write GPIO24_EDGE_HIGH [3:3] read-write GPIO24_EDGE_LOW [2:2] read-write GPIO24_LEVEL_HIGH [1:1] read-write GPIO24_LEVEL_LOW [0:0] read-write PROC1_INTF0 0x00000140 Interrupt Force for proc1 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write PROC1_INTF1 0x00000144 Interrupt Force for proc1 0x00000000 GPIO15_EDGE_HIGH [31:31] read-write GPIO15_EDGE_LOW [30:30] read-write GPIO15_LEVEL_HIGH [29:29] read-write GPIO15_LEVEL_LOW [28:28] read-write GPIO14_EDGE_HIGH [27:27] read-write GPIO14_EDGE_LOW [26:26] read-write GPIO14_LEVEL_HIGH [25:25] read-write GPIO14_LEVEL_LOW [24:24] read-write GPIO13_EDGE_HIGH [23:23] read-write GPIO13_EDGE_LOW [22:22] read-write GPIO13_LEVEL_HIGH [21:21] read-write GPIO13_LEVEL_LOW [20:20] read-write GPIO12_EDGE_HIGH [19:19] read-write GPIO12_EDGE_LOW [18:18] read-write GPIO12_LEVEL_HIGH [17:17] read-write GPIO12_LEVEL_LOW [16:16] read-write GPIO11_EDGE_HIGH [15:15] read-write GPIO11_EDGE_LOW [14:14] read-write GPIO11_LEVEL_HIGH [13:13] read-write GPIO11_LEVEL_LOW [12:12] read-write GPIO10_EDGE_HIGH [11:11] read-write GPIO10_EDGE_LOW [10:10] read-write GPIO10_LEVEL_HIGH [9:9] read-write GPIO10_LEVEL_LOW [8:8] read-write GPIO9_EDGE_HIGH [7:7] read-write GPIO9_EDGE_LOW [6:6] read-write GPIO9_LEVEL_HIGH [5:5] read-write GPIO9_LEVEL_LOW [4:4] read-write GPIO8_EDGE_HIGH [3:3] read-write GPIO8_EDGE_LOW [2:2] read-write GPIO8_LEVEL_HIGH [1:1] read-write GPIO8_LEVEL_LOW [0:0] read-write PROC1_INTF2 0x00000148 Interrupt Force for proc1 0x00000000 GPIO23_EDGE_HIGH [31:31] read-write GPIO23_EDGE_LOW [30:30] read-write GPIO23_LEVEL_HIGH [29:29] read-write GPIO23_LEVEL_LOW [28:28] read-write GPIO22_EDGE_HIGH [27:27] read-write GPIO22_EDGE_LOW [26:26] read-write GPIO22_LEVEL_HIGH [25:25] read-write GPIO22_LEVEL_LOW [24:24] read-write GPIO21_EDGE_HIGH [23:23] read-write GPIO21_EDGE_LOW [22:22] read-write GPIO21_LEVEL_HIGH [21:21] read-write GPIO21_LEVEL_LOW [20:20] read-write GPIO20_EDGE_HIGH [19:19] read-write GPIO20_EDGE_LOW [18:18] read-write GPIO20_LEVEL_HIGH [17:17] read-write GPIO20_LEVEL_LOW [16:16] read-write GPIO19_EDGE_HIGH [15:15] read-write GPIO19_EDGE_LOW [14:14] read-write GPIO19_LEVEL_HIGH [13:13] read-write GPIO19_LEVEL_LOW [12:12] read-write GPIO18_EDGE_HIGH [11:11] read-write GPIO18_EDGE_LOW [10:10] read-write GPIO18_LEVEL_HIGH [9:9] read-write GPIO18_LEVEL_LOW [8:8] read-write GPIO17_EDGE_HIGH [7:7] read-write GPIO17_EDGE_LOW [6:6] read-write GPIO17_LEVEL_HIGH [5:5] read-write GPIO17_LEVEL_LOW [4:4] read-write GPIO16_EDGE_HIGH [3:3] read-write GPIO16_EDGE_LOW [2:2] read-write GPIO16_LEVEL_HIGH [1:1] read-write GPIO16_LEVEL_LOW [0:0] read-write PROC1_INTF3 0x0000014c Interrupt Force for proc1 0x00000000 GPIO29_EDGE_HIGH [23:23] read-write GPIO29_EDGE_LOW [22:22] read-write GPIO29_LEVEL_HIGH [21:21] read-write GPIO29_LEVEL_LOW [20:20] read-write GPIO28_EDGE_HIGH [19:19] read-write GPIO28_EDGE_LOW [18:18] read-write GPIO28_LEVEL_HIGH [17:17] read-write GPIO28_LEVEL_LOW [16:16] read-write GPIO27_EDGE_HIGH [15:15] read-write GPIO27_EDGE_LOW [14:14] read-write GPIO27_LEVEL_HIGH [13:13] read-write GPIO27_LEVEL_LOW [12:12] read-write GPIO26_EDGE_HIGH [11:11] read-write GPIO26_EDGE_LOW [10:10] read-write GPIO26_LEVEL_HIGH [9:9] read-write GPIO26_LEVEL_LOW [8:8] read-write GPIO25_EDGE_HIGH [7:7] read-write GPIO25_EDGE_LOW [6:6] read-write GPIO25_LEVEL_HIGH [5:5] read-write GPIO25_LEVEL_LOW [4:4] read-write GPIO24_EDGE_HIGH [3:3] read-write GPIO24_EDGE_LOW [2:2] read-write GPIO24_LEVEL_HIGH [1:1] read-write GPIO24_LEVEL_LOW [0:0] read-write PROC1_INTS0 0x00000150 Interrupt status after masking & forcing for proc1 0x00000000 GPIO7_EDGE_HIGH [31:31] read-only GPIO7_EDGE_LOW [30:30] read-only GPIO7_LEVEL_HIGH [29:29] read-only GPIO7_LEVEL_LOW [28:28] read-only GPIO6_EDGE_HIGH [27:27] read-only GPIO6_EDGE_LOW [26:26] read-only GPIO6_LEVEL_HIGH [25:25] read-only GPIO6_LEVEL_LOW [24:24] read-only GPIO5_EDGE_HIGH [23:23] read-only GPIO5_EDGE_LOW [22:22] read-only GPIO5_LEVEL_HIGH [21:21] read-only GPIO5_LEVEL_LOW [20:20] read-only GPIO4_EDGE_HIGH [19:19] read-only GPIO4_EDGE_LOW [18:18] read-only GPIO4_LEVEL_HIGH [17:17] read-only GPIO4_LEVEL_LOW [16:16] read-only GPIO3_EDGE_HIGH [15:15] read-only GPIO3_EDGE_LOW [14:14] read-only GPIO3_LEVEL_HIGH [13:13] read-only GPIO3_LEVEL_LOW [12:12] read-only GPIO2_EDGE_HIGH [11:11] read-only GPIO2_EDGE_LOW [10:10] read-only GPIO2_LEVEL_HIGH [9:9] read-only GPIO2_LEVEL_LOW [8:8] read-only GPIO1_EDGE_HIGH [7:7] read-only GPIO1_EDGE_LOW [6:6] read-only GPIO1_LEVEL_HIGH [5:5] read-only GPIO1_LEVEL_LOW [4:4] read-only GPIO0_EDGE_HIGH [3:3] read-only GPIO0_EDGE_LOW [2:2] read-only GPIO0_LEVEL_HIGH [1:1] read-only GPIO0_LEVEL_LOW [0:0] read-only PROC1_INTS1 0x00000154 Interrupt status after masking & forcing for proc1 0x00000000 GPIO15_EDGE_HIGH [31:31] read-only GPIO15_EDGE_LOW [30:30] read-only GPIO15_LEVEL_HIGH [29:29] read-only GPIO15_LEVEL_LOW [28:28] read-only GPIO14_EDGE_HIGH [27:27] read-only GPIO14_EDGE_LOW [26:26] read-only GPIO14_LEVEL_HIGH [25:25] read-only GPIO14_LEVEL_LOW [24:24] read-only GPIO13_EDGE_HIGH [23:23] read-only GPIO13_EDGE_LOW [22:22] read-only GPIO13_LEVEL_HIGH [21:21] read-only GPIO13_LEVEL_LOW [20:20] read-only GPIO12_EDGE_HIGH [19:19] read-only GPIO12_EDGE_LOW [18:18] read-only GPIO12_LEVEL_HIGH [17:17] read-only GPIO12_LEVEL_LOW [16:16] read-only GPIO11_EDGE_HIGH [15:15] read-only GPIO11_EDGE_LOW [14:14] read-only GPIO11_LEVEL_HIGH [13:13] read-only GPIO11_LEVEL_LOW [12:12] read-only GPIO10_EDGE_HIGH [11:11] read-only GPIO10_EDGE_LOW [10:10] read-only GPIO10_LEVEL_HIGH [9:9] read-only GPIO10_LEVEL_LOW [8:8] read-only GPIO9_EDGE_HIGH [7:7] read-only GPIO9_EDGE_LOW [6:6] read-only GPIO9_LEVEL_HIGH [5:5] read-only GPIO9_LEVEL_LOW [4:4] read-only GPIO8_EDGE_HIGH [3:3] read-only GPIO8_EDGE_LOW [2:2] read-only GPIO8_LEVEL_HIGH [1:1] read-only GPIO8_LEVEL_LOW [0:0] read-only PROC1_INTS2 0x00000158 Interrupt status after masking & forcing for proc1 0x00000000 GPIO23_EDGE_HIGH [31:31] read-only GPIO23_EDGE_LOW [30:30] read-only GPIO23_LEVEL_HIGH [29:29] read-only GPIO23_LEVEL_LOW [28:28] read-only GPIO22_EDGE_HIGH [27:27] read-only GPIO22_EDGE_LOW [26:26] read-only GPIO22_LEVEL_HIGH [25:25] read-only GPIO22_LEVEL_LOW [24:24] read-only GPIO21_EDGE_HIGH [23:23] read-only GPIO21_EDGE_LOW [22:22] read-only GPIO21_LEVEL_HIGH [21:21] read-only GPIO21_LEVEL_LOW [20:20] read-only GPIO20_EDGE_HIGH [19:19] read-only GPIO20_EDGE_LOW [18:18] read-only GPIO20_LEVEL_HIGH [17:17] read-only GPIO20_LEVEL_LOW [16:16] read-only GPIO19_EDGE_HIGH [15:15] read-only GPIO19_EDGE_LOW [14:14] read-only GPIO19_LEVEL_HIGH [13:13] read-only GPIO19_LEVEL_LOW [12:12] read-only GPIO18_EDGE_HIGH [11:11] read-only GPIO18_EDGE_LOW [10:10] read-only GPIO18_LEVEL_HIGH [9:9] read-only GPIO18_LEVEL_LOW [8:8] read-only GPIO17_EDGE_HIGH [7:7] read-only GPIO17_EDGE_LOW [6:6] read-only GPIO17_LEVEL_HIGH [5:5] read-only GPIO17_LEVEL_LOW [4:4] read-only GPIO16_EDGE_HIGH [3:3] read-only GPIO16_EDGE_LOW [2:2] read-only GPIO16_LEVEL_HIGH [1:1] read-only GPIO16_LEVEL_LOW [0:0] read-only PROC1_INTS3 0x0000015c Interrupt status after masking & forcing for proc1 0x00000000 GPIO29_EDGE_HIGH [23:23] read-only GPIO29_EDGE_LOW [22:22] read-only GPIO29_LEVEL_HIGH [21:21] read-only GPIO29_LEVEL_LOW [20:20] read-only GPIO28_EDGE_HIGH [19:19] read-only GPIO28_EDGE_LOW [18:18] read-only GPIO28_LEVEL_HIGH [17:17] read-only GPIO28_LEVEL_LOW [16:16] read-only GPIO27_EDGE_HIGH [15:15] read-only GPIO27_EDGE_LOW [14:14] read-only GPIO27_LEVEL_HIGH [13:13] read-only GPIO27_LEVEL_LOW [12:12] read-only GPIO26_EDGE_HIGH [11:11] read-only GPIO26_EDGE_LOW [10:10] read-only GPIO26_LEVEL_HIGH [9:9] read-only GPIO26_LEVEL_LOW [8:8] read-only GPIO25_EDGE_HIGH [7:7] read-only GPIO25_EDGE_LOW [6:6] read-only GPIO25_LEVEL_HIGH [5:5] read-only GPIO25_LEVEL_LOW [4:4] read-only GPIO24_EDGE_HIGH [3:3] read-only GPIO24_EDGE_LOW [2:2] read-only GPIO24_LEVEL_HIGH [1:1] read-only GPIO24_LEVEL_LOW [0:0] read-only DORMANT_WAKE_INTE0 0x00000160 Interrupt Enable for dormant_wake 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTE1 0x00000164 Interrupt Enable for dormant_wake 0x00000000 GPIO15_EDGE_HIGH [31:31] read-write GPIO15_EDGE_LOW [30:30] read-write GPIO15_LEVEL_HIGH [29:29] read-write GPIO15_LEVEL_LOW [28:28] read-write GPIO14_EDGE_HIGH [27:27] read-write GPIO14_EDGE_LOW [26:26] read-write GPIO14_LEVEL_HIGH [25:25] read-write GPIO14_LEVEL_LOW [24:24] read-write GPIO13_EDGE_HIGH [23:23] read-write GPIO13_EDGE_LOW [22:22] read-write GPIO13_LEVEL_HIGH [21:21] read-write GPIO13_LEVEL_LOW [20:20] read-write GPIO12_EDGE_HIGH [19:19] read-write GPIO12_EDGE_LOW [18:18] read-write GPIO12_LEVEL_HIGH [17:17] read-write GPIO12_LEVEL_LOW [16:16] read-write GPIO11_EDGE_HIGH [15:15] read-write GPIO11_EDGE_LOW [14:14] read-write GPIO11_LEVEL_HIGH [13:13] read-write GPIO11_LEVEL_LOW [12:12] read-write GPIO10_EDGE_HIGH [11:11] read-write GPIO10_EDGE_LOW [10:10] read-write GPIO10_LEVEL_HIGH [9:9] read-write GPIO10_LEVEL_LOW [8:8] read-write GPIO9_EDGE_HIGH [7:7] read-write GPIO9_EDGE_LOW [6:6] read-write GPIO9_LEVEL_HIGH [5:5] read-write GPIO9_LEVEL_LOW [4:4] read-write GPIO8_EDGE_HIGH [3:3] read-write GPIO8_EDGE_LOW [2:2] read-write GPIO8_LEVEL_HIGH [1:1] read-write GPIO8_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTE2 0x00000168 Interrupt Enable for dormant_wake 0x00000000 GPIO23_EDGE_HIGH [31:31] read-write GPIO23_EDGE_LOW [30:30] read-write GPIO23_LEVEL_HIGH [29:29] read-write GPIO23_LEVEL_LOW [28:28] read-write GPIO22_EDGE_HIGH [27:27] read-write GPIO22_EDGE_LOW [26:26] read-write GPIO22_LEVEL_HIGH [25:25] read-write GPIO22_LEVEL_LOW [24:24] read-write GPIO21_EDGE_HIGH [23:23] read-write GPIO21_EDGE_LOW [22:22] read-write GPIO21_LEVEL_HIGH [21:21] read-write GPIO21_LEVEL_LOW [20:20] read-write GPIO20_EDGE_HIGH [19:19] read-write GPIO20_EDGE_LOW [18:18] read-write GPIO20_LEVEL_HIGH [17:17] read-write GPIO20_LEVEL_LOW [16:16] read-write GPIO19_EDGE_HIGH [15:15] read-write GPIO19_EDGE_LOW [14:14] read-write GPIO19_LEVEL_HIGH [13:13] read-write GPIO19_LEVEL_LOW [12:12] read-write GPIO18_EDGE_HIGH [11:11] read-write GPIO18_EDGE_LOW [10:10] read-write GPIO18_LEVEL_HIGH [9:9] read-write GPIO18_LEVEL_LOW [8:8] read-write GPIO17_EDGE_HIGH [7:7] read-write GPIO17_EDGE_LOW [6:6] read-write GPIO17_LEVEL_HIGH [5:5] read-write GPIO17_LEVEL_LOW [4:4] read-write GPIO16_EDGE_HIGH [3:3] read-write GPIO16_EDGE_LOW [2:2] read-write GPIO16_LEVEL_HIGH [1:1] read-write GPIO16_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTE3 0x0000016c Interrupt Enable for dormant_wake 0x00000000 GPIO29_EDGE_HIGH [23:23] read-write GPIO29_EDGE_LOW [22:22] read-write GPIO29_LEVEL_HIGH [21:21] read-write GPIO29_LEVEL_LOW [20:20] read-write GPIO28_EDGE_HIGH [19:19] read-write GPIO28_EDGE_LOW [18:18] read-write GPIO28_LEVEL_HIGH [17:17] read-write GPIO28_LEVEL_LOW [16:16] read-write GPIO27_EDGE_HIGH [15:15] read-write GPIO27_EDGE_LOW [14:14] read-write GPIO27_LEVEL_HIGH [13:13] read-write GPIO27_LEVEL_LOW [12:12] read-write GPIO26_EDGE_HIGH [11:11] read-write GPIO26_EDGE_LOW [10:10] read-write GPIO26_LEVEL_HIGH [9:9] read-write GPIO26_LEVEL_LOW [8:8] read-write GPIO25_EDGE_HIGH [7:7] read-write GPIO25_EDGE_LOW [6:6] read-write GPIO25_LEVEL_HIGH [5:5] read-write GPIO25_LEVEL_LOW [4:4] read-write GPIO24_EDGE_HIGH [3:3] read-write GPIO24_EDGE_LOW [2:2] read-write GPIO24_LEVEL_HIGH [1:1] read-write GPIO24_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTF0 0x00000170 Interrupt Force for dormant_wake 0x00000000 GPIO7_EDGE_HIGH [31:31] read-write GPIO7_EDGE_LOW [30:30] read-write GPIO7_LEVEL_HIGH [29:29] read-write GPIO7_LEVEL_LOW [28:28] read-write GPIO6_EDGE_HIGH [27:27] read-write GPIO6_EDGE_LOW [26:26] read-write GPIO6_LEVEL_HIGH [25:25] read-write GPIO6_LEVEL_LOW [24:24] read-write GPIO5_EDGE_HIGH [23:23] read-write GPIO5_EDGE_LOW [22:22] read-write GPIO5_LEVEL_HIGH [21:21] read-write GPIO5_LEVEL_LOW [20:20] read-write GPIO4_EDGE_HIGH [19:19] read-write GPIO4_EDGE_LOW [18:18] read-write GPIO4_LEVEL_HIGH [17:17] read-write GPIO4_LEVEL_LOW [16:16] read-write GPIO3_EDGE_HIGH [15:15] read-write GPIO3_EDGE_LOW [14:14] read-write GPIO3_LEVEL_HIGH [13:13] read-write GPIO3_LEVEL_LOW [12:12] read-write GPIO2_EDGE_HIGH [11:11] read-write GPIO2_EDGE_LOW [10:10] read-write GPIO2_LEVEL_HIGH [9:9] read-write GPIO2_LEVEL_LOW [8:8] read-write GPIO1_EDGE_HIGH [7:7] read-write GPIO1_EDGE_LOW [6:6] read-write GPIO1_LEVEL_HIGH [5:5] read-write GPIO1_LEVEL_LOW [4:4] read-write GPIO0_EDGE_HIGH [3:3] read-write GPIO0_EDGE_LOW [2:2] read-write GPIO0_LEVEL_HIGH [1:1] read-write GPIO0_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTF1 0x00000174 Interrupt Force for dormant_wake 0x00000000 GPIO15_EDGE_HIGH [31:31] read-write GPIO15_EDGE_LOW [30:30] read-write GPIO15_LEVEL_HIGH [29:29] read-write GPIO15_LEVEL_LOW [28:28] read-write GPIO14_EDGE_HIGH [27:27] read-write GPIO14_EDGE_LOW [26:26] read-write GPIO14_LEVEL_HIGH [25:25] read-write GPIO14_LEVEL_LOW [24:24] read-write GPIO13_EDGE_HIGH [23:23] read-write GPIO13_EDGE_LOW [22:22] read-write GPIO13_LEVEL_HIGH [21:21] read-write GPIO13_LEVEL_LOW [20:20] read-write GPIO12_EDGE_HIGH [19:19] read-write GPIO12_EDGE_LOW [18:18] read-write GPIO12_LEVEL_HIGH [17:17] read-write GPIO12_LEVEL_LOW [16:16] read-write GPIO11_EDGE_HIGH [15:15] read-write GPIO11_EDGE_LOW [14:14] read-write GPIO11_LEVEL_HIGH [13:13] read-write GPIO11_LEVEL_LOW [12:12] read-write GPIO10_EDGE_HIGH [11:11] read-write GPIO10_EDGE_LOW [10:10] read-write GPIO10_LEVEL_HIGH [9:9] read-write GPIO10_LEVEL_LOW [8:8] read-write GPIO9_EDGE_HIGH [7:7] read-write GPIO9_EDGE_LOW [6:6] read-write GPIO9_LEVEL_HIGH [5:5] read-write GPIO9_LEVEL_LOW [4:4] read-write GPIO8_EDGE_HIGH [3:3] read-write GPIO8_EDGE_LOW [2:2] read-write GPIO8_LEVEL_HIGH [1:1] read-write GPIO8_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTF2 0x00000178 Interrupt Force for dormant_wake 0x00000000 GPIO23_EDGE_HIGH [31:31] read-write GPIO23_EDGE_LOW [30:30] read-write GPIO23_LEVEL_HIGH [29:29] read-write GPIO23_LEVEL_LOW [28:28] read-write GPIO22_EDGE_HIGH [27:27] read-write GPIO22_EDGE_LOW [26:26] read-write GPIO22_LEVEL_HIGH [25:25] read-write GPIO22_LEVEL_LOW [24:24] read-write GPIO21_EDGE_HIGH [23:23] read-write GPIO21_EDGE_LOW [22:22] read-write GPIO21_LEVEL_HIGH [21:21] read-write GPIO21_LEVEL_LOW [20:20] read-write GPIO20_EDGE_HIGH [19:19] read-write GPIO20_EDGE_LOW [18:18] read-write GPIO20_LEVEL_HIGH [17:17] read-write GPIO20_LEVEL_LOW [16:16] read-write GPIO19_EDGE_HIGH [15:15] read-write GPIO19_EDGE_LOW [14:14] read-write GPIO19_LEVEL_HIGH [13:13] read-write GPIO19_LEVEL_LOW [12:12] read-write GPIO18_EDGE_HIGH [11:11] read-write GPIO18_EDGE_LOW [10:10] read-write GPIO18_LEVEL_HIGH [9:9] read-write GPIO18_LEVEL_LOW [8:8] read-write GPIO17_EDGE_HIGH [7:7] read-write GPIO17_EDGE_LOW [6:6] read-write GPIO17_LEVEL_HIGH [5:5] read-write GPIO17_LEVEL_LOW [4:4] read-write GPIO16_EDGE_HIGH [3:3] read-write GPIO16_EDGE_LOW [2:2] read-write GPIO16_LEVEL_HIGH [1:1] read-write GPIO16_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTF3 0x0000017c Interrupt Force for dormant_wake 0x00000000 GPIO29_EDGE_HIGH [23:23] read-write GPIO29_EDGE_LOW [22:22] read-write GPIO29_LEVEL_HIGH [21:21] read-write GPIO29_LEVEL_LOW [20:20] read-write GPIO28_EDGE_HIGH [19:19] read-write GPIO28_EDGE_LOW [18:18] read-write GPIO28_LEVEL_HIGH [17:17] read-write GPIO28_LEVEL_LOW [16:16] read-write GPIO27_EDGE_HIGH [15:15] read-write GPIO27_EDGE_LOW [14:14] read-write GPIO27_LEVEL_HIGH [13:13] read-write GPIO27_LEVEL_LOW [12:12] read-write GPIO26_EDGE_HIGH [11:11] read-write GPIO26_EDGE_LOW [10:10] read-write GPIO26_LEVEL_HIGH [9:9] read-write GPIO26_LEVEL_LOW [8:8] read-write GPIO25_EDGE_HIGH [7:7] read-write GPIO25_EDGE_LOW [6:6] read-write GPIO25_LEVEL_HIGH [5:5] read-write GPIO25_LEVEL_LOW [4:4] read-write GPIO24_EDGE_HIGH [3:3] read-write GPIO24_EDGE_LOW [2:2] read-write GPIO24_LEVEL_HIGH [1:1] read-write GPIO24_LEVEL_LOW [0:0] read-write DORMANT_WAKE_INTS0 0x00000180 Interrupt status after masking & forcing for dormant_wake 0x00000000 GPIO7_EDGE_HIGH [31:31] read-only GPIO7_EDGE_LOW [30:30] read-only GPIO7_LEVEL_HIGH [29:29] read-only GPIO7_LEVEL_LOW [28:28] read-only GPIO6_EDGE_HIGH [27:27] read-only GPIO6_EDGE_LOW [26:26] read-only GPIO6_LEVEL_HIGH [25:25] read-only GPIO6_LEVEL_LOW [24:24] read-only GPIO5_EDGE_HIGH [23:23] read-only GPIO5_EDGE_LOW [22:22] read-only GPIO5_LEVEL_HIGH [21:21] read-only GPIO5_LEVEL_LOW [20:20] read-only GPIO4_EDGE_HIGH [19:19] read-only GPIO4_EDGE_LOW [18:18] read-only GPIO4_LEVEL_HIGH [17:17] read-only GPIO4_LEVEL_LOW [16:16] read-only GPIO3_EDGE_HIGH [15:15] read-only GPIO3_EDGE_LOW [14:14] read-only GPIO3_LEVEL_HIGH [13:13] read-only GPIO3_LEVEL_LOW [12:12] read-only GPIO2_EDGE_HIGH [11:11] read-only GPIO2_EDGE_LOW [10:10] read-only GPIO2_LEVEL_HIGH [9:9] read-only GPIO2_LEVEL_LOW [8:8] read-only GPIO1_EDGE_HIGH [7:7] read-only GPIO1_EDGE_LOW [6:6] read-only GPIO1_LEVEL_HIGH [5:5] read-only GPIO1_LEVEL_LOW [4:4] read-only GPIO0_EDGE_HIGH [3:3] read-only GPIO0_EDGE_LOW [2:2] read-only GPIO0_LEVEL_HIGH [1:1] read-only GPIO0_LEVEL_LOW [0:0] read-only DORMANT_WAKE_INTS1 0x00000184 Interrupt status after masking & forcing for dormant_wake 0x00000000 GPIO15_EDGE_HIGH [31:31] read-only GPIO15_EDGE_LOW [30:30] read-only GPIO15_LEVEL_HIGH [29:29] read-only GPIO15_LEVEL_LOW [28:28] read-only GPIO14_EDGE_HIGH [27:27] read-only GPIO14_EDGE_LOW [26:26] read-only GPIO14_LEVEL_HIGH [25:25] read-only GPIO14_LEVEL_LOW [24:24] read-only GPIO13_EDGE_HIGH [23:23] read-only GPIO13_EDGE_LOW [22:22] read-only GPIO13_LEVEL_HIGH [21:21] read-only GPIO13_LEVEL_LOW [20:20] read-only GPIO12_EDGE_HIGH [19:19] read-only GPIO12_EDGE_LOW [18:18] read-only GPIO12_LEVEL_HIGH [17:17] read-only GPIO12_LEVEL_LOW [16:16] read-only GPIO11_EDGE_HIGH [15:15] read-only GPIO11_EDGE_LOW [14:14] read-only GPIO11_LEVEL_HIGH [13:13] read-only GPIO11_LEVEL_LOW [12:12] read-only GPIO10_EDGE_HIGH [11:11] read-only GPIO10_EDGE_LOW [10:10] read-only GPIO10_LEVEL_HIGH [9:9] read-only GPIO10_LEVEL_LOW [8:8] read-only GPIO9_EDGE_HIGH [7:7] read-only GPIO9_EDGE_LOW [6:6] read-only GPIO9_LEVEL_HIGH [5:5] read-only GPIO9_LEVEL_LOW [4:4] read-only GPIO8_EDGE_HIGH [3:3] read-only GPIO8_EDGE_LOW [2:2] read-only GPIO8_LEVEL_HIGH [1:1] read-only GPIO8_LEVEL_LOW [0:0] read-only DORMANT_WAKE_INTS2 0x00000188 Interrupt status after masking & forcing for dormant_wake 0x00000000 GPIO23_EDGE_HIGH [31:31] read-only GPIO23_EDGE_LOW [30:30] read-only GPIO23_LEVEL_HIGH [29:29] read-only GPIO23_LEVEL_LOW [28:28] read-only GPIO22_EDGE_HIGH [27:27] read-only GPIO22_EDGE_LOW [26:26] read-only GPIO22_LEVEL_HIGH [25:25] read-only GPIO22_LEVEL_LOW [24:24] read-only GPIO21_EDGE_HIGH [23:23] read-only GPIO21_EDGE_LOW [22:22] read-only GPIO21_LEVEL_HIGH [21:21] read-only GPIO21_LEVEL_LOW [20:20] read-only GPIO20_EDGE_HIGH [19:19] read-only GPIO20_EDGE_LOW [18:18] read-only GPIO20_LEVEL_HIGH [17:17] read-only GPIO20_LEVEL_LOW [16:16] read-only GPIO19_EDGE_HIGH [15:15] read-only GPIO19_EDGE_LOW [14:14] read-only GPIO19_LEVEL_HIGH [13:13] read-only GPIO19_LEVEL_LOW [12:12] read-only GPIO18_EDGE_HIGH [11:11] read-only GPIO18_EDGE_LOW [10:10] read-only GPIO18_LEVEL_HIGH [9:9] read-only GPIO18_LEVEL_LOW [8:8] read-only GPIO17_EDGE_HIGH [7:7] read-only GPIO17_EDGE_LOW [6:6] read-only GPIO17_LEVEL_HIGH [5:5] read-only GPIO17_LEVEL_LOW [4:4] read-only GPIO16_EDGE_HIGH [3:3] read-only GPIO16_EDGE_LOW [2:2] read-only GPIO16_LEVEL_HIGH [1:1] read-only GPIO16_LEVEL_LOW [0:0] read-only DORMANT_WAKE_INTS3 0x0000018c Interrupt status after masking & forcing for dormant_wake 0x00000000 GPIO29_EDGE_HIGH [23:23] read-only GPIO29_EDGE_LOW [22:22] read-only GPIO29_LEVEL_HIGH [21:21] read-only GPIO29_LEVEL_LOW [20:20] read-only GPIO28_EDGE_HIGH [19:19] read-only GPIO28_EDGE_LOW [18:18] read-only GPIO28_LEVEL_HIGH [17:17] read-only GPIO28_LEVEL_LOW [16:16] read-only GPIO27_EDGE_HIGH [15:15] read-only GPIO27_EDGE_LOW [14:14] read-only GPIO27_LEVEL_HIGH [13:13] read-only GPIO27_LEVEL_LOW [12:12] read-only GPIO26_EDGE_HIGH [11:11] read-only GPIO26_EDGE_LOW [10:10] read-only GPIO26_LEVEL_HIGH [9:9] read-only GPIO26_LEVEL_LOW [8:8] read-only GPIO25_EDGE_HIGH [7:7] read-only GPIO25_EDGE_LOW [6:6] read-only GPIO25_LEVEL_HIGH [5:5] read-only GPIO25_LEVEL_LOW [4:4] read-only GPIO24_EDGE_HIGH [3:3] read-only GPIO24_EDGE_LOW [2:2] read-only GPIO24_LEVEL_HIGH [1:1] read-only GPIO24_LEVEL_LOW [0:0] read-only SYSINFO 0x40000000 0 20 registers CHIP_ID 0x00000000 JEDEC JEP-106 compliant chip identifier. 0x00000000 REVISION [31:28] read-only PART [27:12] read-only MANUFACTURER [11:0] read-only PLATFORM 0x00000004 Platform register. Allows software to know what environment it is running in. 0x00000000 ASIC [1:1] read-only FPGA [0:0] read-only GITREF_RP2040 0x00000010 Git hash of the chip source. Used to identify chip version. 0x00000000 GITREF_RP2040 [31:0] read-only PPB 0xe0000000 0 60836 registers SYST_CSR 0x0000e010 Use the SysTick Control and Status Register to enable the SysTick features. 0x00000000 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger. [16:16] read-only CLKSOURCE SysTick clock source. Always reads as one if SYST_CALIB reports NOREF. Selects the SysTick timer clock source: 0 = External reference clock. 1 = Processor clock. [2:2] read-write TICKINT Enables SysTick exception request: 0 = Counting down to zero does not assert the SysTick exception request. 1 = Counting down to zero to asserts the SysTick exception request. [1:1] read-write ENABLE Enable SysTick counter: 0 = Counter disabled. 1 = Counter enabled. [0:0] read-write SYST_RVR 0x0000e014 Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN. To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99. 0x00000000 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0. [23:0] read-write SYST_CVR 0x0000e018 Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN. 0x00000000 CURRENT Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. [23:0] read-write SYST_CALIB 0x0000e01c Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. 0x00000000 NOREF If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0. [31:31] read-only SKEW If reads as 1, the calibration value for 10ms is inexact (due to clock frequency). [30:30] read-only TENMS An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known. [23:0] read-only NVIC_ISER 0x0000e100 Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. 0x00000000 SETENA Interrupt set-enable bits. Write: 0 = No effect. 1 = Enable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled. [31:0] read-write NVIC_ICER 0x0000e180 Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled. 0x00000000 CLRENA Interrupt clear-enable bits. Write: 0 = No effect. 1 = Disable interrupt. Read: 0 = Interrupt disabled. 1 = Interrupt enabled. [31:0] read-write NVIC_ISPR 0x0000e200 The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending. 0x00000000 SETPEND Interrupt set-pending bits. Write: 0 = No effect. 1 = Changes interrupt state to pending. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: An interrupt that is pending has no effect. A disabled interrupt sets the state of that interrupt to pending. [31:0] read-write NVIC_ICPR 0x0000e280 Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending. 0x00000000 CLRPEND Interrupt clear-pending bits. Write: 0 = No effect. 1 = Removes pending state and interrupt. Read: 0 = Interrupt is not pending. 1 = Interrupt is pending. [31:0] read-write NVIC_IPR0 0x0000e400 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt. These registers are only word-accessible 0x00000000 IP_3 Priority of interrupt 3 [31:30] read-write IP_2 Priority of interrupt 2 [23:22] read-write IP_1 Priority of interrupt 1 [15:14] read-write IP_0 Priority of interrupt 0 [7:6] read-write NVIC_IPR1 0x0000e404 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. 0x00000000 IP_7 Priority of interrupt 7 [31:30] read-write IP_6 Priority of interrupt 6 [23:22] read-write IP_5 Priority of interrupt 5 [15:14] read-write IP_4 Priority of interrupt 4 [7:6] read-write NVIC_IPR2 0x0000e408 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. 0x00000000 IP_11 Priority of interrupt 11 [31:30] read-write IP_10 Priority of interrupt 10 [23:22] read-write IP_9 Priority of interrupt 9 [15:14] read-write IP_8 Priority of interrupt 8 [7:6] read-write NVIC_IPR3 0x0000e40c Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. 0x00000000 IP_15 Priority of interrupt 15 [31:30] read-write IP_14 Priority of interrupt 14 [23:22] read-write IP_13 Priority of interrupt 13 [15:14] read-write IP_12 Priority of interrupt 12 [7:6] read-write NVIC_IPR4 0x0000e410 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. 0x00000000 IP_19 Priority of interrupt 19 [31:30] read-write IP_18 Priority of interrupt 18 [23:22] read-write IP_17 Priority of interrupt 17 [15:14] read-write IP_16 Priority of interrupt 16 [7:6] read-write NVIC_IPR5 0x0000e414 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. 0x00000000 IP_23 Priority of interrupt 23 [31:30] read-write IP_22 Priority of interrupt 22 [23:22] read-write IP_21 Priority of interrupt 21 [15:14] read-write IP_20 Priority of interrupt 20 [7:6] read-write NVIC_IPR6 0x0000e418 Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. 0x00000000 IP_27 Priority of interrupt 27 [31:30] read-write IP_26 Priority of interrupt 26 [23:22] read-write IP_25 Priority of interrupt 25 [15:14] read-write IP_24 Priority of interrupt 24 [7:6] read-write NVIC_IPR7 0x0000e41c Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest. 0x00000000 IP_31 Priority of interrupt 31 [31:30] read-write IP_30 Priority of interrupt 30 [23:22] read-write IP_29 Priority of interrupt 29 [15:14] read-write IP_28 Priority of interrupt 28 [7:6] read-write CPUID 0x0000ed00 Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. 0x410cc601 IMPLEMENTER Implementor code: 0x41 = ARM [31:24] read-only VARIANT Major revision number n in the rnpm revision status: 0x0 = Revision 0. [23:20] read-only ARCHITECTURE Constant that defines the architecture of the processor: 0xC = ARMv6-M architecture. [19:16] read-only PARTNO Number of processor within family: 0xC60 = Cortex-M0+ [15:4] read-only REVISION Minor revision number m in the rnpm revision status: 0x1 = Patch 1. [3:0] read-only ICSR 0x0000ed04 Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. 0x00000000 NMIPENDSET Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered. NMI set-pending bit. Write: 0 = No effect. 1 = Changes NMI exception state to pending. Read: 0 = NMI exception is not pending. 1 = NMI exception is pending. Because NMI is the highest-priority exception, normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the NMI signal is reasserted while the processor is executing that handler. [31:31] read-write PENDSVSET PendSV set-pending bit. Write: 0 = No effect. 1 = Changes PendSV exception state to pending. Read: 0 = PendSV exception is not pending. 1 = PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending. [28:28] read-write PENDSVCLR PendSV clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the PendSV exception. [27:27] read-write PENDSTSET SysTick exception set-pending bit. Write: 0 = No effect. 1 = Changes SysTick exception state to pending. Read: 0 = SysTick exception is not pending. 1 = SysTick exception is pending. [26:26] read-write PENDSTCLR SysTick exception clear-pending bit. Write: 0 = No effect. 1 = Removes the pending state from the SysTick exception. This bit is WO. On a register read its value is Unknown. [25:25] read-write ISRPREEMPT The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. [23:23] read-only ISRPENDING External interrupt pending flag [22:22] read-only VECTPENDING Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. [20:12] read-only VECTACTIVE Active exception number field. Reset clears the VECTACTIVE field. [8:0] read-only VTOR 0x0000ed08 The VTOR holds the vector table offset address. 0x00000000 TBLOFF Bits [31:8] of the indicate the vector table offset address. [31:8] read-write AIRCR 0x0000ed0c Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset. 0x00000000 VECTKEY Register key: Reads as Unknown On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. [31:16] read-write ENDIANESS Data endianness implemented: 0 = Little-endian. [15:15] read-only SYSRESETREQ Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device. [2:2] read-write VECTCLRACTIVE Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. [1:1] read-write SCR 0x0000ed10 System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. 0x00000000 SEVONPEND Send Event on Pending bit: 0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded. 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor. When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE. The processor also wakes up on execution of an SEV instruction or an external event. [4:4] read-write SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode: 0 = Sleep. 1 = Deep sleep. [2:2] read-write SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0 = Do not sleep when returning to Thread mode. 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application. [1:1] read-write CCR 0x0000ed14 The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault. 0x00000000 STKALIGN Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment. [9:9] read-only UNALIGN_TRP Always reads as one, indicates that all unaligned accesses generate a HardFault. [3:3] read-only SHPR2 0x0000ed1c System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall. 0x00000000 PRI_11 Priority of system handler 11, SVCall [31:30] read-write SHPR3 0x0000ed20 System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick. 0x00000000 PRI_15 Priority of system handler 15, SysTick [31:30] read-write PRI_14 Priority of system handler 14, PendSV [23:22] read-write SHCSR 0x0000ed24 Use the System Handler Control and State Register to determine or clear the pending status of SVCall. 0x00000000 SVCALLPENDED Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall. [15:15] read-write MPU_TYPE 0x0000ed90 Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports. 0x00000800 IREGION Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. [23:16] read-only DREGION Number of regions supported by the MPU. [15:8] read-only SEPARATE Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU. [0:0] read-only MPU_CTRL 0x0000ed94 Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs. 0x00000000 PRIVDEFENA Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear. 0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. 1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map. [2:2] read-write HFNMIENA Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour. When the MPU is enabled: 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit. 1 = the MPU is enabled during HardFault and NMI handlers. [1:1] read-write ENABLE Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map. 0 = MPU disabled. 1 = MPU enabled. [0:0] read-write MPU_RNR 0x0000ed98 Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR. 0x00000000 REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7. [3:0] read-write MPU_RBAR 0x0000ed9c Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated. 0x00000000 ADDR Base address of the region. [31:8] read-write VALID On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region. Write: 0 = MPU_RNR not changed, and the processor: Updates the base address for the region specified in the MPU_RNR. Ignores the value of the REGION field. 1 = The processor: Updates the value of the MPU_RNR to the value of the REGION field. Updates the base address for the region specified in the REGION field. Always reads as zero. [4:4] read-write REGION On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. [3:0] read-write MPU_RASR 0x0000eda0 Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region. 0x00000000 ATTRS The MPU Region Attribute field. Use to define the region attribute control. 28 = XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. 26:24 = AP: Access permission field 18 = S: Shareable bit 17 = C: Cacheable bit 16 = B: Bufferable bit [31:16] read-write SRD Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled. [15:8] read-write SIZE Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes [5:1] read-write ENABLE Enables the region. [0:0] read-write SSI DW_apb_ssi has the following features: * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation. * APB3 and APB4 protocol support. * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits. * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices. * Programmable Dual/Quad/Octal SPI support in Master Mode. * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation. * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes. * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes. * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests. * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently. * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus. * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains. * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates. * Programmable features: - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire. - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation. - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer. * Configured features: - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits. - 1 slave select output. - Hardware slave-select – Dedicated hardware slave-select line. - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller. - Interrupt polarity – active high interrupt lines. - Serial clock polarity – low serial-clock polarity directly after reset. - Serial clock phase – capture on first edge of serial-clock directly after reset. 0x18000000 0 252 registers CTRLR0 0x00000000 Control register 0 0x00000000 SSTE Slave select toggle enable [24:24] read-write SPI_FRF SPI frame format [22:21] read-write STD 0 Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex DUAL 1 Dual-SPI frame format; two bits per SCK, half-duplex QUAD 2 Quad-SPI frame format; four bits per SCK, half-duplex DFS_32 Data frame size in 32b transfer mode Value of n -> n+1 clocks per frame. [20:16] read-write CFS Control frame size Value of n -> n+1 clocks per frame. [15:12] read-write SRL Shift register loop (test mode) [11:11] read-write SLV_OE Slave output enable [10:10] read-write TMOD Transfer mode [9:8] read-write TX_AND_RX 0 Both transmit and receive TX_ONLY 1 Transmit only (not for FRF == 0, standard SPI mode) RX_ONLY 2 Receive only (not for FRF == 0, standard SPI mode) EEPROM_READ 3 EEPROM read mode (TX then RX; RX starts after control data TX'd) SCPOL Serial clock polarity [7:7] read-write SCPH Serial clock phase [6:6] read-write FRF Frame format [5:4] read-write DFS Data frame size [3:0] read-write CTRLR1 0x00000004 Master Control register 1 0x00000000 NDF Number of data frames [15:0] read-write SSIENR 0x00000008 SSI Enable 0x00000000 SSI_EN SSI enable [0:0] read-write MWCR 0x0000000c Microwire Control 0x00000000 MHS Microwire handshaking [2:2] read-write MDD Microwire control [1:1] read-write MWMOD Microwire transfer mode [0:0] read-write SER 0x00000010 Slave enable 0x00000000 SER For each bit: 0 -> slave not selected 1 -> slave selected [0:0] read-write BAUDR 0x00000014 Baud rate 0x00000000 SCKDV SSI clock divider [15:0] read-write TXFTLR 0x00000018 TX FIFO threshold level 0x00000000 TFT Transmit FIFO threshold [7:0] read-write RXFTLR 0x0000001c RX FIFO threshold level 0x00000000 RFT Receive FIFO threshold [7:0] read-write TXFLR 0x00000020 TX FIFO level 0x00000000 TFTFL Transmit FIFO level [7:0] read-only RXFLR 0x00000024 RX FIFO level 0x00000000 RXTFL Receive FIFO level [7:0] read-only SR 0x00000028 Status register 0x00000000 DCOL Data collision error [6:6] read-only TXE Transmission error [5:5] read-only RFF Receive FIFO full [4:4] read-only RFNE Receive FIFO not empty [3:3] read-only TFE Transmit FIFO empty [2:2] read-only TFNF Transmit FIFO not full [1:1] read-only BUSY SSI busy flag [0:0] read-only IMR 0x0000002c Interrupt mask 0x00000000 MSTIM Multi-master contention interrupt mask [5:5] read-write RXFIM Receive FIFO full interrupt mask [4:4] read-write RXOIM Receive FIFO overflow interrupt mask [3:3] read-write RXUIM Receive FIFO underflow interrupt mask [2:2] read-write TXOIM Transmit FIFO overflow interrupt mask [1:1] read-write TXEIM Transmit FIFO empty interrupt mask [0:0] read-write ISR 0x00000030 Interrupt status 0x00000000 MSTIS Multi-master contention interrupt status [5:5] read-only RXFIS Receive FIFO full interrupt status [4:4] read-only RXOIS Receive FIFO overflow interrupt status [3:3] read-only RXUIS Receive FIFO underflow interrupt status [2:2] read-only TXOIS Transmit FIFO overflow interrupt status [1:1] read-only TXEIS Transmit FIFO empty interrupt status [0:0] read-only RISR 0x00000034 Raw interrupt status 0x00000000 MSTIR Multi-master contention raw interrupt status [5:5] read-only RXFIR Receive FIFO full raw interrupt status [4:4] read-only RXOIR Receive FIFO overflow raw interrupt status [3:3] read-only RXUIR Receive FIFO underflow raw interrupt status [2:2] read-only TXOIR Transmit FIFO overflow raw interrupt status [1:1] read-only TXEIR Transmit FIFO empty raw interrupt status [0:0] read-only TXOICR 0x00000038 TX FIFO overflow interrupt clear 0x00000000 TXOICR Clear-on-read transmit FIFO overflow interrupt [0:0] read-only RXOICR 0x0000003c RX FIFO overflow interrupt clear 0x00000000 RXOICR Clear-on-read receive FIFO overflow interrupt [0:0] read-only RXUICR 0x00000040 RX FIFO underflow interrupt clear 0x00000000 RXUICR Clear-on-read receive FIFO underflow interrupt [0:0] read-only MSTICR 0x00000044 Multi-master interrupt clear 0x00000000 MSTICR Clear-on-read multi-master contention interrupt [0:0] read-only ICR 0x00000048 Interrupt clear 0x00000000 ICR Clear-on-read all active interrupts [0:0] read-only DMACR 0x0000004c DMA control 0x00000000 TDMAE Transmit DMA enable [1:1] read-write RDMAE Receive DMA enable [0:0] read-write DMATDLR 0x00000050 DMA TX data level 0x00000000 DMATDL Transmit data watermark level [7:0] read-write DMARDLR 0x00000054 DMA RX data level 0x00000000 DMARDL Receive data watermark level (DMARDLR+1) [7:0] read-write IDR 0x00000058 Identification register 0x51535049 IDCODE Peripheral dentification code [31:0] read-only SSI_VERSION_ID 0x0000005c Version ID 0x3430312a SSI_COMP_VERSION SNPS component version (format X.YY) [31:0] read-only DR0 0x00000060 Data Register 0 (of 36) 0x00000000 DR First data register of 36 [31:0] read-write RX_SAMPLE_DLY 0x000000f0 RX sample delay 0x00000000 RSD RXD sample delay (in SCLK cycles) [7:0] read-write SPI_CTRLR0 0x000000f4 SPI control 0x03000000 XIP_CMD SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit) [31:24] read-write SPI_RXDS_EN Read data strobe enable [18:18] read-write INST_DDR_EN Instruction DDR transfer enable [17:17] read-write SPI_DDR_EN SPI DDR transfer enable [16:16] read-write WAIT_CYCLES Wait cycles between control frame transmit and data reception (in SCLK cycles) [15:11] read-write INST_L Instruction length (0/4/8/16b) [9:8] read-write NONE 0 No instruction 4B 1 4-bit instruction 8B 2 8-bit instruction 16B 3 16-bit instruction ADDR_L Address length (0b-60b in 4b increments) [5:2] read-write TRANS_TYPE Address and instruction transfer format [1:0] read-write 1C1A 0 Command and address both in standard SPI frame format 1C2A 1 Command in standard SPI format, address in format specified by FRF 2C2A 2 Command and address both in format specified by FRF (e.g. Dual-SPI) TXD_DRIVE_EDGE 0x000000f8 TX drive edge 0x00000000 TDE TXD drive edge [7:0] read-write XIP_CTRL QSPI flash execute-in-place block 0x14000000 0 32 registers XIP_IRQ 6 CTRL 0x00000000 Cache control 0x00000003 POWER_DOWN When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down. [3:3] read-write ERR_BADWRITE When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual. [1:1] read-write EN When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response. [0:0] read-write FLUSH 0x00000004 Cache Flush control 0x00000000 FLUSH Write 1 to flush the cache. This clears the tag memory, but the data memory retains its contents. (This means cache-as-SRAM contents is not affected by flush or reset.) Reading will hold the bus (stall the processor) until the flush completes. Alternatively STAT can be polled until completion. [0:0] write-only STAT 0x00000008 Cache Status 0x00000002 FIFO_FULL When 1, indicates the XIP streaming FIFO is completely full. The streaming FIFO is 2 entries deep, so the full and empty flag allow its level to be ascertained. [2:2] read-only FIFO_EMPTY When 1, indicates the XIP streaming FIFO is completely empty. [1:1] read-only FLUSH_READY Reads as 0 while a cache flush is in progress, and 1 otherwise. The cache is flushed whenever the XIP block is reset, and also when requested via the FLUSH register. [0:0] read-only CTR_HIT 0x0000000c Cache Hit counter 0x00000000 CTR_HIT A 32 bit saturating counter that increments upon each cache hit, i.e. when an XIP access is serviced directly from cached data. Write any value to clear. [31:0] read-write oneToClear CTR_ACC 0x00000010 Cache Access counter 0x00000000 CTR_ACC A 32 bit saturating counter that increments upon each XIP access, whether the cache is hit or not. This includes noncacheable accesses. Write any value to clear. [31:0] read-write oneToClear STREAM_ADDR 0x00000014 FIFO stream address 0x00000000 STREAM_ADDR The address of the next word to be streamed from flash to the streaming FIFO. Increments automatically after each flash access. Write the initial access address here before starting a streaming read. [31:2] read-write STREAM_CTR 0x00000018 FIFO stream control 0x00000000 STREAM_CTR Write a nonzero value to start a streaming read. This will then progress in the background, using flash idle cycles to transfer a linear data block from flash to the streaming FIFO. Decrements automatically (1 at a time) as the stream progresses, and halts on reaching 0. Write 0 to halt an in-progress stream, and discard any in-flight read, so that a new stream can immediately be started (after draining the FIFO and reinitialising STREAM_ADDR) [21:0] read-write STREAM_FIFO 0x0000001c FIFO stream data 0x00000000 STREAM_FIFO Streamed data is buffered here, for retrieval by the system DMA. This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing the DMA to bus stalls caused by other XIP traffic. [31:0] read-only modify SYSCFG Register block for various chip control signals 0x40004000 0 28 registers PROC0_NMI_MASK 0x00000000 Processor core 0 NMI source mask 0x00000000 PROC0_NMI_MASK Set a bit high to enable NMI from that IRQ [31:0] read-write PROC1_NMI_MASK 0x00000004 Processor core 1 NMI source mask 0x00000000 PROC1_NMI_MASK Set a bit high to enable NMI from that IRQ [31:0] read-write PROC_CONFIG 0x00000008 Configuration for processors 0x10000000 PROC1_DAP_INSTID Configure proc1 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP [31:28] read-write PROC0_DAP_INSTID Configure proc0 DAP instance ID. Recommend that this is NOT changed until you require debug access in multi-chip environment WARNING: do not set to 15 as this is reserved for RescueDP [27:24] read-write PROC1_HALTED Indication that proc1 has halted [1:1] read-only PROC0_HALTED Indication that proc0 has halted [0:0] read-only PROC_IN_SYNC_BYPASS 0x0000000c For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...29. 0x00000000 PROC_IN_SYNC_BYPASS [29:0] read-write PROC_IN_SYNC_BYPASS_HI 0x00000010 For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30...35 (the QSPI IOs). 0x00000000 PROC_IN_SYNC_BYPASS_HI [5:0] read-write DBGFORCE 0x00000014 Directly control the SWD debug port of either processor 0x00000066 PROC1_ATTACH Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads. [7:7] read-write PROC1_SWCLK Directly drive processor 1 SWCLK, if PROC1_ATTACH is set [6:6] read-write PROC1_SWDI Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set [5:5] read-write PROC1_SWDO Observe the value of processor 1 SWDIO output. [4:4] read-only PROC0_ATTACH Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads. [3:3] read-write PROC0_SWCLK Directly drive processor 0 SWCLK, if PROC0_ATTACH is set [2:2] read-write PROC0_SWDI Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set [1:1] read-write PROC0_SWDO Observe the value of processor 0 SWDIO output. [0:0] read-only MEMPOWERDOWN 0x00000018 Control power downs to memories. Set high to power down memories. Use with extreme caution 0x00000000 ROM [7:7] read-write USB [6:6] read-write SRAM5 [5:5] read-write SRAM4 [4:4] read-write SRAM3 [3:3] read-write SRAM2 [2:2] read-write SRAM1 [1:1] read-write SRAM0 [0:0] read-write XOSC Controls the crystal oscillator 0x40024000 0 32 registers CTRL 0x00000000 Crystal Oscillator Control 0x00000000 ENABLE On power-up this field is initialised to DISABLE and the chip runs from the ROSC. If the chip has subsequently been programmed to run from the XOSC then DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature. The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. [23:12] read-write DISABLE 3358 ENABLE 4011 FREQ_RANGE Frequency range. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE. This resets to 0xAA0 and cannot be changed. [11:0] read-write 1_15MHZ 2720 RESERVED_1 2721 RESERVED_2 2722 RESERVED_3 2723 STATUS 0x00000004 Crystal Oscillator Status 0x00000000 STABLE Oscillator is running and stable [31:31] read-only BADWRITE An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT [24:24] read-write oneToClear ENABLED Oscillator is enabled but not necessarily running and stable, resets to 0 [12:12] read-only FREQ_RANGE The current frequency range setting, always reads 0 [1:0] read-only 1_15MHZ 0 RESERVED_1 1 RESERVED_2 2 RESERVED_3 3 DORMANT 0x00000008 Crystal Oscillator pause control 0x00000000 DORMANT This is used to save power by pausing the XOSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: stop the PLLs before selecting dormant mode Warning: setup the irq before selecting dormant mode [31:0] read-write dormant 1668246881 WAKE 2002873189 STARTUP 0x0000000c Controls the startup delay 0x00000000 X4 Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly. [20:20] read-write DELAY in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles. [13:0] read-write COUNT 0x0000001c A down counter running at the xosc frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. 0x00000000 COUNT [7:0] read-write PLL_SYS 0x40028000 0 16 registers CS 0x00000000 Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz 0x00000001 LOCK PLL is locked [31:31] read-only BYPASS Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so. [8:8] read-write REFDIV Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it. [5:0] read-write PWR 0x00000004 Controls the PLL power modes. 0x0000002d VCOPD PLL VCO powerdown To save power set high when PLL output not required or bypass=1. [5:5] read-write POSTDIVPD PLL post divider powerdown To save power set high when PLL output not required or bypass=1. [3:3] read-write DSMPD PLL DSM powerdown Nothing is achieved by setting this low. [2:2] read-write PD PLL powerdown To save power set high when PLL output not required. [0:0] read-write FBDIV_INT 0x00000008 Feedback divisor (note: this PLL does not support fractional division) 0x00000000 FBDIV_INT see ctrl reg description for constraints [11:0] read-write PRIM 0x0000000c Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2 0x00077000 POSTDIV1 divide by 1-7 [18:16] read-write POSTDIV2 divide by 1-7 [14:12] read-write PLL_USB 0x4002c000 UART0 0x40034000 0 4096 registers UART0_IRQ 20 UARTDR 0x00000000 Data Register, UARTDR 0x00000000 OE Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it. [11:11] read-only BE Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received. [10:10] read-only PE Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO. [9:9] read-only FE Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO. [8:8] read-only DATA Receive (read) data character. Transmit (write) data character. [7:0] read-write modify UARTRSR 0x00000004 Receive Status Register/Error Clear Register, UARTRSR/UARTECR 0x00000000 OE Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO. [3:3] read-write oneToClear BE Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. [2:2] read-write oneToClear PE Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. [1:1] read-write oneToClear FE Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. [0:0] read-write oneToClear UARTFR 0x00000018 Flag Register, UARTFR 0x00000090 RI Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW. [8:8] read-only TXFE Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register. [7:7] read-only RXFF Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full. [6:6] read-only TXFF Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full. [5:5] read-only RXFE Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty. [4:4] read-only BUSY UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not. [3:3] read-only DCD Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. [2:2] read-only DSR Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW. [1:1] read-only CTS Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW. [0:0] read-only UARTILPR 0x00000020 IrDA Low-Power Counter Register, UARTILPR 0x00000000 ILPDVSR 8-bit low-power divisor value. These bits are cleared to 0 at reset. [7:0] read-write UARTIBRD 0x00000024 Integer Baud Rate Register, UARTIBRD 0x00000000 BAUD_DIVINT The integer baud rate divisor. These bits are cleared to 0 on reset. [15:0] read-write UARTFBRD 0x00000028 Fractional Baud Rate Register, UARTFBRD 0x00000000 BAUD_DIVFRAC The fractional baud rate divisor. These bits are cleared to 0 on reset. [5:0] read-write UARTLCR_H 0x0000002c Line Control Register, UARTLCR_H 0x00000000 SPS Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation. [7:7] read-write WLEN Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. [6:5] read-write FEN Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode). [4:4] read-write STP2 Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received. [3:3] read-write EPS Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation. [2:2] read-write PEN Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled. [1:1] read-write BRK Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0. [0:0] read-write UARTCR 0x00000030 Control Register, UARTCR 0x00000300 CTSEN CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted. [15:15] read-write RTSEN RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received. [14:14] read-write OUT2 This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI). [13:13] read-write OUT1 This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD). [12:12] read-write RTS Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW. [11:11] read-write DTR Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW. [10:10] read-write RXE Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping. [9:9] read-write TXE Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping. [8:8] read-write LBE Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback. [7:7] read-write SIRLP SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. [2:2] read-write SIREN SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART. [1:1] read-write UARTEN UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. [0:0] read-write UARTIFLS 0x00000034 Interrupt FIFO Level Select Register, UARTIFLS 0x00000012 RXIFLSEL Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved. [5:3] read-write TXIFLSEL Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved. [2:0] read-write UARTIMSC 0x00000038 Interrupt Mask Set/Clear Register, UARTIMSC 0x00000000 OEIM Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask. [10:10] read-write BEIM Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask. [9:9] read-write PEIM Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask. [8:8] read-write FEIM Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask. [7:7] read-write RTIM Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask. [6:6] read-write TXIM Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask. [5:5] read-write RXIM Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask. [4:4] read-write DSRMIM nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask. [3:3] read-write DCDMIM nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask. [2:2] read-write CTSMIM nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask. [1:1] read-write RIMIM nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask. [0:0] read-write UARTRIS 0x0000003c Raw Interrupt Status Register, UARTRIS 0x00000000 OERIS Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt. [10:10] read-only BERIS Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt. [9:9] read-only PERIS Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt. [8:8] read-only FERIS Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt. [7:7] read-only RTRIS Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a [6:6] read-only TXRIS Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt. [5:5] read-only RXRIS Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt. [4:4] read-only DSRRMIS nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt. [3:3] read-only DCDRMIS nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt. [2:2] read-only CTSRMIS nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt. [1:1] read-only RIRMIS nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt. [0:0] read-only UARTMIS 0x00000040 Masked Interrupt Status Register, UARTMIS 0x00000000 OEMIS Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt. [10:10] read-only BEMIS Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt. [9:9] read-only PEMIS Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt. [8:8] read-only FEMIS Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt. [7:7] read-only RTMIS Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt. [6:6] read-only TXMIS Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt. [5:5] read-only RXMIS Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt. [4:4] read-only DSRMMIS nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt. [3:3] read-only DCDMMIS nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt. [2:2] read-only CTSMMIS nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt. [1:1] read-only RIMMIS nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt. [0:0] read-only UARTICR 0x00000044 Interrupt Clear Register, UARTICR 0x00000000 OEIC Overrun error interrupt clear. Clears the UARTOEINTR interrupt. [10:10] read-write oneToClear BEIC Break error interrupt clear. Clears the UARTBEINTR interrupt. [9:9] read-write oneToClear PEIC Parity error interrupt clear. Clears the UARTPEINTR interrupt. [8:8] read-write oneToClear FEIC Framing error interrupt clear. Clears the UARTFEINTR interrupt. [7:7] read-write oneToClear RTIC Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. [6:6] read-write oneToClear TXIC Transmit interrupt clear. Clears the UARTTXINTR interrupt. [5:5] read-write oneToClear RXIC Receive interrupt clear. Clears the UARTRXINTR interrupt. [4:4] read-write oneToClear DSRMIC nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. [3:3] read-write oneToClear DCDMIC nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. [2:2] read-write oneToClear CTSMIC nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. [1:1] read-write oneToClear RIMIC nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. [0:0] read-write oneToClear UARTDMACR 0x00000048 DMA Control Register, UARTDMACR 0x00000000 DMAONERR DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted. [2:2] read-write TXDMAE Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write RXDMAE Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write UARTPERIPHID0 0x00000fe0 UARTPeriphID0 Register 0x00000011 PARTNUMBER0 These bits read back as 0x11 [7:0] read-only UARTPERIPHID1 0x00000fe4 UARTPeriphID1 Register 0x00000010 DESIGNER0 These bits read back as 0x1 [7:4] read-only PARTNUMBER1 These bits read back as 0x0 [3:0] read-only UARTPERIPHID2 0x00000fe8 UARTPeriphID2 Register 0x00000034 REVISION This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3 [7:4] read-only DESIGNER1 These bits read back as 0x4 [3:0] read-only UARTPERIPHID3 0x00000fec UARTPeriphID3 Register 0x00000000 CONFIGURATION These bits read back as 0x00 [7:0] read-only UARTPCELLID0 0x00000ff0 UARTPCellID0 Register 0x0000000d UARTPCELLID0 These bits read back as 0x0D [7:0] read-only UARTPCELLID1 0x00000ff4 UARTPCellID1 Register 0x000000f0 UARTPCELLID1 These bits read back as 0xF0 [7:0] read-only UARTPCELLID2 0x00000ff8 UARTPCellID2 Register 0x00000005 UARTPCELLID2 These bits read back as 0x05 [7:0] read-only UARTPCELLID3 0x00000ffc UARTPCellID3 Register 0x000000b1 UARTPCELLID3 These bits read back as 0xB1 [7:0] read-only UART1 0x40038000 UART1_IRQ 21 ROSC 0x40060000 0 36 registers CTRL 0x00000000 Ring Oscillator control 0x00000aa0 ENABLE On power-up this field is initialised to ENABLE The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator. [23:12] read-write DISABLE 3358 ENABLE 4011 FREQ_RANGE Controls the number of delay stages in the ROSC ring LOW uses stages 0 to 7 MEDIUM uses stages 2 to 7 HIGH uses stages 4 to 7 TOOHIGH uses stages 6 to 7 and should not be used because its frequency exceeds design specifications The clock output will not glitch when changing the range up one step at a time The clock output will glitch when changing the range down Note: the values here are gray coded which is why HIGH comes before TOOHIGH [11:0] read-write LOW 4004 MEDIUM 4005 HIGH 4007 TOOHIGH 4006 FREQA 0x00000004 The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage The drive strength has 4 levels determined by the number of bits set Increasing the number of bits set increases the drive strength and increases the oscillation frequency 0 bits set is the default drive strength 1 bit set doubles the drive strength 2 bits set triples drive strength 3 bits set quadruples drive strength 0x00000000 PASSWD Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 [31:16] read-write PASS 38550 DS3 Stage 3 drive strength [14:12] read-write DS2 Stage 2 drive strength [10:8] read-write DS1 Stage 1 drive strength [6:4] read-write DS0 Stage 0 drive strength [2:0] read-write FREQB 0x00000008 For a detailed description see freqa register 0x00000000 PASSWD Set to 0x9696 to apply the settings Any other value in this field will set all drive strengths to 0 [31:16] read-write PASS 38550 DS7 Stage 7 drive strength [14:12] read-write DS6 Stage 6 drive strength [10:8] read-write DS5 Stage 5 drive strength [6:4] read-write DS4 Stage 4 drive strength [2:0] read-write DORMANT 0x0000000c Ring Oscillator pause control 0x00000000 DORMANT This is used to save power by pausing the ROSC On power-up this field is initialised to WAKE An invalid write will also select WAKE Warning: setup the irq before selecting dormant mode [31:0] read-write dormant 1668246881 WAKE 2002873189 DIV 0x00000010 Controls the output divider 0x00000000 DIV set to 0xaa0 + div where div = 0 divides by 32 div = 1-31 divides by div any other value sets div=31 this register resets to div=16 [11:0] read-write PASS 2720 PHASE 0x00000014 Controls the phase shifted output 0x00000008 PASSWD set to 0xaa any other value enables the output with shift=0 [11:4] read-write ENABLE enable the phase-shifted output this can be changed on-the-fly [3:3] read-write FLIP invert the phase-shifted output this is ignored when div=1 [2:2] read-write SHIFT phase shift the phase-shifted output by SHIFT input clocks this can be changed on-the-fly must be set to 0 before setting div=1 [1:0] read-write STATUS 0x00000018 Ring Oscillator Status 0x00000000 STABLE Oscillator is running and stable [31:31] read-only BADWRITE An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT [24:24] read-write oneToClear DIV_RUNNING post-divider is running this resets to 0 but transitions to 1 during chip startup [16:16] read-only ENABLED Oscillator is enabled but not necessarily running and stable this resets to 0 but transitions to 1 during chip startup [12:12] read-only RANDOMBIT 0x0000001c This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency 0x00000001 RANDOMBIT [0:0] read-only COUNT 0x00000020 A down counter running at the ROSC frequency which counts to zero and stops. To start the counter write a non-zero value. Can be used for short software pauses when setting up time sensitive hardware. 0x00000000 COUNT [7:0] read-write WATCHDOG 0x40058000 0 48 registers CTRL 0x00000000 Watchdog control The rst_wdsel register determines which subsystems are reset when the watchdog is triggered. The watchdog can be triggered in software. 0x07000000 TRIGGER Trigger a watchdog reset [31:31] write-only ENABLE When not enabled the watchdog timer is paused [30:30] read-write PAUSE_DBG1 Pause the watchdog timer when processor 1 is in debug mode [26:26] read-write PAUSE_DBG0 Pause the watchdog timer when processor 0 is in debug mode [25:25] read-write PAUSE_JTAG Pause the watchdog timer when JTAG is accessing the bus fabric [24:24] read-write TIME Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered [23:0] read-only LOAD 0x00000004 Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). 0x00000000 LOAD [23:0] write-only REASON 0x00000008 Logs the reason for the last reset. Both bits are zero for the case of a hardware reset. 0x00000000 FORCE [1:1] read-only TIMER [0:0] read-only SCRATCH0 0x0000000c Scratch register. Information persists through soft reset of the chip. 0x00000000 SCRATCH0 [31:0] read-write SCRATCH1 0x00000010 Scratch register. Information persists through soft reset of the chip. 0x00000000 SCRATCH1 [31:0] read-write SCRATCH2 0x00000014 Scratch register. Information persists through soft reset of the chip. 0x00000000 SCRATCH2 [31:0] read-write SCRATCH3 0x00000018 Scratch register. Information persists through soft reset of the chip. 0x00000000 SCRATCH3 [31:0] read-write SCRATCH4 0x0000001c Scratch register. Information persists through soft reset of the chip. 0x00000000 SCRATCH4 [31:0] read-write SCRATCH5 0x00000020 Scratch register. Information persists through soft reset of the chip. 0x00000000 SCRATCH5 [31:0] read-write SCRATCH6 0x00000024 Scratch register. Information persists through soft reset of the chip. 0x00000000 SCRATCH6 [31:0] read-write SCRATCH7 0x00000028 Scratch register. Information persists through soft reset of the chip. 0x00000000 SCRATCH7 [31:0] read-write TICK 0x0000002c Controls the tick generator 0x00000200 COUNT Count down timer: the remaining number clk_tick cycles before the next tick is generated. [19:11] read-only RUNNING Is the tick generator running? [10:10] read-only ENABLE start / stop tick generation [9:9] read-write CYCLES Total number of clk_tick cycles before the next tick. [8:0] read-write DMA DMA with separate read and write masters 0x50000000 0 2760 registers DMA_IRQ_0 11 DMA_IRQ_1 12 CH0_READ_ADDR 0x00000000 DMA Channel 0 Read Address pointer 0x00000000 CH0_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH0_WRITE_ADDR 0x00000004 DMA Channel 0 Write Address pointer 0x00000000 CH0_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH0_TRANS_COUNT 0x00000008 DMA Channel 0 Transfer Count 0x00000000 CH0_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH0_CTRL_TRIG 0x0000000c DMA Channel 0 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH0_AL1_CTRL 0x00000010 Alias for channel 0 CTRL register 0x00000000 CH0_AL1_CTRL [31:0] read-write CH0_AL1_READ_ADDR 0x00000014 Alias for channel 0 READ_ADDR register 0x00000000 CH0_AL1_READ_ADDR [31:0] read-write CH0_AL1_WRITE_ADDR 0x00000018 Alias for channel 0 WRITE_ADDR register 0x00000000 CH0_AL1_WRITE_ADDR [31:0] read-write CH0_AL1_TRANS_COUNT_TRIG 0x0000001c Alias for channel 0 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH0_AL1_TRANS_COUNT_TRIG [31:0] read-write CH0_AL2_CTRL 0x00000020 Alias for channel 0 CTRL register 0x00000000 CH0_AL2_CTRL [31:0] read-write CH0_AL2_TRANS_COUNT 0x00000024 Alias for channel 0 TRANS_COUNT register 0x00000000 CH0_AL2_TRANS_COUNT [31:0] read-write CH0_AL2_READ_ADDR 0x00000028 Alias for channel 0 READ_ADDR register 0x00000000 CH0_AL2_READ_ADDR [31:0] read-write CH0_AL2_WRITE_ADDR_TRIG 0x0000002c Alias for channel 0 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH0_AL2_WRITE_ADDR_TRIG [31:0] read-write CH0_AL3_CTRL 0x00000030 Alias for channel 0 CTRL register 0x00000000 CH0_AL3_CTRL [31:0] read-write CH0_AL3_WRITE_ADDR 0x00000034 Alias for channel 0 WRITE_ADDR register 0x00000000 CH0_AL3_WRITE_ADDR [31:0] read-write CH0_AL3_TRANS_COUNT 0x00000038 Alias for channel 0 TRANS_COUNT register 0x00000000 CH0_AL3_TRANS_COUNT [31:0] read-write CH0_AL3_READ_ADDR_TRIG 0x0000003c Alias for channel 0 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH0_AL3_READ_ADDR_TRIG [31:0] read-write CH1_READ_ADDR 0x00000040 DMA Channel 1 Read Address pointer 0x00000000 CH1_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH1_WRITE_ADDR 0x00000044 DMA Channel 1 Write Address pointer 0x00000000 CH1_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH1_TRANS_COUNT 0x00000048 DMA Channel 1 Transfer Count 0x00000000 CH1_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH1_CTRL_TRIG 0x0000004c DMA Channel 1 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH1_AL1_CTRL 0x00000050 Alias for channel 1 CTRL register 0x00000000 CH1_AL1_CTRL [31:0] read-write CH1_AL1_READ_ADDR 0x00000054 Alias for channel 1 READ_ADDR register 0x00000000 CH1_AL1_READ_ADDR [31:0] read-write CH1_AL1_WRITE_ADDR 0x00000058 Alias for channel 1 WRITE_ADDR register 0x00000000 CH1_AL1_WRITE_ADDR [31:0] read-write CH1_AL1_TRANS_COUNT_TRIG 0x0000005c Alias for channel 1 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH1_AL1_TRANS_COUNT_TRIG [31:0] read-write CH1_AL2_CTRL 0x00000060 Alias for channel 1 CTRL register 0x00000000 CH1_AL2_CTRL [31:0] read-write CH1_AL2_TRANS_COUNT 0x00000064 Alias for channel 1 TRANS_COUNT register 0x00000000 CH1_AL2_TRANS_COUNT [31:0] read-write CH1_AL2_READ_ADDR 0x00000068 Alias for channel 1 READ_ADDR register 0x00000000 CH1_AL2_READ_ADDR [31:0] read-write CH1_AL2_WRITE_ADDR_TRIG 0x0000006c Alias for channel 1 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH1_AL2_WRITE_ADDR_TRIG [31:0] read-write CH1_AL3_CTRL 0x00000070 Alias for channel 1 CTRL register 0x00000000 CH1_AL3_CTRL [31:0] read-write CH1_AL3_WRITE_ADDR 0x00000074 Alias for channel 1 WRITE_ADDR register 0x00000000 CH1_AL3_WRITE_ADDR [31:0] read-write CH1_AL3_TRANS_COUNT 0x00000078 Alias for channel 1 TRANS_COUNT register 0x00000000 CH1_AL3_TRANS_COUNT [31:0] read-write CH1_AL3_READ_ADDR_TRIG 0x0000007c Alias for channel 1 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH1_AL3_READ_ADDR_TRIG [31:0] read-write CH2_READ_ADDR 0x00000080 DMA Channel 2 Read Address pointer 0x00000000 CH2_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH2_WRITE_ADDR 0x00000084 DMA Channel 2 Write Address pointer 0x00000000 CH2_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH2_TRANS_COUNT 0x00000088 DMA Channel 2 Transfer Count 0x00000000 CH2_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH2_CTRL_TRIG 0x0000008c DMA Channel 2 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH2_AL1_CTRL 0x00000090 Alias for channel 2 CTRL register 0x00000000 CH2_AL1_CTRL [31:0] read-write CH2_AL1_READ_ADDR 0x00000094 Alias for channel 2 READ_ADDR register 0x00000000 CH2_AL1_READ_ADDR [31:0] read-write CH2_AL1_WRITE_ADDR 0x00000098 Alias for channel 2 WRITE_ADDR register 0x00000000 CH2_AL1_WRITE_ADDR [31:0] read-write CH2_AL1_TRANS_COUNT_TRIG 0x0000009c Alias for channel 2 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH2_AL1_TRANS_COUNT_TRIG [31:0] read-write CH2_AL2_CTRL 0x000000a0 Alias for channel 2 CTRL register 0x00000000 CH2_AL2_CTRL [31:0] read-write CH2_AL2_TRANS_COUNT 0x000000a4 Alias for channel 2 TRANS_COUNT register 0x00000000 CH2_AL2_TRANS_COUNT [31:0] read-write CH2_AL2_READ_ADDR 0x000000a8 Alias for channel 2 READ_ADDR register 0x00000000 CH2_AL2_READ_ADDR [31:0] read-write CH2_AL2_WRITE_ADDR_TRIG 0x000000ac Alias for channel 2 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH2_AL2_WRITE_ADDR_TRIG [31:0] read-write CH2_AL3_CTRL 0x000000b0 Alias for channel 2 CTRL register 0x00000000 CH2_AL3_CTRL [31:0] read-write CH2_AL3_WRITE_ADDR 0x000000b4 Alias for channel 2 WRITE_ADDR register 0x00000000 CH2_AL3_WRITE_ADDR [31:0] read-write CH2_AL3_TRANS_COUNT 0x000000b8 Alias for channel 2 TRANS_COUNT register 0x00000000 CH2_AL3_TRANS_COUNT [31:0] read-write CH2_AL3_READ_ADDR_TRIG 0x000000bc Alias for channel 2 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH2_AL3_READ_ADDR_TRIG [31:0] read-write CH3_READ_ADDR 0x000000c0 DMA Channel 3 Read Address pointer 0x00000000 CH3_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH3_WRITE_ADDR 0x000000c4 DMA Channel 3 Write Address pointer 0x00000000 CH3_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH3_TRANS_COUNT 0x000000c8 DMA Channel 3 Transfer Count 0x00000000 CH3_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH3_CTRL_TRIG 0x000000cc DMA Channel 3 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH3_AL1_CTRL 0x000000d0 Alias for channel 3 CTRL register 0x00000000 CH3_AL1_CTRL [31:0] read-write CH3_AL1_READ_ADDR 0x000000d4 Alias for channel 3 READ_ADDR register 0x00000000 CH3_AL1_READ_ADDR [31:0] read-write CH3_AL1_WRITE_ADDR 0x000000d8 Alias for channel 3 WRITE_ADDR register 0x00000000 CH3_AL1_WRITE_ADDR [31:0] read-write CH3_AL1_TRANS_COUNT_TRIG 0x000000dc Alias for channel 3 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH3_AL1_TRANS_COUNT_TRIG [31:0] read-write CH3_AL2_CTRL 0x000000e0 Alias for channel 3 CTRL register 0x00000000 CH3_AL2_CTRL [31:0] read-write CH3_AL2_TRANS_COUNT 0x000000e4 Alias for channel 3 TRANS_COUNT register 0x00000000 CH3_AL2_TRANS_COUNT [31:0] read-write CH3_AL2_READ_ADDR 0x000000e8 Alias for channel 3 READ_ADDR register 0x00000000 CH3_AL2_READ_ADDR [31:0] read-write CH3_AL2_WRITE_ADDR_TRIG 0x000000ec Alias for channel 3 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH3_AL2_WRITE_ADDR_TRIG [31:0] read-write CH3_AL3_CTRL 0x000000f0 Alias for channel 3 CTRL register 0x00000000 CH3_AL3_CTRL [31:0] read-write CH3_AL3_WRITE_ADDR 0x000000f4 Alias for channel 3 WRITE_ADDR register 0x00000000 CH3_AL3_WRITE_ADDR [31:0] read-write CH3_AL3_TRANS_COUNT 0x000000f8 Alias for channel 3 TRANS_COUNT register 0x00000000 CH3_AL3_TRANS_COUNT [31:0] read-write CH3_AL3_READ_ADDR_TRIG 0x000000fc Alias for channel 3 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH3_AL3_READ_ADDR_TRIG [31:0] read-write CH4_READ_ADDR 0x00000100 DMA Channel 4 Read Address pointer 0x00000000 CH4_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH4_WRITE_ADDR 0x00000104 DMA Channel 4 Write Address pointer 0x00000000 CH4_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH4_TRANS_COUNT 0x00000108 DMA Channel 4 Transfer Count 0x00000000 CH4_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH4_CTRL_TRIG 0x0000010c DMA Channel 4 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH4_AL1_CTRL 0x00000110 Alias for channel 4 CTRL register 0x00000000 CH4_AL1_CTRL [31:0] read-write CH4_AL1_READ_ADDR 0x00000114 Alias for channel 4 READ_ADDR register 0x00000000 CH4_AL1_READ_ADDR [31:0] read-write CH4_AL1_WRITE_ADDR 0x00000118 Alias for channel 4 WRITE_ADDR register 0x00000000 CH4_AL1_WRITE_ADDR [31:0] read-write CH4_AL1_TRANS_COUNT_TRIG 0x0000011c Alias for channel 4 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH4_AL1_TRANS_COUNT_TRIG [31:0] read-write CH4_AL2_CTRL 0x00000120 Alias for channel 4 CTRL register 0x00000000 CH4_AL2_CTRL [31:0] read-write CH4_AL2_TRANS_COUNT 0x00000124 Alias for channel 4 TRANS_COUNT register 0x00000000 CH4_AL2_TRANS_COUNT [31:0] read-write CH4_AL2_READ_ADDR 0x00000128 Alias for channel 4 READ_ADDR register 0x00000000 CH4_AL2_READ_ADDR [31:0] read-write CH4_AL2_WRITE_ADDR_TRIG 0x0000012c Alias for channel 4 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH4_AL2_WRITE_ADDR_TRIG [31:0] read-write CH4_AL3_CTRL 0x00000130 Alias for channel 4 CTRL register 0x00000000 CH4_AL3_CTRL [31:0] read-write CH4_AL3_WRITE_ADDR 0x00000134 Alias for channel 4 WRITE_ADDR register 0x00000000 CH4_AL3_WRITE_ADDR [31:0] read-write CH4_AL3_TRANS_COUNT 0x00000138 Alias for channel 4 TRANS_COUNT register 0x00000000 CH4_AL3_TRANS_COUNT [31:0] read-write CH4_AL3_READ_ADDR_TRIG 0x0000013c Alias for channel 4 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH4_AL3_READ_ADDR_TRIG [31:0] read-write CH5_READ_ADDR 0x00000140 DMA Channel 5 Read Address pointer 0x00000000 CH5_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH5_WRITE_ADDR 0x00000144 DMA Channel 5 Write Address pointer 0x00000000 CH5_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH5_TRANS_COUNT 0x00000148 DMA Channel 5 Transfer Count 0x00000000 CH5_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH5_CTRL_TRIG 0x0000014c DMA Channel 5 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH5_AL1_CTRL 0x00000150 Alias for channel 5 CTRL register 0x00000000 CH5_AL1_CTRL [31:0] read-write CH5_AL1_READ_ADDR 0x00000154 Alias for channel 5 READ_ADDR register 0x00000000 CH5_AL1_READ_ADDR [31:0] read-write CH5_AL1_WRITE_ADDR 0x00000158 Alias for channel 5 WRITE_ADDR register 0x00000000 CH5_AL1_WRITE_ADDR [31:0] read-write CH5_AL1_TRANS_COUNT_TRIG 0x0000015c Alias for channel 5 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH5_AL1_TRANS_COUNT_TRIG [31:0] read-write CH5_AL2_CTRL 0x00000160 Alias for channel 5 CTRL register 0x00000000 CH5_AL2_CTRL [31:0] read-write CH5_AL2_TRANS_COUNT 0x00000164 Alias for channel 5 TRANS_COUNT register 0x00000000 CH5_AL2_TRANS_COUNT [31:0] read-write CH5_AL2_READ_ADDR 0x00000168 Alias for channel 5 READ_ADDR register 0x00000000 CH5_AL2_READ_ADDR [31:0] read-write CH5_AL2_WRITE_ADDR_TRIG 0x0000016c Alias for channel 5 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH5_AL2_WRITE_ADDR_TRIG [31:0] read-write CH5_AL3_CTRL 0x00000170 Alias for channel 5 CTRL register 0x00000000 CH5_AL3_CTRL [31:0] read-write CH5_AL3_WRITE_ADDR 0x00000174 Alias for channel 5 WRITE_ADDR register 0x00000000 CH5_AL3_WRITE_ADDR [31:0] read-write CH5_AL3_TRANS_COUNT 0x00000178 Alias for channel 5 TRANS_COUNT register 0x00000000 CH5_AL3_TRANS_COUNT [31:0] read-write CH5_AL3_READ_ADDR_TRIG 0x0000017c Alias for channel 5 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH5_AL3_READ_ADDR_TRIG [31:0] read-write CH6_READ_ADDR 0x00000180 DMA Channel 6 Read Address pointer 0x00000000 CH6_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH6_WRITE_ADDR 0x00000184 DMA Channel 6 Write Address pointer 0x00000000 CH6_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH6_TRANS_COUNT 0x00000188 DMA Channel 6 Transfer Count 0x00000000 CH6_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH6_CTRL_TRIG 0x0000018c DMA Channel 6 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH6_AL1_CTRL 0x00000190 Alias for channel 6 CTRL register 0x00000000 CH6_AL1_CTRL [31:0] read-write CH6_AL1_READ_ADDR 0x00000194 Alias for channel 6 READ_ADDR register 0x00000000 CH6_AL1_READ_ADDR [31:0] read-write CH6_AL1_WRITE_ADDR 0x00000198 Alias for channel 6 WRITE_ADDR register 0x00000000 CH6_AL1_WRITE_ADDR [31:0] read-write CH6_AL1_TRANS_COUNT_TRIG 0x0000019c Alias for channel 6 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH6_AL1_TRANS_COUNT_TRIG [31:0] read-write CH6_AL2_CTRL 0x000001a0 Alias for channel 6 CTRL register 0x00000000 CH6_AL2_CTRL [31:0] read-write CH6_AL2_TRANS_COUNT 0x000001a4 Alias for channel 6 TRANS_COUNT register 0x00000000 CH6_AL2_TRANS_COUNT [31:0] read-write CH6_AL2_READ_ADDR 0x000001a8 Alias for channel 6 READ_ADDR register 0x00000000 CH6_AL2_READ_ADDR [31:0] read-write CH6_AL2_WRITE_ADDR_TRIG 0x000001ac Alias for channel 6 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH6_AL2_WRITE_ADDR_TRIG [31:0] read-write CH6_AL3_CTRL 0x000001b0 Alias for channel 6 CTRL register 0x00000000 CH6_AL3_CTRL [31:0] read-write CH6_AL3_WRITE_ADDR 0x000001b4 Alias for channel 6 WRITE_ADDR register 0x00000000 CH6_AL3_WRITE_ADDR [31:0] read-write CH6_AL3_TRANS_COUNT 0x000001b8 Alias for channel 6 TRANS_COUNT register 0x00000000 CH6_AL3_TRANS_COUNT [31:0] read-write CH6_AL3_READ_ADDR_TRIG 0x000001bc Alias for channel 6 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH6_AL3_READ_ADDR_TRIG [31:0] read-write CH7_READ_ADDR 0x000001c0 DMA Channel 7 Read Address pointer 0x00000000 CH7_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH7_WRITE_ADDR 0x000001c4 DMA Channel 7 Write Address pointer 0x00000000 CH7_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH7_TRANS_COUNT 0x000001c8 DMA Channel 7 Transfer Count 0x00000000 CH7_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH7_CTRL_TRIG 0x000001cc DMA Channel 7 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH7_AL1_CTRL 0x000001d0 Alias for channel 7 CTRL register 0x00000000 CH7_AL1_CTRL [31:0] read-write CH7_AL1_READ_ADDR 0x000001d4 Alias for channel 7 READ_ADDR register 0x00000000 CH7_AL1_READ_ADDR [31:0] read-write CH7_AL1_WRITE_ADDR 0x000001d8 Alias for channel 7 WRITE_ADDR register 0x00000000 CH7_AL1_WRITE_ADDR [31:0] read-write CH7_AL1_TRANS_COUNT_TRIG 0x000001dc Alias for channel 7 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH7_AL1_TRANS_COUNT_TRIG [31:0] read-write CH7_AL2_CTRL 0x000001e0 Alias for channel 7 CTRL register 0x00000000 CH7_AL2_CTRL [31:0] read-write CH7_AL2_TRANS_COUNT 0x000001e4 Alias for channel 7 TRANS_COUNT register 0x00000000 CH7_AL2_TRANS_COUNT [31:0] read-write CH7_AL2_READ_ADDR 0x000001e8 Alias for channel 7 READ_ADDR register 0x00000000 CH7_AL2_READ_ADDR [31:0] read-write CH7_AL2_WRITE_ADDR_TRIG 0x000001ec Alias for channel 7 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH7_AL2_WRITE_ADDR_TRIG [31:0] read-write CH7_AL3_CTRL 0x000001f0 Alias for channel 7 CTRL register 0x00000000 CH7_AL3_CTRL [31:0] read-write CH7_AL3_WRITE_ADDR 0x000001f4 Alias for channel 7 WRITE_ADDR register 0x00000000 CH7_AL3_WRITE_ADDR [31:0] read-write CH7_AL3_TRANS_COUNT 0x000001f8 Alias for channel 7 TRANS_COUNT register 0x00000000 CH7_AL3_TRANS_COUNT [31:0] read-write CH7_AL3_READ_ADDR_TRIG 0x000001fc Alias for channel 7 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH7_AL3_READ_ADDR_TRIG [31:0] read-write CH8_READ_ADDR 0x00000200 DMA Channel 8 Read Address pointer 0x00000000 CH8_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH8_WRITE_ADDR 0x00000204 DMA Channel 8 Write Address pointer 0x00000000 CH8_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH8_TRANS_COUNT 0x00000208 DMA Channel 8 Transfer Count 0x00000000 CH8_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH8_CTRL_TRIG 0x0000020c DMA Channel 8 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH8_AL1_CTRL 0x00000210 Alias for channel 8 CTRL register 0x00000000 CH8_AL1_CTRL [31:0] read-write CH8_AL1_READ_ADDR 0x00000214 Alias for channel 8 READ_ADDR register 0x00000000 CH8_AL1_READ_ADDR [31:0] read-write CH8_AL1_WRITE_ADDR 0x00000218 Alias for channel 8 WRITE_ADDR register 0x00000000 CH8_AL1_WRITE_ADDR [31:0] read-write CH8_AL1_TRANS_COUNT_TRIG 0x0000021c Alias for channel 8 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH8_AL1_TRANS_COUNT_TRIG [31:0] read-write CH8_AL2_CTRL 0x00000220 Alias for channel 8 CTRL register 0x00000000 CH8_AL2_CTRL [31:0] read-write CH8_AL2_TRANS_COUNT 0x00000224 Alias for channel 8 TRANS_COUNT register 0x00000000 CH8_AL2_TRANS_COUNT [31:0] read-write CH8_AL2_READ_ADDR 0x00000228 Alias for channel 8 READ_ADDR register 0x00000000 CH8_AL2_READ_ADDR [31:0] read-write CH8_AL2_WRITE_ADDR_TRIG 0x0000022c Alias for channel 8 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH8_AL2_WRITE_ADDR_TRIG [31:0] read-write CH8_AL3_CTRL 0x00000230 Alias for channel 8 CTRL register 0x00000000 CH8_AL3_CTRL [31:0] read-write CH8_AL3_WRITE_ADDR 0x00000234 Alias for channel 8 WRITE_ADDR register 0x00000000 CH8_AL3_WRITE_ADDR [31:0] read-write CH8_AL3_TRANS_COUNT 0x00000238 Alias for channel 8 TRANS_COUNT register 0x00000000 CH8_AL3_TRANS_COUNT [31:0] read-write CH8_AL3_READ_ADDR_TRIG 0x0000023c Alias for channel 8 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH8_AL3_READ_ADDR_TRIG [31:0] read-write CH9_READ_ADDR 0x00000240 DMA Channel 9 Read Address pointer 0x00000000 CH9_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH9_WRITE_ADDR 0x00000244 DMA Channel 9 Write Address pointer 0x00000000 CH9_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH9_TRANS_COUNT 0x00000248 DMA Channel 9 Transfer Count 0x00000000 CH9_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH9_CTRL_TRIG 0x0000024c DMA Channel 9 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH9_AL1_CTRL 0x00000250 Alias for channel 9 CTRL register 0x00000000 CH9_AL1_CTRL [31:0] read-write CH9_AL1_READ_ADDR 0x00000254 Alias for channel 9 READ_ADDR register 0x00000000 CH9_AL1_READ_ADDR [31:0] read-write CH9_AL1_WRITE_ADDR 0x00000258 Alias for channel 9 WRITE_ADDR register 0x00000000 CH9_AL1_WRITE_ADDR [31:0] read-write CH9_AL1_TRANS_COUNT_TRIG 0x0000025c Alias for channel 9 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH9_AL1_TRANS_COUNT_TRIG [31:0] read-write CH9_AL2_CTRL 0x00000260 Alias for channel 9 CTRL register 0x00000000 CH9_AL2_CTRL [31:0] read-write CH9_AL2_TRANS_COUNT 0x00000264 Alias for channel 9 TRANS_COUNT register 0x00000000 CH9_AL2_TRANS_COUNT [31:0] read-write CH9_AL2_READ_ADDR 0x00000268 Alias for channel 9 READ_ADDR register 0x00000000 CH9_AL2_READ_ADDR [31:0] read-write CH9_AL2_WRITE_ADDR_TRIG 0x0000026c Alias for channel 9 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH9_AL2_WRITE_ADDR_TRIG [31:0] read-write CH9_AL3_CTRL 0x00000270 Alias for channel 9 CTRL register 0x00000000 CH9_AL3_CTRL [31:0] read-write CH9_AL3_WRITE_ADDR 0x00000274 Alias for channel 9 WRITE_ADDR register 0x00000000 CH9_AL3_WRITE_ADDR [31:0] read-write CH9_AL3_TRANS_COUNT 0x00000278 Alias for channel 9 TRANS_COUNT register 0x00000000 CH9_AL3_TRANS_COUNT [31:0] read-write CH9_AL3_READ_ADDR_TRIG 0x0000027c Alias for channel 9 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH9_AL3_READ_ADDR_TRIG [31:0] read-write CH10_READ_ADDR 0x00000280 DMA Channel 10 Read Address pointer 0x00000000 CH10_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH10_WRITE_ADDR 0x00000284 DMA Channel 10 Write Address pointer 0x00000000 CH10_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH10_TRANS_COUNT 0x00000288 DMA Channel 10 Transfer Count 0x00000000 CH10_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH10_CTRL_TRIG 0x0000028c DMA Channel 10 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH10_AL1_CTRL 0x00000290 Alias for channel 10 CTRL register 0x00000000 CH10_AL1_CTRL [31:0] read-write CH10_AL1_READ_ADDR 0x00000294 Alias for channel 10 READ_ADDR register 0x00000000 CH10_AL1_READ_ADDR [31:0] read-write CH10_AL1_WRITE_ADDR 0x00000298 Alias for channel 10 WRITE_ADDR register 0x00000000 CH10_AL1_WRITE_ADDR [31:0] read-write CH10_AL1_TRANS_COUNT_TRIG 0x0000029c Alias for channel 10 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH10_AL1_TRANS_COUNT_TRIG [31:0] read-write CH10_AL2_CTRL 0x000002a0 Alias for channel 10 CTRL register 0x00000000 CH10_AL2_CTRL [31:0] read-write CH10_AL2_TRANS_COUNT 0x000002a4 Alias for channel 10 TRANS_COUNT register 0x00000000 CH10_AL2_TRANS_COUNT [31:0] read-write CH10_AL2_READ_ADDR 0x000002a8 Alias for channel 10 READ_ADDR register 0x00000000 CH10_AL2_READ_ADDR [31:0] read-write CH10_AL2_WRITE_ADDR_TRIG 0x000002ac Alias for channel 10 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH10_AL2_WRITE_ADDR_TRIG [31:0] read-write CH10_AL3_CTRL 0x000002b0 Alias for channel 10 CTRL register 0x00000000 CH10_AL3_CTRL [31:0] read-write CH10_AL3_WRITE_ADDR 0x000002b4 Alias for channel 10 WRITE_ADDR register 0x00000000 CH10_AL3_WRITE_ADDR [31:0] read-write CH10_AL3_TRANS_COUNT 0x000002b8 Alias for channel 10 TRANS_COUNT register 0x00000000 CH10_AL3_TRANS_COUNT [31:0] read-write CH10_AL3_READ_ADDR_TRIG 0x000002bc Alias for channel 10 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH10_AL3_READ_ADDR_TRIG [31:0] read-write CH11_READ_ADDR 0x000002c0 DMA Channel 11 Read Address pointer 0x00000000 CH11_READ_ADDR This register updates automatically each time a read completes. The current value is the next address to be read by this channel. [31:0] read-write CH11_WRITE_ADDR 0x000002c4 DMA Channel 11 Write Address pointer 0x00000000 CH11_WRITE_ADDR This register updates automatically each time a write completes. The current value is the next address to be written by this channel. [31:0] read-write CH11_TRANS_COUNT 0x000002c8 DMA Channel 11 Transfer Count 0x00000000 CH11_TRANS_COUNT Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD. [31:0] read-write CH11_CTRL_TRIG 0x000002cc DMA Channel 11 Control and Status 0x00000000 AHB_ERROR Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag. [31:31] read-only READ_ERROR If 1, the channel received a read bus error. Write one to clear. READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later) [30:30] read-write oneToClear WRITE_ERROR If 1, the channel received a write bus error. Write one to clear. WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later) [29:29] read-write oneToClear BUSY This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused. To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. [24:24] read-only SNIFF_EN If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected. This allows checksum to be enabled or disabled on a per-control- block basis. [23:23] read-write BSWAP Apply byte-swap transformation to DMA data. For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order. [22:22] read-write IRQ_QUIET In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain. This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks. [21:21] read-write TREQ_SEL Select a Transfer Request signal. The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system). 0x0 to 0x3a -> select DREQ n as TREQ [20:15] read-write PIO0_TX0 0 Select PIO0's TX FIFO 0 as TREQ PIO0_TX1 1 Select PIO0's TX FIFO 1 as TREQ PIO0_TX2 2 Select PIO0's TX FIFO 2 as TREQ PIO0_TX3 3 Select PIO0's TX FIFO 3 as TREQ PIO0_RX0 4 Select PIO0's RX FIFO 0 as TREQ PIO0_RX1 5 Select PIO0's RX FIFO 1 as TREQ PIO0_RX2 6 Select PIO0's RX FIFO 2 as TREQ PIO0_RX3 7 Select PIO0's RX FIFO 3 as TREQ PIO1_TX0 8 Select PIO1's TX FIFO 0 as TREQ PIO1_TX1 9 Select PIO1's TX FIFO 1 as TREQ PIO1_TX2 10 Select PIO1's TX FIFO 2 as TREQ PIO1_TX3 11 Select PIO1's TX FIFO 3 as TREQ PIO1_RX0 12 Select PIO1's RX FIFO 0 as TREQ PIO1_RX1 13 Select PIO1's RX FIFO 1 as TREQ PIO1_RX2 14 Select PIO1's RX FIFO 2 as TREQ PIO1_RX3 15 Select PIO1's RX FIFO 3 as TREQ SPI0_TX 16 Select SPI0's TX FIFO as TREQ SPI0_RX 17 Select SPI0's RX FIFO as TREQ SPI1_TX 18 Select SPI1's TX FIFO as TREQ SPI1_RX 19 Select SPI1's RX FIFO as TREQ UART0_TX 20 Select UART0's TX FIFO as TREQ UART0_RX 21 Select UART0's RX FIFO as TREQ UART1_TX 22 Select UART1's TX FIFO as TREQ UART1_RX 23 Select UART1's RX FIFO as TREQ PWM_WRAP0 24 Select PWM Counter 0's Wrap Value as TREQ PWM_WRAP1 25 Select PWM Counter 1's Wrap Value as TREQ PWM_WRAP2 26 Select PWM Counter 2's Wrap Value as TREQ PWM_WRAP3 27 Select PWM Counter 3's Wrap Value as TREQ PWM_WRAP4 28 Select PWM Counter 4's Wrap Value as TREQ PWM_WRAP5 29 Select PWM Counter 5's Wrap Value as TREQ PWM_WRAP6 30 Select PWM Counter 6's Wrap Value as TREQ PWM_WRAP7 31 Select PWM Counter 7's Wrap Value as TREQ I2C0_TX 32 Select I2C0's TX FIFO as TREQ I2C0_RX 33 Select I2C0's RX FIFO as TREQ I2C1_TX 34 Select I2C1's TX FIFO as TREQ I2C1_RX 35 Select I2C1's RX FIFO as TREQ ADC 36 Select the ADC as TREQ XIP_STREAM 37 Select the XIP Streaming FIFO as TREQ XIP_SSITX 38 Select the XIP SSI TX FIFO as TREQ XIP_SSIRX 39 Select the XIP SSI RX FIFO as TREQ TIMER0 59 Select Timer 0 as TREQ TIMER1 60 Select Timer 1 as TREQ TIMER2 61 Select Timer 2 as TREQ (Optional) TIMER3 62 Select Timer 3 as TREQ (Optional) PERMANENT 63 Permanent request, for unpaced transfers. CHAIN_TO When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_. [14:11] read-write RING_SEL Select whether RING_SIZE applies to read or write addresses. If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped. [10:10] read-write RING_SIZE Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers. Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL. [9:6] read-write RING_NONE 0 INCR_WRITE If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address. Generally this should be disabled for memory-to-peripheral transfers. [5:5] read-write INCR_READ If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address. Generally this should be disabled for peripheral-to-memory transfers. [4:4] read-write DATA_SIZE Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer. [3:2] read-write SIZE_BYTE 0 SIZE_HALFWORD 1 SIZE_WORD 2 HIGH_PRIORITY HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels. This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput. [1:1] read-write EN DMA Channel Enable. When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high) [0:0] read-write CH11_AL1_CTRL 0x000002d0 Alias for channel 11 CTRL register 0x00000000 CH11_AL1_CTRL [31:0] read-write CH11_AL1_READ_ADDR 0x000002d4 Alias for channel 11 READ_ADDR register 0x00000000 CH11_AL1_READ_ADDR [31:0] read-write CH11_AL1_WRITE_ADDR 0x000002d8 Alias for channel 11 WRITE_ADDR register 0x00000000 CH11_AL1_WRITE_ADDR [31:0] read-write CH11_AL1_TRANS_COUNT_TRIG 0x000002dc Alias for channel 11 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH11_AL1_TRANS_COUNT_TRIG [31:0] read-write CH11_AL2_CTRL 0x000002e0 Alias for channel 11 CTRL register 0x00000000 CH11_AL2_CTRL [31:0] read-write CH11_AL2_TRANS_COUNT 0x000002e4 Alias for channel 11 TRANS_COUNT register 0x00000000 CH11_AL2_TRANS_COUNT [31:0] read-write CH11_AL2_READ_ADDR 0x000002e8 Alias for channel 11 READ_ADDR register 0x00000000 CH11_AL2_READ_ADDR [31:0] read-write CH11_AL2_WRITE_ADDR_TRIG 0x000002ec Alias for channel 11 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH11_AL2_WRITE_ADDR_TRIG [31:0] read-write CH11_AL3_CTRL 0x000002f0 Alias for channel 11 CTRL register 0x00000000 CH11_AL3_CTRL [31:0] read-write CH11_AL3_WRITE_ADDR 0x000002f4 Alias for channel 11 WRITE_ADDR register 0x00000000 CH11_AL3_WRITE_ADDR [31:0] read-write CH11_AL3_TRANS_COUNT 0x000002f8 Alias for channel 11 TRANS_COUNT register 0x00000000 CH11_AL3_TRANS_COUNT [31:0] read-write CH11_AL3_READ_ADDR_TRIG 0x000002fc Alias for channel 11 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel. 0x00000000 CH11_AL3_READ_ADDR_TRIG [31:0] read-write INTR 0x00000400 Interrupt Status (raw) 0x00000000 INTR Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. [15:0] read-write oneToClear INTE0 0x00000404 Interrupt Enables for IRQ 0 0x00000000 INTE0 Set bit n to pass interrupts from channel n to DMA IRQ 0. [15:0] read-write INTF0 0x00000408 Force Interrupts 0x00000000 INTF0 Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. [15:0] read-write INTS0 0x0000040c Interrupt Status for IRQ 0 0x00000000 INTS0 Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted. Channel interrupts can be cleared by writing a bit mask here. [15:0] read-write oneToClear INTR1 0x00000410 Interrupt Status (raw) 0x00000000 INTR1 Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1. Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1. This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores. It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0. [15:0] read-write oneToClear INTE1 0x00000414 Interrupt Enables for IRQ 1 0x00000000 INTE1 Set bit n to pass interrupts from channel n to DMA IRQ 1. [15:0] read-write INTF1 0x00000418 Force Interrupts for IRQ 1 0x00000000 INTF1 Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared. [15:0] read-write INTS1 0x0000041c Interrupt Status (masked) for IRQ 1 0x00000000 INTS1 Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted. Channel interrupts can be cleared by writing a bit mask here. [15:0] read-write oneToClear TIMER0 0x00000420 Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. 0x00000000 X Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. [31:16] read-write Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. [15:0] read-write TIMER1 0x00000424 Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. 0x00000000 X Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. [31:16] read-write Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. [15:0] read-write TIMER2 0x00000428 Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. 0x00000000 X Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. [31:16] read-write Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. [15:0] read-write TIMER3 0x0000042c Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. 0x00000000 X Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. [31:16] read-write Y Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. [15:0] read-write MULTI_CHAN_TRIGGER 0x00000430 Trigger one or more channels simultaneously 0x00000000 MULTI_CHAN_TRIGGER Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy. [15:0] write-only SNIFF_CTRL 0x00000434 Sniffer Control 0x00000000 OUT_INV If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. [11:11] read-write OUT_REV If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus. [10:10] read-write BSWAP Locally perform a byte reverse on the sniffed data, before feeding into checksum. Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view. [9:9] read-write CALC [8:5] read-write CRC32 0 Calculate a CRC-32 (IEEE802.3 polynomial) CRC32R 1 Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data CRC16 2 Calculate a CRC-16-CCITT CRC16R 3 Calculate a CRC-16-CCITT with bit reversed data EVEN 14 XOR reduction over all data. == 1 if the total 1 population count is odd. SUM 15 Calculate a simple 32-bit checksum (addition with a 32 bit accumulator) DMACH DMA channel for Sniffer to observe [4:1] read-write EN Enable sniffer [0:0] read-write SNIFF_DATA 0x00000438 Data accumulator for sniff hardware 0x00000000 SNIFF_DATA Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register. [31:0] read-write FIFO_LEVELS 0x00000440 Debug RAF, WAF, TDF levels 0x00000000 RAF_LVL Current Read-Address-FIFO fill level [23:16] read-only WAF_LVL Current Write-Address-FIFO fill level [15:8] read-only TDF_LVL Current Transfer-Data-FIFO fill level [7:0] read-only CHAN_ABORT 0x00000444 Abort an in-progress transfer sequence on one or more channels 0x00000000 CHAN_ABORT Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs. After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel. [15:0] read-write oneToClear N_CHANNELS 0x00000448 The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area. 0x00000000 N_CHANNELS [4:0] read-only CH0_DBG_CTDREQ 0x00000800 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH0_DBG_CTDREQ [5:0] read-write oneToClear CH0_DBG_TCR 0x00000804 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH0_DBG_TCR [31:0] read-only CH1_DBG_CTDREQ 0x00000840 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH1_DBG_CTDREQ [5:0] read-write oneToClear CH1_DBG_TCR 0x00000844 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH1_DBG_TCR [31:0] read-only CH2_DBG_CTDREQ 0x00000880 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH2_DBG_CTDREQ [5:0] read-write oneToClear CH2_DBG_TCR 0x00000884 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH2_DBG_TCR [31:0] read-only CH3_DBG_CTDREQ 0x000008c0 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH3_DBG_CTDREQ [5:0] read-write oneToClear CH3_DBG_TCR 0x000008c4 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH3_DBG_TCR [31:0] read-only CH4_DBG_CTDREQ 0x00000900 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH4_DBG_CTDREQ [5:0] read-write oneToClear CH4_DBG_TCR 0x00000904 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH4_DBG_TCR [31:0] read-only CH5_DBG_CTDREQ 0x00000940 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH5_DBG_CTDREQ [5:0] read-write oneToClear CH5_DBG_TCR 0x00000944 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH5_DBG_TCR [31:0] read-only CH6_DBG_CTDREQ 0x00000980 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH6_DBG_CTDREQ [5:0] read-write oneToClear CH6_DBG_TCR 0x00000984 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH6_DBG_TCR [31:0] read-only CH7_DBG_CTDREQ 0x000009c0 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH7_DBG_CTDREQ [5:0] read-write oneToClear CH7_DBG_TCR 0x000009c4 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH7_DBG_TCR [31:0] read-only CH8_DBG_CTDREQ 0x00000a00 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH8_DBG_CTDREQ [5:0] read-write oneToClear CH8_DBG_TCR 0x00000a04 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH8_DBG_TCR [31:0] read-only CH9_DBG_CTDREQ 0x00000a40 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH9_DBG_CTDREQ [5:0] read-write oneToClear CH9_DBG_TCR 0x00000a44 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH9_DBG_TCR [31:0] read-only CH10_DBG_CTDREQ 0x00000a80 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH10_DBG_CTDREQ [5:0] read-write oneToClear CH10_DBG_TCR 0x00000a84 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH10_DBG_TCR [31:0] read-only CH11_DBG_CTDREQ 0x00000ac0 Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake. 0x00000000 CH11_DBG_CTDREQ [5:0] read-write oneToClear CH11_DBG_TCR 0x00000ac4 Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer 0x00000000 CH11_DBG_TCR [31:0] read-only TIMER Controls time and alarms time is a 64 bit value indicating the time in usec since power-on timeh is the top 32 bits of time & timel is the bottom 32 bits to change time write to timelw before timehw to read time read from timelr before timehr An alarm is set by setting alarm_enable and writing to the corresponding alarm register When an alarm is pending, the corresponding alarm_running signal will be high An alarm can be cancelled before it has finished by clearing the alarm_enable When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared To clear the interrupt write a 1 to the corresponding alarm_irq 0x40054000 0 68 registers TIMER_IRQ_0 0 TIMER_IRQ_1 1 TIMER_IRQ_2 2 TIMER_IRQ_3 3 TIMEHW 0x00000000 Write to bits 63:32 of time always write timelw before timehw 0x00000000 TIMEHW [31:0] write-only TIMELW 0x00000004 Write to bits 31:0 of time writes do not get copied to time until timehw is written 0x00000000 TIMELW [31:0] write-only TIMEHR 0x00000008 Read from bits 63:32 of time always read timelr before timehr 0x00000000 TIMEHR [31:0] read-only TIMELR 0x0000000c Read from bits 31:0 of time 0x00000000 TIMELR [31:0] read-only modify ALARM0 0x00000010 Arm alarm 0, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x00000000 ALARM0 [31:0] read-write ALARM1 0x00000014 Arm alarm 1, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x00000000 ALARM1 [31:0] read-write ALARM2 0x00000018 Arm alarm 2, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x00000000 ALARM2 [31:0] read-write ALARM3 0x0000001c Arm alarm 3, and configure the time it will fire. Once armed, the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will disarm itself once it fires, and can be disarmed early using the ARMED status register. 0x00000000 ALARM3 [31:0] read-write ARMED 0x00000020 Indicates the armed/disarmed status of each alarm. A write to the corresponding ALARMx register arms the alarm. Alarms automatically disarm upon firing, but writing ones here will disarm immediately without waiting to fire. 0x00000000 ARMED [3:0] read-write oneToClear TIMERAWH 0x00000024 Raw read from bits 63:32 of time (no side effects) 0x00000000 TIMERAWH [31:0] read-only TIMERAWL 0x00000028 Raw read from bits 31:0 of time (no side effects) 0x00000000 TIMERAWL [31:0] read-only DBGPAUSE 0x0000002c Set bits high to enable pause when the corresponding debug ports are active 0x00000007 DBG1 Pause when processor 1 is in debug mode [2:2] read-write DBG0 Pause when processor 0 is in debug mode [1:1] read-write PAUSE 0x00000030 Set high to pause the timer 0x00000000 PAUSE [0:0] read-write INTR 0x00000034 Raw Interrupts 0x00000000 ALARM_3 [3:3] read-write oneToClear ALARM_2 [2:2] read-write oneToClear ALARM_1 [1:1] read-write oneToClear ALARM_0 [0:0] read-write oneToClear INTE 0x00000038 Interrupt Enable 0x00000000 ALARM_3 [3:3] read-write ALARM_2 [2:2] read-write ALARM_1 [1:1] read-write ALARM_0 [0:0] read-write INTF 0x0000003c Interrupt Force 0x00000000 ALARM_3 [3:3] read-write ALARM_2 [2:2] read-write ALARM_1 [1:1] read-write ALARM_0 [0:0] read-write INTS 0x00000040 Interrupt status after masking & forcing 0x00000000 ALARM_3 [3:3] read-only ALARM_2 [2:2] read-only ALARM_1 [1:1] read-only ALARM_0 [0:0] read-only PWM Simple PWM 0x40050000 0 180 registers PWM_IRQ_WRAP 4 CH0_CSR 0x00000000 Control and status register 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div 0 Free-running counting at rate dictated by fractional divider level 1 Fractional divider operation is gated by the PWM B pin. rise 2 Counter advances with each rising edge of the PWM B pin. fall 3 Counter advances with each falling edge of the PWM B pin. B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CH0_DIV 0x00000004 INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x00000010 INT [11:4] read-write FRAC [3:0] read-write CH0_CTR 0x00000008 Direct access to the PWM counter 0x00000000 CH0_CTR [15:0] read-write CH0_CC 0x0000000c Counter compare values 0x00000000 B [31:16] read-write A [15:0] read-write CH0_TOP 0x00000010 Counter wrap value 0x0000ffff CH0_TOP [15:0] read-write CH1_CSR 0x00000014 Control and status register 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div 0 Free-running counting at rate dictated by fractional divider level 1 Fractional divider operation is gated by the PWM B pin. rise 2 Counter advances with each rising edge of the PWM B pin. fall 3 Counter advances with each falling edge of the PWM B pin. B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CH1_DIV 0x00000018 INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x00000010 INT [11:4] read-write FRAC [3:0] read-write CH1_CTR 0x0000001c Direct access to the PWM counter 0x00000000 CH1_CTR [15:0] read-write CH1_CC 0x00000020 Counter compare values 0x00000000 B [31:16] read-write A [15:0] read-write CH1_TOP 0x00000024 Counter wrap value 0x0000ffff CH1_TOP [15:0] read-write CH2_CSR 0x00000028 Control and status register 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div 0 Free-running counting at rate dictated by fractional divider level 1 Fractional divider operation is gated by the PWM B pin. rise 2 Counter advances with each rising edge of the PWM B pin. fall 3 Counter advances with each falling edge of the PWM B pin. B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CH2_DIV 0x0000002c INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x00000010 INT [11:4] read-write FRAC [3:0] read-write CH2_CTR 0x00000030 Direct access to the PWM counter 0x00000000 CH2_CTR [15:0] read-write CH2_CC 0x00000034 Counter compare values 0x00000000 B [31:16] read-write A [15:0] read-write CH2_TOP 0x00000038 Counter wrap value 0x0000ffff CH2_TOP [15:0] read-write CH3_CSR 0x0000003c Control and status register 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div 0 Free-running counting at rate dictated by fractional divider level 1 Fractional divider operation is gated by the PWM B pin. rise 2 Counter advances with each rising edge of the PWM B pin. fall 3 Counter advances with each falling edge of the PWM B pin. B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CH3_DIV 0x00000040 INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x00000010 INT [11:4] read-write FRAC [3:0] read-write CH3_CTR 0x00000044 Direct access to the PWM counter 0x00000000 CH3_CTR [15:0] read-write CH3_CC 0x00000048 Counter compare values 0x00000000 B [31:16] read-write A [15:0] read-write CH3_TOP 0x0000004c Counter wrap value 0x0000ffff CH3_TOP [15:0] read-write CH4_CSR 0x00000050 Control and status register 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div 0 Free-running counting at rate dictated by fractional divider level 1 Fractional divider operation is gated by the PWM B pin. rise 2 Counter advances with each rising edge of the PWM B pin. fall 3 Counter advances with each falling edge of the PWM B pin. B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CH4_DIV 0x00000054 INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x00000010 INT [11:4] read-write FRAC [3:0] read-write CH4_CTR 0x00000058 Direct access to the PWM counter 0x00000000 CH4_CTR [15:0] read-write CH4_CC 0x0000005c Counter compare values 0x00000000 B [31:16] read-write A [15:0] read-write CH4_TOP 0x00000060 Counter wrap value 0x0000ffff CH4_TOP [15:0] read-write CH5_CSR 0x00000064 Control and status register 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div 0 Free-running counting at rate dictated by fractional divider level 1 Fractional divider operation is gated by the PWM B pin. rise 2 Counter advances with each rising edge of the PWM B pin. fall 3 Counter advances with each falling edge of the PWM B pin. B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CH5_DIV 0x00000068 INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x00000010 INT [11:4] read-write FRAC [3:0] read-write CH5_CTR 0x0000006c Direct access to the PWM counter 0x00000000 CH5_CTR [15:0] read-write CH5_CC 0x00000070 Counter compare values 0x00000000 B [31:16] read-write A [15:0] read-write CH5_TOP 0x00000074 Counter wrap value 0x0000ffff CH5_TOP [15:0] read-write CH6_CSR 0x00000078 Control and status register 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div 0 Free-running counting at rate dictated by fractional divider level 1 Fractional divider operation is gated by the PWM B pin. rise 2 Counter advances with each rising edge of the PWM B pin. fall 3 Counter advances with each falling edge of the PWM B pin. B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CH6_DIV 0x0000007c INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x00000010 INT [11:4] read-write FRAC [3:0] read-write CH6_CTR 0x00000080 Direct access to the PWM counter 0x00000000 CH6_CTR [15:0] read-write CH6_CC 0x00000084 Counter compare values 0x00000000 B [31:16] read-write A [15:0] read-write CH6_TOP 0x00000088 Counter wrap value 0x0000ffff CH6_TOP [15:0] read-write CH7_CSR 0x0000008c Control and status register 0x00000000 PH_ADV Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1) [7:7] write-only PH_RET Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running. [6:6] write-only DIVMODE [5:4] read-write div 0 Free-running counting at rate dictated by fractional divider level 1 Fractional divider operation is gated by the PWM B pin. rise 2 Counter advances with each rising edge of the PWM B pin. fall 3 Counter advances with each falling edge of the PWM B pin. B_INV Invert output B [3:3] read-write A_INV Invert output A [2:2] read-write PH_CORRECT 1: Enable phase-correct modulation. 0: Trailing-edge [1:1] read-write EN Enable the PWM channel. [0:0] read-write CH7_DIV 0x00000090 INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta. 0x00000010 INT [11:4] read-write FRAC [3:0] read-write CH7_CTR 0x00000094 Direct access to the PWM counter 0x00000000 CH7_CTR [15:0] read-write CH7_CC 0x00000098 Counter compare values 0x00000000 B [31:16] read-write A [15:0] read-write CH7_TOP 0x0000009c Counter wrap value 0x0000ffff CH7_TOP [15:0] read-write EN 0x000000a0 This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR. 0x00000000 CH7 [7:7] read-write CH6 [6:6] read-write CH5 [5:5] read-write CH4 [4:4] read-write CH3 [3:3] read-write CH2 [2:2] read-write CH1 [1:1] read-write CH0 [0:0] read-write INTR 0x000000a4 Raw Interrupts 0x00000000 CH7 [7:7] read-write oneToClear CH6 [6:6] read-write oneToClear CH5 [5:5] read-write oneToClear CH4 [4:4] read-write oneToClear CH3 [3:3] read-write oneToClear CH2 [2:2] read-write oneToClear CH1 [1:1] read-write oneToClear CH0 [0:0] read-write oneToClear INTE 0x000000a8 Interrupt Enable 0x00000000 CH7 [7:7] read-write CH6 [6:6] read-write CH5 [5:5] read-write CH4 [4:4] read-write CH3 [3:3] read-write CH2 [2:2] read-write CH1 [1:1] read-write CH0 [0:0] read-write INTF 0x000000ac Interrupt Force 0x00000000 CH7 [7:7] read-write CH6 [6:6] read-write CH5 [5:5] read-write CH4 [4:4] read-write CH3 [3:3] read-write CH2 [2:2] read-write CH1 [1:1] read-write CH0 [0:0] read-write INTS 0x000000b0 Interrupt status after masking & forcing 0x00000000 CH7 [7:7] read-only CH6 [6:6] read-only CH5 [5:5] read-only CH4 [4:4] read-only CH3 [3:3] read-only CH2 [2:2] read-only CH1 [1:1] read-only CH0 [0:0] read-only ADC Control and data interface to SAR ADC 0x4004c000 0 36 registers ADC_IRQ_FIFO 22 CS 0x00000000 ADC Control and Status 0x00000000 RROBIN Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. The first channel to be sampled will be the one currently indicated by AINSEL. AINSEL will be updated after each conversion with the newly-selected channel. [20:16] read-write AINSEL Select analog mux input. Updated automatically in round-robin mode. [14:12] read-write ERR_STICKY Some past ADC conversion encountered an error. Write 1 to clear. [10:10] read-write oneToClear ERR The most recent ADC conversion encountered an error; result is undefined or noisy. [9:9] read-only READY 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 0 whilst conversion in progress. [8:8] read-only START_MANY Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes. [3:3] read-write START_ONCE Start a single conversion. Self-clearing. Ignored if start_many is asserted. [2:2] write-only TS_EN Power on temperature sensor. 1 - enabled. 0 - disabled. [1:1] read-write EN Power on ADC and enable its clock. 1 - enabled. 0 - disabled. [0:0] read-write RESULT 0x00000004 Result of most recent ADC conversion 0x00000000 RESULT [11:0] read-only FCS 0x00000008 FIFO control and status 0x00000000 THRESH DREQ/IRQ asserted when level >= threshold [27:24] read-write LEVEL The number of conversion results currently waiting in the FIFO [19:16] read-only OVER 1 if the FIFO has been overflowed. Write 1 to clear. [11:11] read-write oneToClear UNDER 1 if the FIFO has been underflowed. Write 1 to clear. [10:10] read-write oneToClear FULL [9:9] read-only EMPTY [8:8] read-only DREQ_EN If 1: assert DMA requests when FIFO contains data [3:3] read-write ERR If 1: conversion error bit appears in the FIFO alongside the result [2:2] read-write SHIFT If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers. [1:1] read-write EN If 1: write result to the FIFO after each conversion. [0:0] read-write FIFO 0x0000000c Conversion result FIFO 0x00000000 ERR 1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted. [15:15] read-only modify VAL [11:0] read-only modify DIV 0x00000010 Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256 0x00000000 INT Integer part of clock divisor. [23:8] read-write FRAC Fractional part of clock divisor. First-order delta-sigma. [7:0] read-write INTR 0x00000014 Raw Interrupts 0x00000000 FIFO Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. [0:0] read-only INTE 0x00000018 Interrupt Enable 0x00000000 FIFO Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. [0:0] read-write INTF 0x0000001c Interrupt Force 0x00000000 FIFO Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. [0:0] read-write INTS 0x00000020 Interrupt status after masking & forcing 0x00000000 FIFO Triggered when the sample FIFO reaches a certain level. This level can be programmed via the FCS_THRESH field. [0:0] read-only I2C0 DW_apb_i2c address block List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time): IC_ULTRA_FAST_MODE ................ 0x0 IC_UFM_TBUF_CNT_DEFAULT ........... 0x8 IC_UFM_SCL_LOW_COUNT .............. 0x0008 IC_UFM_SCL_HIGH_COUNT ............. 0x0006 IC_TX_TL .......................... 0x0 IC_TX_CMD_BLOCK ................... 0x1 IC_HAS_DMA ........................ 0x1 IC_HAS_ASYNC_FIFO ................. 0x0 IC_SMBUS_ARP ...................... 0x0 IC_FIRST_DATA_BYTE_STATUS ......... 0x1 IC_INTR_IO ........................ 0x1 IC_MASTER_MODE .................... 0x1 IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1 IC_INTR_POL ....................... 0x1 IC_OPTIONAL_SAR ................... 0x0 IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055 IC_DEFAULT_SLAVE_ADDR ............. 0x055 IC_DEFAULT_HS_SPKLEN .............. 0x1 IC_FS_SCL_HIGH_COUNT .............. 0x0006 IC_HS_SCL_LOW_COUNT ............... 0x0008 IC_DEVICE_ID_VALUE ................ 0x0 IC_10BITADDR_MASTER ............... 0x0 IC_CLK_FREQ_OPTIMIZATION .......... 0x0 IC_DEFAULT_FS_SPKLEN .............. 0x7 IC_ADD_ENCODED_PARAMS ............. 0x0 IC_DEFAULT_SDA_HOLD ............... 0x000001 IC_DEFAULT_SDA_SETUP .............. 0x64 IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0 IC_CLOCK_PERIOD ................... 100 IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1 IC_RESTART_EN ..................... 0x1 IC_TX_CMD_BLOCK_DEFAULT ........... 0x0 IC_BUS_CLEAR_FEATURE .............. 0x0 IC_CAP_LOADING .................... 100 IC_FS_SCL_LOW_COUNT ............... 0x000d APB_DATA_WIDTH .................... 32 IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_SLV_DATA_NACK_ONLY ............. 0x1 IC_10BITADDR_SLAVE ................ 0x0 IC_CLK_TYPE ....................... 0x0 IC_SMBUS_UDID_MSB ................. 0x0 IC_SMBUS_SUSPEND_ALERT ............ 0x0 IC_HS_SCL_HIGH_COUNT .............. 0x0006 IC_SLV_RESTART_DET_EN ............. 0x1 IC_SMBUS .......................... 0x0 IC_OPTIONAL_SAR_DEFAULT ........... 0x0 IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0 IC_USE_COUNTS ..................... 0x0 IC_RX_BUFFER_DEPTH ................ 16 IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff IC_RX_FULL_HLD_BUS_EN ............. 0x1 IC_SLAVE_DISABLE .................. 0x1 IC_RX_TL .......................... 0x0 IC_DEVICE_ID ...................... 0x0 IC_HC_COUNT_VALUES ................ 0x0 I2C_DYNAMIC_TAR_UPDATE ............ 0 IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff IC_HS_MASTER_CODE ................. 0x1 IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff IC_SS_SCL_HIGH_COUNT .............. 0x0028 IC_SS_SCL_LOW_COUNT ............... 0x002f IC_MAX_SPEED_MODE ................. 0x2 IC_STAT_FOR_CLK_STRETCH ........... 0x0 IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0 IC_DEFAULT_UFM_SPKLEN ............. 0x1 IC_TX_BUFFER_DEPTH ................ 16 0x40044000 0 256 registers I2C0_IRQ 23 IC_CON 0x00000000 I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only. 0x00000065 STOP_DET_IF_MASTER_ACTIVE Master issues the STOP_DET interrupt irrespective of whether master is active or not [10:10] read-only RX_FIFO_FULL_HLD_CTRL This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0. [9:9] read-write DISABLED 0 Overflow when RX_FIFO is full ENABLED 1 Hold bus when RX_FIFO is full TX_EMPTY_CTRL This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. [8:8] read-write DISABLED 0 Default behaviour of TX_EMPTY interrupt ENABLED 1 Controlled generation of TX_EMPTY interrupt STOP_DET_IFADDRESSED In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). [7:7] read-write DISABLED 0 slave issues STOP_DET intr always ENABLED 1 slave issues STOP_DET intr only if addressed IC_SLAVE_DISABLE This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. [6:6] read-write SLAVE_ENABLED 0 Slave mode is enabled SLAVE_DISABLED 1 Slave mode is disabled IC_RESTART_EN Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: ENABLED [5:5] read-write DISABLED 0 Master restart disabled ENABLED 1 Master restart enabled IC_10BITADDR_MASTER Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing [4:4] read-write ADDR_7BITS 0 Master 7Bit addressing mode ADDR_10BITS 1 Master 10Bit addressing mode IC_10BITADDR_SLAVE When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. [3:3] read-write ADDR_7BITS 0 Slave 7Bit addressing ADDR_10BITS 1 Slave 10Bit addressing SPEED These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 [2:1] read-write STANDARD 1 Standard Speed mode of operation FAST 2 Fast or Fast Plus mode of operation HIGH 3 High Speed mode of operation MASTER_MODE This bit controls whether the DW_apb_i2c master is enabled. NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. [0:0] read-write DISABLED 0 Master mode is disabled ENABLED 1 Master mode is enabled IC_TAR 0x00000004 I2C Target Address Register This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only. 0x00000055 SPECIAL This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0 [11:11] read-write DISABLED 0 Disables programming of GENERAL_CALL or START_BYTE transmission ENABLED 1 Enables programming of GENERAL_CALL or START_BYTE transmission GC_OR_START If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0 [10:10] read-write GENERAL_CALL 0 GENERAL_CALL byte transmission START_BYTE 1 START byte transmission IC_TAR This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave. [9:0] read-write IC_SAR 0x00000008 I2C Slave Address Register 0x00000055 IC_SAR The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <<table_I2C_firstbyte_bit_defs>> for a complete list of these reserved values. [9:0] read-write IC_DATA_CMD 0x00000010 I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging. 0x00000000 FIRST_DATA_BYTE Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8, 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit. 2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not). 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status. [11:11] read-only INACTIVE 0 Sequential data byte received ACTIVE 1 Non sequential data byte received RESTART This bit controls whether a RESTART is issued before the byte is sent or received. 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead. Reset value: 0x0 [10:10] write-only DISABLE 0 Don't Issue RESTART before this command ENABLE 1 Issue RESTART before this command STOP This bit controls whether a STOP is issued after the byte is sent or received. - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0 [9:9] write-only DISABLE 0 Don't Issue STOP after this command ENABLE 1 Issue STOP after this command CMD This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. Reset value: 0x0 [8:8] write-only WRITE 0 Master Write Command READ 1 Master Read Command DAT This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface. Reset value: 0x0 [7:0] read-write IC_SS_SCL_HCNT 0x00000014 Standard Speed I2C Clock SCL High Count Register 0x00000028 IC_SS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10. [15:0] read-write IC_SS_SCL_LCNT 0x00000018 Standard Speed I2C Clock SCL Low Count Register 0x0000002f IC_SS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration' This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed. [15:0] read-write IC_FS_SCL_HCNT 0x0000001c Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register 0x00000006 IC_FS_SCL_HCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. [15:0] read-write IC_FS_SCL_LCNT 0x00000020 Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register 0x0000000d IC_FS_SCL_LCNT This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'. This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8. [15:0] read-write IC_INTR_STAT 0x0000002c I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. 0x00000000 R_RESTART_DET See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0 [12:12] read-only INACTIVE 0 R_RESTART_DET interrupt is inactive ACTIVE 1 R_RESTART_DET interrupt is active R_GEN_CALL See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0 [11:11] read-only INACTIVE 0 R_GEN_CALL interrupt is inactive ACTIVE 1 R_GEN_CALL interrupt is active R_START_DET See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0 [10:10] read-only INACTIVE 0 R_START_DET interrupt is inactive ACTIVE 1 R_START_DET interrupt is active R_STOP_DET See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0 [9:9] read-only INACTIVE 0 R_STOP_DET interrupt is inactive ACTIVE 1 R_STOP_DET interrupt is active R_ACTIVITY See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0 [8:8] read-only INACTIVE 0 R_ACTIVITY interrupt is inactive ACTIVE 1 R_ACTIVITY interrupt is active R_RX_DONE See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0 [7:7] read-only INACTIVE 0 R_RX_DONE interrupt is inactive ACTIVE 1 R_RX_DONE interrupt is active R_TX_ABRT See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0 [6:6] read-only INACTIVE 0 R_TX_ABRT interrupt is inactive ACTIVE 1 R_TX_ABRT interrupt is active R_RD_REQ See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0 [5:5] read-only INACTIVE 0 R_RD_REQ interrupt is inactive ACTIVE 1 R_RD_REQ interrupt is active R_TX_EMPTY See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0 [4:4] read-only INACTIVE 0 R_TX_EMPTY interrupt is inactive ACTIVE 1 R_TX_EMPTY interrupt is active R_TX_OVER See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0 [3:3] read-only INACTIVE 0 R_TX_OVER interrupt is inactive ACTIVE 1 R_TX_OVER interrupt is active R_RX_FULL See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0 [2:2] read-only INACTIVE 0 R_RX_FULL interrupt is inactive ACTIVE 1 R_RX_FULL interrupt is active R_RX_OVER See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0 [1:1] read-only INACTIVE 0 R_RX_OVER interrupt is inactive ACTIVE 1 R_RX_OVER interrupt is active R_RX_UNDER See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0 [0:0] read-only INACTIVE 0 RX_UNDER interrupt is inactive ACTIVE 1 RX_UNDER interrupt is active IC_INTR_MASK 0x00000030 I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. 0x000008ff M_RESTART_DET This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 [12:12] read-write ENABLED 0 RESTART_DET interrupt is masked DISABLED 1 RESTART_DET interrupt is unmasked M_GEN_CALL This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1 [11:11] read-write ENABLED 0 GEN_CALL interrupt is masked DISABLED 1 GEN_CALL interrupt is unmasked M_START_DET This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 [10:10] read-write ENABLED 0 START_DET interrupt is masked DISABLED 1 START_DET interrupt is unmasked M_STOP_DET This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 [9:9] read-write ENABLED 0 STOP_DET interrupt is masked DISABLED 1 STOP_DET interrupt is unmasked M_ACTIVITY This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0 [8:8] read-write ENABLED 0 ACTIVITY interrupt is masked DISABLED 1 ACTIVITY interrupt is unmasked M_RX_DONE This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1 [7:7] read-write ENABLED 0 RX_DONE interrupt is masked DISABLED 1 RX_DONE interrupt is unmasked M_TX_ABRT This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1 [6:6] read-write ENABLED 0 TX_ABORT interrupt is masked DISABLED 1 TX_ABORT interrupt is unmasked M_RD_REQ This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1 [5:5] read-write ENABLED 0 RD_REQ interrupt is masked DISABLED 1 RD_REQ interrupt is unmasked M_TX_EMPTY This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1 [4:4] read-write ENABLED 0 TX_EMPTY interrupt is masked DISABLED 1 TX_EMPTY interrupt is unmasked M_TX_OVER This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 [3:3] read-write ENABLED 0 TX_OVER interrupt is masked DISABLED 1 TX_OVER interrupt is unmasked M_RX_FULL This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1 [2:2] read-write ENABLED 0 RX_FULL interrupt is masked DISABLED 1 RX_FULL interrupt is unmasked M_RX_OVER This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 [1:1] read-write ENABLED 0 RX_OVER interrupt is masked DISABLED 1 RX_OVER interrupt is unmasked M_RX_UNDER This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1 [0:0] read-write ENABLED 0 RX_UNDER interrupt is masked DISABLED 1 RX_UNDER interrupt is unmasked IC_RAW_INTR_STAT 0x00000034 I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. 0x00000000 RESTART_DET Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt. Reset value: 0x0 [12:12] read-only INACTIVE 0 RESTART_DET interrupt is inactive ACTIVE 1 RESTART_DET interrupt is active GEN_CALL Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0 [11:11] read-only INACTIVE 0 GEN_CALL interrupt is inactive ACTIVE 1 GEN_CALL interrupt is active START_DET Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0 [10:10] read-only INACTIVE 0 START_DET interrupt is inactive ACTIVE 1 START_DET interrupt is active STOP_DET Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0 [9:9] read-only INACTIVE 0 STOP_DET interrupt is inactive ACTIVE 1 STOP_DET interrupt is active ACTIVITY This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0 [8:8] read-only INACTIVE 0 RAW_INTR_ACTIVITY interrupt is inactive ACTIVE 1 RAW_INTR_ACTIVITY interrupt is active RX_DONE When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0 [7:7] read-only INACTIVE 0 RX_DONE interrupt is inactive ACTIVE 1 RX_DONE interrupt is active TX_ABRT This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0 [6:6] read-only INACTIVE 0 TX_ABRT interrupt is inactive ACTIVE 1 TX_ABRT interrupt is active RD_REQ This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0 [5:5] read-only INACTIVE 0 RD_REQ interrupt is inactive ACTIVE 1 RD_REQ interrupt is active TX_EMPTY The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0. [4:4] read-only INACTIVE 0 TX_EMPTY interrupt is inactive ACTIVE 1 TX_EMPTY interrupt is active TX_OVER Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 [3:3] read-only INACTIVE 0 TX_OVER interrupt is inactive ACTIVE 1 TX_OVER interrupt is active RX_FULL Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0 [2:2] read-only INACTIVE 0 RX_FULL interrupt is inactive ACTIVE 1 RX_FULL interrupt is active RX_OVER Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows. Reset value: 0x0 [1:1] read-only INACTIVE 0 RX_OVER interrupt is inactive ACTIVE 1 RX_OVER interrupt is active RX_UNDER Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 [0:0] read-only INACTIVE 0 RX_UNDER interrupt is inactive ACTIVE 1 RX_UNDER interrupt is active IC_RX_TL 0x00000038 I2C Receive FIFO Threshold Register 0x00000000 RX_TL Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. [7:0] read-write IC_TX_TL 0x0000003c I2C Transmit FIFO Threshold Register 0x00000000 TX_TL Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries. [7:0] read-write IC_CLR_INTR 0x00000040 Clear Combined and Individual Interrupt Register 0x00000000 CLR_INTR Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0 [0:0] read-only IC_CLR_RX_UNDER 0x00000044 Clear RX_UNDER Interrupt Register 0x00000000 CLR_RX_UNDER Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_RX_OVER 0x00000048 Clear RX_OVER Interrupt Register 0x00000000 CLR_RX_OVER Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_TX_OVER 0x0000004c Clear TX_OVER Interrupt Register 0x00000000 CLR_TX_OVER Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_RD_REQ 0x00000050 Clear RD_REQ Interrupt Register 0x00000000 CLR_RD_REQ Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_TX_ABRT 0x00000054 Clear TX_ABRT Interrupt Register 0x00000000 CLR_TX_ABRT Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE. Reset value: 0x0 [0:0] read-only IC_CLR_RX_DONE 0x00000058 Clear RX_DONE Interrupt Register 0x00000000 CLR_RX_DONE Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_ACTIVITY 0x0000005c Clear ACTIVITY Interrupt Register 0x00000000 CLR_ACTIVITY Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_STOP_DET 0x00000060 Clear STOP_DET Interrupt Register 0x00000000 CLR_STOP_DET Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_START_DET 0x00000064 Clear START_DET Interrupt Register 0x00000000 CLR_START_DET Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_CLR_GEN_CALL 0x00000068 Clear GEN_CALL Interrupt Register 0x00000000 CLR_GEN_CALL Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_ENABLE 0x0000006c I2C Enable Register 0x00000000 TX_CMD_BLOCK In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT [2:2] read-write NOT_BLOCKED 0 Tx Command execution not blocked BLOCKED 1 Tx Command execution blocked ABORT When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation. For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'. Reset value: 0x0 [1:1] read-write DISABLE 0 ABORT operation not in progress ENABLED 1 ABORT operation in progress ENABLE Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'. When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer. In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c' Reset value: 0x0 [0:0] read-write DISABLED 0 I2C is disabled ENABLED 1 I2C is enabled IC_STATUS 0x00000070 I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 0x00000006 SLV_ACTIVITY Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0 [6:6] read-only IDLE 0 Slave is idle ACTIVE 1 Slave not idle MST_ACTIVITY Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits. Reset value: 0x0 [5:5] read-only IDLE 0 Master is idle ACTIVE 1 Master not idle RFF Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 [4:4] read-only NOT_FULL 0 Rx FIFO not full FULL 1 Rx FIFO is full RFNE Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 [3:3] read-only EMPTY 0 Rx FIFO is empty NOT_EMPTY 1 Rx FIFO not empty TFE Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1 [2:2] read-only NON_EMPTY 0 Tx FIFO not empty EMPTY 1 Tx FIFO is empty TFNF Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 [1:1] read-only FULL 0 Tx FIFO is full NOT_FULL 1 Tx FIFO not full ACTIVITY I2C Activity Status. Reset value: 0x0 [0:0] read-only INACTIVE 0 I2C is idle ACTIVE 1 I2C is active IC_TXFLR 0x00000074 I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO. 0x00000000 TXFLR Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0 [4:0] read-only IC_RXFLR 0x00000078 I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO. 0x00000000 RXFLR Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0 [4:0] read-only IC_SDA_HOLD 0x0000007c I2C SDA Hold Time Length Register The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode. Writes to this register succeed only when IC_ENABLE[0]=0. The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented. The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. 0x00000001 IC_SDA_RX_HOLD Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD[23:16]. [23:16] read-write IC_SDA_TX_HOLD Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD[15:0]. [15:0] read-write IC_TX_ABRT_SOURCE 0x00000080 I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted. 0x00000000 TX_FLUSH_CNT This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter [31:23] read-only ABRT_USER_ABRT This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter [16:16] read-only ABRT_USER_ABRT_VOID 0 Transfer abort detected by master- scenario not present ABRT_USER_ABRT_GENERATED 1 Transfer abort detected by master ABRT_SLVRD_INTX 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter [15:15] read-only ABRT_SLVRD_INTX_VOID 0 Slave trying to transmit to remote master in read mode- scenario not present ABRT_SLVRD_INTX_GENERATED 1 Slave trying to transmit to remote master in read mode ABRT_SLV_ARBLOST This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter [14:14] read-only ABRT_SLV_ARBLOST_VOID 0 Slave lost arbitration to remote master- scenario not present ABRT_SLV_ARBLOST_GENERATED 1 Slave lost arbitration to remote master ABRT_SLVFLUSH_TXFIFO This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter [13:13] read-only ABRT_SLVFLUSH_TXFIFO_VOID 0 Slave flushes existing data in TX-FIFO upon getting read command- scenario not present ABRT_SLVFLUSH_TXFIFO_GENERATED 1 Slave flushes existing data in TX-FIFO upon getting read command ARB_LOST This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter [12:12] read-only ABRT_LOST_VOID 0 Master or Slave-Transmitter lost arbitration- scenario not present ABRT_LOST_GENERATED 1 Master or Slave-Transmitter lost arbitration ABRT_MASTER_DIS This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [11:11] read-only ABRT_MASTER_DIS_VOID 0 User initiating master operation when MASTER disabled- scenario not present ABRT_MASTER_DIS_GENERATED 1 User initiating master operation when MASTER disabled ABRT_10B_RD_NORSTRT This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver [10:10] read-only ABRT_10B_RD_VOID 0 Master not trying to read in 10Bit addressing mode when RESTART disabled ABRT_10B_RD_GENERATED 1 Master trying to read in 10Bit addressing mode when RESTART disabled ABRT_SBYTE_NORSTRT To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte. Reset value: 0x0 Role of DW_apb_i2c: Master [9:9] read-only ABRT_SBYTE_NORSTRT_VOID 0 User trying to send START byte when RESTART disabled- scenario not present ABRT_SBYTE_NORSTRT_GENERATED 1 User trying to send START byte when RESTART disabled ABRT_HS_NORSTRT This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [8:8] read-only ABRT_HS_NORSTRT_VOID 0 User trying to switch Master to HS mode when RESTART disabled- scenario not present ABRT_HS_NORSTRT_GENERATED 1 User trying to switch Master to HS mode when RESTART disabled ABRT_SBYTE_ACKDET This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master [7:7] read-only ABRT_SBYTE_ACKDET_VOID 0 ACK detected for START byte- scenario not present ABRT_SBYTE_ACKDET_GENERATED 1 ACK detected for START byte ABRT_HS_ACKDET This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master [6:6] read-only ABRT_HS_ACK_VOID 0 HS Master code ACKed in HS Mode- scenario not present ABRT_HS_ACK_GENERATED 1 HS Master code ACKed in HS Mode ABRT_GCALL_READ This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter [5:5] read-only ABRT_GCALL_READ_VOID 0 GCALL is followed by read from bus-scenario not present ABRT_GCALL_READ_GENERATED 1 GCALL is followed by read from bus ABRT_GCALL_NOACK This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter [4:4] read-only ABRT_GCALL_NOACK_VOID 0 GCALL not ACKed by any slave-scenario not present ABRT_GCALL_NOACK_GENERATED 1 GCALL not ACKed by any slave ABRT_TXDATA_NOACK This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s). Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter [3:3] read-only ABRT_TXDATA_NOACK_VOID 0 Transmitted data non-ACKed by addressed slave-scenario not present ABRT_TXDATA_NOACK_GENERATED 1 Transmitted data not ACKed by addressed slave ABRT_10ADDR2_NOACK This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [2:2] read-only INACTIVE 0 This abort is not generated ACTIVE 1 Byte 2 of 10Bit Address not ACKed by any slave ABRT_10ADDR1_NOACK This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [1:1] read-only INACTIVE 0 This abort is not generated ACTIVE 1 Byte 1 of 10Bit Address not ACKed by any slave ABRT_7B_ADDR_NOACK This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver [0:0] read-only INACTIVE 0 This abort is not generated ACTIVE 1 This abort is generated because of NOACK for 7-bit address IC_SLV_DATA_NACK_ONLY 0x00000084 Generate Slave Data NACK Register The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect. A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit. 0x00000000 NACK Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer. When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0 [0:0] read-write DISABLED 0 Slave receiver generates NACK normally ENABLED 1 Slave receiver generates NACK upon data reception only IC_DMA_CR 0x00000088 DMA Control Register The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE. 0x00000000 TDMAE Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 [1:1] read-write DISABLED 0 transmit FIFO DMA channel disabled ENABLED 1 Transmit FIFO DMA channel enabled RDMAE Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 [0:0] read-write DISABLED 0 Receive FIFO DMA channel disabled ENABLED 1 Receive FIFO DMA channel enabled IC_DMA_TDLR 0x0000008c DMA Transmit Data Level Register 0x00000000 DMATDL Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1. Reset value: 0x0 [3:0] read-write IC_DMA_RDLR 0x00000090 I2C Receive Data Level Register 0x00000000 DMARDL Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0 [3:0] read-write IC_SDA_SETUP 0x00000094 I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. Writes to this register succeed only when IC_ENABLE[0] = 0. Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter. 0x00000064 SDA_SETUP SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. [7:0] read-write IC_ACK_GENERAL_CALL 0x00000098 I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode. 0x00000001 ACK_GEN_CALL ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe). [0:0] read-write DISABLED 0 Generate NACK for a General Call ENABLED 1 Generate ACK for a General Call IC_ENABLE_STATUS 0x0000009c I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled. If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1. If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'. Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities. 0x00000000 SLV_RX_DATA_LOST Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 [2:2] read-only INACTIVE 0 Slave RX Data is not lost ACTIVE 1 Slave RX Data is lost SLV_DISABLED_WHILE_BUSY Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 [1:1] read-only INACTIVE 0 Slave is disabled when it is idle ACTIVE 1 Slave is disabled when it is active IC_EN ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0 [0:0] read-only DISABLED 0 I2C disabled ENABLED 1 I2C enabled IC_FS_SPKLEN 0x000000a0 I2C SS, FS or FM+ spike suppression limit This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1. 0x00000007 IC_FS_SPKLEN This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'. [7:0] read-write IC_CLR_RESTART_DET 0x000000a8 Clear RESTART_DET Interrupt Register 0x00000000 CLR_RESTART_DET Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0 [0:0] read-only IC_COMP_PARAM_1 0x000000f4 Component Parameter Register 1 Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters 0x00000000 TX_BUFFER_DEPTH TX Buffer Depth = 16 [23:16] read-only RX_BUFFER_DEPTH RX Buffer Depth = 16 [15:8] read-only ADD_ENCODED_PARAMS Encoded parameters not visible [7:7] read-only HAS_DMA DMA handshaking signals are enabled [6:6] read-only INTR_IO COMBINED Interrupt outputs [5:5] read-only HC_COUNT_VALUES Programmable count values for each mode. [4:4] read-only MAX_SPEED_MODE MAX SPEED MODE = FAST MODE [3:2] read-only APB_DATA_WIDTH APB data bus width is 32 bits [1:0] read-only IC_COMP_VERSION 0x000000f8 I2C Component Version Register 0x3230312a IC_COMP_VERSION [31:0] read-only IC_COMP_TYPE 0x000000fc I2C Component Type Register 0x44570140 IC_COMP_TYPE Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number. [31:0] read-only I2C1 0x40048000 I2C1_IRQ 24 SPI0 0x4003c000 0 4096 registers SPI0_IRQ 18 SSPCR0 0x00000000 Control register 0, SSPCR0 on page 3-4 0x00000000 SCR Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255. [15:8] read-write SPH SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. [7:7] read-write SPO SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10. [6:6] read-write FRF Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation. [5:4] read-write DSS Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data. [3:0] read-write SSPCR1 0x00000004 Control register 1, SSPCR1 on page 3-5 0x00000000 SOD Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode. [3:3] read-write MS Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave. [2:2] read-write SSE Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled. [1:1] read-write LBM Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally. [0:0] read-write SSPDR 0x00000008 Data register, SSPDR on page 3-6 0x00000000 DATA Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies. [15:0] read-write modify SSPSR 0x0000000c Status register, SSPSR on page 3-7 0x00000003 BSY PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty. [4:4] read-only RFF Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. [3:3] read-only RNE Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty. [2:2] read-only TNF Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full. [1:1] read-only TFE Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. [0:0] read-only SSPCPSR 0x00000010 Clock prescale register, SSPCPSR on page 3-8 0x00000000 CPSDVSR Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads. [7:0] read-write SSPIMSC 0x00000014 Interrupt mask set or clear register, SSPIMSC on page 3-9 0x00000000 TXIM Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked. [3:3] read-write RXIM Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked. [2:2] read-write RTIM Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked. [1:1] read-write RORIM Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked. [0:0] read-write SSPRIS 0x00000018 Raw interrupt status register, SSPRIS on page 3-10 0x00000008 TXRIS Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt [3:3] read-only RXRIS Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt [2:2] read-only RTRIS Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt [1:1] read-only RORRIS Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt [0:0] read-only SSPMIS 0x0000001c Masked interrupt status register, SSPMIS on page 3-11 0x00000000 TXMIS Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt [3:3] read-only RXMIS Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt [2:2] read-only RTMIS Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt [1:1] read-only RORMIS Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt [0:0] read-only SSPICR 0x00000020 Interrupt clear register, SSPICR on page 3-11 0x00000000 RTIC Clears the SSPRTINTR interrupt [1:1] read-write oneToClear RORIC Clears the SSPRORINTR interrupt [0:0] read-write oneToClear SSPDMACR 0x00000024 DMA control register, SSPDMACR on page 3-12 0x00000000 TXDMAE Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled. [1:1] read-write RXDMAE Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled. [0:0] read-write SSPPERIPHID0 0x00000fe0 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0x00000022 PARTNUMBER0 These bits read back as 0x22 [7:0] read-only SSPPERIPHID1 0x00000fe4 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0x00000010 DESIGNER0 These bits read back as 0x1 [7:4] read-only PARTNUMBER1 These bits read back as 0x0 [3:0] read-only SSPPERIPHID2 0x00000fe8 Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0x00000034 REVISION These bits return the peripheral revision [7:4] read-only DESIGNER1 These bits read back as 0x4 [3:0] read-only SSPPERIPHID3 0x00000fec Peripheral identification registers, SSPPeriphID0-3 on page 3-13 0x00000000 CONFIGURATION These bits read back as 0x00 [7:0] read-only SSPPCELLID0 0x00000ff0 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 0x0000000d SSPPCELLID0 These bits read back as 0x0D [7:0] read-only SSPPCELLID1 0x00000ff4 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 0x000000f0 SSPPCELLID1 These bits read back as 0xF0 [7:0] read-only SSPPCELLID2 0x00000ff8 PrimeCell identification registers, SSPPCellID0-3 on page 3-16 0x00000005 SSPPCELLID2 These bits read back as 0x05 [7:0] read-only SSPPCELLID3 0x00000ffc PrimeCell identification registers, SSPPCellID0-3 on page 3-16 0x000000b1 SSPPCELLID3 These bits read back as 0xB1 [7:0] read-only SPI1 0x40040000 SPI1_IRQ 19 PIO0 Programmable IO block 0x50200000 0 324 registers PIO0_IRQ_0 7 PIO0_IRQ_1 8 CTRL 0x00000000 PIO control register 0x00000000 CLKDIV_RESTART Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep. Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync. Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly. [11:8] write-only SM_RESTART Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution. Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY. The program counter, the contents of the output shift register and the X/Y scratch registers are not affected. [7:4] write-only SM_ENABLE Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously. [3:0] read-write FSTAT 0x00000004 FIFO status register 0x0f000f00 TXEMPTY State machine TX FIFO is empty [27:24] read-only TXFULL State machine TX FIFO is full [19:16] read-only RXEMPTY State machine RX FIFO is empty [11:8] read-only RXFULL State machine RX FIFO is full [3:0] read-only FDEBUG 0x00000008 FIFO debug register 0x00000000 TXSTALL State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear. [27:24] read-write oneToClear TXOVER TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor. [19:16] read-write oneToClear RXUNDER RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error. [11:8] read-write oneToClear RXSTALL State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear. [3:0] read-write oneToClear FLEVEL 0x0000000c FIFO levels 0x00000000 RX3 [31:28] read-only TX3 [27:24] read-only RX2 [23:20] read-only TX2 [19:16] read-only RX1 [15:12] read-only TX1 [11:8] read-only RX0 [7:4] read-only TX0 [3:0] read-only TXF0 0x00000010 Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. 0x00000000 TXF0 [31:0] write-only TXF1 0x00000014 Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. 0x00000000 TXF1 [31:0] write-only TXF2 0x00000018 Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. 0x00000000 TXF2 [31:0] write-only TXF3 0x0000001c Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. 0x00000000 TXF3 [31:0] write-only RXF0 0x00000020 Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. 0x00000000 RXF0 [31:0] read-only modify RXF1 0x00000024 Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. 0x00000000 RXF1 [31:0] read-only modify RXF2 0x00000028 Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. 0x00000000 RXF2 [31:0] read-only modify RXF3 0x0000002c Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined. 0x00000000 RXF3 [31:0] read-only modify IRQ 0x00000030 State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag. Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE. 0x00000000 IRQ [7:0] read-write oneToClear IRQ_FORCE 0x00000034 Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines. 0x00000000 IRQ_FORCE [7:0] write-only INPUT_SYNC_BYPASS 0x00000038 There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO. 0 -> input is synchronized (default) 1 -> synchronizer is bypassed If in doubt, leave this register as all zeroes. 0x00000000 INPUT_SYNC_BYPASS [31:0] read-write DBG_PADOUT 0x0000003c Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. 0x00000000 DBG_PADOUT [31:0] read-only DBG_PADOE 0x00000040 Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. 0x00000000 DBG_PADOE [31:0] read-only DBG_CFGINFO 0x00000044 The PIO hardware has some free parameters that may vary between chip products. These should be provided in the chip datasheet, but are also exposed here. 0x00000000 IMEM_SIZE The size of the instruction memory, measured in units of one instruction [21:16] read-only SM_COUNT The number of state machines this PIO instance is equipped with. [11:8] read-only FIFO_DEPTH The depth of the state machine TX/RX FIFOs, measured in words. Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double this depth. [5:0] read-only INSTR_MEM0 0x00000048 Write-only access to instruction memory location 0 0x00000000 INSTR_MEM0 [15:0] write-only INSTR_MEM1 0x0000004c Write-only access to instruction memory location 1 0x00000000 INSTR_MEM1 [15:0] write-only INSTR_MEM2 0x00000050 Write-only access to instruction memory location 2 0x00000000 INSTR_MEM2 [15:0] write-only INSTR_MEM3 0x00000054 Write-only access to instruction memory location 3 0x00000000 INSTR_MEM3 [15:0] write-only INSTR_MEM4 0x00000058 Write-only access to instruction memory location 4 0x00000000 INSTR_MEM4 [15:0] write-only INSTR_MEM5 0x0000005c Write-only access to instruction memory location 5 0x00000000 INSTR_MEM5 [15:0] write-only INSTR_MEM6 0x00000060 Write-only access to instruction memory location 6 0x00000000 INSTR_MEM6 [15:0] write-only INSTR_MEM7 0x00000064 Write-only access to instruction memory location 7 0x00000000 INSTR_MEM7 [15:0] write-only INSTR_MEM8 0x00000068 Write-only access to instruction memory location 8 0x00000000 INSTR_MEM8 [15:0] write-only INSTR_MEM9 0x0000006c Write-only access to instruction memory location 9 0x00000000 INSTR_MEM9 [15:0] write-only INSTR_MEM10 0x00000070 Write-only access to instruction memory location 10 0x00000000 INSTR_MEM10 [15:0] write-only INSTR_MEM11 0x00000074 Write-only access to instruction memory location 11 0x00000000 INSTR_MEM11 [15:0] write-only INSTR_MEM12 0x00000078 Write-only access to instruction memory location 12 0x00000000 INSTR_MEM12 [15:0] write-only INSTR_MEM13 0x0000007c Write-only access to instruction memory location 13 0x00000000 INSTR_MEM13 [15:0] write-only INSTR_MEM14 0x00000080 Write-only access to instruction memory location 14 0x00000000 INSTR_MEM14 [15:0] write-only INSTR_MEM15 0x00000084 Write-only access to instruction memory location 15 0x00000000 INSTR_MEM15 [15:0] write-only INSTR_MEM16 0x00000088 Write-only access to instruction memory location 16 0x00000000 INSTR_MEM16 [15:0] write-only INSTR_MEM17 0x0000008c Write-only access to instruction memory location 17 0x00000000 INSTR_MEM17 [15:0] write-only INSTR_MEM18 0x00000090 Write-only access to instruction memory location 18 0x00000000 INSTR_MEM18 [15:0] write-only INSTR_MEM19 0x00000094 Write-only access to instruction memory location 19 0x00000000 INSTR_MEM19 [15:0] write-only INSTR_MEM20 0x00000098 Write-only access to instruction memory location 20 0x00000000 INSTR_MEM20 [15:0] write-only INSTR_MEM21 0x0000009c Write-only access to instruction memory location 21 0x00000000 INSTR_MEM21 [15:0] write-only INSTR_MEM22 0x000000a0 Write-only access to instruction memory location 22 0x00000000 INSTR_MEM22 [15:0] write-only INSTR_MEM23 0x000000a4 Write-only access to instruction memory location 23 0x00000000 INSTR_MEM23 [15:0] write-only INSTR_MEM24 0x000000a8 Write-only access to instruction memory location 24 0x00000000 INSTR_MEM24 [15:0] write-only INSTR_MEM25 0x000000ac Write-only access to instruction memory location 25 0x00000000 INSTR_MEM25 [15:0] write-only INSTR_MEM26 0x000000b0 Write-only access to instruction memory location 26 0x00000000 INSTR_MEM26 [15:0] write-only INSTR_MEM27 0x000000b4 Write-only access to instruction memory location 27 0x00000000 INSTR_MEM27 [15:0] write-only INSTR_MEM28 0x000000b8 Write-only access to instruction memory location 28 0x00000000 INSTR_MEM28 [15:0] write-only INSTR_MEM29 0x000000bc Write-only access to instruction memory location 29 0x00000000 INSTR_MEM29 [15:0] write-only INSTR_MEM30 0x000000c0 Write-only access to instruction memory location 30 0x00000000 INSTR_MEM30 [15:0] write-only INSTR_MEM31 0x000000c4 Write-only access to instruction memory location 31 0x00000000 INSTR_MEM31 [15:0] write-only SM0_CLKDIV 0x000000c8 Clock divisor register for state machine 0 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 0x00010000 INT Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. [31:16] read-write FRAC Fractional part of clock divisor [15:8] read-write SM0_EXECCTRL 0x000000cc Execution/behavioural settings for state machine 0 0x0001f000 EXEC_STALLED If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. [31:31] read-only SIDE_EN If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. [30:30] read-write SIDE_PINDIR If 1, side-set data is asserted to pin directions, instead of pin values [29:29] read-write JMP_PIN The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. [28:24] read-write OUT_EN_SEL Which data bit to use for inline OUT enable [23:19] read-write INLINE_OUT_EN If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) [18:18] read-write OUT_STICKY Continuously assert the most recent OUT/SET to the pins [17:17] read-write WRAP_TOP After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority. [16:12] read-write WRAP_BOTTOM After reaching wrap_top, execution is wrapped to this address. [11:7] read-write STATUS_SEL Comparison used for the MOV x, STATUS instruction. [4:4] read-write TXLEVEL 0 All-ones if TX FIFO level < N, otherwise all-zeroes RXLEVEL 1 All-ones if RX FIFO level < N, otherwise all-zeroes STATUS_N Comparison level for the MOV x, STATUS instruction [3:0] read-write SM0_SHIFTCTRL 0x000000d0 Control behaviour of the input/output shift registers for state machine 0 0x000c0000 FJOIN_RX When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [31:31] read-write FJOIN_TX When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [30:30] read-write PULL_THRESH Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. [29:25] read-write PUSH_THRESH Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. [24:20] read-write OUT_SHIFTDIR 1 = shift out of output shift register to right. 0 = to left. [19:19] read-write IN_SHIFTDIR 1 = shift input shift register to right (data enters from left). 0 = to left. [18:18] read-write AUTOPULL Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. [17:17] read-write AUTOPUSH Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. [16:16] read-write SM0_ADDR 0x000000d4 Current instruction address of state machine 0 0x00000000 SM0_ADDR [4:0] read-only SM0_INSTR 0x000000d8 Read to see the instruction currently addressed by state machine 0's program counter Write to execute an instruction immediately (including jumps) and then resume execution. 0x00000000 SM0_INSTR [15:0] read-write SM0_PINCTRL 0x000000dc State machine pin control 0x14000000 SIDESET_COUNT The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). [31:29] read-write SET_COUNT The number of pins asserted by a SET. In the range 0 to 5 inclusive. [28:26] read-write OUT_COUNT The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. [25:20] read-write IN_BASE The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. [19:15] read-write SIDESET_BASE The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. [14:10] read-write SET_BASE The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. [9:5] read-write OUT_BASE The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. [4:0] read-write SM1_CLKDIV 0x000000e0 Clock divisor register for state machine 1 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 0x00010000 INT Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. [31:16] read-write FRAC Fractional part of clock divisor [15:8] read-write SM1_EXECCTRL 0x000000e4 Execution/behavioural settings for state machine 1 0x0001f000 EXEC_STALLED If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. [31:31] read-only SIDE_EN If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. [30:30] read-write SIDE_PINDIR If 1, side-set data is asserted to pin directions, instead of pin values [29:29] read-write JMP_PIN The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. [28:24] read-write OUT_EN_SEL Which data bit to use for inline OUT enable [23:19] read-write INLINE_OUT_EN If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) [18:18] read-write OUT_STICKY Continuously assert the most recent OUT/SET to the pins [17:17] read-write WRAP_TOP After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority. [16:12] read-write WRAP_BOTTOM After reaching wrap_top, execution is wrapped to this address. [11:7] read-write STATUS_SEL Comparison used for the MOV x, STATUS instruction. [4:4] read-write TXLEVEL 0 All-ones if TX FIFO level < N, otherwise all-zeroes RXLEVEL 1 All-ones if RX FIFO level < N, otherwise all-zeroes STATUS_N Comparison level for the MOV x, STATUS instruction [3:0] read-write SM1_SHIFTCTRL 0x000000e8 Control behaviour of the input/output shift registers for state machine 1 0x000c0000 FJOIN_RX When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [31:31] read-write FJOIN_TX When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [30:30] read-write PULL_THRESH Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. [29:25] read-write PUSH_THRESH Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. [24:20] read-write OUT_SHIFTDIR 1 = shift out of output shift register to right. 0 = to left. [19:19] read-write IN_SHIFTDIR 1 = shift input shift register to right (data enters from left). 0 = to left. [18:18] read-write AUTOPULL Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. [17:17] read-write AUTOPUSH Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. [16:16] read-write SM1_ADDR 0x000000ec Current instruction address of state machine 1 0x00000000 SM1_ADDR [4:0] read-only SM1_INSTR 0x000000f0 Read to see the instruction currently addressed by state machine 1's program counter Write to execute an instruction immediately (including jumps) and then resume execution. 0x00000000 SM1_INSTR [15:0] read-write SM1_PINCTRL 0x000000f4 State machine pin control 0x14000000 SIDESET_COUNT The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). [31:29] read-write SET_COUNT The number of pins asserted by a SET. In the range 0 to 5 inclusive. [28:26] read-write OUT_COUNT The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. [25:20] read-write IN_BASE The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. [19:15] read-write SIDESET_BASE The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. [14:10] read-write SET_BASE The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. [9:5] read-write OUT_BASE The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. [4:0] read-write SM2_CLKDIV 0x000000f8 Clock divisor register for state machine 2 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 0x00010000 INT Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. [31:16] read-write FRAC Fractional part of clock divisor [15:8] read-write SM2_EXECCTRL 0x000000fc Execution/behavioural settings for state machine 2 0x0001f000 EXEC_STALLED If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. [31:31] read-only SIDE_EN If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. [30:30] read-write SIDE_PINDIR If 1, side-set data is asserted to pin directions, instead of pin values [29:29] read-write JMP_PIN The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. [28:24] read-write OUT_EN_SEL Which data bit to use for inline OUT enable [23:19] read-write INLINE_OUT_EN If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) [18:18] read-write OUT_STICKY Continuously assert the most recent OUT/SET to the pins [17:17] read-write WRAP_TOP After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority. [16:12] read-write WRAP_BOTTOM After reaching wrap_top, execution is wrapped to this address. [11:7] read-write STATUS_SEL Comparison used for the MOV x, STATUS instruction. [4:4] read-write TXLEVEL 0 All-ones if TX FIFO level < N, otherwise all-zeroes RXLEVEL 1 All-ones if RX FIFO level < N, otherwise all-zeroes STATUS_N Comparison level for the MOV x, STATUS instruction [3:0] read-write SM2_SHIFTCTRL 0x00000100 Control behaviour of the input/output shift registers for state machine 2 0x000c0000 FJOIN_RX When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [31:31] read-write FJOIN_TX When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [30:30] read-write PULL_THRESH Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. [29:25] read-write PUSH_THRESH Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. [24:20] read-write OUT_SHIFTDIR 1 = shift out of output shift register to right. 0 = to left. [19:19] read-write IN_SHIFTDIR 1 = shift input shift register to right (data enters from left). 0 = to left. [18:18] read-write AUTOPULL Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. [17:17] read-write AUTOPUSH Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. [16:16] read-write SM2_ADDR 0x00000104 Current instruction address of state machine 2 0x00000000 SM2_ADDR [4:0] read-only SM2_INSTR 0x00000108 Read to see the instruction currently addressed by state machine 2's program counter Write to execute an instruction immediately (including jumps) and then resume execution. 0x00000000 SM2_INSTR [15:0] read-write SM2_PINCTRL 0x0000010c State machine pin control 0x14000000 SIDESET_COUNT The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). [31:29] read-write SET_COUNT The number of pins asserted by a SET. In the range 0 to 5 inclusive. [28:26] read-write OUT_COUNT The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. [25:20] read-write IN_BASE The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. [19:15] read-write SIDESET_BASE The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. [14:10] read-write SET_BASE The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. [9:5] read-write OUT_BASE The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. [4:0] read-write SM3_CLKDIV 0x00000110 Clock divisor register for state machine 3 Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) 0x00010000 INT Effective frequency is sysclk/(int + frac/256). Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. [31:16] read-write FRAC Fractional part of clock divisor [15:8] read-write SM3_EXECCTRL 0x00000114 Execution/behavioural settings for state machine 3 0x0001f000 EXEC_STALLED If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes. [31:31] read-only SIDE_EN If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit. [30:30] read-write SIDE_PINDIR If 1, side-set data is asserted to pin directions, instead of pin values [29:29] read-write JMP_PIN The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. [28:24] read-write OUT_EN_SEL Which data bit to use for inline OUT enable [23:19] read-write INLINE_OUT_EN If 1, use a bit of OUT data as an auxiliary write enable When used in conjunction with OUT_STICKY, writes with an enable of 0 will deassert the latest pin write. This can create useful masking/override behaviour due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) [18:18] read-write OUT_STICKY Continuously assert the most recent OUT/SET to the pins [17:17] read-write WRAP_TOP After reaching this address, execution is wrapped to wrap_bottom. If the instruction is a jump, and the jump condition is true, the jump takes priority. [16:12] read-write WRAP_BOTTOM After reaching wrap_top, execution is wrapped to this address. [11:7] read-write STATUS_SEL Comparison used for the MOV x, STATUS instruction. [4:4] read-write TXLEVEL 0 All-ones if TX FIFO level < N, otherwise all-zeroes RXLEVEL 1 All-ones if RX FIFO level < N, otherwise all-zeroes STATUS_N Comparison level for the MOV x, STATUS instruction [3:0] read-write SM3_SHIFTCTRL 0x00000118 Control behaviour of the input/output shift registers for state machine 3 0x000c0000 FJOIN_RX When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [31:31] read-write FJOIN_TX When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. [30:30] read-write PULL_THRESH Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. [29:25] read-write PUSH_THRESH Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. [24:20] read-write OUT_SHIFTDIR 1 = shift out of output shift register to right. 0 = to left. [19:19] read-write IN_SHIFTDIR 1 = shift input shift register to right (data enters from left). 0 = to left. [18:18] read-write AUTOPULL Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. [17:17] read-write AUTOPUSH Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. [16:16] read-write SM3_ADDR 0x0000011c Current instruction address of state machine 3 0x00000000 SM3_ADDR [4:0] read-only SM3_INSTR 0x00000120 Read to see the instruction currently addressed by state machine 3's program counter Write to execute an instruction immediately (including jumps) and then resume execution. 0x00000000 SM3_INSTR [15:0] read-write SM3_PINCTRL 0x00000124 State machine pin control 0x14000000 SIDESET_COUNT The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay). [31:29] read-write SET_COUNT The number of pins asserted by a SET. In the range 0 to 5 inclusive. [28:26] read-write OUT_COUNT The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive. [25:20] read-write IN_BASE The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number. [19:15] read-write SIDESET_BASE The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins. [14:10] read-write SET_BASE The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data. [9:5] read-write OUT_BASE The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data. [4:0] read-write INTR 0x00000128 Raw Interrupts 0x00000000 SM3 [11:11] read-only SM2 [10:10] read-only SM1 [9:9] read-only SM0 [8:8] read-only SM3_TXNFULL [7:7] read-only SM2_TXNFULL [6:6] read-only SM1_TXNFULL [5:5] read-only SM0_TXNFULL [4:4] read-only SM3_RXNEMPTY [3:3] read-only SM2_RXNEMPTY [2:2] read-only SM1_RXNEMPTY [1:1] read-only SM0_RXNEMPTY [0:0] read-only IRQ0_INTE 0x0000012c Interrupt Enable for irq0 0x00000000 SM3 [11:11] read-write SM2 [10:10] read-write SM1 [9:9] read-write SM0 [8:8] read-write SM3_TXNFULL [7:7] read-write SM2_TXNFULL [6:6] read-write SM1_TXNFULL [5:5] read-write SM0_TXNFULL [4:4] read-write SM3_RXNEMPTY [3:3] read-write SM2_RXNEMPTY [2:2] read-write SM1_RXNEMPTY [1:1] read-write SM0_RXNEMPTY [0:0] read-write IRQ0_INTF 0x00000130 Interrupt Force for irq0 0x00000000 SM3 [11:11] read-write SM2 [10:10] read-write SM1 [9:9] read-write SM0 [8:8] read-write SM3_TXNFULL [7:7] read-write SM2_TXNFULL [6:6] read-write SM1_TXNFULL [5:5] read-write SM0_TXNFULL [4:4] read-write SM3_RXNEMPTY [3:3] read-write SM2_RXNEMPTY [2:2] read-write SM1_RXNEMPTY [1:1] read-write SM0_RXNEMPTY [0:0] read-write IRQ0_INTS 0x00000134 Interrupt status after masking & forcing for irq0 0x00000000 SM3 [11:11] read-only SM2 [10:10] read-only SM1 [9:9] read-only SM0 [8:8] read-only SM3_TXNFULL [7:7] read-only SM2_TXNFULL [6:6] read-only SM1_TXNFULL [5:5] read-only SM0_TXNFULL [4:4] read-only SM3_RXNEMPTY [3:3] read-only SM2_RXNEMPTY [2:2] read-only SM1_RXNEMPTY [1:1] read-only SM0_RXNEMPTY [0:0] read-only IRQ1_INTE 0x00000138 Interrupt Enable for irq1 0x00000000 SM3 [11:11] read-write SM2 [10:10] read-write SM1 [9:9] read-write SM0 [8:8] read-write SM3_TXNFULL [7:7] read-write SM2_TXNFULL [6:6] read-write SM1_TXNFULL [5:5] read-write SM0_TXNFULL [4:4] read-write SM3_RXNEMPTY [3:3] read-write SM2_RXNEMPTY [2:2] read-write SM1_RXNEMPTY [1:1] read-write SM0_RXNEMPTY [0:0] read-write IRQ1_INTF 0x0000013c Interrupt Force for irq1 0x00000000 SM3 [11:11] read-write SM2 [10:10] read-write SM1 [9:9] read-write SM0 [8:8] read-write SM3_TXNFULL [7:7] read-write SM2_TXNFULL [6:6] read-write SM1_TXNFULL [5:5] read-write SM0_TXNFULL [4:4] read-write SM3_RXNEMPTY [3:3] read-write SM2_RXNEMPTY [2:2] read-write SM1_RXNEMPTY [1:1] read-write SM0_RXNEMPTY [0:0] read-write IRQ1_INTS 0x00000140 Interrupt status after masking & forcing for irq1 0x00000000 SM3 [11:11] read-only SM2 [10:10] read-only SM1 [9:9] read-only SM0 [8:8] read-only SM3_TXNFULL [7:7] read-only SM2_TXNFULL [6:6] read-only SM1_TXNFULL [5:5] read-only SM0_TXNFULL [4:4] read-only SM3_RXNEMPTY [3:3] read-only SM2_RXNEMPTY [2:2] read-only SM1_RXNEMPTY [1:1] read-only SM0_RXNEMPTY [0:0] read-only PIO1 0x50300000 PIO1_IRQ_0 9 PIO1_IRQ_1 10 BUSCTRL Register block for busfabric control signals and performance counters 0x40030000 0 40 registers BUS_PRIORITY 0x00000000 Set the priority of each master for bus arbitration. 0x00000000 DMA_W 0 - low priority, 1 - high priority [12:12] read-write DMA_R 0 - low priority, 1 - high priority [8:8] read-write PROC1 0 - low priority, 1 - high priority [4:4] read-write PROC0 0 - low priority, 1 - high priority [0:0] read-write BUS_PRIORITY_ACK 0x00000004 Bus priority acknowledge 0x00000000 BUS_PRIORITY_ACK Goes to 1 once all arbiters have registered the new global priority levels. Arbiters update their local priority when servicing a new nonsequential access. In normal circumstances this will happen almost immediately. [0:0] read-only PERFCTR0 0x00000008 Bus fabric performance counter 0 0x00000000 PERFCTR0 Busfabric saturating performance counter 0 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL0 [23:0] read-write oneToClear PERFSEL0 0x0000000c Bus fabric performance event select for PERFCTR0 0x0000001f PERFSEL0 Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. [4:0] read-write apb_contested 0 apb 1 fastperi_contested 2 fastperi 3 sram5_contested 4 sram5 5 sram4_contested 6 sram4 7 sram3_contested 8 sram3 9 sram2_contested 10 sram2 11 sram1_contested 12 sram1 13 sram0_contested 14 sram0 15 xip_main_contested 16 xip_main 17 rom_contested 18 rom 19 PERFCTR1 0x00000010 Bus fabric performance counter 1 0x00000000 PERFCTR1 Busfabric saturating performance counter 1 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL1 [23:0] read-write oneToClear PERFSEL1 0x00000014 Bus fabric performance event select for PERFCTR1 0x0000001f PERFSEL1 Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. [4:0] read-write apb_contested 0 apb 1 fastperi_contested 2 fastperi 3 sram5_contested 4 sram5 5 sram4_contested 6 sram4 7 sram3_contested 8 sram3 9 sram2_contested 10 sram2 11 sram1_contested 12 sram1 13 sram0_contested 14 sram0 15 xip_main_contested 16 xip_main 17 rom_contested 18 rom 19 PERFCTR2 0x00000018 Bus fabric performance counter 2 0x00000000 PERFCTR2 Busfabric saturating performance counter 2 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL2 [23:0] read-write oneToClear PERFSEL2 0x0000001c Bus fabric performance event select for PERFCTR2 0x0000001f PERFSEL2 Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. [4:0] read-write apb_contested 0 apb 1 fastperi_contested 2 fastperi 3 sram5_contested 4 sram5 5 sram4_contested 6 sram4 7 sram3_contested 8 sram3 9 sram2_contested 10 sram2 11 sram1_contested 12 sram1 13 sram0_contested 14 sram0 15 xip_main_contested 16 xip_main 17 rom_contested 18 rom 19 PERFCTR3 0x00000020 Bus fabric performance counter 3 0x00000000 PERFCTR3 Busfabric saturating performance counter 3 Count some event signal from the busfabric arbiters. Write any value to clear. Select an event to count using PERFSEL3 [23:0] read-write oneToClear PERFSEL3 0x00000024 Bus fabric performance event select for PERFCTR3 0x0000001f PERFSEL3 Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar. [4:0] read-write apb_contested 0 apb 1 fastperi_contested 2 fastperi 3 sram5_contested 4 sram5 5 sram4_contested 6 sram4 7 sram3_contested 8 sram3 9 sram2_contested 10 sram2 11 sram1_contested 12 sram1 13 sram0_contested 14 sram0 15 xip_main_contested 16 xip_main 17 rom_contested 18 rom 19 SIO Single-cycle IO block Provides core-local and inter-core hardware for the two processors, with single-cycle access. 0xd0000000 0 384 registers SIO_IRQ_PROC0 15 SIO_IRQ_PROC1 16 CPUID 0x00000000 Processor core identifier 0x00000000 CPUID Value is 0 when read from processor core 0, and 1 when read from processor core 1. [31:0] read-only GPIO_IN 0x00000004 Input value for GPIO pins 0x00000000 GPIO_IN Input value for GPIO0...29 [29:0] read-only GPIO_HI_IN 0x00000008 Input value for QSPI pins 0x00000000 GPIO_HI_IN Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 [5:0] read-only GPIO_OUT 0x00000010 GPIO output value 0x00000000 GPIO_OUT Set output level (1/0 -> high/low) for GPIO0...29. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. [29:0] read-write GPIO_OUT_SET 0x00000014 GPIO output value set 0x00000000 GPIO_OUT_SET Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata` [29:0] write-only GPIO_OUT_CLR 0x00000018 GPIO output value clear 0x00000000 GPIO_OUT_CLR Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata` [29:0] write-only GPIO_OUT_XOR 0x0000001c GPIO output value XOR 0x00000000 GPIO_OUT_XOR Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata` [29:0] write-only GPIO_OE 0x00000020 GPIO output enable 0x00000000 GPIO_OE Set output enable (1/0 -> output/input) for GPIO0...29. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. [29:0] read-write GPIO_OE_SET 0x00000024 GPIO output enable set 0x00000000 GPIO_OE_SET Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata` [29:0] write-only GPIO_OE_CLR 0x00000028 GPIO output enable clear 0x00000000 GPIO_OE_CLR Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata` [29:0] write-only GPIO_OE_XOR 0x0000002c GPIO output enable XOR 0x00000000 GPIO_OE_XOR Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata` [29:0] write-only GPIO_HI_OUT 0x00000030 QSPI output value 0x00000000 GPIO_HI_OUT Set output level (1/0 -> high/low) for QSPI IO0...5. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. [5:0] read-write GPIO_HI_OUT_SET 0x00000034 QSPI output value set 0x00000000 GPIO_HI_OUT_SET Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata` [5:0] write-only GPIO_HI_OUT_CLR 0x00000038 QSPI output value clear 0x00000000 GPIO_HI_OUT_CLR Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata` [5:0] write-only GPIO_HI_OUT_XOR 0x0000003c QSPI output value XOR 0x00000000 GPIO_HI_OUT_XOR Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata` [5:0] write-only GPIO_HI_OE 0x00000040 QSPI output enable 0x00000000 GPIO_HI_OE Set output enable (1/0 -> output/input) for QSPI IO0...5. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. [5:0] read-write GPIO_HI_OE_SET 0x00000044 QSPI output enable set 0x00000000 GPIO_HI_OE_SET Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata` [5:0] write-only GPIO_HI_OE_CLR 0x00000048 QSPI output enable clear 0x00000000 GPIO_HI_OE_CLR Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata` [5:0] write-only GPIO_HI_OE_XOR 0x0000004c QSPI output enable XOR 0x00000000 GPIO_HI_OE_XOR Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata` [5:0] write-only FIFO_ST 0x00000050 Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register. 0x00000002 ROE Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO. [3:3] read-write oneToClear WOF Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO. [2:2] read-write oneToClear RDY Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data) [1:1] read-only VLD Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) [0:0] read-only FIFO_WR 0x00000054 Write access to this core's TX FIFO 0x00000000 FIFO_WR [31:0] write-only FIFO_RD 0x00000058 Read access to this core's RX FIFO 0x00000000 FIFO_RD [31:0] read-only modify SPINLOCK_ST 0x0000005c Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging. 0x00000000 SPINLOCK_ST [31:0] read-only DIV_UDIVIDEND 0x00000060 Divider unsigned dividend Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. 0x00000000 DIV_UDIVIDEND [31:0] read-write DIV_UDIVISOR 0x00000064 Divider unsigned divisor Write to the DIVISOR operand of the divider, i.e. the q in `p / q`. Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER. UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an unsigned calculation, and the S alias starts a signed calculation. 0x00000000 DIV_UDIVISOR [31:0] read-write DIV_SDIVIDEND 0x00000068 Divider signed dividend The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. 0x00000000 DIV_SDIVIDEND [31:0] read-write DIV_SDIVISOR 0x0000006c Divider signed divisor The same as UDIVISOR, but starts a signed calculation, rather than unsigned. 0x00000000 DIV_SDIVISOR [31:0] read-write DIV_QUOTIENT 0x00000070 Divider result quotient The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low. For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order REMAINDER, QUOTIENT if CSR_DIRTY is used. 0x00000000 DIV_QUOTIENT [31:0] read-write DIV_REMAINDER 0x00000074 Divider result remainder The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low. For signed calculations, REMAINDER is negative only when DIVIDEND is negative. This register can be written to directly, for context save/restore purposes. This halts any in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. 0x00000000 DIV_REMAINDER [31:0] read-write DIV_CSR 0x00000078 Control and status register for divider. 0x00000001 DIRTY Changes to 1 when any register is written, and back to 0 when QUOTIENT is read. Software can use this flag to make save/restore more efficient (skip if not DIRTY). If the flag is used in this way, it's recommended to either read QUOTIENT only, or REMAINDER and then QUOTIENT, to prevent data loss on context switch. [1:1] read-only READY Reads as 0 when a calculation is in progress, 1 otherwise. Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no matter if one is already in progress. Writing to a result register will immediately terminate any in-progress calculation and set the READY and DIRTY flags. [0:0] read-only INTERP0_ACCUM0 0x00000080 Read/write access to accumulator 0 0x00000000 INTERP0_ACCUM0 [31:0] read-write INTERP0_ACCUM1 0x00000084 Read/write access to accumulator 1 0x00000000 INTERP0_ACCUM1 [31:0] read-write INTERP0_BASE0 0x00000088 Read/write access to BASE0 register. 0x00000000 INTERP0_BASE0 [31:0] read-write INTERP0_BASE1 0x0000008c Read/write access to BASE1 register. 0x00000000 INTERP0_BASE1 [31:0] read-write INTERP0_BASE2 0x00000090 Read/write access to BASE2 register. 0x00000000 INTERP0_BASE2 [31:0] read-write INTERP0_POP_LANE0 0x00000094 Read LANE0 result, and simultaneously write lane results to both accumulators (POP). 0x00000000 INTERP0_POP_LANE0 [31:0] read-only INTERP0_POP_LANE1 0x00000098 Read LANE1 result, and simultaneously write lane results to both accumulators (POP). 0x00000000 INTERP0_POP_LANE1 [31:0] read-only INTERP0_POP_FULL 0x0000009c Read FULL result, and simultaneously write lane results to both accumulators (POP). 0x00000000 INTERP0_POP_FULL [31:0] read-only INTERP0_PEEK_LANE0 0x000000a0 Read LANE0 result, without altering any internal state (PEEK). 0x00000000 INTERP0_PEEK_LANE0 [31:0] read-only INTERP0_PEEK_LANE1 0x000000a4 Read LANE1 result, without altering any internal state (PEEK). 0x00000000 INTERP0_PEEK_LANE1 [31:0] read-only INTERP0_PEEK_FULL 0x000000a8 Read FULL result, without altering any internal state (PEEK). 0x00000000 INTERP0_PEEK_FULL [31:0] read-only INTERP0_CTRL_LANE0 0x000000ac Control register for lane 0 0x00000000 OVERF Set if either OVERF0 or OVERF1 is set. [25:25] read-only OVERF1 Indicates if any masked-off MSBs in ACCUM1 are set. [24:24] read-only OVERF0 Indicates if any masked-off MSBs in ACCUM0 are set. [23:23] read-only BLEND Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. [21:21] read-write FORCE_MSB ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. [20:19] read-write ADD_RAW If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. [18:18] read-write CROSS_RESULT If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write CROSS_INPUT If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write SIGNED If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write MASK_MSB The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out [14:10] read-write MASK_LSB The least-significant bit allowed to pass by the mask (inclusive) [9:5] read-write SHIFT Logical right-shift applied to accumulator before masking [4:0] read-write INTERP0_CTRL_LANE1 0x000000b0 Control register for lane 1 0x00000000 FORCE_MSB ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. [20:19] read-write ADD_RAW If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. [18:18] read-write CROSS_RESULT If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write CROSS_INPUT If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write SIGNED If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write MASK_MSB The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out [14:10] read-write MASK_LSB The least-significant bit allowed to pass by the mask (inclusive) [9:5] read-write SHIFT Logical right-shift applied to accumulator before masking [4:0] read-write INTERP0_ACCUM0_ADD 0x000000b4 Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). 0x00000000 INTERP0_ACCUM0_ADD [23:0] read-write INTERP0_ACCUM1_ADD 0x000000b8 Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). 0x00000000 INTERP0_ACCUM1_ADD [23:0] read-write INTERP0_BASE_1AND0 0x000000bc On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. 0x00000000 INTERP0_BASE_1AND0 [31:0] write-only INTERP1_ACCUM0 0x000000c0 Read/write access to accumulator 0 0x00000000 INTERP1_ACCUM0 [31:0] read-write INTERP1_ACCUM1 0x000000c4 Read/write access to accumulator 1 0x00000000 INTERP1_ACCUM1 [31:0] read-write INTERP1_BASE0 0x000000c8 Read/write access to BASE0 register. 0x00000000 INTERP1_BASE0 [31:0] read-write INTERP1_BASE1 0x000000cc Read/write access to BASE1 register. 0x00000000 INTERP1_BASE1 [31:0] read-write INTERP1_BASE2 0x000000d0 Read/write access to BASE2 register. 0x00000000 INTERP1_BASE2 [31:0] read-write INTERP1_POP_LANE0 0x000000d4 Read LANE0 result, and simultaneously write lane results to both accumulators (POP). 0x00000000 INTERP1_POP_LANE0 [31:0] read-only INTERP1_POP_LANE1 0x000000d8 Read LANE1 result, and simultaneously write lane results to both accumulators (POP). 0x00000000 INTERP1_POP_LANE1 [31:0] read-only INTERP1_POP_FULL 0x000000dc Read FULL result, and simultaneously write lane results to both accumulators (POP). 0x00000000 INTERP1_POP_FULL [31:0] read-only INTERP1_PEEK_LANE0 0x000000e0 Read LANE0 result, without altering any internal state (PEEK). 0x00000000 INTERP1_PEEK_LANE0 [31:0] read-only INTERP1_PEEK_LANE1 0x000000e4 Read LANE1 result, without altering any internal state (PEEK). 0x00000000 INTERP1_PEEK_LANE1 [31:0] read-only INTERP1_PEEK_FULL 0x000000e8 Read FULL result, without altering any internal state (PEEK). 0x00000000 INTERP1_PEEK_FULL [31:0] read-only INTERP1_CTRL_LANE0 0x000000ec Control register for lane 0 0x00000000 OVERF Set if either OVERF0 or OVERF1 is set. [25:25] read-only OVERF1 Indicates if any masked-off MSBs in ACCUM1 are set. [24:24] read-only OVERF0 Indicates if any masked-off MSBs in ACCUM0 are set. [23:23] read-only CLAMP Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED [22:22] read-write FORCE_MSB ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. [20:19] read-write ADD_RAW If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result. [18:18] read-write CROSS_RESULT If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write CROSS_INPUT If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write SIGNED If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write MASK_MSB The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out [14:10] read-write MASK_LSB The least-significant bit allowed to pass by the mask (inclusive) [9:5] read-write SHIFT Logical right-shift applied to accumulator before masking [4:0] read-write INTERP1_CTRL_LANE1 0x000000f0 Control register for lane 1 0x00000000 FORCE_MSB ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM. [20:19] read-write ADD_RAW If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result. [18:18] read-write CROSS_RESULT If 1, feed the opposite lane's result into this lane's accumulator on POP. [17:17] read-write CROSS_INPUT If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass) [16:16] read-write SIGNED If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor. [15:15] read-write MASK_MSB The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out [14:10] read-write MASK_LSB The least-significant bit allowed to pass by the mask (inclusive) [9:5] read-write SHIFT Logical right-shift applied to accumulator before masking [4:0] read-write INTERP1_ACCUM0_ADD 0x000000f4 Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added). 0x00000000 INTERP1_ACCUM0_ADD [23:0] read-write INTERP1_ACCUM1_ADD 0x000000f8 Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added). 0x00000000 INTERP1_ACCUM1_ADD [23:0] read-write INTERP1_BASE_1AND0 0x000000fc On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. 0x00000000 INTERP1_BASE_1AND0 [31:0] write-only SPINLOCK0 0x00000100 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK0 [31:0] read-write modify SPINLOCK1 0x00000104 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK1 [31:0] read-write modify SPINLOCK2 0x00000108 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK2 [31:0] read-write modify SPINLOCK3 0x0000010c Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK3 [31:0] read-write modify SPINLOCK4 0x00000110 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK4 [31:0] read-write modify SPINLOCK5 0x00000114 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK5 [31:0] read-write modify SPINLOCK6 0x00000118 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK6 [31:0] read-write modify SPINLOCK7 0x0000011c Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK7 [31:0] read-write modify SPINLOCK8 0x00000120 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK8 [31:0] read-write modify SPINLOCK9 0x00000124 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK9 [31:0] read-write modify SPINLOCK10 0x00000128 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK10 [31:0] read-write modify SPINLOCK11 0x0000012c Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK11 [31:0] read-write modify SPINLOCK12 0x00000130 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK12 [31:0] read-write modify SPINLOCK13 0x00000134 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK13 [31:0] read-write modify SPINLOCK14 0x00000138 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK14 [31:0] read-write modify SPINLOCK15 0x0000013c Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK15 [31:0] read-write modify SPINLOCK16 0x00000140 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK16 [31:0] read-write modify SPINLOCK17 0x00000144 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK17 [31:0] read-write modify SPINLOCK18 0x00000148 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK18 [31:0] read-write modify SPINLOCK19 0x0000014c Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK19 [31:0] read-write modify SPINLOCK20 0x00000150 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK20 [31:0] read-write modify SPINLOCK21 0x00000154 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK21 [31:0] read-write modify SPINLOCK22 0x00000158 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK22 [31:0] read-write modify SPINLOCK23 0x0000015c Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK23 [31:0] read-write modify SPINLOCK24 0x00000160 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK24 [31:0] read-write modify SPINLOCK25 0x00000164 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK25 [31:0] read-write modify SPINLOCK26 0x00000168 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK26 [31:0] read-write modify SPINLOCK27 0x0000016c Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK27 [31:0] read-write modify SPINLOCK28 0x00000170 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK28 [31:0] read-write modify SPINLOCK29 0x00000174 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK29 [31:0] read-write modify SPINLOCK30 0x00000178 Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK30 [31:0] read-write modify SPINLOCK31 0x0000017c Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number. 0x00000000 SPINLOCK31 [31:0] read-write modify USB USB FS/LS controller device registers 0x50110000 0 156 registers USBCTRL_IRQ 5 ADDR_ENDP 0x00000000 Device address and endpoint control 0x00000000 ENDPOINT Device endpoint to send data to. Only valid for HOST mode. [19:16] read-write ADDRESS In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with. [6:0] read-write ADDR_ENDP1 0x00000004 Interrupt endpoint 1. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP2 0x00000008 Interrupt endpoint 2. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP3 0x0000000c Interrupt endpoint 3. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP4 0x00000010 Interrupt endpoint 4. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP5 0x00000014 Interrupt endpoint 5. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP6 0x00000018 Interrupt endpoint 6. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP7 0x0000001c Interrupt endpoint 7. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP8 0x00000020 Interrupt endpoint 8. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP9 0x00000024 Interrupt endpoint 9. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP10 0x00000028 Interrupt endpoint 10. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP11 0x0000002c Interrupt endpoint 11. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP12 0x00000030 Interrupt endpoint 12. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP13 0x00000034 Interrupt endpoint 13. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP14 0x00000038 Interrupt endpoint 14. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write ADDR_ENDP15 0x0000003c Interrupt endpoint 15. Only valid for HOST mode. 0x00000000 INTEP_PREAMBLE Interrupt EP requires preamble (is a low speed device on a full speed hub) [26:26] read-write INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 [25:25] read-write ENDPOINT Endpoint number of the interrupt endpoint [19:16] read-write ADDRESS Device address [6:0] read-write MAIN_CTRL 0x00000040 Main control register 0x00000000 SIM_TIMING Reduced timings for simulation [31:31] read-write HOST_NDEVICE Device mode = 0, Host mode = 1 [1:1] read-write CONTROLLER_EN Enable controller [0:0] read-write SOF_WR 0x00000044 Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time. 0x00000000 COUNT [10:0] write-only SOF_RD 0x00000048 Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host. 0x00000000 COUNT [10:0] read-only SIE_CTRL 0x0000004c SIE control register 0x00000000 EP0_INT_STALL Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL [31:31] read-write EP0_DOUBLE_BUF Device: EP0 single buffered = 0, double buffered = 1 [30:30] read-write EP0_INT_1BUF Device: Set bit in BUFF_STATUS for every buffer completed on EP0 [29:29] read-write EP0_INT_2BUF Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 [28:28] read-write EP0_INT_NAK Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK [27:27] read-write DIRECT_EN Direct bus drive enable [26:26] read-write DIRECT_DP Direct control of DP [25:25] read-write DIRECT_DM Direct control of DM [24:24] read-write TRANSCEIVER_PD Power down bus transceiver [18:18] read-write RPU_OPT Device: Pull-up strength (0=1K2, 1=2k3) [17:17] read-write PULLUP_EN Device: Enable pull up resistor [16:16] read-write PULLDOWN_EN Host: Enable pull down resistors [15:15] read-write RESET_BUS Host: Reset bus [13:13] write-only RESUME Device: Remote wakeup. Device can initiate its own resume after suspend. [12:12] write-only VBUS_EN Host: Enable VBUS [11:11] read-write KEEP_ALIVE_EN Host: Enable keep alive packet (for low speed bus) [10:10] read-write SOF_EN Host: Enable SOF generation (for full speed bus) [9:9] read-write SOF_SYNC Host: Delay packet(s) until after SOF [8:8] read-write PREAMBLE_EN Host: Preable enable for LS device on FS hub [6:6] read-write STOP_TRANS Host: Stop transaction [4:4] write-only RECEIVE_DATA Host: Receive transaction (IN to host) [3:3] read-write SEND_DATA Host: Send transaction (OUT from host) [2:2] read-write SEND_SETUP Host: Send Setup packet [1:1] read-write START_TRANS Host: Start transaction [0:0] write-only SIE_STATUS 0x00000050 SIE status register 0x00000000 DATA_SEQ_ERROR Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID [31:31] read-write oneToClear ACK_REC ACK received. Raised by both host and device. [30:30] read-write oneToClear STALL_REC Host: STALL received [29:29] read-write oneToClear NAK_REC Host: NAK received [28:28] read-write oneToClear RX_TIMEOUT RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec. [27:27] read-write oneToClear RX_OVERFLOW RX overflow is raised by the Serial RX engine if the incoming data is too fast. [26:26] read-write oneToClear BIT_STUFF_ERROR Bit Stuff Error. Raised by the Serial RX engine. [25:25] read-write oneToClear CRC_ERROR CRC Error. Raised by the Serial RX engine. [24:24] read-write oneToClear BUS_RESET Device: bus reset received [19:19] read-write oneToClear TRANS_COMPLETE Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set [18:18] read-write oneToClear SETUP_REC Device: Setup packet received [17:17] read-write oneToClear CONNECTED Device: connected [16:16] read-only RESUME Host: Device has initiated a remote resume. Device: host has initiated a resume. [11:11] read-write oneToClear VBUS_OVER_CURR VBUS over current detected [10:10] read-only SPEED Host: device speed. Disconnected = 00, LS = 01, FS = 10 [9:8] read-only SUSPENDED Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled. [4:4] read-only LINE_STATE USB bus line state [3:2] read-only VBUS_DETECTED Device: VBUS Detected [0:0] read-only INT_EP_CTRL 0x00000054 interrupt endpoint control register 0x00000000 INT_EP_ACTIVE Host: Enable interrupt endpoint 1 => 15 [15:1] read-write BUFF_STATUS 0x00000058 Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle. 0x00000000 EP15_OUT [31:31] read-write oneToClear EP15_IN [30:30] read-write oneToClear EP14_OUT [29:29] read-write oneToClear EP14_IN [28:28] read-write oneToClear EP13_OUT [27:27] read-write oneToClear EP13_IN [26:26] read-write oneToClear EP12_OUT [25:25] read-write oneToClear EP12_IN [24:24] read-write oneToClear EP11_OUT [23:23] read-write oneToClear EP11_IN [22:22] read-write oneToClear EP10_OUT [21:21] read-write oneToClear EP10_IN [20:20] read-write oneToClear EP9_OUT [19:19] read-write oneToClear EP9_IN [18:18] read-write oneToClear EP8_OUT [17:17] read-write oneToClear EP8_IN [16:16] read-write oneToClear EP7_OUT [15:15] read-write oneToClear EP7_IN [14:14] read-write oneToClear EP6_OUT [13:13] read-write oneToClear EP6_IN [12:12] read-write oneToClear EP5_OUT [11:11] read-write oneToClear EP5_IN [10:10] read-write oneToClear EP4_OUT [9:9] read-write oneToClear EP4_IN [8:8] read-write oneToClear EP3_OUT [7:7] read-write oneToClear EP3_IN [6:6] read-write oneToClear EP2_OUT [5:5] read-write oneToClear EP2_IN [4:4] read-write oneToClear EP1_OUT [3:3] read-write oneToClear EP1_IN [2:2] read-write oneToClear EP0_OUT [1:1] read-write oneToClear EP0_IN [0:0] read-write oneToClear BUFF_CPU_SHOULD_HANDLE 0x0000005c Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered. 0x00000000 EP15_OUT [31:31] read-only EP15_IN [30:30] read-only EP14_OUT [29:29] read-only EP14_IN [28:28] read-only EP13_OUT [27:27] read-only EP13_IN [26:26] read-only EP12_OUT [25:25] read-only EP12_IN [24:24] read-only EP11_OUT [23:23] read-only EP11_IN [22:22] read-only EP10_OUT [21:21] read-only EP10_IN [20:20] read-only EP9_OUT [19:19] read-only EP9_IN [18:18] read-only EP8_OUT [17:17] read-only EP8_IN [16:16] read-only EP7_OUT [15:15] read-only EP7_IN [14:14] read-only EP6_OUT [13:13] read-only EP6_IN [12:12] read-only EP5_OUT [11:11] read-only EP5_IN [10:10] read-only EP4_OUT [9:9] read-only EP4_IN [8:8] read-only EP3_OUT [7:7] read-only EP3_IN [6:6] read-only EP2_OUT [5:5] read-only EP2_IN [4:4] read-only EP1_OUT [3:3] read-only EP1_IN [2:2] read-only EP0_OUT [1:1] read-only EP0_IN [0:0] read-only EP_ABORT 0x00000060 Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. 0x00000000 EP15_OUT [31:31] read-write EP15_IN [30:30] read-write EP14_OUT [29:29] read-write EP14_IN [28:28] read-write EP13_OUT [27:27] read-write EP13_IN [26:26] read-write EP12_OUT [25:25] read-write EP12_IN [24:24] read-write EP11_OUT [23:23] read-write EP11_IN [22:22] read-write EP10_OUT [21:21] read-write EP10_IN [20:20] read-write EP9_OUT [19:19] read-write EP9_IN [18:18] read-write EP8_OUT [17:17] read-write EP8_IN [16:16] read-write EP7_OUT [15:15] read-write EP7_IN [14:14] read-write EP6_OUT [13:13] read-write EP6_IN [12:12] read-write EP5_OUT [11:11] read-write EP5_IN [10:10] read-write EP4_OUT [9:9] read-write EP4_IN [8:8] read-write EP3_OUT [7:7] read-write EP3_IN [6:6] read-write EP2_OUT [5:5] read-write EP2_IN [4:4] read-write EP1_OUT [3:3] read-write EP1_IN [2:2] read-write EP0_OUT [1:1] read-write EP0_IN [0:0] read-write EP_ABORT_DONE 0x00000064 Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register. 0x00000000 EP15_OUT [31:31] read-write oneToClear EP15_IN [30:30] read-write oneToClear EP14_OUT [29:29] read-write oneToClear EP14_IN [28:28] read-write oneToClear EP13_OUT [27:27] read-write oneToClear EP13_IN [26:26] read-write oneToClear EP12_OUT [25:25] read-write oneToClear EP12_IN [24:24] read-write oneToClear EP11_OUT [23:23] read-write oneToClear EP11_IN [22:22] read-write oneToClear EP10_OUT [21:21] read-write oneToClear EP10_IN [20:20] read-write oneToClear EP9_OUT [19:19] read-write oneToClear EP9_IN [18:18] read-write oneToClear EP8_OUT [17:17] read-write oneToClear EP8_IN [16:16] read-write oneToClear EP7_OUT [15:15] read-write oneToClear EP7_IN [14:14] read-write oneToClear EP6_OUT [13:13] read-write oneToClear EP6_IN [12:12] read-write oneToClear EP5_OUT [11:11] read-write oneToClear EP5_IN [10:10] read-write oneToClear EP4_OUT [9:9] read-write oneToClear EP4_IN [8:8] read-write oneToClear EP3_OUT [7:7] read-write oneToClear EP3_IN [6:6] read-write oneToClear EP2_OUT [5:5] read-write oneToClear EP2_IN [4:4] read-write oneToClear EP1_OUT [3:3] read-write oneToClear EP1_IN [2:2] read-write oneToClear EP0_OUT [1:1] read-write oneToClear EP0_IN [0:0] read-write oneToClear EP_STALL_ARM 0x00000068 Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received. 0x00000000 EP0_OUT [1:1] read-write EP0_IN [0:0] read-write NAK_POLL 0x0000006c Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK. 0x00100010 DELAY_FS NAK polling interval for a full speed device [25:16] read-write DELAY_LS NAK polling interval for a low speed device [9:0] read-write EP_STATUS_STALL_NAK 0x00000070 Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register. 0x00000000 EP15_OUT [31:31] read-write oneToClear EP15_IN [30:30] read-write oneToClear EP14_OUT [29:29] read-write oneToClear EP14_IN [28:28] read-write oneToClear EP13_OUT [27:27] read-write oneToClear EP13_IN [26:26] read-write oneToClear EP12_OUT [25:25] read-write oneToClear EP12_IN [24:24] read-write oneToClear EP11_OUT [23:23] read-write oneToClear EP11_IN [22:22] read-write oneToClear EP10_OUT [21:21] read-write oneToClear EP10_IN [20:20] read-write oneToClear EP9_OUT [19:19] read-write oneToClear EP9_IN [18:18] read-write oneToClear EP8_OUT [17:17] read-write oneToClear EP8_IN [16:16] read-write oneToClear EP7_OUT [15:15] read-write oneToClear EP7_IN [14:14] read-write oneToClear EP6_OUT [13:13] read-write oneToClear EP6_IN [12:12] read-write oneToClear EP5_OUT [11:11] read-write oneToClear EP5_IN [10:10] read-write oneToClear EP4_OUT [9:9] read-write oneToClear EP4_IN [8:8] read-write oneToClear EP3_OUT [7:7] read-write oneToClear EP3_IN [6:6] read-write oneToClear EP2_OUT [5:5] read-write oneToClear EP2_IN [4:4] read-write oneToClear EP1_OUT [3:3] read-write oneToClear EP1_IN [2:2] read-write oneToClear EP0_OUT [1:1] read-write oneToClear EP0_IN [0:0] read-write oneToClear USB_MUXING 0x00000074 Where to connect the USB controller. Should be to_phy by default. 0x00000000 SOFTCON [3:3] read-write TO_DIGITAL_PAD [2:2] read-write TO_EXTPHY [1:1] read-write TO_PHY [0:0] read-write USB_PWR 0x00000078 Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable so switch over to the override value. 0x00000000 OVERCURR_DETECT_EN [5:5] read-write OVERCURR_DETECT [4:4] read-write VBUS_DETECT_OVERRIDE_EN [3:3] read-write VBUS_DETECT [2:2] read-write VBUS_EN_OVERRIDE_EN [1:1] read-write VBUS_EN [0:0] read-write USBPHY_DIRECT 0x0000007c Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation Use in conjunction with usbphy_direct_override register 0x00000000 DM_OVV Status bit from USB PHY [22:22] read-only DP_OVV Status bit from USB PHY [21:21] read-only DM_OVCN Status bit from USB PHY [20:20] read-only DP_OVCN Status bit from USB PHY [19:19] read-only RX_DM Status bit from USB PHY DPM pin state [18:18] read-only RX_DP Status bit from USB PHY DPP pin state [17:17] read-only RX_DD Status bit from USB PHY RX Diff data [16:16] read-only TX_DIFFMODE [15:15] read-write TX_FSSLEW [14:14] read-write TX_PD [13:13] read-write RX_PD [12:12] read-write TX_DM Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored TX_SEMODE=1, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM [11:11] read-write TX_DP Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP TX_SEMODE=1, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP [10:10] read-write TX_DM_OE Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, Ignored. TX_SEMODE=1, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving [9:9] read-write TX_DP_OE Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller TX_SEMODE=0, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving TX_SEMODE=1, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving [8:8] read-write DM_PULLDN_EN Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPM [6:6] read-write DM_PULLUP_EN Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpu on DPM [5:5] read-write DM_PULLUP_HISEL when dm_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 [4:4] read-write DP_PULLDN_EN Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller 1 - Enable Rpd on DPP [2:2] read-write DP_PULLUP_EN Value to drive to USB PHY when override enable is set (which will override the default value or value driven from USB controller [1:1] read-write DP_PULLUP_HISEL when dp_pullup_en is set high, this enables second resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 [0:0] read-write USBPHY_DIRECT_OVERRIDE 0x00000080 0x00000000 TX_DIFFMODE_OVERRIDE_EN [15:15] read-write DM_PULLUP_OVERRIDE_EN [12:12] read-write TX_FSSLEW_OVERRIDE_EN [11:11] read-write TX_PD_OVERRIDE_EN [10:10] read-write RX_PD_OVERRIDE_EN [9:9] read-write TX_DM_OVERRIDE_EN Override default value or value driven from USB Controller to PHY [8:8] read-write TX_DP_OVERRIDE_EN Override default value or value driven from USB Controller to PHY [7:7] read-write TX_DM_OE_OVERRIDE_EN Override default value or value driven from USB Controller to PHY [6:6] read-write TX_DP_OE_OVERRIDE_EN Override default value or value driven from USB Controller to PHY [5:5] read-write DM_PULLDN_EN_OVERRIDE_EN Override default value or value driven from USB Controller to PHY [4:4] read-write DP_PULLDN_EN_OVERRIDE_EN Override default value or value driven from USB Controller to PHY [3:3] read-write DP_PULLUP_EN_OVERRIDE_EN Override default value or value driven from USB Controller to PHY [2:2] read-write DM_PULLUP_HISEL_OVERRIDE_EN [1:1] read-write DP_PULLUP_HISEL_OVERRIDE_EN [0:0] read-write USBPHY_TRIM 0x00000084 Note that most functions are driven directly from usb_fsls controller. This register allows more detailed control/status from the USB PHY. Useful for debug but not expected to be used in normal operation 0x00001f1f DM_PULLDN_TRIM Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required [12:8] read-write DP_PULLDN_TRIM Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required [4:0] read-write INTR 0x0000008c Raw Interrupts 0x00000000 EP_STALL_NAK Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. [19:19] read-only ABORT_DONE Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] read-only DEV_SOF Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] read-only SETUP_REQ Device. Source: SIE_STATUS.SETUP_REC [16:16] read-only DEV_RESUME_FROM_HOST Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [15:15] read-only DEV_SUSPEND Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED [14:14] read-only DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED [13:13] read-only BUS_RESET Source: SIE_STATUS.BUS_RESET [12:12] read-only VBUS_DETECT Source: SIE_STATUS.VBUS_DETECT [11:11] read-only STALL Source: SIE_STATUS.STALL_REC [10:10] read-only ERROR_CRC Source: SIE_STATUS.CRC_ERROR [9:9] read-only ERROR_BIT_STUFF Source: SIE_STATUS.BIT_STUFF_ERROR [8:8] read-only ERROR_RX_OVERFLOW Source: SIE_STATUS.RX_OVERFLOW [7:7] read-only ERROR_RX_TIMEOUT Source: SIE_STATUS.RX_TIMEOUT [6:6] read-only ERROR_DATA_SEQ Source: SIE_STATUS.DATA_SEQ_ERROR [5:5] read-only BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. [4:4] read-only TRANS_COMPLETE Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-only HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-only HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [1:1] read-only HOST_CONN_DIS Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] read-only INTE 0x00000090 Interrupt Enable 0x00000000 EP_STALL_NAK Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. [19:19] read-write ABORT_DONE Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] read-write DEV_SOF Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] read-write SETUP_REQ Device. Source: SIE_STATUS.SETUP_REC [16:16] read-write DEV_RESUME_FROM_HOST Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [15:15] read-write DEV_SUSPEND Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED [14:14] read-write DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED [13:13] read-write BUS_RESET Source: SIE_STATUS.BUS_RESET [12:12] read-write VBUS_DETECT Source: SIE_STATUS.VBUS_DETECT [11:11] read-write STALL Source: SIE_STATUS.STALL_REC [10:10] read-write ERROR_CRC Source: SIE_STATUS.CRC_ERROR [9:9] read-write ERROR_BIT_STUFF Source: SIE_STATUS.BIT_STUFF_ERROR [8:8] read-write ERROR_RX_OVERFLOW Source: SIE_STATUS.RX_OVERFLOW [7:7] read-write ERROR_RX_TIMEOUT Source: SIE_STATUS.RX_TIMEOUT [6:6] read-write ERROR_DATA_SEQ Source: SIE_STATUS.DATA_SEQ_ERROR [5:5] read-write BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. [4:4] read-write TRANS_COMPLETE Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-write HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-write HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [1:1] read-write HOST_CONN_DIS Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] read-write INTF 0x00000094 Interrupt Force 0x00000000 EP_STALL_NAK Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. [19:19] read-write ABORT_DONE Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] read-write DEV_SOF Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] read-write SETUP_REQ Device. Source: SIE_STATUS.SETUP_REC [16:16] read-write DEV_RESUME_FROM_HOST Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [15:15] read-write DEV_SUSPEND Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED [14:14] read-write DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED [13:13] read-write BUS_RESET Source: SIE_STATUS.BUS_RESET [12:12] read-write VBUS_DETECT Source: SIE_STATUS.VBUS_DETECT [11:11] read-write STALL Source: SIE_STATUS.STALL_REC [10:10] read-write ERROR_CRC Source: SIE_STATUS.CRC_ERROR [9:9] read-write ERROR_BIT_STUFF Source: SIE_STATUS.BIT_STUFF_ERROR [8:8] read-write ERROR_RX_OVERFLOW Source: SIE_STATUS.RX_OVERFLOW [7:7] read-write ERROR_RX_TIMEOUT Source: SIE_STATUS.RX_TIMEOUT [6:6] read-write ERROR_DATA_SEQ Source: SIE_STATUS.DATA_SEQ_ERROR [5:5] read-write BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. [4:4] read-write TRANS_COMPLETE Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-write HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-write HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [1:1] read-write HOST_CONN_DIS Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] read-write INTS 0x00000098 Interrupt status after masking & forcing 0x00000000 EP_STALL_NAK Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK. [19:19] read-only ABORT_DONE Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE. [18:18] read-only DEV_SOF Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD [17:17] read-only SETUP_REQ Device. Source: SIE_STATUS.SETUP_REC [16:16] read-only DEV_RESUME_FROM_HOST Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [15:15] read-only DEV_SUSPEND Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED [14:14] read-only DEV_CONN_DIS Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED [13:13] read-only BUS_RESET Source: SIE_STATUS.BUS_RESET [12:12] read-only VBUS_DETECT Source: SIE_STATUS.VBUS_DETECT [11:11] read-only STALL Source: SIE_STATUS.STALL_REC [10:10] read-only ERROR_CRC Source: SIE_STATUS.CRC_ERROR [9:9] read-only ERROR_BIT_STUFF Source: SIE_STATUS.BIT_STUFF_ERROR [8:8] read-only ERROR_RX_OVERFLOW Source: SIE_STATUS.RX_OVERFLOW [7:7] read-only ERROR_RX_TIMEOUT Source: SIE_STATUS.RX_TIMEOUT [6:6] read-only ERROR_DATA_SEQ Source: SIE_STATUS.DATA_SEQ_ERROR [5:5] read-only BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS. [4:4] read-only TRANS_COMPLETE Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit. [3:3] read-only HOST_SOF Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD [2:2] read-only HOST_RESUME Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME_REMOTE [1:1] read-only HOST_CONN_DIS Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED [0:0] read-only USB_DPRAM DPRAM layout for USB device. 0x50100000 0 256 registers SETUP_PACKET_LOW 0x00000000 Bytes 0-3 of the SETUP packet from the host. 0x00000000 WVALUE [31:16] read-write BREQUEST [15:8] read-write BMREQUESTTYPE [7:0] read-write SETUP_PACKET_HIGH 0x00000004 Bytes 4-7 of the setup packet from the host. 0x00000000 WLENGTH [31:16] read-write WINDEX [15:0] read-write EP1_IN_CONTROL 0x00000008 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP1_OUT_CONTROL 0x0000000c 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP2_IN_CONTROL 0x00000010 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP2_OUT_CONTROL 0x00000014 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP3_IN_CONTROL 0x00000018 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP3_OUT_CONTROL 0x0000001c 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP4_IN_CONTROL 0x00000020 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP4_OUT_CONTROL 0x00000024 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP5_IN_CONTROL 0x00000028 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP5_OUT_CONTROL 0x0000002c 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP6_IN_CONTROL 0x00000030 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP6_OUT_CONTROL 0x00000034 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP7_IN_CONTROL 0x00000038 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP7_OUT_CONTROL 0x0000003c 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP8_IN_CONTROL 0x00000040 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP8_OUT_CONTROL 0x00000044 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP9_IN_CONTROL 0x00000048 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP9_OUT_CONTROL 0x0000004c 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP10_IN_CONTROL 0x00000050 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP10_OUT_CONTROL 0x00000054 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP11_IN_CONTROL 0x00000058 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP11_OUT_CONTROL 0x0000005c 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP12_IN_CONTROL 0x00000060 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP12_OUT_CONTROL 0x00000064 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP13_IN_CONTROL 0x00000068 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP13_OUT_CONTROL 0x0000006c 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP14_IN_CONTROL 0x00000070 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP14_OUT_CONTROL 0x00000074 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP15_IN_CONTROL 0x00000078 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP15_OUT_CONTROL 0x0000007c 0x00000000 ENABLE Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. [31:31] read-write DOUBLE_BUFFERED This endpoint is double buffered. [30:30] read-write INTERRUPT_PER_BUFF Trigger an interrupt each time a buffer is done. [29:29] read-write INTERRUPT_PER_DOUBLE_BUFF Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. [28:28] read-write ENDPOINT_TYPE [27:26] read-write Control 0 Isochronous 1 Bulk 2 Interrupt 3 INTERRUPT_ON_STALL Trigger an interrupt if a STALL is sent. Intended for debug only. [17:17] read-write INTERRUPT_ON_NAK Trigger an interrupt if a NAK is sent. Intended for debug only. [16:16] read-write BUFFER_ADDRESS 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. [15:0] read-write EP0_IN_BUFFER_CONTROL 0x00000080 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP0_OUT_BUFFER_CONTROL 0x00000084 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP1_IN_BUFFER_CONTROL 0x00000088 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP1_OUT_BUFFER_CONTROL 0x0000008c Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP2_IN_BUFFER_CONTROL 0x00000090 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP2_OUT_BUFFER_CONTROL 0x00000094 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP3_IN_BUFFER_CONTROL 0x00000098 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP3_OUT_BUFFER_CONTROL 0x0000009c Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP4_IN_BUFFER_CONTROL 0x000000a0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP4_OUT_BUFFER_CONTROL 0x000000a4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP5_IN_BUFFER_CONTROL 0x000000a8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP5_OUT_BUFFER_CONTROL 0x000000ac Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP6_IN_BUFFER_CONTROL 0x000000b0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP6_OUT_BUFFER_CONTROL 0x000000b4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP7_IN_BUFFER_CONTROL 0x000000b8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP7_OUT_BUFFER_CONTROL 0x000000bc Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP8_IN_BUFFER_CONTROL 0x000000c0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP8_OUT_BUFFER_CONTROL 0x000000c4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP9_IN_BUFFER_CONTROL 0x000000c8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP9_OUT_BUFFER_CONTROL 0x000000cc Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP10_IN_BUFFER_CONTROL 0x000000d0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP10_OUT_BUFFER_CONTROL 0x000000d4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP11_IN_BUFFER_CONTROL 0x000000d8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP11_OUT_BUFFER_CONTROL 0x000000dc Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP12_IN_BUFFER_CONTROL 0x000000e0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP12_OUT_BUFFER_CONTROL 0x000000e4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP13_IN_BUFFER_CONTROL 0x000000e8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP13_OUT_BUFFER_CONTROL 0x000000ec Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP14_IN_BUFFER_CONTROL 0x000000f0 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP14_OUT_BUFFER_CONTROL 0x000000f4 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP15_IN_BUFFER_CONTROL 0x000000f8 Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write EP15_OUT_BUFFER_CONTROL 0x000000fc Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1. Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. 0x00000000 FULL_1 Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [31:31] read-write LAST_1 Buffer 1 is the last buffer of the transfer. [30:30] read-write PID_1 The data pid of buffer 1. [29:29] read-write DOUBLE_BUFFER_ISO_OFFSET The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint. For a non Isochronous endpoint the offset is always 64 bytes. [28:27] read-write 128 0 256 1 512 2 1024 3 AVAILABLE_1 Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [26:26] read-write LENGTH_1 The length of the data in buffer 1. [25:16] read-write FULL_0 Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. [15:15] read-write LAST_0 Buffer 0 is the last buffer of the transfer. [14:14] read-write PID_0 The data pid of buffer 0. [13:13] read-write RESET Reset the buffer selector to buffer 0. [12:12] read-write STALL Reply with a stall (valid for both buffers). [11:11] read-write AVAILABLE_0 Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. [10:10] read-write LENGTH_0 The length of the data in buffer 0. [9:0] read-write TBMAN Testbench manager. Allows the programmer to know what platform their software is running on. 0x4006c000 0 4 registers PLATFORM 0x00000000 Indicates the type of platform in use 0x00000005 FPGA Indicates the platform is an FPGA [1:1] read-only ASIC Indicates the platform is an ASIC [0:0] read-only VREG_AND_CHIP_RESET control and status for on-chip voltage regulator and chip level reset subsystem 0x40064000 0 12 registers VREG 0x00000000 Voltage regulator control and status 0x000000b1 ROK regulation status 0=not in regulation, 1=in regulation [12:12] read-only VSEL output voltage select 0000 to 0101 - 0.80V 0110 - 0.85V 0111 - 0.90V 1000 - 0.95V 1001 - 1.00V 1010 - 1.05V 1011 - 1.10V (default) 1100 - 1.15V 1101 - 1.20V 1110 - 1.25V 1111 - 1.30V [7:4] read-write HIZ high impedance mode select 0=not in high impedance mode, 1=in high impedance mode [1:1] read-write EN enable 0=not enabled, 1=enabled [0:0] read-write BOD 0x00000004 brown-out detection control 0x00000091 VSEL threshold select 0000 - 0.473V 0001 - 0.516V 0010 - 0.559V 0011 - 0.602V 0100 - 0.645V 0101 - 0.688V 0110 - 0.731V 0111 - 0.774V 1000 - 0.817V 1001 - 0.860V (default) 1010 - 0.903V 1011 - 0.946V 1100 - 0.989V 1101 - 1.032V 1110 - 1.075V 1111 - 1.118V [7:4] read-write EN enable 0=not enabled, 1=enabled [0:0] read-write CHIP_RESET 0x00000008 Chip reset control and status 0x00000000 PSM_RESTART_FLAG This is set by psm_restart from the debugger. Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up. In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor. [24:24] read-write oneToClear HAD_PSM_RESTART Last reset was from the debug port [20:20] read-only HAD_RUN Last reset was from the RUN pin [16:16] read-only HAD_POR Last reset was from the power-on reset or brown-out detection blocks [8:8] read-only RTC Register block to control RTC 0x4005c000 0 48 registers RTC_IRQ 25 CLKDIV_M1 0x00000000 Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled. 0x00000000 CLKDIV_M1 [15:0] read-write SETUP_0 0x00000004 RTC setup register 0 0x00000000 YEAR Year [23:12] read-write MONTH Month (1..12) [11:8] read-write DAY Day of the month (1..31) [4:0] read-write SETUP_1 0x00000008 RTC setup register 1 0x00000000 DOTW Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 [26:24] read-write HOUR Hours [20:16] read-write MIN Minutes [13:8] read-write SEC Seconds [5:0] read-write CTRL 0x0000000c RTC Control and status 0x00000000 FORCE_NOTLEAPYEAR If set, leapyear is forced off. Useful for years divisible by 100 but not by 400 [8:8] read-write LOAD Load RTC [4:4] write-only RTC_ACTIVE RTC enabled (running) [1:1] read-only RTC_ENABLE Enable RTC [0:0] read-write IRQ_SETUP_0 0x00000010 Interrupt setup register 0 0x00000000 MATCH_ACTIVE [29:29] read-only MATCH_ENA Global match enable. Don't change any other value while this one is enabled [28:28] read-write YEAR_ENA Enable year matching [26:26] read-write MONTH_ENA Enable month matching [25:25] read-write DAY_ENA Enable day matching [24:24] read-write YEAR Year [23:12] read-write MONTH Month (1..12) [11:8] read-write DAY Day of the month (1..31) [4:0] read-write IRQ_SETUP_1 0x00000014 Interrupt setup register 1 0x00000000 DOTW_ENA Enable day of the week matching [31:31] read-write HOUR_ENA Enable hour matching [30:30] read-write MIN_ENA Enable minute matching [29:29] read-write SEC_ENA Enable second matching [28:28] read-write DOTW Day of the week [26:24] read-write HOUR Hours [20:16] read-write MIN Minutes [13:8] read-write SEC Seconds [5:0] read-write RTC_1 0x00000018 RTC register 1. 0x00000000 YEAR Year [23:12] read-only MONTH Month (1..12) [11:8] read-only DAY Day of the month (1..31) [4:0] read-only RTC_0 0x0000001c RTC register 0 Read this before RTC 1! 0x00000000 DOTW Day of the week [26:24] read-only modify HOUR Hours [20:16] read-only modify MIN Minutes [13:8] read-only modify SEC Seconds [5:0] read-only modify INTR 0x00000020 Raw Interrupts 0x00000000 RTC [0:0] read-only INTE 0x00000024 Interrupt Enable 0x00000000 RTC [0:0] read-write INTF 0x00000028 Interrupt Force 0x00000000 RTC [0:0] read-write INTS 0x0000002c Interrupt status after masking & forcing 0x00000000 RTC [0:0] read-only SPARE_IRQ 0x00000000 0 4 reserved SPARE_IRQ_0 26 SPARE_IRQ_1 27 SPARE_IRQ_2 28 SPARE_IRQ_3 29 SPARE_IRQ_4 30 SPARE_IRQ_5 31