(kicad_pcb (version 20171130) (host pcbnew "(5.1.6-0-10_14)") (general (thickness 1.6) (drawings 9) (tracks 0) (zones 0) (modules 3) (nets 20) ) (page A4) (layers (0 F.Cu signal) (1 In1.Cu signal) (2 In2.Cu signal) (31 B.Cu signal) (32 B.Adhes user) (33 F.Adhes user) (34 B.Paste user) (35 F.Paste user) (36 B.SilkS user) (37 F.SilkS user) (38 B.Mask user hide) (39 F.Mask user hide) (40 Dwgs.User user hide) (41 Cmts.User user hide) (42 Eco1.User user hide) (43 Eco2.User user hide) (44 Edge.Cuts user) (45 Margin user hide) (46 B.CrtYd user) (47 F.CrtYd user hide) (48 B.Fab user hide) (49 F.Fab user hide) ) (setup (last_trace_width 0.25) (user_trace_width 0.2) (user_trace_width 0.3) (user_trace_width 0.5) (user_trace_width 0.7) (user_trace_width 1.6) (trace_clearance 0.2) (zone_clearance 0.2) (zone_45_only no) (trace_min 0.2) (via_size 0.8) (via_drill 0.4) (via_min_size 0.4) (via_min_drill 0.3) (user_via 0.6 0.3) (uvia_size 0.3) (uvia_drill 0.1) (uvias_allowed no) (uvia_min_size 0.2) (uvia_min_drill 0.1) (edge_width 0.05) (segment_width 0.2) (pcb_text_width 0.3) (pcb_text_size 1.5 1.5) (mod_edge_width 0.12) (mod_text_size 1 1) (mod_text_width 0.15) (pad_size 0.7 4.3) (pad_drill 0) (pad_to_mask_clearance 0.051) (solder_mask_min_width 0.25) (aux_axis_origin 0 0) (visible_elements FFFFFF7F) (pcbplotparams (layerselection 0x010fc_ffffffff) (usegerberextensions false) (usegerberattributes false) (usegerberadvancedattributes false) (creategerberjobfile false) (excludeedgelayer true) (linewidth 0.100000) (plotframeref false) (viasonmask false) (mode 1) (useauxorigin false) (hpglpennumber 1) (hpglpenspeed 20) (hpglpendiameter 15.000000) (psnegative false) (psa4output false) (plotreference true) (plotvalue true) (plotinvisibletext false) (padsonsilk false) (subtractmaskfromsilk false) (outputformat 1) (mirror false) (drillshape 0) (scaleselection 1) (outputdirectory "Fab Files/")) ) (net 0 "") (net 1 GND) (net 2 VBUS) (net 3 /hTX) (net 4 /hRX) (net 5 /hRTS) (net 6 /hCTS) (net 7 /hDCD) (net 8 /hDTR) (net 9 /hRI) (net 10 +BATT) (net 11 /PWROK) (net 12 /TMS) (net 13 /TDI) (net 14 /TCK) (net 15 /SW_PWR) (net 16 /TRST) (net 17 /SMDAT) (net 18 /SMCLK) (net 19 /SYSID) (net_class Default "This is the default net class." (clearance 0.2) (trace_width 0.25) (via_dia 0.8) (via_drill 0.4) (uvia_dia 0.3) (uvia_drill 0.1) (add_net +BATT) (add_net /PWROK) (add_net /SMCLK) (add_net /SMDAT) (add_net /SW_PWR) (add_net /SYSID) (add_net /TCK) (add_net /TDI) (add_net /TMS) (add_net /TRST) (add_net /hCTS) (add_net /hDCD) (add_net /hDTR) (add_net /hRI) (add_net /hRTS) (add_net /hRX) (add_net /hTX) (add_net GND) (add_net VBUS) ) (module MountingHole:MountingHole_2.7mm_M2.5_ISO7380_Pad (layer F.Cu) (tedit 56D1B4CB) (tstamp 5E617B37) (at 127.6 112.9 180) (descr "Mounting Hole 2.7mm, M2.5, ISO7380") (tags "mounting hole 2.7mm m2.5 iso7380") (path /5F0C61BC) (attr virtual) (fp_text reference H1 (at 0 -3.25) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value MountingHole_Pad (at 0 3.25) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_circle (center 0 0) (end 2.5 0) (layer F.CrtYd) (width 0.05)) (fp_circle (center 0 0) (end 2.25 0) (layer Cmts.User) (width 0.15)) (fp_text user %R (at 0.3 0) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole circle (at 0 0 180) (size 4.5 4.5) (drill 2.7) (layers *.Cu *.Mask) (net 1 GND)) ) (module MountingHole:MountingHole_2.7mm_M2.5_ISO7380_Pad (layer F.Cu) (tedit 56D1B4CB) (tstamp 5E616266) (at 127.6 88.7 180) (descr "Mounting Hole 2.7mm, M2.5, ISO7380") (tags "mounting hole 2.7mm m2.5 iso7380") (path /60D0EE9E) (attr virtual) (fp_text reference H2 (at 0 -3.25) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value MountingHole_Pad (at 0 3.25) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_circle (center 0 0) (end 2.5 0) (layer F.CrtYd) (width 0.05)) (fp_circle (center 0 0) (end 2.25 0) (layer Cmts.User) (width 0.15)) (fp_text user %R (at 0.3 0) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (pad 1 thru_hole circle (at 0 0 180) (size 4.5 4.5) (drill 2.7) (layers *.Cu *.Mask) (net 1 GND)) ) (module Connector_PCBEdge:BUS_PCIexpress_x1 (layer F.Cu) (tedit 5E6085AC) (tstamp 5E610363) (at 172.25 112.25 90) (descr "PCIexpress Bus Edge Connector x1 http://www.ritrontek.com/uploadfile/2016/1026/20161026105231124.pdf#page=70") (tags PCIe) (path /5E618E7D) (attr virtual) (fp_text reference J4 (at 5 -3.5 90) (layer F.SilkS) hide (effects (font (size 1 1) (thickness 0.15))) ) (fp_text value PCIExpress (at 10.33 -8.01 90) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_line (start -1.15 -5.45) (end 20.15 -5.45) (layer F.CrtYd) (width 0.05)) (fp_line (start -1.15 -5.45) (end -1.15 3.95) (layer F.CrtYd) (width 0.05)) (fp_line (start 20.15 3.95) (end 20.15 -5.45) (layer F.CrtYd) (width 0.05)) (fp_line (start 20.15 3.95) (end -1.15 3.95) (layer F.CrtYd) (width 0.05)) (fp_line (start 10.55 -4) (end 10.55 2.95) (layer Edge.Cuts) (width 0.1)) (fp_line (start 12.45 -4) (end 12.45 2.95) (layer Edge.Cuts) (width 0.1)) (fp_line (start -0.65 -4.95) (end -0.65 2.95) (layer Edge.Cuts) (width 0.1)) (fp_line (start -0.15 3.45) (end 10.05 3.45) (layer Edge.Cuts) (width 0.1)) (fp_line (start 19.65 -4.95) (end 19.65 2.95) (layer Edge.Cuts) (width 0.1)) (fp_line (start 12.95 3.45) (end 19.15 3.45) (layer Edge.Cuts) (width 0.1)) (fp_line (start -0.65 2.95) (end -0.15 3.45) (layer Edge.Cuts) (width 0.1)) (fp_line (start 10.55 2.95) (end 10.05 3.45) (layer Edge.Cuts) (width 0.1)) (fp_line (start 12.45 2.95) (end 12.95 3.45) (layer Edge.Cuts) (width 0.1)) (fp_line (start 19.65 2.95) (end 19.15 3.45) (layer Edge.Cuts) (width 0.1)) (fp_text user %R (at 16 -3.5 90) (layer F.Fab) (effects (font (size 1 1) (thickness 0.15))) ) (fp_text user "PCB Thickness 1.57 mm" (at 5 2.8 270) (layer Cmts.User) (effects (font (size 0.5 0.5) (thickness 0.1))) ) (fp_arc (start 11.5 -4) (end 12.45 -4) (angle -180) (layer Edge.Cuts) (width 0.1)) (pad b1 connect rect (at 0 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 10 +BATT)) (pad b2 connect rect (at 1 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 10 +BATT)) (pad b3 connect rect (at 2 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 19 /SYSID)) (pad b4 connect rect (at 3 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 1 GND)) (pad b5 connect rect (at 4 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 18 /SMCLK)) (pad b6 connect rect (at 5 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 17 /SMDAT)) (pad b7 connect rect (at 6 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 1 GND)) (pad b8 connect rect (at 7 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 2 VBUS)) (pad b9 connect rect (at 8 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 16 /TRST)) (pad b10 connect rect (at 9 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 2 VBUS)) (pad b11 connect rect (at 10 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 15 /SW_PWR)) (pad b14 connect rect (at 15 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 3 /hTX)) (pad b15 connect rect (at 16 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 5 /hRTS)) (pad b16 connect rect (at 17 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 1 GND)) (pad b17 connect rect (at 18 -0.55 90) (size 0.7 3.2) (layers F.Cu F.Mask) (net 1 GND)) (pad b18 connect rect (at 19 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 1 GND)) (pad b12 connect rect (at 13 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 9 /hRI)) (pad b13 connect rect (at 14 0 90) (size 0.7 4.3) (layers F.Cu F.Mask) (net 1 GND)) (pad a1 connect rect (at 0 -0.55 90) (size 0.7 3.2) (layers B.Cu B.Mask) (net 1 GND)) (pad a2 connect rect (at 1 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 10 +BATT)) (pad a3 connect rect (at 2 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 10 +BATT)) (pad a4 connect rect (at 3 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 1 GND)) (pad a5 connect rect (at 4 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 14 /TCK)) (pad a6 connect rect (at 5 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 13 /TDI)) (pad a7 connect rect (at 6 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 13 /TDI)) (pad a8 connect rect (at 7 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 12 /TMS)) (pad a9 connect rect (at 8 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 2 VBUS)) (pad a10 connect rect (at 9 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 2 VBUS)) (pad a11 connect rect (at 10 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 11 /PWROK)) (pad a14 connect rect (at 15 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 7 /hDCD)) (pad a15 connect rect (at 16 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 1 GND)) (pad a16 connect rect (at 17 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 4 /hRX)) (pad a17 connect rect (at 18 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 6 /hCTS)) (pad a18 connect rect (at 19 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 1 GND)) (pad a12 connect rect (at 13 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 1 GND)) (pad a13 connect rect (at 14 0 90) (size 0.7 4.3) (layers B.Cu B.Mask) (net 8 /hDTR)) ) (gr_line (start 167.3 112.9) (end 165.7 112.9) (layer Edge.Cuts) (width 0.1) (tstamp 5E610329)) (gr_text puccilabs.com (at 163 95.7 90) (layer F.SilkS) (effects (font (size 1.5 1.5) (thickness 0.3))) ) (gr_text X1 (at 137.1 112.4) (layer F.SilkS) (effects (font (size 5 5) (thickness 1.25))) ) (gr_line (start 165.7 92.6) (end 165.7 85.8) (layer Edge.Cuts) (width 0.1) (tstamp 5E67593C)) (gr_line (start 167.3 92.6) (end 165.7 92.6) (layer Edge.Cuts) (width 0.1)) (gr_line (start 165.7 115.8) (end 124.7 115.8) (layer Edge.Cuts) (width 0.1) (tstamp 5E612064)) (gr_line (start 124.7 85.8) (end 165.7 85.8) (layer Edge.Cuts) (width 0.1) (tstamp 5E6105C9)) (gr_line (start 165.7 112.9) (end 165.7 115.8) (layer Edge.Cuts) (width 0.1)) (gr_line (start 124.7 85.8) (end 124.7 115.8) (layer Edge.Cuts) (width 0.1)) )