$ cpu-info

Packages:
	0: Unknown
Microarchitectures:
	8x Cortex-A55
Cores:
	0: 1 processor (0), ARM Cortex-A55
	1: 1 processor (1), ARM Cortex-A55
	2: 1 processor (2), ARM Cortex-A55
	3: 1 processor (3), ARM Cortex-A55
	4: 1 processor (4), ARM Cortex-A55
	5: 1 processor (5), ARM Cortex-A55
	6: 1 processor (6), ARM Cortex-A55
	7: 1 processor (7), ARM Cortex-A55
Clusters:
	0: 8 processors (0-7),	0: 8 cores (0-7), ARM Cortex-A55
Logical processors (System ID):
	0 (0)
	1 (1)
	2 (2)
	3 (3)
	4 (4)
	5 (5)
	6 (6)
	7 (7)

$ isa-info

Instruction sets:
	ARM v8.1 atomics: yes
	ARM v8.1 SQRDMLxH: yes
	ARM v8.2 FP16 arithmetics: yes
	ARM v8.2 FHM: no
	ARM v8.2 BF16: no
	ARM v8.2 Int8 dot product: yes
	ARM v8.2 Int8 matrix multiplication: no
	ARM v8.3 JS conversion: no
	ARM v8.3 complex: no
SIMD extensions:
	ARM SVE: no
	ARM SVE 2: no
	ARM SME: no
	ARM SME 2: no
ARM SVE Capabilities:
	SVE max length: 0
	SME max length: 0
Cryptography extensions:
	AES: yes
	SHA1: yes
	SHA2: yes
	PMULL: yes
	CRC32: yes

$ cache-info

Max cache size (upper bound): 4194304 bytes
L1 instruction cache: 8 x 32 KB, 4-way set associative (128 sets), 64 byte lines, shared by 1 processors
L1 data cache: 8 x 32 KB, 4-way set associative (128 sets), 64 byte lines, shared by 1 processors
L2 data cache: 8 x 128 KB (exclusive), 4-way set associative (512 sets), 64 byte lines, shared by 1 processors
L3 data cache: 1 MB (exclusive), 16-way set associative (1024 sets), 64 byte lines, shared by 8 processors