"F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Debug1.v" Line 63: Port ps2_clk is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 75: Port dbg_keyLine is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 82: Port segment is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 97: Port rdn is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 127: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 128: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 129: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 130: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 137: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 138: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 139: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 140: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 148: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 149: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 150: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 151: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 152: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 153: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 154: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 155: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 156: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 157: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 158: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 159: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 551: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 552: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 557: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 568: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 576: Port wea is not connected to this instance "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Debug1.v" Line 69: Size mismatch in connection of port <debugaddr>. Formal port size is 10-bit while actual signal size is 1-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Debug1.v" Line 72: Size mismatch in connection of port <debugvgad>. Formal port size is 12-bit while actual signal size is 1-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 127: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 128: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 129: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 130: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 137: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 138: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 139: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 140: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 148: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 149: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 150: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 151: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 152: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 153: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 154: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 155: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 156: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 157: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 158: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/RecursionBox/RecursionBox/Top.v" Line 159: Size mismatch in connection of port <addra>. Formal port size is 10-bit while actual signal size is 32-bit. Unable to copy libPortabilityNOSH.dll to the simulation executable directory: boost::filesystem::copy_file: ￏﾵￍﾳￕￒﾲﾻﾵﾽￖﾸﾶﾨﾵￄￂﾷﾾﾶﾡﾣ, "isim\Debug1_isim_beh.exe.sim\libPortability.dll".