INFO:sim:172 - Generating IP...
Resolving generics for 'Lvpic'...
Applying external generics to 'Lvpic'...
Delivering associated files for 'Lvpic'...
Delivering EJava files for 'Lvpic'...
Generating implementation netlist for 'Lvpic'...
INFO:sim - Pre-processing HDL files for 'Lvpic'...
Running synthesis for 'Lvpic'
Running ngcbuild...
Writing VEO instantiation template for 'Lvpic'...
Writing Verilog behavioral simulation model for 'Lvpic'...
WARNING:sim - Overwriting existing file
   F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/
   VGAdemo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic/doc/blk_mem_gen_v7_3_vinfo.html with
   file from view xilinx_documentation
Delivered 1 file into directory
F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/VGA
demo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'Lvpic'...
Generating metadata file...
Generating ISE project file for 'Lvpic'...
Generating ISE project...
XCO file found: Lvpic.xco
XMDF file found: Lvpic_xmdf.tcl
Adding
F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/VGA
demo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic.asy -view all -origin_type imported
Adding
F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/VGA
demo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic.ngc -view all -origin_type created
Checking file
"F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/VG
Ademo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic.ngc" for project device match ...
File
"F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/VG
Ademo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic.ngc" device information matches project
device.
Adding
F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/VGA
demo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic.sym -view all -origin_type imported
Adding
F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/VGA
demo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic.v -view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020
   /VGAdemo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
F:/_TOT_FILES/ZJU/A_1_Course/2_1/Digital_Logic_Design/project/bigProgram2020/VGA
demo/VGAdemo/ipcore_dir/tmp/_cg/Lvpic.veo -view all -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/Lvpic"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'Lvpic'.