extern void __VERIFIER_error() __attribute__ ((__noreturn__)); /* Generated by CIL v. 1.5.1 */ /* print_CIL_Input is false */ typedef unsigned char __u8; typedef unsigned short __u16; typedef int __s32; typedef unsigned int __u32; typedef unsigned long long __u64; typedef signed char s8; typedef unsigned char u8; typedef unsigned short u16; typedef int s32; typedef unsigned int u32; typedef long long s64; typedef unsigned long long u64; typedef long __kernel_long_t; typedef unsigned long __kernel_ulong_t; typedef int __kernel_pid_t; typedef __kernel_long_t __kernel_suseconds_t; typedef unsigned int __kernel_uid32_t; typedef unsigned int __kernel_gid32_t; typedef __kernel_ulong_t __kernel_size_t; typedef __kernel_long_t __kernel_ssize_t; typedef long long __kernel_loff_t; typedef __kernel_long_t __kernel_time_t; typedef __kernel_long_t __kernel_clock_t; typedef int __kernel_timer_t; typedef int __kernel_clockid_t; struct kernel_symbol { unsigned long value ; char const *name ; }; struct module; typedef __u32 __kernel_dev_t; typedef __kernel_dev_t dev_t; typedef unsigned short umode_t; typedef __kernel_pid_t pid_t; typedef __kernel_clockid_t clockid_t; typedef _Bool bool; typedef __kernel_uid32_t uid_t; typedef __kernel_gid32_t gid_t; typedef __kernel_loff_t loff_t; typedef __kernel_size_t size_t; typedef __kernel_ssize_t ssize_t; typedef __kernel_time_t time_t; typedef __s32 int32_t; typedef __u8 uint8_t; typedef __u16 uint16_t; typedef __u32 uint32_t; typedef __u64 uint64_t; typedef unsigned long sector_t; typedef unsigned long blkcnt_t; typedef u64 dma_addr_t; typedef unsigned int gfp_t; typedef unsigned int fmode_t; typedef unsigned int oom_flags_t; typedef u64 phys_addr_t; typedef phys_addr_t resource_size_t; struct __anonstruct_atomic_t_6 { int counter ; }; typedef struct __anonstruct_atomic_t_6 atomic_t; struct __anonstruct_atomic64_t_7 { long counter ; }; typedef struct __anonstruct_atomic64_t_7 atomic64_t; struct list_head { struct list_head *next ; struct list_head *prev ; }; struct hlist_node; struct hlist_head { struct hlist_node *first ; }; struct hlist_node { struct hlist_node *next ; struct hlist_node **pprev ; }; struct callback_head { struct callback_head *next ; void (*func)(struct callback_head * ) ; }; struct pt_regs { unsigned long r15 ; unsigned long r14 ; unsigned long r13 ; unsigned long r12 ; unsigned long bp ; unsigned long bx ; unsigned long r11 ; unsigned long r10 ; unsigned long r9 ; unsigned long r8 ; unsigned long ax ; unsigned long cx ; unsigned long dx ; unsigned long si ; unsigned long di ; unsigned long orig_ax ; unsigned long ip ; unsigned long cs ; unsigned long flags ; unsigned long sp ; unsigned long ss ; }; struct __anonstruct____missing_field_name_9 { unsigned int a ; unsigned int b ; }; struct __anonstruct____missing_field_name_10 { u16 limit0 ; u16 base0 ; unsigned char base1 ; unsigned char type : 4 ; unsigned char s : 1 ; unsigned char dpl : 2 ; unsigned char p : 1 ; unsigned char limit : 4 ; unsigned char avl : 1 ; unsigned char l : 1 ; unsigned char d : 1 ; unsigned char g : 1 ; unsigned char base2 ; }; union __anonunion____missing_field_name_8 { struct __anonstruct____missing_field_name_9 __annonCompField4 ; struct __anonstruct____missing_field_name_10 __annonCompField5 ; }; struct desc_struct { union __anonunion____missing_field_name_8 __annonCompField6 ; }; typedef unsigned long pteval_t; typedef unsigned long pgdval_t; typedef unsigned long pgprotval_t; struct __anonstruct_pte_t_11 { pteval_t pte ; }; typedef struct __anonstruct_pte_t_11 pte_t; struct pgprot { pgprotval_t pgprot ; }; typedef struct pgprot pgprot_t; struct __anonstruct_pgd_t_12 { pgdval_t pgd ; }; typedef struct __anonstruct_pgd_t_12 pgd_t; struct page; typedef struct page *pgtable_t; struct file; struct seq_file; struct thread_struct; struct mm_struct; struct task_struct; struct cpumask; struct qspinlock { atomic_t val ; }; typedef struct qspinlock arch_spinlock_t; struct qrwlock { atomic_t cnts ; arch_spinlock_t lock ; }; typedef struct qrwlock arch_rwlock_t; typedef void (*ctor_fn_t)(void); struct device; struct file_operations; struct completion; struct bug_entry { int bug_addr_disp ; int file_disp ; unsigned short line ; unsigned short flags ; }; struct timespec; struct compat_timespec; struct __anonstruct_futex_16 { u32 *uaddr ; u32 val ; u32 flags ; u32 bitset ; u64 time ; u32 *uaddr2 ; }; struct __anonstruct_nanosleep_17 { clockid_t clockid ; struct timespec *rmtp ; struct compat_timespec *compat_rmtp ; u64 expires ; }; struct pollfd; struct __anonstruct_poll_18 { struct pollfd *ufds ; int nfds ; int has_timeout ; unsigned long tv_sec ; unsigned long tv_nsec ; }; union __anonunion____missing_field_name_15 { struct __anonstruct_futex_16 futex ; struct __anonstruct_nanosleep_17 nanosleep ; struct __anonstruct_poll_18 poll ; }; struct restart_block { long (*fn)(struct restart_block * ) ; union __anonunion____missing_field_name_15 __annonCompField7 ; }; struct kernel_vm86_regs { struct pt_regs pt ; unsigned short es ; unsigned short __esh ; unsigned short ds ; unsigned short __dsh ; unsigned short fs ; unsigned short __fsh ; unsigned short gs ; unsigned short __gsh ; }; union __anonunion____missing_field_name_19 { struct pt_regs *regs ; struct kernel_vm86_regs *vm86 ; }; struct math_emu_info { long ___orig_eip ; union __anonunion____missing_field_name_19 __annonCompField8 ; }; struct cpumask { unsigned long bits[128U] ; }; typedef struct cpumask cpumask_t; typedef struct cpumask *cpumask_var_t; struct fregs_state { u32 cwd ; u32 swd ; u32 twd ; u32 fip ; u32 fcs ; u32 foo ; u32 fos ; u32 st_space[20U] ; u32 status ; }; struct __anonstruct____missing_field_name_29 { u64 rip ; u64 rdp ; }; struct __anonstruct____missing_field_name_30 { u32 fip ; u32 fcs ; u32 foo ; u32 fos ; }; union __anonunion____missing_field_name_28 { struct __anonstruct____missing_field_name_29 __annonCompField12 ; struct __anonstruct____missing_field_name_30 __annonCompField13 ; }; union __anonunion____missing_field_name_31 { u32 padding1[12U] ; u32 sw_reserved[12U] ; }; struct fxregs_state { u16 cwd ; u16 swd ; u16 twd ; u16 fop ; union __anonunion____missing_field_name_28 __annonCompField14 ; u32 mxcsr ; u32 mxcsr_mask ; u32 st_space[32U] ; u32 xmm_space[64U] ; u32 padding[12U] ; union __anonunion____missing_field_name_31 __annonCompField15 ; }; struct swregs_state { u32 cwd ; u32 swd ; u32 twd ; u32 fip ; u32 fcs ; u32 foo ; u32 fos ; u32 st_space[20U] ; u8 ftop ; u8 changed ; u8 lookahead ; u8 no_update ; u8 rm ; u8 alimit ; struct math_emu_info *info ; u32 entry_eip ; }; struct xstate_header { u64 xfeatures ; u64 xcomp_bv ; u64 reserved[6U] ; }; struct xregs_state { struct fxregs_state i387 ; struct xstate_header header ; u8 __reserved[464U] ; }; union fpregs_state { struct fregs_state fsave ; struct fxregs_state fxsave ; struct swregs_state soft ; struct xregs_state xsave ; }; struct fpu { union fpregs_state state ; unsigned int last_cpu ; unsigned char fpstate_active ; unsigned char fpregs_active ; unsigned char counter ; }; struct seq_operations; struct perf_event; struct thread_struct { struct desc_struct tls_array[3U] ; unsigned long sp0 ; unsigned long sp ; unsigned short es ; unsigned short ds ; unsigned short fsindex ; unsigned short gsindex ; unsigned long fs ; unsigned long gs ; struct fpu fpu ; struct perf_event *ptrace_bps[4U] ; unsigned long debugreg6 ; unsigned long ptrace_dr7 ; unsigned long cr2 ; unsigned long trap_nr ; unsigned long error_code ; unsigned long *io_bitmap_ptr ; unsigned long iopl ; unsigned int io_bitmap_max ; }; typedef atomic64_t atomic_long_t; struct lockdep_map; struct stack_trace { unsigned int nr_entries ; unsigned int max_entries ; unsigned long *entries ; int skip ; }; struct lockdep_subclass_key { char __one_byte ; }; struct lock_class_key { struct lockdep_subclass_key subkeys[8U] ; }; struct lock_class { struct list_head hash_entry ; struct list_head lock_entry ; struct lockdep_subclass_key *key ; unsigned int subclass ; unsigned int dep_gen_id ; unsigned long usage_mask ; struct stack_trace usage_traces[13U] ; struct list_head locks_after ; struct list_head locks_before ; unsigned int version ; unsigned long ops ; char const *name ; int name_version ; unsigned long contention_point[4U] ; unsigned long contending_point[4U] ; }; struct lockdep_map { struct lock_class_key *key ; struct lock_class *class_cache[2U] ; char const *name ; int cpu ; unsigned long ip ; }; struct held_lock { u64 prev_chain_key ; unsigned long acquire_ip ; struct lockdep_map *instance ; struct lockdep_map *nest_lock ; u64 waittime_stamp ; u64 holdtime_stamp ; unsigned short class_idx : 13 ; unsigned char irq_context : 2 ; unsigned char trylock : 1 ; unsigned char read : 2 ; unsigned char check : 1 ; unsigned char hardirqs_off : 1 ; unsigned short references : 12 ; unsigned int pin_count ; }; struct raw_spinlock { arch_spinlock_t raw_lock ; unsigned int magic ; unsigned int owner_cpu ; void *owner ; struct lockdep_map dep_map ; }; typedef struct raw_spinlock raw_spinlock_t; struct __anonstruct____missing_field_name_35 { u8 __padding[24U] ; struct lockdep_map dep_map ; }; union __anonunion____missing_field_name_34 { struct raw_spinlock rlock ; struct __anonstruct____missing_field_name_35 __annonCompField17 ; }; struct spinlock { union __anonunion____missing_field_name_34 __annonCompField18 ; }; typedef struct spinlock spinlock_t; struct __anonstruct_rwlock_t_36 { arch_rwlock_t raw_lock ; unsigned int magic ; unsigned int owner_cpu ; void *owner ; struct lockdep_map dep_map ; }; typedef struct __anonstruct_rwlock_t_36 rwlock_t; struct seqcount { unsigned int sequence ; struct lockdep_map dep_map ; }; typedef struct seqcount seqcount_t; struct __anonstruct_seqlock_t_45 { struct seqcount seqcount ; spinlock_t lock ; }; typedef struct __anonstruct_seqlock_t_45 seqlock_t; struct timespec { __kernel_time_t tv_sec ; long tv_nsec ; }; struct timeval { __kernel_time_t tv_sec ; __kernel_suseconds_t tv_usec ; }; struct user_namespace; struct __anonstruct_kuid_t_46 { uid_t val ; }; typedef struct __anonstruct_kuid_t_46 kuid_t; struct __anonstruct_kgid_t_47 { gid_t val ; }; typedef struct __anonstruct_kgid_t_47 kgid_t; struct kstat { u64 ino ; dev_t dev ; umode_t mode ; unsigned int nlink ; kuid_t uid ; kgid_t gid ; dev_t rdev ; loff_t size ; struct timespec atime ; struct timespec mtime ; struct timespec ctime ; unsigned long blksize ; unsigned long long blocks ; }; struct vm_area_struct; struct __wait_queue_head { spinlock_t lock ; struct list_head task_list ; }; typedef struct __wait_queue_head wait_queue_head_t; struct __anonstruct_nodemask_t_48 { unsigned long bits[16U] ; }; typedef struct __anonstruct_nodemask_t_48 nodemask_t; struct optimistic_spin_queue { atomic_t tail ; }; struct mutex { atomic_t count ; spinlock_t wait_lock ; struct list_head wait_list ; struct task_struct *owner ; void *magic ; struct lockdep_map dep_map ; }; struct mutex_waiter { struct list_head list ; struct task_struct *task ; void *magic ; }; struct rw_semaphore; struct rw_semaphore { long count ; struct list_head wait_list ; raw_spinlock_t wait_lock ; struct optimistic_spin_queue osq ; struct task_struct *owner ; struct lockdep_map dep_map ; }; struct completion { unsigned int done ; wait_queue_head_t wait ; }; union ktime { s64 tv64 ; }; typedef union ktime ktime_t; struct notifier_block; struct timer_list { struct hlist_node entry ; unsigned long expires ; void (*function)(unsigned long ) ; unsigned long data ; u32 flags ; int slack ; int start_pid ; void *start_site ; char start_comm[16U] ; struct lockdep_map lockdep_map ; }; struct hrtimer; enum hrtimer_restart; struct rb_node { unsigned long __rb_parent_color ; struct rb_node *rb_right ; struct rb_node *rb_left ; }; struct rb_root { struct rb_node *rb_node ; }; struct nsproxy; struct workqueue_struct; struct work_struct; struct work_struct { atomic_long_t data ; struct list_head entry ; void (*func)(struct work_struct * ) ; struct lockdep_map lockdep_map ; }; struct delayed_work { struct work_struct work ; struct timer_list timer ; struct workqueue_struct *wq ; int cpu ; }; struct notifier_block { int (*notifier_call)(struct notifier_block * , unsigned long , void * ) ; struct notifier_block *next ; int priority ; }; struct resource { resource_size_t start ; resource_size_t end ; char const *name ; unsigned long flags ; struct resource *parent ; struct resource *sibling ; struct resource *child ; }; struct pci_dev; struct pm_message { int event ; }; typedef struct pm_message pm_message_t; struct dev_pm_ops { int (*prepare)(struct device * ) ; void (*complete)(struct device * ) ; int (*suspend)(struct device * ) ; int (*resume)(struct device * ) ; int (*freeze)(struct device * ) ; int (*thaw)(struct device * ) ; int (*poweroff)(struct device * ) ; int (*restore)(struct device * ) ; int (*suspend_late)(struct device * ) ; int (*resume_early)(struct device * ) ; int (*freeze_late)(struct device * ) ; int (*thaw_early)(struct device * ) ; int (*poweroff_late)(struct device * ) ; int (*restore_early)(struct device * ) ; int (*suspend_noirq)(struct device * ) ; int (*resume_noirq)(struct device * ) ; int (*freeze_noirq)(struct device * ) ; int (*thaw_noirq)(struct device * ) ; int (*poweroff_noirq)(struct device * ) ; int (*restore_noirq)(struct device * ) ; int (*runtime_suspend)(struct device * ) ; int (*runtime_resume)(struct device * ) ; int (*runtime_idle)(struct device * ) ; }; enum rpm_status { RPM_ACTIVE = 0, RPM_RESUMING = 1, RPM_SUSPENDED = 2, RPM_SUSPENDING = 3 } ; enum rpm_request { RPM_REQ_NONE = 0, RPM_REQ_IDLE = 1, RPM_REQ_SUSPEND = 2, RPM_REQ_AUTOSUSPEND = 3, RPM_REQ_RESUME = 4 } ; struct wakeup_source; struct wake_irq; struct pm_subsys_data { spinlock_t lock ; unsigned int refcount ; struct list_head clock_list ; }; struct dev_pm_qos; struct dev_pm_info { pm_message_t power_state ; unsigned char can_wakeup : 1 ; unsigned char async_suspend : 1 ; bool is_prepared ; bool is_suspended ; bool is_noirq_suspended ; bool is_late_suspended ; bool ignore_children ; bool early_init ; bool direct_complete ; spinlock_t lock ; struct list_head entry ; struct completion completion ; struct wakeup_source *wakeup ; bool wakeup_path ; bool syscore ; struct timer_list suspend_timer ; unsigned long timer_expires ; struct work_struct work ; wait_queue_head_t wait_queue ; struct wake_irq *wakeirq ; atomic_t usage_count ; atomic_t child_count ; unsigned char disable_depth : 3 ; unsigned char idle_notification : 1 ; unsigned char request_pending : 1 ; unsigned char deferred_resume : 1 ; unsigned char run_wake : 1 ; unsigned char runtime_auto : 1 ; unsigned char no_callbacks : 1 ; unsigned char irq_safe : 1 ; unsigned char use_autosuspend : 1 ; unsigned char timer_autosuspends : 1 ; unsigned char memalloc_noio : 1 ; enum rpm_request request ; enum rpm_status runtime_status ; int runtime_error ; int autosuspend_delay ; unsigned long last_busy ; unsigned long active_jiffies ; unsigned long suspended_jiffies ; unsigned long accounting_timestamp ; struct pm_subsys_data *subsys_data ; void (*set_latency_tolerance)(struct device * , s32 ) ; struct dev_pm_qos *qos ; }; struct dev_pm_domain { struct dev_pm_ops ops ; void (*detach)(struct device * , bool ) ; int (*activate)(struct device * ) ; void (*sync)(struct device * ) ; void (*dismiss)(struct device * ) ; }; struct pci_bus; struct __anonstruct_mm_context_t_115 { void *ldt ; int size ; unsigned short ia32_compat ; struct mutex lock ; void *vdso ; atomic_t perf_rdpmc_allowed ; }; typedef struct __anonstruct_mm_context_t_115 mm_context_t; struct llist_node; struct llist_head { struct llist_node *first ; }; struct llist_node { struct llist_node *next ; }; struct cred; struct inode; struct arch_uprobe_task { unsigned long saved_scratch_register ; unsigned int saved_trap_nr ; unsigned int saved_tf ; }; enum uprobe_task_state { UTASK_RUNNING = 0, UTASK_SSTEP = 1, UTASK_SSTEP_ACK = 2, UTASK_SSTEP_TRAPPED = 3 } ; struct __anonstruct____missing_field_name_148 { struct arch_uprobe_task autask ; unsigned long vaddr ; }; struct __anonstruct____missing_field_name_149 { struct callback_head dup_xol_work ; unsigned long dup_xol_addr ; }; union __anonunion____missing_field_name_147 { struct __anonstruct____missing_field_name_148 __annonCompField33 ; struct __anonstruct____missing_field_name_149 __annonCompField34 ; }; struct uprobe; struct return_instance; struct uprobe_task { enum uprobe_task_state state ; union __anonunion____missing_field_name_147 __annonCompField35 ; struct uprobe *active_uprobe ; unsigned long xol_vaddr ; struct return_instance *return_instances ; unsigned int depth ; }; struct xol_area; struct uprobes_state { struct xol_area *xol_area ; }; struct address_space; struct mem_cgroup; typedef void compound_page_dtor(struct page * ); union __anonunion____missing_field_name_150 { struct address_space *mapping ; void *s_mem ; }; union __anonunion____missing_field_name_152 { unsigned long index ; void *freelist ; bool pfmemalloc ; }; struct __anonstruct____missing_field_name_156 { unsigned short inuse ; unsigned short objects : 15 ; unsigned char frozen : 1 ; }; union __anonunion____missing_field_name_155 { atomic_t _mapcount ; struct __anonstruct____missing_field_name_156 __annonCompField38 ; int units ; }; struct __anonstruct____missing_field_name_154 { union __anonunion____missing_field_name_155 __annonCompField39 ; atomic_t _count ; }; union __anonunion____missing_field_name_153 { unsigned long counters ; struct __anonstruct____missing_field_name_154 __annonCompField40 ; unsigned int active ; }; struct __anonstruct____missing_field_name_151 { union __anonunion____missing_field_name_152 __annonCompField37 ; union __anonunion____missing_field_name_153 __annonCompField41 ; }; struct __anonstruct____missing_field_name_158 { struct page *next ; int pages ; int pobjects ; }; struct slab; struct __anonstruct____missing_field_name_159 { compound_page_dtor *compound_dtor ; unsigned long compound_order ; }; union __anonunion____missing_field_name_157 { struct list_head lru ; struct __anonstruct____missing_field_name_158 __annonCompField43 ; struct slab *slab_page ; struct callback_head callback_head ; struct __anonstruct____missing_field_name_159 __annonCompField44 ; pgtable_t pmd_huge_pte ; }; struct kmem_cache; union __anonunion____missing_field_name_160 { unsigned long private ; spinlock_t *ptl ; struct kmem_cache *slab_cache ; struct page *first_page ; }; struct page { unsigned long flags ; union __anonunion____missing_field_name_150 __annonCompField36 ; struct __anonstruct____missing_field_name_151 __annonCompField42 ; union __anonunion____missing_field_name_157 __annonCompField45 ; union __anonunion____missing_field_name_160 __annonCompField46 ; struct mem_cgroup *mem_cgroup ; }; struct page_frag { struct page *page ; __u32 offset ; __u32 size ; }; struct __anonstruct_shared_161 { struct rb_node rb ; unsigned long rb_subtree_last ; }; struct anon_vma; struct vm_operations_struct; struct mempolicy; struct vm_area_struct { unsigned long vm_start ; unsigned long vm_end ; struct vm_area_struct *vm_next ; struct vm_area_struct *vm_prev ; struct rb_node vm_rb ; unsigned long rb_subtree_gap ; struct mm_struct *vm_mm ; pgprot_t vm_page_prot ; unsigned long vm_flags ; struct __anonstruct_shared_161 shared ; struct list_head anon_vma_chain ; struct anon_vma *anon_vma ; struct vm_operations_struct const *vm_ops ; unsigned long vm_pgoff ; struct file *vm_file ; void *vm_private_data ; struct mempolicy *vm_policy ; }; struct core_thread { struct task_struct *task ; struct core_thread *next ; }; struct core_state { atomic_t nr_threads ; struct core_thread dumper ; struct completion startup ; }; struct task_rss_stat { int events ; int count[3U] ; }; struct mm_rss_stat { atomic_long_t count[3U] ; }; struct kioctx_table; struct linux_binfmt; struct mmu_notifier_mm; struct mm_struct { struct vm_area_struct *mmap ; struct rb_root mm_rb ; u32 vmacache_seqnum ; unsigned long (*get_unmapped_area)(struct file * , unsigned long , unsigned long , unsigned long , unsigned long ) ; unsigned long mmap_base ; unsigned long mmap_legacy_base ; unsigned long task_size ; unsigned long highest_vm_end ; pgd_t *pgd ; atomic_t mm_users ; atomic_t mm_count ; atomic_long_t nr_ptes ; atomic_long_t nr_pmds ; int map_count ; spinlock_t page_table_lock ; struct rw_semaphore mmap_sem ; struct list_head mmlist ; unsigned long hiwater_rss ; unsigned long hiwater_vm ; unsigned long total_vm ; unsigned long locked_vm ; unsigned long pinned_vm ; unsigned long shared_vm ; unsigned long exec_vm ; unsigned long stack_vm ; unsigned long def_flags ; unsigned long start_code ; unsigned long end_code ; unsigned long start_data ; unsigned long end_data ; unsigned long start_brk ; unsigned long brk ; unsigned long start_stack ; unsigned long arg_start ; unsigned long arg_end ; unsigned long env_start ; unsigned long env_end ; unsigned long saved_auxv[46U] ; struct mm_rss_stat rss_stat ; struct linux_binfmt *binfmt ; cpumask_var_t cpu_vm_mask_var ; mm_context_t context ; unsigned long flags ; struct core_state *core_state ; spinlock_t ioctx_lock ; struct kioctx_table *ioctx_table ; struct task_struct *owner ; struct file *exe_file ; struct mmu_notifier_mm *mmu_notifier_mm ; struct cpumask cpumask_allocation ; unsigned long numa_next_scan ; unsigned long numa_scan_offset ; int numa_scan_seq ; bool tlb_flush_pending ; struct uprobes_state uprobes_state ; void *bd_addr ; }; typedef __u64 Elf64_Addr; typedef __u16 Elf64_Half; typedef __u32 Elf64_Word; typedef __u64 Elf64_Xword; struct elf64_sym { Elf64_Word st_name ; unsigned char st_info ; unsigned char st_other ; Elf64_Half st_shndx ; Elf64_Addr st_value ; Elf64_Xword st_size ; }; typedef struct elf64_sym Elf64_Sym; union __anonunion____missing_field_name_166 { unsigned long bitmap[4U] ; struct callback_head callback_head ; }; struct idr_layer { int prefix ; int layer ; struct idr_layer *ary[256U] ; int count ; union __anonunion____missing_field_name_166 __annonCompField47 ; }; struct idr { struct idr_layer *hint ; struct idr_layer *top ; int layers ; int cur ; spinlock_t lock ; int id_free_cnt ; struct idr_layer *id_free ; }; struct ida_bitmap { long nr_busy ; unsigned long bitmap[15U] ; }; struct ida { struct idr idr ; struct ida_bitmap *free_bitmap ; }; struct dentry; struct iattr; struct super_block; struct file_system_type; struct kernfs_open_node; struct kernfs_iattrs; struct kernfs_root; struct kernfs_elem_dir { unsigned long subdirs ; struct rb_root children ; struct kernfs_root *root ; }; struct kernfs_node; struct kernfs_elem_symlink { struct kernfs_node *target_kn ; }; struct kernfs_ops; struct kernfs_elem_attr { struct kernfs_ops const *ops ; struct kernfs_open_node *open ; loff_t size ; struct kernfs_node *notify_next ; }; union __anonunion____missing_field_name_171 { struct kernfs_elem_dir dir ; struct kernfs_elem_symlink symlink ; struct kernfs_elem_attr attr ; }; struct kernfs_node { atomic_t count ; atomic_t active ; struct lockdep_map dep_map ; struct kernfs_node *parent ; char const *name ; struct rb_node rb ; void const *ns ; unsigned int hash ; union __anonunion____missing_field_name_171 __annonCompField48 ; void *priv ; unsigned short flags ; umode_t mode ; unsigned int ino ; struct kernfs_iattrs *iattr ; }; struct kernfs_syscall_ops { int (*remount_fs)(struct kernfs_root * , int * , char * ) ; int (*show_options)(struct seq_file * , struct kernfs_root * ) ; int (*mkdir)(struct kernfs_node * , char const * , umode_t ) ; int (*rmdir)(struct kernfs_node * ) ; int (*rename)(struct kernfs_node * , struct kernfs_node * , char const * ) ; }; struct kernfs_root { struct kernfs_node *kn ; unsigned int flags ; struct ida ino_ida ; struct kernfs_syscall_ops *syscall_ops ; struct list_head supers ; wait_queue_head_t deactivate_waitq ; }; struct kernfs_open_file { struct kernfs_node *kn ; struct file *file ; void *priv ; struct mutex mutex ; int event ; struct list_head list ; char *prealloc_buf ; size_t atomic_write_len ; bool mmapped ; struct vm_operations_struct const *vm_ops ; }; struct kernfs_ops { int (*seq_show)(struct seq_file * , void * ) ; void *(*seq_start)(struct seq_file * , loff_t * ) ; void *(*seq_next)(struct seq_file * , void * , loff_t * ) ; void (*seq_stop)(struct seq_file * , void * ) ; ssize_t (*read)(struct kernfs_open_file * , char * , size_t , loff_t ) ; size_t atomic_write_len ; bool prealloc ; ssize_t (*write)(struct kernfs_open_file * , char * , size_t , loff_t ) ; int (*mmap)(struct kernfs_open_file * , struct vm_area_struct * ) ; struct lock_class_key lockdep_key ; }; struct sock; struct kobject; enum kobj_ns_type { KOBJ_NS_TYPE_NONE = 0, KOBJ_NS_TYPE_NET = 1, KOBJ_NS_TYPES = 2 } ; struct kobj_ns_type_operations { enum kobj_ns_type type ; bool (*current_may_mount)(void) ; void *(*grab_current_ns)(void) ; void const *(*netlink_ns)(struct sock * ) ; void const *(*initial_ns)(void) ; void (*drop_ns)(void * ) ; }; struct bin_attribute; struct attribute { char const *name ; umode_t mode ; bool ignore_lockdep ; struct lock_class_key *key ; struct lock_class_key skey ; }; struct attribute_group { char const *name ; umode_t (*is_visible)(struct kobject * , struct attribute * , int ) ; struct attribute **attrs ; struct bin_attribute **bin_attrs ; }; struct bin_attribute { struct attribute attr ; size_t size ; void *private ; ssize_t (*read)(struct file * , struct kobject * , struct bin_attribute * , char * , loff_t , size_t ) ; ssize_t (*write)(struct file * , struct kobject * , struct bin_attribute * , char * , loff_t , size_t ) ; int (*mmap)(struct file * , struct kobject * , struct bin_attribute * , struct vm_area_struct * ) ; }; struct sysfs_ops { ssize_t (*show)(struct kobject * , struct attribute * , char * ) ; ssize_t (*store)(struct kobject * , struct attribute * , char const * , size_t ) ; }; struct kref { atomic_t refcount ; }; struct kset; struct kobj_type; struct kobject { char const *name ; struct list_head entry ; struct kobject *parent ; struct kset *kset ; struct kobj_type *ktype ; struct kernfs_node *sd ; struct kref kref ; struct delayed_work release ; unsigned char state_initialized : 1 ; unsigned char state_in_sysfs : 1 ; unsigned char state_add_uevent_sent : 1 ; unsigned char state_remove_uevent_sent : 1 ; unsigned char uevent_suppress : 1 ; }; struct kobj_type { void (*release)(struct kobject * ) ; struct sysfs_ops const *sysfs_ops ; struct attribute **default_attrs ; struct kobj_ns_type_operations const *(*child_ns_type)(struct kobject * ) ; void const *(*namespace)(struct kobject * ) ; }; struct kobj_uevent_env { char *argv[3U] ; char *envp[32U] ; int envp_idx ; char buf[2048U] ; int buflen ; }; struct kset_uevent_ops { int (* const filter)(struct kset * , struct kobject * ) ; char const *(* const name)(struct kset * , struct kobject * ) ; int (* const uevent)(struct kset * , struct kobject * , struct kobj_uevent_env * ) ; }; struct kset { struct list_head list ; spinlock_t list_lock ; struct kobject kobj ; struct kset_uevent_ops const *uevent_ops ; }; struct kernel_param; struct kernel_param_ops { unsigned int flags ; int (*set)(char const * , struct kernel_param const * ) ; int (*get)(char * , struct kernel_param const * ) ; void (*free)(void * ) ; }; struct kparam_string; struct kparam_array; union __anonunion____missing_field_name_172 { void *arg ; struct kparam_string const *str ; struct kparam_array const *arr ; }; struct kernel_param { char const *name ; struct module *mod ; struct kernel_param_ops const *ops ; u16 const perm ; s8 level ; u8 flags ; union __anonunion____missing_field_name_172 __annonCompField49 ; }; struct kparam_string { unsigned int maxlen ; char *string ; }; struct kparam_array { unsigned int max ; unsigned int elemsize ; unsigned int *num ; struct kernel_param_ops const *ops ; void *elem ; }; struct latch_tree_node { struct rb_node node[2U] ; }; struct mod_arch_specific { }; struct module_param_attrs; struct module_kobject { struct kobject kobj ; struct module *mod ; struct kobject *drivers_dir ; struct module_param_attrs *mp ; struct completion *kobj_completion ; }; struct module_attribute { struct attribute attr ; ssize_t (*show)(struct module_attribute * , struct module_kobject * , char * ) ; ssize_t (*store)(struct module_attribute * , struct module_kobject * , char const * , size_t ) ; void (*setup)(struct module * , char const * ) ; int (*test)(struct module * ) ; void (*free)(struct module * ) ; }; struct exception_table_entry; enum module_state { MODULE_STATE_LIVE = 0, MODULE_STATE_COMING = 1, MODULE_STATE_GOING = 2, MODULE_STATE_UNFORMED = 3 } ; struct mod_tree_node { struct module *mod ; struct latch_tree_node node ; }; struct module_sect_attrs; struct module_notes_attrs; struct tracepoint; struct trace_event_call; struct trace_enum_map; struct module { enum module_state state ; struct list_head list ; char name[56U] ; struct module_kobject mkobj ; struct module_attribute *modinfo_attrs ; char const *version ; char const *srcversion ; struct kobject *holders_dir ; struct kernel_symbol const *syms ; unsigned long const *crcs ; unsigned int num_syms ; struct mutex param_lock ; struct kernel_param *kp ; unsigned int num_kp ; unsigned int num_gpl_syms ; struct kernel_symbol const *gpl_syms ; unsigned long const *gpl_crcs ; struct kernel_symbol const *unused_syms ; unsigned long const *unused_crcs ; unsigned int num_unused_syms ; unsigned int num_unused_gpl_syms ; struct kernel_symbol const *unused_gpl_syms ; unsigned long const *unused_gpl_crcs ; bool sig_ok ; bool async_probe_requested ; struct kernel_symbol const *gpl_future_syms ; unsigned long const *gpl_future_crcs ; unsigned int num_gpl_future_syms ; unsigned int num_exentries ; struct exception_table_entry *extable ; int (*init)(void) ; void *module_init ; void *module_core ; unsigned int init_size ; unsigned int core_size ; unsigned int init_text_size ; unsigned int core_text_size ; struct mod_tree_node mtn_core ; struct mod_tree_node mtn_init ; unsigned int init_ro_size ; unsigned int core_ro_size ; struct mod_arch_specific arch ; unsigned int taints ; unsigned int num_bugs ; struct list_head bug_list ; struct bug_entry *bug_table ; Elf64_Sym *symtab ; Elf64_Sym *core_symtab ; unsigned int num_symtab ; unsigned int core_num_syms ; char *strtab ; char *core_strtab ; struct module_sect_attrs *sect_attrs ; struct module_notes_attrs *notes_attrs ; char *args ; void *percpu ; unsigned int percpu_size ; unsigned int num_tracepoints ; struct tracepoint * const *tracepoints_ptrs ; unsigned int num_trace_bprintk_fmt ; char const **trace_bprintk_fmt_start ; struct trace_event_call **trace_events ; unsigned int num_trace_events ; struct trace_enum_map **trace_enums ; unsigned int num_trace_enums ; unsigned int num_ftrace_callsites ; unsigned long *ftrace_callsites ; bool klp_alive ; struct list_head source_list ; struct list_head target_list ; void (*exit)(void) ; atomic_t refcnt ; ctor_fn_t (**ctors)(void) ; unsigned int num_ctors ; }; struct kernel_cap_struct { __u32 cap[2U] ; }; typedef struct kernel_cap_struct kernel_cap_t; struct plist_node { int prio ; struct list_head prio_list ; struct list_head node_list ; }; typedef unsigned long cputime_t; struct sem_undo_list; struct sysv_sem { struct sem_undo_list *undo_list ; }; struct user_struct; struct sysv_shm { struct list_head shm_clist ; }; struct __anonstruct_sigset_t_180 { unsigned long sig[1U] ; }; typedef struct __anonstruct_sigset_t_180 sigset_t; struct siginfo; typedef void __signalfn_t(int ); typedef __signalfn_t *__sighandler_t; typedef void __restorefn_t(void); typedef __restorefn_t *__sigrestore_t; union sigval { int sival_int ; void *sival_ptr ; }; typedef union sigval sigval_t; struct __anonstruct__kill_182 { __kernel_pid_t _pid ; __kernel_uid32_t _uid ; }; struct __anonstruct__timer_183 { __kernel_timer_t _tid ; int _overrun ; char _pad[0U] ; sigval_t _sigval ; int _sys_private ; }; struct __anonstruct__rt_184 { __kernel_pid_t _pid ; __kernel_uid32_t _uid ; sigval_t _sigval ; }; struct __anonstruct__sigchld_185 { __kernel_pid_t _pid ; __kernel_uid32_t _uid ; int _status ; __kernel_clock_t _utime ; __kernel_clock_t _stime ; }; struct __anonstruct__addr_bnd_187 { void *_lower ; void *_upper ; }; struct __anonstruct__sigfault_186 { void *_addr ; short _addr_lsb ; struct __anonstruct__addr_bnd_187 _addr_bnd ; }; struct __anonstruct__sigpoll_188 { long _band ; int _fd ; }; struct __anonstruct__sigsys_189 { void *_call_addr ; int _syscall ; unsigned int _arch ; }; union __anonunion__sifields_181 { int _pad[28U] ; struct __anonstruct__kill_182 _kill ; struct __anonstruct__timer_183 _timer ; struct __anonstruct__rt_184 _rt ; struct __anonstruct__sigchld_185 _sigchld ; struct __anonstruct__sigfault_186 _sigfault ; struct __anonstruct__sigpoll_188 _sigpoll ; struct __anonstruct__sigsys_189 _sigsys ; }; struct siginfo { int si_signo ; int si_errno ; int si_code ; union __anonunion__sifields_181 _sifields ; }; typedef struct siginfo siginfo_t; struct sigpending { struct list_head list ; sigset_t signal ; }; struct sigaction { __sighandler_t sa_handler ; unsigned long sa_flags ; __sigrestore_t sa_restorer ; sigset_t sa_mask ; }; struct k_sigaction { struct sigaction sa ; }; enum pid_type { PIDTYPE_PID = 0, PIDTYPE_PGID = 1, PIDTYPE_SID = 2, PIDTYPE_MAX = 3 } ; struct pid_namespace; struct upid { int nr ; struct pid_namespace *ns ; struct hlist_node pid_chain ; }; struct pid { atomic_t count ; unsigned int level ; struct hlist_head tasks[3U] ; struct callback_head rcu ; struct upid numbers[1U] ; }; struct pid_link { struct hlist_node node ; struct pid *pid ; }; struct percpu_counter { raw_spinlock_t lock ; s64 count ; struct list_head list ; s32 *counters ; }; struct seccomp_filter; struct seccomp { int mode ; struct seccomp_filter *filter ; }; struct rt_mutex { raw_spinlock_t wait_lock ; struct rb_root waiters ; struct rb_node *waiters_leftmost ; struct task_struct *owner ; int save_state ; char const *name ; char const *file ; int line ; void *magic ; }; struct rt_mutex_waiter; struct rlimit { __kernel_ulong_t rlim_cur ; __kernel_ulong_t rlim_max ; }; struct timerqueue_node { struct rb_node node ; ktime_t expires ; }; struct timerqueue_head { struct rb_root head ; struct timerqueue_node *next ; }; struct hrtimer_clock_base; struct hrtimer_cpu_base; enum hrtimer_restart { HRTIMER_NORESTART = 0, HRTIMER_RESTART = 1 } ; struct hrtimer { struct timerqueue_node node ; ktime_t _softexpires ; enum hrtimer_restart (*function)(struct hrtimer * ) ; struct hrtimer_clock_base *base ; unsigned long state ; int start_pid ; void *start_site ; char start_comm[16U] ; }; struct hrtimer_clock_base { struct hrtimer_cpu_base *cpu_base ; int index ; clockid_t clockid ; struct timerqueue_head active ; ktime_t (*get_time)(void) ; ktime_t offset ; }; struct hrtimer_cpu_base { raw_spinlock_t lock ; seqcount_t seq ; struct hrtimer *running ; unsigned int cpu ; unsigned int active_bases ; unsigned int clock_was_set_seq ; bool migration_enabled ; bool nohz_active ; unsigned char in_hrtirq : 1 ; unsigned char hres_active : 1 ; unsigned char hang_detected : 1 ; ktime_t expires_next ; struct hrtimer *next_timer ; unsigned int nr_events ; unsigned int nr_retries ; unsigned int nr_hangs ; unsigned int max_hang_time ; struct hrtimer_clock_base clock_base[4U] ; }; struct task_io_accounting { u64 rchar ; u64 wchar ; u64 syscr ; u64 syscw ; u64 read_bytes ; u64 write_bytes ; u64 cancelled_write_bytes ; }; struct latency_record { unsigned long backtrace[12U] ; unsigned int count ; unsigned long time ; unsigned long max ; }; struct assoc_array_ptr; struct assoc_array { struct assoc_array_ptr *root ; unsigned long nr_leaves_on_tree ; }; typedef int32_t key_serial_t; typedef uint32_t key_perm_t; struct key; struct signal_struct; struct key_type; struct keyring_index_key { struct key_type *type ; char const *description ; size_t desc_len ; }; union __anonunion____missing_field_name_196 { struct list_head graveyard_link ; struct rb_node serial_node ; }; struct key_user; union __anonunion____missing_field_name_197 { time_t expiry ; time_t revoked_at ; }; struct __anonstruct____missing_field_name_199 { struct key_type *type ; char *description ; }; union __anonunion____missing_field_name_198 { struct keyring_index_key index_key ; struct __anonstruct____missing_field_name_199 __annonCompField52 ; }; union __anonunion_type_data_200 { struct list_head link ; unsigned long x[2U] ; void *p[2U] ; int reject_error ; }; union __anonunion_payload_202 { unsigned long value ; void *rcudata ; void *data ; void *data2[2U] ; }; union __anonunion____missing_field_name_201 { union __anonunion_payload_202 payload ; struct assoc_array keys ; }; struct key { atomic_t usage ; key_serial_t serial ; union __anonunion____missing_field_name_196 __annonCompField50 ; struct rw_semaphore sem ; struct key_user *user ; void *security ; union __anonunion____missing_field_name_197 __annonCompField51 ; time_t last_used_at ; kuid_t uid ; kgid_t gid ; key_perm_t perm ; unsigned short quotalen ; unsigned short datalen ; unsigned long flags ; union __anonunion____missing_field_name_198 __annonCompField53 ; union __anonunion_type_data_200 type_data ; union __anonunion____missing_field_name_201 __annonCompField54 ; }; struct audit_context; struct group_info { atomic_t usage ; int ngroups ; int nblocks ; kgid_t small_block[32U] ; kgid_t *blocks[0U] ; }; struct cred { atomic_t usage ; atomic_t subscribers ; void *put_addr ; unsigned int magic ; kuid_t uid ; kgid_t gid ; kuid_t suid ; kgid_t sgid ; kuid_t euid ; kgid_t egid ; kuid_t fsuid ; kgid_t fsgid ; unsigned int securebits ; kernel_cap_t cap_inheritable ; kernel_cap_t cap_permitted ; kernel_cap_t cap_effective ; kernel_cap_t cap_bset ; unsigned char jit_keyring ; struct key *session_keyring ; struct key *process_keyring ; struct key *thread_keyring ; struct key *request_key_auth ; void *security ; struct user_struct *user ; struct user_namespace *user_ns ; struct group_info *group_info ; struct callback_head rcu ; }; struct percpu_ref; typedef void percpu_ref_func_t(struct percpu_ref * ); struct percpu_ref { atomic_long_t count ; unsigned long percpu_count_ptr ; percpu_ref_func_t *release ; percpu_ref_func_t *confirm_switch ; bool force_atomic ; struct callback_head rcu ; }; struct cgroup; struct cgroup_root; struct cgroup_subsys; struct cgroup_taskset; struct cgroup_subsys_state { struct cgroup *cgroup ; struct cgroup_subsys *ss ; struct percpu_ref refcnt ; struct cgroup_subsys_state *parent ; struct list_head sibling ; struct list_head children ; int id ; unsigned int flags ; u64 serial_nr ; struct callback_head callback_head ; struct work_struct destroy_work ; }; struct css_set { atomic_t refcount ; struct hlist_node hlist ; struct list_head tasks ; struct list_head mg_tasks ; struct list_head cgrp_links ; struct cgroup *dfl_cgrp ; struct cgroup_subsys_state *subsys[12U] ; struct list_head mg_preload_node ; struct list_head mg_node ; struct cgroup *mg_src_cgrp ; struct css_set *mg_dst_cset ; struct list_head e_cset_node[12U] ; struct callback_head callback_head ; }; struct cgroup { struct cgroup_subsys_state self ; unsigned long flags ; int id ; int populated_cnt ; struct kernfs_node *kn ; struct kernfs_node *procs_kn ; struct kernfs_node *populated_kn ; unsigned int subtree_control ; unsigned int child_subsys_mask ; struct cgroup_subsys_state *subsys[12U] ; struct cgroup_root *root ; struct list_head cset_links ; struct list_head e_csets[12U] ; struct list_head pidlists ; struct mutex pidlist_mutex ; wait_queue_head_t offline_waitq ; struct work_struct release_agent_work ; }; struct cgroup_root { struct kernfs_root *kf_root ; unsigned int subsys_mask ; int hierarchy_id ; struct cgroup cgrp ; atomic_t nr_cgrps ; struct list_head root_list ; unsigned int flags ; struct idr cgroup_idr ; char release_agent_path[4096U] ; char name[64U] ; }; struct cftype { char name[64U] ; int private ; umode_t mode ; size_t max_write_len ; unsigned int flags ; struct cgroup_subsys *ss ; struct list_head node ; struct kernfs_ops *kf_ops ; u64 (*read_u64)(struct cgroup_subsys_state * , struct cftype * ) ; s64 (*read_s64)(struct cgroup_subsys_state * , struct cftype * ) ; int (*seq_show)(struct seq_file * , void * ) ; void *(*seq_start)(struct seq_file * , loff_t * ) ; void *(*seq_next)(struct seq_file * , void * , loff_t * ) ; void (*seq_stop)(struct seq_file * , void * ) ; int (*write_u64)(struct cgroup_subsys_state * , struct cftype * , u64 ) ; int (*write_s64)(struct cgroup_subsys_state * , struct cftype * , s64 ) ; ssize_t (*write)(struct kernfs_open_file * , char * , size_t , loff_t ) ; struct lock_class_key lockdep_key ; }; struct cgroup_subsys { struct cgroup_subsys_state *(*css_alloc)(struct cgroup_subsys_state * ) ; int (*css_online)(struct cgroup_subsys_state * ) ; void (*css_offline)(struct cgroup_subsys_state * ) ; void (*css_released)(struct cgroup_subsys_state * ) ; void (*css_free)(struct cgroup_subsys_state * ) ; void (*css_reset)(struct cgroup_subsys_state * ) ; void (*css_e_css_changed)(struct cgroup_subsys_state * ) ; int (*can_attach)(struct cgroup_subsys_state * , struct cgroup_taskset * ) ; void (*cancel_attach)(struct cgroup_subsys_state * , struct cgroup_taskset * ) ; void (*attach)(struct cgroup_subsys_state * , struct cgroup_taskset * ) ; void (*fork)(struct task_struct * ) ; void (*exit)(struct cgroup_subsys_state * , struct cgroup_subsys_state * , struct task_struct * ) ; void (*bind)(struct cgroup_subsys_state * ) ; int disabled ; int early_init ; bool broken_hierarchy ; bool warned_broken_hierarchy ; int id ; char const *name ; struct cgroup_root *root ; struct idr css_idr ; struct list_head cfts ; struct cftype *dfl_cftypes ; struct cftype *legacy_cftypes ; unsigned int depends_on ; }; struct futex_pi_state; struct robust_list_head; struct bio_list; struct fs_struct; struct perf_event_context; struct blk_plug; struct nameidata; struct cfs_rq; struct task_group; struct sighand_struct { atomic_t count ; struct k_sigaction action[64U] ; spinlock_t siglock ; wait_queue_head_t signalfd_wqh ; }; struct pacct_struct { int ac_flag ; long ac_exitcode ; unsigned long ac_mem ; cputime_t ac_utime ; cputime_t ac_stime ; unsigned long ac_minflt ; unsigned long ac_majflt ; }; struct cpu_itimer { cputime_t expires ; cputime_t incr ; u32 error ; u32 incr_error ; }; struct cputime { cputime_t utime ; cputime_t stime ; }; struct task_cputime { cputime_t utime ; cputime_t stime ; unsigned long long sum_exec_runtime ; }; struct task_cputime_atomic { atomic64_t utime ; atomic64_t stime ; atomic64_t sum_exec_runtime ; }; struct thread_group_cputimer { struct task_cputime_atomic cputime_atomic ; int running ; }; struct autogroup; struct tty_struct; struct taskstats; struct tty_audit_buf; struct signal_struct { atomic_t sigcnt ; atomic_t live ; int nr_threads ; struct list_head thread_head ; wait_queue_head_t wait_chldexit ; struct task_struct *curr_target ; struct sigpending shared_pending ; int group_exit_code ; int notify_count ; struct task_struct *group_exit_task ; int group_stop_count ; unsigned int flags ; unsigned char is_child_subreaper : 1 ; unsigned char has_child_subreaper : 1 ; int posix_timer_id ; struct list_head posix_timers ; struct hrtimer real_timer ; struct pid *leader_pid ; ktime_t it_real_incr ; struct cpu_itimer it[2U] ; struct thread_group_cputimer cputimer ; struct task_cputime cputime_expires ; struct list_head cpu_timers[3U] ; struct pid *tty_old_pgrp ; int leader ; struct tty_struct *tty ; struct autogroup *autogroup ; seqlock_t stats_lock ; cputime_t utime ; cputime_t stime ; cputime_t cutime ; cputime_t cstime ; cputime_t gtime ; cputime_t cgtime ; struct cputime prev_cputime ; unsigned long nvcsw ; unsigned long nivcsw ; unsigned long cnvcsw ; unsigned long cnivcsw ; unsigned long min_flt ; unsigned long maj_flt ; unsigned long cmin_flt ; unsigned long cmaj_flt ; unsigned long inblock ; unsigned long oublock ; unsigned long cinblock ; unsigned long coublock ; unsigned long maxrss ; unsigned long cmaxrss ; struct task_io_accounting ioac ; unsigned long long sum_sched_runtime ; struct rlimit rlim[16U] ; struct pacct_struct pacct ; struct taskstats *stats ; unsigned int audit_tty ; unsigned int audit_tty_log_passwd ; struct tty_audit_buf *tty_audit_buf ; oom_flags_t oom_flags ; short oom_score_adj ; short oom_score_adj_min ; struct mutex cred_guard_mutex ; }; struct user_struct { atomic_t __count ; atomic_t processes ; atomic_t sigpending ; atomic_t inotify_watches ; atomic_t inotify_devs ; atomic_t fanotify_listeners ; atomic_long_t epoll_watches ; unsigned long mq_bytes ; unsigned long locked_shm ; struct key *uid_keyring ; struct key *session_keyring ; struct hlist_node uidhash_node ; kuid_t uid ; atomic_long_t locked_vm ; }; struct backing_dev_info; struct reclaim_state; struct sched_info { unsigned long pcount ; unsigned long long run_delay ; unsigned long long last_arrival ; unsigned long long last_queued ; }; struct task_delay_info { spinlock_t lock ; unsigned int flags ; u64 blkio_start ; u64 blkio_delay ; u64 swapin_delay ; u32 blkio_count ; u32 swapin_count ; u64 freepages_start ; u64 freepages_delay ; u32 freepages_count ; }; struct wake_q_node { struct wake_q_node *next ; }; struct io_context; struct pipe_inode_info; struct load_weight { unsigned long weight ; u32 inv_weight ; }; struct sched_avg { u64 last_runnable_update ; s64 decay_count ; unsigned long load_avg_contrib ; unsigned long utilization_avg_contrib ; u32 runnable_avg_sum ; u32 avg_period ; u32 running_avg_sum ; }; struct sched_statistics { u64 wait_start ; u64 wait_max ; u64 wait_count ; u64 wait_sum ; u64 iowait_count ; u64 iowait_sum ; u64 sleep_start ; u64 sleep_max ; s64 sum_sleep_runtime ; u64 block_start ; u64 block_max ; u64 exec_max ; u64 slice_max ; u64 nr_migrations_cold ; u64 nr_failed_migrations_affine ; u64 nr_failed_migrations_running ; u64 nr_failed_migrations_hot ; u64 nr_forced_migrations ; u64 nr_wakeups ; u64 nr_wakeups_sync ; u64 nr_wakeups_migrate ; u64 nr_wakeups_local ; u64 nr_wakeups_remote ; u64 nr_wakeups_affine ; u64 nr_wakeups_affine_attempts ; u64 nr_wakeups_passive ; u64 nr_wakeups_idle ; }; struct sched_entity { struct load_weight load ; struct rb_node run_node ; struct list_head group_node ; unsigned int on_rq ; u64 exec_start ; u64 sum_exec_runtime ; u64 vruntime ; u64 prev_sum_exec_runtime ; u64 nr_migrations ; struct sched_statistics statistics ; int depth ; struct sched_entity *parent ; struct cfs_rq *cfs_rq ; struct cfs_rq *my_q ; struct sched_avg avg ; }; struct rt_rq; struct sched_rt_entity { struct list_head run_list ; unsigned long timeout ; unsigned long watchdog_stamp ; unsigned int time_slice ; struct sched_rt_entity *back ; struct sched_rt_entity *parent ; struct rt_rq *rt_rq ; struct rt_rq *my_q ; }; struct sched_dl_entity { struct rb_node rb_node ; u64 dl_runtime ; u64 dl_deadline ; u64 dl_period ; u64 dl_bw ; s64 runtime ; u64 deadline ; unsigned int flags ; int dl_throttled ; int dl_new ; int dl_boosted ; int dl_yielded ; struct hrtimer dl_timer ; }; struct memcg_oom_info { struct mem_cgroup *memcg ; gfp_t gfp_mask ; int order ; unsigned char may_oom : 1 ; }; struct sched_class; struct files_struct; struct compat_robust_list_head; struct numa_group; struct ftrace_ret_stack; struct task_struct { long volatile state ; void *stack ; atomic_t usage ; unsigned int flags ; unsigned int ptrace ; struct llist_node wake_entry ; int on_cpu ; struct task_struct *last_wakee ; unsigned long wakee_flips ; unsigned long wakee_flip_decay_ts ; int wake_cpu ; int on_rq ; int prio ; int static_prio ; int normal_prio ; unsigned int rt_priority ; struct sched_class const *sched_class ; struct sched_entity se ; struct sched_rt_entity rt ; struct task_group *sched_task_group ; struct sched_dl_entity dl ; struct hlist_head preempt_notifiers ; unsigned int btrace_seq ; unsigned int policy ; int nr_cpus_allowed ; cpumask_t cpus_allowed ; unsigned long rcu_tasks_nvcsw ; bool rcu_tasks_holdout ; struct list_head rcu_tasks_holdout_list ; int rcu_tasks_idle_cpu ; struct sched_info sched_info ; struct list_head tasks ; struct plist_node pushable_tasks ; struct rb_node pushable_dl_tasks ; struct mm_struct *mm ; struct mm_struct *active_mm ; u32 vmacache_seqnum ; struct vm_area_struct *vmacache[4U] ; struct task_rss_stat rss_stat ; int exit_state ; int exit_code ; int exit_signal ; int pdeath_signal ; unsigned long jobctl ; unsigned int personality ; unsigned char in_execve : 1 ; unsigned char in_iowait : 1 ; unsigned char sched_reset_on_fork : 1 ; unsigned char sched_contributes_to_load : 1 ; unsigned char sched_migrated : 1 ; unsigned char memcg_kmem_skip_account : 1 ; unsigned char brk_randomized : 1 ; unsigned long atomic_flags ; struct restart_block restart_block ; pid_t pid ; pid_t tgid ; struct task_struct *real_parent ; struct task_struct *parent ; struct list_head children ; struct list_head sibling ; struct task_struct *group_leader ; struct list_head ptraced ; struct list_head ptrace_entry ; struct pid_link pids[3U] ; struct list_head thread_group ; struct list_head thread_node ; struct completion *vfork_done ; int *set_child_tid ; int *clear_child_tid ; cputime_t utime ; cputime_t stime ; cputime_t utimescaled ; cputime_t stimescaled ; cputime_t gtime ; struct cputime prev_cputime ; unsigned long nvcsw ; unsigned long nivcsw ; u64 start_time ; u64 real_start_time ; unsigned long min_flt ; unsigned long maj_flt ; struct task_cputime cputime_expires ; struct list_head cpu_timers[3U] ; struct cred const *real_cred ; struct cred const *cred ; char comm[16U] ; struct nameidata *nameidata ; struct sysv_sem sysvsem ; struct sysv_shm sysvshm ; unsigned long last_switch_count ; struct thread_struct thread ; struct fs_struct *fs ; struct files_struct *files ; struct nsproxy *nsproxy ; struct signal_struct *signal ; struct sighand_struct *sighand ; sigset_t blocked ; sigset_t real_blocked ; sigset_t saved_sigmask ; struct sigpending pending ; unsigned long sas_ss_sp ; size_t sas_ss_size ; int (*notifier)(void * ) ; void *notifier_data ; sigset_t *notifier_mask ; struct callback_head *task_works ; struct audit_context *audit_context ; kuid_t loginuid ; unsigned int sessionid ; struct seccomp seccomp ; u32 parent_exec_id ; u32 self_exec_id ; spinlock_t alloc_lock ; raw_spinlock_t pi_lock ; struct wake_q_node wake_q ; struct rb_root pi_waiters ; struct rb_node *pi_waiters_leftmost ; struct rt_mutex_waiter *pi_blocked_on ; struct mutex_waiter *blocked_on ; unsigned int irq_events ; unsigned long hardirq_enable_ip ; unsigned long hardirq_disable_ip ; unsigned int hardirq_enable_event ; unsigned int hardirq_disable_event ; int hardirqs_enabled ; int hardirq_context ; unsigned long softirq_disable_ip ; unsigned long softirq_enable_ip ; unsigned int softirq_disable_event ; unsigned int softirq_enable_event ; int softirqs_enabled ; int softirq_context ; u64 curr_chain_key ; int lockdep_depth ; unsigned int lockdep_recursion ; struct held_lock held_locks[48U] ; gfp_t lockdep_reclaim_gfp ; void *journal_info ; struct bio_list *bio_list ; struct blk_plug *plug ; struct reclaim_state *reclaim_state ; struct backing_dev_info *backing_dev_info ; struct io_context *io_context ; unsigned long ptrace_message ; siginfo_t *last_siginfo ; struct task_io_accounting ioac ; u64 acct_rss_mem1 ; u64 acct_vm_mem1 ; cputime_t acct_timexpd ; nodemask_t mems_allowed ; seqcount_t mems_allowed_seq ; int cpuset_mem_spread_rotor ; int cpuset_slab_spread_rotor ; struct css_set *cgroups ; struct list_head cg_list ; struct robust_list_head *robust_list ; struct compat_robust_list_head *compat_robust_list ; struct list_head pi_state_list ; struct futex_pi_state *pi_state_cache ; struct perf_event_context *perf_event_ctxp[2U] ; struct mutex perf_event_mutex ; struct list_head perf_event_list ; struct mempolicy *mempolicy ; short il_next ; short pref_node_fork ; int numa_scan_seq ; unsigned int numa_scan_period ; unsigned int numa_scan_period_max ; int numa_preferred_nid ; unsigned long numa_migrate_retry ; u64 node_stamp ; u64 last_task_numa_placement ; u64 last_sum_exec_runtime ; struct callback_head numa_work ; struct list_head numa_entry ; struct numa_group *numa_group ; unsigned long *numa_faults ; unsigned long total_numa_faults ; unsigned long numa_faults_locality[3U] ; unsigned long numa_pages_migrated ; struct callback_head rcu ; struct pipe_inode_info *splice_pipe ; struct page_frag task_frag ; struct task_delay_info *delays ; int make_it_fail ; int nr_dirtied ; int nr_dirtied_pause ; unsigned long dirty_paused_when ; int latency_record_count ; struct latency_record latency_record[32U] ; unsigned long timer_slack_ns ; unsigned long default_timer_slack_ns ; unsigned int kasan_depth ; int curr_ret_stack ; struct ftrace_ret_stack *ret_stack ; unsigned long long ftrace_timestamp ; atomic_t trace_overrun ; atomic_t tracing_graph_pause ; unsigned long trace ; unsigned long trace_recursion ; struct memcg_oom_info memcg_oom ; struct uprobe_task *utask ; unsigned int sequential_io ; unsigned int sequential_io_avg ; unsigned long task_state_change ; int pagefault_disabled ; }; enum irqreturn { IRQ_NONE = 0, IRQ_HANDLED = 1, IRQ_WAKE_THREAD = 2 } ; typedef enum irqreturn irqreturn_t; struct fb_var_screeninfo; struct drm_connector; struct fb_info; struct drm_encoder; struct gma_clock_t; struct drm_device; struct drm_crtc; struct drm_file; struct drm_framebuffer; struct drm_display_mode; struct i2c_adapter; struct shrink_control { gfp_t gfp_mask ; unsigned long nr_to_scan ; int nid ; struct mem_cgroup *memcg ; }; struct shrinker { unsigned long (*count_objects)(struct shrinker * , struct shrink_control * ) ; unsigned long (*scan_objects)(struct shrinker * , struct shrink_control * ) ; int seeks ; long batch ; unsigned long flags ; struct list_head list ; atomic_long_t *nr_deferred ; }; struct file_ra_state; struct writeback_control; struct bdi_writeback; struct vm_fault { unsigned int flags ; unsigned long pgoff ; void *virtual_address ; struct page *cow_page ; struct page *page ; unsigned long max_pgoff ; pte_t *pte ; }; struct vm_operations_struct { void (*open)(struct vm_area_struct * ) ; void (*close)(struct vm_area_struct * ) ; int (*fault)(struct vm_area_struct * , struct vm_fault * ) ; void (*map_pages)(struct vm_area_struct * , struct vm_fault * ) ; int (*page_mkwrite)(struct vm_area_struct * , struct vm_fault * ) ; int (*pfn_mkwrite)(struct vm_area_struct * , struct vm_fault * ) ; int (*access)(struct vm_area_struct * , unsigned long , void * , int , int ) ; char const *(*name)(struct vm_area_struct * ) ; int (*set_policy)(struct vm_area_struct * , struct mempolicy * ) ; struct mempolicy *(*get_policy)(struct vm_area_struct * , unsigned long ) ; struct page *(*find_special_page)(struct vm_area_struct * , unsigned long ) ; }; struct hlist_bl_node; struct hlist_bl_head { struct hlist_bl_node *first ; }; struct hlist_bl_node { struct hlist_bl_node *next ; struct hlist_bl_node **pprev ; }; struct __anonstruct____missing_field_name_220 { spinlock_t lock ; int count ; }; union __anonunion____missing_field_name_219 { struct __anonstruct____missing_field_name_220 __annonCompField58 ; }; struct lockref { union __anonunion____missing_field_name_219 __annonCompField59 ; }; struct path; struct vfsmount; struct __anonstruct____missing_field_name_222 { u32 hash ; u32 len ; }; union __anonunion____missing_field_name_221 { struct __anonstruct____missing_field_name_222 __annonCompField60 ; u64 hash_len ; }; struct qstr { union __anonunion____missing_field_name_221 __annonCompField61 ; unsigned char const *name ; }; struct dentry_operations; union __anonunion_d_u_223 { struct hlist_node d_alias ; struct callback_head d_rcu ; }; struct dentry { unsigned int d_flags ; seqcount_t d_seq ; struct hlist_bl_node d_hash ; struct dentry *d_parent ; struct qstr d_name ; struct inode *d_inode ; unsigned char d_iname[32U] ; struct lockref d_lockref ; struct dentry_operations const *d_op ; struct super_block *d_sb ; unsigned long d_time ; void *d_fsdata ; struct list_head d_lru ; struct list_head d_child ; struct list_head d_subdirs ; union __anonunion_d_u_223 d_u ; }; struct dentry_operations { int (*d_revalidate)(struct dentry * , unsigned int ) ; int (*d_weak_revalidate)(struct dentry * , unsigned int ) ; int (*d_hash)(struct dentry const * , struct qstr * ) ; int (*d_compare)(struct dentry const * , struct dentry const * , unsigned int , char const * , struct qstr const * ) ; int (*d_delete)(struct dentry const * ) ; void (*d_release)(struct dentry * ) ; void (*d_prune)(struct dentry * ) ; void (*d_iput)(struct dentry * , struct inode * ) ; char *(*d_dname)(struct dentry * , char * , int ) ; struct vfsmount *(*d_automount)(struct path * ) ; int (*d_manage)(struct dentry * , bool ) ; struct inode *(*d_select_inode)(struct dentry * , unsigned int ) ; }; struct path { struct vfsmount *mnt ; struct dentry *dentry ; }; struct list_lru_one { struct list_head list ; long nr_items ; }; struct list_lru_memcg { struct list_lru_one *lru[0U] ; }; struct list_lru_node { spinlock_t lock ; struct list_lru_one lru ; struct list_lru_memcg *memcg_lrus ; }; struct list_lru { struct list_lru_node *node ; struct list_head list ; }; struct __anonstruct____missing_field_name_227 { struct radix_tree_node *parent ; void *private_data ; }; union __anonunion____missing_field_name_226 { struct __anonstruct____missing_field_name_227 __annonCompField62 ; struct callback_head callback_head ; }; struct radix_tree_node { unsigned int path ; unsigned int count ; union __anonunion____missing_field_name_226 __annonCompField63 ; struct list_head private_list ; void *slots[64U] ; unsigned long tags[3U][1U] ; }; struct radix_tree_root { unsigned int height ; gfp_t gfp_mask ; struct radix_tree_node *rnode ; }; struct fiemap_extent { __u64 fe_logical ; __u64 fe_physical ; __u64 fe_length ; __u64 fe_reserved64[2U] ; __u32 fe_flags ; __u32 fe_reserved[3U] ; }; enum migrate_mode { MIGRATE_ASYNC = 0, MIGRATE_SYNC_LIGHT = 1, MIGRATE_SYNC = 2 } ; struct block_device; struct export_operations; struct kiocb; struct poll_table_struct; struct kstatfs; struct swap_info_struct; struct iov_iter; struct iattr { unsigned int ia_valid ; umode_t ia_mode ; kuid_t ia_uid ; kgid_t ia_gid ; loff_t ia_size ; struct timespec ia_atime ; struct timespec ia_mtime ; struct timespec ia_ctime ; struct file *ia_file ; }; struct dquot; typedef __kernel_uid32_t projid_t; struct __anonstruct_kprojid_t_231 { projid_t val ; }; typedef struct __anonstruct_kprojid_t_231 kprojid_t; enum quota_type { USRQUOTA = 0, GRPQUOTA = 1, PRJQUOTA = 2 } ; typedef long long qsize_t; union __anonunion____missing_field_name_232 { kuid_t uid ; kgid_t gid ; kprojid_t projid ; }; struct kqid { union __anonunion____missing_field_name_232 __annonCompField65 ; enum quota_type type ; }; struct mem_dqblk { qsize_t dqb_bhardlimit ; qsize_t dqb_bsoftlimit ; qsize_t dqb_curspace ; qsize_t dqb_rsvspace ; qsize_t dqb_ihardlimit ; qsize_t dqb_isoftlimit ; qsize_t dqb_curinodes ; time_t dqb_btime ; time_t dqb_itime ; }; struct quota_format_type; struct mem_dqinfo { struct quota_format_type *dqi_format ; int dqi_fmt_id ; struct list_head dqi_dirty_list ; unsigned long dqi_flags ; unsigned int dqi_bgrace ; unsigned int dqi_igrace ; qsize_t dqi_max_spc_limit ; qsize_t dqi_max_ino_limit ; void *dqi_priv ; }; struct dquot { struct hlist_node dq_hash ; struct list_head dq_inuse ; struct list_head dq_free ; struct list_head dq_dirty ; struct mutex dq_lock ; atomic_t dq_count ; wait_queue_head_t dq_wait_unused ; struct super_block *dq_sb ; struct kqid dq_id ; loff_t dq_off ; unsigned long dq_flags ; struct mem_dqblk dq_dqb ; }; struct quota_format_ops { int (*check_quota_file)(struct super_block * , int ) ; int (*read_file_info)(struct super_block * , int ) ; int (*write_file_info)(struct super_block * , int ) ; int (*free_file_info)(struct super_block * , int ) ; int (*read_dqblk)(struct dquot * ) ; int (*commit_dqblk)(struct dquot * ) ; int (*release_dqblk)(struct dquot * ) ; }; struct dquot_operations { int (*write_dquot)(struct dquot * ) ; struct dquot *(*alloc_dquot)(struct super_block * , int ) ; void (*destroy_dquot)(struct dquot * ) ; int (*acquire_dquot)(struct dquot * ) ; int (*release_dquot)(struct dquot * ) ; int (*mark_dirty)(struct dquot * ) ; int (*write_info)(struct super_block * , int ) ; qsize_t *(*get_reserved_space)(struct inode * ) ; int (*get_projid)(struct inode * , kprojid_t * ) ; }; struct qc_dqblk { int d_fieldmask ; u64 d_spc_hardlimit ; u64 d_spc_softlimit ; u64 d_ino_hardlimit ; u64 d_ino_softlimit ; u64 d_space ; u64 d_ino_count ; s64 d_ino_timer ; s64 d_spc_timer ; int d_ino_warns ; int d_spc_warns ; u64 d_rt_spc_hardlimit ; u64 d_rt_spc_softlimit ; u64 d_rt_space ; s64 d_rt_spc_timer ; int d_rt_spc_warns ; }; struct qc_type_state { unsigned int flags ; unsigned int spc_timelimit ; unsigned int ino_timelimit ; unsigned int rt_spc_timelimit ; unsigned int spc_warnlimit ; unsigned int ino_warnlimit ; unsigned int rt_spc_warnlimit ; unsigned long long ino ; blkcnt_t blocks ; blkcnt_t nextents ; }; struct qc_state { unsigned int s_incoredqs ; struct qc_type_state s_state[3U] ; }; struct qc_info { int i_fieldmask ; unsigned int i_flags ; unsigned int i_spc_timelimit ; unsigned int i_ino_timelimit ; unsigned int i_rt_spc_timelimit ; unsigned int i_spc_warnlimit ; unsigned int i_ino_warnlimit ; unsigned int i_rt_spc_warnlimit ; }; struct quotactl_ops { int (*quota_on)(struct super_block * , int , int , struct path * ) ; int (*quota_off)(struct super_block * , int ) ; int (*quota_enable)(struct super_block * , unsigned int ) ; int (*quota_disable)(struct super_block * , unsigned int ) ; int (*quota_sync)(struct super_block * , int ) ; int (*set_info)(struct super_block * , int , struct qc_info * ) ; int (*get_dqblk)(struct super_block * , struct kqid , struct qc_dqblk * ) ; int (*set_dqblk)(struct super_block * , struct kqid , struct qc_dqblk * ) ; int (*get_state)(struct super_block * , struct qc_state * ) ; int (*rm_xquota)(struct super_block * , unsigned int ) ; }; struct quota_format_type { int qf_fmt_id ; struct quota_format_ops const *qf_ops ; struct module *qf_owner ; struct quota_format_type *qf_next ; }; struct quota_info { unsigned int flags ; struct mutex dqio_mutex ; struct mutex dqonoff_mutex ; struct inode *files[3U] ; struct mem_dqinfo info[3U] ; struct quota_format_ops const *ops[3U] ; }; struct kiocb { struct file *ki_filp ; loff_t ki_pos ; void (*ki_complete)(struct kiocb * , long , long ) ; void *private ; int ki_flags ; }; struct address_space_operations { int (*writepage)(struct page * , struct writeback_control * ) ; int (*readpage)(struct file * , struct page * ) ; int (*writepages)(struct address_space * , struct writeback_control * ) ; int (*set_page_dirty)(struct page * ) ; int (*readpages)(struct file * , struct address_space * , struct list_head * , unsigned int ) ; int (*write_begin)(struct file * , struct address_space * , loff_t , unsigned int , unsigned int , struct page ** , void ** ) ; int (*write_end)(struct file * , struct address_space * , loff_t , unsigned int , unsigned int , struct page * , void * ) ; sector_t (*bmap)(struct address_space * , sector_t ) ; void (*invalidatepage)(struct page * , unsigned int , unsigned int ) ; int (*releasepage)(struct page * , gfp_t ) ; void (*freepage)(struct page * ) ; ssize_t (*direct_IO)(struct kiocb * , struct iov_iter * , loff_t ) ; int (*migratepage)(struct address_space * , struct page * , struct page * , enum migrate_mode ) ; int (*launder_page)(struct page * ) ; int (*is_partially_uptodate)(struct page * , unsigned long , unsigned long ) ; void (*is_dirty_writeback)(struct page * , bool * , bool * ) ; int (*error_remove_page)(struct address_space * , struct page * ) ; int (*swap_activate)(struct swap_info_struct * , struct file * , sector_t * ) ; void (*swap_deactivate)(struct file * ) ; }; struct address_space { struct inode *host ; struct radix_tree_root page_tree ; spinlock_t tree_lock ; atomic_t i_mmap_writable ; struct rb_root i_mmap ; struct rw_semaphore i_mmap_rwsem ; unsigned long nrpages ; unsigned long nrshadows ; unsigned long writeback_index ; struct address_space_operations const *a_ops ; unsigned long flags ; spinlock_t private_lock ; struct list_head private_list ; void *private_data ; }; struct request_queue; struct hd_struct; struct gendisk; struct block_device { dev_t bd_dev ; int bd_openers ; struct inode *bd_inode ; struct super_block *bd_super ; struct mutex bd_mutex ; struct list_head bd_inodes ; void *bd_claiming ; void *bd_holder ; int bd_holders ; bool bd_write_holder ; struct list_head bd_holder_disks ; struct block_device *bd_contains ; unsigned int bd_block_size ; struct hd_struct *bd_part ; unsigned int bd_part_count ; int bd_invalidated ; struct gendisk *bd_disk ; struct request_queue *bd_queue ; struct list_head bd_list ; unsigned long bd_private ; int bd_fsfreeze_count ; struct mutex bd_fsfreeze_mutex ; }; struct posix_acl; struct inode_operations; union __anonunion____missing_field_name_235 { unsigned int const i_nlink ; unsigned int __i_nlink ; }; union __anonunion____missing_field_name_236 { struct hlist_head i_dentry ; struct callback_head i_rcu ; }; struct file_lock_context; struct cdev; union __anonunion____missing_field_name_237 { struct pipe_inode_info *i_pipe ; struct block_device *i_bdev ; struct cdev *i_cdev ; char *i_link ; }; struct inode { umode_t i_mode ; unsigned short i_opflags ; kuid_t i_uid ; kgid_t i_gid ; unsigned int i_flags ; struct posix_acl *i_acl ; struct posix_acl *i_default_acl ; struct inode_operations const *i_op ; struct super_block *i_sb ; struct address_space *i_mapping ; void *i_security ; unsigned long i_ino ; union __anonunion____missing_field_name_235 __annonCompField66 ; dev_t i_rdev ; loff_t i_size ; struct timespec i_atime ; struct timespec i_mtime ; struct timespec i_ctime ; spinlock_t i_lock ; unsigned short i_bytes ; unsigned int i_blkbits ; blkcnt_t i_blocks ; unsigned long i_state ; struct mutex i_mutex ; unsigned long dirtied_when ; unsigned long dirtied_time_when ; struct hlist_node i_hash ; struct list_head i_wb_list ; struct bdi_writeback *i_wb ; int i_wb_frn_winner ; u16 i_wb_frn_avg_time ; u16 i_wb_frn_history ; struct list_head i_lru ; struct list_head i_sb_list ; union __anonunion____missing_field_name_236 __annonCompField67 ; u64 i_version ; atomic_t i_count ; atomic_t i_dio_count ; atomic_t i_writecount ; atomic_t i_readcount ; struct file_operations const *i_fop ; struct file_lock_context *i_flctx ; struct address_space i_data ; struct list_head i_devices ; union __anonunion____missing_field_name_237 __annonCompField68 ; __u32 i_generation ; __u32 i_fsnotify_mask ; struct hlist_head i_fsnotify_marks ; void *i_private ; }; struct fown_struct { rwlock_t lock ; struct pid *pid ; enum pid_type pid_type ; kuid_t uid ; kuid_t euid ; int signum ; }; struct file_ra_state { unsigned long start ; unsigned int size ; unsigned int async_size ; unsigned int ra_pages ; unsigned int mmap_miss ; loff_t prev_pos ; }; union __anonunion_f_u_238 { struct llist_node fu_llist ; struct callback_head fu_rcuhead ; }; struct file { union __anonunion_f_u_238 f_u ; struct path f_path ; struct inode *f_inode ; struct file_operations const *f_op ; spinlock_t f_lock ; atomic_long_t f_count ; unsigned int f_flags ; fmode_t f_mode ; struct mutex f_pos_lock ; loff_t f_pos ; struct fown_struct f_owner ; struct cred const *f_cred ; struct file_ra_state f_ra ; u64 f_version ; void *f_security ; void *private_data ; struct list_head f_ep_links ; struct list_head f_tfile_llink ; struct address_space *f_mapping ; }; typedef void *fl_owner_t; struct file_lock; struct file_lock_operations { void (*fl_copy_lock)(struct file_lock * , struct file_lock * ) ; void (*fl_release_private)(struct file_lock * ) ; }; struct lock_manager_operations { int (*lm_compare_owner)(struct file_lock * , struct file_lock * ) ; unsigned long (*lm_owner_key)(struct file_lock * ) ; fl_owner_t (*lm_get_owner)(fl_owner_t ) ; void (*lm_put_owner)(fl_owner_t ) ; void (*lm_notify)(struct file_lock * ) ; int (*lm_grant)(struct file_lock * , int ) ; bool (*lm_break)(struct file_lock * ) ; int (*lm_change)(struct file_lock * , int , struct list_head * ) ; void (*lm_setup)(struct file_lock * , void ** ) ; }; struct nlm_lockowner; struct nfs_lock_info { u32 state ; struct nlm_lockowner *owner ; struct list_head list ; }; struct nfs4_lock_state; struct nfs4_lock_info { struct nfs4_lock_state *owner ; }; struct fasync_struct; struct __anonstruct_afs_240 { struct list_head link ; int state ; }; union __anonunion_fl_u_239 { struct nfs_lock_info nfs_fl ; struct nfs4_lock_info nfs4_fl ; struct __anonstruct_afs_240 afs ; }; struct file_lock { struct file_lock *fl_next ; struct list_head fl_list ; struct hlist_node fl_link ; struct list_head fl_block ; fl_owner_t fl_owner ; unsigned int fl_flags ; unsigned char fl_type ; unsigned int fl_pid ; int fl_link_cpu ; struct pid *fl_nspid ; wait_queue_head_t fl_wait ; struct file *fl_file ; loff_t fl_start ; loff_t fl_end ; struct fasync_struct *fl_fasync ; unsigned long fl_break_time ; unsigned long fl_downgrade_time ; struct file_lock_operations const *fl_ops ; struct lock_manager_operations const *fl_lmops ; union __anonunion_fl_u_239 fl_u ; }; struct file_lock_context { spinlock_t flc_lock ; struct list_head flc_flock ; struct list_head flc_posix ; struct list_head flc_lease ; }; struct fasync_struct { spinlock_t fa_lock ; int magic ; int fa_fd ; struct fasync_struct *fa_next ; struct file *fa_file ; struct callback_head fa_rcu ; }; struct sb_writers { struct percpu_counter counter[3U] ; wait_queue_head_t wait ; int frozen ; wait_queue_head_t wait_unfrozen ; struct lockdep_map lock_map[3U] ; }; struct super_operations; struct xattr_handler; struct mtd_info; struct super_block { struct list_head s_list ; dev_t s_dev ; unsigned char s_blocksize_bits ; unsigned long s_blocksize ; loff_t s_maxbytes ; struct file_system_type *s_type ; struct super_operations const *s_op ; struct dquot_operations const *dq_op ; struct quotactl_ops const *s_qcop ; struct export_operations const *s_export_op ; unsigned long s_flags ; unsigned long s_iflags ; unsigned long s_magic ; struct dentry *s_root ; struct rw_semaphore s_umount ; int s_count ; atomic_t s_active ; void *s_security ; struct xattr_handler const **s_xattr ; struct list_head s_inodes ; struct hlist_bl_head s_anon ; struct list_head s_mounts ; struct block_device *s_bdev ; struct backing_dev_info *s_bdi ; struct mtd_info *s_mtd ; struct hlist_node s_instances ; unsigned int s_quota_types ; struct quota_info s_dquot ; struct sb_writers s_writers ; char s_id[32U] ; u8 s_uuid[16U] ; void *s_fs_info ; unsigned int s_max_links ; fmode_t s_mode ; u32 s_time_gran ; struct mutex s_vfs_rename_mutex ; char *s_subtype ; char *s_options ; struct dentry_operations const *s_d_op ; int cleancache_poolid ; struct shrinker s_shrink ; atomic_long_t s_remove_count ; int s_readonly_remount ; struct workqueue_struct *s_dio_done_wq ; struct hlist_head s_pins ; struct list_lru s_dentry_lru ; struct list_lru s_inode_lru ; struct callback_head rcu ; int s_stack_depth ; }; struct fiemap_extent_info { unsigned int fi_flags ; unsigned int fi_extents_mapped ; unsigned int fi_extents_max ; struct fiemap_extent *fi_extents_start ; }; struct dir_context; struct dir_context { int (*actor)(struct dir_context * , char const * , int , loff_t , u64 , unsigned int ) ; loff_t pos ; }; struct file_operations { struct module *owner ; loff_t (*llseek)(struct file * , loff_t , int ) ; ssize_t (*read)(struct file * , char * , size_t , loff_t * ) ; ssize_t (*write)(struct file * , char const * , size_t , loff_t * ) ; ssize_t (*read_iter)(struct kiocb * , struct iov_iter * ) ; ssize_t (*write_iter)(struct kiocb * , struct iov_iter * ) ; int (*iterate)(struct file * , struct dir_context * ) ; unsigned int (*poll)(struct file * , struct poll_table_struct * ) ; long (*unlocked_ioctl)(struct file * , unsigned int , unsigned long ) ; long (*compat_ioctl)(struct file * , unsigned int , unsigned long ) ; int (*mmap)(struct file * , struct vm_area_struct * ) ; int (*mremap)(struct file * , struct vm_area_struct * ) ; int (*open)(struct inode * , struct file * ) ; int (*flush)(struct file * , fl_owner_t ) ; int (*release)(struct inode * , struct file * ) ; int (*fsync)(struct file * , loff_t , loff_t , int ) ; int (*aio_fsync)(struct kiocb * , int ) ; int (*fasync)(int , struct file * , int ) ; int (*lock)(struct file * , int , struct file_lock * ) ; ssize_t (*sendpage)(struct file * , struct page * , int , size_t , loff_t * , int ) ; unsigned long (*get_unmapped_area)(struct file * , unsigned long , unsigned long , unsigned long , unsigned long ) ; int (*check_flags)(int ) ; int (*flock)(struct file * , int , struct file_lock * ) ; ssize_t (*splice_write)(struct pipe_inode_info * , struct file * , loff_t * , size_t , unsigned int ) ; ssize_t (*splice_read)(struct file * , loff_t * , struct pipe_inode_info * , size_t , unsigned int ) ; int (*setlease)(struct file * , long , struct file_lock ** , void ** ) ; long (*fallocate)(struct file * , int , loff_t , loff_t ) ; void (*show_fdinfo)(struct seq_file * , struct file * ) ; }; struct inode_operations { struct dentry *(*lookup)(struct inode * , struct dentry * , unsigned int ) ; char const *(*follow_link)(struct dentry * , void ** ) ; int (*permission)(struct inode * , int ) ; struct posix_acl *(*get_acl)(struct inode * , int ) ; int (*readlink)(struct dentry * , char * , int ) ; void (*put_link)(struct inode * , void * ) ; int (*create)(struct inode * , struct dentry * , umode_t , bool ) ; int (*link)(struct dentry * , struct inode * , struct dentry * ) ; int (*unlink)(struct inode * , struct dentry * ) ; int (*symlink)(struct inode * , struct dentry * , char const * ) ; int (*mkdir)(struct inode * , struct dentry * , umode_t ) ; int (*rmdir)(struct inode * , struct dentry * ) ; int (*mknod)(struct inode * , struct dentry * , umode_t , dev_t ) ; int (*rename)(struct inode * , struct dentry * , struct inode * , struct dentry * ) ; int (*rename2)(struct inode * , struct dentry * , struct inode * , struct dentry * , unsigned int ) ; int (*setattr)(struct dentry * , struct iattr * ) ; int (*getattr)(struct vfsmount * , struct dentry * , struct kstat * ) ; int (*setxattr)(struct dentry * , char const * , void const * , size_t , int ) ; ssize_t (*getxattr)(struct dentry * , char const * , void * , size_t ) ; ssize_t (*listxattr)(struct dentry * , char * , size_t ) ; int (*removexattr)(struct dentry * , char const * ) ; int (*fiemap)(struct inode * , struct fiemap_extent_info * , u64 , u64 ) ; int (*update_time)(struct inode * , struct timespec * , int ) ; int (*atomic_open)(struct inode * , struct dentry * , struct file * , unsigned int , umode_t , int * ) ; int (*tmpfile)(struct inode * , struct dentry * , umode_t ) ; int (*set_acl)(struct inode * , struct posix_acl * , int ) ; }; struct super_operations { struct inode *(*alloc_inode)(struct super_block * ) ; void (*destroy_inode)(struct inode * ) ; void (*dirty_inode)(struct inode * , int ) ; int (*write_inode)(struct inode * , struct writeback_control * ) ; int (*drop_inode)(struct inode * ) ; void (*evict_inode)(struct inode * ) ; void (*put_super)(struct super_block * ) ; int (*sync_fs)(struct super_block * , int ) ; int (*freeze_super)(struct super_block * ) ; int (*freeze_fs)(struct super_block * ) ; int (*thaw_super)(struct super_block * ) ; int (*unfreeze_fs)(struct super_block * ) ; int (*statfs)(struct dentry * , struct kstatfs * ) ; int (*remount_fs)(struct super_block * , int * , char * ) ; void (*umount_begin)(struct super_block * ) ; int (*show_options)(struct seq_file * , struct dentry * ) ; int (*show_devname)(struct seq_file * , struct dentry * ) ; int (*show_path)(struct seq_file * , struct dentry * ) ; int (*show_stats)(struct seq_file * , struct dentry * ) ; ssize_t (*quota_read)(struct super_block * , int , char * , size_t , loff_t ) ; ssize_t (*quota_write)(struct super_block * , int , char const * , size_t , loff_t ) ; struct dquot **(*get_dquots)(struct inode * ) ; int (*bdev_try_to_free_page)(struct super_block * , struct page * , gfp_t ) ; long (*nr_cached_objects)(struct super_block * , struct shrink_control * ) ; long (*free_cached_objects)(struct super_block * , struct shrink_control * ) ; }; struct file_system_type { char const *name ; int fs_flags ; struct dentry *(*mount)(struct file_system_type * , int , char const * , void * ) ; void (*kill_sb)(struct super_block * ) ; struct module *owner ; struct file_system_type *next ; struct hlist_head fs_supers ; struct lock_class_key s_lock_key ; struct lock_class_key s_umount_key ; struct lock_class_key s_vfs_rename_key ; struct lock_class_key s_writers_key[3U] ; struct lock_class_key i_lock_key ; struct lock_class_key i_mutex_key ; struct lock_class_key i_mutex_dir_key ; }; struct exception_table_entry { int insn ; int fixup ; }; typedef unsigned char cc_t; typedef unsigned int speed_t; typedef unsigned int tcflag_t; struct ktermios { tcflag_t c_iflag ; tcflag_t c_oflag ; tcflag_t c_cflag ; tcflag_t c_lflag ; cc_t c_line ; cc_t c_cc[19U] ; speed_t c_ispeed ; speed_t c_ospeed ; }; struct winsize { unsigned short ws_row ; unsigned short ws_col ; unsigned short ws_xpixel ; unsigned short ws_ypixel ; }; struct termiox { __u16 x_hflag ; __u16 x_cflag ; __u16 x_rflag[5U] ; __u16 x_sflag ; }; struct cdev { struct kobject kobj ; struct module *owner ; struct file_operations const *ops ; struct list_head list ; dev_t dev ; unsigned int count ; }; struct tty_driver; struct serial_icounter_struct; struct tty_operations { struct tty_struct *(*lookup)(struct tty_driver * , struct inode * , int ) ; int (*install)(struct tty_driver * , struct tty_struct * ) ; void (*remove)(struct tty_driver * , struct tty_struct * ) ; int (*open)(struct tty_struct * , struct file * ) ; void (*close)(struct tty_struct * , struct file * ) ; void (*shutdown)(struct tty_struct * ) ; void (*cleanup)(struct tty_struct * ) ; int (*write)(struct tty_struct * , unsigned char const * , int ) ; int (*put_char)(struct tty_struct * , unsigned char ) ; void (*flush_chars)(struct tty_struct * ) ; int (*write_room)(struct tty_struct * ) ; int (*chars_in_buffer)(struct tty_struct * ) ; int (*ioctl)(struct tty_struct * , unsigned int , unsigned long ) ; long (*compat_ioctl)(struct tty_struct * , unsigned int , unsigned long ) ; void (*set_termios)(struct tty_struct * , struct ktermios * ) ; void (*throttle)(struct tty_struct * ) ; void (*unthrottle)(struct tty_struct * ) ; void (*stop)(struct tty_struct * ) ; void (*start)(struct tty_struct * ) ; void (*hangup)(struct tty_struct * ) ; int (*break_ctl)(struct tty_struct * , int ) ; void (*flush_buffer)(struct tty_struct * ) ; void (*set_ldisc)(struct tty_struct * ) ; void (*wait_until_sent)(struct tty_struct * , int ) ; void (*send_xchar)(struct tty_struct * , char ) ; int (*tiocmget)(struct tty_struct * ) ; int (*tiocmset)(struct tty_struct * , unsigned int , unsigned int ) ; int (*resize)(struct tty_struct * , struct winsize * ) ; int (*set_termiox)(struct tty_struct * , struct termiox * ) ; int (*get_icount)(struct tty_struct * , struct serial_icounter_struct * ) ; int (*poll_init)(struct tty_driver * , int , char * ) ; int (*poll_get_char)(struct tty_driver * , int ) ; void (*poll_put_char)(struct tty_driver * , int , char ) ; struct file_operations const *proc_fops ; }; struct proc_dir_entry; struct tty_port; struct tty_driver { int magic ; struct kref kref ; struct cdev *cdevs ; struct module *owner ; char const *driver_name ; char const *name ; int name_base ; int major ; int minor_start ; unsigned int num ; short type ; short subtype ; struct ktermios init_termios ; unsigned long flags ; struct proc_dir_entry *proc_entry ; struct tty_driver *other ; struct tty_struct **ttys ; struct tty_port **ports ; struct ktermios **termios ; void *driver_state ; struct tty_operations const *ops ; struct list_head tty_drivers ; }; struct ld_semaphore { long count ; raw_spinlock_t wait_lock ; unsigned int wait_readers ; struct list_head read_wait ; struct list_head write_wait ; struct lockdep_map dep_map ; }; struct tty_ldisc_ops { int magic ; char *name ; int num ; int flags ; int (*open)(struct tty_struct * ) ; void (*close)(struct tty_struct * ) ; void (*flush_buffer)(struct tty_struct * ) ; ssize_t (*chars_in_buffer)(struct tty_struct * ) ; ssize_t (*read)(struct tty_struct * , struct file * , unsigned char * , size_t ) ; ssize_t (*write)(struct tty_struct * , struct file * , unsigned char const * , size_t ) ; int (*ioctl)(struct tty_struct * , struct file * , unsigned int , unsigned long ) ; long (*compat_ioctl)(struct tty_struct * , struct file * , unsigned int , unsigned long ) ; void (*set_termios)(struct tty_struct * , struct ktermios * ) ; unsigned int (*poll)(struct tty_struct * , struct file * , struct poll_table_struct * ) ; int (*hangup)(struct tty_struct * ) ; void (*receive_buf)(struct tty_struct * , unsigned char const * , char * , int ) ; void (*write_wakeup)(struct tty_struct * ) ; void (*dcd_change)(struct tty_struct * , unsigned int ) ; void (*fasync)(struct tty_struct * , int ) ; int (*receive_buf2)(struct tty_struct * , unsigned char const * , char * , int ) ; struct module *owner ; int refcount ; }; struct tty_ldisc { struct tty_ldisc_ops *ops ; struct tty_struct *tty ; }; union __anonunion____missing_field_name_241 { struct tty_buffer *next ; struct llist_node free ; }; struct tty_buffer { union __anonunion____missing_field_name_241 __annonCompField69 ; int used ; int size ; int commit ; int read ; int flags ; unsigned long data[0U] ; }; struct tty_bufhead { struct tty_buffer *head ; struct work_struct work ; struct mutex lock ; atomic_t priority ; struct tty_buffer sentinel ; struct llist_head free ; atomic_t mem_used ; int mem_limit ; struct tty_buffer *tail ; }; struct tty_port_operations { int (*carrier_raised)(struct tty_port * ) ; void (*dtr_rts)(struct tty_port * , int ) ; void (*shutdown)(struct tty_port * ) ; int (*activate)(struct tty_port * , struct tty_struct * ) ; void (*destruct)(struct tty_port * ) ; }; struct tty_port { struct tty_bufhead buf ; struct tty_struct *tty ; struct tty_struct *itty ; struct tty_port_operations const *ops ; spinlock_t lock ; int blocked_open ; int count ; wait_queue_head_t open_wait ; wait_queue_head_t close_wait ; wait_queue_head_t delta_msr_wait ; unsigned long flags ; unsigned char console : 1 ; unsigned char low_latency : 1 ; struct mutex mutex ; struct mutex buf_mutex ; unsigned char *xmit_buf ; unsigned int close_delay ; unsigned int closing_wait ; int drain_delay ; struct kref kref ; }; struct tty_struct { int magic ; struct kref kref ; struct device *dev ; struct tty_driver *driver ; struct tty_operations const *ops ; int index ; struct ld_semaphore ldisc_sem ; struct tty_ldisc *ldisc ; struct mutex atomic_write_lock ; struct mutex legacy_mutex ; struct mutex throttle_mutex ; struct rw_semaphore termios_rwsem ; struct mutex winsize_mutex ; spinlock_t ctrl_lock ; spinlock_t flow_lock ; struct ktermios termios ; struct ktermios termios_locked ; struct termiox *termiox ; char name[64U] ; struct pid *pgrp ; struct pid *session ; unsigned long flags ; int count ; struct winsize winsize ; unsigned char stopped : 1 ; unsigned char flow_stopped : 1 ; unsigned long unused : 62 ; int hw_stopped ; unsigned char ctrl_status ; unsigned char packet : 1 ; unsigned long unused_ctrl : 55 ; unsigned int receive_room ; int flow_change ; struct tty_struct *link ; struct fasync_struct *fasync ; int alt_speed ; wait_queue_head_t write_wait ; wait_queue_head_t read_wait ; struct work_struct hangup_work ; void *disc_data ; void *driver_data ; struct list_head tty_files ; int closing ; unsigned char *write_buf ; int write_cnt ; struct work_struct SAK_work ; struct tty_port *port ; }; struct class; typedef unsigned long kernel_ulong_t; struct pci_device_id { __u32 vendor ; __u32 device ; __u32 subvendor ; __u32 subdevice ; __u32 class ; __u32 class_mask ; kernel_ulong_t driver_data ; }; struct acpi_device_id { __u8 id[9U] ; kernel_ulong_t driver_data ; }; struct of_device_id { char name[32U] ; char type[32U] ; char compatible[128U] ; void const *data ; }; struct platform_device_id { char name[20U] ; kernel_ulong_t driver_data ; }; struct klist_node; struct klist_node { void *n_klist ; struct list_head n_node ; struct kref n_ref ; }; struct seq_file { char *buf ; size_t size ; size_t from ; size_t count ; size_t pad_until ; loff_t index ; loff_t read_pos ; u64 version ; struct mutex lock ; struct seq_operations const *op ; int poll_event ; struct user_namespace *user_ns ; void *private ; }; struct seq_operations { void *(*start)(struct seq_file * , loff_t * ) ; void (*stop)(struct seq_file * , void * ) ; void *(*next)(struct seq_file * , void * , loff_t * ) ; int (*show)(struct seq_file * , void * ) ; }; struct pinctrl; struct pinctrl_state; struct dev_pin_info { struct pinctrl *p ; struct pinctrl_state *default_state ; struct pinctrl_state *sleep_state ; struct pinctrl_state *idle_state ; }; struct dma_map_ops; struct dev_archdata { struct dma_map_ops *dma_ops ; void *iommu ; }; struct pdev_archdata { }; struct device_private; struct device_driver; struct driver_private; struct subsys_private; struct bus_type; struct device_node; struct fwnode_handle; struct iommu_ops; struct iommu_group; struct device_attribute; struct bus_type { char const *name ; char const *dev_name ; struct device *dev_root ; struct device_attribute *dev_attrs ; struct attribute_group const **bus_groups ; struct attribute_group const **dev_groups ; struct attribute_group const **drv_groups ; int (*match)(struct device * , struct device_driver * ) ; int (*uevent)(struct device * , struct kobj_uevent_env * ) ; int (*probe)(struct device * ) ; int (*remove)(struct device * ) ; void (*shutdown)(struct device * ) ; int (*online)(struct device * ) ; int (*offline)(struct device * ) ; int (*suspend)(struct device * , pm_message_t ) ; int (*resume)(struct device * ) ; struct dev_pm_ops const *pm ; struct iommu_ops const *iommu_ops ; struct subsys_private *p ; struct lock_class_key lock_key ; }; struct device_type; enum probe_type { PROBE_DEFAULT_STRATEGY = 0, PROBE_PREFER_ASYNCHRONOUS = 1, PROBE_FORCE_SYNCHRONOUS = 2 } ; struct device_driver { char const *name ; struct bus_type *bus ; struct module *owner ; char const *mod_name ; bool suppress_bind_attrs ; enum probe_type probe_type ; struct of_device_id const *of_match_table ; struct acpi_device_id const *acpi_match_table ; int (*probe)(struct device * ) ; int (*remove)(struct device * ) ; void (*shutdown)(struct device * ) ; int (*suspend)(struct device * , pm_message_t ) ; int (*resume)(struct device * ) ; struct attribute_group const **groups ; struct dev_pm_ops const *pm ; struct driver_private *p ; }; struct class_attribute; struct class { char const *name ; struct module *owner ; struct class_attribute *class_attrs ; struct attribute_group const **dev_groups ; struct kobject *dev_kobj ; int (*dev_uevent)(struct device * , struct kobj_uevent_env * ) ; char *(*devnode)(struct device * , umode_t * ) ; void (*class_release)(struct class * ) ; void (*dev_release)(struct device * ) ; int (*suspend)(struct device * , pm_message_t ) ; int (*resume)(struct device * ) ; struct kobj_ns_type_operations const *ns_type ; void const *(*namespace)(struct device * ) ; struct dev_pm_ops const *pm ; struct subsys_private *p ; }; struct class_attribute { struct attribute attr ; ssize_t (*show)(struct class * , struct class_attribute * , char * ) ; ssize_t (*store)(struct class * , struct class_attribute * , char const * , size_t ) ; }; struct device_type { char const *name ; struct attribute_group const **groups ; int (*uevent)(struct device * , struct kobj_uevent_env * ) ; char *(*devnode)(struct device * , umode_t * , kuid_t * , kgid_t * ) ; void (*release)(struct device * ) ; struct dev_pm_ops const *pm ; }; struct device_attribute { struct attribute attr ; ssize_t (*show)(struct device * , struct device_attribute * , char * ) ; ssize_t (*store)(struct device * , struct device_attribute * , char const * , size_t ) ; }; struct device_dma_parameters { unsigned int max_segment_size ; unsigned long segment_boundary_mask ; }; struct dma_coherent_mem; struct cma; struct device { struct device *parent ; struct device_private *p ; struct kobject kobj ; char const *init_name ; struct device_type const *type ; struct mutex mutex ; struct bus_type *bus ; struct device_driver *driver ; void *platform_data ; void *driver_data ; struct dev_pm_info power ; struct dev_pm_domain *pm_domain ; struct dev_pin_info *pins ; int numa_node ; u64 *dma_mask ; u64 coherent_dma_mask ; unsigned long dma_pfn_offset ; struct device_dma_parameters *dma_parms ; struct list_head dma_pools ; struct dma_coherent_mem *dma_mem ; struct cma *cma_area ; struct dev_archdata archdata ; struct device_node *of_node ; struct fwnode_handle *fwnode ; dev_t devt ; u32 id ; spinlock_t devres_lock ; struct list_head devres_head ; struct klist_node knode_class ; struct class *class ; struct attribute_group const **groups ; void (*release)(struct device * ) ; struct iommu_group *iommu_group ; bool offline_disabled ; bool offline ; }; struct wakeup_source { char const *name ; struct list_head entry ; spinlock_t lock ; struct wake_irq *wakeirq ; struct timer_list timer ; unsigned long timer_expires ; ktime_t total_time ; ktime_t max_time ; ktime_t last_time ; ktime_t start_prevent_time ; ktime_t prevent_sleep_time ; unsigned long event_count ; unsigned long active_count ; unsigned long relax_count ; unsigned long expire_count ; unsigned long wakeup_count ; bool active ; bool autosleep_enabled ; }; enum fwnode_type { FWNODE_INVALID = 0, FWNODE_OF = 1, FWNODE_ACPI = 2, FWNODE_PDATA = 3 } ; struct fwnode_handle { enum fwnode_type type ; struct fwnode_handle *secondary ; }; typedef u32 phandle; struct property { char *name ; int length ; void *value ; struct property *next ; unsigned long _flags ; unsigned int unique_id ; struct bin_attribute attr ; }; struct device_node { char const *name ; char const *type ; phandle phandle ; char const *full_name ; struct fwnode_handle fwnode ; struct property *properties ; struct property *deadprops ; struct device_node *parent ; struct device_node *child ; struct device_node *sibling ; struct kobject kobj ; unsigned long _flags ; void *data ; }; struct i2c_msg { __u16 addr ; __u16 flags ; __u16 len ; __u8 *buf ; }; union i2c_smbus_data { __u8 byte ; __u16 word ; __u8 block[34U] ; }; struct i2c_algorithm; struct i2c_client; enum i2c_slave_event; enum i2c_slave_event; struct i2c_client { unsigned short flags ; unsigned short addr ; char name[20U] ; struct i2c_adapter *adapter ; struct device dev ; int irq ; struct list_head detected ; int (*slave_cb)(struct i2c_client * , enum i2c_slave_event , u8 * ) ; }; enum i2c_slave_event { I2C_SLAVE_READ_REQUESTED = 0, I2C_SLAVE_WRITE_REQUESTED = 1, I2C_SLAVE_READ_PROCESSED = 2, I2C_SLAVE_WRITE_RECEIVED = 3, I2C_SLAVE_STOP = 4 } ; struct i2c_algorithm { int (*master_xfer)(struct i2c_adapter * , struct i2c_msg * , int ) ; int (*smbus_xfer)(struct i2c_adapter * , u16 , unsigned short , char , u8 , int , union i2c_smbus_data * ) ; u32 (*functionality)(struct i2c_adapter * ) ; int (*reg_slave)(struct i2c_client * ) ; int (*unreg_slave)(struct i2c_client * ) ; }; struct i2c_bus_recovery_info { int (*recover_bus)(struct i2c_adapter * ) ; int (*get_scl)(struct i2c_adapter * ) ; void (*set_scl)(struct i2c_adapter * , int ) ; int (*get_sda)(struct i2c_adapter * ) ; void (*prepare_recovery)(struct i2c_adapter * ) ; void (*unprepare_recovery)(struct i2c_adapter * ) ; int scl_gpio ; int sda_gpio ; }; struct i2c_adapter_quirks { u64 flags ; int max_num_msgs ; u16 max_write_len ; u16 max_read_len ; u16 max_comb_1st_msg_len ; u16 max_comb_2nd_msg_len ; }; struct i2c_adapter { struct module *owner ; unsigned int class ; struct i2c_algorithm const *algo ; void *algo_data ; struct rt_mutex bus_lock ; int timeout ; int retries ; struct device dev ; int nr ; char name[48U] ; struct completion dev_released ; struct mutex userspace_clients_lock ; struct list_head userspace_clients ; struct i2c_bus_recovery_info *bus_recovery_info ; struct i2c_adapter_quirks const *quirks ; }; struct fb_fix_screeninfo { char id[16U] ; unsigned long smem_start ; __u32 smem_len ; __u32 type ; __u32 type_aux ; __u32 visual ; __u16 xpanstep ; __u16 ypanstep ; __u16 ywrapstep ; __u32 line_length ; unsigned long mmio_start ; __u32 mmio_len ; __u32 accel ; __u16 capabilities ; __u16 reserved[2U] ; }; struct fb_bitfield { __u32 offset ; __u32 length ; __u32 msb_right ; }; struct fb_var_screeninfo { __u32 xres ; __u32 yres ; __u32 xres_virtual ; __u32 yres_virtual ; __u32 xoffset ; __u32 yoffset ; __u32 bits_per_pixel ; __u32 grayscale ; struct fb_bitfield red ; struct fb_bitfield green ; struct fb_bitfield blue ; struct fb_bitfield transp ; __u32 nonstd ; __u32 activate ; __u32 height ; __u32 width ; __u32 accel_flags ; __u32 pixclock ; __u32 left_margin ; __u32 right_margin ; __u32 upper_margin ; __u32 lower_margin ; __u32 hsync_len ; __u32 vsync_len ; __u32 sync ; __u32 vmode ; __u32 rotate ; __u32 colorspace ; __u32 reserved[4U] ; }; struct fb_cmap { __u32 start ; __u32 len ; __u16 *red ; __u16 *green ; __u16 *blue ; __u16 *transp ; }; struct fb_copyarea { __u32 dx ; __u32 dy ; __u32 width ; __u32 height ; __u32 sx ; __u32 sy ; }; struct fb_fillrect { __u32 dx ; __u32 dy ; __u32 width ; __u32 height ; __u32 color ; __u32 rop ; }; struct fb_image { __u32 dx ; __u32 dy ; __u32 width ; __u32 height ; __u32 fg_color ; __u32 bg_color ; __u8 depth ; char const *data ; struct fb_cmap cmap ; }; struct fbcurpos { __u16 x ; __u16 y ; }; struct fb_cursor { __u16 set ; __u16 enable ; __u16 rop ; char const *mask ; struct fbcurpos hot ; struct fb_image image ; }; enum backlight_type { BACKLIGHT_RAW = 1, BACKLIGHT_PLATFORM = 2, BACKLIGHT_FIRMWARE = 3, BACKLIGHT_TYPE_MAX = 4 } ; struct backlight_device; struct backlight_ops { unsigned int options ; int (*update_status)(struct backlight_device * ) ; int (*get_brightness)(struct backlight_device * ) ; int (*check_fb)(struct backlight_device * , struct fb_info * ) ; }; struct backlight_properties { int brightness ; int max_brightness ; int power ; int fb_blank ; enum backlight_type type ; unsigned int state ; }; struct backlight_device { struct backlight_properties props ; struct mutex update_lock ; struct mutex ops_lock ; struct backlight_ops const *ops ; struct notifier_block fb_notif ; struct list_head entry ; struct device dev ; bool fb_bl_on[32U] ; int use_count ; }; struct fb_chroma { __u32 redx ; __u32 greenx ; __u32 bluex ; __u32 whitex ; __u32 redy ; __u32 greeny ; __u32 bluey ; __u32 whitey ; }; struct fb_videomode; struct fb_monspecs { struct fb_chroma chroma ; struct fb_videomode *modedb ; __u8 manufacturer[4U] ; __u8 monitor[14U] ; __u8 serial_no[14U] ; __u8 ascii[14U] ; __u32 modedb_len ; __u32 model ; __u32 serial ; __u32 year ; __u32 week ; __u32 hfmin ; __u32 hfmax ; __u32 dclkmin ; __u32 dclkmax ; __u16 input ; __u16 dpms ; __u16 signal ; __u16 vfmin ; __u16 vfmax ; __u16 gamma ; unsigned char gtf : 1 ; __u16 misc ; __u8 version ; __u8 revision ; __u8 max_x ; __u8 max_y ; }; struct fb_blit_caps { u32 x ; u32 y ; u32 len ; u32 flags ; }; struct fb_pixmap { u8 *addr ; u32 size ; u32 offset ; u32 buf_align ; u32 scan_align ; u32 access_align ; u32 flags ; u32 blit_x ; u32 blit_y ; void (*writeio)(struct fb_info * , void * , void * , unsigned int ) ; void (*readio)(struct fb_info * , void * , void * , unsigned int ) ; }; struct fb_deferred_io { unsigned long delay ; struct mutex lock ; struct list_head pagelist ; void (*first_io)(struct fb_info * ) ; void (*deferred_io)(struct fb_info * , struct list_head * ) ; }; struct fb_ops { struct module *owner ; int (*fb_open)(struct fb_info * , int ) ; int (*fb_release)(struct fb_info * , int ) ; ssize_t (*fb_read)(struct fb_info * , char * , size_t , loff_t * ) ; ssize_t (*fb_write)(struct fb_info * , char const * , size_t , loff_t * ) ; int (*fb_check_var)(struct fb_var_screeninfo * , struct fb_info * ) ; int (*fb_set_par)(struct fb_info * ) ; int (*fb_setcolreg)(unsigned int , unsigned int , unsigned int , unsigned int , unsigned int , struct fb_info * ) ; int (*fb_setcmap)(struct fb_cmap * , struct fb_info * ) ; int (*fb_blank)(int , struct fb_info * ) ; int (*fb_pan_display)(struct fb_var_screeninfo * , struct fb_info * ) ; void (*fb_fillrect)(struct fb_info * , struct fb_fillrect const * ) ; void (*fb_copyarea)(struct fb_info * , struct fb_copyarea const * ) ; void (*fb_imageblit)(struct fb_info * , struct fb_image const * ) ; int (*fb_cursor)(struct fb_info * , struct fb_cursor * ) ; void (*fb_rotate)(struct fb_info * , int ) ; int (*fb_sync)(struct fb_info * ) ; int (*fb_ioctl)(struct fb_info * , unsigned int , unsigned long ) ; int (*fb_compat_ioctl)(struct fb_info * , unsigned int , unsigned long ) ; int (*fb_mmap)(struct fb_info * , struct vm_area_struct * ) ; void (*fb_get_caps)(struct fb_info * , struct fb_blit_caps * , struct fb_var_screeninfo * ) ; void (*fb_destroy)(struct fb_info * ) ; int (*fb_debug_enter)(struct fb_info * ) ; int (*fb_debug_leave)(struct fb_info * ) ; }; struct fb_tilemap { __u32 width ; __u32 height ; __u32 depth ; __u32 length ; __u8 const *data ; }; struct fb_tilerect { __u32 sx ; __u32 sy ; __u32 width ; __u32 height ; __u32 index ; __u32 fg ; __u32 bg ; __u32 rop ; }; struct fb_tilearea { __u32 sx ; __u32 sy ; __u32 dx ; __u32 dy ; __u32 width ; __u32 height ; }; struct fb_tileblit { __u32 sx ; __u32 sy ; __u32 width ; __u32 height ; __u32 fg ; __u32 bg ; __u32 length ; __u32 *indices ; }; struct fb_tilecursor { __u32 sx ; __u32 sy ; __u32 mode ; __u32 shape ; __u32 fg ; __u32 bg ; }; struct fb_tile_ops { void (*fb_settile)(struct fb_info * , struct fb_tilemap * ) ; void (*fb_tilecopy)(struct fb_info * , struct fb_tilearea * ) ; void (*fb_tilefill)(struct fb_info * , struct fb_tilerect * ) ; void (*fb_tileblit)(struct fb_info * , struct fb_tileblit * ) ; void (*fb_tilecursor)(struct fb_info * , struct fb_tilecursor * ) ; int (*fb_get_tilemax)(struct fb_info * ) ; }; struct aperture { resource_size_t base ; resource_size_t size ; }; struct apertures_struct { unsigned int count ; struct aperture ranges[0U] ; }; struct fb_info { atomic_t count ; int node ; int flags ; struct mutex lock ; struct mutex mm_lock ; struct fb_var_screeninfo var ; struct fb_fix_screeninfo fix ; struct fb_monspecs monspecs ; struct work_struct queue ; struct fb_pixmap pixmap ; struct fb_pixmap sprite ; struct fb_cmap cmap ; struct list_head modelist ; struct fb_videomode *mode ; struct backlight_device *bl_dev ; struct mutex bl_curve_mutex ; u8 bl_curve[128U] ; struct delayed_work deferred_work ; struct fb_deferred_io *fbdefio ; struct fb_ops *fbops ; struct device *device ; struct device *dev ; int class_flag ; struct fb_tile_ops *tileops ; char *screen_base ; unsigned long screen_size ; void *pseudo_palette ; u32 state ; void *fbcon_par ; void *par ; struct apertures_struct *apertures ; bool skip_vt_switch ; }; struct fb_videomode { char const *name ; u32 refresh ; u32 xres ; u32 yres ; u32 pixclock ; u32 left_margin ; u32 right_margin ; u32 upper_margin ; u32 lower_margin ; u32 hsync_len ; u32 vsync_len ; u32 sync ; u32 vmode ; u32 flag ; }; enum chipset_type { NOT_SUPPORTED = 0, SUPPORTED = 1 } ; struct agp_version { u16 major ; u16 minor ; }; struct agp_kern_info { struct agp_version version ; struct pci_dev *device ; enum chipset_type chipset ; unsigned long mode ; unsigned long aper_base ; size_t aper_size ; int max_memory ; int current_memory ; bool cant_use_aperture ; unsigned long page_mask ; struct vm_operations_struct const *vm_ops ; }; struct agp_bridge_data; struct scatterlist; struct dma_attrs { unsigned long flags[1U] ; }; enum dma_data_direction { DMA_BIDIRECTIONAL = 0, DMA_TO_DEVICE = 1, DMA_FROM_DEVICE = 2, DMA_NONE = 3 } ; struct scatterlist { unsigned long sg_magic ; unsigned long page_link ; unsigned int offset ; unsigned int length ; dma_addr_t dma_address ; unsigned int dma_length ; }; struct sg_table { struct scatterlist *sgl ; unsigned int nents ; unsigned int orig_nents ; }; struct dma_map_ops { void *(*alloc)(struct device * , size_t , dma_addr_t * , gfp_t , struct dma_attrs * ) ; void (*free)(struct device * , size_t , void * , dma_addr_t , struct dma_attrs * ) ; int (*mmap)(struct device * , struct vm_area_struct * , void * , dma_addr_t , size_t , struct dma_attrs * ) ; int (*get_sgtable)(struct device * , struct sg_table * , void * , dma_addr_t , size_t , struct dma_attrs * ) ; dma_addr_t (*map_page)(struct device * , struct page * , unsigned long , size_t , enum dma_data_direction , struct dma_attrs * ) ; void (*unmap_page)(struct device * , dma_addr_t , size_t , enum dma_data_direction , struct dma_attrs * ) ; int (*map_sg)(struct device * , struct scatterlist * , int , enum dma_data_direction , struct dma_attrs * ) ; void (*unmap_sg)(struct device * , struct scatterlist * , int , enum dma_data_direction , struct dma_attrs * ) ; void (*sync_single_for_cpu)(struct device * , dma_addr_t , size_t , enum dma_data_direction ) ; void (*sync_single_for_device)(struct device * , dma_addr_t , size_t , enum dma_data_direction ) ; void (*sync_sg_for_cpu)(struct device * , struct scatterlist * , int , enum dma_data_direction ) ; void (*sync_sg_for_device)(struct device * , struct scatterlist * , int , enum dma_data_direction ) ; int (*mapping_error)(struct device * , dma_addr_t ) ; int (*dma_supported)(struct device * , u64 ) ; int (*set_dma_mask)(struct device * , u64 ) ; int is_phys ; }; struct hotplug_slot; struct pci_slot { struct pci_bus *bus ; struct list_head list ; struct hotplug_slot *hotplug ; unsigned char number ; struct kobject kobj ; }; typedef int pci_power_t; typedef unsigned int pci_channel_state_t; enum pci_channel_state { pci_channel_io_normal = 1, pci_channel_io_frozen = 2, pci_channel_io_perm_failure = 3 } ; typedef unsigned short pci_dev_flags_t; typedef unsigned short pci_bus_flags_t; struct pcie_link_state; struct pci_vpd; struct pci_sriov; struct pci_ats; struct pci_driver; union __anonunion____missing_field_name_254 { struct pci_sriov *sriov ; struct pci_dev *physfn ; }; struct pci_dev { struct list_head bus_list ; struct pci_bus *bus ; struct pci_bus *subordinate ; void *sysdata ; struct proc_dir_entry *procent ; struct pci_slot *slot ; unsigned int devfn ; unsigned short vendor ; unsigned short device ; unsigned short subsystem_vendor ; unsigned short subsystem_device ; unsigned int class ; u8 revision ; u8 hdr_type ; u8 pcie_cap ; u8 msi_cap ; u8 msix_cap ; unsigned char pcie_mpss : 3 ; u8 rom_base_reg ; u8 pin ; u16 pcie_flags_reg ; u8 dma_alias_devfn ; struct pci_driver *driver ; u64 dma_mask ; struct device_dma_parameters dma_parms ; pci_power_t current_state ; u8 pm_cap ; unsigned char pme_support : 5 ; unsigned char pme_interrupt : 1 ; unsigned char pme_poll : 1 ; unsigned char d1_support : 1 ; unsigned char d2_support : 1 ; unsigned char no_d1d2 : 1 ; unsigned char no_d3cold : 1 ; unsigned char d3cold_allowed : 1 ; unsigned char mmio_always_on : 1 ; unsigned char wakeup_prepared : 1 ; unsigned char runtime_d3cold : 1 ; unsigned char ignore_hotplug : 1 ; unsigned int d3_delay ; unsigned int d3cold_delay ; struct pcie_link_state *link_state ; pci_channel_state_t error_state ; struct device dev ; int cfg_size ; unsigned int irq ; struct resource resource[17U] ; bool match_driver ; unsigned char transparent : 1 ; unsigned char multifunction : 1 ; unsigned char is_added : 1 ; unsigned char is_busmaster : 1 ; unsigned char no_msi : 1 ; unsigned char no_64bit_msi : 1 ; unsigned char block_cfg_access : 1 ; unsigned char broken_parity_status : 1 ; unsigned char irq_reroute_variant : 2 ; unsigned char msi_enabled : 1 ; unsigned char msix_enabled : 1 ; unsigned char ari_enabled : 1 ; unsigned char is_managed : 1 ; unsigned char needs_freset : 1 ; unsigned char state_saved : 1 ; unsigned char is_physfn : 1 ; unsigned char is_virtfn : 1 ; unsigned char reset_fn : 1 ; unsigned char is_hotplug_bridge : 1 ; unsigned char __aer_firmware_first_valid : 1 ; unsigned char __aer_firmware_first : 1 ; unsigned char broken_intx_masking : 1 ; unsigned char io_window_1k : 1 ; unsigned char irq_managed : 1 ; unsigned char has_secondary_link : 1 ; pci_dev_flags_t dev_flags ; atomic_t enable_cnt ; u32 saved_config_space[16U] ; struct hlist_head saved_cap_space ; struct bin_attribute *rom_attr ; int rom_attr_enabled ; struct bin_attribute *res_attr[17U] ; struct bin_attribute *res_attr_wc[17U] ; struct list_head msi_list ; struct attribute_group const **msi_irq_groups ; struct pci_vpd *vpd ; union __anonunion____missing_field_name_254 __annonCompField77 ; struct pci_ats *ats ; phys_addr_t rom ; size_t romlen ; char *driver_override ; }; struct pci_ops; struct msi_controller; struct pci_bus { struct list_head node ; struct pci_bus *parent ; struct list_head children ; struct list_head devices ; struct pci_dev *self ; struct list_head slots ; struct resource *resource[4U] ; struct list_head resources ; struct resource busn_res ; struct pci_ops *ops ; struct msi_controller *msi ; void *sysdata ; struct proc_dir_entry *procdir ; unsigned char number ; unsigned char primary ; unsigned char max_bus_speed ; unsigned char cur_bus_speed ; char name[48U] ; unsigned short bridge_ctl ; pci_bus_flags_t bus_flags ; struct device *bridge ; struct device dev ; struct bin_attribute *legacy_io ; struct bin_attribute *legacy_mem ; unsigned char is_added : 1 ; }; struct pci_ops { void *(*map_bus)(struct pci_bus * , unsigned int , int ) ; int (*read)(struct pci_bus * , unsigned int , int , int , u32 * ) ; int (*write)(struct pci_bus * , unsigned int , int , int , u32 ) ; }; struct pci_dynids { spinlock_t lock ; struct list_head list ; }; typedef unsigned int pci_ers_result_t; struct pci_error_handlers { pci_ers_result_t (*error_detected)(struct pci_dev * , enum pci_channel_state ) ; pci_ers_result_t (*mmio_enabled)(struct pci_dev * ) ; pci_ers_result_t (*link_reset)(struct pci_dev * ) ; pci_ers_result_t (*slot_reset)(struct pci_dev * ) ; void (*reset_notify)(struct pci_dev * , bool ) ; void (*resume)(struct pci_dev * ) ; }; struct pci_driver { struct list_head node ; char const *name ; struct pci_device_id const *id_table ; int (*probe)(struct pci_dev * , struct pci_device_id const * ) ; void (*remove)(struct pci_dev * ) ; int (*suspend)(struct pci_dev * , pm_message_t ) ; int (*suspend_late)(struct pci_dev * , pm_message_t ) ; int (*resume_early)(struct pci_dev * ) ; int (*resume)(struct pci_dev * ) ; void (*shutdown)(struct pci_dev * ) ; int (*sriov_configure)(struct pci_dev * , int ) ; struct pci_error_handlers const *err_handler ; struct device_driver driver ; struct pci_dynids dynids ; }; struct mfd_cell; struct platform_device { char const *name ; int id ; bool id_auto ; struct device dev ; u32 num_resources ; struct resource *resource ; struct platform_device_id const *id_entry ; char *driver_override ; struct mfd_cell *mfd_cell ; struct pdev_archdata archdata ; }; struct pollfd { int fd ; short events ; short revents ; }; struct poll_table_struct { void (*_qproc)(struct file * , wait_queue_head_t * , struct poll_table_struct * ) ; unsigned long _key ; }; typedef unsigned int drm_magic_t; struct drm_clip_rect { unsigned short x1 ; unsigned short y1 ; unsigned short x2 ; unsigned short y2 ; }; struct drm_hw_lock { unsigned int volatile lock ; char padding[60U] ; }; struct drm_mode_fb_cmd2 { __u32 fb_id ; __u32 width ; __u32 height ; __u32 pixel_format ; __u32 flags ; __u32 handles[4U] ; __u32 pitches[4U] ; __u32 offsets[4U] ; __u64 modifier[4U] ; }; struct drm_mode_create_dumb { uint32_t height ; uint32_t width ; uint32_t bpp ; uint32_t flags ; uint32_t handle ; uint32_t pitch ; uint64_t size ; }; struct drm_event { __u32 type ; __u32 length ; }; struct drm_event_vblank { struct drm_event base ; __u64 user_data ; __u32 tv_sec ; __u32 tv_usec ; __u32 sequence ; __u32 reserved ; }; struct drm_agp_head { struct agp_kern_info agp_info ; struct list_head memory ; unsigned long mode ; struct agp_bridge_data *bridge ; int enabled ; int acquired ; unsigned long base ; int agp_mtrr ; int cant_use_aperture ; unsigned long page_mask ; }; enum hdmi_picture_aspect { HDMI_PICTURE_ASPECT_NONE = 0, HDMI_PICTURE_ASPECT_4_3 = 1, HDMI_PICTURE_ASPECT_16_9 = 2, HDMI_PICTURE_ASPECT_RESERVED = 3 } ; struct ww_class { atomic_long_t stamp ; struct lock_class_key acquire_key ; struct lock_class_key mutex_key ; char const *acquire_name ; char const *mutex_name ; }; struct ww_mutex; struct ww_acquire_ctx { struct task_struct *task ; unsigned long stamp ; unsigned int acquired ; unsigned int done_acquire ; struct ww_class *ww_class ; struct ww_mutex *contending_lock ; struct lockdep_map dep_map ; unsigned int deadlock_inject_interval ; unsigned int deadlock_inject_countdown ; }; struct ww_mutex { struct mutex base ; struct ww_acquire_ctx *ctx ; struct ww_class *ww_class ; }; struct drm_modeset_lock; struct drm_modeset_acquire_ctx { struct ww_acquire_ctx ww_ctx ; struct drm_modeset_lock *contended ; struct list_head locked ; bool trylock_only ; }; struct drm_modeset_lock { struct ww_mutex mutex ; struct list_head head ; }; struct drm_plane; struct drm_mode_set; struct drm_object_properties; struct fence; struct drm_mode_object { uint32_t id ; uint32_t type ; struct drm_object_properties *properties ; }; struct drm_property; struct drm_object_properties { int count ; int atomic_count ; struct drm_property *properties[24U] ; uint64_t values[24U] ; }; enum drm_connector_force { DRM_FORCE_UNSPECIFIED = 0, DRM_FORCE_OFF = 1, DRM_FORCE_ON = 2, DRM_FORCE_ON_DIGITAL = 3 } ; enum drm_mode_status { MODE_OK = 0, MODE_HSYNC = 1, MODE_VSYNC = 2, MODE_H_ILLEGAL = 3, MODE_V_ILLEGAL = 4, MODE_BAD_WIDTH = 5, MODE_NOMODE = 6, MODE_NO_INTERLACE = 7, MODE_NO_DBLESCAN = 8, MODE_NO_VSCAN = 9, MODE_MEM = 10, MODE_VIRTUAL_X = 11, MODE_VIRTUAL_Y = 12, MODE_MEM_VIRT = 13, MODE_NOCLOCK = 14, MODE_CLOCK_HIGH = 15, MODE_CLOCK_LOW = 16, MODE_CLOCK_RANGE = 17, MODE_BAD_HVALUE = 18, MODE_BAD_VVALUE = 19, MODE_BAD_VSCAN = 20, MODE_HSYNC_NARROW = 21, MODE_HSYNC_WIDE = 22, MODE_HBLANK_NARROW = 23, MODE_HBLANK_WIDE = 24, MODE_VSYNC_NARROW = 25, MODE_VSYNC_WIDE = 26, MODE_VBLANK_NARROW = 27, MODE_VBLANK_WIDE = 28, MODE_PANEL = 29, MODE_INTERLACE_WIDTH = 30, MODE_ONE_WIDTH = 31, MODE_ONE_HEIGHT = 32, MODE_ONE_SIZE = 33, MODE_NO_REDUCED = 34, MODE_NO_STEREO = 35, MODE_UNVERIFIED = -3, MODE_BAD = -2, MODE_ERROR = -1 } ; struct drm_display_mode { struct list_head head ; struct drm_mode_object base ; char name[32U] ; enum drm_mode_status status ; unsigned int type ; int clock ; int hdisplay ; int hsync_start ; int hsync_end ; int htotal ; int hskew ; int vdisplay ; int vsync_start ; int vsync_end ; int vtotal ; int vscan ; unsigned int flags ; int width_mm ; int height_mm ; int crtc_clock ; int crtc_hdisplay ; int crtc_hblank_start ; int crtc_hblank_end ; int crtc_hsync_start ; int crtc_hsync_end ; int crtc_htotal ; int crtc_hskew ; int crtc_vdisplay ; int crtc_vblank_start ; int crtc_vblank_end ; int crtc_vsync_start ; int crtc_vsync_end ; int crtc_vtotal ; int *private ; int private_flags ; int vrefresh ; int hsync ; enum hdmi_picture_aspect picture_aspect_ratio ; }; struct drm_cmdline_mode { bool specified ; bool refresh_specified ; bool bpp_specified ; int xres ; int yres ; int bpp ; int refresh ; bool rb ; bool interlace ; bool cvt ; bool margins ; enum drm_connector_force force ; }; enum drm_connector_status { connector_status_connected = 1, connector_status_disconnected = 2, connector_status_unknown = 3 } ; enum subpixel_order { SubPixelUnknown = 0, SubPixelHorizontalRGB = 1, SubPixelHorizontalBGR = 2, SubPixelVerticalRGB = 3, SubPixelVerticalBGR = 4, SubPixelNone = 5 } ; struct drm_display_info { char name[32U] ; unsigned int width_mm ; unsigned int height_mm ; unsigned int min_vfreq ; unsigned int max_vfreq ; unsigned int min_hfreq ; unsigned int max_hfreq ; unsigned int pixel_clock ; unsigned int bpc ; enum subpixel_order subpixel_order ; u32 color_formats ; u32 const *bus_formats ; unsigned int num_bus_formats ; u8 edid_hdmi_dc_modes ; u8 cea_rev ; }; struct drm_tile_group { struct kref refcount ; struct drm_device *dev ; int id ; u8 group_data[8U] ; }; struct drm_framebuffer_funcs { void (*destroy)(struct drm_framebuffer * ) ; int (*create_handle)(struct drm_framebuffer * , struct drm_file * , unsigned int * ) ; int (*dirty)(struct drm_framebuffer * , struct drm_file * , unsigned int , unsigned int , struct drm_clip_rect * , unsigned int ) ; }; struct drm_framebuffer { struct drm_device *dev ; struct kref refcount ; struct list_head head ; struct drm_mode_object base ; struct drm_framebuffer_funcs const *funcs ; unsigned int pitches[4U] ; unsigned int offsets[4U] ; uint64_t modifier[4U] ; unsigned int width ; unsigned int height ; unsigned int depth ; int bits_per_pixel ; int flags ; uint32_t pixel_format ; struct list_head filp_head ; void *helper_private ; }; struct drm_property_blob { struct drm_mode_object base ; struct drm_device *dev ; struct kref refcount ; struct list_head head_global ; struct list_head head_file ; size_t length ; unsigned char data[] ; }; struct drm_property { struct list_head head ; struct drm_mode_object base ; uint32_t flags ; char name[32U] ; uint32_t num_values ; uint64_t *values ; struct drm_device *dev ; struct list_head enum_list ; }; struct drm_pending_vblank_event; struct drm_bridge; struct drm_atomic_state; struct drm_crtc_state { struct drm_crtc *crtc ; bool enable ; bool active ; bool planes_changed ; bool mode_changed ; bool active_changed ; u32 plane_mask ; u32 last_vblank_count ; struct drm_display_mode adjusted_mode ; struct drm_display_mode mode ; struct drm_property_blob *mode_blob ; struct drm_pending_vblank_event *event ; struct drm_atomic_state *state ; }; struct drm_crtc_funcs { void (*save)(struct drm_crtc * ) ; void (*restore)(struct drm_crtc * ) ; void (*reset)(struct drm_crtc * ) ; int (*cursor_set)(struct drm_crtc * , struct drm_file * , uint32_t , uint32_t , uint32_t ) ; int (*cursor_set2)(struct drm_crtc * , struct drm_file * , uint32_t , uint32_t , uint32_t , int32_t , int32_t ) ; int (*cursor_move)(struct drm_crtc * , int , int ) ; void (*gamma_set)(struct drm_crtc * , u16 * , u16 * , u16 * , uint32_t , uint32_t ) ; void (*destroy)(struct drm_crtc * ) ; int (*set_config)(struct drm_mode_set * ) ; int (*page_flip)(struct drm_crtc * , struct drm_framebuffer * , struct drm_pending_vblank_event * , uint32_t ) ; int (*set_property)(struct drm_crtc * , struct drm_property * , uint64_t ) ; struct drm_crtc_state *(*atomic_duplicate_state)(struct drm_crtc * ) ; void (*atomic_destroy_state)(struct drm_crtc * , struct drm_crtc_state * ) ; int (*atomic_set_property)(struct drm_crtc * , struct drm_crtc_state * , struct drm_property * , uint64_t ) ; int (*atomic_get_property)(struct drm_crtc * , struct drm_crtc_state const * , struct drm_property * , uint64_t * ) ; }; struct drm_crtc { struct drm_device *dev ; struct device_node *port ; struct list_head head ; struct drm_modeset_lock mutex ; struct drm_mode_object base ; struct drm_plane *primary ; struct drm_plane *cursor ; int cursor_x ; int cursor_y ; bool enabled ; struct drm_display_mode mode ; struct drm_display_mode hwmode ; bool invert_dimensions ; int x ; int y ; struct drm_crtc_funcs const *funcs ; uint32_t gamma_size ; uint16_t *gamma_store ; int framedur_ns ; int linedur_ns ; int pixeldur_ns ; void const *helper_private ; struct drm_object_properties properties ; struct drm_crtc_state *state ; struct drm_modeset_acquire_ctx *acquire_ctx ; }; struct drm_connector_state { struct drm_connector *connector ; struct drm_crtc *crtc ; struct drm_encoder *best_encoder ; struct drm_atomic_state *state ; }; struct drm_connector_funcs { void (*dpms)(struct drm_connector * , int ) ; void (*save)(struct drm_connector * ) ; void (*restore)(struct drm_connector * ) ; void (*reset)(struct drm_connector * ) ; enum drm_connector_status (*detect)(struct drm_connector * , bool ) ; int (*fill_modes)(struct drm_connector * , uint32_t , uint32_t ) ; int (*set_property)(struct drm_connector * , struct drm_property * , uint64_t ) ; void (*destroy)(struct drm_connector * ) ; void (*force)(struct drm_connector * ) ; struct drm_connector_state *(*atomic_duplicate_state)(struct drm_connector * ) ; void (*atomic_destroy_state)(struct drm_connector * , struct drm_connector_state * ) ; int (*atomic_set_property)(struct drm_connector * , struct drm_connector_state * , struct drm_property * , uint64_t ) ; int (*atomic_get_property)(struct drm_connector * , struct drm_connector_state const * , struct drm_property * , uint64_t * ) ; }; struct drm_encoder_funcs { void (*reset)(struct drm_encoder * ) ; void (*destroy)(struct drm_encoder * ) ; }; struct drm_encoder { struct drm_device *dev ; struct list_head head ; struct drm_mode_object base ; char *name ; int encoder_type ; uint32_t possible_crtcs ; uint32_t possible_clones ; struct drm_crtc *crtc ; struct drm_bridge *bridge ; struct drm_encoder_funcs const *funcs ; void const *helper_private ; }; struct drm_connector { struct drm_device *dev ; struct device *kdev ; struct device_attribute *attr ; struct list_head head ; struct drm_mode_object base ; char *name ; int connector_type ; int connector_type_id ; bool interlace_allowed ; bool doublescan_allowed ; bool stereo_allowed ; struct list_head modes ; enum drm_connector_status status ; struct list_head probed_modes ; struct drm_display_info display_info ; struct drm_connector_funcs const *funcs ; struct drm_property_blob *edid_blob_ptr ; struct drm_object_properties properties ; struct drm_property_blob *path_blob_ptr ; struct drm_property_blob *tile_blob_ptr ; uint8_t polled ; int dpms ; void const *helper_private ; struct drm_cmdline_mode cmdline_mode ; enum drm_connector_force force ; bool override_edid ; uint32_t encoder_ids[3U] ; struct drm_encoder *encoder ; uint8_t eld[128U] ; bool dvi_dual ; int max_tmds_clock ; bool latency_present[2U] ; int video_latency[2U] ; int audio_latency[2U] ; int null_edid_counter ; unsigned int bad_edid_counter ; bool edid_corrupt ; struct dentry *debugfs_entry ; struct drm_connector_state *state ; bool has_tile ; struct drm_tile_group *tile_group ; bool tile_is_single_monitor ; uint8_t num_h_tile ; uint8_t num_v_tile ; uint8_t tile_h_loc ; uint8_t tile_v_loc ; uint16_t tile_h_size ; uint16_t tile_v_size ; struct list_head destroy_list ; }; struct drm_plane_state { struct drm_plane *plane ; struct drm_crtc *crtc ; struct drm_framebuffer *fb ; struct fence *fence ; int32_t crtc_x ; int32_t crtc_y ; uint32_t crtc_w ; uint32_t crtc_h ; uint32_t src_x ; uint32_t src_y ; uint32_t src_h ; uint32_t src_w ; unsigned int rotation ; struct drm_atomic_state *state ; }; struct drm_plane_funcs { int (*update_plane)(struct drm_plane * , struct drm_crtc * , struct drm_framebuffer * , int , int , unsigned int , unsigned int , uint32_t , uint32_t , uint32_t , uint32_t ) ; int (*disable_plane)(struct drm_plane * ) ; void (*destroy)(struct drm_plane * ) ; void (*reset)(struct drm_plane * ) ; int (*set_property)(struct drm_plane * , struct drm_property * , uint64_t ) ; struct drm_plane_state *(*atomic_duplicate_state)(struct drm_plane * ) ; void (*atomic_destroy_state)(struct drm_plane * , struct drm_plane_state * ) ; int (*atomic_set_property)(struct drm_plane * , struct drm_plane_state * , struct drm_property * , uint64_t ) ; int (*atomic_get_property)(struct drm_plane * , struct drm_plane_state const * , struct drm_property * , uint64_t * ) ; }; enum drm_plane_type { DRM_PLANE_TYPE_OVERLAY = 0, DRM_PLANE_TYPE_PRIMARY = 1, DRM_PLANE_TYPE_CURSOR = 2 } ; struct drm_plane { struct drm_device *dev ; struct list_head head ; struct drm_modeset_lock mutex ; struct drm_mode_object base ; uint32_t possible_crtcs ; uint32_t *format_types ; uint32_t format_count ; bool format_default ; struct drm_crtc *crtc ; struct drm_framebuffer *fb ; struct drm_framebuffer *old_fb ; struct drm_plane_funcs const *funcs ; struct drm_object_properties properties ; enum drm_plane_type type ; void const *helper_private ; struct drm_plane_state *state ; }; struct drm_bridge_funcs { int (*attach)(struct drm_bridge * ) ; bool (*mode_fixup)(struct drm_bridge * , struct drm_display_mode const * , struct drm_display_mode * ) ; void (*disable)(struct drm_bridge * ) ; void (*post_disable)(struct drm_bridge * ) ; void (*mode_set)(struct drm_bridge * , struct drm_display_mode * , struct drm_display_mode * ) ; void (*pre_enable)(struct drm_bridge * ) ; void (*enable)(struct drm_bridge * ) ; }; struct drm_bridge { struct drm_device *dev ; struct drm_encoder *encoder ; struct drm_bridge *next ; struct device_node *of_node ; struct list_head list ; struct drm_bridge_funcs const *funcs ; void *driver_private ; }; struct drm_atomic_state { struct drm_device *dev ; bool allow_modeset ; bool legacy_cursor_update ; struct drm_plane **planes ; struct drm_plane_state **plane_states ; struct drm_crtc **crtcs ; struct drm_crtc_state **crtc_states ; int num_connector ; struct drm_connector **connectors ; struct drm_connector_state **connector_states ; struct drm_modeset_acquire_ctx *acquire_ctx ; }; struct drm_mode_set { struct drm_framebuffer *fb ; struct drm_crtc *crtc ; struct drm_display_mode *mode ; uint32_t x ; uint32_t y ; struct drm_connector **connectors ; size_t num_connectors ; }; struct drm_mode_config_funcs { struct drm_framebuffer *(*fb_create)(struct drm_device * , struct drm_file * , struct drm_mode_fb_cmd2 * ) ; void (*output_poll_changed)(struct drm_device * ) ; int (*atomic_check)(struct drm_device * , struct drm_atomic_state * ) ; int (*atomic_commit)(struct drm_device * , struct drm_atomic_state * , bool ) ; struct drm_atomic_state *(*atomic_state_alloc)(struct drm_device * ) ; void (*atomic_state_clear)(struct drm_atomic_state * ) ; void (*atomic_state_free)(struct drm_atomic_state * ) ; }; struct drm_mode_group { uint32_t num_crtcs ; uint32_t num_encoders ; uint32_t num_connectors ; uint32_t *id_list ; }; struct drm_mode_config { struct mutex mutex ; struct drm_modeset_lock connection_mutex ; struct drm_modeset_acquire_ctx *acquire_ctx ; struct mutex idr_mutex ; struct idr crtc_idr ; struct idr tile_idr ; struct mutex fb_lock ; int num_fb ; struct list_head fb_list ; int num_connector ; struct list_head connector_list ; int num_encoder ; struct list_head encoder_list ; int num_overlay_plane ; int num_total_plane ; struct list_head plane_list ; int num_crtc ; struct list_head crtc_list ; struct list_head property_list ; int min_width ; int min_height ; int max_width ; int max_height ; struct drm_mode_config_funcs const *funcs ; resource_size_t fb_base ; bool poll_enabled ; bool poll_running ; bool delayed_event ; struct delayed_work output_poll_work ; struct mutex blob_lock ; struct list_head property_blob_list ; struct drm_property *edid_property ; struct drm_property *dpms_property ; struct drm_property *path_property ; struct drm_property *tile_property ; struct drm_property *plane_type_property ; struct drm_property *rotation_property ; struct drm_property *prop_src_x ; struct drm_property *prop_src_y ; struct drm_property *prop_src_w ; struct drm_property *prop_src_h ; struct drm_property *prop_crtc_x ; struct drm_property *prop_crtc_y ; struct drm_property *prop_crtc_w ; struct drm_property *prop_crtc_h ; struct drm_property *prop_fb_id ; struct drm_property *prop_crtc_id ; struct drm_property *prop_active ; struct drm_property *prop_mode_id ; struct drm_property *dvi_i_subconnector_property ; struct drm_property *dvi_i_select_subconnector_property ; struct drm_property *tv_subconnector_property ; struct drm_property *tv_select_subconnector_property ; struct drm_property *tv_mode_property ; struct drm_property *tv_left_margin_property ; struct drm_property *tv_right_margin_property ; struct drm_property *tv_top_margin_property ; struct drm_property *tv_bottom_margin_property ; struct drm_property *tv_brightness_property ; struct drm_property *tv_contrast_property ; struct drm_property *tv_flicker_reduction_property ; struct drm_property *tv_overscan_property ; struct drm_property *tv_saturation_property ; struct drm_property *tv_hue_property ; struct drm_property *scaling_mode_property ; struct drm_property *aspect_ratio_property ; struct drm_property *dirty_info_property ; struct drm_property *suggested_x_property ; struct drm_property *suggested_y_property ; uint32_t preferred_depth ; uint32_t prefer_shadow ; bool async_page_flip ; bool allow_fb_modifiers ; uint32_t cursor_width ; uint32_t cursor_height ; }; struct drm_open_hash { struct hlist_head *table ; u8 order ; }; struct drm_mm; struct drm_mm_node { struct list_head node_list ; struct list_head hole_stack ; unsigned char hole_follows : 1 ; unsigned char scanned_block : 1 ; unsigned char scanned_prev_free : 1 ; unsigned char scanned_next_free : 1 ; unsigned char scanned_preceeds_hole : 1 ; unsigned char allocated : 1 ; unsigned long color ; u64 start ; u64 size ; struct drm_mm *mm ; }; struct drm_mm { struct list_head hole_stack ; struct drm_mm_node head_node ; unsigned char scan_check_range : 1 ; unsigned int scan_alignment ; unsigned long scan_color ; u64 scan_size ; u64 scan_hit_start ; u64 scan_hit_end ; unsigned int scanned_blocks ; u64 scan_start ; u64 scan_end ; struct drm_mm_node *prev_scanned_node ; void (*color_adjust)(struct drm_mm_node * , unsigned long , u64 * , u64 * ) ; }; struct drm_vma_offset_node { rwlock_t vm_lock ; struct drm_mm_node vm_node ; struct rb_node vm_rb ; struct rb_root vm_files ; }; struct drm_vma_offset_manager { rwlock_t vm_lock ; struct rb_root vm_addr_space_rb ; struct drm_mm vm_addr_space_mm ; }; struct drm_local_map; struct drm_device_dma; struct drm_gem_object; struct reservation_object; struct dma_buf_attachment; typedef int drm_ioctl_t(struct drm_device * , void * , struct drm_file * ); struct drm_ioctl_desc { unsigned int cmd ; int flags ; drm_ioctl_t *func ; char const *name ; }; struct drm_pending_event { struct drm_event *event ; struct list_head link ; struct drm_file *file_priv ; pid_t pid ; void (*destroy)(struct drm_pending_event * ) ; }; struct drm_prime_file_private { struct list_head head ; struct mutex lock ; }; struct drm_minor; struct drm_master; struct drm_file { unsigned char authenticated : 1 ; unsigned char is_master : 1 ; unsigned char stereo_allowed : 1 ; unsigned char universal_planes : 1 ; unsigned char atomic : 1 ; struct pid *pid ; kuid_t uid ; drm_magic_t magic ; struct list_head lhead ; struct drm_minor *minor ; unsigned long lock_count ; struct idr object_idr ; spinlock_t table_lock ; struct file *filp ; void *driver_priv ; struct drm_master *master ; struct list_head fbs ; struct mutex fbs_lock ; struct list_head blobs ; wait_queue_head_t event_wait ; struct list_head event_list ; int event_space ; struct drm_prime_file_private prime ; }; struct drm_lock_data { struct drm_hw_lock *hw_lock ; struct drm_file *file_priv ; wait_queue_head_t lock_queue ; unsigned long lock_time ; spinlock_t spinlock ; uint32_t kernel_waiters ; uint32_t user_waiters ; int idle_has_lock ; }; struct drm_master { struct kref refcount ; struct drm_minor *minor ; char *unique ; int unique_len ; struct idr magic_map ; struct drm_lock_data lock ; void *driver_priv ; }; struct dma_buf; struct drm_driver { int (*load)(struct drm_device * , unsigned long ) ; int (*firstopen)(struct drm_device * ) ; int (*open)(struct drm_device * , struct drm_file * ) ; void (*preclose)(struct drm_device * , struct drm_file * ) ; void (*postclose)(struct drm_device * , struct drm_file * ) ; void (*lastclose)(struct drm_device * ) ; int (*unload)(struct drm_device * ) ; int (*suspend)(struct drm_device * , pm_message_t ) ; int (*resume)(struct drm_device * ) ; int (*dma_ioctl)(struct drm_device * , void * , struct drm_file * ) ; int (*dma_quiescent)(struct drm_device * ) ; int (*context_dtor)(struct drm_device * , int ) ; int (*set_busid)(struct drm_device * , struct drm_master * ) ; u32 (*get_vblank_counter)(struct drm_device * , int ) ; int (*enable_vblank)(struct drm_device * , int ) ; void (*disable_vblank)(struct drm_device * , int ) ; int (*device_is_agp)(struct drm_device * ) ; int (*get_scanout_position)(struct drm_device * , int , unsigned int , int * , int * , ktime_t * , ktime_t * ) ; int (*get_vblank_timestamp)(struct drm_device * , int , int * , struct timeval * , unsigned int ) ; irqreturn_t (*irq_handler)(int , void * ) ; void (*irq_preinstall)(struct drm_device * ) ; int (*irq_postinstall)(struct drm_device * ) ; void (*irq_uninstall)(struct drm_device * ) ; int (*master_create)(struct drm_device * , struct drm_master * ) ; void (*master_destroy)(struct drm_device * , struct drm_master * ) ; int (*master_set)(struct drm_device * , struct drm_file * , bool ) ; void (*master_drop)(struct drm_device * , struct drm_file * , bool ) ; int (*debugfs_init)(struct drm_minor * ) ; void (*debugfs_cleanup)(struct drm_minor * ) ; void (*gem_free_object)(struct drm_gem_object * ) ; int (*gem_open_object)(struct drm_gem_object * , struct drm_file * ) ; void (*gem_close_object)(struct drm_gem_object * , struct drm_file * ) ; int (*prime_handle_to_fd)(struct drm_device * , struct drm_file * , uint32_t , uint32_t , int * ) ; int (*prime_fd_to_handle)(struct drm_device * , struct drm_file * , int , uint32_t * ) ; struct dma_buf *(*gem_prime_export)(struct drm_device * , struct drm_gem_object * , int ) ; struct drm_gem_object *(*gem_prime_import)(struct drm_device * , struct dma_buf * ) ; int (*gem_prime_pin)(struct drm_gem_object * ) ; void (*gem_prime_unpin)(struct drm_gem_object * ) ; struct reservation_object *(*gem_prime_res_obj)(struct drm_gem_object * ) ; struct sg_table *(*gem_prime_get_sg_table)(struct drm_gem_object * ) ; struct drm_gem_object *(*gem_prime_import_sg_table)(struct drm_device * , struct dma_buf_attachment * , struct sg_table * ) ; void *(*gem_prime_vmap)(struct drm_gem_object * ) ; void (*gem_prime_vunmap)(struct drm_gem_object * , void * ) ; int (*gem_prime_mmap)(struct drm_gem_object * , struct vm_area_struct * ) ; void (*vgaarb_irq)(struct drm_device * , bool ) ; int (*dumb_create)(struct drm_file * , struct drm_device * , struct drm_mode_create_dumb * ) ; int (*dumb_map_offset)(struct drm_file * , struct drm_device * , uint32_t , uint64_t * ) ; int (*dumb_destroy)(struct drm_file * , struct drm_device * , uint32_t ) ; struct vm_operations_struct const *gem_vm_ops ; int major ; int minor ; int patchlevel ; char *name ; char *desc ; char *date ; u32 driver_features ; int dev_priv_size ; struct drm_ioctl_desc const *ioctls ; int num_ioctls ; struct file_operations const *fops ; struct list_head legacy_dev_list ; }; struct drm_minor { int index ; int type ; struct device *kdev ; struct drm_device *dev ; struct dentry *debugfs_root ; struct list_head debugfs_list ; struct mutex debugfs_lock ; struct drm_master *master ; struct drm_mode_group mode_group ; }; struct drm_pending_vblank_event { struct drm_pending_event base ; int pipe ; struct drm_event_vblank event ; }; struct drm_vblank_crtc { struct drm_device *dev ; wait_queue_head_t queue ; struct timer_list disable_timer ; unsigned long count ; struct timeval time[2U] ; atomic_t refcount ; u32 last ; u32 last_wait ; unsigned int inmodeset ; int crtc ; bool enabled ; }; struct virtio_device; struct drm_sg_mem; struct __anonstruct_sigdata_258 { int context ; struct drm_hw_lock *lock ; }; struct drm_device { struct list_head legacy_dev_list ; int if_version ; struct kref ref ; struct device *dev ; struct drm_driver *driver ; void *dev_private ; struct drm_minor *control ; struct drm_minor *primary ; struct drm_minor *render ; atomic_t unplugged ; struct inode *anon_inode ; char *unique ; struct mutex struct_mutex ; struct mutex master_mutex ; int open_count ; spinlock_t buf_lock ; int buf_use ; atomic_t buf_alloc ; struct list_head filelist ; struct list_head maplist ; struct drm_open_hash map_hash ; struct list_head ctxlist ; struct mutex ctxlist_mutex ; struct idr ctx_idr ; struct list_head vmalist ; struct drm_device_dma *dma ; long volatile context_flag ; int last_context ; bool irq_enabled ; int irq ; bool vblank_disable_allowed ; bool vblank_disable_immediate ; struct drm_vblank_crtc *vblank ; spinlock_t vblank_time_lock ; spinlock_t vbl_lock ; u32 max_vblank_count ; struct list_head vblank_event_list ; spinlock_t event_lock ; struct drm_agp_head *agp ; struct pci_dev *pdev ; struct platform_device *platformdev ; struct virtio_device *virtdev ; struct drm_sg_mem *sg ; unsigned int num_crtcs ; sigset_t sigmask ; struct __anonstruct_sigdata_258 sigdata ; struct drm_local_map *agp_buffer_map ; unsigned int agp_buffer_token ; struct drm_mode_config mode_config ; struct mutex object_name_lock ; struct idr object_name_idr ; struct drm_vma_offset_manager *vma_offset_manager ; int switch_power_state ; }; struct i2c_algo_bit_data { void *data ; void (*setsda)(void * , int ) ; void (*setscl)(void * , int ) ; int (*getsda)(void * ) ; int (*getscl)(void * ) ; int (*pre_xfer)(struct i2c_adapter * ) ; void (*post_xfer)(struct i2c_adapter * ) ; int udelay ; int timeout ; }; enum mode_set_atomic { LEAVE_ATOMIC_MODE_SET = 0, ENTER_ATOMIC_MODE_SET = 1 } ; struct drm_crtc_helper_funcs { void (*dpms)(struct drm_crtc * , int ) ; void (*prepare)(struct drm_crtc * ) ; void (*commit)(struct drm_crtc * ) ; bool (*mode_fixup)(struct drm_crtc * , struct drm_display_mode const * , struct drm_display_mode * ) ; int (*mode_set)(struct drm_crtc * , struct drm_display_mode * , struct drm_display_mode * , int , int , struct drm_framebuffer * ) ; void (*mode_set_nofb)(struct drm_crtc * ) ; int (*mode_set_base)(struct drm_crtc * , int , int , struct drm_framebuffer * ) ; int (*mode_set_base_atomic)(struct drm_crtc * , struct drm_framebuffer * , int , int , enum mode_set_atomic ) ; void (*load_lut)(struct drm_crtc * ) ; void (*disable)(struct drm_crtc * ) ; void (*enable)(struct drm_crtc * ) ; int (*atomic_check)(struct drm_crtc * , struct drm_crtc_state * ) ; void (*atomic_begin)(struct drm_crtc * ) ; void (*atomic_flush)(struct drm_crtc * ) ; }; struct gma_clock_t { int n ; int m1 ; int m2 ; int p1 ; int p2 ; int dot ; int vco ; int m ; int p ; }; struct gma_range_t { int min ; int max ; }; struct gma_p2_t { int dot_limit ; int p2_slow ; int p2_fast ; }; struct gma_limit_t { struct gma_range_t dot ; struct gma_range_t vco ; struct gma_range_t n ; struct gma_range_t m ; struct gma_range_t m1 ; struct gma_range_t m2 ; struct gma_range_t p ; struct gma_range_t p1 ; struct gma_p2_t p2 ; bool (*find_pll)(struct gma_limit_t const * , struct drm_crtc * , int , int , struct gma_clock_t * ) ; }; struct gma_clock_funcs { void (*clock)(int , struct gma_clock_t * ) ; struct gma_limit_t const *(*limit)(struct drm_crtc * , int ) ; bool (*pll_is_valid)(struct drm_crtc * , struct gma_limit_t const * , struct gma_clock_t * ) ; }; struct psb_intel_mode_device { size_t (*bo_offset)(struct drm_device * , void * ) ; int backlight_duty_cycle ; bool panel_wants_dither ; struct drm_display_mode *panel_fixed_mode ; struct drm_display_mode *panel_fixed_mode2 ; struct drm_display_mode *vbt_mode ; uint32_t saveBLC_PWM_CTL ; }; struct psb_intel_i2c_chan { struct drm_device *drm_dev ; u32 reg ; struct i2c_adapter adapter ; struct i2c_algo_bit_data algo ; u8 slave_addr ; }; struct gtt_range; struct child_device_config { u16 handle ; u16 device_type ; u8 device_id[10U] ; u16 addin_offset ; u8 dvo_port ; u8 i2c_pin ; u8 slave_addr ; u8 ddc_pin ; u16 edid_ptr ; u8 dvo_cfg ; u8 dvo2_port ; u8 i2c2_pin ; u8 slave2_addr ; u8 ddc2_pin ; u8 capabilities ; u8 dvo_wiring ; u8 dvo2_wiring ; u16 extended_type ; u8 dvo_function ; }; struct bdb_lvds_backlight { unsigned char type : 2 ; unsigned char pol : 1 ; unsigned char gpio : 3 ; unsigned char gmbus : 2 ; u16 freq ; u8 minbrightness ; u8 i2caddr ; u8 brightnesscmd ; }; struct edp_power_seq { u16 t1_t3 ; u16 t8 ; u16 t9 ; u16 t10 ; u16 t11_t12 ; }; struct drm_gem_object { struct kref refcount ; unsigned int handle_count ; struct drm_device *dev ; struct file *filp ; struct drm_vma_offset_node vma_node ; size_t size ; int name ; uint32_t read_domains ; uint32_t write_domain ; uint32_t pending_read_domains ; uint32_t pending_write_domain ; struct dma_buf *dma_buf ; struct dma_buf_attachment *import_attach ; }; struct psb_gtt { uint32_t gatt_start ; uint32_t mmu_gatt_start ; uint32_t gtt_start ; uint32_t gtt_phys_start ; unsigned int gtt_pages ; unsigned int gatt_pages ; unsigned long stolen_size ; unsigned long vram_stolen_size ; struct rw_semaphore sem ; }; struct gtt_range { struct resource resource ; u32 offset ; struct drm_gem_object gem ; int in_gart ; bool stolen ; bool mmapping ; struct page **pages ; int npage ; int roll ; }; struct oaktrail_timing_info { u16 pixel_clock ; u8 hactive_lo ; u8 hblank_lo ; unsigned char hblank_hi : 4 ; unsigned char hactive_hi : 4 ; u8 vactive_lo ; u8 vblank_lo ; unsigned char vblank_hi : 4 ; unsigned char vactive_hi : 4 ; u8 hsync_offset_lo ; u8 hsync_pulse_width_lo ; unsigned char vsync_pulse_width_lo : 4 ; unsigned char vsync_offset_lo : 4 ; unsigned char vsync_pulse_width_hi : 2 ; unsigned char vsync_offset_hi : 2 ; unsigned char hsync_pulse_width_hi : 2 ; unsigned char hsync_offset_hi : 2 ; u8 width_mm_lo ; u8 height_mm_lo ; unsigned char height_mm_hi : 4 ; unsigned char width_mm_hi : 4 ; u8 hborder ; u8 vborder ; unsigned char unknown0 : 1 ; unsigned char hsync_positive : 1 ; unsigned char vsync_positive : 1 ; unsigned char separate_sync : 2 ; unsigned char stereo : 1 ; unsigned char unknown6 : 1 ; unsigned char interlaced : 1 ; }; struct oaktrail_gct_data { u8 bpi ; u8 pt ; struct oaktrail_timing_info DTD ; u32 Panel_Port_Control ; u32 PP_On_Sequencing ; u32 PP_Off_Sequencing ; u32 PP_Cycle_Delay ; u16 Panel_Backlight_Inverter_Descriptor ; u16 Panel_MIPI_Display_Descriptor ; }; struct hdmi_i2c_dev; struct oaktrail_hdmi_dev { struct pci_dev *dev ; void *regs ; unsigned int mmio ; unsigned int mmio_len ; int dpms_mode ; struct hdmi_i2c_dev *i2c_dev ; u32 saveDPLL_CTRL ; u32 saveDPLL_DIV_CTRL ; u32 saveDPLL_ADJUST ; u32 saveDPLL_UPDATE ; u32 saveDPLL_CLK_ENABLE ; u32 savePCH_HTOTAL_B ; u32 savePCH_HBLANK_B ; u32 savePCH_HSYNC_B ; u32 savePCH_VTOTAL_B ; u32 savePCH_VBLANK_B ; u32 savePCH_VSYNC_B ; u32 savePCH_PIPEBCONF ; u32 savePCH_PIPEBSRC ; }; struct psb_mmu_pd; struct psb_mmu_driver { struct rw_semaphore sem ; spinlock_t lock ; atomic_t needs_tlbflush ; atomic_t *msvdx_mmu_invaldc ; struct psb_mmu_pd *default_pd ; uint32_t bif_ctrl ; int has_clflush ; int clflush_add ; unsigned long clflush_mask ; struct drm_device *dev ; }; struct psb_mmu_pt { struct psb_mmu_pd *pd ; uint32_t index ; uint32_t count ; struct page *p ; uint32_t *v ; }; struct psb_mmu_pd { struct psb_mmu_driver *driver ; int hw_context ; struct psb_mmu_pt **tables ; struct page *p ; struct page *dummy_pt ; struct page *dummy_page ; uint32_t pd_mask ; uint32_t invalid_pde ; uint32_t invalid_pte ; }; struct opregion_header; struct opregion_acpi; struct opregion_swsci; struct opregion_asle; struct psb_intel_opregion { struct opregion_header *header ; struct opregion_acpi *acpi ; struct opregion_swsci *swsci ; struct opregion_asle *asle ; void *vbt ; u32 *lid_state ; struct work_struct asle_work ; }; struct sdvo_device_mapping { u8 initialized ; u8 dvo_port ; u8 slave_addr ; u8 dvo_wiring ; u8 i2c_pin ; u8 i2c_speed ; u8 ddc_pin ; }; struct intel_gmbus { struct i2c_adapter adapter ; struct i2c_adapter *force_bit ; u32 reg0 ; }; struct psb_offset { u32 fp0 ; u32 fp1 ; u32 cntr ; u32 conf ; u32 src ; u32 dpll ; u32 dpll_md ; u32 htotal ; u32 hblank ; u32 hsync ; u32 vtotal ; u32 vblank ; u32 vsync ; u32 stride ; u32 size ; u32 pos ; u32 surf ; u32 addr ; u32 base ; u32 status ; u32 linoff ; u32 tileoff ; u32 palette ; }; struct psb_pipe { u32 fp0 ; u32 fp1 ; u32 cntr ; u32 conf ; u32 src ; u32 dpll ; u32 dpll_md ; u32 htotal ; u32 hblank ; u32 hsync ; u32 vtotal ; u32 vblank ; u32 vsync ; u32 stride ; u32 size ; u32 pos ; u32 base ; u32 surf ; u32 addr ; u32 status ; u32 linoff ; u32 tileoff ; u32 palette[256U] ; }; struct psb_state { uint32_t saveVCLK_DIVISOR_VGA0 ; uint32_t saveVCLK_DIVISOR_VGA1 ; uint32_t saveVCLK_POST_DIV ; uint32_t saveVGACNTRL ; uint32_t saveADPA ; uint32_t saveLVDS ; uint32_t saveDVOA ; uint32_t saveDVOB ; uint32_t saveDVOC ; uint32_t savePP_ON ; uint32_t savePP_OFF ; uint32_t savePP_CONTROL ; uint32_t savePP_CYCLE ; uint32_t savePFIT_CONTROL ; uint32_t saveCLOCKGATING ; uint32_t saveDSPARB ; uint32_t savePFIT_AUTO_RATIOS ; uint32_t savePFIT_PGM_RATIOS ; uint32_t savePP_ON_DELAYS ; uint32_t savePP_OFF_DELAYS ; uint32_t savePP_DIVISOR ; uint32_t saveBCLRPAT_A ; uint32_t saveBCLRPAT_B ; uint32_t savePERF_MODE ; uint32_t saveDSPFW1 ; uint32_t saveDSPFW2 ; uint32_t saveDSPFW3 ; uint32_t saveDSPFW4 ; uint32_t saveDSPFW5 ; uint32_t saveDSPFW6 ; uint32_t saveCHICKENBIT ; uint32_t saveDSPACURSOR_CTRL ; uint32_t saveDSPBCURSOR_CTRL ; uint32_t saveDSPACURSOR_BASE ; uint32_t saveDSPBCURSOR_BASE ; uint32_t saveDSPACURSOR_POS ; uint32_t saveDSPBCURSOR_POS ; uint32_t saveOV_OVADD ; uint32_t saveOV_OGAMC0 ; uint32_t saveOV_OGAMC1 ; uint32_t saveOV_OGAMC2 ; uint32_t saveOV_OGAMC3 ; uint32_t saveOV_OGAMC4 ; uint32_t saveOV_OGAMC5 ; uint32_t saveOVC_OVADD ; uint32_t saveOVC_OGAMC0 ; uint32_t saveOVC_OGAMC1 ; uint32_t saveOVC_OGAMC2 ; uint32_t saveOVC_OGAMC3 ; uint32_t saveOVC_OGAMC4 ; uint32_t saveOVC_OGAMC5 ; uint32_t saveHISTOGRAM_INT_CONTROL_REG ; uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG ; uint32_t savePWM_CONTROL_LOGIC ; }; struct medfield_state { uint32_t saveMIPI ; uint32_t saveMIPI_C ; uint32_t savePFIT_CONTROL ; uint32_t savePFIT_PGM_RATIOS ; uint32_t saveHDMIPHYMISCCTL ; uint32_t saveHDMIB_CONTROL ; }; struct cdv_state { uint32_t saveDSPCLK_GATE_D ; uint32_t saveRAMCLK_GATE_D ; uint32_t saveDSPARB ; uint32_t saveDSPFW[6U] ; uint32_t saveADPA ; uint32_t savePP_CONTROL ; uint32_t savePFIT_PGM_RATIOS ; uint32_t saveLVDS ; uint32_t savePFIT_CONTROL ; uint32_t savePP_ON_DELAYS ; uint32_t savePP_OFF_DELAYS ; uint32_t savePP_CYCLE ; uint32_t saveVGACNTRL ; uint32_t saveIER ; uint32_t saveIMR ; u8 saveLBB ; }; union __anonunion____missing_field_name_264 { struct psb_state psb ; struct medfield_state mdfld ; struct cdv_state cdv ; }; struct psb_save_area { struct psb_pipe pipe[3U] ; uint32_t saveBSM ; uint32_t saveVBT ; union __anonunion____missing_field_name_264 __annonCompField80 ; uint32_t saveBLC_PWM_CTL2 ; uint32_t saveBLC_PWM_CTL ; }; struct psb_ops; struct psb_gtt_mm; struct __anonstruct_edp_265 { int rate ; int lanes ; int preemphasis ; int vswing ; bool initialized ; bool support ; int bpp ; struct edp_power_seq pps ; }; struct drm_psb_private { struct drm_device *dev ; struct pci_dev *aux_pdev ; struct pci_dev *lpc_pdev ; struct psb_ops const *ops ; struct psb_offset const *regmap ; struct child_device_config *child_dev ; int child_dev_num ; struct psb_gtt gtt ; struct psb_gtt_mm *gtt_mm ; struct page *scratch_page ; u32 *gtt_map ; uint32_t stolen_base ; u8 *vram_addr ; unsigned long vram_stolen_size ; int gtt_initialized ; u16 gmch_ctrl ; u32 pge_ctl ; struct mutex gtt_mutex ; struct resource *gtt_mem ; struct psb_mmu_driver *mmu ; struct psb_mmu_pd *pf_pd ; uint8_t *sgx_reg ; uint8_t *vdc_reg ; uint8_t *aux_reg ; uint16_t lpc_gpio_base ; uint32_t gatt_free_offset ; uint32_t vdc_irq_mask ; uint32_t pipestat[3U] ; spinlock_t irqmask_lock ; bool suspended ; bool display_power ; int display_count ; struct psb_intel_mode_device mode_dev ; bool modeset ; struct drm_crtc *plane_to_crtc_mapping[3U] ; struct drm_crtc *pipe_to_crtc_mapping[3U] ; uint32_t num_pipe ; uint32_t ospm_base ; u32 fuse_reg_value ; u32 video_device_fuse ; uint8_t platform_rev_id ; struct intel_gmbus *gmbus ; uint8_t *gmbus_reg ; int crt_ddc_pin ; struct sdvo_device_mapping sdvo_mappings[2U] ; u32 hotplug_supported_mask ; struct drm_property *broadcast_rgb_property ; struct drm_property *force_audio_property ; int backlight_duty_cycle ; bool panel_wants_dither ; struct drm_display_mode *panel_fixed_mode ; struct drm_display_mode *lfp_lvds_vbt_mode ; struct drm_display_mode *sdvo_lvds_vbt_mode ; struct bdb_lvds_backlight *lvds_bl ; struct psb_intel_i2c_chan *lvds_i2c_bus ; unsigned char int_tv_support : 1 ; unsigned char lvds_dither : 1 ; unsigned char lvds_vbt : 1 ; unsigned char int_crt_support : 1 ; unsigned char lvds_use_ssc : 1 ; int lvds_ssc_freq ; bool is_lvds_on ; bool is_mipi_on ; u32 mipi_ctrl_display ; unsigned int core_freq ; uint32_t iLVDS_enable ; int rpm_enabled ; bool has_gct ; struct oaktrail_gct_data gct_data ; struct oaktrail_hdmi_dev *hdmi_priv ; struct psb_save_area regs ; uint32_t msi_addr ; uint32_t msi_data ; struct work_struct hotplug_work ; spinlock_t lid_lock ; struct timer_list lid_timer ; struct psb_intel_opregion opregion ; u32 lid_last_state ; uint32_t apm_reg ; uint16_t apm_base ; struct backlight_device *backlight_device ; struct drm_property *backlight_property ; bool backlight_enabled ; int backlight_level ; uint32_t blc_adj1 ; uint32_t blc_adj2 ; void *fbdev ; spinlock_t lock_2d ; int brightness ; int brightness_adjusted ; bool dsr_enable ; u32 dsr_fb_update ; bool dpi_panel_on[3U] ; void *dsi_configs[2U] ; u32 bpp ; u32 bpp2 ; u32 pipeconf[3U] ; u32 dspcntr[3U] ; int mdfld_panel_id ; bool dplla_96mhz ; struct __anonstruct_edp_265 edp ; uint8_t panel_type ; }; struct psb_ops { char const *name ; unsigned char accel_2d : 1 ; int pipes ; int crtcs ; int sgx_offset ; int hdmi_mask ; int lvds_mask ; int sdvo_mask ; int cursor_needs_phys ; struct drm_crtc_helper_funcs const *crtc_helper ; struct drm_crtc_funcs const *crtc_funcs ; struct gma_clock_funcs const *clock_funcs ; int (*chip_setup)(struct drm_device * ) ; void (*chip_teardown)(struct drm_device * ) ; void (*errata)(struct drm_device * ) ; int (*output_init)(struct drm_device * ) ; int (*hotplug)(struct drm_device * ) ; void (*hotplug_enable)(struct drm_device * , bool ) ; void (*init_pm)(struct drm_device * ) ; int (*save_regs)(struct drm_device * ) ; int (*restore_regs)(struct drm_device * ) ; int (*power_up)(struct drm_device * ) ; int (*power_down)(struct drm_device * ) ; void (*update_wm)(struct drm_device * , struct drm_crtc * ) ; void (*disable_sr)(struct drm_device * ) ; void (*lvds_bl_power)(struct drm_device * , bool ) ; int i2c_bus ; }; struct drm_fb_helper; struct drm_fb_offset { int x ; int y ; }; struct drm_fb_helper_crtc { struct drm_mode_set mode_set ; struct drm_display_mode *desired_mode ; int x ; int y ; }; struct drm_fb_helper_surface_size { u32 fb_width ; u32 fb_height ; u32 surface_width ; u32 surface_height ; u32 surface_bpp ; u32 surface_depth ; }; struct drm_fb_helper_funcs { void (*gamma_set)(struct drm_crtc * , u16 , u16 , u16 , int ) ; void (*gamma_get)(struct drm_crtc * , u16 * , u16 * , u16 * , int ) ; int (*fb_probe)(struct drm_fb_helper * , struct drm_fb_helper_surface_size * ) ; bool (*initial_config)(struct drm_fb_helper * , struct drm_fb_helper_crtc ** , struct drm_display_mode ** , struct drm_fb_offset * , bool * , int , int ) ; }; struct drm_fb_helper_connector { struct drm_connector *connector ; }; struct drm_fb_helper { struct drm_framebuffer *fb ; struct drm_device *dev ; int crtc_count ; struct drm_fb_helper_crtc *crtc_info ; int connector_count ; int connector_info_alloc_count ; struct drm_fb_helper_connector **connector_info ; struct drm_fb_helper_funcs const *funcs ; struct fb_info *fbdev ; u32 pseudo_palette[17U] ; struct list_head kernel_fb_list ; bool delayed_hotplug ; }; struct psb_framebuffer { struct drm_framebuffer base ; struct address_space *addr_space ; struct fb_info *fbdev ; struct gtt_range *gtt ; }; struct psb_fbdev { struct drm_fb_helper psb_fb_helper ; struct psb_framebuffer pfb ; }; typedef bool ldv_func_ret_type; typedef bool ldv_func_ret_type___0; typedef bool ldv_func_ret_type___1; typedef bool ldv_func_ret_type___2; enum hrtimer_restart; enum page_cache_mode { _PAGE_CACHE_MODE_WB = 0, _PAGE_CACHE_MODE_WC = 1, _PAGE_CACHE_MODE_UC_MINUS = 2, _PAGE_CACHE_MODE_UC = 3, _PAGE_CACHE_MODE_WT = 4, _PAGE_CACHE_MODE_WP = 5, _PAGE_CACHE_MODE_NUM = 8 } ; struct cpuinfo_x86; struct _ddebug { char const *modname ; char const *function ; char const *filename ; char const *format ; unsigned int lineno : 18 ; unsigned char flags ; }; struct cpuinfo_x86 { __u8 x86 ; __u8 x86_vendor ; __u8 x86_model ; __u8 x86_mask ; int x86_tlbsize ; __u8 x86_virt_bits ; __u8 x86_phys_bits ; __u8 x86_coreid_bits ; __u32 extended_cpuid_level ; int cpuid_level ; __u32 x86_capability[14U] ; char x86_vendor_id[16U] ; char x86_model_id[64U] ; int x86_cache_size ; int x86_cache_alignment ; int x86_cache_max_rmid ; int x86_cache_occ_scale ; int x86_power ; unsigned long loops_per_jiffy ; u16 x86_max_cores ; u16 apicid ; u16 initial_apicid ; u16 x86_clflush_size ; u16 booted_cores ; u16 phys_proc_id ; u16 cpu_core_id ; u8 compute_unit_id ; u16 cpu_index ; u32 microcode ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct gma_encoder { struct drm_encoder base ; int type ; bool needs_tv_clock ; void (*hot_plug)(struct gma_encoder * ) ; int crtc_mask ; int clone_mask ; u32 ddi_select ; void *dev_priv ; struct psb_intel_i2c_chan *i2c_bus ; struct psb_intel_i2c_chan *ddc_bus ; }; struct gma_connector { struct drm_connector base ; struct gma_encoder *encoder ; }; struct psb_intel_crtc_state { uint32_t saveDSPCNTR ; uint32_t savePIPECONF ; uint32_t savePIPESRC ; uint32_t saveDPLL ; uint32_t saveFP0 ; uint32_t saveFP1 ; uint32_t saveHTOTAL ; uint32_t saveHBLANK ; uint32_t saveHSYNC ; uint32_t saveVTOTAL ; uint32_t saveVBLANK ; uint32_t saveVSYNC ; uint32_t saveDSPSTRIDE ; uint32_t saveDSPSIZE ; uint32_t saveDSPPOS ; uint32_t saveDSPBASE ; uint32_t savePalette[256U] ; }; struct psb_intel_framebuffer; struct gma_crtc { struct drm_crtc base ; int pipe ; int plane ; uint32_t cursor_addr ; struct gtt_range *cursor_gt ; u8 lut_r[256U] ; u8 lut_g[256U] ; u8 lut_b[256U] ; u8 lut_adj[256U] ; struct psb_intel_framebuffer *fbdev_fb ; struct drm_mode_set mode_set ; struct drm_gem_object *cursor_obj ; struct drm_display_mode saved_mode ; struct drm_display_mode saved_adjusted_mode ; struct psb_intel_mode_device *mode_dev ; u32 mode_flags ; bool active ; struct psb_intel_crtc_state *crtc_state ; struct gma_clock_funcs const *clock_funcs ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct taskstats { __u16 version ; __u32 ac_exitcode ; __u8 ac_flag ; __u8 ac_nice ; __u64 cpu_count ; __u64 cpu_delay_total ; __u64 blkio_count ; __u64 blkio_delay_total ; __u64 swapin_count ; __u64 swapin_delay_total ; __u64 cpu_run_real_total ; __u64 cpu_run_virtual_total ; char ac_comm[32U] ; __u8 ac_sched ; __u8 ac_pad[3U] ; __u32 ac_uid ; __u32 ac_gid ; __u32 ac_pid ; __u32 ac_ppid ; __u32 ac_btime ; __u64 ac_etime ; __u64 ac_utime ; __u64 ac_stime ; __u64 ac_minflt ; __u64 ac_majflt ; __u64 coremem ; __u64 virtmem ; __u64 hiwater_rss ; __u64 hiwater_vm ; __u64 read_char ; __u64 write_char ; __u64 read_syscalls ; __u64 write_syscalls ; __u64 read_bytes ; __u64 write_bytes ; __u64 cancelled_write_bytes ; __u64 nvcsw ; __u64 nivcsw ; __u64 ac_utimescaled ; __u64 ac_stimescaled ; __u64 cpu_scaled_run_real_total ; __u64 freepages_count ; __u64 freepages_delay_total ; }; struct reclaim_state { unsigned long reclaimed_slab ; }; struct swap_extent { struct list_head list ; unsigned long start_page ; unsigned long nr_pages ; sector_t start_block ; }; struct swap_cluster_info { unsigned int data : 24 ; unsigned char flags ; }; struct percpu_cluster { struct swap_cluster_info index ; unsigned int next ; }; struct swap_info_struct { unsigned long flags ; short prio ; struct plist_node list ; struct plist_node avail_list ; signed char type ; unsigned int max ; unsigned char *swap_map ; struct swap_cluster_info *cluster_info ; struct swap_cluster_info free_cluster_head ; struct swap_cluster_info free_cluster_tail ; unsigned int lowest_bit ; unsigned int highest_bit ; unsigned int pages ; unsigned int inuse_pages ; unsigned int cluster_next ; unsigned int cluster_nr ; struct percpu_cluster *percpu_cluster ; struct swap_extent *curr_swap_extent ; struct swap_extent first_swap_extent ; struct block_device *bdev ; struct file *swap_file ; unsigned int old_block_size ; unsigned long *frontswap_map ; atomic_t frontswap_pages ; spinlock_t lock ; struct work_struct discard_work ; struct swap_cluster_info discard_cluster_head ; struct swap_cluster_info discard_cluster_tail ; }; union __anonunion_v_268 { short preferred_node ; nodemask_t nodes ; }; union __anonunion_w_269 { nodemask_t cpuset_mems_allowed ; nodemask_t user_nodemask ; }; struct mempolicy { atomic_t refcnt ; unsigned short mode ; unsigned short flags ; union __anonunion_v_268 v ; union __anonunion_w_269 w ; }; struct xattr_handler { char const *prefix ; int flags ; size_t (*list)(struct dentry * , char * , size_t , char const * , size_t , int ) ; int (*get)(struct dentry * , char const * , void * , size_t , int ) ; int (*set)(struct dentry * , char const * , void const * , size_t , int , int ) ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct vbt_header { u8 signature[20U] ; u16 version ; u16 header_size ; u16 vbt_size ; u8 vbt_checksum ; u8 reserved0 ; u32 bdb_offset ; u32 aim_offset[4U] ; }; struct bdb_header { u8 signature[16U] ; u16 version ; u16 header_size ; u16 bdb_size ; }; struct bdb_general_features { unsigned char panel_fitting : 2 ; unsigned char flexaim : 1 ; unsigned char msg_enable : 1 ; unsigned char clear_screen : 3 ; unsigned char color_flip : 1 ; unsigned char download_ext_vbt : 1 ; unsigned char enable_ssc : 1 ; unsigned char ssc_freq : 1 ; unsigned char enable_lfp_on_override : 1 ; unsigned char disable_ssc_ddt : 1 ; unsigned char rsvd8 : 3 ; unsigned char disable_smooth_vision : 1 ; unsigned char single_dvi : 1 ; unsigned char rsvd9 : 6 ; u8 legacy_monitor_detect ; unsigned char int_crt_support : 1 ; unsigned char int_tv_support : 1 ; unsigned char int_efp_support : 1 ; unsigned char dp_ssc_enb : 1 ; unsigned char dp_ssc_freq : 1 ; unsigned char rsvd11 : 3 ; }; struct bdb_general_definitions { u8 crt_ddc_gmbus_pin ; unsigned char dpms_acpi : 1 ; unsigned char skip_boot_crt_detect : 1 ; unsigned char dpms_aim : 1 ; unsigned char rsvd1 : 5 ; u8 boot_display[2U] ; u8 child_dev_size ; struct child_device_config devices[0U] ; }; struct bdb_lvds_options { u8 panel_type ; u8 rsvd1 ; unsigned char pfit_mode : 2 ; unsigned char pfit_text_mode_enhanced : 1 ; unsigned char pfit_gfx_mode_enhanced : 1 ; unsigned char pfit_ratio_auto : 1 ; unsigned char pixel_dither : 1 ; unsigned char lvds_edid : 1 ; unsigned char rsvd2 : 1 ; u8 rsvd4 ; }; struct lvds_fp_timing { u16 x_res ; u16 y_res ; u32 lvds_reg ; u32 lvds_reg_val ; u32 pp_on_reg ; u32 pp_on_reg_val ; u32 pp_off_reg ; u32 pp_off_reg_val ; u32 pp_cycle_reg ; u32 pp_cycle_reg_val ; u32 pfit_reg ; u32 pfit_reg_val ; u16 terminator ; }; struct lvds_dvo_timing { u16 clock ; u8 hactive_lo ; u8 hblank_lo ; unsigned char hblank_hi : 4 ; unsigned char hactive_hi : 4 ; u8 vactive_lo ; u8 vblank_lo ; unsigned char vblank_hi : 4 ; unsigned char vactive_hi : 4 ; u8 hsync_off_lo ; u8 hsync_pulse_width ; unsigned char vsync_pulse_width : 4 ; unsigned char vsync_off : 4 ; unsigned char rsvd0 : 6 ; unsigned char hsync_off_hi : 2 ; u8 h_image ; u8 v_image ; u8 max_hv ; u8 h_border ; u8 v_border ; unsigned char rsvd1 : 3 ; unsigned char digital : 2 ; unsigned char vsync_positive : 1 ; unsigned char hsync_positive : 1 ; unsigned char rsvd2 : 1 ; }; struct lvds_pnp_id { u16 mfg_name ; u16 product_code ; u32 serial ; u8 mfg_week ; u8 mfg_year ; }; struct bdb_lvds_lfp_data_entry { struct lvds_fp_timing fp_timing ; struct lvds_dvo_timing dvo_timing ; struct lvds_pnp_id pnp_id ; }; struct bdb_lvds_lfp_data { struct bdb_lvds_lfp_data_entry data[16U] ; }; struct bdb_sdvo_lvds_options { u8 panel_backlight ; u8 h40_set_panel_type ; u8 panel_type ; u8 ssc_clk_freq ; u16 als_low_trip ; u16 als_high_trip ; u8 sclalarcoeff_tab_row_num ; u8 sclalarcoeff_tab_row_size ; u8 coefficient[8U] ; u8 panel_misc_bits_1 ; u8 panel_misc_bits_2 ; u8 panel_misc_bits_3 ; u8 panel_misc_bits_4 ; }; struct bdb_driver_features { unsigned char boot_dev_algorithm : 1 ; unsigned char block_display_switch : 1 ; unsigned char allow_display_switch : 1 ; unsigned char hotplug_dvo : 1 ; unsigned char dual_view_zoom : 1 ; unsigned char int15h_hook : 1 ; unsigned char sprite_in_clone : 1 ; unsigned char primary_lfp_id : 1 ; u16 boot_mode_x ; u16 boot_mode_y ; u8 boot_mode_bpp ; u8 boot_mode_refresh ; unsigned char enable_lfp_primary : 1 ; unsigned char selective_mode_pruning : 1 ; unsigned char dual_frequency : 1 ; unsigned char render_clock_freq : 1 ; unsigned char nt_clone_support : 1 ; unsigned char power_scheme_ui : 1 ; unsigned char sprite_display_assign : 1 ; unsigned char cui_aspect_scaling : 1 ; unsigned char preserve_aspect_ratio : 1 ; unsigned char sdvo_device_power_down : 1 ; unsigned char crt_hotplug : 1 ; unsigned char lvds_config : 2 ; unsigned char tv_hotplug : 1 ; unsigned char hdmi_config : 2 ; unsigned char static_display : 1 ; unsigned char reserved2 : 7 ; u16 legacy_crt_max_x ; u16 legacy_crt_max_y ; u8 legacy_crt_max_refresh ; u8 hdmi_termination ; u8 custom_vbt_version ; }; struct edp_link_params { unsigned char rate : 4 ; unsigned char lanes : 4 ; unsigned char preemphasis : 4 ; unsigned char vswing : 4 ; }; struct bdb_edp { struct edp_power_seq power_seqs[16U] ; u32 color_depth ; u32 sdrrs_msa_timing_delay ; struct edp_link_params link_params[16U] ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct intel_gpio { struct i2c_adapter adapter ; struct i2c_algo_bit_data algo ; struct drm_psb_private *dev_priv ; u32 reg ; }; struct gate_struct64 { u16 offset_low ; u16 segment ; unsigned char ist : 3 ; unsigned char zero0 : 5 ; unsigned char type : 5 ; unsigned char dpl : 2 ; unsigned char p : 1 ; u16 offset_middle ; u32 offset_high ; u32 zero1 ; }; typedef struct gate_struct64 gate_desc; struct desc_ptr { unsigned short size ; unsigned long address ; }; struct tss_struct; struct pv_cpu_ops { unsigned long (*get_debugreg)(int ) ; void (*set_debugreg)(int , unsigned long ) ; void (*clts)(void) ; unsigned long (*read_cr0)(void) ; void (*write_cr0)(unsigned long ) ; unsigned long (*read_cr4_safe)(void) ; unsigned long (*read_cr4)(void) ; void (*write_cr4)(unsigned long ) ; unsigned long (*read_cr8)(void) ; void (*write_cr8)(unsigned long ) ; void (*load_tr_desc)(void) ; void (*load_gdt)(struct desc_ptr const * ) ; void (*load_idt)(struct desc_ptr const * ) ; void (*store_idt)(struct desc_ptr * ) ; void (*set_ldt)(void const * , unsigned int ) ; unsigned long (*store_tr)(void) ; void (*load_tls)(struct thread_struct * , unsigned int ) ; void (*load_gs_index)(unsigned int ) ; void (*write_ldt_entry)(struct desc_struct * , int , void const * ) ; void (*write_gdt_entry)(struct desc_struct * , int , void const * , int ) ; void (*write_idt_entry)(gate_desc * , int , gate_desc const * ) ; void (*alloc_ldt)(struct desc_struct * , unsigned int ) ; void (*free_ldt)(struct desc_struct * , unsigned int ) ; void (*load_sp0)(struct tss_struct * , struct thread_struct * ) ; void (*set_iopl_mask)(unsigned int ) ; void (*wbinvd)(void) ; void (*io_delay)(void) ; void (*cpuid)(unsigned int * , unsigned int * , unsigned int * , unsigned int * ) ; u64 (*read_msr)(unsigned int , int * ) ; int (*write_msr)(unsigned int , unsigned int , unsigned int ) ; u64 (*read_tsc)(void) ; u64 (*read_pmc)(int ) ; unsigned long long (*read_tscp)(unsigned int * ) ; void (*usergs_sysret64)(void) ; void (*usergs_sysret32)(void) ; void (*iret)(void) ; void (*swapgs)(void) ; void (*start_context_switch)(struct task_struct * ) ; void (*end_context_switch)(struct task_struct * ) ; }; struct x86_hw_tss { u32 reserved1 ; u64 sp0 ; u64 sp1 ; u64 sp2 ; u64 reserved2 ; u64 ist[7U] ; u32 reserved3 ; u32 reserved4 ; u16 reserved5 ; u16 io_bitmap_base ; }; struct tss_struct { struct x86_hw_tss x86_tss ; unsigned long io_bitmap[1025U] ; unsigned long SYSENTER_stack[64U] ; }; typedef int pao_T__; typedef int pao_T_____0; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct drm_encoder_helper_funcs { void (*dpms)(struct drm_encoder * , int ) ; void (*save)(struct drm_encoder * ) ; void (*restore)(struct drm_encoder * ) ; bool (*mode_fixup)(struct drm_encoder * , struct drm_display_mode const * , struct drm_display_mode * ) ; void (*prepare)(struct drm_encoder * ) ; void (*commit)(struct drm_encoder * ) ; void (*mode_set)(struct drm_encoder * , struct drm_display_mode * , struct drm_display_mode * ) ; struct drm_crtc *(*get_crtc)(struct drm_encoder * ) ; enum drm_connector_status (*detect)(struct drm_encoder * , struct drm_connector * ) ; void (*disable)(struct drm_encoder * ) ; void (*enable)(struct drm_encoder * ) ; int (*atomic_check)(struct drm_encoder * , struct drm_crtc_state * , struct drm_connector_state * ) ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct drm_connector_helper_funcs { int (*get_modes)(struct drm_connector * ) ; enum drm_mode_status (*mode_valid)(struct drm_connector * , struct drm_display_mode * ) ; struct drm_encoder *(*best_encoder)(struct drm_connector * ) ; }; struct psb_intel_lvds_priv { uint32_t savePP_ON ; uint32_t savePP_OFF ; uint32_t saveLVDS ; uint32_t savePP_CONTROL ; uint32_t savePP_CYCLE ; uint32_t savePFIT_CONTROL ; uint32_t savePFIT_PGM_RATIOS ; uint32_t saveBLC_PWM_CTL ; struct psb_intel_i2c_chan *i2c_bus ; struct psb_intel_i2c_chan *ddc_bus ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct edid; typedef __u16 __le16; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct est_timings { u8 t1 ; u8 t2 ; u8 mfg_rsvd ; }; struct std_timing { u8 hsize ; u8 vfreq_aspect ; }; struct detailed_pixel_timing { u8 hactive_lo ; u8 hblank_lo ; u8 hactive_hblank_hi ; u8 vactive_lo ; u8 vblank_lo ; u8 vactive_vblank_hi ; u8 hsync_offset_lo ; u8 hsync_pulse_width_lo ; u8 vsync_offset_pulse_width_lo ; u8 hsync_vsync_offset_pulse_width_hi ; u8 width_mm_lo ; u8 height_mm_lo ; u8 width_height_mm_hi ; u8 hborder ; u8 vborder ; u8 misc ; }; struct detailed_data_string { u8 str[13U] ; }; struct __anonstruct_gtf2_259 { u8 reserved ; u8 hfreq_start_khz ; u8 c ; __le16 m ; u8 k ; u8 j ; }; struct __anonstruct_cvt_260 { u8 version ; u8 data1 ; u8 data2 ; u8 supported_aspects ; u8 flags ; u8 supported_scalings ; u8 preferred_refresh ; }; union __anonunion_formula_258 { struct __anonstruct_gtf2_259 gtf2 ; struct __anonstruct_cvt_260 cvt ; }; struct detailed_data_monitor_range { u8 min_vfreq ; u8 max_vfreq ; u8 min_hfreq_khz ; u8 max_hfreq_khz ; u8 pixel_clock_mhz ; u8 flags ; union __anonunion_formula_258 formula ; }; struct detailed_data_wpindex { u8 white_yx_lo ; u8 white_x_hi ; u8 white_y_hi ; u8 gamma ; }; struct cvt_timing { u8 code[3U] ; }; union __anonunion_data_261 { struct detailed_data_string str ; struct detailed_data_monitor_range range ; struct detailed_data_wpindex color ; struct std_timing timings[6U] ; struct cvt_timing cvt[4U] ; }; struct detailed_non_pixel { u8 pad1 ; u8 type ; u8 pad2 ; union __anonunion_data_261 data ; }; union __anonunion_data_262 { struct detailed_pixel_timing pixel_data ; struct detailed_non_pixel other_data ; }; struct detailed_timing { __le16 pixel_clock ; union __anonunion_data_262 data ; }; struct edid { u8 header[8U] ; u8 mfg_id[2U] ; u8 prod_code[2U] ; u32 serial ; u8 mfg_week ; u8 mfg_year ; u8 version ; u8 revision ; u8 input ; u8 width_cm ; u8 height_cm ; u8 gamma ; u8 features ; u8 red_green_lo ; u8 black_white_lo ; u8 red_x ; u8 red_y ; u8 green_x ; u8 green_y ; u8 blue_x ; u8 blue_y ; u8 white_x ; u8 white_y ; struct est_timings established_timings ; struct std_timing standard_timings[8U] ; struct detailed_timing detailed_timings[4U] ; u8 extensions ; u8 checksum ; }; struct psb_intel_sdvo_caps { u8 vendor_id ; u8 device_id ; u8 device_rev_id ; u8 sdvo_version_major ; u8 sdvo_version_minor ; unsigned char sdvo_inputs_mask : 2 ; unsigned char smooth_scaling : 1 ; unsigned char sharp_scaling : 1 ; unsigned char up_scaling : 1 ; unsigned char down_scaling : 1 ; unsigned char stall_support : 1 ; unsigned char pad : 1 ; u16 output_flags ; }; struct __anonstruct_part1_270 { u16 clock ; u8 h_active ; u8 h_blank ; u8 h_high ; u8 v_active ; u8 v_blank ; u8 v_high ; }; struct __anonstruct_part2_271 { u8 h_sync_off ; u8 h_sync_width ; u8 v_sync_off_width ; u8 sync_off_width_high ; u8 dtd_flags ; u8 sdvo_flags ; u8 v_sync_off_high ; u8 reserved ; }; struct psb_intel_sdvo_dtd { struct __anonstruct_part1_270 part1 ; struct __anonstruct_part2_271 part2 ; }; struct psb_intel_sdvo_pixel_clock_range { u16 min ; u16 max ; }; struct psb_intel_sdvo_preferred_input_timing_args { u16 clock ; u16 width ; u16 height ; unsigned char interlace : 1 ; unsigned char scaled : 1 ; unsigned char pad : 6 ; }; struct psb_intel_sdvo_get_trained_inputs_response { unsigned char input0_trained : 1 ; unsigned char input1_trained : 1 ; unsigned char pad : 6 ; }; struct psb_intel_sdvo_in_out_map { u16 in0 ; u16 in1 ; }; struct psb_intel_sdvo_set_target_input_args { unsigned char target_1 : 1 ; unsigned char pad : 7 ; }; struct psb_intel_sdvo_tv_format { unsigned char ntsc_m : 1 ; unsigned char ntsc_j : 1 ; unsigned char ntsc_443 : 1 ; unsigned char pal_b : 1 ; unsigned char pal_d : 1 ; unsigned char pal_g : 1 ; unsigned char pal_h : 1 ; unsigned char pal_i : 1 ; unsigned char pal_m : 1 ; unsigned char pal_n : 1 ; unsigned char pal_nc : 1 ; unsigned char pal_60 : 1 ; unsigned char secam_b : 1 ; unsigned char secam_d : 1 ; unsigned char secam_g : 1 ; unsigned char secam_k : 1 ; unsigned char secam_k1 : 1 ; unsigned char secam_l : 1 ; unsigned char secam_60 : 1 ; unsigned char hdtv_std_smpte_240m_1080i_59 : 1 ; unsigned char hdtv_std_smpte_240m_1080i_60 : 1 ; unsigned char hdtv_std_smpte_260m_1080i_59 : 1 ; unsigned char hdtv_std_smpte_260m_1080i_60 : 1 ; unsigned char hdtv_std_smpte_274m_1080i_50 : 1 ; unsigned char hdtv_std_smpte_274m_1080i_59 : 1 ; unsigned char hdtv_std_smpte_274m_1080i_60 : 1 ; unsigned char hdtv_std_smpte_274m_1080p_23 : 1 ; unsigned char hdtv_std_smpte_274m_1080p_24 : 1 ; unsigned char hdtv_std_smpte_274m_1080p_25 : 1 ; unsigned char hdtv_std_smpte_274m_1080p_29 : 1 ; unsigned char hdtv_std_smpte_274m_1080p_30 : 1 ; unsigned char hdtv_std_smpte_274m_1080p_50 : 1 ; unsigned char hdtv_std_smpte_274m_1080p_59 : 1 ; unsigned char hdtv_std_smpte_274m_1080p_60 : 1 ; unsigned char hdtv_std_smpte_295m_1080i_50 : 1 ; unsigned char hdtv_std_smpte_295m_1080p_50 : 1 ; unsigned char hdtv_std_smpte_296m_720p_59 : 1 ; unsigned char hdtv_std_smpte_296m_720p_60 : 1 ; unsigned char hdtv_std_smpte_296m_720p_50 : 1 ; unsigned char hdtv_std_smpte_293m_480p_59 : 1 ; unsigned char hdtv_std_smpte_170m_480i_59 : 1 ; unsigned char hdtv_std_iturbt601_576i_50 : 1 ; unsigned char hdtv_std_iturbt601_576p_50 : 1 ; unsigned char hdtv_std_eia_7702a_480i_60 : 1 ; unsigned char hdtv_std_eia_7702a_480p_60 : 1 ; unsigned char pad : 3 ; }; struct psb_intel_sdvo_sdtv_resolution_request { unsigned char ntsc_m : 1 ; unsigned char ntsc_j : 1 ; unsigned char ntsc_443 : 1 ; unsigned char pal_b : 1 ; unsigned char pal_d : 1 ; unsigned char pal_g : 1 ; unsigned char pal_h : 1 ; unsigned char pal_i : 1 ; unsigned char pal_m : 1 ; unsigned char pal_n : 1 ; unsigned char pal_nc : 1 ; unsigned char pal_60 : 1 ; unsigned char secam_b : 1 ; unsigned char secam_d : 1 ; unsigned char secam_g : 1 ; unsigned char secam_k : 1 ; unsigned char secam_k1 : 1 ; unsigned char secam_l : 1 ; unsigned char secam_60 : 1 ; unsigned char pad : 5 ; }; struct psb_intel_sdvo_enhancements_reply { unsigned char flicker_filter : 1 ; unsigned char flicker_filter_adaptive : 1 ; unsigned char flicker_filter_2d : 1 ; unsigned char saturation : 1 ; unsigned char hue : 1 ; unsigned char brightness : 1 ; unsigned char contrast : 1 ; unsigned char overscan_h : 1 ; unsigned char overscan_v : 1 ; unsigned char hpos : 1 ; unsigned char vpos : 1 ; unsigned char sharpness : 1 ; unsigned char dot_crawl : 1 ; unsigned char dither : 1 ; unsigned char tv_chroma_filter : 1 ; unsigned char tv_luma_filter : 1 ; }; struct psb_intel_sdvo_encode { u8 dvi_rev ; u8 hdmi_rev ; }; struct psb_intel_sdvo { struct gma_encoder base ; struct i2c_adapter *i2c ; u8 slave_addr ; struct i2c_adapter ddc ; int sdvo_reg ; uint16_t controlled_output ; struct psb_intel_sdvo_caps caps ; int pixel_clock_min ; int pixel_clock_max ; uint16_t attached_output ; uint32_t color_range ; bool is_tv ; int tv_format_index ; bool is_hdmi ; bool has_hdmi_monitor ; bool has_hdmi_audio ; bool is_lvds ; struct drm_display_mode *sdvo_lvds_fixed_mode ; uint8_t ddc_bus ; struct psb_intel_sdvo_dtd input_dtd ; uint32_t saveSDVO ; }; struct psb_intel_sdvo_connector { struct gma_connector base ; uint16_t output_flag ; int force_audio ; u8 tv_format_supported[19U] ; int format_supported_num ; struct drm_property *tv_format ; struct drm_property *left ; struct drm_property *right ; struct drm_property *top ; struct drm_property *bottom ; struct drm_property *hpos ; struct drm_property *vpos ; struct drm_property *contrast ; struct drm_property *saturation ; struct drm_property *hue ; struct drm_property *sharpness ; struct drm_property *flicker_filter ; struct drm_property *flicker_filter_adaptive ; struct drm_property *flicker_filter_2d ; struct drm_property *tv_chroma_filter ; struct drm_property *tv_luma_filter ; struct drm_property *dot_crawl ; struct drm_property *brightness ; u32 left_margin ; u32 right_margin ; u32 top_margin ; u32 bottom_margin ; u32 max_hscan ; u32 max_vscan ; u32 max_hpos ; u32 cur_hpos ; u32 max_vpos ; u32 cur_vpos ; u32 cur_brightness ; u32 max_brightness ; u32 cur_contrast ; u32 max_contrast ; u32 cur_saturation ; u32 max_saturation ; u32 cur_hue ; u32 max_hue ; u32 cur_sharpness ; u32 max_sharpness ; u32 cur_flicker_filter ; u32 max_flicker_filter ; u32 cur_flicker_filter_adaptive ; u32 max_flicker_filter_adaptive ; u32 cur_flicker_filter_2d ; u32 max_flicker_filter_2d ; u32 cur_tv_chroma_filter ; u32 max_tv_chroma_filter ; u32 cur_tv_luma_filter ; u32 max_tv_luma_filter ; u32 cur_dot_crawl ; u32 max_dot_crawl ; }; struct _sdvo_cmd_name { u8 cmd ; char const *name ; }; union __anonunion_enhancements_280 { struct psb_intel_sdvo_enhancements_reply reply ; uint16_t response ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; typedef int ldv_func_ret_type___3; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct gct_r10_timing_info { u16 pixel_clock ; unsigned char hactive_lo ; unsigned char hactive_hi : 4 ; unsigned char hblank_lo ; unsigned char hblank_hi : 4 ; unsigned char hsync_offset_lo ; unsigned char hsync_offset_hi : 2 ; unsigned char hsync_pulse_width_lo ; unsigned char hsync_pulse_width_hi : 2 ; unsigned char hsync_positive : 1 ; unsigned char rsvd_1 : 3 ; u8 vactive_lo ; unsigned char vactive_hi : 4 ; unsigned char vblank_lo ; unsigned char vblank_hi : 4 ; unsigned char vsync_offset_lo : 4 ; unsigned char vsync_offset_hi : 2 ; unsigned char vsync_pulse_width_lo : 4 ; unsigned char vsync_pulse_width_hi : 2 ; unsigned char vsync_positive : 1 ; unsigned char rsvd_2 : 3 ; }; struct oaktrail_panel_descriptor_v1 { u32 Panel_Port_Control ; u32 Panel_Power_On_Sequencing ; u32 Panel_Power_Off_Sequencing ; u32 Panel_Power_Cycle_Delay_and_Reference_Divisor ; struct oaktrail_timing_info DTD ; u16 Panel_Backlight_Inverter_Descriptor ; u16 Panel_MIPI_Display_Descriptor ; }; struct oaktrail_panel_descriptor_v2 { u32 Panel_Port_Control ; u32 Panel_Power_On_Sequencing ; u32 Panel_Power_Off_Sequencing ; u8 Panel_Power_Cycle_Delay_and_Reference_Divisor ; struct oaktrail_timing_info DTD ; u16 Panel_Backlight_Inverter_Descriptor ; u8 Panel_Initial_Brightness ; u16 Panel_MIPI_Display_Descriptor ; }; struct __anonstruct_panelrx_258 { unsigned char NumberOfLanes : 2 ; unsigned char MaxLaneFreq : 3 ; unsigned char SupportedVideoTransferMode : 2 ; unsigned char HSClkBehavior : 1 ; unsigned char DuoDisplaySupport : 1 ; unsigned char ECC_ChecksumCapabilities : 1 ; unsigned char BidirectionalCommunication : 1 ; unsigned char Rsvd : 5 ; }; union oaktrail_panel_rx { struct __anonstruct_panelrx_258 panelrx ; u16 panel_receiver ; }; struct __anonstruct_PD_260 { unsigned char PanelType : 4 ; unsigned char BootPanelIndex : 2 ; unsigned char BootMIPI_DSI_RxIndex : 2 ; }; union __anonunion____missing_field_name_259 { struct __anonstruct_PD_260 PD ; u8 PanelDescriptor ; }; struct gct_r0 { union __anonunion____missing_field_name_259 __annonCompField77 ; struct oaktrail_panel_descriptor_v1 panel[4U] ; union oaktrail_panel_rx panelrx[4U] ; }; struct __anonstruct_PD_262 { unsigned char PanelType : 4 ; unsigned char BootPanelIndex : 2 ; unsigned char BootMIPI_DSI_RxIndex : 2 ; }; union __anonunion____missing_field_name_261 { struct __anonstruct_PD_262 PD ; u8 PanelDescriptor ; }; struct gct_r1 { union __anonunion____missing_field_name_261 __annonCompField78 ; struct oaktrail_panel_descriptor_v2 panel[4U] ; union oaktrail_panel_rx panelrx[4U] ; }; struct gct_r10 { struct gct_r10_timing_info DTD ; u16 Panel_MIPI_Display_Descriptor ; u16 Panel_MIPI_Receiver_Descriptor ; u16 Panel_Backlight_Inverter_Descriptor ; u8 Panel_Initial_Brightness ; u32 MIPI_Ctlr_Init_ptr ; u32 MIPI_Panel_Init_ptr ; }; struct mid_vbt_header { u32 signature ; u8 revision ; }; struct vbt_r0 { struct mid_vbt_header vbt_header ; u8 size ; u8 checksum ; }; struct vbt_r10 { struct mid_vbt_header vbt_header ; u8 checksum ; u16 size ; u8 panel_count ; u8 primary_panel_idx ; u8 secondary_panel_idx ; u8 __reserved[5U] ; }; enum hrtimer_restart; typedef u64 acpi_size; typedef u64 acpi_physical_address; enum i2c_slave_event; enum i2c_slave_event; struct opregion_header { u8 signature[16U] ; u32 size ; u32 opregion_ver ; u8 bios_ver[32U] ; u8 vbios_ver[16U] ; u8 driver_ver[16U] ; u32 mboxes ; u8 reserved[164U] ; }; struct opregion_acpi { u32 drdy ; u32 csts ; u32 cevt ; u8 rsvd1[20U] ; u32 didl[8U] ; u32 cpdl[8U] ; u32 cadl[8U] ; u32 nadl[8U] ; u32 aslp ; u32 tidx ; u32 chpd ; u32 clid ; u32 cdck ; u32 sxsw ; u32 evts ; u32 cnot ; u32 nrdy ; u8 rsvd2[60U] ; }; struct opregion_swsci { }; struct opregion_asle { u32 ardy ; u32 aslc ; u32 tche ; u32 alsi ; u32 bclp ; u32 pfit ; u32 cblv ; u16 bclm[20U] ; u32 cpfm ; u32 epfm ; u8 plut[74U] ; u32 pfmb ; u8 rsvd[102U] ; }; typedef bool ldv_func_ret_type___4; typedef unsigned int uint; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct mdfld_hdmi_i2c; struct mid_intel_hdmi_priv { u32 hdmi_reg ; u32 save_HDMIB ; bool has_hdmi_sink ; bool has_hdmi_audio ; bool hdmi_device_connected ; struct mdfld_hdmi_i2c *i2c_bus ; struct i2c_adapter *hdmi_i2c_adapter ; struct drm_device *dev ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct cdv_intel_lvds_priv { uint32_t savePP_ON ; uint32_t savePP_OFF ; uint32_t saveLVDS ; uint32_t savePP_CONTROL ; uint32_t savePP_CYCLE ; uint32_t savePFIT_CONTROL ; uint32_t savePFIT_PGM_RATIOS ; uint32_t saveBLC_PWM_CTL ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct i2c_algo_dp_aux_data { bool running ; u16 address ; int (*aux_ch)(struct i2c_adapter * , int , uint8_t , uint8_t * ) ; }; struct cdv_intel_dp { uint32_t output_reg ; uint32_t DP ; uint8_t link_configuration[9U] ; bool has_audio ; int force_audio ; uint32_t color_range ; uint8_t link_bw ; uint8_t lane_count ; uint8_t dpcd[4U] ; struct gma_encoder *encoder ; struct i2c_adapter adapter ; struct i2c_algo_dp_aux_data algo ; uint8_t train_set[4U] ; uint8_t link_status[6U] ; int panel_power_up_delay ; int panel_power_down_delay ; int panel_power_cycle_delay ; int backlight_on_delay ; int backlight_off_delay ; struct drm_display_mode *panel_fixed_mode ; bool panel_on ; }; struct ddi_regoff { uint32_t PreEmph1 ; uint32_t PreEmph2 ; uint32_t VSwing1 ; uint32_t VSwing2 ; uint32_t VSwing3 ; uint32_t VSwing4 ; uint32_t VSwing5 ; }; struct cdv_intel_dp_m_n { uint32_t tu ; uint32_t gmch_m ; uint32_t gmch_n ; uint32_t link_m ; uint32_t link_n ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct intel_range { int min ; int max ; }; struct oaktrail_hdmi_limit { struct intel_range vco ; struct intel_range np ; struct intel_range nr ; struct intel_range nf ; }; struct oaktrail_hdmi_clock { int np ; int nr ; int nf ; int dot ; }; enum hrtimer_restart; enum i2c_slave_event; enum i2c_slave_event; struct hdmi_i2c_dev { struct i2c_adapter *adap ; struct mutex i2c_lock ; struct completion complete ; int status ; struct i2c_msg *msg ; int buf_offset ; }; __inline static long ldv__builtin_expect(long exp , long c ) ; extern void *memset(void * , int , size_t ) ; __inline static void rep_nop(void) { { __asm__ volatile ("rep; nop": : : "memory"); return; } } __inline static void cpu_relax(void) { { rep_nop(); return; } } extern unsigned long _raw_spin_lock_irqsave(raw_spinlock_t * ) ; extern void _raw_spin_unlock_irqrestore(raw_spinlock_t * , unsigned long ) ; __inline static raw_spinlock_t *spinlock_check(spinlock_t *lock ) { { return (& lock->__annonCompField18.rlock); } } __inline static void spin_unlock_irqrestore(spinlock_t *lock , unsigned long flags ) { { _raw_spin_unlock_irqrestore(& lock->__annonCompField18.rlock, flags); return; } } extern unsigned long volatile jiffies ; extern bool queue_work_on(int , struct workqueue_struct * , struct work_struct * ) ; bool ldv_queue_work_on_5(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_7(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; extern bool queue_delayed_work_on(int , struct workqueue_struct * , struct delayed_work * , unsigned long ) ; bool ldv_queue_delayed_work_on_6(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_9(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; extern void flush_workqueue(struct workqueue_struct * ) ; void ldv_flush_workqueue_8(struct workqueue_struct *ldv_func_arg1 ) ; extern unsigned int ioread32(void * ) ; extern void iowrite32(u32 , void * ) ; extern void *malloc(size_t ) ; extern void *calloc(size_t , size_t ) ; extern int __VERIFIER_nondet_int(void) ; extern unsigned long __VERIFIER_nondet_ulong(void) ; extern void *__VERIFIER_nondet_pointer(void) ; extern void __VERIFIER_assume(int ) ; void *ldv_malloc(size_t size ) { void *p ; void *tmp ; int tmp___0 ; { tmp___0 = __VERIFIER_nondet_int(); if (tmp___0 != 0) { return ((void *)0); } else { tmp = malloc(size); p = tmp; __VERIFIER_assume((unsigned long )p != (unsigned long )((void *)0)); return (p); } } } void *ldv_zalloc(size_t size ) { void *p ; void *tmp ; int tmp___0 ; { tmp___0 = __VERIFIER_nondet_int(); if (tmp___0 != 0) { return ((void *)0); } else { tmp = calloc(1UL, size); p = tmp; __VERIFIER_assume((unsigned long )p != (unsigned long )((void *)0)); return (p); } } } void *ldv_init_zalloc(size_t size ) { void *p ; void *tmp ; { tmp = calloc(1UL, size); p = tmp; __VERIFIER_assume((unsigned long )p != (unsigned long )((void *)0)); return (p); } } void *ldv_memset(void *s , int c , size_t n ) { void *tmp ; { tmp = memset(s, c, n); return (tmp); } } int ldv_undef_int(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); return (tmp); } } void *ldv_undef_ptr(void) { void *tmp ; { tmp = __VERIFIER_nondet_pointer(); return (tmp); } } unsigned long ldv_undef_ulong(void) { unsigned long tmp ; { tmp = __VERIFIER_nondet_ulong(); return (tmp); } } __inline static long ldv__builtin_expect(long exp , long c ) { { return (exp); } } int ldv_irq_1_3 = 0; int LDV_IN_INTERRUPT = 1; int ldv_irq_1_1 = 0; int ldv_timer_state_4 = 0; int ldv_irq_1_0 = 0; int ldv_irq_1_2 = 0; void call_and_disable_all_2(int state ) ; void activate_work_2(struct work_struct *work , int state ) ; extern void msleep(unsigned int ) ; extern void cfb_copyarea(struct fb_info * , struct fb_copyarea const * ) ; bool gma_power_begin(struct drm_device *dev , bool force_on ) ; void gma_power_end(struct drm_device *dev ) ; void psbfb_copyarea(struct fb_info *info , struct fb_copyarea const *region ) ; int psbfb_sync(struct fb_info *info ) ; void psb_spank(struct drm_psb_private *dev_priv ) ; void psb_spank(struct drm_psb_private *dev_priv ) { unsigned int tmp ; unsigned int tmp___0 ; { iowrite32(127U, (void *)dev_priv->sgx_reg + 128U); ioread32((void *)dev_priv->sgx_reg + 128U); msleep(1U); iowrite32(0U, (void *)dev_priv->sgx_reg + 128U); __asm__ volatile ("sfence": : : "memory"); tmp = ioread32((void *)dev_priv->sgx_reg + 3072U); iowrite32(tmp | 16U, (void *)dev_priv->sgx_reg + 3072U); __asm__ volatile ("sfence": : : "memory"); ioread32((void *)dev_priv->sgx_reg + 3072U); msleep(1U); tmp___0 = ioread32((void *)dev_priv->sgx_reg + 3072U); iowrite32(tmp___0 & 4294967279U, (void *)dev_priv->sgx_reg + 3072U); ioread32((void *)dev_priv->sgx_reg + 3072U); iowrite32(dev_priv->gtt.gatt_start, (void *)dev_priv->sgx_reg + 3208U); return; } } static int psb_2d_wait_available(struct drm_psb_private *dev_priv , unsigned int size ) { uint32_t avail ; unsigned int tmp ; unsigned long t ; { tmp = ioread32((void *)dev_priv->sgx_reg + 3608U); avail = tmp; t = (unsigned long )jiffies + 250UL; goto ldv_42722; ldv_42721: avail = ioread32((void *)dev_priv->sgx_reg + 3608U); if ((long )(t - (unsigned long )jiffies) < 0L) { psb_spank(dev_priv); return (-5); } else { } ldv_42722: ; if (avail < size) { goto ldv_42721; } else { } return (0); } } static int psbfb_2d_submit(struct drm_psb_private *dev_priv , uint32_t *cmdbuf , unsigned int size ) { int ret ; int i ; unsigned int submit_size ; unsigned long flags ; raw_spinlock_t *tmp ; uint32_t *tmp___0 ; { ret = 0; tmp = spinlock_check(& dev_priv->lock_2d); flags = _raw_spin_lock_irqsave(tmp); goto ldv_42741; ldv_42740: submit_size = 96U < size ? 96U : size; size = size - submit_size; ret = psb_2d_wait_available(dev_priv, submit_size); if (ret != 0) { goto ldv_42736; } else { } submit_size = submit_size << 2; i = 0; goto ldv_42738; ldv_42737: tmp___0 = cmdbuf; cmdbuf = cmdbuf + 1; iowrite32(*tmp___0, (void *)dev_priv->sgx_reg + (unsigned long )(i + 16384)); i = i + 4; ldv_42738: ; if ((unsigned int )i < submit_size) { goto ldv_42737; } else { } ioread32((void *)(dev_priv->sgx_reg + ((unsigned long )(i + 16384) + 0xfffffffffffffffcUL))); ldv_42741: ; if (size != 0U) { goto ldv_42740; } else { } ldv_42736: spin_unlock_irqrestore(& dev_priv->lock_2d, flags); return (ret); } } static u32 psb_accel_2d_copy_direction(int xdir , int ydir ) { { if (xdir < 0) { return (ydir < 0 ? 8388608U : 16777216U); } else { return (ydir < 0 ? 25165824U : 0U); } } } static int psb_accel_2d_copy(struct drm_psb_private *dev_priv , uint32_t src_offset , uint32_t src_stride , uint32_t src_format , uint32_t dst_offset , uint32_t dst_stride , uint32_t dst_format , uint16_t src_x , uint16_t src_y , uint16_t dst_x , uint16_t dst_y , uint16_t size_x , uint16_t size_y ) { uint32_t blit_cmd ; uint32_t buffer[10U] ; uint32_t *buf ; uint32_t direction ; uint32_t *tmp ; uint32_t *tmp___0 ; uint32_t *tmp___1 ; uint32_t *tmp___2 ; uint32_t *tmp___3 ; uint32_t *tmp___4 ; uint32_t *tmp___5 ; uint32_t *tmp___6 ; uint32_t *tmp___7 ; uint32_t *tmp___8 ; int tmp___9 ; { buf = (uint32_t *)(& buffer); direction = psb_accel_2d_copy_direction((int )src_x - (int )dst_x, (int )src_y - (int )dst_y); if (direction == 8388608U || direction == 16777216U) { src_x = (unsigned int )((int )size_x + (int )src_x) + 65535U; dst_x = (unsigned int )((int )size_x + (int )dst_x) + 65535U; } else { } if (direction == 8388608U || direction == 25165824U) { src_y = (unsigned int )((int )size_y + (int )src_y) + 65535U; dst_y = (unsigned int )((int )size_y + (int )dst_y) + 65535U; } else { } blit_cmd = direction | 2147601612U; tmp = buf; buf = buf + 1; *tmp = 1879048192U; tmp___0 = buf; buf = buf + 1; *tmp___0 = (dst_format | dst_stride) | 2684354560U; tmp___1 = buf; buf = buf + 1; *tmp___1 = dst_offset; tmp___2 = buf; buf = buf + 1; *tmp___2 = (src_format | src_stride) | 2415919104U; tmp___3 = buf; buf = buf + 1; *tmp___3 = src_offset; tmp___4 = buf; buf = buf + 1; *tmp___4 = (uint32_t )((((int )src_x << 12) | 805306368) | (int )src_y); tmp___5 = buf; buf = buf + 1; *tmp___5 = blit_cmd; tmp___6 = buf; buf = buf + 1; *tmp___6 = (uint32_t )(((int )dst_x << 12) | (int )dst_y); tmp___7 = buf; buf = buf + 1; *tmp___7 = (uint32_t )(((int )size_x << 12) | (int )size_y); tmp___8 = buf; buf = buf + 1; *tmp___8 = 4026531840U; tmp___9 = psbfb_2d_submit(dev_priv, (uint32_t *)(& buffer), (unsigned int )(((long )buf - (long )(& buffer)) / 4L)); return (tmp___9); } } static void psbfb_copyarea_accel(struct fb_info *info , struct fb_copyarea const *a ) { struct psb_fbdev *fbdev ; struct psb_framebuffer *psbfb ; struct drm_device *dev ; struct drm_framebuffer *fb ; struct drm_psb_private *dev_priv ; uint32_t offset ; uint32_t stride ; uint32_t src_format ; uint32_t dst_format ; bool tmp ; int tmp___0 ; { fbdev = (struct psb_fbdev *)info->par; psbfb = & fbdev->pfb; dev = psbfb->base.dev; fb = fbdev->psb_fb_helper.fb; dev_priv = (struct drm_psb_private *)dev->dev_private; if ((unsigned long )fb == (unsigned long )((struct drm_framebuffer *)0)) { return; } else { } offset = (psbfb->gtt)->offset; stride = fb->pitches[0]; switch (fb->depth) { case 8U: src_format = 196608U; dst_format = 196608U; goto ldv_42779; case 15U: src_format = 262144U; dst_format = 262144U; goto ldv_42779; case 16U: src_format = 327680U; dst_format = 327680U; goto ldv_42779; case 24U: ; case 32U: src_format = 393216U; dst_format = 393216U; goto ldv_42779; default: cfb_copyarea(info, a); return; } ldv_42779: tmp = gma_power_begin(dev, 0); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { cfb_copyarea(info, a); return; } else { } psb_accel_2d_copy(dev_priv, offset, stride, src_format, offset, stride, dst_format, (int )((uint16_t )a->sx), (int )((uint16_t )a->sy), (int )((uint16_t )a->dx), (int )((uint16_t )a->dy), (int )((uint16_t )a->width), (int )((uint16_t )a->height)); gma_power_end(dev); return; } } void psbfb_copyarea(struct fb_info *info , struct fb_copyarea const *region ) { long tmp ; { tmp = ldv__builtin_expect(info->state != 0U, 0L); if (tmp != 0L) { return; } else { } if (((unsigned int )region->width == 8U || (unsigned int )region->height == 8U) || (info->flags & 2) != 0) { return; } else { } psbfb_copyarea_accel(info, region); return; } } int psbfb_sync(struct fb_info *info ) { struct psb_fbdev *fbdev ; struct psb_framebuffer *psbfb ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; unsigned long _end___0 ; int busy ; unsigned long flags ; raw_spinlock_t *tmp ; unsigned int tmp___0 ; unsigned int tmp___1 ; unsigned int tmp___2 ; unsigned int tmp___3 ; unsigned int tmp___4 ; unsigned int tmp___5 ; { fbdev = (struct psb_fbdev *)info->par; psbfb = & fbdev->pfb; dev = psbfb->base.dev; dev_priv = (struct drm_psb_private *)dev->dev_private; _end___0 = (unsigned long )jiffies + 250UL; busy = 0; tmp = spinlock_check(& dev_priv->lock_2d); flags = _raw_spin_lock_irqsave(tmp); tmp___0 = ioread32((void *)dev_priv->sgx_reg + 3608U); if (tmp___0 == 128U) { tmp___1 = ioread32((void *)dev_priv->sgx_reg + 3588U); if ((tmp___1 & 16777216U) == 0U) { goto out; } else { } } else { } ldv_42809: tmp___2 = ioread32((void *)dev_priv->sgx_reg + 3608U); busy = tmp___2 != 128U; cpu_relax(); if (busy != 0 && (long )((unsigned long )jiffies - _end___0) < 0L) { goto ldv_42809; } else { } if (busy != 0) { tmp___3 = ioread32((void *)dev_priv->sgx_reg + 3608U); busy = tmp___3 != 128U; } else { } if (busy != 0) { goto out; } else { } ldv_42817: tmp___4 = ioread32((void *)dev_priv->sgx_reg + 3588U); busy = (tmp___4 & 16777216U) != 0U; cpu_relax(); if (busy != 0 && (long )((unsigned long )jiffies - _end___0) < 0L) { goto ldv_42817; } else { } if (busy != 0) { tmp___5 = ioread32((void *)dev_priv->sgx_reg + 3588U); busy = (tmp___5 & 16777216U) != 0U; } else { } out: spin_unlock_irqrestore(& dev_priv->lock_2d, flags); return (busy != 0 ? -16 : 0); } } bool ldv_queue_work_on_5(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_6(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_7(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_8(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_9(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_19(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_21(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_20(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_23(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_22(struct workqueue_struct *ldv_func_arg1 ) ; int gma_backlight_init(struct drm_device *dev ) ; void gma_backlight_exit(struct drm_device *dev ) ; void gma_backlight_disable(struct drm_device *dev ) ; void gma_backlight_enable(struct drm_device *dev ) ; void gma_backlight_set(struct drm_device *dev , int v ) ; void gma_backlight_enable(struct drm_device *dev ) { { return; } } void gma_backlight_disable(struct drm_device *dev ) { { return; } } void gma_backlight_set(struct drm_device *dev , int v ) { { return; } } int gma_backlight_init(struct drm_device *dev ) { { return (0); } } void gma_backlight_exit(struct drm_device *dev ) { { return; } } bool ldv_queue_work_on_19(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_20(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_21(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_22(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_23(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; extern struct module __this_module ; extern uint16_t __cachemode2pte_tbl[8U] ; __inline static unsigned long cachemode2protval(enum page_cache_mode pcm ) { long tmp ; { tmp = ldv__builtin_expect((unsigned int )pcm == 0U, 1L); if (tmp != 0L) { return (0UL); } else { } return ((unsigned long )__cachemode2pte_tbl[(unsigned int )pcm]); } } extern void __dynamic_dev_dbg(struct _ddebug * , struct device const * , char const * , ...) ; void *ldv_err_ptr(long error ) ; extern void warn_slowpath_null(char const * , int const ) ; extern char *strcpy(char * , char const * ) ; __inline static void *ERR_PTR(long error ) ; extern struct cpuinfo_x86 boot_cpu_data ; extern void __cmpxchg_wrong_size(void) ; __inline static int atomic_read(atomic_t const *v ) { int __var ; { __var = 0; return ((int )*((int const volatile *)(& v->counter))); } } __inline static int atomic_sub_and_test(int i , atomic_t *v ) { char c ; { __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; subl %2, %0; sete %1": "+m" (v->counter), "=qm" (c): "er" (i): "memory"); return ((int )((signed char )c) != 0); } } __inline static int atomic_dec_and_test(atomic_t *v ) { char c ; { __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; decl %0; sete %1": "+m" (v->counter), "=qm" (c): : "memory"); return ((int )((signed char )c) != 0); } } __inline static int atomic_cmpxchg(atomic_t *v , int old , int new ) { int __ret ; int __old ; int __new ; u8 volatile *__ptr ; u16 volatile *__ptr___0 ; u32 volatile *__ptr___1 ; u64 volatile *__ptr___2 ; { __old = old; __new = new; switch (4UL) { case 1UL: __ptr = (u8 volatile *)(& v->counter); __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; cmpxchgb %2,%1": "=a" (__ret), "+m" (*__ptr): "q" (__new), "0" (__old): "memory"); goto ldv_5679; case 2UL: __ptr___0 = (u16 volatile *)(& v->counter); __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; cmpxchgw %2,%1": "=a" (__ret), "+m" (*__ptr___0): "r" (__new), "0" (__old): "memory"); goto ldv_5679; case 4UL: __ptr___1 = (u32 volatile *)(& v->counter); __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; cmpxchgl %2,%1": "=a" (__ret), "+m" (*__ptr___1): "r" (__new), "0" (__old): "memory"); goto ldv_5679; case 8UL: __ptr___2 = (u64 volatile *)(& v->counter); __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; cmpxchgq %2,%1": "=a" (__ret), "+m" (*__ptr___2): "r" (__new), "0" (__old): "memory"); goto ldv_5679; default: __cmpxchg_wrong_size(); } ldv_5679: ; return (__ret); } } __inline static int __atomic_add_unless(atomic_t *v , int a , int u ) { int c ; int old ; long tmp ; long tmp___0 ; { c = atomic_read((atomic_t const *)v); ldv_5708: tmp = ldv__builtin_expect(c == u, 0L); if (tmp != 0L) { goto ldv_5707; } else { } old = atomic_cmpxchg(v, c, c + a); tmp___0 = ldv__builtin_expect(old == c, 1L); if (tmp___0 != 0L) { goto ldv_5707; } else { } c = old; goto ldv_5708; ldv_5707: ; return (c); } } __inline static int atomic_add_unless(atomic_t *v , int a , int u ) { int tmp ; { tmp = __atomic_add_unless(v, a, u); return (tmp != u); } } extern void lock_acquire(struct lockdep_map * , unsigned int , int , int , int , struct lockdep_map * , unsigned long ) ; extern void lock_release(struct lockdep_map * , int , unsigned long ) ; extern void mutex_lock_nested(struct mutex * , unsigned int ) ; extern void mutex_unlock(struct mutex * ) ; bool ldv_queue_work_on_33(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_35(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_34(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_37(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_36(struct workqueue_struct *ldv_func_arg1 ) ; __inline static int kref_sub(struct kref *kref , unsigned int count , void (*release)(struct kref * ) ) { int __ret_warn_on ; long tmp ; int tmp___0 ; { __ret_warn_on = (unsigned long )release == (unsigned long )((void (*)(struct kref * ))0); tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("include/linux/kref.h", 71); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); tmp___0 = atomic_sub_and_test((int )count, & kref->refcount); if (tmp___0 != 0) { (*release)(kref); return (1); } else { } return (0); } } __inline static int kref_put(struct kref *kref , void (*release)(struct kref * ) ) { int tmp ; { tmp = kref_sub(kref, 1U, release); return (tmp); } } __inline static int kref_put_mutex(struct kref *kref , void (*release)(struct kref * ) , struct mutex *lock ) { int __ret_warn_on ; long tmp ; int tmp___0 ; long tmp___1 ; int tmp___2 ; long tmp___3 ; { __ret_warn_on = (unsigned long )release == (unsigned long )((void (*)(struct kref * ))0); tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("include/linux/kref.h", 138); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); tmp___2 = atomic_add_unless(& kref->refcount, -1, 1); tmp___3 = ldv__builtin_expect(tmp___2 == 0, 0L); if (tmp___3 != 0L) { mutex_lock_nested(lock, 0U); tmp___0 = atomic_dec_and_test(& kref->refcount); tmp___1 = ldv__builtin_expect(tmp___0 == 0, 0L); if (tmp___1 != 0L) { mutex_unlock(lock); return (0); } else { } (*release)(kref); return (1); } else { } return (0); } } extern void kfree(void const * ) ; extern void *__kmalloc(size_t , gfp_t ) ; __inline static void *kmalloc(size_t size , gfp_t flags ) { void *tmp___2 ; { tmp___2 = __kmalloc(size, flags); return (tmp___2); } } __inline static void *kzalloc(size_t size , gfp_t flags ) { void *tmp ; { tmp = kmalloc(size, flags | 32768U); return (tmp); } } __inline static void ldv_stop(void) { { LDV_STOP: ; goto LDV_STOP; } } struct fb_var_screeninfo *psbfb_roll_ops_group0 ; struct fb_info *psbfb_ops_group0 ; int ldv_state_variable_54 ; struct drm_crtc *psb_fb_helper_funcs_group0 ; struct drm_device *psb_mode_funcs_group0 ; int ref_cnt ; int ldv_state_variable_55 ; int ldv_state_variable_59 ; int ldv_state_variable_58 ; int ldv_state_variable_56 ; struct drm_framebuffer *psb_fb_funcs_group0 ; int ldv_state_variable_60 ; struct fb_info *psbfb_roll_ops_group1 ; struct vm_area_struct *psbfb_vm_ops_group0 ; struct fb_info *psbfb_unaccel_ops_group0 ; int ldv_state_variable_57 ; void ldv_initialize_fb_ops_57(void) ; void ldv_initialize_drm_mode_config_funcs_54(void) ; void ldv_initialize_vm_operations_struct_59(void) ; void ldv_initialize_drm_fb_helper_funcs_55(void) ; void ldv_initialize_fb_ops_56(void) ; void ldv_initialize_fb_ops_58(void) ; void ldv_initialize_drm_framebuffer_funcs_60(void) ; extern int vm_insert_mixed(struct vm_area_struct * , unsigned long , unsigned long ) ; extern void dev_err(struct device const * , char const * , ...) ; __inline static struct apertures_struct *alloc_apertures(unsigned int max_num ) { struct apertures_struct *a ; void *tmp ; { tmp = kzalloc((unsigned long )max_num * 16UL + 8UL, 208U); a = (struct apertures_struct *)tmp; if ((unsigned long )a == (unsigned long )((struct apertures_struct *)0)) { return ((struct apertures_struct *)0); } else { } a->count = max_num; return (a); } } extern void cfb_fillrect(struct fb_info * , struct fb_fillrect const * ) ; extern void cfb_imageblit(struct fb_info * , struct fb_image const * ) ; extern int unregister_framebuffer(struct fb_info * ) ; extern struct fb_info *framebuffer_alloc(size_t , struct device * ) ; extern void framebuffer_release(struct fb_info * ) ; extern int fb_alloc_cmap(struct fb_cmap * , int , int ) ; extern void fb_dealloc_cmap(struct fb_cmap * ) ; extern int pci_bus_read_config_dword(struct pci_bus * , unsigned int , int , u32 * ) ; __inline static int pci_read_config_dword(struct pci_dev const *dev , int where , u32 *val ) { int tmp ; { tmp = pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); return (tmp); } } extern void drm_mode_config_init(struct drm_device * ) ; extern void drm_mode_config_cleanup(struct drm_device * ) ; extern int drm_framebuffer_init(struct drm_device * , struct drm_framebuffer * , struct drm_framebuffer_funcs const * ) ; extern void drm_framebuffer_cleanup(struct drm_framebuffer * ) ; extern void drm_framebuffer_unregister_private(struct drm_framebuffer * ) ; extern struct drm_property *drm_property_create_range(struct drm_device * , int , char const * , uint64_t , uint64_t ) ; extern int drm_mode_create_scaling_mode_property(struct drm_device * ) ; extern uint32_t drm_mode_legacy_fb_format(uint32_t , uint32_t ) ; extern void drm_fb_get_bpp_depth(uint32_t , unsigned int * , int * ) ; extern void drm_fb_helper_prepare(struct drm_device * , struct drm_fb_helper * , struct drm_fb_helper_funcs const * ) ; extern int drm_fb_helper_init(struct drm_device * , struct drm_fb_helper * , int , int ) ; extern void drm_fb_helper_fini(struct drm_fb_helper * ) ; extern int drm_fb_helper_blank(int , struct fb_info * ) ; extern int drm_fb_helper_set_par(struct fb_info * ) ; extern int drm_fb_helper_check_var(struct fb_var_screeninfo * , struct fb_info * ) ; extern void drm_fb_helper_fill_var(struct fb_info * , struct drm_fb_helper * , uint32_t , uint32_t ) ; extern void drm_fb_helper_fill_fix(struct fb_info * , uint32_t , uint32_t ) ; extern int drm_fb_helper_hotplug_event(struct drm_fb_helper * ) ; extern int drm_fb_helper_initial_config(struct drm_fb_helper * , int ) ; extern int drm_fb_helper_single_add_all_connectors(struct drm_fb_helper * ) ; extern void drm_helper_disable_unused_functions(struct drm_device * ) ; extern void drm_helper_mode_fill_fb_struct(struct drm_framebuffer * , struct drm_mode_fb_cmd2 * ) ; extern void drm_kms_helper_poll_fini(struct drm_device * ) ; void psb_intel_crtc_init(struct drm_device *dev , int pipe , struct psb_intel_mode_device *mode_dev ) ; __inline static struct gma_encoder *gma_attached_encoder(struct drm_connector *connector ) { struct drm_connector const *__mptr ; { __mptr = (struct drm_connector const *)connector; return (((struct gma_connector *)__mptr)->encoder); } } extern void drm_gem_object_free(struct kref * ) ; extern void drm_gem_private_object_init(struct drm_device * , struct drm_gem_object * , size_t ) ; __inline static void drm_gem_object_unreference(struct drm_gem_object *obj ) { { if ((unsigned long )obj != (unsigned long )((struct drm_gem_object *)0)) { kref_put(& obj->refcount, & drm_gem_object_free); } else { } return; } } __inline static void drm_gem_object_unreference_unlocked(struct drm_gem_object *obj ) { struct drm_device *dev ; int tmp ; { if ((unsigned long )obj == (unsigned long )((struct drm_gem_object *)0)) { return; } else { } dev = obj->dev; tmp = kref_put_mutex(& obj->refcount, & drm_gem_object_free, & dev->struct_mutex); if (tmp != 0) { mutex_unlock(& dev->struct_mutex); } else { lock_acquire(& dev->struct_mutex.dep_map, 0U, 0, 0, 1, (struct lockdep_map *)0, 0UL); lock_release(& dev->struct_mutex.dep_map, 0, 0UL); } return; } } extern int drm_gem_handle_create(struct drm_file * , struct drm_gem_object * , u32 * ) ; extern struct drm_gem_object *drm_gem_object_lookup(struct drm_device * , struct drm_file * , u32 ) ; struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev , int len , char const *name , int backed , u32 align ) ; void psb_gtt_free_range(struct drm_device *dev , struct gtt_range *gt ) ; void psb_gtt_roll(struct drm_device *dev , struct gtt_range *r , int roll ) ; void psb_modeset_init(struct drm_device *dev ) ; void psb_modeset_cleanup(struct drm_device *dev ) ; int psb_fbdev_init(struct drm_device *dev ) ; int gma_connector_clones(struct drm_device *dev , int type_mask ) ; static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb ) ; static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb , struct drm_file *file_priv , unsigned int *handle ) ; static struct drm_framebuffer_funcs const psb_fb_funcs = {& psb_user_framebuffer_destroy, & psb_user_framebuffer_create_handle, 0}; static int psbfb_setcolreg(unsigned int regno , unsigned int red , unsigned int green , unsigned int blue , unsigned int transp , struct fb_info *info ) { struct psb_fbdev *fbdev ; struct drm_framebuffer *fb ; uint32_t v ; { fbdev = (struct psb_fbdev *)info->par; fb = fbdev->psb_fb_helper.fb; if ((unsigned long )fb == (unsigned long )((struct drm_framebuffer *)0)) { return (-12); } else { } if (regno > 255U) { return (1); } else { } red = (((red << (int )info->var.red.length) - red) + 32767U) >> 16; blue = (((blue << (int )info->var.blue.length) - blue) + 32767U) >> 16; green = (((green << (int )info->var.green.length) - green) + 32767U) >> 16; transp = (((transp << (int )info->var.transp.length) - transp) + 32767U) >> 16; v = (((red << (int )info->var.red.offset) | (green << (int )info->var.green.offset)) | (blue << (int )info->var.blue.offset)) | (transp << (int )info->var.transp.offset); if (regno <= 15U) { switch (fb->bits_per_pixel) { case 16: *((uint32_t *)info->pseudo_palette + (unsigned long )regno) = v; goto ldv_42753; case 24: ; case 32: *((uint32_t *)info->pseudo_palette + (unsigned long )regno) = v; goto ldv_42753; } ldv_42753: ; } else { } return (0); } } static int psbfb_pan(struct fb_var_screeninfo *var , struct fb_info *info ) { struct psb_fbdev *fbdev ; struct psb_framebuffer *psbfb ; struct drm_device *dev ; int pages ; { fbdev = (struct psb_fbdev *)info->par; psbfb = & fbdev->pfb; dev = psbfb->base.dev; if ((psbfb->gtt)->npage != 0) { pages = (int )(info->fix.line_length >> 12); psb_gtt_roll(dev, psbfb->gtt, (int )(var->yoffset * (__u32 )pages)); } else { } return (0); } } static int psbfb_vm_fault(struct vm_area_struct *vma , struct vm_fault *vmf ) { struct psb_framebuffer *psbfb ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; int page_num ; int i ; unsigned long address ; int ret ; unsigned long pfn ; unsigned long phys_addr ; pgprot_t __constr_expr_0 ; unsigned long tmp ; long tmp___0 ; long tmp___1 ; { psbfb = (struct psb_framebuffer *)vma->vm_private_data; dev = psbfb->base.dev; dev_priv = (struct drm_psb_private *)dev->dev_private; phys_addr = (unsigned long )dev_priv->stolen_base + (unsigned long )(psbfb->gtt)->offset; page_num = (int )((vma->vm_end - vma->vm_start) >> 12); address = (unsigned long )vmf->virtual_address - (vmf->pgoff << 12); if ((unsigned int )boot_cpu_data.x86 > 3U) { tmp = cachemode2protval(2); __constr_expr_0.pgprot = vma->vm_page_prot.pgprot | tmp; vma->vm_page_prot = __constr_expr_0; } else { vma->vm_page_prot = vma->vm_page_prot; } i = 0; goto ldv_42780; ldv_42779: pfn = phys_addr >> 12; ret = vm_insert_mixed(vma, address, pfn); tmp___1 = ldv__builtin_expect((long )(ret == -16 || (ret != 0 && i > 0)), 0L); if (tmp___1 != 0L) { goto ldv_42778; } else { tmp___0 = ldv__builtin_expect(ret != 0, 0L); if (tmp___0 != 0L) { ret = ret == -12 ? 1 : 2; return (ret); } else { } } address = address + 4096UL; phys_addr = phys_addr + 4096UL; i = i + 1; ldv_42780: ; if (i < page_num) { goto ldv_42779; } else { } ldv_42778: ; return (256); } } static void psbfb_vm_open(struct vm_area_struct *vma ) { { return; } } static void psbfb_vm_close(struct vm_area_struct *vma ) { { return; } } static struct vm_operations_struct const psbfb_vm_ops = {& psbfb_vm_open, & psbfb_vm_close, & psbfb_vm_fault, 0, 0, 0, 0, 0, 0, 0, 0}; static int psbfb_mmap(struct fb_info *info , struct vm_area_struct *vma ) { struct psb_fbdev *fbdev ; struct psb_framebuffer *psbfb ; { fbdev = (struct psb_fbdev *)info->par; psbfb = & fbdev->pfb; if (vma->vm_pgoff != 0UL) { return (-22); } else { } if (vma->vm_pgoff > 4503599627370495UL) { return (-22); } else { } if ((unsigned long )psbfb->addr_space == (unsigned long )((struct address_space *)0)) { psbfb->addr_space = (vma->vm_file)->f_mapping; } else { } vma->vm_ops = & psbfb_vm_ops; vma->vm_private_data = (void *)psbfb; vma->vm_flags = vma->vm_flags | 335822848UL; return (0); } } static int psbfb_ioctl(struct fb_info *info , unsigned int cmd , unsigned long arg ) { { return (-25); } } static struct fb_ops psbfb_ops = {& __this_module, 0, 0, 0, 0, & drm_fb_helper_check_var, & drm_fb_helper_set_par, & psbfb_setcolreg, 0, & drm_fb_helper_blank, 0, & cfb_fillrect, & psbfb_copyarea, & cfb_imageblit, 0, 0, & psbfb_sync, & psbfb_ioctl, 0, & psbfb_mmap, 0, 0, 0, 0}; static struct fb_ops psbfb_roll_ops = {& __this_module, 0, 0, 0, 0, & drm_fb_helper_check_var, & drm_fb_helper_set_par, & psbfb_setcolreg, 0, & drm_fb_helper_blank, & psbfb_pan, & cfb_fillrect, & cfb_copyarea, & cfb_imageblit, 0, 0, 0, & psbfb_ioctl, 0, & psbfb_mmap, 0, 0, 0, 0}; static struct fb_ops psbfb_unaccel_ops = {& __this_module, 0, 0, 0, 0, & drm_fb_helper_check_var, & drm_fb_helper_set_par, & psbfb_setcolreg, 0, & drm_fb_helper_blank, 0, & cfb_fillrect, & cfb_copyarea, & cfb_imageblit, 0, 0, 0, & psbfb_ioctl, 0, & psbfb_mmap, 0, 0, 0, 0}; static int psb_framebuffer_init(struct drm_device *dev , struct psb_framebuffer *fb , struct drm_mode_fb_cmd2 *mode_cmd , struct gtt_range *gt ) { u32 bpp ; u32 depth ; int ret ; { drm_fb_get_bpp_depth(mode_cmd->pixel_format, & depth, (int *)(& bpp)); if ((mode_cmd->pitches[0] & 63U) != 0U) { return (-22); } else { } switch (bpp) { case 8U: ; case 16U: ; case 24U: ; case 32U: ; goto ldv_42815; default: ; return (-22); } ldv_42815: drm_helper_mode_fill_fb_struct(& fb->base, mode_cmd); fb->gtt = gt; ret = drm_framebuffer_init(dev, & fb->base, & psb_fb_funcs); if (ret != 0) { dev_err((struct device const *)dev->dev, "framebuffer init failed: %d\n", ret); return (ret); } else { } return (0); } } static struct drm_framebuffer *psb_framebuffer_create(struct drm_device *dev , struct drm_mode_fb_cmd2 *mode_cmd , struct gtt_range *gt ) { struct psb_framebuffer *fb ; int ret ; void *tmp ; void *tmp___0 ; void *tmp___1 ; { tmp = kzalloc(192UL, 208U); fb = (struct psb_framebuffer *)tmp; if ((unsigned long )fb == (unsigned long )((struct psb_framebuffer *)0)) { tmp___0 = ERR_PTR(-12L); return ((struct drm_framebuffer *)tmp___0); } else { } ret = psb_framebuffer_init(dev, fb, mode_cmd, gt); if (ret != 0) { kfree((void const *)fb); tmp___1 = ERR_PTR((long )ret); return ((struct drm_framebuffer *)tmp___1); } else { } return (& fb->base); } } static struct gtt_range *psbfb_alloc(struct drm_device *dev , int aligned_size ) { struct gtt_range *backing ; { backing = psb_gtt_alloc_range(dev, aligned_size, "fb", 1, 4096U); if ((unsigned long )backing != (unsigned long )((struct gtt_range *)0)) { drm_gem_private_object_init(dev, & backing->gem, (size_t )aligned_size); return (backing); } else { } return ((struct gtt_range *)0); } } static int psbfb_create(struct psb_fbdev *fbdev , struct drm_fb_helper_surface_size *sizes ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct fb_info *info ; struct drm_framebuffer *fb ; struct psb_framebuffer *psbfb ; struct drm_mode_fb_cmd2 mode_cmd ; struct device *device ; int size ; int ret ; struct gtt_range *backing ; u32 bpp ; u32 depth ; int gtt_roll ; int pitch_lines ; struct _ddebug descriptor ; long tmp ; { dev = fbdev->psb_fb_helper.dev; dev_priv = (struct drm_psb_private *)dev->dev_private; psbfb = & fbdev->pfb; device = & (dev->pdev)->dev; gtt_roll = 0; pitch_lines = 0; mode_cmd.width = sizes->surface_width; mode_cmd.height = sizes->surface_height; bpp = sizes->surface_bpp; depth = sizes->surface_depth; if (bpp == 24U) { bpp = 32U; } else { } ldv_42847: mode_cmd.pitches[0] = ((mode_cmd.width * ((bpp + 7U) / 8U) + (__u32 )(4096 >> pitch_lines)) - 1U) & - ((unsigned int )(4096 >> pitch_lines)); size = (int )(mode_cmd.pitches[0] * mode_cmd.height); size = (size + 4095) & -4096; backing = psbfb_alloc(dev, size); if (pitch_lines != 0) { pitch_lines = pitch_lines * 2; } else { pitch_lines = 1; } gtt_roll = gtt_roll + 1; if ((unsigned long )backing == (unsigned long )((struct gtt_range *)0) && pitch_lines <= 16) { goto ldv_42847; } else { } pitch_lines = pitch_lines / 2; if ((unsigned long )backing == (unsigned long )((struct gtt_range *)0)) { gtt_roll = 0; pitch_lines = 64; mode_cmd.pitches[0] = (mode_cmd.width * ((bpp + 7U) / 8U) + 63U) & 4294967232U; size = (int )(mode_cmd.pitches[0] * mode_cmd.height); size = (size + 4095) & -4096; backing = psbfb_alloc(dev, size); if ((unsigned long )backing == (unsigned long )((struct gtt_range *)0)) { return (-12); } else { } } else { } memset((void *)dev_priv->vram_addr + (unsigned long )backing->offset, 0, (size_t )size); mutex_lock_nested(& dev->struct_mutex, 0U); info = framebuffer_alloc(0UL, device); if ((unsigned long )info == (unsigned long )((struct fb_info *)0)) { ret = -12; goto out_err1; } else { } info->par = (void *)fbdev; mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); ret = psb_framebuffer_init(dev, psbfb, & mode_cmd, backing); if (ret != 0) { goto out_unref; } else { } fb = & psbfb->base; psbfb->fbdev = info; fbdev->psb_fb_helper.fb = fb; fbdev->psb_fb_helper.fbdev = info; drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); strcpy((char *)(& info->fix.id), "psbdrmfb"); info->flags = 1; if ((unsigned int )*((unsigned char *)dev_priv->ops + 8UL) != 0U && pitch_lines > 8) { info->fbops = & psbfb_ops; } else if (gtt_roll != 0) { info->fbops = & psbfb_roll_ops; info->flags = info->flags | 8192; } else { info->fbops = & psbfb_unaccel_ops; } ret = fb_alloc_cmap(& info->cmap, 256, 0); if (ret != 0) { ret = -12; goto out_unref; } else { } info->fix.smem_start = (unsigned long )dev->mode_config.fb_base; info->fix.smem_len = (__u32 )size; info->fix.ywrapstep = (__u16 )gtt_roll; info->fix.ypanstep = 0U; info->screen_base = (char *)dev_priv->vram_addr + (unsigned long )backing->offset; info->screen_size = (unsigned long )size; if (dev_priv->gtt.stolen_size != 0UL) { info->apertures = alloc_apertures(1U); if ((unsigned long )info->apertures == (unsigned long )((struct apertures_struct *)0)) { ret = -12; goto out_unref; } else { } (info->apertures)->ranges[0].base = dev->mode_config.fb_base; (info->apertures)->ranges[0].size = (resource_size_t )dev_priv->gtt.stolen_size; } else { } drm_fb_helper_fill_var(info, & fbdev->psb_fb_helper, sizes->fb_width, sizes->fb_height); info->fix.mmio_start = (unsigned long )(dev->pdev)->resource[0].start; info->fix.mmio_len = (dev->pdev)->resource[0].start != 0ULL || (dev->pdev)->resource[0].end != (dev->pdev)->resource[0].start ? ((__u32 )(dev->pdev)->resource[0].end - (__u32 )(dev->pdev)->resource[0].start) + 1U : 0U; descriptor.modname = "gma500_gfx"; descriptor.function = "psbfb_create"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/framebuffer.c"; descriptor.format = "allocated %dx%d fb\n"; descriptor.lineno = 477U; descriptor.flags = 0U; tmp = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "allocated %dx%d fb\n", psbfb->base.width, psbfb->base.height); } else { } mutex_unlock(& dev->struct_mutex); return (0); out_unref: ; if ((int )backing->stolen) { psb_gtt_free_range(dev, backing); } else { drm_gem_object_unreference(& backing->gem); } out_err1: mutex_unlock(& dev->struct_mutex); psb_gtt_free_range(dev, backing); return (ret); } } static struct drm_framebuffer *psb_user_framebuffer_create(struct drm_device *dev , struct drm_file *filp , struct drm_mode_fb_cmd2 *cmd ) { struct gtt_range *r ; struct drm_gem_object *obj ; void *tmp ; struct drm_gem_object const *__mptr ; struct drm_framebuffer *tmp___0 ; { obj = drm_gem_object_lookup(dev, filp, cmd->handles[0]); if ((unsigned long )obj == (unsigned long )((struct drm_gem_object *)0)) { tmp = ERR_PTR(-2L); return ((struct drm_framebuffer *)tmp); } else { } __mptr = (struct drm_gem_object const *)obj; r = (struct gtt_range *)__mptr + 0xffffffffffffffc0UL; tmp___0 = psb_framebuffer_create(dev, cmd, r); return (tmp___0); } } static void psbfb_gamma_set(struct drm_crtc *crtc , u16 red , u16 green , u16 blue , int regno ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; gma_crtc->lut_r[regno] = (u8 )((int )red >> 8); gma_crtc->lut_g[regno] = (u8 )((int )green >> 8); gma_crtc->lut_b[regno] = (u8 )((int )blue >> 8); return; } } static void psbfb_gamma_get(struct drm_crtc *crtc , u16 *red , u16 *green , u16 *blue , int regno ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; *red = (int )((u16 )gma_crtc->lut_r[regno]) << 8U; *green = (int )((u16 )gma_crtc->lut_g[regno]) << 8U; *blue = (int )((u16 )gma_crtc->lut_b[regno]) << 8U; return; } } static int psbfb_probe(struct drm_fb_helper *helper , struct drm_fb_helper_surface_size *sizes ) { struct psb_fbdev *psb_fbdev ; struct drm_fb_helper const *__mptr ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; int bytespp ; int tmp ; { __mptr = (struct drm_fb_helper const *)helper; psb_fbdev = (struct psb_fbdev *)__mptr; dev = psb_fbdev->psb_fb_helper.dev; dev_priv = (struct drm_psb_private *)dev->dev_private; bytespp = (int )(sizes->surface_bpp / 8U); if (bytespp == 3) { bytespp = 4; } else { } if ((unsigned long )(((sizes->fb_width * (u32 )bytespp + 63U) & 4294967232U) * sizes->fb_height) > dev_priv->vram_stolen_size) { sizes->surface_bpp = 16U; sizes->surface_depth = 16U; } else { } tmp = psbfb_create(psb_fbdev, sizes); return (tmp); } } static struct drm_fb_helper_funcs const psb_fb_helper_funcs = {& psbfb_gamma_set, & psbfb_gamma_get, & psbfb_probe, 0}; static int psb_fbdev_destroy(struct drm_device *dev , struct psb_fbdev *fbdev ) { struct fb_info *info ; struct psb_framebuffer *psbfb ; { psbfb = & fbdev->pfb; if ((unsigned long )fbdev->psb_fb_helper.fbdev != (unsigned long )((struct fb_info *)0)) { info = fbdev->psb_fb_helper.fbdev; unregister_framebuffer(info); if (info->cmap.len != 0U) { fb_dealloc_cmap(& info->cmap); } else { } framebuffer_release(info); } else { } drm_fb_helper_fini(& fbdev->psb_fb_helper); drm_framebuffer_unregister_private(& psbfb->base); drm_framebuffer_cleanup(& psbfb->base); if ((unsigned long )psbfb->gtt != (unsigned long )((struct gtt_range *)0)) { drm_gem_object_unreference(& (psbfb->gtt)->gem); } else { } return (0); } } int psb_fbdev_init(struct drm_device *dev ) { struct psb_fbdev *fbdev ; struct drm_psb_private *dev_priv ; int ret ; void *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = kzalloc(352UL, 208U); fbdev = (struct psb_fbdev *)tmp; if ((unsigned long )fbdev == (unsigned long )((struct psb_fbdev *)0)) { dev_err((struct device const *)dev->dev, "no memory\n"); return (-12); } else { } dev_priv->fbdev = (void *)fbdev; drm_fb_helper_prepare(dev, & fbdev->psb_fb_helper, & psb_fb_helper_funcs); ret = drm_fb_helper_init(dev, & fbdev->psb_fb_helper, (dev_priv->ops)->crtcs, 4); if (ret != 0) { goto free; } else { } ret = drm_fb_helper_single_add_all_connectors(& fbdev->psb_fb_helper); if (ret != 0) { goto fini; } else { } drm_helper_disable_unused_functions(dev); ret = drm_fb_helper_initial_config(& fbdev->psb_fb_helper, 32); if (ret != 0) { goto fini; } else { } return (0); fini: drm_fb_helper_fini(& fbdev->psb_fb_helper); free: kfree((void const *)fbdev); return (ret); } } static void psb_fbdev_fini(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if ((unsigned long )dev_priv->fbdev == (unsigned long )((void *)0)) { return; } else { } psb_fbdev_destroy(dev, (struct psb_fbdev *)dev_priv->fbdev); kfree((void const *)dev_priv->fbdev); dev_priv->fbdev = (void *)0; return; } } static void psbfb_output_poll_changed(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_fbdev *fbdev ; { dev_priv = (struct drm_psb_private *)dev->dev_private; fbdev = (struct psb_fbdev *)dev_priv->fbdev; drm_fb_helper_hotplug_event(& fbdev->psb_fb_helper); return; } } static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb , struct drm_file *file_priv , unsigned int *handle ) { struct psb_framebuffer *psbfb ; struct drm_framebuffer const *__mptr ; struct gtt_range *r ; int tmp ; { __mptr = (struct drm_framebuffer const *)fb; psbfb = (struct psb_framebuffer *)__mptr; r = psbfb->gtt; tmp = drm_gem_handle_create(file_priv, & r->gem, handle); return (tmp); } } static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb ) { struct psb_framebuffer *psbfb ; struct drm_framebuffer const *__mptr ; struct gtt_range *r ; { __mptr = (struct drm_framebuffer const *)fb; psbfb = (struct psb_framebuffer *)__mptr; r = psbfb->gtt; drm_framebuffer_cleanup(fb); drm_gem_object_unreference_unlocked(& r->gem); kfree((void const *)fb); return; } } static struct drm_mode_config_funcs const psb_mode_funcs = {& psb_user_framebuffer_create, & psbfb_output_poll_changed, 0, 0, 0, 0, 0}; static int psb_create_backlight_property(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct drm_property *backlight ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if ((unsigned long )dev_priv->backlight_property != (unsigned long )((struct drm_property *)0)) { return (0); } else { } backlight = drm_property_create_range(dev, 0, "backlight", 0ULL, 100ULL); dev_priv->backlight_property = backlight; return (0); } } static void psb_setup_outputs(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct drm_connector *connector ; struct list_head const *__mptr ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct drm_encoder *encoder ; int crtc_mask ; int clone_mask ; int tmp___0 ; struct list_head const *__mptr___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; drm_mode_create_scaling_mode_property(dev); psb_create_backlight_property(dev); (*((dev_priv->ops)->output_init))(dev); __mptr = (struct list_head const *)dev->mode_config.connector_list.next; connector = (struct drm_connector *)__mptr + 0xffffffffffffffe8UL; goto ldv_42961; ldv_42960: tmp = gma_attached_encoder(connector); gma_encoder = tmp; encoder = & gma_encoder->base; crtc_mask = 0; clone_mask = 0; switch (gma_encoder->type) { case 1: crtc_mask = 1; clone_mask = 2; goto ldv_42952; case 3: crtc_mask = (dev_priv->ops)->sdvo_mask; clone_mask = 8; goto ldv_42952; case 4: crtc_mask = (dev_priv->ops)->lvds_mask; clone_mask = 16; goto ldv_42952; case 7: crtc_mask = 1; clone_mask = 128; goto ldv_42952; case 8: crtc_mask = 4; clone_mask = 256; goto ldv_42952; case 6: crtc_mask = (dev_priv->ops)->hdmi_mask; clone_mask = 64; goto ldv_42952; case 9: crtc_mask = 3; clone_mask = 512; goto ldv_42952; case 10: crtc_mask = 2; clone_mask = 1024; } ldv_42952: encoder->possible_crtcs = (uint32_t )crtc_mask; tmp___0 = gma_connector_clones(dev, clone_mask); encoder->possible_clones = (uint32_t )tmp___0; __mptr___0 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; ldv_42961: ; if ((unsigned long )(& connector->head) != (unsigned long )(& dev->mode_config.connector_list)) { goto ldv_42960; } else { } return; } } void psb_modeset_init(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; int i ; { dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; drm_mode_config_init(dev); dev->mode_config.min_width = 0; dev->mode_config.min_height = 0; dev->mode_config.funcs = & psb_mode_funcs; pci_read_config_dword((struct pci_dev const *)dev->pdev, 92, (u32 *)(& dev->mode_config.fb_base)); i = 0; goto ldv_42970; ldv_42969: psb_intel_crtc_init(dev, i, mode_dev); i = i + 1; ldv_42970: ; if ((uint32_t )i < dev_priv->num_pipe) { goto ldv_42969; } else { } dev->mode_config.max_width = 4096; dev->mode_config.max_height = 4096; psb_setup_outputs(dev); if ((unsigned long )(dev_priv->ops)->errata != (unsigned long )((void (*/* const */)(struct drm_device * ))0)) { (*((dev_priv->ops)->errata))(dev); } else { } dev_priv->modeset = 1; return; } } void psb_modeset_cleanup(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if ((int )dev_priv->modeset) { mutex_lock_nested(& dev->struct_mutex, 0U); drm_kms_helper_poll_fini(dev); psb_fbdev_fini(dev); drm_mode_config_cleanup(dev); mutex_unlock(& dev->struct_mutex); } else { } return; } } extern int ldv_probe_60(void) ; void ldv_initialize_fb_ops_57(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(160UL); psbfb_roll_ops_group0 = (struct fb_var_screeninfo *)tmp; tmp___0 = ldv_init_zalloc(1608UL); psbfb_roll_ops_group1 = (struct fb_info *)tmp___0; return; } } void ldv_initialize_drm_mode_config_funcs_54(void) { void *tmp ; { tmp = ldv_init_zalloc(3320UL); psb_mode_funcs_group0 = (struct drm_device *)tmp; return; } } void ldv_initialize_vm_operations_struct_59(void) { void *tmp ; { tmp = ldv_init_zalloc(184UL); psbfb_vm_ops_group0 = (struct vm_area_struct *)tmp; return; } } void ldv_initialize_drm_fb_helper_funcs_55(void) { void *tmp ; { tmp = ldv_init_zalloc(1160UL); psb_fb_helper_funcs_group0 = (struct drm_crtc *)tmp; return; } } void ldv_initialize_fb_ops_56(void) { void *tmp ; { tmp = ldv_init_zalloc(1608UL); psbfb_unaccel_ops_group0 = (struct fb_info *)tmp; return; } } void ldv_initialize_fb_ops_58(void) { void *tmp ; { tmp = ldv_init_zalloc(1608UL); psbfb_ops_group0 = (struct fb_info *)tmp; return; } } void ldv_initialize_drm_framebuffer_funcs_60(void) { void *tmp ; { tmp = ldv_init_zalloc(168UL); psb_fb_funcs_group0 = (struct drm_framebuffer *)tmp; return; } } void ldv_main_exported_59(void) { struct vm_fault *ldvarg82 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(56UL); ldvarg82 = (struct vm_fault *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_59 == 1) { psbfb_vm_fault(psbfb_vm_ops_group0, ldvarg82); ldv_state_variable_59 = 1; } else { } if (ldv_state_variable_59 == 2) { psbfb_vm_fault(psbfb_vm_ops_group0, ldvarg82); ldv_state_variable_59 = 2; } else { } goto ldv_43004; case 1: ; if (ldv_state_variable_59 == 2) { psbfb_vm_close(psbfb_vm_ops_group0); ldv_state_variable_59 = 1; } else { } goto ldv_43004; case 2: ; if (ldv_state_variable_59 == 1) { psbfb_vm_open(psbfb_vm_ops_group0); ldv_state_variable_59 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_43004; default: ldv_stop(); } ldv_43004: ; return; } } void ldv_main_exported_60(void) { unsigned int *ldvarg190 ; void *tmp ; struct drm_file *ldvarg191 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(4UL); ldvarg190 = (unsigned int *)tmp; tmp___0 = ldv_init_zalloc(744UL); ldvarg191 = (struct drm_file *)tmp___0; tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_60 == 2) { psb_user_framebuffer_destroy(psb_fb_funcs_group0); ldv_state_variable_60 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_43014; case 1: ; if (ldv_state_variable_60 == 2) { psb_user_framebuffer_create_handle(psb_fb_funcs_group0, ldvarg191, ldvarg190); ldv_state_variable_60 = 2; } else { } if (ldv_state_variable_60 == 1) { psb_user_framebuffer_create_handle(psb_fb_funcs_group0, ldvarg191, ldvarg190); ldv_state_variable_60 = 1; } else { } goto ldv_43014; case 2: ; if (ldv_state_variable_60 == 1) { ldv_probe_60(); ldv_state_variable_60 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_43014; default: ldv_stop(); } ldv_43014: ; return; } } void ldv_main_exported_57(void) { unsigned int ldvarg66 ; unsigned int ldvarg64 ; int ldvarg61 ; unsigned int ldvarg65 ; unsigned long ldvarg62 ; struct fb_image *ldvarg69 ; void *tmp ; unsigned int ldvarg68 ; struct vm_area_struct *ldvarg71 ; void *tmp___0 ; struct fb_fillrect *ldvarg60 ; void *tmp___1 ; unsigned int ldvarg67 ; struct fb_copyarea *ldvarg70 ; void *tmp___2 ; unsigned int ldvarg63 ; int tmp___3 ; { tmp = ldv_init_zalloc(80UL); ldvarg69 = (struct fb_image *)tmp; tmp___0 = ldv_init_zalloc(184UL); ldvarg71 = (struct vm_area_struct *)tmp___0; tmp___1 = ldv_init_zalloc(24UL); ldvarg60 = (struct fb_fillrect *)tmp___1; tmp___2 = ldv_init_zalloc(24UL); ldvarg70 = (struct fb_copyarea *)tmp___2; ldv_memset((void *)(& ldvarg66), 0, 4UL); ldv_memset((void *)(& ldvarg64), 0, 4UL); ldv_memset((void *)(& ldvarg61), 0, 4UL); ldv_memset((void *)(& ldvarg65), 0, 4UL); ldv_memset((void *)(& ldvarg62), 0, 8UL); ldv_memset((void *)(& ldvarg68), 0, 4UL); ldv_memset((void *)(& ldvarg67), 0, 4UL); ldv_memset((void *)(& ldvarg63), 0, 4UL); tmp___3 = __VERIFIER_nondet_int(); switch (tmp___3) { case 0: ; if (ldv_state_variable_57 == 1) { psbfb_mmap(psbfb_roll_ops_group1, ldvarg71); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 1: ; if (ldv_state_variable_57 == 1) { psbfb_pan(psbfb_roll_ops_group0, psbfb_roll_ops_group1); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 2: ; if (ldv_state_variable_57 == 1) { cfb_copyarea(psbfb_roll_ops_group1, (struct fb_copyarea const *)ldvarg70); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 3: ; if (ldv_state_variable_57 == 1) { cfb_imageblit(psbfb_roll_ops_group1, (struct fb_image const *)ldvarg69); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 4: ; if (ldv_state_variable_57 == 1) { drm_fb_helper_set_par(psbfb_roll_ops_group1); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 5: ; if (ldv_state_variable_57 == 1) { psbfb_setcolreg(ldvarg65, ldvarg67, ldvarg66, ldvarg64, ldvarg68, psbfb_roll_ops_group1); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 6: ; if (ldv_state_variable_57 == 1) { psbfb_ioctl(psbfb_roll_ops_group1, ldvarg63, ldvarg62); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 7: ; if (ldv_state_variable_57 == 1) { drm_fb_helper_blank(ldvarg61, psbfb_roll_ops_group1); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 8: ; if (ldv_state_variable_57 == 1) { drm_fb_helper_check_var(psbfb_roll_ops_group0, psbfb_roll_ops_group1); ldv_state_variable_57 = 1; } else { } goto ldv_43034; case 9: ; if (ldv_state_variable_57 == 1) { cfb_fillrect(psbfb_roll_ops_group1, (struct fb_fillrect const *)ldvarg60); ldv_state_variable_57 = 1; } else { } goto ldv_43034; default: ldv_stop(); } ldv_43034: ; return; } } void ldv_main_exported_56(void) { unsigned int ldvarg201 ; struct fb_copyarea *ldvarg206 ; void *tmp ; unsigned int ldvarg199 ; unsigned long ldvarg198 ; struct fb_image *ldvarg205 ; void *tmp___0 ; int ldvarg197 ; struct fb_var_screeninfo *ldvarg196 ; void *tmp___1 ; unsigned int ldvarg202 ; struct fb_fillrect *ldvarg195 ; void *tmp___2 ; struct vm_area_struct *ldvarg207 ; void *tmp___3 ; unsigned int ldvarg200 ; unsigned int ldvarg203 ; unsigned int ldvarg204 ; int tmp___4 ; { tmp = ldv_init_zalloc(24UL); ldvarg206 = (struct fb_copyarea *)tmp; tmp___0 = ldv_init_zalloc(80UL); ldvarg205 = (struct fb_image *)tmp___0; tmp___1 = ldv_init_zalloc(160UL); ldvarg196 = (struct fb_var_screeninfo *)tmp___1; tmp___2 = ldv_init_zalloc(24UL); ldvarg195 = (struct fb_fillrect *)tmp___2; tmp___3 = ldv_init_zalloc(184UL); ldvarg207 = (struct vm_area_struct *)tmp___3; ldv_memset((void *)(& ldvarg201), 0, 4UL); ldv_memset((void *)(& ldvarg199), 0, 4UL); ldv_memset((void *)(& ldvarg198), 0, 8UL); ldv_memset((void *)(& ldvarg197), 0, 4UL); ldv_memset((void *)(& ldvarg202), 0, 4UL); ldv_memset((void *)(& ldvarg200), 0, 4UL); ldv_memset((void *)(& ldvarg203), 0, 4UL); ldv_memset((void *)(& ldvarg204), 0, 4UL); tmp___4 = __VERIFIER_nondet_int(); switch (tmp___4) { case 0: ; if (ldv_state_variable_56 == 1) { psbfb_mmap(psbfb_unaccel_ops_group0, ldvarg207); ldv_state_variable_56 = 1; } else { } goto ldv_43062; case 1: ; if (ldv_state_variable_56 == 1) { cfb_copyarea(psbfb_unaccel_ops_group0, (struct fb_copyarea const *)ldvarg206); ldv_state_variable_56 = 1; } else { } goto ldv_43062; case 2: ; if (ldv_state_variable_56 == 1) { cfb_imageblit(psbfb_unaccel_ops_group0, (struct fb_image const *)ldvarg205); ldv_state_variable_56 = 1; } else { } goto ldv_43062; case 3: ; if (ldv_state_variable_56 == 1) { drm_fb_helper_set_par(psbfb_unaccel_ops_group0); ldv_state_variable_56 = 1; } else { } goto ldv_43062; case 4: ; if (ldv_state_variable_56 == 1) { psbfb_setcolreg(ldvarg201, ldvarg203, ldvarg202, ldvarg200, ldvarg204, psbfb_unaccel_ops_group0); ldv_state_variable_56 = 1; } else { } goto ldv_43062; case 5: ; if (ldv_state_variable_56 == 1) { psbfb_ioctl(psbfb_unaccel_ops_group0, ldvarg199, ldvarg198); ldv_state_variable_56 = 1; } else { } goto ldv_43062; case 6: ; if (ldv_state_variable_56 == 1) { drm_fb_helper_blank(ldvarg197, psbfb_unaccel_ops_group0); ldv_state_variable_56 = 1; } else { } goto ldv_43062; case 7: ; if (ldv_state_variable_56 == 1) { drm_fb_helper_check_var(ldvarg196, psbfb_unaccel_ops_group0); ldv_state_variable_56 = 1; } else { } goto ldv_43062; case 8: ; if (ldv_state_variable_56 == 1) { cfb_fillrect(psbfb_unaccel_ops_group0, (struct fb_fillrect const *)ldvarg195); ldv_state_variable_56 = 1; } else { } goto ldv_43062; default: ldv_stop(); } ldv_43062: ; return; } } void ldv_main_exported_58(void) { struct fb_var_screeninfo *ldvarg160 ; void *tmp ; unsigned long ldvarg162 ; int ldvarg161 ; struct fb_image *ldvarg169 ; void *tmp___0 ; unsigned int ldvarg166 ; struct fb_fillrect *ldvarg159 ; void *tmp___1 ; unsigned int ldvarg165 ; unsigned int ldvarg163 ; unsigned int ldvarg168 ; struct vm_area_struct *ldvarg171 ; void *tmp___2 ; struct fb_copyarea *ldvarg170 ; void *tmp___3 ; unsigned int ldvarg164 ; unsigned int ldvarg167 ; int tmp___4 ; { tmp = ldv_init_zalloc(160UL); ldvarg160 = (struct fb_var_screeninfo *)tmp; tmp___0 = ldv_init_zalloc(80UL); ldvarg169 = (struct fb_image *)tmp___0; tmp___1 = ldv_init_zalloc(24UL); ldvarg159 = (struct fb_fillrect *)tmp___1; tmp___2 = ldv_init_zalloc(184UL); ldvarg171 = (struct vm_area_struct *)tmp___2; tmp___3 = ldv_init_zalloc(24UL); ldvarg170 = (struct fb_copyarea *)tmp___3; ldv_memset((void *)(& ldvarg162), 0, 8UL); ldv_memset((void *)(& ldvarg161), 0, 4UL); ldv_memset((void *)(& ldvarg166), 0, 4UL); ldv_memset((void *)(& ldvarg165), 0, 4UL); ldv_memset((void *)(& ldvarg163), 0, 4UL); ldv_memset((void *)(& ldvarg168), 0, 4UL); ldv_memset((void *)(& ldvarg164), 0, 4UL); ldv_memset((void *)(& ldvarg167), 0, 4UL); tmp___4 = __VERIFIER_nondet_int(); switch (tmp___4) { case 0: ; if (ldv_state_variable_58 == 1) { psbfb_mmap(psbfb_ops_group0, ldvarg171); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 1: ; if (ldv_state_variable_58 == 1) { psbfb_copyarea(psbfb_ops_group0, (struct fb_copyarea const *)ldvarg170); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 2: ; if (ldv_state_variable_58 == 1) { psbfb_sync(psbfb_ops_group0); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 3: ; if (ldv_state_variable_58 == 1) { cfb_imageblit(psbfb_ops_group0, (struct fb_image const *)ldvarg169); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 4: ; if (ldv_state_variable_58 == 1) { drm_fb_helper_set_par(psbfb_ops_group0); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 5: ; if (ldv_state_variable_58 == 1) { psbfb_setcolreg(ldvarg165, ldvarg167, ldvarg166, ldvarg164, ldvarg168, psbfb_ops_group0); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 6: ; if (ldv_state_variable_58 == 1) { psbfb_ioctl(psbfb_ops_group0, ldvarg163, ldvarg162); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 7: ; if (ldv_state_variable_58 == 1) { drm_fb_helper_blank(ldvarg161, psbfb_ops_group0); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 8: ; if (ldv_state_variable_58 == 1) { drm_fb_helper_check_var(ldvarg160, psbfb_ops_group0); ldv_state_variable_58 = 1; } else { } goto ldv_43089; case 9: ; if (ldv_state_variable_58 == 1) { cfb_fillrect(psbfb_ops_group0, (struct fb_fillrect const *)ldvarg159); ldv_state_variable_58 = 1; } else { } goto ldv_43089; default: ldv_stop(); } ldv_43089: ; return; } } void ldv_main_exported_55(void) { u16 *ldvarg34 ; void *tmp ; struct drm_fb_helper *ldvarg28 ; void *tmp___0 ; struct drm_fb_helper_surface_size *ldvarg29 ; void *tmp___1 ; u16 *ldvarg36 ; void *tmp___2 ; int ldvarg37 ; u16 ldvarg30 ; int ldvarg33 ; u16 ldvarg31 ; u16 ldvarg32 ; u16 *ldvarg35 ; void *tmp___3 ; int tmp___4 ; { tmp = ldv_init_zalloc(2UL); ldvarg34 = (u16 *)tmp; tmp___0 = ldv_init_zalloc(160UL); ldvarg28 = (struct drm_fb_helper *)tmp___0; tmp___1 = ldv_init_zalloc(24UL); ldvarg29 = (struct drm_fb_helper_surface_size *)tmp___1; tmp___2 = ldv_init_zalloc(2UL); ldvarg36 = (u16 *)tmp___2; tmp___3 = ldv_init_zalloc(2UL); ldvarg35 = (u16 *)tmp___3; ldv_memset((void *)(& ldvarg37), 0, 4UL); ldv_memset((void *)(& ldvarg30), 0, 2UL); ldv_memset((void *)(& ldvarg33), 0, 4UL); ldv_memset((void *)(& ldvarg31), 0, 2UL); ldv_memset((void *)(& ldvarg32), 0, 2UL); tmp___4 = __VERIFIER_nondet_int(); switch (tmp___4) { case 0: ; if (ldv_state_variable_55 == 1) { psbfb_gamma_get(psb_fb_helper_funcs_group0, ldvarg36, ldvarg35, ldvarg34, ldvarg37); ldv_state_variable_55 = 1; } else { } goto ldv_43114; case 1: ; if (ldv_state_variable_55 == 1) { psbfb_gamma_set(psb_fb_helper_funcs_group0, (int )ldvarg32, (int )ldvarg31, (int )ldvarg30, ldvarg33); ldv_state_variable_55 = 1; } else { } goto ldv_43114; case 2: ; if (ldv_state_variable_55 == 1) { psbfb_probe(ldvarg28, ldvarg29); ldv_state_variable_55 = 1; } else { } goto ldv_43114; default: ldv_stop(); } ldv_43114: ; return; } } void ldv_main_exported_54(void) { struct drm_mode_fb_cmd2 *ldvarg214 ; void *tmp ; struct drm_file *ldvarg215 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(104UL); ldvarg214 = (struct drm_mode_fb_cmd2 *)tmp; tmp___0 = ldv_init_zalloc(744UL); ldvarg215 = (struct drm_file *)tmp___0; tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_54 == 1) { psb_user_framebuffer_create(psb_mode_funcs_group0, ldvarg215, ldvarg214); ldv_state_variable_54 = 1; } else { } goto ldv_43124; case 1: ; if (ldv_state_variable_54 == 1) { psbfb_output_poll_changed(psb_mode_funcs_group0); ldv_state_variable_54 = 1; } else { } goto ldv_43124; default: ldv_stop(); } ldv_43124: ; return; } } __inline static void *ERR_PTR(long error ) { void *tmp ; { tmp = ldv_err_ptr(error); return (tmp); } } bool ldv_queue_work_on_33(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_34(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_35(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_36(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_37(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_47(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_49(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_48(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_51(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_50(struct workqueue_struct *ldv_func_arg1 ) ; __inline static int kref_sub___0(struct kref *kref , unsigned int count , void (*release)(struct kref * ) ) { int __ret_warn_on ; long tmp ; int tmp___0 ; { __ret_warn_on = (unsigned long )release == (unsigned long )((void (*)(struct kref * ))0); tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("include/linux/kref.h", 71); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); tmp___0 = atomic_sub_and_test((int )count, & kref->refcount); if (tmp___0 != 0) { (*release)(kref); return (1); } else { } return (0); } } __inline static int kref_put___0(struct kref *kref , void (*release)(struct kref * ) ) { int tmp ; { tmp = kref_sub___0(kref, 1U, release); return (tmp); } } extern int vm_insert_pfn(struct vm_area_struct * , unsigned long , unsigned long ) ; __inline static void mapping_set_gfp_mask(struct address_space *m , gfp_t mask ) { { m->flags = (m->flags & 0xfffffffffe000000UL) | (unsigned long )mask; return; } } __inline static __u64 drm_vma_node_offset_addr(struct drm_vma_offset_node *node ) { { return (node->vm_node.start << 12); } } extern void drm_gem_object_release(struct drm_gem_object * ) ; extern int drm_gem_object_init(struct drm_device * , struct drm_gem_object * , size_t ) ; __inline static void drm_gem_object_unreference___0(struct drm_gem_object *obj ) { { if ((unsigned long )obj != (unsigned long )((struct drm_gem_object *)0)) { kref_put___0(& obj->refcount, & drm_gem_object_free); } else { } return; } } extern void drm_gem_free_mmap_offset(struct drm_gem_object * ) ; extern int drm_gem_create_mmap_offset(struct drm_gem_object * ) ; int psb_gtt_pin(struct gtt_range *gt ) ; void psb_gem_free_object(struct drm_gem_object *obj ) ; int psb_gem_get_aperture(struct drm_device *dev , void *data , struct drm_file *file ) ; int psb_gem_dumb_create(struct drm_file *file , struct drm_device *dev , struct drm_mode_create_dumb *args ) ; int psb_gem_dumb_map_gtt(struct drm_file *file , struct drm_device *dev , uint32_t handle , uint64_t *offset ) ; int psb_gem_fault(struct vm_area_struct *vma , struct vm_fault *vmf ) ; void psb_gem_free_object(struct drm_gem_object *obj ) { struct gtt_range *gtt ; struct drm_gem_object const *__mptr ; { __mptr = (struct drm_gem_object const *)obj; gtt = (struct gtt_range *)__mptr + 0xffffffffffffffc0UL; drm_gem_free_mmap_offset(obj); drm_gem_object_release(obj); psb_gtt_free_range(obj->dev, gtt); return; } } int psb_gem_get_aperture(struct drm_device *dev , void *data , struct drm_file *file ) { { return (-22); } } int psb_gem_dumb_map_gtt(struct drm_file *file , struct drm_device *dev , uint32_t handle , uint64_t *offset ) { int ret ; struct drm_gem_object *obj ; { ret = 0; mutex_lock_nested(& dev->struct_mutex, 0U); obj = drm_gem_object_lookup(dev, file, handle); if ((unsigned long )obj == (unsigned long )((struct drm_gem_object *)0)) { ret = -2; goto unlock; } else { } ret = drm_gem_create_mmap_offset(obj); if (ret != 0) { goto out; } else { } *offset = drm_vma_node_offset_addr(& obj->vma_node); out: drm_gem_object_unreference___0(obj); unlock: mutex_unlock(& dev->struct_mutex); return (ret); } } int psb_gem_create(struct drm_file *file , struct drm_device *dev , u64 size , u32 *handlep , int stolen , u32 align ) { struct gtt_range *r ; int ret ; u32 handle ; unsigned long __y ; int tmp ; { __y = 4096UL; size = ((((unsigned long long )__y + size) - 1ULL) / (unsigned long long )__y) * (unsigned long long )__y; r = psb_gtt_alloc_range(dev, (int )size, "gem", 0, 4096U); if ((unsigned long )r == (unsigned long )((struct gtt_range *)0)) { dev_err((struct device const *)dev->dev, "no memory for %lld byte GEM object\n", size); return (-28); } else { } tmp = drm_gem_object_init(dev, & r->gem, (size_t )size); if (tmp != 0) { psb_gtt_free_range(dev, r); dev_err((struct device const *)dev->dev, "GEM init failed for %lld\n", size); return (-12); } else { } mapping_set_gfp_mask((r->gem.filp)->f_mapping, 212U); ret = drm_gem_handle_create(file, & r->gem, & handle); if (ret != 0) { dev_err((struct device const *)dev->dev, "GEM handle failed for %p, %lld\n", & r->gem, size); drm_gem_object_release(& r->gem); psb_gtt_free_range(dev, r); return (ret); } else { } drm_gem_object_unreference___0(& r->gem); *handlep = handle; return (0); } } int psb_gem_dumb_create(struct drm_file *file , struct drm_device *dev , struct drm_mode_create_dumb *args ) { int tmp ; { args->pitch = (args->width * ((args->bpp + 7U) / 8U) + 63U) & 4294967232U; args->size = (uint64_t )(args->pitch * args->height); tmp = psb_gem_create(file, dev, args->size, & args->handle, 0, 4096U); return (tmp); } } int psb_gem_fault(struct vm_area_struct *vma , struct vm_fault *vmf ) { struct drm_gem_object *obj ; struct gtt_range *r ; int ret ; unsigned long pfn ; unsigned long page_offset___0 ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct drm_gem_object const *__mptr ; { obj = (struct drm_gem_object *)vma->vm_private_data; dev = obj->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_gem_object const *)obj; r = (struct gtt_range *)__mptr + 0xffffffffffffffc0UL; mutex_lock_nested(& dev->struct_mutex, 0U); if (! r->mmapping) { ret = psb_gtt_pin(r); if (ret < 0) { dev_err((struct device const *)dev->dev, "gma500: pin failed: %d\n", ret); goto fail; } else { } r->mmapping = 1; } else { } page_offset___0 = ((unsigned long )vmf->virtual_address - vma->vm_start) >> 12; if ((int )r->stolen) { pfn = (unsigned long )((dev_priv->stolen_base + r->offset) >> 12); } else { pfn = (unsigned long )(((long )*(r->pages + page_offset___0) + 24189255811072L) / 64L); } ret = vm_insert_pfn(vma, (unsigned long )vmf->virtual_address, pfn); fail: mutex_unlock(& dev->struct_mutex); switch (ret) { case 0: ; case -512: ; case -4: ; return (256); case -12: ; return (1); default: ; return (2); } } } bool ldv_queue_work_on_47(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_48(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_49(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_50(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_51(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_is_err(void const *ptr ) ; long ldv_ptr_err(void const *ptr ) ; __inline static long PTR_ERR(void const *ptr ) ; __inline static bool IS_ERR(void const *ptr ) ; extern void __mutex_init(struct mutex * , char const * , struct lock_class_key * ) ; extern void __init_rwsem(struct rw_semaphore * , char const * , struct lock_class_key * ) ; bool ldv_queue_work_on_61(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_63(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_62(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_65(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_64(struct workqueue_struct *ldv_func_arg1 ) ; extern int release_resource(struct resource * ) ; extern int allocate_resource(struct resource * , struct resource * , resource_size_t , resource_size_t , resource_size_t , resource_size_t , resource_size_t (*)(void * , struct resource const * , resource_size_t , resource_size_t ) , void * ) ; extern void *ioremap_nocache(resource_size_t , unsigned long ) ; extern void iounmap(void volatile * ) ; extern void *ioremap_wc(resource_size_t , unsigned long ) ; extern int set_pages_array_wc(struct page ** , int ) ; extern int set_pages_array_wb(struct page ** , int ) ; extern int pci_bus_read_config_word(struct pci_bus * , unsigned int , int , u16 * ) ; extern int pci_bus_write_config_word(struct pci_bus * , unsigned int , int , u16 ) ; __inline static int pci_read_config_word(struct pci_dev const *dev , int where , u16 *val ) { int tmp ; { tmp = pci_bus_read_config_word(dev->bus, dev->devfn, where, val); return (tmp); } } __inline static int pci_write_config_word(struct pci_dev const *dev , int where , u16 val ) { int tmp ; { tmp = pci_bus_write_config_word(dev->bus, dev->devfn, where, (int )val); return (tmp); } } extern void drm_ut_debug_printk(char const * , char const * , ...) ; extern void drm_err(char const * , ...) ; extern unsigned int drm_debug ; extern struct page **drm_gem_get_pages(struct drm_gem_object * ) ; extern void drm_gem_put_pages(struct drm_gem_object * , struct page ** , bool , bool ) ; int psb_gtt_init(struct drm_device *dev , int resume ) ; void psb_gtt_takedown(struct drm_device *dev ) ; void psb_gtt_unpin(struct gtt_range *gt ) ; int psb_gtt_restore(struct drm_device *dev ) ; struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver___0 ) ; int psb_mmu_insert_pages(struct psb_mmu_pd *pd , struct page **pages , unsigned long address , uint32_t num_pages , uint32_t desired_tile_stride , uint32_t hw_tile_stride , int type ) ; void psb_mmu_remove_pages(struct psb_mmu_pd *pd , unsigned long address , uint32_t num_pages , uint32_t desired_tile_stride , uint32_t hw_tile_stride ) ; int gma_blt_wait_idle(struct drm_psb_private *dev_priv ) ; __inline static uint32_t psb_gtt_mask_pte(uint32_t pfn , int type ) { uint32_t mask ; long tmp ; { mask = 1U; tmp = ldv__builtin_expect((pfn & 4293918720U) != 0U, 0L); if (tmp != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c"), "i" (45), "i" (12UL)); ldv_42711: ; goto ldv_42711; } else { } if (type & 1) { mask = mask | 8U; } else { } if ((type & 2) != 0) { mask = mask | 4U; } else { } if ((type & 4) != 0) { mask = mask | 2U; } else { } return ((pfn << 12) | mask); } } static u32 *psb_gtt_entry(struct drm_device *dev , struct gtt_range *r ) { struct drm_psb_private *dev_priv ; unsigned long offset ; { dev_priv = (struct drm_psb_private *)dev->dev_private; offset = (unsigned long )(r->resource.start - (dev_priv->gtt_mem)->start); return (dev_priv->gtt_map + (offset >> 12)); } } static int psb_gtt_insert(struct drm_device *dev , struct gtt_range *r , int resume ) { u32 *gtt_slot ; u32 pte ; struct page **pages ; int i ; int __ret_warn_on ; long tmp ; int __ret_warn_on___0 ; long tmp___0 ; u32 *tmp___1 ; u32 *tmp___2 ; { if ((unsigned long )r->pages == (unsigned long )((struct page **)0)) { __ret_warn_on = 1; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c", 93); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return (-22); } else { } __ret_warn_on___0 = (int )r->stolen; tmp___0 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c", 97); } else { } ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); gtt_slot = psb_gtt_entry(dev, r); pages = r->pages; if (resume == 0) { set_pages_array_wc(pages, r->npage); } else { } i = r->roll; goto ldv_42732; ldv_42731: pte = psb_gtt_mask_pte((uint32_t )(((long )*(r->pages + (unsigned long )i) + 24189255811072L) / 64L), 1); tmp___1 = gtt_slot; gtt_slot = gtt_slot + 1; iowrite32(pte, (void *)tmp___1); i = i + 1; ldv_42732: ; if (r->npage > i) { goto ldv_42731; } else { } i = 0; goto ldv_42735; ldv_42734: pte = psb_gtt_mask_pte((uint32_t )(((long )*(r->pages + (unsigned long )i) + 24189255811072L) / 64L), 1); tmp___2 = gtt_slot; gtt_slot = gtt_slot + 1; iowrite32(pte, (void *)tmp___2); i = i + 1; ldv_42735: ; if (r->roll > i) { goto ldv_42734; } else { } ioread32((void *)gtt_slot + 0xffffffffffffffffUL); return (0); } } void psb_gtt_remove(struct drm_device *dev , struct gtt_range *r ) { struct drm_psb_private *dev_priv ; u32 *gtt_slot ; u32 pte ; int i ; int __ret_warn_on ; long tmp ; u32 *tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; __ret_warn_on = (int )r->stolen; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c", 140); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); gtt_slot = psb_gtt_entry(dev, r); pte = psb_gtt_mask_pte((uint32_t )(((long )dev_priv->scratch_page + 24189255811072L) / 64L), 1); i = 0; goto ldv_42748; ldv_42747: tmp___0 = gtt_slot; gtt_slot = gtt_slot + 1; iowrite32(pte, (void *)tmp___0); i = i + 1; ldv_42748: ; if (r->npage > i) { goto ldv_42747; } else { } ioread32((void *)gtt_slot + 0xffffffffffffffffUL); set_pages_array_wb(r->pages, r->npage); return; } } void psb_gtt_roll(struct drm_device *dev , struct gtt_range *r , int roll ) { u32 *gtt_slot ; u32 pte ; int i ; int __ret_warn_on ; long tmp ; u32 *tmp___0 ; u32 *tmp___1 ; { if (r->npage <= roll) { __ret_warn_on = 1; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c", 169); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return; } else { } r->roll = roll; if (! r->stolen && r->in_gart == 0) { return; } else { } gtt_slot = psb_gtt_entry(dev, r); i = r->roll; goto ldv_42761; ldv_42760: pte = psb_gtt_mask_pte((uint32_t )(((long )*(r->pages + (unsigned long )i) + 24189255811072L) / 64L), 1); tmp___0 = gtt_slot; gtt_slot = gtt_slot + 1; iowrite32(pte, (void *)tmp___0); i = i + 1; ldv_42761: ; if (r->npage > i) { goto ldv_42760; } else { } i = 0; goto ldv_42764; ldv_42763: pte = psb_gtt_mask_pte((uint32_t )(((long )*(r->pages + (unsigned long )i) + 24189255811072L) / 64L), 1); tmp___1 = gtt_slot; gtt_slot = gtt_slot + 1; iowrite32(pte, (void *)tmp___1); i = i + 1; ldv_42764: ; if (r->roll > i) { goto ldv_42763; } else { } ioread32((void *)gtt_slot + 0xffffffffffffffffUL); return; } } static int psb_gtt_attach_pages(struct gtt_range *gt ) { struct page **pages ; int __ret_warn_on ; long tmp ; long tmp___0 ; bool tmp___1 ; { __ret_warn_on = (unsigned long )gt->pages != (unsigned long )((struct page **)0); tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c", 207); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); pages = drm_gem_get_pages(& gt->gem); tmp___1 = IS_ERR((void const *)pages); if ((int )tmp___1) { tmp___0 = PTR_ERR((void const *)pages); return ((int )tmp___0); } else { } gt->npage = (int )(gt->gem.size / 4096UL); gt->pages = pages; return (0); } } static void psb_gtt_detach_pages(struct gtt_range *gt ) { { drm_gem_put_pages(& gt->gem, gt->pages, 1, 0); gt->pages = (struct page **)0; return; } } int psb_gtt_pin(struct gtt_range *gt ) { int ret ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; u32 gpu_base ; struct psb_mmu_pd *tmp ; { ret = 0; dev = gt->gem.dev; dev_priv = (struct drm_psb_private *)dev->dev_private; gpu_base = dev_priv->gtt.gatt_start; mutex_lock_nested(& dev_priv->gtt_mutex, 0U); if (gt->in_gart == 0 && ! gt->stolen) { ret = psb_gtt_attach_pages(gt); if (ret < 0) { goto out; } else { } ret = psb_gtt_insert(dev, gt, 0); if (ret < 0) { psb_gtt_detach_pages(gt); goto out; } else { } tmp = psb_mmu_get_default_pd(dev_priv->mmu); psb_mmu_insert_pages(tmp, gt->pages, (unsigned long )(gt->offset + gpu_base), (uint32_t )gt->npage, 0U, 0U, 1); } else { } gt->in_gart = gt->in_gart + 1; out: mutex_unlock(& dev_priv->gtt_mutex); return (ret); } } void psb_gtt_unpin(struct gtt_range *gt ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; u32 gpu_base ; int ret ; int __ret_warn_on ; long tmp ; struct psb_mmu_pd *tmp___0 ; { dev = gt->gem.dev; dev_priv = (struct drm_psb_private *)dev->dev_private; gpu_base = dev_priv->gtt.gatt_start; mutex_lock_nested(& dev_priv->gtt_mutex, 0U); ret = gma_blt_wait_idle(dev_priv); if (ret != 0) { drm_err("Failed to idle the blitter, unpin failed!"); goto out; } else { } __ret_warn_on = gt->in_gart == 0; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c", 300); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); gt->in_gart = gt->in_gart - 1; if (gt->in_gart == 0 && ! gt->stolen) { tmp___0 = psb_mmu_get_default_pd(dev_priv->mmu); psb_mmu_remove_pages(tmp___0, (unsigned long )(gt->offset + gpu_base), (uint32_t )gt->npage, 0U, 0U); psb_gtt_remove(dev, gt); psb_gtt_detach_pages(gt); } else { } out: mutex_unlock(& dev_priv->gtt_mutex); return; } } struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev , int len , char const *name , int backed , u32 align ) { struct drm_psb_private *dev_priv ; struct gtt_range *gt ; struct resource *r ; int ret ; unsigned long start ; unsigned long end ; void *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; r = dev_priv->gtt_mem; if (backed != 0) { start = (unsigned long )r->start; end = (unsigned long )((r->start + (unsigned long long )dev_priv->gtt.stolen_size) - 1ULL); } else { start = (unsigned long )(r->start + (unsigned long long )dev_priv->gtt.stolen_size); end = (unsigned long )r->end; } tmp = kzalloc(336UL, 208U); gt = (struct gtt_range *)tmp; if ((unsigned long )gt == (unsigned long )((struct gtt_range *)0)) { return ((struct gtt_range *)0); } else { } gt->resource.name = name; gt->stolen = backed != 0; gt->in_gart = backed; gt->roll = 0; gt->gem.dev = dev; ret = allocate_resource(dev_priv->gtt_mem, & gt->resource, (resource_size_t )len, (resource_size_t )start, (resource_size_t )end, (resource_size_t )align, (resource_size_t (*)(void * , struct resource const * , resource_size_t , resource_size_t ))0, (void *)0); if (ret == 0) { gt->offset = (u32 )gt->resource.start - (u32 )r->start; return (gt); } else { } kfree((void const *)gt); return ((struct gtt_range *)0); } } void psb_gtt_free_range(struct drm_device *dev , struct gtt_range *gt ) { int __ret_warn_on ; long tmp ; { if ((int )gt->mmapping) { psb_gtt_unpin(gt); gt->mmapping = 0; } else { } __ret_warn_on = gt->in_gart != 0 && ! gt->stolen; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c", 385); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); release_resource(& gt->resource); kfree((void const *)gt); return; } } static void psb_gtt_alloc(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct lock_class_key __key ; { dev_priv = (struct drm_psb_private *)dev->dev_private; __init_rwsem(& dev_priv->gtt.sem, "&dev_priv->gtt.sem", & __key); return; } } void psb_gtt_takedown(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if ((unsigned long )dev_priv->gtt_map != (unsigned long )((u32 *)0U)) { iounmap((void volatile *)dev_priv->gtt_map); dev_priv->gtt_map = (u32 *)0U; } else { } if (dev_priv->gtt_initialized != 0) { pci_write_config_word((struct pci_dev const *)dev->pdev, 82, (int )dev_priv->gmch_ctrl); iowrite32(dev_priv->pge_ctl, (void *)dev_priv->vdc_reg + 8224U); ioread32((void *)dev_priv->vdc_reg + 8224U); } else { } if ((unsigned long )dev_priv->vram_addr != (unsigned long )((u8 *)0U)) { iounmap((void volatile *)dev_priv->gtt_map); } else { } return; } } int psb_gtt_init(struct drm_device *dev , int resume ) { struct drm_psb_private *dev_priv ; unsigned int gtt_pages ; unsigned long stolen_size ; unsigned long vram_stolen_size ; unsigned int i ; unsigned int num_pages ; unsigned int pfn_base ; struct psb_gtt *pg ; int ret ; uint32_t pte ; struct lock_class_key __key ; struct _ddebug descriptor ; long tmp ; struct resource fudge ; struct _ddebug descriptor___0 ; long tmp___0 ; struct _ddebug descriptor___1 ; long tmp___1 ; void *tmp___2 ; void *tmp___3 ; struct _ddebug descriptor___2 ; long tmp___4 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; ret = 0; if (resume == 0) { __mutex_init(& dev_priv->gtt_mutex, "&dev_priv->gtt_mutex", & __key); psb_gtt_alloc(dev); } else { } pg = & dev_priv->gtt; pci_read_config_word((struct pci_dev const *)dev->pdev, 82, & dev_priv->gmch_ctrl); pci_write_config_word((struct pci_dev const *)dev->pdev, 82, (int )((unsigned int )dev_priv->gmch_ctrl | 4U)); dev_priv->pge_ctl = ioread32((void *)dev_priv->vdc_reg + 8224U); iowrite32(dev_priv->pge_ctl | 1U, (void *)dev_priv->vdc_reg + 8224U); ioread32((void *)dev_priv->vdc_reg + 8224U); dev_priv->gtt_initialized = 1; pg->gtt_phys_start = dev_priv->pge_ctl & 4294963200U; pg->mmu_gatt_start = 3758096384U; pg->gtt_start = (uint32_t )(dev->pdev)->resource[3].start; gtt_pages = (dev->pdev)->resource[3].start != 0ULL || (dev->pdev)->resource[3].end != (dev->pdev)->resource[3].start ? (unsigned int )((((dev->pdev)->resource[3].end - (dev->pdev)->resource[3].start) + 1ULL) >> 12) : 0U; if (pg->gtt_start == 0U || gtt_pages == 0U) { descriptor.modname = "gma500_gfx"; descriptor.function = "psb_gtt_init"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c"; descriptor.format = "GTT PCI BAR not initialized.\n"; descriptor.lineno = 460U; descriptor.flags = 0U; tmp = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "GTT PCI BAR not initialized.\n"); } else { } gtt_pages = 64U; pg->gtt_start = dev_priv->pge_ctl; } else { } pg->gatt_start = (uint32_t )(dev->pdev)->resource[2].start; pg->gatt_pages = (dev->pdev)->resource[2].start != 0ULL || (dev->pdev)->resource[2].end != (dev->pdev)->resource[2].start ? (unsigned int )((((dev->pdev)->resource[2].end - (dev->pdev)->resource[2].start) + 1ULL) >> 12) : 0U; dev_priv->gtt_mem = (struct resource *)(& (dev->pdev)->resource) + 2UL; if (pg->gatt_pages == 0U || pg->gatt_start == 0U) { descriptor___0.modname = "gma500_gfx"; descriptor___0.function = "psb_gtt_init"; descriptor___0.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c"; descriptor___0.format = "GATT PCI BAR not initialized.\n"; descriptor___0.lineno = 475U; descriptor___0.flags = 0U; tmp___0 = ldv__builtin_expect((long )descriptor___0.flags & 1L, 0L); if (tmp___0 != 0L) { __dynamic_dev_dbg(& descriptor___0, (struct device const *)dev->dev, "GATT PCI BAR not initialized.\n"); } else { } pg->gatt_start = 1073741824U; pg->gatt_pages = 32768U; fudge.start = 1073741824ULL; fudge.end = 1207959551ULL; fudge.name = "fudge"; fudge.flags = 512UL; dev_priv->gtt_mem = & fudge; } else { } pci_read_config_dword((struct pci_dev const *)dev->pdev, 92, & dev_priv->stolen_base); vram_stolen_size = (unsigned long )(pg->gtt_phys_start - dev_priv->stolen_base) - 4096UL; stolen_size = vram_stolen_size; descriptor___1.modname = "gma500_gfx"; descriptor___1.function = "psb_gtt_init"; descriptor___1.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c"; descriptor___1.format = "Stolen memory base 0x%x, size %luK\n"; descriptor___1.lineno = 496U; descriptor___1.flags = 0U; tmp___1 = ldv__builtin_expect((long )descriptor___1.flags & 1L, 0L); if (tmp___1 != 0L) { __dynamic_dev_dbg(& descriptor___1, (struct device const *)dev->dev, "Stolen memory base 0x%x, size %luK\n", dev_priv->stolen_base, vram_stolen_size / 1024UL); } else { } if ((resume != 0 && pg->gtt_pages != gtt_pages) && pg->stolen_size != stolen_size) { dev_err((struct device const *)dev->dev, "GTT resume error.\n"); ret = -22; goto out_err; } else { } pg->gtt_pages = gtt_pages; pg->stolen_size = stolen_size; dev_priv->vram_stolen_size = vram_stolen_size; if (resume == 0) { tmp___2 = ioremap_nocache((resource_size_t )pg->gtt_phys_start, (unsigned long )(gtt_pages << 12)); dev_priv->gtt_map = (u32 *)tmp___2; } else { } if ((unsigned long )dev_priv->gtt_map == (unsigned long )((u32 *)0U)) { dev_err((struct device const *)dev->dev, "Failure to map gtt.\n"); ret = -12; goto out_err; } else { } if (resume == 0) { tmp___3 = ioremap_wc((resource_size_t )dev_priv->stolen_base, stolen_size); dev_priv->vram_addr = (u8 *)tmp___3; } else { } if ((unsigned long )dev_priv->vram_addr == (unsigned long )((u8 *)0U)) { dev_err((struct device const *)dev->dev, "Failure to map stolen base.\n"); ret = -12; goto out_err; } else { } pfn_base = dev_priv->stolen_base >> 12; num_pages = (unsigned int )(vram_stolen_size >> 12); descriptor___2.modname = "gma500_gfx"; descriptor___2.function = "psb_gtt_init"; descriptor___2.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gtt.c"; descriptor___2.format = "Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n"; descriptor___2.lineno = 538U; descriptor___2.flags = 0U; tmp___4 = ldv__builtin_expect((long )descriptor___2.flags & 1L, 0L); if (tmp___4 != 0L) { __dynamic_dev_dbg(& descriptor___2, (struct device const *)dev->dev, "Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n", num_pages, pfn_base << 12, 0); } else { } i = 0U; goto ldv_42844; ldv_42843: pte = psb_gtt_mask_pte(pfn_base + i, 1); iowrite32(pte, (void *)dev_priv->gtt_map + (unsigned long )i); i = i + 1U; ldv_42844: ; if (i < num_pages) { goto ldv_42843; } else { } pfn_base = (unsigned int )(((long )dev_priv->scratch_page + 24189255811072L) / 64L); pte = psb_gtt_mask_pte(pfn_base, 1); goto ldv_42847; ldv_42846: iowrite32(pte, (void *)dev_priv->gtt_map + (unsigned long )i); i = i + 1U; ldv_42847: ; if (i < gtt_pages) { goto ldv_42846; } else { } ioread32((void *)(dev_priv->gtt_map + ((unsigned long )i + 0xffffffffffffffffUL))); return (0); out_err: psb_gtt_takedown(dev); return (ret); } } int psb_gtt_restore(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct resource *r ; struct gtt_range *range ; unsigned int restored ; unsigned int total ; unsigned int size ; struct resource const *__mptr ; long tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; r = (dev_priv->gtt_mem)->child; restored = 0U; total = 0U; size = 0U; mutex_lock_nested(& dev_priv->gtt_mutex, 0U); psb_gtt_init(dev, 1); goto ldv_42861; ldv_42860: __mptr = (struct resource const *)r; range = (struct gtt_range *)__mptr; if ((unsigned long )range->pages != (unsigned long )((struct page **)0)) { psb_gtt_insert(dev, range, 1); size = ((unsigned int )range->resource.end - (unsigned int )range->resource.start) + size; restored = restored + 1U; } else { } r = r->sibling; total = total + 1U; ldv_42861: ; if ((unsigned long )r != (unsigned long )((struct resource *)0)) { goto ldv_42860; } else { } mutex_unlock(& dev_priv->gtt_mutex); tmp = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("psb_gtt_restore", "Restored %u of %u gtt ranges (%u KB)", restored, total, size / 1024U); } else { } return (0); } } __inline static long PTR_ERR(void const *ptr ) { long tmp ; { tmp = ldv_ptr_err(ptr); return (tmp); } } __inline static bool IS_ERR(void const *ptr ) { bool tmp ; { tmp = ldv_is_err(ptr); return (tmp); } } bool ldv_queue_work_on_61(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_62(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_63(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_64(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_65(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; extern void *memcpy(void * , void const * , size_t ) ; extern int memcmp(void const * , void const * , size_t ) ; extern void *kmemdup(void const * , size_t , gfp_t ) ; bool ldv_queue_work_on_75(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_77(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_76(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_79(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_78(struct workqueue_struct *ldv_func_arg1 ) ; __inline static void *kmalloc_array(size_t n , size_t size , gfp_t flags ) { void *tmp ; { if (size != 0UL && 0xffffffffffffffffUL / size < n) { return ((void *)0); } else { } tmp = __kmalloc(n * size, flags); return (tmp); } } __inline static void *kcalloc(size_t n , size_t size , gfp_t flags ) { void *tmp ; { tmp = kmalloc_array(n, size, flags | 32768U); return (tmp); } } extern void *pci_map_rom(struct pci_dev * , size_t * ) ; extern void pci_unmap_rom(struct pci_dev * , void * ) ; extern void drm_mode_debug_printmodeline(struct drm_display_mode const * ) ; extern void drm_mode_set_name(struct drm_display_mode * ) ; int psb_intel_init_bios(struct drm_device *dev ) ; void psb_intel_destroy_bios(struct drm_device *dev ) ; static void *find_section(struct bdb_header *bdb , int section_id ) { u8 *base ; int index ; u16 total ; u16 current_size ; u8 current_id ; { base = (u8 *)bdb; index = 0; index = (int )bdb->header_size + index; total = bdb->bdb_size; goto ldv_41554; ldv_41553: current_id = *(base + (unsigned long )index); index = index + 1; current_size = *((u16 *)base + (unsigned long )index); index = index + 2; if ((int )current_id == section_id) { return ((void *)base + (unsigned long )index); } else { } index = (int )current_size + index; ldv_41554: ; if ((int )total > index) { goto ldv_41553; } else { } return ((void *)0); } } static void parse_edp(struct drm_psb_private *dev_priv , struct bdb_header *bdb ) { struct bdb_edp *edp ; struct edp_power_seq *edp_pps ; struct edp_link_params *edp_link_params ; uint8_t panel_type ; void *tmp ; long tmp___0 ; long tmp___1 ; long tmp___2 ; long tmp___3 ; { tmp = find_section(bdb, 27); edp = (struct bdb_edp *)tmp; dev_priv->edp.bpp = 18; if ((unsigned long )edp == (unsigned long )((struct bdb_edp *)0)) { if ((int )dev_priv->edp.support) { tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("parse_edp", "No eDP BDB found but eDP panel supported, assume %dbpp panel color depth.\n", dev_priv->edp.bpp); } else { } } else { } return; } else { } panel_type = dev_priv->panel_type; switch ((edp->color_depth >> (int )panel_type * 2) & 3U) { case 0U: dev_priv->edp.bpp = 18; goto ldv_41566; case 1U: dev_priv->edp.bpp = 24; goto ldv_41566; case 2U: dev_priv->edp.bpp = 30; goto ldv_41566; } ldv_41566: edp_pps = (struct edp_power_seq *)(& edp->power_seqs) + (unsigned long )panel_type; edp_link_params = (struct edp_link_params *)(& edp->link_params) + (unsigned long )panel_type; dev_priv->edp.pps = *edp_pps; tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("parse_edp", "EDP timing in vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", (int )dev_priv->edp.pps.t1_t3, (int )dev_priv->edp.pps.t8, (int )dev_priv->edp.pps.t9, (int )dev_priv->edp.pps.t10, (int )dev_priv->edp.pps.t11_t12); } else { } dev_priv->edp.rate = (unsigned int )*((unsigned char *)edp_link_params + 0UL) != 0U ? 10 : 6; switch ((int )edp_link_params->lanes) { case 0: dev_priv->edp.lanes = 1; goto ldv_41570; case 1: dev_priv->edp.lanes = 2; goto ldv_41570; case 3: ; default: dev_priv->edp.lanes = 4; goto ldv_41570; } ldv_41570: tmp___2 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("parse_edp", "VBT reports EDP: Lane_count %d, Lane_rate %d, Bpp %d\n", dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); } else { } switch ((int )edp_link_params->preemphasis) { case 0: dev_priv->edp.preemphasis = 0; goto ldv_41575; case 1: dev_priv->edp.preemphasis = 8; goto ldv_41575; case 2: dev_priv->edp.preemphasis = 16; goto ldv_41575; case 3: dev_priv->edp.preemphasis = 24; goto ldv_41575; } ldv_41575: ; switch ((int )edp_link_params->vswing) { case 0: dev_priv->edp.vswing = 0; goto ldv_41580; case 1: dev_priv->edp.vswing = 1; goto ldv_41580; case 2: dev_priv->edp.vswing = 2; goto ldv_41580; case 3: dev_priv->edp.vswing = 3; goto ldv_41580; } ldv_41580: tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("parse_edp", "VBT reports EDP: VSwing %d, Preemph %d\n", dev_priv->edp.vswing, dev_priv->edp.preemphasis); } else { } return; } } static u16 get_blocksize(void *p ) { u16 *block_ptr ; u16 block_size ; { block_ptr = (u16 *)p + 0xfffffffffffffffeUL; block_size = *block_ptr; return (block_size); } } static void fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode , struct lvds_dvo_timing *dvo_timing ) { { panel_fixed_mode->hdisplay = ((int )dvo_timing->hactive_hi << 8) | (int )dvo_timing->hactive_lo; panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + (((int )dvo_timing->hsync_off_hi << 8) | (int )dvo_timing->hsync_off_lo); panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + (int )dvo_timing->hsync_pulse_width; panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + (((int )dvo_timing->hblank_hi << 8) | (int )dvo_timing->hblank_lo); panel_fixed_mode->vdisplay = ((int )dvo_timing->vactive_hi << 8) | (int )dvo_timing->vactive_lo; panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + (int )dvo_timing->vsync_off; panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + (int )dvo_timing->vsync_pulse_width; panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + (((int )dvo_timing->vblank_hi << 8) | (int )dvo_timing->vblank_lo); panel_fixed_mode->clock = (int )dvo_timing->clock * 10; panel_fixed_mode->type = 8U; if ((unsigned int )*((unsigned char *)dvo_timing + 17UL) != 0U) { panel_fixed_mode->flags = panel_fixed_mode->flags | 1U; } else { panel_fixed_mode->flags = panel_fixed_mode->flags | 2U; } if ((unsigned int )*((unsigned char *)dvo_timing + 17UL) != 0U) { panel_fixed_mode->flags = panel_fixed_mode->flags | 4U; } else { panel_fixed_mode->flags = panel_fixed_mode->flags | 8U; } if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) { panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; } else { } if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) { panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; } else { } drm_mode_set_name(panel_fixed_mode); return; } } static void parse_backlight_data(struct drm_psb_private *dev_priv , struct bdb_header *bdb ) { struct bdb_lvds_backlight *vbt_lvds_bl ; struct bdb_lvds_backlight *lvds_bl ; u8 p_type ; void *bl_start ; struct bdb_lvds_options *lvds_opts ; void *tmp ; void *tmp___0 ; { vbt_lvds_bl = (struct bdb_lvds_backlight *)0; p_type = 0U; bl_start = (void *)0; tmp = find_section(bdb, 40); lvds_opts = (struct bdb_lvds_options *)tmp; dev_priv->lvds_bl = (struct bdb_lvds_backlight *)0; if ((unsigned long )lvds_opts != (unsigned long )((struct bdb_lvds_options *)0)) { p_type = lvds_opts->panel_type; } else { return; } bl_start = find_section(bdb, 43); vbt_lvds_bl = (struct bdb_lvds_backlight *)bl_start + ((unsigned long )p_type + 1UL); tmp___0 = kmemdup((void const *)vbt_lvds_bl, 6UL, 208U); lvds_bl = (struct bdb_lvds_backlight *)tmp___0; if ((unsigned long )lvds_bl == (unsigned long )((struct bdb_lvds_backlight *)0)) { dev_err((struct device const *)(dev_priv->dev)->dev, "out of memory for backlight data\n"); return; } else { } dev_priv->lvds_bl = lvds_bl; return; } } static void parse_lfp_panel_data(struct drm_psb_private *dev_priv , struct bdb_header *bdb ) { struct bdb_lvds_options *lvds_options ; struct bdb_lvds_lfp_data *lvds_lfp_data ; struct bdb_lvds_lfp_data_entry *entry ; struct lvds_dvo_timing *dvo_timing ; struct drm_display_mode *panel_fixed_mode ; void *tmp ; void *tmp___0 ; void *tmp___1 ; struct _ddebug descriptor ; long tmp___2 ; { dev_priv->lvds_dither = 0U; dev_priv->lvds_vbt = 0U; tmp = find_section(bdb, 40); lvds_options = (struct bdb_lvds_options *)tmp; if ((unsigned long )lvds_options == (unsigned long )((struct bdb_lvds_options *)0)) { return; } else { } dev_priv->lvds_dither = lvds_options->pixel_dither; dev_priv->panel_type = lvds_options->panel_type; if ((unsigned int )lvds_options->panel_type == 255U) { return; } else { } tmp___0 = find_section(bdb, 42); lvds_lfp_data = (struct bdb_lvds_lfp_data *)tmp___0; if ((unsigned long )lvds_lfp_data == (unsigned long )((struct bdb_lvds_lfp_data *)0)) { return; } else { } entry = (struct bdb_lvds_lfp_data_entry *)(& lvds_lfp_data->data) + (unsigned long )lvds_options->panel_type; dvo_timing = & entry->dvo_timing; tmp___1 = kzalloc(208UL, 208U); panel_fixed_mode = (struct drm_display_mode *)tmp___1; if ((unsigned long )panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { dev_err((struct device const *)(dev_priv->dev)->dev, "out of memory for fixed panel mode\n"); return; } else { } dev_priv->lvds_vbt = 1U; fill_detail_timing_data(panel_fixed_mode, dvo_timing); if (panel_fixed_mode->htotal > 0 && panel_fixed_mode->vtotal > 0) { dev_priv->lfp_lvds_vbt_mode = panel_fixed_mode; drm_mode_debug_printmodeline((struct drm_display_mode const *)panel_fixed_mode); } else { descriptor.modname = "gma500_gfx"; descriptor.function = "parse_lfp_panel_data"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/intel_bios.c"; descriptor.format = "ignoring invalid LVDS VBT\n"; descriptor.lineno = 275U; descriptor.flags = 0U; tmp___2 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___2 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)(dev_priv->dev)->dev, "ignoring invalid LVDS VBT\n"); } else { } dev_priv->lvds_vbt = 0U; kfree((void const *)panel_fixed_mode); } return; } } static void parse_sdvo_panel_data(struct drm_psb_private *dev_priv , struct bdb_header *bdb ) { struct bdb_sdvo_lvds_options *sdvo_lvds_options ; struct lvds_dvo_timing *dvo_timing ; struct drm_display_mode *panel_fixed_mode ; void *tmp ; void *tmp___0 ; void *tmp___1 ; { dev_priv->sdvo_lvds_vbt_mode = (struct drm_display_mode *)0; tmp = find_section(bdb, 22); sdvo_lvds_options = (struct bdb_sdvo_lvds_options *)tmp; if ((unsigned long )sdvo_lvds_options == (unsigned long )((struct bdb_sdvo_lvds_options *)0)) { return; } else { } tmp___0 = find_section(bdb, 23); dvo_timing = (struct lvds_dvo_timing *)tmp___0; if ((unsigned long )dvo_timing == (unsigned long )((struct lvds_dvo_timing *)0)) { return; } else { } tmp___1 = kzalloc(208UL, 208U); panel_fixed_mode = (struct drm_display_mode *)tmp___1; if ((unsigned long )panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { return; } else { } fill_detail_timing_data(panel_fixed_mode, dvo_timing + (unsigned long )sdvo_lvds_options->panel_type); dev_priv->sdvo_lvds_vbt_mode = panel_fixed_mode; return; } } static void parse_general_features(struct drm_psb_private *dev_priv , struct bdb_header *bdb ) { struct bdb_general_features *general ; void *tmp ; { dev_priv->int_tv_support = 1U; dev_priv->int_crt_support = 1U; tmp = find_section(bdb, 1); general = (struct bdb_general_features *)tmp; if ((unsigned long )general != (unsigned long )((struct bdb_general_features *)0)) { dev_priv->int_tv_support = general->int_tv_support; dev_priv->int_crt_support = general->int_crt_support; dev_priv->lvds_use_ssc = general->enable_ssc; if ((unsigned int )*((unsigned char *)dev_priv + 864UL) != 0U) { dev_priv->lvds_ssc_freq = (unsigned int )*((unsigned char *)general + 1UL) != 0U ? 100 : 96; } else { } } else { } return; } } static void parse_sdvo_device_mapping(struct drm_psb_private *dev_priv , struct bdb_header *bdb ) { struct sdvo_device_mapping *p_mapping ; struct bdb_general_definitions *p_defs ; struct child_device_config *p_child ; int i ; int child_device_num ; int count ; u16 block_size ; void *tmp ; long tmp___0 ; long tmp___1 ; long tmp___2 ; long tmp___3 ; long tmp___4 ; long tmp___5 ; long tmp___6 ; long tmp___7 ; { tmp = find_section(bdb, 2); p_defs = (struct bdb_general_definitions *)tmp; if ((unsigned long )p_defs == (unsigned long )((struct bdb_general_definitions *)0)) { tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("parse_sdvo_device_mapping", "No general definition block is found, unable to construct sdvo mapping.\n"); } else { } return; } else { } if ((unsigned int )p_defs->child_dev_size != 33U) { tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("parse_sdvo_device_mapping", "different child size is found. Invalid.\n"); } else { } return; } else { } block_size = get_blocksize((void *)p_defs); child_device_num = (int )(((unsigned long )block_size - 5UL) / 33UL); count = 0; i = 0; goto ldv_41639; ldv_41638: p_child = (struct child_device_config *)(& p_defs->devices) + (unsigned long )i; if ((unsigned int )p_child->device_type == 0U) { goto ldv_41637; } else { } if ((unsigned int )p_child->slave_addr != 112U && (unsigned int )p_child->slave_addr != 114U) { goto ldv_41637; } else { } if ((unsigned int )p_child->dvo_port != 1U && (unsigned int )p_child->dvo_port != 2U) { tmp___2 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("parse_sdvo_device_mapping", "Incorrect SDVO port. Skip it\n"); } else { } goto ldv_41637; } else { } tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("parse_sdvo_device_mapping", "the SDVO device with slave addr %2x is found on %s port\n", (int )p_child->slave_addr, (unsigned int )p_child->dvo_port == 1U ? (char *)"SDVOB" : (char *)"SDVOC"); } else { } p_mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings) + ((unsigned long )p_child->dvo_port + 0xffffffffffffffffUL); if ((unsigned int )p_mapping->initialized == 0U) { p_mapping->dvo_port = p_child->dvo_port; p_mapping->slave_addr = p_child->slave_addr; p_mapping->dvo_wiring = p_child->dvo_wiring; p_mapping->ddc_pin = p_child->ddc_pin; p_mapping->i2c_pin = p_child->i2c_pin; p_mapping->initialized = 1U; tmp___4 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("parse_sdvo_device_mapping", "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", (int )p_mapping->dvo_port, (int )p_mapping->slave_addr, (int )p_mapping->dvo_wiring, (int )p_mapping->ddc_pin, (int )p_mapping->i2c_pin); } else { } } else { tmp___5 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___5 != 0L) { drm_ut_debug_printk("parse_sdvo_device_mapping", "Maybe one SDVO port is shared by two SDVO device.\n"); } else { } } if ((unsigned int )p_child->slave2_addr != 0U) { tmp___6 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___6 != 0L) { drm_ut_debug_printk("parse_sdvo_device_mapping", "there exists the slave2_addr. Maybe this is a SDVO device with multiple inputs.\n"); } else { } } else { } count = count + 1; ldv_41637: i = i + 1; ldv_41639: ; if (i < child_device_num) { goto ldv_41638; } else { } if (count == 0) { tmp___7 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___7 != 0L) { drm_ut_debug_printk("parse_sdvo_device_mapping", "No SDVO device info is found in VBT\n"); } else { } } else { } return; } } static void parse_driver_features(struct drm_psb_private *dev_priv , struct bdb_header *bdb ) { struct bdb_driver_features *driver___0 ; void *tmp ; { tmp = find_section(bdb, 12); driver___0 = (struct bdb_driver_features *)tmp; if ((unsigned long )driver___0 == (unsigned long )((struct bdb_driver_features *)0)) { return; } else { } if ((unsigned int )*((unsigned char *)driver___0 + 8UL) == 24U) { dev_priv->edp.support = 1; } else { } if ((unsigned int )*((unsigned char *)driver___0 + 0UL) != 0U) { dev_priv->dplla_96mhz = 1; } else { dev_priv->dplla_96mhz = 0; } return; } } static void parse_device_mapping(struct drm_psb_private *dev_priv , struct bdb_header *bdb ) { struct bdb_general_definitions *p_defs ; struct child_device_config *p_child ; struct child_device_config *child_dev_ptr ; int i ; int child_device_num ; int count ; u16 block_size ; void *tmp ; long tmp___0 ; long tmp___1 ; long tmp___2 ; void *tmp___3 ; long tmp___4 ; { tmp = find_section(bdb, 2); p_defs = (struct bdb_general_definitions *)tmp; if ((unsigned long )p_defs == (unsigned long )((struct bdb_general_definitions *)0)) { tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("parse_device_mapping", "No general definition block is found, no devices defined.\n"); } else { } return; } else { } if ((unsigned int )p_defs->child_dev_size != 33U) { tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("parse_device_mapping", "different child size is found. Invalid.\n"); } else { } return; } else { } block_size = get_blocksize((void *)p_defs); child_device_num = (int )(((unsigned long )block_size - 5UL) / 33UL); count = 0; i = 0; goto ldv_41660; ldv_41659: p_child = (struct child_device_config *)(& p_defs->devices) + (unsigned long )i; if ((unsigned int )p_child->device_type == 0U) { goto ldv_41658; } else { } count = count + 1; ldv_41658: i = i + 1; ldv_41660: ; if (i < child_device_num) { goto ldv_41659; } else { } if (count == 0) { tmp___2 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("parse_device_mapping", "no child dev is parsed from VBT\n"); } else { } return; } else { } tmp___3 = kcalloc((size_t )count, 33UL, 208U); dev_priv->child_dev = (struct child_device_config *)tmp___3; if ((unsigned long )dev_priv->child_dev == (unsigned long )((struct child_device_config *)0)) { tmp___4 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("parse_device_mapping", "No memory space for child devices\n"); } else { } return; } else { } dev_priv->child_dev_num = count; count = 0; i = 0; goto ldv_41664; ldv_41663: p_child = (struct child_device_config *)(& p_defs->devices) + (unsigned long )i; if ((unsigned int )p_child->device_type == 0U) { goto ldv_41662; } else { } child_dev_ptr = dev_priv->child_dev + (unsigned long )count; count = count + 1; memcpy((void *)child_dev_ptr, (void const *)p_child, 33UL); ldv_41662: i = i + 1; ldv_41664: ; if (i < child_device_num) { goto ldv_41663; } else { } return; } } int psb_intel_init_bios(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct pci_dev *pdev ; struct vbt_header *vbt ; struct bdb_header *bdb ; u8 *bios ; size_t size ; int i ; struct vbt_header *vbt___0 ; long tmp ; int tmp___0 ; void *tmp___1 ; int tmp___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; pdev = dev->pdev; vbt = (struct vbt_header *)0; bdb = (struct bdb_header *)0; bios = (u8 *)0U; dev_priv->panel_type = 255U; if ((unsigned long )dev_priv->opregion.vbt != (unsigned long )((void *)0)) { vbt___0 = (struct vbt_header *)dev_priv->opregion.vbt; tmp___0 = memcmp((void const *)(& vbt___0->signature), (void const *)"$VBT", 4UL); if (tmp___0 == 0) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("psb_intel_init_bios", "Using VBT from OpRegion: %20s\n", (u8 *)(& vbt___0->signature)); } else { } bdb = (struct bdb_header *)vbt___0 + (unsigned long )vbt___0->bdb_offset; } else { dev_priv->opregion.vbt = (void *)0; } } else { } if ((unsigned long )bdb == (unsigned long )((struct bdb_header *)0)) { tmp___1 = pci_map_rom(pdev, & size); bios = (u8 *)tmp___1; if ((unsigned long )bios == (unsigned long )((u8 *)0U)) { return (-1); } else { } i = 0; goto ldv_41680; ldv_41679: tmp___2 = memcmp((void const *)bios + (unsigned long )i, (void const *)"$VBT", 4UL); if (tmp___2 == 0) { vbt = (struct vbt_header *)bios + (unsigned long )i; goto ldv_41678; } else { } i = i + 1; ldv_41680: ; if ((size_t )(i + 4) < size) { goto ldv_41679; } else { } ldv_41678: ; if ((unsigned long )vbt == (unsigned long )((struct vbt_header *)0)) { dev_err((struct device const *)dev->dev, "VBT signature missing\n"); pci_unmap_rom(pdev, (void *)bios); return (-1); } else { } bdb = (struct bdb_header *)(bios + ((unsigned long )i + (unsigned long )vbt->bdb_offset)); } else { } parse_general_features(dev_priv, bdb); parse_driver_features(dev_priv, bdb); parse_lfp_panel_data(dev_priv, bdb); parse_sdvo_panel_data(dev_priv, bdb); parse_sdvo_device_mapping(dev_priv, bdb); parse_device_mapping(dev_priv, bdb); parse_backlight_data(dev_priv, bdb); parse_edp(dev_priv, bdb); if ((unsigned long )bios != (unsigned long )((u8 *)0U)) { pci_unmap_rom(pdev, (void *)bios); } else { } return (0); } } void psb_intel_destroy_bios(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; kfree((void const *)dev_priv->sdvo_lvds_vbt_mode); kfree((void const *)dev_priv->lfp_lvds_vbt_mode); kfree((void const *)dev_priv->lvds_bl); return; } } bool ldv_queue_work_on_75(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_76(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_77(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_78(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_79(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } extern int snprintf(char * , size_t , char const * , ...) ; extern unsigned long __usecs_to_jiffies(unsigned int const ) ; __inline static unsigned long usecs_to_jiffies(unsigned int const u ) { unsigned long tmp___1 ; { tmp___1 = __usecs_to_jiffies(u); return (tmp___1); } } bool ldv_queue_work_on_89(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_91(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_90(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_93(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_92(struct workqueue_struct *ldv_func_arg1 ) ; __inline static void dev_set_drvdata(struct device *dev , void *data ) { { dev->driver_data = data; return; } } __inline static void i2c_set_adapdata(struct i2c_adapter *dev , void *data ) { { dev_set_drvdata(& dev->dev, data); return; } } extern void i2c_del_adapter(struct i2c_adapter * ) ; extern int i2c_bit_add_bus(struct i2c_adapter * ) ; extern void __const_udelay(unsigned long ) ; struct psb_intel_i2c_chan *psb_intel_i2c_create(struct drm_device *dev , u32 const reg , char const *name ) ; void psb_intel_i2c_destroy(struct psb_intel_i2c_chan *chan ) ; __inline static uint32_t REGISTER_READ(struct drm_device *dev , uint32_t reg ) { struct drm_psb_private *dev_priv ; unsigned int tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = ioread32((void *)dev_priv->vdc_reg + (unsigned long )reg); return (tmp); } } __inline static void REGISTER_WRITE(struct drm_device *dev , uint32_t reg , uint32_t val ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; iowrite32(val, (void *)dev_priv->vdc_reg + (unsigned long )reg); return; } } static int get_clock(void *data ) { struct psb_intel_i2c_chan *chan ; struct drm_device *dev ; u32 val ; { chan = (struct psb_intel_i2c_chan *)data; dev = chan->drm_dev; val = REGISTER_READ(dev, chan->reg); return ((val & 16U) != 0U); } } static int get_data(void *data ) { struct psb_intel_i2c_chan *chan ; struct drm_device *dev ; u32 val ; { chan = (struct psb_intel_i2c_chan *)data; dev = chan->drm_dev; val = REGISTER_READ(dev, chan->reg); return ((val & 4096U) != 0U); } } static void set_clock(void *data , int state_high ) { struct psb_intel_i2c_chan *chan ; struct drm_device *dev ; u32 reserved ; u32 clock_bits ; uint32_t tmp ; { chan = (struct psb_intel_i2c_chan *)data; dev = chan->drm_dev; reserved = 0U; tmp = REGISTER_READ(dev, chan->reg); reserved = tmp & 8224U; if (state_high != 0) { clock_bits = 1U; } else { clock_bits = 7U; } REGISTER_WRITE(dev, chan->reg, reserved | clock_bits); __const_udelay(85900UL); return; } } static void set_data(void *data , int state_high ) { struct psb_intel_i2c_chan *chan ; struct drm_device *dev ; u32 reserved ; u32 data_bits ; uint32_t tmp ; { chan = (struct psb_intel_i2c_chan *)data; dev = chan->drm_dev; reserved = 0U; tmp = REGISTER_READ(dev, chan->reg); reserved = tmp & 8224U; if (state_high != 0) { data_bits = 256U; } else { data_bits = 1792U; } REGISTER_WRITE(dev, chan->reg, reserved | data_bits); __const_udelay(85900UL); return; } } struct psb_intel_i2c_chan *psb_intel_i2c_create(struct drm_device *dev , u32 const reg , char const *name ) { struct psb_intel_i2c_chan *chan ; void *tmp ; unsigned long tmp___0 ; int tmp___1 ; { tmp = kzalloc(2024UL, 208U); chan = (struct psb_intel_i2c_chan *)tmp; if ((unsigned long )chan == (unsigned long )((struct psb_intel_i2c_chan *)0)) { goto out_free; } else { } chan->drm_dev = dev; chan->reg = reg; snprintf((char *)(& chan->adapter.name), 20UL, "intel drm %s", name); chan->adapter.owner = & __this_module; chan->adapter.algo_data = (void *)(& chan->algo); chan->adapter.dev.parent = & (dev->pdev)->dev; chan->algo.setsda = & set_data; chan->algo.setscl = & set_clock; chan->algo.getsda = & get_data; chan->algo.getscl = & get_clock; chan->algo.udelay = 20; tmp___0 = usecs_to_jiffies(2200U); chan->algo.timeout = (int )tmp___0; chan->algo.data = (void *)chan; i2c_set_adapdata(& chan->adapter, (void *)chan); tmp___1 = i2c_bit_add_bus(& chan->adapter); if (tmp___1 != 0) { goto out_free; } else { } set_data((void *)chan, 1); set_clock((void *)chan, 1); __const_udelay(85900UL); return (chan); out_free: kfree((void const *)chan); return ((struct psb_intel_i2c_chan *)0); } } void psb_intel_i2c_destroy(struct psb_intel_i2c_chan *chan ) { { if ((unsigned long )chan == (unsigned long )((struct psb_intel_i2c_chan *)0)) { return; } else { } i2c_del_adapter(& chan->adapter); kfree((void const *)chan); return; } } bool ldv_queue_work_on_89(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_90(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_91(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_92(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_93(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } extern int printk(char const * , ...) ; extern void __bad_percpu_size(void) ; extern void __bad_size_call_parameter(void) ; extern int __preempt_count ; __inline static int preempt_count(void) { int pfo_ret__ ; { switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret__): "m" (__preempt_count)); goto ldv_6002; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret__): "m" (__preempt_count)); goto ldv_6002; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret__): "m" (__preempt_count)); goto ldv_6002; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret__): "m" (__preempt_count)); goto ldv_6002; default: __bad_percpu_size(); } ldv_6002: ; return (pfo_ret__ & 2147483647); } } extern unsigned long __msecs_to_jiffies(unsigned int const ) ; __inline static unsigned long msecs_to_jiffies(unsigned int const m ) { unsigned long tmp___0 ; { tmp___0 = __msecs_to_jiffies(m); return (tmp___0); } } bool ldv_queue_work_on_103(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_105(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_104(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_107(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_106(struct workqueue_struct *ldv_func_arg1 ) ; extern int cpu_number ; struct i2c_adapter *gmbus_algorithm_group0 ; int ldv_state_variable_53 ; void ldv_initialize_i2c_algorithm_53(void) ; extern int i2c_add_adapter(struct i2c_adapter * ) ; extern atomic_t kgdb_active ; void gma_intel_i2c_reset(struct drm_device *dev ) ; int gma_intel_setup_gmbus(struct drm_device *dev ) ; void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter , int speed ) ; void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter , bool force_bit ) ; void gma_intel_teardown_gmbus(struct drm_device *dev ) ; __inline static struct intel_gmbus *to_intel_gmbus(struct i2c_adapter *i2c ) { struct i2c_adapter const *__mptr ; { __mptr = (struct i2c_adapter const *)i2c; return ((struct intel_gmbus *)__mptr); } } void gma_intel_i2c_reset(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; iowrite32(0U, (void *)dev_priv->gmbus_reg + 20736U); return; } } static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv , bool enable ) { { return; } } static u32 get_reserved(struct intel_gpio *gpio ) { struct drm_psb_private *dev_priv ; u32 reserved ; unsigned int tmp ; { dev_priv = gpio->dev_priv; reserved = 0U; tmp = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); reserved = tmp & 8224U; return (reserved); } } static int get_clock___0(void *data ) { struct intel_gpio *gpio ; struct drm_psb_private *dev_priv ; u32 reserved ; u32 tmp ; unsigned int tmp___0 ; { gpio = (struct intel_gpio *)data; dev_priv = gpio->dev_priv; tmp = get_reserved(gpio); reserved = tmp; iowrite32(reserved | 1U, (void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); iowrite32(reserved, (void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); tmp___0 = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); return ((tmp___0 & 16U) != 0U); } } static int get_data___0(void *data ) { struct intel_gpio *gpio ; struct drm_psb_private *dev_priv ; u32 reserved ; u32 tmp ; unsigned int tmp___0 ; { gpio = (struct intel_gpio *)data; dev_priv = gpio->dev_priv; tmp = get_reserved(gpio); reserved = tmp; iowrite32(reserved | 256U, (void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); iowrite32(reserved, (void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); tmp___0 = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); return ((tmp___0 & 4096U) != 0U); } } static void set_clock___0(void *data , int state_high ) { struct intel_gpio *gpio ; struct drm_psb_private *dev_priv ; u32 reserved ; u32 tmp ; u32 clock_bits ; { gpio = (struct intel_gpio *)data; dev_priv = gpio->dev_priv; tmp = get_reserved(gpio); reserved = tmp; if (state_high != 0) { clock_bits = 1U; } else { clock_bits = 7U; } iowrite32(reserved | clock_bits, (void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); ioread32((void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); return; } } static void set_data___0(void *data , int state_high ) { struct intel_gpio *gpio ; struct drm_psb_private *dev_priv ; u32 reserved ; u32 tmp ; u32 data_bits ; { gpio = (struct intel_gpio *)data; dev_priv = gpio->dev_priv; tmp = get_reserved(gpio); reserved = tmp; if (state_high != 0) { data_bits = 256U; } else { data_bits = 1792U; } iowrite32(reserved | data_bits, (void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); ioread32((void *)dev_priv->gmbus_reg + (unsigned long )gpio->reg); return; } } static struct i2c_adapter *intel_gpio_create(struct drm_psb_private *dev_priv , u32 pin ) { int map_pin_to_reg[8U] ; struct intel_gpio *gpio ; void *tmp ; unsigned long tmp___0 ; int tmp___1 ; { map_pin_to_reg[0] = 0; map_pin_to_reg[1] = 20500; map_pin_to_reg[2] = 20496; map_pin_to_reg[3] = 20504; map_pin_to_reg[4] = 20508; map_pin_to_reg[5] = 20512; map_pin_to_reg[6] = 0; map_pin_to_reg[7] = 20516; if (pin > 7U || map_pin_to_reg[pin] == 0) { return ((struct i2c_adapter *)0); } else { } tmp = kzalloc(2016UL, 208U); gpio = (struct intel_gpio *)tmp; if ((unsigned long )gpio == (unsigned long )((struct intel_gpio *)0)) { return ((struct i2c_adapter *)0); } else { } gpio->reg = (u32 )map_pin_to_reg[pin]; gpio->dev_priv = dev_priv; snprintf((char *)(& gpio->adapter.name), 48UL, "gma500 GPIO%c", (int )*("?BACDE?F" + pin)); gpio->adapter.owner = & __this_module; gpio->adapter.algo_data = (void *)(& gpio->algo); gpio->adapter.dev.parent = & ((dev_priv->dev)->pdev)->dev; gpio->algo.setsda = & set_data___0; gpio->algo.setscl = & set_clock___0; gpio->algo.getsda = & get_data___0; gpio->algo.getscl = & get_clock___0; gpio->algo.udelay = 20; tmp___0 = usecs_to_jiffies(2200U); gpio->algo.timeout = (int )tmp___0; gpio->algo.data = (void *)gpio; tmp___1 = i2c_bit_add_bus(& gpio->adapter); if (tmp___1 != 0) { goto out_free; } else { } return (& gpio->adapter); out_free: kfree((void const *)gpio); return ((struct i2c_adapter *)0); } } static int intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv , struct i2c_adapter *adapter , struct i2c_msg *msgs , int num ) { struct intel_gpio *gpio ; struct i2c_adapter const *__mptr ; int ret ; { __mptr = (struct i2c_adapter const *)adapter; gpio = (struct intel_gpio *)__mptr; gma_intel_i2c_reset(dev_priv->dev); intel_i2c_quirk_set(dev_priv, 1); set_data___0((void *)gpio, 1); set_clock___0((void *)gpio, 1); __const_udelay(85900UL); ret = (*((adapter->algo)->master_xfer))(adapter, msgs, num); set_data___0((void *)gpio, 1); set_clock___0((void *)gpio, 1); intel_i2c_quirk_set(dev_priv, 0); return (ret); } } static int gmbus_xfer(struct i2c_adapter *adapter , struct i2c_msg *msgs , int num ) { struct intel_gmbus *bus ; struct i2c_adapter const *__mptr ; struct drm_psb_private *dev_priv ; int i ; int reg_offset ; int tmp ; u16 len ; u8 *buf ; u32 val ; u32 loop ; unsigned long timeout__ ; unsigned long tmp___0 ; int ret__ ; int tmp___1 ; int pscr_ret__ ; void const *__vpp_verify ; int pfo_ret__ ; int pfo_ret_____0 ; int pfo_ret_____1 ; int pfo_ret_____2 ; int tmp___2 ; unsigned int tmp___3 ; unsigned int tmp___4 ; u8 *tmp___5 ; u32 val___0 ; u32 loop___0 ; u8 *tmp___6 ; unsigned long timeout_____0 ; unsigned long tmp___7 ; int ret_____0 ; int tmp___8 ; int pscr_ret_____0 ; void const *__vpp_verify___0 ; int pfo_ret_____3 ; int pfo_ret_____4 ; int pfo_ret_____5 ; int pfo_ret_____6 ; int tmp___9 ; unsigned int tmp___10 ; unsigned int tmp___11 ; u8 *tmp___12 ; unsigned long timeout_____1 ; unsigned long tmp___13 ; int ret_____1 ; int tmp___14 ; int pscr_ret_____1 ; void const *__vpp_verify___1 ; int pfo_ret_____7 ; int pfo_ret_____8 ; int pfo_ret_____9 ; int pfo_ret_____10 ; int tmp___15 ; unsigned int tmp___16 ; unsigned int tmp___17 ; int tmp___18 ; { __mptr = (struct i2c_adapter const *)adapter; bus = (struct intel_gmbus *)__mptr; dev_priv = (struct drm_psb_private *)adapter->algo_data; if ((unsigned long )bus->force_bit != (unsigned long )((struct i2c_adapter *)0)) { tmp = intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num); return (tmp); } else { } reg_offset = 0; iowrite32(bus->reg0, (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20736)); i = 0; goto ldv_41804; ldv_41803: len = (msgs + (unsigned long )i)->len; buf = (msgs + (unsigned long )i)->buf; if ((int )(msgs + (unsigned long )i)->flags & 1) { iowrite32((u32 )((((i + 1 == num ? 167772160 : 33554432) | ((int )len << 16)) | ((int )(msgs + (unsigned long )i)->addr << 1)) | 1073741825), (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20740)); ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); ldv_41686: loop = 0U; tmp___0 = msecs_to_jiffies(50U); timeout__ = tmp___0 + (unsigned long )jiffies; ret__ = 0; goto ldv_41680; ldv_41679: ; if ((long )(timeout__ - (unsigned long )jiffies) < 0L) { ret__ = -110; goto ldv_41637; } else { } tmp___1 = preempt_count(); if (tmp___1 == 0) { __vpp_verify = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret__): "m" (cpu_number)); goto ldv_41643; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41643; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41643; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41643; default: __bad_percpu_size(); } ldv_41643: pscr_ret__ = pfo_ret__; goto ldv_41649; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41653; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41653; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41653; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41653; default: __bad_percpu_size(); } ldv_41653: pscr_ret__ = pfo_ret_____0; goto ldv_41649; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41662; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41662; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41662; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41662; default: __bad_percpu_size(); } ldv_41662: pscr_ret__ = pfo_ret_____1; goto ldv_41649; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41671; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41671; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41671; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41671; default: __bad_percpu_size(); } ldv_41671: pscr_ret__ = pfo_ret_____2; goto ldv_41649; default: __bad_size_call_parameter(); goto ldv_41649; } ldv_41649: tmp___2 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret__ != tmp___2) { msleep(1U); } else { } } else { } ldv_41680: tmp___3 = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); if ((tmp___3 & 3072U) == 0U) { goto ldv_41679; } else { } ldv_41637: ; if (ret__ != 0) { goto timeout; } else { } tmp___4 = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); if ((tmp___4 & 1024U) != 0U) { goto clear_err; } else { } val = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20748)); ldv_41684: tmp___5 = buf; buf = buf + 1; *tmp___5 = (u8 )val; val = val >> 8; len = (u16 )((int )len - 1); if ((unsigned int )len != 0U) { loop = loop + 1U; if (loop <= 3U) { goto ldv_41684; } else { goto ldv_41685; } } else { } ldv_41685: ; if ((unsigned int )len != 0U) { goto ldv_41686; } else { } } else { loop___0 = 0U; val___0 = loop___0; ldv_41690: tmp___6 = buf; buf = buf + 1; val___0 = (u32 )((int )*tmp___6 << (int )(loop___0 * 8U)) | val___0; len = (u16 )((int )len - 1); if ((unsigned int )len != 0U) { loop___0 = loop___0 + 1U; if (loop___0 <= 3U) { goto ldv_41690; } else { goto ldv_41691; } } else { } ldv_41691: iowrite32(val___0, (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20748)); iowrite32((u32 )((((i + 1 == num ? 134217728 : 33554432) | ((int )(msgs + (unsigned long )i)->len << 16)) | ((int )(msgs + (unsigned long )i)->addr << 1)) | 1073741824), (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20740)); ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); goto ldv_41748; ldv_41747: tmp___7 = msecs_to_jiffies(50U); timeout_____0 = tmp___7 + (unsigned long )jiffies; ret_____0 = 0; goto ldv_41743; ldv_41742: ; if ((long )(timeout_____0 - (unsigned long )jiffies) < 0L) { ret_____0 = -110; goto ldv_41700; } else { } tmp___8 = preempt_count(); if (tmp___8 == 0) { __vpp_verify___0 = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41706; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41706; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41706; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41706; default: __bad_percpu_size(); } ldv_41706: pscr_ret_____0 = pfo_ret_____3; goto ldv_41712; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41716; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41716; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41716; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41716; default: __bad_percpu_size(); } ldv_41716: pscr_ret_____0 = pfo_ret_____4; goto ldv_41712; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41725; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41725; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41725; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41725; default: __bad_percpu_size(); } ldv_41725: pscr_ret_____0 = pfo_ret_____5; goto ldv_41712; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41734; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41734; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41734; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41734; default: __bad_percpu_size(); } ldv_41734: pscr_ret_____0 = pfo_ret_____6; goto ldv_41712; default: __bad_size_call_parameter(); goto ldv_41712; } ldv_41712: tmp___9 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret_____0 != tmp___9) { msleep(1U); } else { } } else { } ldv_41743: tmp___10 = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); if ((tmp___10 & 3072U) == 0U) { goto ldv_41742; } else { } ldv_41700: ; if (ret_____0 != 0) { goto timeout; } else { } tmp___11 = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); if ((tmp___11 & 1024U) != 0U) { goto clear_err; } else { } loop___0 = 0U; val___0 = loop___0; ldv_41745: tmp___12 = buf; buf = buf + 1; val___0 = (u32 )((int )*tmp___12 << (int )(loop___0 * 8U)) | val___0; len = (u16 )((int )len - 1); if ((unsigned int )len != 0U) { loop___0 = loop___0 + 1U; if (loop___0 <= 3U) { goto ldv_41745; } else { goto ldv_41746; } } else { } ldv_41746: iowrite32(val___0, (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20748)); ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); ldv_41748: ; if ((unsigned int )len != 0U) { goto ldv_41747; } else { } } if (i + 1 < num) { tmp___13 = msecs_to_jiffies(50U); timeout_____1 = tmp___13 + (unsigned long )jiffies; ret_____1 = 0; goto ldv_41801; ldv_41800: ; if ((long )(timeout_____1 - (unsigned long )jiffies) < 0L) { ret_____1 = -110; goto ldv_41758; } else { } tmp___14 = preempt_count(); if (tmp___14 == 0) { __vpp_verify___1 = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____7): "m" (cpu_number)); goto ldv_41764; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____7): "m" (cpu_number)); goto ldv_41764; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____7): "m" (cpu_number)); goto ldv_41764; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____7): "m" (cpu_number)); goto ldv_41764; default: __bad_percpu_size(); } ldv_41764: pscr_ret_____1 = pfo_ret_____7; goto ldv_41770; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____8): "m" (cpu_number)); goto ldv_41774; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____8): "m" (cpu_number)); goto ldv_41774; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____8): "m" (cpu_number)); goto ldv_41774; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____8): "m" (cpu_number)); goto ldv_41774; default: __bad_percpu_size(); } ldv_41774: pscr_ret_____1 = pfo_ret_____8; goto ldv_41770; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____9): "m" (cpu_number)); goto ldv_41783; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____9): "m" (cpu_number)); goto ldv_41783; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____9): "m" (cpu_number)); goto ldv_41783; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____9): "m" (cpu_number)); goto ldv_41783; default: __bad_percpu_size(); } ldv_41783: pscr_ret_____1 = pfo_ret_____9; goto ldv_41770; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____10): "m" (cpu_number)); goto ldv_41792; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____10): "m" (cpu_number)); goto ldv_41792; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____10): "m" (cpu_number)); goto ldv_41792; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____10): "m" (cpu_number)); goto ldv_41792; default: __bad_percpu_size(); } ldv_41792: pscr_ret_____1 = pfo_ret_____10; goto ldv_41770; default: __bad_size_call_parameter(); goto ldv_41770; } ldv_41770: tmp___15 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret_____1 != tmp___15) { msleep(1U); } else { } } else { } ldv_41801: tmp___16 = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); if ((tmp___16 & 17408U) == 0U) { goto ldv_41800; } else { } ldv_41758: ; if (ret_____1 != 0) { goto timeout; } else { } } else { } tmp___17 = ioread32((void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20744)); if ((tmp___17 & 1024U) != 0U) { goto clear_err; } else { } i = i + 1; ldv_41804: ; if (i < num) { goto ldv_41803; } else { } goto done; clear_err: iowrite32(2147483648U, (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20740)); iowrite32(0U, (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20740)); done: iowrite32(0U, (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20736)); return (i); timeout: printk("\016[drm] GMBUS timed out, falling back to bit banging on pin %d [%s]\n", bus->reg0 & 255U, (char *)(& bus->adapter.name)); iowrite32(0U, (void *)dev_priv->gmbus_reg + (unsigned long )(reg_offset + 20736)); bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 255U); if ((unsigned long )bus->force_bit == (unsigned long )((struct i2c_adapter *)0)) { return (-12); } else { } tmp___18 = intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num); return (tmp___18); } } static u32 gmbus_func(struct i2c_adapter *adapter ) { struct intel_gmbus *bus ; struct i2c_adapter const *__mptr ; { __mptr = (struct i2c_adapter const *)adapter; bus = (struct intel_gmbus *)__mptr; if ((unsigned long )bus->force_bit != (unsigned long )((struct i2c_adapter *)0)) { (*(((bus->force_bit)->algo)->functionality))(bus->force_bit); } else { } return (268402697U); } } static struct i2c_algorithm const gmbus_algorithm = {& gmbus_xfer, 0, & gmbus_func, 0, 0}; int gma_intel_setup_gmbus(struct drm_device *dev ) { char const *names[8U] ; struct drm_psb_private *dev_priv ; int ret ; int i ; void *tmp ; struct intel_gmbus *bus ; struct intel_gmbus *bus___0 ; { names[0] = "disabled"; names[1] = "ssc"; names[2] = "vga"; names[3] = "panel"; names[4] = "dpc"; names[5] = "dpb"; names[6] = "reserved"; names[7] = "dpd"; dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = kcalloc(8UL, 1952UL, 208U); dev_priv->gmbus = (struct intel_gmbus *)tmp; if ((unsigned long )dev_priv->gmbus == (unsigned long )((struct intel_gmbus *)0)) { return (-12); } else { } if (((int )(dev->pdev)->device & 65520) == 16640) { dev_priv->gmbus_reg = dev_priv->aux_reg; } else { dev_priv->gmbus_reg = dev_priv->vdc_reg; } i = 0; goto ldv_41824; ldv_41823: bus = dev_priv->gmbus + (unsigned long )i; bus->adapter.owner = & __this_module; bus->adapter.class = 8U; snprintf((char *)(& bus->adapter.name), 48UL, "gma500 gmbus %s", names[i]); bus->adapter.dev.parent = & (dev->pdev)->dev; bus->adapter.algo_data = (void *)dev_priv; bus->adapter.algo = & gmbus_algorithm; ret = i2c_add_adapter(& bus->adapter); if (ret != 0) { goto err; } else { } bus->reg0 = (u32 )i; bus->force_bit = intel_gpio_create(dev_priv, (u32 )i); i = i + 1; ldv_41824: ; if (i <= 7) { goto ldv_41823; } else { } gma_intel_i2c_reset(dev_priv->dev); return (0); err: ; goto ldv_41828; ldv_41827: bus___0 = dev_priv->gmbus + (unsigned long )i; i2c_del_adapter(& bus___0->adapter); ldv_41828: i = i - 1; if (i != 0) { goto ldv_41827; } else { } kfree((void const *)dev_priv->gmbus); dev_priv->gmbus = (struct intel_gmbus *)0; return (ret); } } void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter , int speed ) { struct intel_gmbus *bus ; struct intel_gmbus *tmp ; { tmp = to_intel_gmbus(adapter); bus = tmp; bus->reg0 = (bus->reg0 & 4294966527U) | (u32 )(speed << 8); return; } } void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter , bool force_bit ) { struct intel_gmbus *bus ; struct intel_gmbus *tmp ; struct drm_psb_private *dev_priv ; { tmp = to_intel_gmbus(adapter); bus = tmp; if ((int )force_bit) { if ((unsigned long )bus->force_bit == (unsigned long )((struct i2c_adapter *)0)) { dev_priv = (struct drm_psb_private *)adapter->algo_data; bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 255U); } else { } } else if ((unsigned long )bus->force_bit != (unsigned long )((struct i2c_adapter *)0)) { i2c_del_adapter(bus->force_bit); kfree((void const *)bus->force_bit); bus->force_bit = (struct i2c_adapter *)0; } else { } return; } } void gma_intel_teardown_gmbus(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; int i ; struct intel_gmbus *bus ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if ((unsigned long )dev_priv->gmbus == (unsigned long )((struct intel_gmbus *)0)) { return; } else { } i = 0; goto ldv_41848; ldv_41847: bus = dev_priv->gmbus + (unsigned long )i; if ((unsigned long )bus->force_bit != (unsigned long )((struct i2c_adapter *)0)) { i2c_del_adapter(bus->force_bit); kfree((void const *)bus->force_bit); } else { } i2c_del_adapter(& bus->adapter); i = i + 1; ldv_41848: ; if (i <= 7) { goto ldv_41847; } else { } dev_priv->gmbus_reg = (uint8_t *)0U; kfree((void const *)dev_priv->gmbus); dev_priv->gmbus = (struct intel_gmbus *)0; return; } } void ldv_initialize_i2c_algorithm_53(void) { void *tmp ; { tmp = ldv_init_zalloc(1936UL); gmbus_algorithm_group0 = (struct i2c_adapter *)tmp; return; } } void ldv_main_exported_53(void) { struct i2c_msg *ldvarg109 ; void *tmp ; int ldvarg108 ; int tmp___0 ; { tmp = ldv_init_zalloc(16UL); ldvarg109 = (struct i2c_msg *)tmp; ldv_memset((void *)(& ldvarg108), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_53 == 1) { gmbus_xfer(gmbus_algorithm_group0, ldvarg109, ldvarg108); ldv_state_variable_53 = 1; } else { } goto ldv_41859; case 1: ; if (ldv_state_variable_53 == 1) { gmbus_func(gmbus_algorithm_group0); ldv_state_variable_53 = 1; } else { } goto ldv_41859; default: ldv_stop(); } ldv_41859: ; return; } } bool ldv_queue_work_on_103(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_104(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_105(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_106(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_107(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; extern struct pv_cpu_ops pv_cpu_ops ; __inline static int constant_test_bit(long nr , unsigned long const volatile *addr ) { { return ((int )((unsigned long )*(addr + (unsigned long )(nr >> 6)) >> ((int )nr & 63)) & 1); } } extern void __might_sleep(char const * , int , int ) ; extern void clear_page(void * ) ; extern struct task_struct *current_task ; __inline static struct task_struct *get_current(void) { struct task_struct *pfo_ret__ ; { switch (8UL) { case 1UL: __asm__ ("movb %%gs:%P1,%0": "=q" (pfo_ret__): "p" (& current_task)); goto ldv_3129; case 2UL: __asm__ ("movw %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& current_task)); goto ldv_3129; case 4UL: __asm__ ("movl %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& current_task)); goto ldv_3129; case 8UL: __asm__ ("movq %%gs:%P1,%0": "=r" (pfo_ret__): "p" (& current_task)); goto ldv_3129; default: __bad_percpu_size(); } ldv_3129: ; return (pfo_ret__); } } __inline static void __cpuid(unsigned int *eax , unsigned int *ebx , unsigned int *ecx , unsigned int *edx ) { unsigned long __edi ; unsigned long __esi ; unsigned long __edx ; unsigned long __ecx ; unsigned long __eax ; long tmp ; { __edi = __edi; __esi = __esi; __edx = __edx; __ecx = __ecx; __eax = __eax; tmp = ldv__builtin_expect((unsigned long )pv_cpu_ops.cpuid == (unsigned long )((void (*)(unsigned int * , unsigned int * , unsigned int * , unsigned int * ))0), 0L); if (tmp != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"./arch/x86/include/asm/paravirt.h"), "i" (32), "i" (12UL)); ldv_3863: ; goto ldv_3863; } else { } __asm__ volatile ("771:\n\tcall *%c5;\n772:\n.pushsection .parainstructions,\"a\"\n .balign 8 \n .quad 771b\n .byte %c4\n .byte 772b-771b\n .short %c6\n.popsection\n": "=D" (__edi), "=S" (__esi), "=d" (__edx), "=c" (__ecx): [paravirt_typenum] "i" (31UL), [paravirt_opptr] "i" (& pv_cpu_ops.cpuid), [paravirt_clobber] "i" (511), "D" ((unsigned long )eax), "S" ((unsigned long )ebx), "d" ((unsigned long )ecx), "c" ((unsigned long )edx): "memory", "cc", "rax", "r8", "r9", "r10", "r11"); return; } } __inline static void cpuid(unsigned int op , unsigned int *eax , unsigned int *ebx , unsigned int *ecx , unsigned int *edx ) { { *eax = op; *ecx = 0U; __cpuid(eax, ebx, ecx, edx); return; } } __inline static void atomic_set(atomic_t *v , int i ) { { v->counter = i; return; } } __inline static void __preempt_count_add(int val ) { int pao_ID__ ; { pao_ID__ = 0; switch (4UL) { case 1UL: ; if (pao_ID__ == 1) { __asm__ ("incb %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decb %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addb %1, %%gs:%0": "+m" (__preempt_count): "qi" (val)); } goto ldv_6059; case 2UL: ; if (pao_ID__ == 1) { __asm__ ("incw %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decw %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addw %1, %%gs:%0": "+m" (__preempt_count): "ri" (val)); } goto ldv_6059; case 4UL: ; if (pao_ID__ == 1) { __asm__ ("incl %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decl %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addl %1, %%gs:%0": "+m" (__preempt_count): "ri" (val)); } goto ldv_6059; case 8UL: ; if (pao_ID__ == 1) { __asm__ ("incq %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decq %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addq %1, %%gs:%0": "+m" (__preempt_count): "re" (val)); } goto ldv_6059; default: __bad_percpu_size(); } ldv_6059: ; return; } } __inline static void __preempt_count_sub(int val ) { int pao_ID__ ; { pao_ID__ = 0; switch (4UL) { case 1UL: ; if (pao_ID__ == 1) { __asm__ ("incb %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decb %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addb %1, %%gs:%0": "+m" (__preempt_count): "qi" (- val)); } goto ldv_6071; case 2UL: ; if (pao_ID__ == 1) { __asm__ ("incw %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decw %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addw %1, %%gs:%0": "+m" (__preempt_count): "ri" (- val)); } goto ldv_6071; case 4UL: ; if (pao_ID__ == 1) { __asm__ ("incl %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decl %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addl %1, %%gs:%0": "+m" (__preempt_count): "ri" (- val)); } goto ldv_6071; case 8UL: ; if (pao_ID__ == 1) { __asm__ ("incq %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decq %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addq %1, %%gs:%0": "+m" (__preempt_count): "re" (- val)); } goto ldv_6071; default: __bad_percpu_size(); } ldv_6071: ; return; } } extern void __raw_spin_lock_init(raw_spinlock_t * , char const * , struct lock_class_key * ) ; extern void _raw_spin_lock(raw_spinlock_t * ) ; extern void _raw_spin_unlock(raw_spinlock_t * ) ; __inline static void spin_lock(spinlock_t *lock ) { { _raw_spin_lock(& lock->__annonCompField18.rlock); return; } } __inline static void spin_unlock(spinlock_t *lock ) { { _raw_spin_unlock(& lock->__annonCompField18.rlock); return; } } extern void down_read(struct rw_semaphore * ) ; extern void down_write(struct rw_semaphore * ) ; extern void up_read(struct rw_semaphore * ) ; extern void up_write(struct rw_semaphore * ) ; bool ldv_queue_work_on_117(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_119(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_118(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_121(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_120(struct workqueue_struct *ldv_func_arg1 ) ; extern struct page *alloc_pages_current(gfp_t , unsigned int ) ; __inline static struct page *alloc_pages(gfp_t gfp_mask , unsigned int order ) { struct page *tmp ; { tmp = alloc_pages_current(gfp_mask, order); return (tmp); } } extern void __free_pages(struct page * , unsigned int ) ; __inline static void *lowmem_page_address(struct page const *page ) { { return ((void *)((unsigned long )((unsigned long long )(((long )page + 24189255811072L) / 64L) << 12) + 0xffff880000000000UL)); } } __inline static void pagefault_disabled_inc(void) { struct task_struct *tmp ; { tmp = get_current(); tmp->pagefault_disabled = tmp->pagefault_disabled + 1; return; } } __inline static void pagefault_disabled_dec(void) { struct task_struct *tmp ; int __ret_warn_on ; struct task_struct *tmp___0 ; long tmp___1 ; { tmp = get_current(); tmp->pagefault_disabled = tmp->pagefault_disabled - 1; tmp___0 = get_current(); __ret_warn_on = tmp___0->pagefault_disabled < 0; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_null("include/linux/uaccess.h", 15); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return; } } __inline static void pagefault_disable(void) { { pagefault_disabled_inc(); __asm__ volatile ("": : : "memory"); return; } } __inline static void pagefault_enable(void) { { __asm__ volatile ("": : : "memory"); pagefault_disabled_dec(); return; } } __inline static void *kmap(struct page *page ) { void *tmp ; { __might_sleep("include/linux/highmem.h", 58, 0); tmp = lowmem_page_address((struct page const *)page); return (tmp); } } __inline static void kunmap(struct page *page ) { { return; } } __inline static void *kmap_atomic(struct page *page ) { void *tmp ; { __preempt_count_add(1); __asm__ volatile ("": : : "memory"); pagefault_disable(); tmp = lowmem_page_address((struct page const *)page); return (tmp); } } __inline static void __kunmap_atomic(void *addr ) { { pagefault_enable(); __asm__ volatile ("": : : "memory"); __preempt_count_sub(1); return; } } extern void *vmalloc_user(unsigned long ) ; extern void vfree(void const * ) ; struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev , int trap_pagefaults , int invalid_type , atomic_t *msvdx_mmu_invaldc ) ; void psb_mmu_driver_takedown(struct psb_mmu_driver *driver___0 ) ; struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver___0 , int trap_pagefaults , int invalid_type ) ; void psb_mmu_free_pagedir(struct psb_mmu_pd *pd ) ; void psb_mmu_flush(struct psb_mmu_driver *driver___0 ) ; void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd , unsigned long address , uint32_t num_pages ) ; int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd , uint32_t start_pfn , unsigned long address , uint32_t num_pages , int type ) ; int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd , uint32_t virtual , unsigned long *pfn ) ; void psb_mmu_set_pd_context(struct psb_mmu_pd *pd , int hw_context ) ; __inline static uint32_t psb_mmu_pt_index(uint32_t offset ) { { return ((offset >> 12) & 1023U); } } __inline static uint32_t psb_mmu_pd_index(uint32_t offset ) { { return (offset >> 22); } } __inline static void psb_clflush(void *addr ) { { __asm__ volatile ("clflush (%0)\n": : "r" (addr): "memory"); return; } } __inline static void psb_mmu_clflush(struct psb_mmu_driver *driver___0 , void *addr ) { { if (driver___0->has_clflush == 0) { return; } else { } __asm__ volatile ("mfence": : : "memory"); psb_clflush(addr); __asm__ volatile ("mfence": : : "memory"); return; } } static void psb_mmu_flush_pd_locked(struct psb_mmu_driver *driver___0 , int force ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; uint32_t val ; unsigned int tmp ; int tmp___0 ; { dev = driver___0->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; tmp___0 = atomic_read((atomic_t const *)(& driver___0->needs_tlbflush)); if (tmp___0 != 0 || force != 0) { tmp = ioread32((void *)dev_priv->sgx_reg + 3072U); val = tmp; iowrite32(val | 8U, (void *)dev_priv->sgx_reg + 3072U); __asm__ volatile ("sfence": : : "memory"); iowrite32(val & 4294967287U, (void *)dev_priv->sgx_reg + 3072U); ioread32((void *)dev_priv->sgx_reg + 3072U); if ((unsigned long )driver___0->msvdx_mmu_invaldc != (unsigned long )((atomic_t *)0)) { atomic_set(driver___0->msvdx_mmu_invaldc, 1); } else { } } else { } atomic_set(& driver___0->needs_tlbflush, 0); return; } } void psb_mmu_flush(struct psb_mmu_driver *driver___0 ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; uint32_t val ; int tmp ; { dev = driver___0->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; down_write(& driver___0->sem); val = ioread32((void *)dev_priv->sgx_reg + 3072U); tmp = atomic_read((atomic_t const *)(& driver___0->needs_tlbflush)); if (tmp != 0) { iowrite32(val | 8U, (void *)dev_priv->sgx_reg + 3072U); } else { iowrite32(val | 4U, (void *)dev_priv->sgx_reg + 3072U); } __asm__ volatile ("sfence": : : "memory"); iowrite32(val & 4294967283U, (void *)dev_priv->sgx_reg + 3072U); ioread32((void *)dev_priv->sgx_reg + 3072U); atomic_set(& driver___0->needs_tlbflush, 0); if ((unsigned long )driver___0->msvdx_mmu_invaldc != (unsigned long )((atomic_t *)0)) { atomic_set(driver___0->msvdx_mmu_invaldc, 1); } else { } up_write(& driver___0->sem); return; } } void psb_mmu_set_pd_context(struct psb_mmu_pd *pd , int hw_context ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; uint32_t offset ; { dev = (pd->driver)->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; offset = hw_context != 0 ? (uint32_t )((hw_context + 782) * 4) : 3204U; down_write(& (pd->driver)->sem); iowrite32((u32 )(((long )pd->p + 24189255811072L) / 64L) << 12U, (void *)dev_priv->sgx_reg + (unsigned long )offset); __asm__ volatile ("sfence": : : "memory"); psb_mmu_flush_pd_locked(pd->driver, 1); pd->hw_context = hw_context; up_write(& (pd->driver)->sem); return; } } __inline static unsigned long psb_pd_addr_end(unsigned long addr , unsigned long end ) { { addr = (addr + 4194304UL) & 0xffffffffffc00000UL; return (addr < end ? addr : end); } } __inline static uint32_t psb_mmu_mask_pte(uint32_t pfn , int type ) { uint32_t mask ; { mask = 1U; if (type & 1) { mask = mask | 8U; } else { } if ((type & 2) != 0) { mask = mask | 4U; } else { } if ((type & 4) != 0) { mask = mask | 2U; } else { } return ((pfn << 12) | mask); } } struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver___0 , int trap_pagefaults , int invalid_type ) { struct psb_mmu_pd *pd ; void *tmp ; uint32_t *v ; int i ; void *tmp___0 ; void *tmp___1 ; void *tmp___2 ; void *tmp___3 ; { tmp = kmalloc(64UL, 208U); pd = (struct psb_mmu_pd *)tmp; if ((unsigned long )pd == (unsigned long )((struct psb_mmu_pd *)0)) { return ((struct psb_mmu_pd *)0); } else { } pd->p = alloc_pages(4U, 0U); if ((unsigned long )pd->p == (unsigned long )((struct page *)0)) { goto out_err1; } else { } pd->dummy_pt = alloc_pages(4U, 0U); if ((unsigned long )pd->dummy_pt == (unsigned long )((struct page *)0)) { goto out_err2; } else { } pd->dummy_page = alloc_pages(4U, 0U); if ((unsigned long )pd->dummy_page == (unsigned long )((struct page *)0)) { goto out_err3; } else { } if (trap_pagefaults == 0) { pd->invalid_pde = psb_mmu_mask_pte((uint32_t )(((long )pd->dummy_pt + 24189255811072L) / 64L), invalid_type); pd->invalid_pte = psb_mmu_mask_pte((uint32_t )(((long )pd->dummy_page + 24189255811072L) / 64L), invalid_type); } else { pd->invalid_pde = 0U; pd->invalid_pte = 0U; } tmp___0 = kmap(pd->dummy_pt); v = (uint32_t *)tmp___0; i = 0; goto ldv_41570; ldv_41569: *(v + (unsigned long )i) = pd->invalid_pte; i = i + 1; ldv_41570: ; if ((unsigned int )i <= 1023U) { goto ldv_41569; } else { } kunmap(pd->dummy_pt); tmp___1 = kmap(pd->p); v = (uint32_t *)tmp___1; i = 0; goto ldv_41573; ldv_41572: *(v + (unsigned long )i) = pd->invalid_pde; i = i + 1; ldv_41573: ; if ((unsigned int )i <= 1023U) { goto ldv_41572; } else { } kunmap(pd->p); tmp___2 = kmap(pd->dummy_page); clear_page(tmp___2); kunmap(pd->dummy_page); tmp___3 = vmalloc_user(8192UL); pd->tables = (struct psb_mmu_pt **)tmp___3; if ((unsigned long )pd->tables == (unsigned long )((struct psb_mmu_pt **)0)) { goto out_err4; } else { } pd->hw_context = -1; pd->pd_mask = 1U; pd->driver = driver___0; return (pd); out_err4: __free_pages(pd->dummy_page, 0U); out_err3: __free_pages(pd->dummy_pt, 0U); out_err2: __free_pages(pd->p, 0U); out_err1: kfree((void const *)pd); return ((struct psb_mmu_pd *)0); } } static void psb_mmu_free_pt(struct psb_mmu_pt *pt ) { { __free_pages(pt->p, 0U); kfree((void const *)pt); return; } } void psb_mmu_free_pagedir(struct psb_mmu_pd *pd ) { struct psb_mmu_driver *driver___0 ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_mmu_pt *pt ; int i ; { driver___0 = pd->driver; dev = driver___0->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; down_write(& driver___0->sem); if (pd->hw_context != -1) { iowrite32(0U, (void *)dev_priv->sgx_reg + (unsigned long )((pd->hw_context + 801) * 4)); psb_mmu_flush_pd_locked(driver___0, 1); } else { } i = 0; goto ldv_41588; ldv_41587: pt = *(pd->tables + (unsigned long )i); if ((unsigned long )pt != (unsigned long )((struct psb_mmu_pt *)0)) { psb_mmu_free_pt(pt); } else { } i = i + 1; ldv_41588: ; if (i <= 1023) { goto ldv_41587; } else { } vfree((void const *)pd->tables); __free_pages(pd->dummy_page, 0U); __free_pages(pd->dummy_pt, 0U); __free_pages(pd->p, 0U); kfree((void const *)pd); up_write(& driver___0->sem); return; } } static struct psb_mmu_pt *psb_mmu_alloc_pt(struct psb_mmu_pd *pd ) { struct psb_mmu_pt *pt ; void *tmp ; void *v ; uint32_t clflush_add ; uint32_t clflush_count ; spinlock_t *lock ; uint8_t *clf ; uint32_t *ptes ; int i ; uint32_t *tmp___0 ; { tmp = kmalloc(32UL, 208U); pt = (struct psb_mmu_pt *)tmp; clflush_add = (uint32_t )((pd->driver)->clflush_add >> 12); clflush_count = 4096U / clflush_add; lock = & (pd->driver)->lock; if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { return ((struct psb_mmu_pt *)0); } else { } pt->p = alloc_pages(4U, 0U); if ((unsigned long )pt->p == (unsigned long )((struct page *)0)) { kfree((void const *)pt); return ((struct psb_mmu_pt *)0); } else { } spin_lock(lock); v = kmap_atomic(pt->p); clf = (uint8_t *)v; ptes = (uint32_t *)v; i = 0; goto ldv_41602; ldv_41601: tmp___0 = ptes; ptes = ptes + 1; *tmp___0 = pd->invalid_pte; i = i + 1; ldv_41602: ; if ((unsigned int )i <= 1023U) { goto ldv_41601; } else { } if ((pd->driver)->has_clflush != 0 && pd->hw_context != -1) { __asm__ volatile ("mfence": : : "memory"); i = 0; goto ldv_41605; ldv_41604: psb_clflush((void *)clf); clf = clf + (unsigned long )clflush_add; i = i + 1; ldv_41605: ; if ((uint32_t )i < clflush_count) { goto ldv_41604; } else { } __asm__ volatile ("mfence": : : "memory"); } else { } __kunmap_atomic(v); spin_unlock(lock); pt->count = 0U; pt->pd = pd; pt->index = 0U; return (pt); } } struct psb_mmu_pt *psb_mmu_pt_alloc_map_lock(struct psb_mmu_pd *pd , unsigned long addr ) { uint32_t index ; uint32_t tmp ; struct psb_mmu_pt *pt ; uint32_t *v ; spinlock_t *lock ; void *tmp___0 ; void *tmp___1 ; { tmp = psb_mmu_pd_index((uint32_t )addr); index = tmp; lock = & (pd->driver)->lock; spin_lock(lock); pt = *(pd->tables + (unsigned long )index); goto ldv_41615; ldv_41616: spin_unlock(lock); pt = psb_mmu_alloc_pt(pd); if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { return ((struct psb_mmu_pt *)0); } else { } spin_lock(lock); if ((unsigned long )*(pd->tables + (unsigned long )index) != (unsigned long )((struct psb_mmu_pt *)0)) { spin_unlock(lock); psb_mmu_free_pt(pt); spin_lock(lock); pt = *(pd->tables + (unsigned long )index); goto ldv_41615; } else { } tmp___0 = kmap_atomic(pd->p); v = (uint32_t *)tmp___0; *(pd->tables + (unsigned long )index) = pt; *(v + (unsigned long )index) = ((uint32_t )(((long )pt->p + 24189255811072L) / 64L) << 12U) | pd->pd_mask; pt->index = index; __kunmap_atomic((void *)v); if (pd->hw_context != -1) { psb_mmu_clflush(pd->driver, (void *)v + (unsigned long )index); atomic_set(& (pd->driver)->needs_tlbflush, 1); } else { } ldv_41615: ; if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { goto ldv_41616; } else { } tmp___1 = kmap_atomic(pt->p); pt->v = (uint32_t *)tmp___1; return (pt); } } static struct psb_mmu_pt *psb_mmu_pt_map_lock(struct psb_mmu_pd *pd , unsigned long addr ) { uint32_t index ; uint32_t tmp ; struct psb_mmu_pt *pt ; spinlock_t *lock ; void *tmp___0 ; { tmp = psb_mmu_pd_index((uint32_t )addr); index = tmp; lock = & (pd->driver)->lock; spin_lock(lock); pt = *(pd->tables + (unsigned long )index); if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { spin_unlock(lock); return ((struct psb_mmu_pt *)0); } else { } tmp___0 = kmap_atomic(pt->p); pt->v = (uint32_t *)tmp___0; return (pt); } } static void psb_mmu_pt_unmap_unlock(struct psb_mmu_pt *pt ) { struct psb_mmu_pd *pd ; uint32_t *v ; void *tmp ; { pd = pt->pd; __kunmap_atomic((void *)pt->v); if (pt->count == 0U) { tmp = kmap_atomic(pd->p); v = (uint32_t *)tmp; *(v + (unsigned long )pt->index) = pd->invalid_pde; *(pd->tables + (unsigned long )pt->index) = (struct psb_mmu_pt *)0; if (pd->hw_context != -1) { psb_mmu_clflush(pd->driver, (void *)v + (unsigned long )pt->index); atomic_set(& (pd->driver)->needs_tlbflush, 1); } else { } __kunmap_atomic((void *)pt->v); spin_unlock(& (pd->driver)->lock); psb_mmu_free_pt(pt); return; } else { } spin_unlock(& (pd->driver)->lock); return; } } __inline static void psb_mmu_set_pte(struct psb_mmu_pt *pt , unsigned long addr , uint32_t pte ) { uint32_t tmp ; { tmp = psb_mmu_pt_index((uint32_t )addr); *(pt->v + (unsigned long )tmp) = pte; return; } } __inline static void psb_mmu_invalidate_pte(struct psb_mmu_pt *pt , unsigned long addr ) { uint32_t tmp ; { tmp = psb_mmu_pt_index((uint32_t )addr); *(pt->v + (unsigned long )tmp) = (pt->pd)->invalid_pte; return; } } struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver *driver___0 ) { struct psb_mmu_pd *pd ; { down_read(& driver___0->sem); pd = driver___0->default_pd; up_read(& driver___0->sem); return (pd); } } uint32_t psb_get_default_pd_addr(struct psb_mmu_driver *driver___0 ) { struct psb_mmu_pd *pd ; { pd = psb_mmu_get_default_pd(driver___0); return ((uint32_t )(((long )pd->p + 24189255811072L) / 64L) << 12U); } } void psb_mmu_driver_takedown(struct psb_mmu_driver *driver___0 ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; { dev = driver___0->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; iowrite32(driver___0->bif_ctrl, (void *)dev_priv->sgx_reg + 3072U); psb_mmu_free_pagedir(driver___0->default_pd); kfree((void const *)driver___0); return; } } struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev , int trap_pagefaults , int invalid_type , atomic_t *msvdx_mmu_invaldc ) { struct psb_mmu_driver *driver___0 ; struct drm_psb_private *dev_priv ; void *tmp ; struct lock_class_key __key ; struct lock_class_key __key___0 ; uint32_t tfms ; uint32_t misc ; uint32_t cap0 ; uint32_t cap4 ; uint32_t clflush_size ; int tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = kmalloc(288UL, 208U); driver___0 = (struct psb_mmu_driver *)tmp; if ((unsigned long )driver___0 == (unsigned long )((struct psb_mmu_driver *)0)) { return ((struct psb_mmu_driver *)0); } else { } driver___0->dev = dev; driver___0->default_pd = psb_mmu_alloc_pd(driver___0, trap_pagefaults, invalid_type); if ((unsigned long )driver___0->default_pd == (unsigned long )((struct psb_mmu_pd *)0)) { goto out_err1; } else { } spinlock_check(& driver___0->lock); __raw_spin_lock_init(& driver___0->lock.__annonCompField18.rlock, "&(&driver->lock)->rlock", & __key); __init_rwsem(& driver___0->sem, "&driver->sem", & __key___0); down_write(& driver___0->sem); atomic_set(& driver___0->needs_tlbflush, 1); driver___0->msvdx_mmu_invaldc = msvdx_mmu_invaldc; driver___0->bif_ctrl = ioread32((void *)dev_priv->sgx_reg + 3072U); iowrite32(driver___0->bif_ctrl | 16U, (void *)dev_priv->sgx_reg + 3072U); iowrite32(driver___0->bif_ctrl & 4294967279U, (void *)dev_priv->sgx_reg + 3072U); driver___0->has_clflush = 0; tmp___0 = constant_test_bit(19L, (unsigned long const volatile *)(& boot_cpu_data.x86_capability)); if (tmp___0 != 0) { cpuid(1U, & tfms, & misc, & cap0, & cap4); clflush_size = ((misc >> 8) & 255U) * 8U; driver___0->has_clflush = 1; driver___0->clflush_add = (int )(((unsigned long )clflush_size * 4096UL) / 4UL); driver___0->clflush_mask = (unsigned long )(driver___0->clflush_add + -1); driver___0->clflush_mask = ~ driver___0->clflush_mask; } else { } up_write(& driver___0->sem); return (driver___0); out_err1: kfree((void const *)driver___0); return ((struct psb_mmu_driver *)0); } } static void psb_mmu_flush_ptes(struct psb_mmu_pd *pd , unsigned long address , uint32_t num_pages , uint32_t desired_tile_stride , uint32_t hw_tile_stride ) { struct psb_mmu_pt *pt ; uint32_t rows ; uint32_t i ; unsigned long addr ; unsigned long end ; unsigned long next ; unsigned long add ; unsigned long row_add ; unsigned long clflush_add ; unsigned long clflush_mask ; uint32_t tmp ; { rows = 1U; clflush_add = (unsigned long )(pd->driver)->clflush_add; clflush_mask = (pd->driver)->clflush_mask; if ((pd->driver)->has_clflush == 0) { return; } else { } if (hw_tile_stride != 0U) { rows = num_pages / desired_tile_stride; } else { desired_tile_stride = num_pages; } add = (unsigned long )(desired_tile_stride << 12); row_add = (unsigned long )(hw_tile_stride << 12); __asm__ volatile ("mfence": : : "memory"); i = 0U; goto ldv_41691; ldv_41690: addr = address; end = addr + add; ldv_41688: next = psb_pd_addr_end(addr, end); pt = psb_mmu_pt_map_lock(pd, addr); if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { goto ldv_41685; } else { } ldv_41686: tmp = psb_mmu_pt_index((uint32_t )addr); psb_clflush((void *)pt->v + (unsigned long )tmp); addr = addr + clflush_add; if ((addr & clflush_mask) < next) { goto ldv_41686; } else { } psb_mmu_pt_unmap_unlock(pt); ldv_41685: addr = next; if (next != end) { goto ldv_41688; } else { } address = address + row_add; i = i + 1U; ldv_41691: ; if (i < rows) { goto ldv_41690; } else { } __asm__ volatile ("mfence": : : "memory"); return; } } void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd , unsigned long address , uint32_t num_pages ) { struct psb_mmu_pt *pt ; unsigned long addr ; unsigned long end ; unsigned long next ; unsigned long f_address ; { f_address = address; down_read(& (pd->driver)->sem); addr = address; end = (unsigned long )(num_pages << 12) + addr; ldv_41706: next = psb_pd_addr_end(addr, end); pt = psb_mmu_pt_alloc_map_lock(pd, addr); if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { goto out; } else { } ldv_41704: psb_mmu_invalidate_pte(pt, addr); pt->count = pt->count - 1U; addr = addr + 4096UL; if (addr < next) { goto ldv_41704; } else { } psb_mmu_pt_unmap_unlock(pt); addr = next; if (next != end) { goto ldv_41706; } else { } out: ; if (pd->hw_context != -1) { psb_mmu_flush_ptes(pd, f_address, num_pages, 1U, 1U); } else { } up_read(& (pd->driver)->sem); if (pd->hw_context != -1) { psb_mmu_flush(pd->driver); } else { } return; } } void psb_mmu_remove_pages(struct psb_mmu_pd *pd , unsigned long address , uint32_t num_pages , uint32_t desired_tile_stride , uint32_t hw_tile_stride ) { struct psb_mmu_pt *pt ; uint32_t rows ; uint32_t i ; unsigned long addr ; unsigned long end ; unsigned long next ; unsigned long add ; unsigned long row_add ; unsigned long f_address ; { rows = 1U; f_address = address; if (hw_tile_stride != 0U) { rows = num_pages / desired_tile_stride; } else { desired_tile_stride = num_pages; } add = (unsigned long )(desired_tile_stride << 12); row_add = (unsigned long )(hw_tile_stride << 12); down_read(& (pd->driver)->sem); i = 0U; goto ldv_41730; ldv_41729: addr = address; end = addr + add; ldv_41727: next = psb_pd_addr_end(addr, end); pt = psb_mmu_pt_map_lock(pd, addr); if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { goto ldv_41724; } else { } ldv_41725: psb_mmu_invalidate_pte(pt, addr); pt->count = pt->count - 1U; addr = addr + 4096UL; if (addr < next) { goto ldv_41725; } else { } psb_mmu_pt_unmap_unlock(pt); ldv_41724: addr = next; if (next != end) { goto ldv_41727; } else { } address = address + row_add; i = i + 1U; ldv_41730: ; if (i < rows) { goto ldv_41729; } else { } if (pd->hw_context != -1) { psb_mmu_flush_ptes(pd, f_address, num_pages, desired_tile_stride, hw_tile_stride); } else { } up_read(& (pd->driver)->sem); if (pd->hw_context != -1) { psb_mmu_flush(pd->driver); } else { } return; } } int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd , uint32_t start_pfn , unsigned long address , uint32_t num_pages , int type ) { struct psb_mmu_pt *pt ; uint32_t pte ; unsigned long addr ; unsigned long end ; unsigned long next ; unsigned long f_address ; int ret ; uint32_t tmp ; { f_address = address; ret = -12; down_read(& (pd->driver)->sem); addr = address; end = (unsigned long )(num_pages << 12) + addr; ldv_41749: next = psb_pd_addr_end(addr, end); pt = psb_mmu_pt_alloc_map_lock(pd, addr); if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { ret = -12; goto out; } else { } ldv_41747: tmp = start_pfn; start_pfn = start_pfn + 1U; pte = psb_mmu_mask_pte(tmp, type); psb_mmu_set_pte(pt, addr, pte); pt->count = pt->count + 1U; addr = addr + 4096UL; if (addr < next) { goto ldv_41747; } else { } psb_mmu_pt_unmap_unlock(pt); addr = next; if (next != end) { goto ldv_41749; } else { } ret = 0; out: ; if (pd->hw_context != -1) { psb_mmu_flush_ptes(pd, f_address, num_pages, 1U, 1U); } else { } up_read(& (pd->driver)->sem); if (pd->hw_context != -1) { psb_mmu_flush(pd->driver); } else { } return (0); } } int psb_mmu_insert_pages(struct psb_mmu_pd *pd , struct page **pages , unsigned long address , uint32_t num_pages , uint32_t desired_tile_stride , uint32_t hw_tile_stride , int type ) { struct psb_mmu_pt *pt ; uint32_t rows ; uint32_t i ; uint32_t pte ; unsigned long addr ; unsigned long end ; unsigned long next ; unsigned long add ; unsigned long row_add ; unsigned long f_address ; int ret ; struct page **tmp ; { rows = 1U; f_address = address; ret = -12; if (hw_tile_stride != 0U) { if (num_pages % desired_tile_stride != 0U) { return (-22); } else { } rows = num_pages / desired_tile_stride; } else { desired_tile_stride = num_pages; } add = (unsigned long )(desired_tile_stride << 12); row_add = (unsigned long )(hw_tile_stride << 12); down_read(& (pd->driver)->sem); i = 0U; goto ldv_41777; ldv_41776: addr = address; end = addr + add; ldv_41774: next = psb_pd_addr_end(addr, end); pt = psb_mmu_pt_alloc_map_lock(pd, addr); if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { goto out; } else { } ldv_41772: tmp = pages; pages = pages + 1; pte = psb_mmu_mask_pte((uint32_t )(((long )*tmp + 24189255811072L) / 64L), type); psb_mmu_set_pte(pt, addr, pte); pt->count = pt->count + 1U; addr = addr + 4096UL; if (addr < next) { goto ldv_41772; } else { } psb_mmu_pt_unmap_unlock(pt); addr = next; if (next != end) { goto ldv_41774; } else { } address = address + row_add; i = i + 1U; ldv_41777: ; if (i < rows) { goto ldv_41776; } else { } ret = 0; out: ; if (pd->hw_context != -1) { psb_mmu_flush_ptes(pd, f_address, num_pages, desired_tile_stride, hw_tile_stride); } else { } up_read(& (pd->driver)->sem); if (pd->hw_context != -1) { psb_mmu_flush(pd->driver); } else { } return (ret); } } int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd , uint32_t virtual , unsigned long *pfn ) { int ret ; struct psb_mmu_pt *pt ; uint32_t tmp ; spinlock_t *lock ; uint32_t *v ; void *tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; { lock = & (pd->driver)->lock; down_read(& (pd->driver)->sem); pt = psb_mmu_pt_map_lock(pd, (unsigned long )virtual); if ((unsigned long )pt == (unsigned long )((struct psb_mmu_pt *)0)) { spin_lock(lock); tmp___0 = kmap_atomic(pd->p); v = (uint32_t *)tmp___0; tmp___1 = psb_mmu_pd_index(virtual); tmp = *(v + (unsigned long )tmp___1); __kunmap_atomic((void *)v); spin_unlock(lock); if ((pd->invalid_pde != tmp || (tmp & 1U) == 0U) || (pd->invalid_pte & 1U) == 0U) { ret = -22; goto out; } else { } ret = 0; *pfn = (unsigned long )(pd->invalid_pte >> 12); goto out; } else { } tmp___2 = psb_mmu_pt_index(virtual); tmp = *(pt->v + (unsigned long )tmp___2); if ((tmp & 1U) == 0U) { ret = -22; } else { ret = 0; *pfn = (unsigned long )(tmp >> 12); } psb_mmu_pt_unmap_unlock(pt); out: up_read(& (pd->driver)->sem); return (ret); } } bool ldv_queue_work_on_117(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_118(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_119(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_120(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_121(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_131(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_133(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_132(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_135(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_134(struct workqueue_struct *ldv_func_arg1 ) ; int gma_blt_wait_idle(struct drm_psb_private *dev_priv ) { unsigned long stop ; int busy ; unsigned int tmp ; unsigned int tmp___0 ; unsigned int tmp___1 ; unsigned int tmp___2 ; { stop = (unsigned long )jiffies + 250UL; busy = 1; if (((int )((dev_priv->dev)->pdev)->device & 65520) == 3040) { return (0); } else { } tmp = ioread32((void *)dev_priv->sgx_reg + 3608U); if (tmp == 128U) { tmp___0 = ioread32((void *)dev_priv->sgx_reg + 3588U); if ((tmp___0 & 16777216U) == 0U) { return (0); } else { } } else { } ldv_41529: tmp___1 = ioread32((void *)dev_priv->sgx_reg + 3608U); busy = tmp___1 != 128U; if (busy != 0 && (long )((unsigned long )jiffies - stop) < 0L) { goto ldv_41529; } else { } if (busy != 0) { return (-16); } else { } ldv_41537: tmp___2 = ioread32((void *)dev_priv->sgx_reg + 3588U); busy = (tmp___2 & 16777216U) != 0U; if (busy != 0 && (long )((unsigned long )jiffies - stop) < 0L) { goto ldv_41537; } else { } return (busy != 0 ? -16 : 0); } } bool ldv_queue_work_on_131(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_132(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_133(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_134(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_135(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_145(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_147(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_146(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_149(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_148(struct workqueue_struct *ldv_func_arg1 ) ; __inline static void *dev_get_drvdata(struct device const *dev ) { { return ((void *)dev->driver_data); } } extern int pci_bus_write_config_dword(struct pci_bus * , unsigned int , int , u32 ) ; __inline static int pci_write_config_dword(struct pci_dev const *dev , int where , u32 val ) { int tmp ; { tmp = pci_bus_write_config_dword(dev->bus, dev->devfn, where, val); return (tmp); } } extern int pci_enable_device(struct pci_dev * ) ; extern void pci_disable_device(struct pci_dev * ) ; extern int pci_save_state(struct pci_dev * ) ; extern void pci_restore_state(struct pci_dev * ) ; extern int pci_set_power_state(struct pci_dev * , pci_power_t ) ; __inline static void *pci_get_drvdata(struct pci_dev *pdev ) { void *tmp ; { tmp = dev_get_drvdata((struct device const *)(& pdev->dev)); return (tmp); } } void gma_power_init(struct drm_device *dev ) ; void gma_power_uninit(struct drm_device *dev ) ; int gma_power_suspend(struct device *_dev ) ; int gma_power_resume(struct device *_dev ) ; int gma_power_thaw(struct device *_dev ) ; int gma_power_freeze(struct device *_dev ) ; int gma_power_restore(struct device *_dev ) ; bool gma_power_is_on(struct drm_device *dev ) ; int psb_runtime_suspend(struct device *dev ) ; int psb_runtime_resume(struct device *dev ) ; int psb_runtime_idle(struct device *dev ) ; extern int __pm_runtime_idle(struct device * , int ) ; extern int __pm_runtime_resume(struct device * , int ) ; extern int __pm_runtime_set_status(struct device * , unsigned int ) ; extern void __pm_runtime_disable(struct device * , bool ) ; __inline static int pm_runtime_get(struct device *dev ) { int tmp ; { tmp = __pm_runtime_resume(dev, 5); return (tmp); } } __inline static int pm_runtime_put(struct device *dev ) { int tmp ; { tmp = __pm_runtime_idle(dev, 5); return (tmp); } } __inline static void pm_runtime_set_suspended(struct device *dev ) { { __pm_runtime_set_status(dev, 2U); return; } } __inline static void pm_runtime_disable(struct device *dev ) { { __pm_runtime_disable(dev, 1); return; } } void psb_irq_preinstall(struct drm_device *dev ) ; int psb_irq_postinstall(struct drm_device *dev ) ; void psb_irq_uninstall(struct drm_device *dev ) ; static struct mutex power_mutex ; static spinlock_t power_ctrl_lock ; void gma_power_init(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct lock_class_key __key ; struct lock_class_key __key___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; dev_priv->apm_base = (uint16_t )dev_priv->apm_reg; dev_priv->ospm_base = dev_priv->ospm_base & 65535U; dev_priv->display_power = 1; dev_priv->display_count = 0; dev_priv->suspended = 0; spinlock_check(& power_ctrl_lock); __raw_spin_lock_init(& power_ctrl_lock.__annonCompField18.rlock, "&(&power_ctrl_lock)->rlock", & __key); __mutex_init(& power_mutex, "&power_mutex", & __key___0); if ((unsigned long )(dev_priv->ops)->init_pm != (unsigned long )((void (*/* const */)(struct drm_device * ))0)) { (*((dev_priv->ops)->init_pm))(dev); } else { } return; } } void gma_power_uninit(struct drm_device *dev ) { { pm_runtime_disable(& (dev->pdev)->dev); pm_runtime_set_suspended(& (dev->pdev)->dev); return; } } static void gma_suspend_display(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if ((int )dev_priv->suspended) { return; } else { } (*((dev_priv->ops)->save_regs))(dev); (*((dev_priv->ops)->power_down))(dev); dev_priv->display_power = 0; return; } } static void gma_resume_display(struct pci_dev *pdev ) { struct drm_device *dev ; void *tmp ; struct drm_psb_private *dev_priv ; { tmp = pci_get_drvdata(pdev); dev = (struct drm_device *)tmp; dev_priv = (struct drm_psb_private *)dev->dev_private; (*((dev_priv->ops)->power_up))(dev); dev_priv->suspended = 0; dev_priv->display_power = 1; iowrite32(dev_priv->pge_ctl | 1U, (void *)dev_priv->vdc_reg + 8224U); pci_write_config_word((struct pci_dev const *)pdev, 82, (int )((unsigned int )dev_priv->gmch_ctrl | 4U)); psb_gtt_restore(dev); (*((dev_priv->ops)->restore_regs))(dev); return; } } static void gma_suspend_pci(struct pci_dev *pdev ) { struct drm_device *dev ; void *tmp ; struct drm_psb_private *dev_priv ; int bsm ; int vbt ; { tmp = pci_get_drvdata(pdev); dev = (struct drm_device *)tmp; dev_priv = (struct drm_psb_private *)dev->dev_private; if ((int )dev_priv->suspended) { return; } else { } pci_save_state(pdev); pci_read_config_dword((struct pci_dev const *)pdev, 92, (u32 *)(& bsm)); dev_priv->regs.saveBSM = (uint32_t )bsm; pci_read_config_dword((struct pci_dev const *)pdev, 252, (u32 *)(& vbt)); dev_priv->regs.saveVBT = (uint32_t )vbt; pci_read_config_dword((struct pci_dev const *)pdev, 148, & dev_priv->msi_addr); pci_read_config_dword((struct pci_dev const *)pdev, 152, & dev_priv->msi_data); pci_disable_device(pdev); pci_set_power_state(pdev, 3); dev_priv->suspended = 1; return; } } static bool gma_resume_pci(struct pci_dev *pdev ) { struct drm_device *dev ; void *tmp ; struct drm_psb_private *dev_priv ; int ret ; { tmp = pci_get_drvdata(pdev); dev = (struct drm_device *)tmp; dev_priv = (struct drm_psb_private *)dev->dev_private; if (! dev_priv->suspended) { return (1); } else { } pci_set_power_state(pdev, 0); pci_restore_state(pdev); pci_write_config_dword((struct pci_dev const *)pdev, 92, dev_priv->regs.saveBSM); pci_write_config_dword((struct pci_dev const *)pdev, 252, dev_priv->regs.saveVBT); pci_write_config_dword((struct pci_dev const *)pdev, 148, dev_priv->msi_addr); pci_write_config_dword((struct pci_dev const *)pdev, 152, dev_priv->msi_data); ret = pci_enable_device(pdev); if (ret != 0) { dev_err((struct device const *)(& pdev->dev), "pci_enable failed: %d\n", ret); } else { dev_priv->suspended = 0; } return ((bool )(! ((int )dev_priv->suspended != 0))); } } int gma_power_suspend(struct device *_dev ) { struct pci_dev *pdev ; struct device const *__mptr ; struct drm_device *dev ; void *tmp ; struct drm_psb_private *dev_priv ; { __mptr = (struct device const *)_dev; pdev = (struct pci_dev *)__mptr + 0xffffffffffffff68UL; tmp = pci_get_drvdata(pdev); dev = (struct drm_device *)tmp; dev_priv = (struct drm_psb_private *)dev->dev_private; mutex_lock_nested(& power_mutex, 0U); if (! dev_priv->suspended) { if (dev_priv->display_count != 0) { mutex_unlock(& power_mutex); dev_err((struct device const *)dev->dev, "GPU hardware busy, cannot suspend\n"); return (-16); } else { } psb_irq_uninstall(dev); gma_suspend_display(dev); gma_suspend_pci(pdev); } else { } mutex_unlock(& power_mutex); return (0); } } int gma_power_resume(struct device *_dev ) { struct pci_dev *pdev ; struct device const *__mptr ; struct drm_device *dev ; void *tmp ; { __mptr = (struct device const *)_dev; pdev = (struct pci_dev *)__mptr + 0xffffffffffffff68UL; tmp = pci_get_drvdata(pdev); dev = (struct drm_device *)tmp; mutex_lock_nested(& power_mutex, 0U); gma_resume_pci(pdev); gma_resume_display(pdev); psb_irq_preinstall(dev); psb_irq_postinstall(dev); mutex_unlock(& power_mutex); return (0); } } bool gma_power_is_on(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; return (dev_priv->display_power); } } bool gma_power_begin(struct drm_device *dev , bool force_on ) { struct drm_psb_private *dev_priv ; int ret ; unsigned long flags ; raw_spinlock_t *tmp ; bool tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = spinlock_check(& power_ctrl_lock); flags = _raw_spin_lock_irqsave(tmp); if ((int )dev_priv->display_power) { dev_priv->display_count = dev_priv->display_count + 1; pm_runtime_get(& (dev->pdev)->dev); spin_unlock_irqrestore(& power_ctrl_lock, flags); return (1); } else { } if (! force_on) { goto out_false; } else { } tmp___0 = gma_resume_pci(dev->pdev); ret = (int )tmp___0; if (ret == 0) { psb_irq_preinstall(dev); psb_irq_postinstall(dev); pm_runtime_get(& (dev->pdev)->dev); dev_priv->display_count = dev_priv->display_count + 1; spin_unlock_irqrestore(& power_ctrl_lock, flags); return (1); } else { } out_false: spin_unlock_irqrestore(& power_ctrl_lock, flags); return (0); } } void gma_power_end(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; unsigned long flags ; raw_spinlock_t *tmp ; int __ret_warn_on ; long tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = spinlock_check(& power_ctrl_lock); flags = _raw_spin_lock_irqsave(tmp); dev_priv->display_count = dev_priv->display_count - 1; __ret_warn_on = dev_priv->display_count < 0; tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/power.c", 294); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); spin_unlock_irqrestore(& power_ctrl_lock, flags); pm_runtime_put(& (dev->pdev)->dev); return; } } int psb_runtime_suspend(struct device *dev ) { int tmp ; { tmp = gma_power_suspend(dev); return (tmp); } } int psb_runtime_resume(struct device *dev ) { int tmp ; { tmp = gma_power_resume(dev); return (tmp); } } int psb_runtime_idle(struct device *dev ) { struct drm_device *drmdev ; struct device const *__mptr ; void *tmp ; struct drm_psb_private *dev_priv ; { __mptr = (struct device const *)dev; tmp = pci_get_drvdata((struct pci_dev *)__mptr + 0xffffffffffffff68UL); drmdev = (struct drm_device *)tmp; dev_priv = (struct drm_psb_private *)drmdev->dev_private; if (dev_priv->display_count != 0) { return (0); } else { return (1); } } } int gma_power_thaw(struct device *_dev ) { int tmp ; { tmp = gma_power_resume(_dev); return (tmp); } } int gma_power_freeze(struct device *_dev ) { int tmp ; { tmp = gma_power_suspend(_dev); return (tmp); } } int gma_power_restore(struct device *_dev ) { int tmp ; { tmp = gma_power_resume(_dev); return (tmp); } } bool ldv_queue_work_on_145(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_146(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_147(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_148(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_149(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_159(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_161(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_160(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_163(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_162(struct workqueue_struct *ldv_func_arg1 ) ; __inline static void *ioremap(resource_size_t offset , unsigned long size ) { void *tmp ; { tmp = ioremap_nocache(offset, size); return (tmp); } } int ldv_state_variable_47 ; struct fb_var_screeninfo *psbfb_roll_ops_group0 ; int ldv_state_variable_20 ; struct timer_list *ldv_timer_list_4 ; struct drm_connector *cdv_hdmi_connector_funcs_group0 ; int pci_counter ; struct work_struct *ldv_work_struct_3_1 ; struct fb_info *psbfb_ops_group0 ; struct drm_encoder *cdv_hdmi_helper_funcs_group0 ; struct gma_clock_t *mrst_clock_funcs_group1 ; struct drm_device *cdv_chip_ops_group0 ; int ldv_state_variable_30 ; int ldv_state_variable_0 ; int ldv_state_variable_45 ; int ldv_state_variable_12 ; struct drm_connector *oaktrail_hdmi_connector_funcs_group0 ; int ldv_state_variable_22 ; int ldv_state_variable_54 ; int ldv_state_variable_14 ; struct drm_crtc *psb_fb_helper_funcs_group0 ; struct drm_file *driver_group0 ; int ldv_state_variable_37 ; int ldv_state_variable_29 ; int ldv_state_variable_17 ; int ldv_state_variable_51 ; struct drm_framebuffer *cdv_intel_helper_funcs_group1 ; struct drm_device *psb_mode_funcs_group0 ; struct work_struct *ldv_work_struct_2_0 ; int ldv_state_variable_19 ; struct drm_encoder *cdv_intel_lvds_helper_funcs_group0 ; int ldv_state_variable_27 ; int ldv_state_variable_9 ; struct work_struct *ldv_work_struct_2_2 ; struct drm_connector *cdv_intel_dp_connector_funcs_group0 ; struct drm_connector *cdv_hdmi_connector_helper_funcs_group0 ; int ref_cnt ; int ldv_state_variable_42 ; struct drm_encoder *psb_intel_lvds_helper_funcs_group0 ; int ldv_irq_line_1_1 ; int ldv_work_3_3 ; struct drm_connector *cdv_intel_dp_connector_helper_funcs_group0 ; int ldv_state_variable_7 ; struct drm_encoder *psb_intel_sdvo_helper_funcs_group0 ; struct drm_connector *cdv_intel_crt_connector_helper_funcs_group0 ; struct drm_encoder *cdv_intel_crt_helper_funcs_group0 ; int ldv_state_variable_23 ; struct work_struct *ldv_work_struct_3_3 ; struct drm_crtc *psb_intel_helper_funcs_group0 ; int ldv_state_variable_55 ; struct file *psb_gem_fops_group2 ; struct drm_connector *psb_intel_lvds_connector_funcs_group0 ; int ldv_state_variable_59 ; struct work_struct *ldv_work_struct_2_1 ; struct work_struct *ldv_work_struct_3_2 ; void *ldv_irq_data_1_0 ; int ldv_state_variable_6 ; struct drm_display_mode *cdv_intel_dp_helper_funcs_group1 ; void *ldv_irq_data_1_3 ; int ldv_state_variable_50 ; struct drm_crtc *mrst_clock_funcs_group0 ; int ldv_state_variable_26 ; int ldv_state_variable_28 ; struct drm_display_mode *oaktrail_lvds_helper_funcs_group1 ; struct device *psb_pm_ops_group1 ; int ldv_state_variable_44 ; int ldv_state_variable_38 ; struct inode *psb_gem_fops_group1 ; int ldv_state_variable_58 ; int ldv_state_variable_39 ; int ldv_state_variable_56 ; int ldv_state_variable_3 ; int ldv_irq_line_1_0 ; struct drm_crtc *cdv_clock_funcs_group0 ; int ldv_state_variable_31 ; int ldv_state_variable_52 ; struct drm_connector *cdv_intel_lvds_connector_helper_funcs_group0 ; struct drm_crtc *cdv_intel_crtc_funcs_group0 ; int ldv_state_variable_4 ; struct drm_framebuffer *psb_fb_funcs_group0 ; struct drm_display_mode *oaktrail_hdmi_helper_funcs_group1 ; int ldv_work_2_1 ; int ldv_state_variable_60 ; int ldv_state_variable_36 ; int ldv_state_variable_8 ; int ldv_state_variable_46 ; struct drm_display_mode *psb_intel_sdvo_helper_funcs_group1 ; int ldv_state_variable_15 ; struct fb_info *psbfb_roll_ops_group1 ; int ldv_state_variable_48 ; struct i2c_adapter *psb_intel_sdvo_ddc_proxy_group0 ; struct vm_area_struct *psbfb_vm_ops_group0 ; int ldv_state_variable_5 ; int ldv_state_variable_21 ; int ldv_state_variable_33 ; int ldv_state_variable_13 ; int ldv_work_3_2 ; struct pci_dev *psb_pci_driver_group1 ; struct drm_display_mode *psb_intel_lvds_helper_funcs_group1 ; int ldv_work_3_0 ; struct drm_encoder *cdv_intel_dp_helper_funcs_group0 ; struct work_struct *ldv_work_struct_2_3 ; int ldv_state_variable_49 ; struct gma_clock_t *psb_clock_funcs_group1 ; int ldv_state_variable_24 ; struct drm_connector *psb_intel_lvds_connector_helper_funcs_group0 ; struct drm_device *driver_group1 ; struct drm_display_mode *cdv_hdmi_helper_funcs_group1 ; struct drm_display_mode *cdv_intel_crt_helper_funcs_group1 ; int ldv_state_variable_1 ; int ldv_state_variable_41 ; int ldv_irq_line_1_2 ; int ldv_state_variable_40 ; struct drm_display_mode *psb_intel_helper_funcs_group2 ; struct drm_framebuffer *psb_intel_helper_funcs_group1 ; struct drm_connector *oaktrail_hdmi_connector_helper_funcs_group0 ; void *ldv_irq_data_1_1 ; struct drm_display_mode *oaktrail_helper_funcs_group2 ; int ldv_state_variable_10 ; struct drm_encoder *oaktrail_hdmi_helper_funcs_group0 ; struct fb_info *psbfb_unaccel_ops_group0 ; struct vm_area_struct *psb_gem_vm_ops_group0 ; struct drm_encoder *oaktrail_lvds_helper_funcs_group0 ; struct drm_connector *cdv_intel_lvds_connector_funcs_group0 ; struct drm_crtc *psb_clock_funcs_group0 ; struct i2c_adapter *i2c_dp_aux_algo_group0 ; int ldv_work_3_1 ; int ldv_state_variable_16 ; struct i2c_adapter *oaktrail_hdmi_i2c_algorithm_group0 ; struct gma_clock_t *cdv_clock_funcs_group1 ; int ldv_state_variable_2 ; int ldv_state_variable_43 ; struct drm_crtc *oaktrail_helper_funcs_group0 ; int ldv_state_variable_25 ; int ldv_work_2_0 ; struct drm_framebuffer *oaktrail_helper_funcs_group1 ; struct drm_device *oaktrail_chip_ops_group0 ; int ldv_state_variable_57 ; void *ldv_irq_data_1_2 ; struct i2c_adapter *gmbus_algorithm_group0 ; struct drm_crtc *psb_intel_crtc_funcs_group0 ; struct work_struct *ldv_work_struct_3_0 ; int ldv_state_variable_11 ; struct drm_crtc *cdv_intel_helper_funcs_group0 ; int ldv_state_variable_53 ; struct drm_connector *psb_intel_sdvo_connector_funcs_group0 ; int ldv_state_variable_18 ; int ldv_irq_line_1_3 ; int ldv_work_2_2 ; struct drm_display_mode *cdv_intel_lvds_helper_funcs_group1 ; int ldv_state_variable_32 ; int ldv_state_variable_34 ; struct drm_display_mode *cdv_intel_helper_funcs_group2 ; int ldv_work_2_3 ; struct drm_device *psb_chip_ops_group0 ; struct drm_connector *cdv_intel_crt_connector_funcs_group0 ; int ldv_state_variable_35 ; struct drm_connector *psb_intel_sdvo_connector_helper_funcs_group0 ; void ldv_initialize_drm_connector_helper_funcs_24(void) ; void work_init_3(void) ; void ldv_initialize_drm_encoder_helper_funcs_25(void) ; void ldv_initialize_drm_crtc_helper_funcs_12(void) ; void ldv_initialize_gma_clock_funcs_11(void) ; void ldv_initialize_drm_encoder_helper_funcs_32(void) ; void ldv_initialize_drm_connector_funcs_23(void) ; void ldv_initialize_drm_crtc_funcs_46(void) ; void ldv_initialize_i2c_algorithm_18(void) ; void ldv_initialize_psb_ops_33(void) ; void ldv_dev_pm_ops_52(void) ; void ldv_initialize_drm_connector_funcs_31(void) ; void ldv_initialize_drm_driver_49(void) ; void ldv_file_operations_50(void) ; void ldv_initialize_drm_encoder_helper_funcs_22(void) ; void ldv_initialize_drm_encoder_helper_funcs_44(void) ; void ldv_initialize_drm_encoder_helper_funcs_17(void) ; void ldv_initialize_gma_clock_funcs_45(void) ; void ldv_initialize_drm_connector_funcs_16(void) ; void ldv_initialize_drm_connector_helper_funcs_8(void) ; void ldv_initialize_i2c_algorithm_36(void) ; void ldv_initialize_drm_connector_funcs_39(void) ; void ldv_initialize_drm_connector_helper_funcs_43(void) ; void work_init_2(void) ; void ldv_initialize_vm_operations_struct_51(void) ; void ldv_initialize_psb_ops_35(void) ; void ldv_initialize_drm_crtc_funcs_27(void) ; void ldv_initialize_drm_crtc_helper_funcs_47(void) ; void ldv_initialize_drm_connector_funcs_42(void) ; void ldv_initialize_drm_encoder_helper_funcs_9(void) ; void ldv_initialize_gma_clock_funcs_26(void) ; void ldv_initialize_drm_encoder_helper_funcs_40(void) ; void ldv_initialize_i2c_algorithm_5(void) ; void ldv_initialize_drm_encoder_helper_funcs_10(void) ; void ldv_pci_driver_48(void) ; void ldv_initialize_drm_crtc_helper_funcs_28(void) ; void ldv_initialize_drm_connector_helper_funcs_30(void) ; void ldv_initialize_drm_connector_helper_funcs_15(void) ; void ldv_initialize_drm_connector_funcs_20(void) ; void ldv_initialize_drm_connector_helper_funcs_21(void) ; void ldv_initialize_drm_connector_funcs_7(void) ; void ldv_initialize_drm_connector_helper_funcs_38(void) ; void ldv_initialize_psb_ops_13(void) ; extern int set_pages_uc(struct page * , int ) ; extern int set_pages_wb(struct page * , int ) ; extern void pci_dev_put(struct pci_dev * ) ; extern struct pci_dev *pci_get_domain_bus_and_slot(int , unsigned int , unsigned int ) ; __inline static struct pci_dev *pci_get_bus_and_slot(unsigned int bus , unsigned int devfn ) { struct pci_dev *tmp ; { tmp = pci_get_domain_bus_and_slot(0, bus, devfn); return (tmp); } } extern void pci_set_master(struct pci_dev * ) ; extern long drm_ioctl(struct file * , unsigned int , unsigned long ) ; extern int drm_open(struct inode * , struct file * ) ; extern ssize_t drm_read(struct file * , char * , size_t , loff_t * ) ; extern int drm_release(struct inode * , struct file * ) ; extern unsigned int drm_poll(struct file * , struct poll_table_struct * ) ; extern int drm_irq_install(struct drm_device * , int ) ; extern int drm_vblank_init(struct drm_device * , int ) ; extern void drm_put_dev(struct drm_device * ) ; extern int drm_pci_init(struct drm_driver * , struct pci_driver * ) ; extern void drm_pci_exit(struct drm_driver * , struct pci_driver * ) ; extern int drm_get_pci_dev(struct pci_dev * , struct pci_device_id const * , struct drm_driver * ) ; extern int drm_pci_set_busid(struct drm_device * , struct drm_master * ) ; extern void drm_kms_helper_poll_init(struct drm_device * ) ; extern void pm_runtime_allow(struct device * ) ; extern void drm_gem_vm_open(struct vm_area_struct * ) ; extern void drm_gem_vm_close(struct vm_area_struct * ) ; extern int drm_gem_mmap(struct file * , struct vm_area_struct * ) ; extern int drm_gem_dumb_destroy(struct drm_file * , struct drm_device * , uint32_t ) ; void psb_intel_opregion_fini(struct drm_device *dev ) ; int psb_intel_opregion_setup(struct drm_device *dev ) ; void psb_intel_opregion_enable_asle(struct drm_device *dev ) ; irqreturn_t psb_irq_handler(int irq , void *arg ) ; int psb_enable_vblank(struct drm_device *dev , int pipe ) ; void psb_disable_vblank(struct drm_device *dev , int pipe ) ; u32 psb_get_vblank_counter(struct drm_device *dev , int pipe ) ; struct psb_ops const psb_chip_ops ; struct psb_ops const oaktrail_chip_ops ; struct psb_ops const cdv_chip_ops ; extern bool drm_fb_helper_restore_fbdev_mode_unlocked(struct drm_fb_helper * ) ; extern int acpi_video_register(void) ; static struct drm_driver driver ; static int psb_pci_probe(struct pci_dev *pdev , struct pci_device_id const *ent ) ; static struct pci_device_id const pciidlist[28U] = { {32902U, 33032U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& psb_chip_ops)}, {32902U, 33033U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& psb_chip_ops)}, {32902U, 16640U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 16641U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 16642U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 16643U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 16644U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 16645U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 16646U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 16647U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 16648U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& oaktrail_chip_ops)}, {32902U, 3040U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3041U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3042U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3043U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3044U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3045U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3046U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3047U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3048U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3049U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3050U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3051U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3052U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3053U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3054U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {32902U, 3055U, 4294967295U, 4294967295U, 0U, 0U, (unsigned long )(& cdv_chip_ops)}, {0U, 0U, 0U, 0U, 0U, 0U, 0UL}}; struct pci_device_id const __mod_pci__pciidlist_device_table[28U] ; static struct drm_ioctl_desc const psb_ioctls[0U] = { }; static void psb_driver_lastclose(struct drm_device *dev ) { int ret ; struct drm_psb_private *dev_priv ; struct psb_fbdev *fbdev ; bool tmp ; long tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; fbdev = (struct psb_fbdev *)dev_priv->fbdev; tmp = drm_fb_helper_restore_fbdev_mode_unlocked(& fbdev->psb_fb_helper); ret = (int )tmp; if (ret != 0) { tmp___0 = ldv__builtin_expect((long )((int )drm_debug) & 1L, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("psb_driver_lastclose", "failed to restore crtc mode\n"); } else { } } else { } return; } } static int psb_do_init(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_gtt *pg ; uint32_t stolen_gtt ; struct lock_class_key __key ; struct lock_class_key __key___0 ; unsigned int tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; pg = & dev_priv->gtt; if ((pg->mmu_gatt_start & 268435455U) != 0U) { dev_err((struct device const *)dev->dev, "Gatt must be 256M aligned. This is a bug.\n"); return (-22); } else { } stolen_gtt = (uint32_t )(pg->stolen_size >> 12) * 4U; stolen_gtt = (uint32_t )(((unsigned long )stolen_gtt + 4095UL) >> 12); stolen_gtt = stolen_gtt < pg->gtt_pages ? stolen_gtt : pg->gtt_pages; dev_priv->gatt_free_offset = pg->mmu_gatt_start + stolen_gtt * 4194304U; spinlock_check(& dev_priv->irqmask_lock); __raw_spin_lock_init(& dev_priv->irqmask_lock.__annonCompField18.rlock, "&(&dev_priv->irqmask_lock)->rlock", & __key); spinlock_check(& dev_priv->lock_2d); __raw_spin_lock_init(& dev_priv->lock_2d.__annonCompField18.rlock, "&(&dev_priv->lock_2d)->rlock", & __key___0); iowrite32(0U, (void *)dev_priv->sgx_reg + 3192U); iowrite32(0U, (void *)dev_priv->sgx_reg + 3196U); ioread32((void *)dev_priv->sgx_reg + 3196U); tmp = ioread32((void *)dev_priv->sgx_reg + 3072U); iowrite32(tmp & 4294836479U, (void *)dev_priv->sgx_reg + 3072U); ioread32((void *)dev_priv->sgx_reg + 3072U); psb_spank(dev_priv); iowrite32(pg->gatt_start, (void *)dev_priv->sgx_reg + 3208U); ioread32((void *)dev_priv->sgx_reg + 3208U); return (0); } } static int psb_driver_unload(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_gtt *pg ; struct psb_mmu_pd *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if ((unsigned long )dev_priv != (unsigned long )((struct drm_psb_private *)0)) { if ((unsigned long )dev_priv->backlight_device != (unsigned long )((struct backlight_device *)0)) { gma_backlight_exit(dev); } else { } psb_modeset_cleanup(dev); if ((unsigned long )(dev_priv->ops)->chip_teardown != (unsigned long )((void (*/* const */)(struct drm_device * ))0)) { (*((dev_priv->ops)->chip_teardown))(dev); } else { } psb_intel_opregion_fini(dev); if ((unsigned long )dev_priv->pf_pd != (unsigned long )((struct psb_mmu_pd *)0)) { psb_mmu_free_pagedir(dev_priv->pf_pd); dev_priv->pf_pd = (struct psb_mmu_pd *)0; } else { } if ((unsigned long )dev_priv->mmu != (unsigned long )((struct psb_mmu_driver *)0)) { pg = & dev_priv->gtt; down_read(& pg->sem); tmp = psb_mmu_get_default_pd(dev_priv->mmu); psb_mmu_remove_pfn_sequence(tmp, (unsigned long )pg->mmu_gatt_start, (uint32_t )(dev_priv->vram_stolen_size >> 12)); up_read(& pg->sem); psb_mmu_driver_takedown(dev_priv->mmu); dev_priv->mmu = (struct psb_mmu_driver *)0; } else { } psb_gtt_takedown(dev); if ((unsigned long )dev_priv->scratch_page != (unsigned long )((struct page *)0)) { set_pages_wb(dev_priv->scratch_page, 1); __free_pages(dev_priv->scratch_page, 0U); dev_priv->scratch_page = (struct page *)0; } else { } if ((unsigned long )dev_priv->vdc_reg != (unsigned long )((uint8_t *)0U)) { iounmap((void volatile *)dev_priv->vdc_reg); dev_priv->vdc_reg = (uint8_t *)0U; } else { } if ((unsigned long )dev_priv->sgx_reg != (unsigned long )((uint8_t *)0U)) { iounmap((void volatile *)dev_priv->sgx_reg); dev_priv->sgx_reg = (uint8_t *)0U; } else { } if ((unsigned long )dev_priv->aux_reg != (unsigned long )((uint8_t *)0U)) { iounmap((void volatile *)dev_priv->aux_reg); dev_priv->aux_reg = (uint8_t *)0U; } else { } if ((unsigned long )dev_priv->aux_pdev != (unsigned long )((struct pci_dev *)0)) { pci_dev_put(dev_priv->aux_pdev); } else { } if ((unsigned long )dev_priv->lpc_pdev != (unsigned long )((struct pci_dev *)0)) { pci_dev_put(dev_priv->lpc_pdev); } else { } psb_intel_destroy_bios(dev); kfree((void const *)dev_priv); dev->dev_private = (void *)0; } else { } gma_power_uninit(dev); return (0); } } static int psb_driver_load(struct drm_device *dev , unsigned long flags ) { struct drm_psb_private *dev_priv ; unsigned long resource_start ; unsigned long resource_len ; unsigned long irqflags ; int ret ; struct drm_connector *connector ; struct gma_encoder *gma_encoder ; struct psb_gtt *pg ; void *tmp ; void *tmp___0 ; void *tmp___1 ; void *tmp___2 ; long tmp___3 ; long tmp___4 ; long tmp___5 ; struct psb_mmu_pd *tmp___6 ; struct psb_mmu_pd *tmp___7 ; raw_spinlock_t *tmp___8 ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; { ret = -12; tmp = kzalloc(5176UL, 208U); dev_priv = (struct drm_psb_private *)tmp; if ((unsigned long )dev_priv == (unsigned long )((struct drm_psb_private *)0)) { return (-12); } else { } dev_priv->ops = (struct psb_ops const *)flags; dev_priv->dev = dev; dev->dev_private = (void *)dev_priv; pg = & dev_priv->gtt; pci_set_master(dev->pdev); dev_priv->num_pipe = (uint32_t )(dev_priv->ops)->pipes; resource_start = (unsigned long )(dev->pdev)->resource[0].start; tmp___0 = ioremap((resource_size_t )resource_start, 524288UL); dev_priv->vdc_reg = (uint8_t *)tmp___0; if ((unsigned long )dev_priv->vdc_reg == (unsigned long )((uint8_t *)0U)) { goto out_err; } else { } tmp___1 = ioremap((resource_size_t )((unsigned long )(dev_priv->ops)->sgx_offset + resource_start), 32768UL); dev_priv->sgx_reg = (uint8_t *)tmp___1; if ((unsigned long )dev_priv->sgx_reg == (unsigned long )((uint8_t *)0U)) { goto out_err; } else { } if (((int )(dev->pdev)->device & 65520) == 16640) { dev_priv->aux_pdev = pci_get_bus_and_slot(0U, 24U); if ((unsigned long )dev_priv->aux_pdev != (unsigned long )((struct pci_dev *)0)) { resource_start = (unsigned long )(dev_priv->aux_pdev)->resource[0].start; resource_len = (dev_priv->aux_pdev)->resource[0].start != 0ULL || (dev_priv->aux_pdev)->resource[0].end != (dev_priv->aux_pdev)->resource[0].start ? (unsigned long )(((dev_priv->aux_pdev)->resource[0].end - (dev_priv->aux_pdev)->resource[0].start) + 1ULL) : 0UL; tmp___2 = ioremap_nocache((resource_size_t )resource_start, resource_len); dev_priv->aux_reg = (uint8_t *)tmp___2; if ((unsigned long )dev_priv->aux_reg == (unsigned long )((uint8_t *)0U)) { goto out_err; } else { } tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("psb_driver_load", "Found aux vdc"); } else { } } else { dev_priv->aux_reg = dev_priv->vdc_reg; tmp___4 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("psb_driver_load", "Couldn\'t find aux pci device"); } else { } } dev_priv->gmbus_reg = dev_priv->aux_reg; dev_priv->lpc_pdev = pci_get_bus_and_slot(0U, 248U); if ((unsigned long )dev_priv->lpc_pdev != (unsigned long )((struct pci_dev *)0)) { pci_read_config_word((struct pci_dev const *)dev_priv->lpc_pdev, 68, & dev_priv->lpc_gpio_base); pci_write_config_dword((struct pci_dev const *)dev_priv->lpc_pdev, 68, (u32 )dev_priv->lpc_gpio_base | 2147483648U); pci_read_config_word((struct pci_dev const *)dev_priv->lpc_pdev, 68, & dev_priv->lpc_gpio_base); dev_priv->lpc_gpio_base = (unsigned int )dev_priv->lpc_gpio_base & 65472U; if ((unsigned int )dev_priv->lpc_gpio_base != 0U) { tmp___5 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___5 != 0L) { drm_ut_debug_printk("psb_driver_load", "Found LPC GPIO at 0x%04x\n", (int )dev_priv->lpc_gpio_base); } else { } } else { pci_dev_put(dev_priv->lpc_pdev); dev_priv->lpc_pdev = (struct pci_dev *)0; } } else { } } else { dev_priv->gmbus_reg = dev_priv->vdc_reg; } psb_intel_opregion_setup(dev); ret = (*((dev_priv->ops)->chip_setup))(dev); if (ret != 0) { goto out_err; } else { } gma_power_init(dev); ret = -12; dev_priv->scratch_page = alloc_pages(32772U, 0U); if ((unsigned long )dev_priv->scratch_page == (unsigned long )((struct page *)0)) { goto out_err; } else { } set_pages_uc(dev_priv->scratch_page, 1); ret = psb_gtt_init(dev, 0); if (ret != 0) { goto out_err; } else { } dev_priv->mmu = psb_mmu_driver_init(dev, 1, 0, (atomic_t *)0); if ((unsigned long )dev_priv->mmu == (unsigned long )((struct psb_mmu_driver *)0)) { goto out_err; } else { } dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0); if ((unsigned long )dev_priv->pf_pd == (unsigned long )((struct psb_mmu_pd *)0)) { goto out_err; } else { } ret = psb_do_init(dev); if (ret != 0) { return (ret); } else { } down_read(& pg->sem); tmp___6 = psb_mmu_get_default_pd(dev_priv->mmu); ret = psb_mmu_insert_pfn_sequence(tmp___6, dev_priv->stolen_base >> 12, (unsigned long )pg->gatt_start, (uint32_t )(pg->stolen_size >> 12), 0); up_read(& pg->sem); tmp___7 = psb_mmu_get_default_pd(dev_priv->mmu); psb_mmu_set_pd_context(tmp___7, 0); psb_mmu_set_pd_context(dev_priv->pf_pd, 1); iowrite32(536870912U, (void *)dev_priv->sgx_reg + 2744U); iowrite32(805306368U, (void *)dev_priv->sgx_reg + 3244U); acpi_video_register(); ret = drm_vblank_init(dev, (int )dev_priv->num_pipe); if (ret != 0) { goto out_err; } else { } dev_priv->vdc_irq_mask = 0U; dev_priv->pipestat[0] = 0U; dev_priv->pipestat[1] = 0U; dev_priv->pipestat[2] = 0U; tmp___8 = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp___8); iowrite32(4294967295U, (void *)dev_priv->vdc_reg + 8344U); iowrite32(0U, (void *)dev_priv->vdc_reg + 8352U); iowrite32(4294967295U, (void *)dev_priv->vdc_reg + 8360U); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); drm_irq_install(dev, (int )(dev->pdev)->irq); dev->vblank_disable_allowed = 1; dev->max_vblank_count = 16777215U; (dev->driver)->get_vblank_counter = & psb_get_vblank_counter; psb_modeset_init(dev); psb_fbdev_init(dev); drm_kms_helper_poll_init(dev); __mptr = (struct list_head const *)dev->mode_config.connector_list.next; connector = (struct drm_connector *)__mptr + 0xffffffffffffffe8UL; goto ldv_41892; ldv_41891: gma_encoder = gma_attached_encoder(connector); switch (gma_encoder->type) { case 4: ; case 7: ret = gma_backlight_init(dev); goto ldv_41890; } ldv_41890: __mptr___0 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; ldv_41892: ; if ((unsigned long )(& connector->head) != (unsigned long )(& dev->mode_config.connector_list)) { goto ldv_41891; } else { } if (ret != 0) { return (ret); } else { } psb_intel_opregion_enable_asle(dev); return (0); out_err: psb_driver_unload(dev); return (ret); } } static int psb_driver_device_is_agp(struct drm_device *dev ) { { return (0); } } static long psb_unlocked_ioctl(struct file *filp , unsigned int cmd , unsigned long arg ) { struct drm_file *file_priv ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; unsigned int runtime_allowed ; long tmp ; { file_priv = (struct drm_file *)filp->private_data; dev = (file_priv->minor)->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; if (runtime_allowed == 1U && (int )dev_priv->is_lvds_on) { runtime_allowed = runtime_allowed + 1U; pm_runtime_allow(& (dev->pdev)->dev); dev_priv->rpm_enabled = 1; } else { } tmp = drm_ioctl(filp, cmd, arg); return (tmp); } } static void psb_driver_preclose(struct drm_device *dev , struct drm_file *priv ) { { return; } } static int psb_pci_probe(struct pci_dev *pdev , struct pci_device_id const *ent ) { int tmp ; { tmp = drm_get_pci_dev(pdev, ent, & driver); return (tmp); } } static void psb_pci_remove(struct pci_dev *pdev ) { struct drm_device *dev ; void *tmp ; { tmp = pci_get_drvdata(pdev); dev = (struct drm_device *)tmp; drm_put_dev(dev); return; } } static struct dev_pm_ops const psb_pm_ops = {0, 0, & gma_power_suspend, & gma_power_resume, & gma_power_freeze, & gma_power_thaw, 0, & gma_power_restore, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, & psb_runtime_suspend, & psb_runtime_resume, & psb_runtime_idle}; static struct vm_operations_struct const psb_gem_vm_ops = {& drm_gem_vm_open, & drm_gem_vm_close, & psb_gem_fault, 0, 0, 0, 0, 0, 0, 0, 0}; static struct file_operations const psb_gem_fops = {& __this_module, 0, & drm_read, 0, 0, 0, 0, & drm_poll, & psb_unlocked_ioctl, 0, & drm_gem_mmap, 0, & drm_open, 0, & drm_release, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static struct drm_driver driver = {& psb_driver_load, 0, 0, & psb_driver_preclose, 0, & psb_driver_lastclose, & psb_driver_unload, 0, 0, 0, 0, 0, & drm_pci_set_busid, & psb_get_vblank_counter, & psb_enable_vblank, & psb_disable_vblank, & psb_driver_device_is_agp, 0, 0, & psb_irq_handler, & psb_irq_preinstall, & psb_irq_postinstall, & psb_irq_uninstall, 0, 0, 0, 0, 0, 0, & psb_gem_free_object, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, & psb_gem_dumb_create, & psb_gem_dumb_map_gtt, & drm_gem_dumb_destroy, & psb_gem_vm_ops, 1, 0, 0, (char *)"gma500", (char *)"DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650", (char *)"20140314", 12480U, 0, (struct drm_ioctl_desc const *)(& psb_ioctls), 0, & psb_gem_fops, {0, 0}}; static struct pci_driver psb_pci_driver = {{0, 0}, "gma500", (struct pci_device_id const *)(& pciidlist), & psb_pci_probe, & psb_pci_remove, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0, & psb_pm_ops, 0}, {{{{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}}}, {0, 0}}}; static int psb_init(void) { int tmp ; { tmp = drm_pci_init(& driver, & psb_pci_driver); return (tmp); } } static void psb_exit(void) { { drm_pci_exit(& driver, & psb_pci_driver); return; } } int ldv_retval_20 ; extern int ldv_shutdown_48(void) ; extern int ldv_thaw_early_52(void) ; int ldv_retval_18 ; int ldv_retval_2 ; int ldv_retval_5 ; int ldv_retval_0 ; int ldv_retval_23 ; int ldv_retval_11 ; int ldv_retval_1 ; extern int ldv_suspend_late_52(void) ; int ldv_retval_22 ; int ldv_retval_15 ; int ldv_retval_16 ; extern int ldv_restore_noirq_52(void) ; extern int ldv_suspend_noirq_52(void) ; void ldv_check_final_state(void) ; int ldv_retval_8 ; extern int ldv_complete_52(void) ; int ldv_retval_7 ; int ldv_retval_19 ; extern int ldv_resume_noirq_52(void) ; int ldv_retval_14 ; extern int ldv_poweroff_noirq_52(void) ; int ldv_retval_17 ; int ldv_retval_12 ; extern int ldv_thaw_noirq_52(void) ; extern int ldv_resume_early_52(void) ; extern void ldv_initialize(void) ; int ldv_retval_6 ; extern int ldv_poweroff_52(void) ; int ldv_retval_21 ; extern int ldv_prepare_52(void) ; extern int ldv_poweroff_late_52(void) ; int ldv_retval_13 ; extern int ldv_freeze_late_52(void) ; int ldv_retval_9 ; int ldv_retval_10 ; extern int ldv_restore_early_52(void) ; extern int ldv_freeze_noirq_52(void) ; int ldv_retval_4 ; int ldv_retval_3 ; void ldv_dev_pm_ops_52(void) { void *tmp ; { tmp = ldv_init_zalloc(1416UL); psb_pm_ops_group1 = (struct device *)tmp; return; } } void ldv_initialize_drm_driver_49(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(744UL); driver_group0 = (struct drm_file *)tmp; tmp___0 = ldv_init_zalloc(3320UL); driver_group1 = (struct drm_device *)tmp___0; return; } } void ldv_file_operations_50(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(1000UL); psb_gem_fops_group1 = (struct inode *)tmp; tmp___0 = ldv_init_zalloc(504UL); psb_gem_fops_group2 = (struct file *)tmp___0; return; } } void ldv_initialize_vm_operations_struct_51(void) { void *tmp ; { tmp = ldv_init_zalloc(184UL); psb_gem_vm_ops_group0 = (struct vm_area_struct *)tmp; return; } } void ldv_pci_driver_48(void) { void *tmp ; { tmp = ldv_init_zalloc(2976UL); psb_pci_driver_group1 = (struct pci_dev *)tmp; return; } } void ldv_main_exported_27(void) ; void ldv_main_exported_28(void) ; void ldv_main_exported_26(void) ; void ldv_main_exported_38(void) ; void ldv_main_exported_39(void) ; void ldv_main_exported_40(void) ; void ldv_main_exported_36(void) ; void ldv_main_exported_37(void) ; void ldv_main_exported_5(void) ; void ldv_main_exported_18(void) ; void ldv_main_exported_16(void) ; void ldv_main_exported_17(void) ; void ldv_main_exported_15(void) ; void ldv_main_exported_14(void) ; void ldv_main_exported_46(void) ; void ldv_main_exported_45(void) ; void ldv_main_exported_47(void) ; void ldv_main_exported_34(void) ; void ldv_main_exported_8(void) ; void ldv_main_exported_6(void) ; void ldv_main_exported_7(void) ; void ldv_main_exported_9(void) ; void ldv_main_exported_13(void) ; void ldv_main_exported_10(void) ; void ldv_main_exported_42(void) ; void ldv_main_exported_43(void) ; void ldv_main_exported_44(void) ; void ldv_main_exported_41(void) ; void ldv_main_exported_11(void) ; void ldv_main_exported_12(void) ; void ldv_main_exported_22(void) ; void ldv_main_exported_21(void) ; void ldv_main_exported_19(void) ; void ldv_main_exported_20(void) ; void ldv_main_exported_35(void) ; void ldv_main_exported_25(void) ; void ldv_main_exported_24(void) ; void ldv_main_exported_23(void) ; void ldv_main_exported_33(void) ; void ldv_main_exported_32(void) ; void ldv_main_exported_30(void) ; void ldv_main_exported_31(void) ; void ldv_main_exported_29(void) ; int main(void) { int ldvarg85 ; int ldvarg84 ; int ldvarg94 ; struct drm_gem_object *ldvarg91 ; void *tmp ; struct drm_master *ldvarg88 ; void *tmp___0 ; unsigned long ldvarg90 ; struct drm_mode_create_dumb *ldvarg87 ; void *tmp___1 ; void *ldvarg86 ; void *tmp___2 ; uint32_t ldvarg93 ; uint64_t *ldvarg92 ; void *tmp___3 ; uint32_t ldvarg89 ; int ldvarg83 ; struct pci_device_id *ldvarg110 ; void *tmp___4 ; size_t ldvarg145 ; struct poll_table_struct *ldvarg143 ; void *tmp___5 ; unsigned long ldvarg140 ; char *ldvarg146 ; void *tmp___6 ; loff_t *ldvarg144 ; void *tmp___7 ; struct vm_area_struct *ldvarg142 ; void *tmp___8 ; unsigned int ldvarg141 ; struct vm_fault *ldvarg155 ; void *tmp___9 ; int tmp___10 ; int tmp___11 ; int tmp___12 ; int tmp___13 ; int tmp___14 ; int tmp___15 ; int tmp___16 ; { tmp = ldv_init_zalloc(248UL); ldvarg91 = (struct drm_gem_object *)tmp; tmp___0 = ldv_init_zalloc(352UL); ldvarg88 = (struct drm_master *)tmp___0; tmp___1 = ldv_init_zalloc(32UL); ldvarg87 = (struct drm_mode_create_dumb *)tmp___1; tmp___2 = ldv_init_zalloc(1UL); ldvarg86 = tmp___2; tmp___3 = ldv_init_zalloc(8UL); ldvarg92 = (uint64_t *)tmp___3; tmp___4 = ldv_init_zalloc(32UL); ldvarg110 = (struct pci_device_id *)tmp___4; tmp___5 = ldv_init_zalloc(16UL); ldvarg143 = (struct poll_table_struct *)tmp___5; tmp___6 = ldv_init_zalloc(1UL); ldvarg146 = (char *)tmp___6; tmp___7 = ldv_init_zalloc(8UL); ldvarg144 = (loff_t *)tmp___7; tmp___8 = ldv_init_zalloc(184UL); ldvarg142 = (struct vm_area_struct *)tmp___8; tmp___9 = ldv_init_zalloc(56UL); ldvarg155 = (struct vm_fault *)tmp___9; ldv_initialize(); ldv_memset((void *)(& ldvarg85), 0, 4UL); ldv_memset((void *)(& ldvarg84), 0, 4UL); ldv_memset((void *)(& ldvarg94), 0, 4UL); ldv_memset((void *)(& ldvarg90), 0, 8UL); ldv_memset((void *)(& ldvarg93), 0, 4UL); ldv_memset((void *)(& ldvarg89), 0, 4UL); ldv_memset((void *)(& ldvarg83), 0, 4UL); ldv_memset((void *)(& ldvarg145), 0, 8UL); ldv_memset((void *)(& ldvarg140), 0, 8UL); ldv_memset((void *)(& ldvarg141), 0, 4UL); ldv_state_variable_33 = 0; ldv_state_variable_32 = 0; ldv_state_variable_21 = 0; ldv_state_variable_7 = 0; ldv_state_variable_26 = 0; ldv_state_variable_17 = 0; work_init_2(); ldv_state_variable_2 = 1; ldv_state_variable_1 = 1; ldv_state_variable_18 = 0; ldv_state_variable_30 = 0; ldv_state_variable_16 = 0; ldv_state_variable_44 = 0; ldv_state_variable_55 = 0; ldv_state_variable_27 = 0; ldv_state_variable_25 = 0; ldv_state_variable_28 = 0; ldv_state_variable_57 = 0; ldv_state_variable_40 = 0; ldv_state_variable_20 = 0; ldv_state_variable_14 = 0; ldv_state_variable_59 = 0; ldv_state_variable_49 = 0; ldv_state_variable_24 = 0; ldv_state_variable_10 = 0; ldv_state_variable_31 = 0; ldv_state_variable_35 = 0; ldv_state_variable_11 = 0; ldv_state_variable_53 = 0; ldv_state_variable_48 = 0; ldv_state_variable_42 = 0; ldv_state_variable_22 = 0; ref_cnt = 0; ldv_state_variable_0 = 1; ldv_state_variable_46 = 0; ldv_state_variable_13 = 0; ldv_state_variable_23 = 0; ldv_state_variable_29 = 0; ldv_state_variable_6 = 0; ldv_state_variable_50 = 0; ldv_state_variable_39 = 0; ldv_state_variable_36 = 0; work_init_3(); ldv_state_variable_3 = 1; ldv_state_variable_51 = 0; ldv_state_variable_9 = 0; ldv_state_variable_58 = 0; ldv_state_variable_41 = 0; ldv_state_variable_12 = 0; ldv_state_variable_47 = 0; ldv_state_variable_15 = 0; ldv_state_variable_52 = 0; ldv_state_variable_38 = 0; ldv_state_variable_8 = 0; ldv_state_variable_60 = 0; ldv_state_variable_4 = 1; ldv_state_variable_34 = 0; ldv_state_variable_56 = 0; ldv_state_variable_45 = 0; ldv_state_variable_37 = 0; ldv_state_variable_43 = 0; ldv_state_variable_19 = 0; ldv_state_variable_54 = 0; ldv_state_variable_5 = 0; ldv_42292: tmp___10 = __VERIFIER_nondet_int(); switch (tmp___10) { case 0: ; if (ldv_state_variable_33 != 0) { ldv_main_exported_33(); } else { } goto ldv_42163; case 1: ; if (ldv_state_variable_32 != 0) { ldv_main_exported_32(); } else { } goto ldv_42163; case 2: ; if (ldv_state_variable_21 != 0) { ldv_main_exported_21(); } else { } goto ldv_42163; case 3: ; if (ldv_state_variable_7 != 0) { ldv_main_exported_7(); } else { } goto ldv_42163; case 4: ; if (ldv_state_variable_26 != 0) { ldv_main_exported_26(); } else { } goto ldv_42163; case 5: ; if (ldv_state_variable_17 != 0) { ldv_main_exported_17(); } else { } goto ldv_42163; case 6: ; goto ldv_42163; case 7: ; goto ldv_42163; case 8: ; if (ldv_state_variable_18 != 0) { ldv_main_exported_18(); } else { } goto ldv_42163; case 9: ; if (ldv_state_variable_30 != 0) { ldv_main_exported_30(); } else { } goto ldv_42163; case 10: ; if (ldv_state_variable_16 != 0) { ldv_main_exported_16(); } else { } goto ldv_42163; case 11: ; if (ldv_state_variable_44 != 0) { ldv_main_exported_44(); } else { } goto ldv_42163; case 12: ; if (ldv_state_variable_55 != 0) { ldv_main_exported_55(); } else { } goto ldv_42163; case 13: ; if (ldv_state_variable_27 != 0) { ldv_main_exported_27(); } else { } goto ldv_42163; case 14: ; if (ldv_state_variable_25 != 0) { ldv_main_exported_25(); } else { } goto ldv_42163; case 15: ; if (ldv_state_variable_28 != 0) { ldv_main_exported_28(); } else { } goto ldv_42163; case 16: ; if (ldv_state_variable_57 != 0) { ldv_main_exported_57(); } else { } goto ldv_42163; case 17: ; if (ldv_state_variable_40 != 0) { ldv_main_exported_40(); } else { } goto ldv_42163; case 18: ; if (ldv_state_variable_20 != 0) { ldv_main_exported_20(); } else { } goto ldv_42163; case 19: ; if (ldv_state_variable_14 != 0) { ldv_main_exported_14(); } else { } goto ldv_42163; case 20: ; if (ldv_state_variable_59 != 0) { ldv_main_exported_59(); } else { } goto ldv_42163; case 21: ; if (ldv_state_variable_49 != 0) { tmp___11 = __VERIFIER_nondet_int(); switch (tmp___11) { case 0: ; if (ldv_state_variable_49 == 1) { psb_driver_lastclose(driver_group1); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 1: ; if (ldv_state_variable_49 == 1) { psb_get_vblank_counter(driver_group1, ldvarg94); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 2: ; if (ldv_state_variable_49 == 1) { psb_gem_dumb_map_gtt(driver_group0, driver_group1, ldvarg93, ldvarg92); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 3: ; if (ldv_state_variable_49 == 1) { psb_gem_free_object(ldvarg91); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 4: ; if (ldv_state_variable_49 == 1) { psb_driver_unload(driver_group1); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 5: ; if (ldv_state_variable_49 == 1) { psb_irq_preinstall(driver_group1); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 6: ; if (ldv_state_variable_49 == 1) { psb_driver_load(driver_group1, ldvarg90); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 7: ; if (ldv_state_variable_49 == 1) { psb_irq_uninstall(driver_group1); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 8: ; if (ldv_state_variable_49 == 1) { drm_gem_dumb_destroy(driver_group0, driver_group1, ldvarg89); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 9: ; if (ldv_state_variable_49 == 1) { psb_irq_postinstall(driver_group1); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 10: ; if (ldv_state_variable_49 == 1) { drm_pci_set_busid(driver_group1, ldvarg88); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 11: ; if (ldv_state_variable_49 == 1) { psb_gem_dumb_create(driver_group0, driver_group1, ldvarg87); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 12: ; if (ldv_state_variable_49 == 1) { psb_irq_handler(ldvarg85, ldvarg86); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 13: ; if (ldv_state_variable_49 == 1) { psb_enable_vblank(driver_group1, ldvarg84); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 14: ; if (ldv_state_variable_49 == 1) { psb_driver_preclose(driver_group1, driver_group0); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 15: ; if (ldv_state_variable_49 == 1) { psb_driver_device_is_agp(driver_group1); ldv_state_variable_49 = 1; } else { } goto ldv_42186; case 16: ; if (ldv_state_variable_49 == 1) { psb_disable_vblank(driver_group1, ldvarg83); ldv_state_variable_49 = 1; } else { } goto ldv_42186; default: ldv_stop(); } ldv_42186: ; } else { } goto ldv_42163; case 22: ; if (ldv_state_variable_24 != 0) { ldv_main_exported_24(); } else { } goto ldv_42163; case 23: ; if (ldv_state_variable_10 != 0) { ldv_main_exported_10(); } else { } goto ldv_42163; case 24: ; if (ldv_state_variable_31 != 0) { ldv_main_exported_31(); } else { } goto ldv_42163; case 25: ; if (ldv_state_variable_35 != 0) { ldv_main_exported_35(); } else { } goto ldv_42163; case 26: ; if (ldv_state_variable_11 != 0) { ldv_main_exported_11(); } else { } goto ldv_42163; case 27: ; if (ldv_state_variable_53 != 0) { ldv_main_exported_53(); } else { } goto ldv_42163; case 28: ; if (ldv_state_variable_48 != 0) { tmp___12 = __VERIFIER_nondet_int(); switch (tmp___12) { case 0: ; if (ldv_state_variable_48 == 1) { ldv_retval_0 = psb_pci_probe(psb_pci_driver_group1, (struct pci_device_id const *)ldvarg110); if (ldv_retval_0 == 0) { ldv_state_variable_48 = 2; ref_cnt = ref_cnt + 1; } else { } } else { } goto ldv_42212; case 1: ; if (ldv_state_variable_48 == 2) { psb_pci_remove(psb_pci_driver_group1); ldv_state_variable_48 = 1; } else { } goto ldv_42212; case 2: ; if (ldv_state_variable_48 == 2) { ldv_shutdown_48(); ldv_state_variable_48 = 2; } else { } goto ldv_42212; default: ldv_stop(); } ldv_42212: ; } else { } goto ldv_42163; case 29: ; if (ldv_state_variable_42 != 0) { ldv_main_exported_42(); } else { } goto ldv_42163; case 30: ; if (ldv_state_variable_22 != 0) { ldv_main_exported_22(); } else { } goto ldv_42163; case 31: ; if (ldv_state_variable_0 != 0) { tmp___13 = __VERIFIER_nondet_int(); switch (tmp___13) { case 0: ; if (ldv_state_variable_0 == 3 && ref_cnt == 0) { psb_exit(); ldv_state_variable_0 = 2; goto ldv_final; } else { } goto ldv_42221; case 1: ; if (ldv_state_variable_0 == 1) { ldv_retval_1 = psb_init(); if (ldv_retval_1 == 0) { ldv_state_variable_0 = 3; ldv_state_variable_5 = 1; ldv_initialize_i2c_algorithm_5(); ldv_state_variable_54 = 1; ldv_initialize_drm_mode_config_funcs_54(); ldv_state_variable_19 = 1; ldv_state_variable_43 = 1; ldv_initialize_drm_connector_helper_funcs_43(); ldv_state_variable_37 = 1; ldv_state_variable_45 = 1; ldv_initialize_gma_clock_funcs_45(); ldv_state_variable_56 = 1; ldv_initialize_fb_ops_56(); ldv_state_variable_34 = 1; ldv_state_variable_60 = 1; ldv_initialize_drm_framebuffer_funcs_60(); ldv_state_variable_8 = 1; ldv_initialize_drm_connector_helper_funcs_8(); ldv_state_variable_38 = 1; ldv_initialize_drm_connector_helper_funcs_38(); ldv_state_variable_52 = 1; ldv_dev_pm_ops_52(); ldv_state_variable_15 = 1; ldv_initialize_drm_connector_helper_funcs_15(); ldv_state_variable_47 = 1; ldv_initialize_drm_crtc_helper_funcs_47(); ldv_state_variable_12 = 1; ldv_initialize_drm_crtc_helper_funcs_12(); ldv_state_variable_41 = 1; ldv_state_variable_58 = 1; ldv_initialize_fb_ops_58(); ldv_state_variable_9 = 1; ldv_initialize_drm_encoder_helper_funcs_9(); ldv_state_variable_51 = 1; ldv_initialize_vm_operations_struct_51(); ldv_state_variable_36 = 1; ldv_initialize_i2c_algorithm_36(); ldv_state_variable_39 = 1; ldv_initialize_drm_connector_funcs_39(); ldv_state_variable_50 = 1; ldv_file_operations_50(); ldv_state_variable_6 = 1; ldv_state_variable_29 = 1; ldv_state_variable_23 = 1; ldv_initialize_drm_connector_funcs_23(); ldv_state_variable_13 = 1; ldv_initialize_psb_ops_13(); ldv_state_variable_46 = 1; ldv_initialize_drm_crtc_funcs_46(); ldv_state_variable_22 = 1; ldv_initialize_drm_encoder_helper_funcs_22(); ldv_state_variable_42 = 1; ldv_initialize_drm_connector_funcs_42(); ldv_state_variable_48 = 1; ldv_pci_driver_48(); ldv_state_variable_53 = 1; ldv_initialize_i2c_algorithm_53(); ldv_state_variable_11 = 1; ldv_initialize_gma_clock_funcs_11(); ldv_state_variable_35 = 1; ldv_initialize_psb_ops_35(); ldv_state_variable_31 = 1; ldv_initialize_drm_connector_funcs_31(); ldv_state_variable_10 = 1; ldv_initialize_drm_encoder_helper_funcs_10(); ldv_state_variable_24 = 1; ldv_initialize_drm_connector_helper_funcs_24(); ldv_state_variable_49 = 1; ldv_initialize_drm_driver_49(); ldv_state_variable_59 = 1; ldv_initialize_vm_operations_struct_59(); ldv_state_variable_20 = 1; ldv_initialize_drm_connector_funcs_20(); ldv_state_variable_14 = 1; ldv_state_variable_40 = 1; ldv_initialize_drm_encoder_helper_funcs_40(); ldv_state_variable_57 = 1; ldv_initialize_fb_ops_57(); ldv_state_variable_28 = 1; ldv_initialize_drm_crtc_helper_funcs_28(); ldv_state_variable_25 = 1; ldv_initialize_drm_encoder_helper_funcs_25(); ldv_state_variable_27 = 1; ldv_initialize_drm_crtc_funcs_27(); ldv_state_variable_55 = 1; ldv_initialize_drm_fb_helper_funcs_55(); ldv_state_variable_44 = 1; ldv_initialize_drm_encoder_helper_funcs_44(); ldv_state_variable_16 = 1; ldv_initialize_drm_connector_funcs_16(); ldv_state_variable_30 = 1; ldv_initialize_drm_connector_helper_funcs_30(); ldv_state_variable_18 = 1; ldv_initialize_i2c_algorithm_18(); ldv_state_variable_17 = 1; ldv_initialize_drm_encoder_helper_funcs_17(); ldv_state_variable_26 = 1; ldv_initialize_gma_clock_funcs_26(); ldv_state_variable_7 = 1; ldv_initialize_drm_connector_funcs_7(); ldv_state_variable_21 = 1; ldv_initialize_drm_connector_helper_funcs_21(); ldv_state_variable_32 = 1; ldv_initialize_drm_encoder_helper_funcs_32(); ldv_state_variable_33 = 1; ldv_initialize_psb_ops_33(); } else { } if (ldv_retval_1 != 0) { ldv_state_variable_0 = 2; goto ldv_final; } else { } } else { } goto ldv_42221; default: ldv_stop(); } ldv_42221: ; } else { } goto ldv_42163; case 32: ; if (ldv_state_variable_46 != 0) { ldv_main_exported_46(); } else { } goto ldv_42163; case 33: ; if (ldv_state_variable_13 != 0) { ldv_main_exported_13(); } else { } goto ldv_42163; case 34: ; if (ldv_state_variable_23 != 0) { ldv_main_exported_23(); } else { } goto ldv_42163; case 35: ; if (ldv_state_variable_29 != 0) { ldv_main_exported_29(); } else { } goto ldv_42163; case 36: ; if (ldv_state_variable_6 != 0) { ldv_main_exported_6(); } else { } goto ldv_42163; case 37: ; if (ldv_state_variable_50 != 0) { tmp___14 = __VERIFIER_nondet_int(); switch (tmp___14) { case 0: ; if (ldv_state_variable_50 == 2) { drm_read(psb_gem_fops_group2, ldvarg146, ldvarg145, ldvarg144); ldv_state_variable_50 = 2; } else { } goto ldv_42231; case 1: ; if (ldv_state_variable_50 == 1) { drm_poll(psb_gem_fops_group2, ldvarg143); ldv_state_variable_50 = 1; } else { } if (ldv_state_variable_50 == 2) { drm_poll(psb_gem_fops_group2, ldvarg143); ldv_state_variable_50 = 2; } else { } goto ldv_42231; case 2: ; if (ldv_state_variable_50 == 1) { ldv_retval_2 = drm_open(psb_gem_fops_group1, psb_gem_fops_group2); if (ldv_retval_2 == 0) { ldv_state_variable_50 = 2; ref_cnt = ref_cnt + 1; } else { } } else { } goto ldv_42231; case 3: ; if (ldv_state_variable_50 == 1) { drm_gem_mmap(psb_gem_fops_group2, ldvarg142); ldv_state_variable_50 = 1; } else { } if (ldv_state_variable_50 == 2) { drm_gem_mmap(psb_gem_fops_group2, ldvarg142); ldv_state_variable_50 = 2; } else { } goto ldv_42231; case 4: ; if (ldv_state_variable_50 == 2) { drm_release(psb_gem_fops_group1, psb_gem_fops_group2); ldv_state_variable_50 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42231; case 5: ; if (ldv_state_variable_50 == 2) { psb_unlocked_ioctl(psb_gem_fops_group2, ldvarg141, ldvarg140); ldv_state_variable_50 = 2; } else { } goto ldv_42231; default: ldv_stop(); } ldv_42231: ; } else { } goto ldv_42163; case 38: ; if (ldv_state_variable_39 != 0) { ldv_main_exported_39(); } else { } goto ldv_42163; case 39: ; if (ldv_state_variable_36 != 0) { ldv_main_exported_36(); } else { } goto ldv_42163; case 40: ; goto ldv_42163; case 41: ; if (ldv_state_variable_51 != 0) { tmp___15 = __VERIFIER_nondet_int(); switch (tmp___15) { case 0: ; if (ldv_state_variable_51 == 1) { psb_gem_fault(psb_gem_vm_ops_group0, ldvarg155); ldv_state_variable_51 = 1; } else { } if (ldv_state_variable_51 == 2) { psb_gem_fault(psb_gem_vm_ops_group0, ldvarg155); ldv_state_variable_51 = 2; } else { } goto ldv_42243; case 1: ; if (ldv_state_variable_51 == 2) { drm_gem_vm_close(psb_gem_vm_ops_group0); ldv_state_variable_51 = 1; } else { } goto ldv_42243; case 2: ; if (ldv_state_variable_51 == 1) { drm_gem_vm_open(psb_gem_vm_ops_group0); ldv_state_variable_51 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42243; default: ldv_stop(); } ldv_42243: ; } else { } goto ldv_42163; case 42: ; if (ldv_state_variable_9 != 0) { ldv_main_exported_9(); } else { } goto ldv_42163; case 43: ; if (ldv_state_variable_58 != 0) { ldv_main_exported_58(); } else { } goto ldv_42163; case 44: ; if (ldv_state_variable_41 != 0) { ldv_main_exported_41(); } else { } goto ldv_42163; case 45: ; if (ldv_state_variable_12 != 0) { ldv_main_exported_12(); } else { } goto ldv_42163; case 46: ; if (ldv_state_variable_47 != 0) { ldv_main_exported_47(); } else { } goto ldv_42163; case 47: ; if (ldv_state_variable_15 != 0) { ldv_main_exported_15(); } else { } goto ldv_42163; case 48: ; if (ldv_state_variable_52 != 0) { tmp___16 = __VERIFIER_nondet_int(); switch (tmp___16) { case 0: ; if (ldv_state_variable_52 == 14) { ldv_retval_23 = gma_power_thaw(psb_pm_ops_group1); if (ldv_retval_23 == 0) { ldv_state_variable_52 = 16; } else { } } else { } goto ldv_42255; case 1: ; if (ldv_state_variable_52 == 2) { ldv_retval_22 = psb_runtime_resume(psb_pm_ops_group1); if (ldv_retval_22 == 0) { ldv_state_variable_52 = 1; ref_cnt = ref_cnt - 1; } else { } } else { } goto ldv_42255; case 2: ; if (ldv_state_variable_52 == 2) { psb_runtime_idle(psb_pm_ops_group1); ldv_state_variable_52 = 2; } else { } if (ldv_state_variable_52 == 1) { psb_runtime_idle(psb_pm_ops_group1); ldv_state_variable_52 = 1; } else { } goto ldv_42255; case 3: ; if (ldv_state_variable_52 == 3) { ldv_retval_21 = gma_power_suspend(psb_pm_ops_group1); if (ldv_retval_21 == 0) { ldv_state_variable_52 = 4; } else { } } else { } goto ldv_42255; case 4: ; if (ldv_state_variable_52 == 15) { ldv_retval_20 = gma_power_restore(psb_pm_ops_group1); if (ldv_retval_20 == 0) { ldv_state_variable_52 = 16; } else { } } else { } goto ldv_42255; case 5: ; if (ldv_state_variable_52 == 1) { ldv_retval_19 = psb_runtime_suspend(psb_pm_ops_group1); if (ldv_retval_19 == 0) { ldv_state_variable_52 = 2; ref_cnt = ref_cnt + 1; } else { } } else { } goto ldv_42255; case 6: ; if (ldv_state_variable_52 == 3) { ldv_retval_18 = gma_power_freeze(psb_pm_ops_group1); if (ldv_retval_18 == 0) { ldv_state_variable_52 = 5; } else { } } else { } goto ldv_42255; case 7: ; if (ldv_state_variable_52 == 13) { ldv_retval_17 = gma_power_resume(psb_pm_ops_group1); if (ldv_retval_17 == 0) { ldv_state_variable_52 = 16; } else { } } else { } goto ldv_42255; case 8: ; if (ldv_state_variable_52 == 4) { ldv_retval_16 = ldv_suspend_late_52(); if (ldv_retval_16 == 0) { ldv_state_variable_52 = 7; } else { } } else { } goto ldv_42255; case 9: ; if (ldv_state_variable_52 == 12) { ldv_retval_15 = ldv_restore_early_52(); if (ldv_retval_15 == 0) { ldv_state_variable_52 = 15; } else { } } else { } goto ldv_42255; case 10: ; if (ldv_state_variable_52 == 7) { ldv_retval_14 = ldv_resume_early_52(); if (ldv_retval_14 == 0) { ldv_state_variable_52 = 13; } else { } } else { } goto ldv_42255; case 11: ; if (ldv_state_variable_52 == 10) { ldv_retval_13 = ldv_thaw_early_52(); if (ldv_retval_13 == 0) { ldv_state_variable_52 = 14; } else { } } else { } goto ldv_42255; case 12: ; if (ldv_state_variable_52 == 8) { ldv_retval_12 = ldv_resume_noirq_52(); if (ldv_retval_12 == 0) { ldv_state_variable_52 = 13; } else { } } else { } goto ldv_42255; case 13: ; if (ldv_state_variable_52 == 5) { ldv_retval_11 = ldv_freeze_noirq_52(); if (ldv_retval_11 == 0) { ldv_state_variable_52 = 9; } else { } } else { } goto ldv_42255; case 14: ; if (ldv_state_variable_52 == 1) { ldv_retval_10 = ldv_prepare_52(); if (ldv_retval_10 == 0) { ldv_state_variable_52 = 3; ref_cnt = ref_cnt + 1; } else { } } else { } goto ldv_42255; case 15: ; if (ldv_state_variable_52 == 5) { ldv_retval_9 = ldv_freeze_late_52(); if (ldv_retval_9 == 0) { ldv_state_variable_52 = 10; } else { } } else { } goto ldv_42255; case 16: ; if (ldv_state_variable_52 == 9) { ldv_retval_8 = ldv_thaw_noirq_52(); if (ldv_retval_8 == 0) { ldv_state_variable_52 = 14; } else { } } else { } goto ldv_42255; case 17: ; if (ldv_state_variable_52 == 3) { ldv_retval_7 = ldv_poweroff_52(); if (ldv_retval_7 == 0) { ldv_state_variable_52 = 6; } else { } } else { } goto ldv_42255; case 18: ; if (ldv_state_variable_52 == 6) { ldv_retval_6 = ldv_poweroff_noirq_52(); if (ldv_retval_6 == 0) { ldv_state_variable_52 = 11; } else { } } else { } goto ldv_42255; case 19: ; if (ldv_state_variable_52 == 6) { ldv_retval_5 = ldv_poweroff_late_52(); if (ldv_retval_5 == 0) { ldv_state_variable_52 = 12; } else { } } else { } goto ldv_42255; case 20: ; if (ldv_state_variable_52 == 11) { ldv_retval_4 = ldv_restore_noirq_52(); if (ldv_retval_4 == 0) { ldv_state_variable_52 = 15; } else { } } else { } goto ldv_42255; case 21: ; if (ldv_state_variable_52 == 4) { ldv_retval_3 = ldv_suspend_noirq_52(); if (ldv_retval_3 == 0) { ldv_state_variable_52 = 8; } else { } } else { } goto ldv_42255; case 22: ; if (ldv_state_variable_52 == 16) { ldv_complete_52(); ldv_state_variable_52 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42255; default: ldv_stop(); } ldv_42255: ; } else { } goto ldv_42163; case 49: ; if (ldv_state_variable_38 != 0) { ldv_main_exported_38(); } else { } goto ldv_42163; case 50: ; if (ldv_state_variable_8 != 0) { ldv_main_exported_8(); } else { } goto ldv_42163; case 51: ; if (ldv_state_variable_60 != 0) { ldv_main_exported_60(); } else { } goto ldv_42163; case 52: ; goto ldv_42163; case 53: ; if (ldv_state_variable_34 != 0) { ldv_main_exported_34(); } else { } goto ldv_42163; case 54: ; if (ldv_state_variable_56 != 0) { ldv_main_exported_56(); } else { } goto ldv_42163; case 55: ; if (ldv_state_variable_45 != 0) { ldv_main_exported_45(); } else { } goto ldv_42163; case 56: ; if (ldv_state_variable_37 != 0) { ldv_main_exported_37(); } else { } goto ldv_42163; case 57: ; if (ldv_state_variable_43 != 0) { ldv_main_exported_43(); } else { } goto ldv_42163; case 58: ; if (ldv_state_variable_19 != 0) { ldv_main_exported_19(); } else { } goto ldv_42163; case 59: ; if (ldv_state_variable_54 != 0) { ldv_main_exported_54(); } else { } goto ldv_42163; case 60: ; if (ldv_state_variable_5 != 0) { ldv_main_exported_5(); } else { } goto ldv_42163; default: ldv_stop(); } ldv_42163: ; goto ldv_42292; ldv_final: ldv_check_final_state(); return 0; } } bool ldv_queue_work_on_159(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_160(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_161(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_162(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_163(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_173(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_175(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_174(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_177(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_176(struct workqueue_struct *ldv_func_arg1 ) ; __inline static int kref_sub___1(struct kref *kref , unsigned int count , void (*release)(struct kref * ) ) { int __ret_warn_on ; long tmp ; int tmp___0 ; { __ret_warn_on = (unsigned long )release == (unsigned long )((void (*)(struct kref * ))0); tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("include/linux/kref.h", 71); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); tmp___0 = atomic_sub_and_test((int )count, & kref->refcount); if (tmp___0 != 0) { (*release)(kref); return (1); } else { } return (0); } } __inline static int kref_put___1(struct kref *kref , void (*release)(struct kref * ) ) { int tmp ; { tmp = kref_sub___1(kref, 1U, release); return (tmp); } } extern void drm_crtc_cleanup(struct drm_crtc * ) ; extern void drm_encoder_cleanup(struct drm_encoder * ) ; extern int drm_mode_connector_attach_encoder(struct drm_connector * , struct drm_encoder * ) ; extern void drm_vblank_off(struct drm_device * , int ) ; extern void pm_runtime_forbid(struct device * ) ; bool gma_pipe_has_type(struct drm_crtc *crtc , int type ) ; void gma_wait_for_vblank(struct drm_device *dev ) ; int gma_pipe_set_base(struct drm_crtc *crtc , int x , int y , struct drm_framebuffer *old_fb ) ; int gma_crtc_cursor_set(struct drm_crtc *crtc , struct drm_file *file_priv , uint32_t handle , uint32_t width , uint32_t height ) ; int gma_crtc_cursor_move(struct drm_crtc *crtc , int x , int y ) ; void gma_crtc_load_lut(struct drm_crtc *crtc ) ; void gma_crtc_gamma_set(struct drm_crtc *crtc , u16 *red , u16 *green , u16 *blue , u32 start , u32 size ) ; void gma_crtc_dpms(struct drm_crtc *crtc , int mode ) ; bool gma_crtc_mode_fixup(struct drm_crtc *crtc , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) ; void gma_crtc_prepare(struct drm_crtc *crtc ) ; void gma_crtc_commit(struct drm_crtc *crtc ) ; void gma_crtc_disable(struct drm_crtc *crtc ) ; void gma_crtc_destroy(struct drm_crtc *crtc ) ; int gma_crtc_set_config(struct drm_mode_set *set ) ; void gma_crtc_save(struct drm_crtc *crtc ) ; void gma_crtc_restore(struct drm_crtc *crtc ) ; void gma_encoder_prepare(struct drm_encoder *encoder ) ; void gma_encoder_commit(struct drm_encoder *encoder ) ; void gma_encoder_destroy(struct drm_encoder *encoder ) ; bool gma_encoder_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) ; bool gma_pll_is_valid(struct drm_crtc *crtc , struct gma_limit_t const *limit , struct gma_clock_t *clock ) ; bool gma_find_best_pll(struct gma_limit_t const *limit , struct drm_crtc *crtc , int target , int refclk , struct gma_clock_t *best_clock ) ; extern int drm_crtc_helper_set_config(struct drm_mode_set * ) ; struct drm_encoder *gma_best_encoder(struct drm_connector *connector ) ; void gma_connector_attach_encoder(struct gma_connector *connector , struct gma_encoder *encoder ) ; __inline static void drm_gem_object_unreference___1(struct drm_gem_object *obj ) { { if ((unsigned long )obj != (unsigned long )((struct drm_gem_object *)0)) { kref_put___1(& obj->refcount, & drm_gem_object_free); } else { } return; } } bool gma_pipe_has_type(struct drm_crtc *crtc , int type ) { struct drm_device *dev ; struct drm_mode_config *mode_config ; struct drm_connector *l_entry ; struct list_head const *__mptr ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct list_head const *__mptr___0 ; { dev = crtc->dev; mode_config = & dev->mode_config; __mptr = (struct list_head const *)mode_config->connector_list.next; l_entry = (struct drm_connector *)__mptr + 0xffffffffffffffe8UL; goto ldv_41683; ldv_41682: ; if ((unsigned long )l_entry->encoder != (unsigned long )((struct drm_encoder *)0) && (unsigned long )(l_entry->encoder)->crtc == (unsigned long )crtc) { tmp = gma_attached_encoder(l_entry); gma_encoder = tmp; if (gma_encoder->type == type) { return (1); } else { } } else { } __mptr___0 = (struct list_head const *)l_entry->head.next; l_entry = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; ldv_41683: ; if ((unsigned long )(& l_entry->head) != (unsigned long )(& mode_config->connector_list)) { goto ldv_41682; } else { } return (0); } } void gma_wait_for_vblank(struct drm_device *dev ) { unsigned long __ms ; unsigned long tmp ; { __ms = 20UL; goto ldv_41690; ldv_41689: __const_udelay(4295000UL); ldv_41690: tmp = __ms; __ms = __ms - 1UL; if (tmp != 0UL) { goto ldv_41689; } else { } return; } } int gma_pipe_set_base(struct drm_crtc *crtc , int x , int y , struct drm_framebuffer *old_fb ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct psb_framebuffer *psbfb ; struct drm_framebuffer const *__mptr___0 ; int pipe ; struct psb_offset const *map ; unsigned long start ; unsigned long offset ; u32 dspcntr ; int ret ; bool tmp ; int tmp___0 ; struct _ddebug descriptor ; long tmp___1 ; struct drm_framebuffer const *__mptr___1 ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; __mptr___0 = (struct drm_framebuffer const *)(crtc->primary)->fb; psbfb = (struct psb_framebuffer *)__mptr___0; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; ret = 0; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } if ((unsigned long )(crtc->primary)->fb == (unsigned long )((struct drm_framebuffer *)0)) { dev_err((struct device const *)dev->dev, "No FB bound\n"); goto gma_pipe_cleaner; } else { } ret = psb_gtt_pin(psbfb->gtt); if (ret < 0) { goto gma_pipe_set_base_exit; } else { } start = (unsigned long )(psbfb->gtt)->offset; offset = (unsigned long )(((crtc->primary)->fb)->pitches[0] * (unsigned int )y + (unsigned int )((((crtc->primary)->fb)->bits_per_pixel / 8) * x)); REGISTER_WRITE(dev, map->stride, ((crtc->primary)->fb)->pitches[0]); dspcntr = REGISTER_READ(dev, map->cntr); dspcntr = dspcntr & 3288334335U; switch (((crtc->primary)->fb)->bits_per_pixel) { case 8: dspcntr = dspcntr | 134217728U; goto ldv_41715; case 16: ; if (((crtc->primary)->fb)->depth == 15U) { dspcntr = dspcntr | 268435456U; } else { dspcntr = dspcntr | 335544320U; } goto ldv_41715; case 24: ; case 32: dspcntr = dspcntr | 402653184U; goto ldv_41715; default: dev_err((struct device const *)dev->dev, "Unknown color depth\n"); ret = -22; goto gma_pipe_set_base_exit; } ldv_41715: REGISTER_WRITE(dev, map->cntr, dspcntr); descriptor.modname = "gma500_gfx"; descriptor.function = "gma_pipe_set_base"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gma_display.c"; descriptor.format = "Writing base %08lX %08lX %d %d\n"; descriptor.lineno = 113U; descriptor.flags = 0U; tmp___1 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___1 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "Writing base %08lX %08lX %d %d\n", start, offset, x, y); } else { } if (((int )(dev->pdev)->device & 65534) == 33032) { REGISTER_WRITE(dev, map->base, (uint32_t )offset + (uint32_t )start); REGISTER_READ(dev, map->base); } else { REGISTER_WRITE(dev, map->base, (uint32_t )offset); REGISTER_READ(dev, map->base); REGISTER_WRITE(dev, map->surf, (uint32_t )start); REGISTER_READ(dev, map->surf); } gma_pipe_cleaner: ; if ((unsigned long )old_fb != (unsigned long )((struct drm_framebuffer *)0)) { __mptr___1 = (struct drm_framebuffer const *)old_fb; psb_gtt_unpin(((struct psb_framebuffer *)__mptr___1)->gtt); } else { } gma_pipe_set_base_exit: gma_power_end(dev); return (ret); } } void gma_crtc_load_lut(struct drm_crtc *crtc ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct psb_offset const *map ; int palreg ; int i ; bool tmp ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; map = dev_priv->regmap + (unsigned long )gma_crtc->pipe; palreg = (int )map->palette; if (! crtc->enabled) { return; } else { } tmp = gma_power_begin(dev, 0); if ((int )tmp) { i = 0; goto ldv_41736; ldv_41735: REGISTER_WRITE(dev, (uint32_t )(i * 4 + palreg), (uint32_t )(((((int )gma_crtc->lut_r[i] + (int )gma_crtc->lut_adj[i]) << 16) | (((int )gma_crtc->lut_g[i] + (int )gma_crtc->lut_adj[i]) << 8)) | ((int )gma_crtc->lut_b[i] + (int )gma_crtc->lut_adj[i]))); i = i + 1; ldv_41736: ; if (i <= 255) { goto ldv_41735; } else { } gma_power_end(dev); } else { i = 0; goto ldv_41739; ldv_41738: dev_priv->regs.pipe[0].palette[i] = (u32 )(((((int )gma_crtc->lut_r[i] + (int )gma_crtc->lut_adj[i]) << 16) | (((int )gma_crtc->lut_g[i] + (int )gma_crtc->lut_adj[i]) << 8)) | ((int )gma_crtc->lut_b[i] + (int )gma_crtc->lut_adj[i])); i = i + 1; ldv_41739: ; if (i <= 255) { goto ldv_41738; } else { } } return; } } void gma_crtc_gamma_set(struct drm_crtc *crtc , u16 *red , u16 *green , u16 *blue , u32 start , u32 size ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int i ; int end ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; end = (int )(256U < start + size ? 256U : start + size); i = (int )start; goto ldv_41755; ldv_41754: gma_crtc->lut_r[i] = (u8 )((int )*(red + (unsigned long )i) >> 8); gma_crtc->lut_g[i] = (u8 )((int )*(green + (unsigned long )i) >> 8); gma_crtc->lut_b[i] = (u8 )((int )*(blue + (unsigned long )i) >> 8); i = i + 1; ldv_41755: ; if (i < end) { goto ldv_41754; } else { } gma_crtc_load_lut(crtc); return; } } void gma_crtc_dpms(struct drm_crtc *crtc , int mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; struct psb_offset const *map ; u32 temp ; uint32_t tmp ; uint32_t tmp___0 ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; if (((int )(dev->pdev)->device & 65520) == 3040) { (*((dev_priv->ops)->disable_sr))(dev); } else { } switch (mode) { case 0: ; case 1: ; case 2: ; if ((int )gma_crtc->active) { goto ldv_41772; } else { } gma_crtc->active = 1; temp = REGISTER_READ(dev, map->dpll); if ((int )temp >= 0) { REGISTER_WRITE(dev, map->dpll, temp); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); REGISTER_WRITE(dev, map->dpll, temp | 2147483648U); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); REGISTER_WRITE(dev, map->dpll, temp | 2147483648U); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); } else { } temp = REGISTER_READ(dev, map->cntr); if ((int )temp >= 0) { REGISTER_WRITE(dev, map->cntr, temp | 2147483648U); tmp = REGISTER_READ(dev, map->base); REGISTER_WRITE(dev, map->base, tmp); } else { } __const_udelay(644250UL); temp = REGISTER_READ(dev, map->conf); if ((int )temp >= 0) { REGISTER_WRITE(dev, map->conf, temp | 2147483648U); } else { } temp = REGISTER_READ(dev, map->status); temp = temp & 4294901760U; temp = temp | 2147483648U; REGISTER_WRITE(dev, map->status, temp); REGISTER_READ(dev, map->status); gma_crtc_load_lut(crtc); goto ldv_41772; case 3: ; if (! gma_crtc->active) { goto ldv_41772; } else { } gma_crtc->active = 0; REGISTER_WRITE(dev, 463872U, 2147483648U); drm_vblank_off(dev, pipe); gma_wait_for_vblank(dev); temp = REGISTER_READ(dev, map->cntr); if ((int )temp < 0) { REGISTER_WRITE(dev, map->cntr, temp & 2147483647U); tmp___0 = REGISTER_READ(dev, map->base); REGISTER_WRITE(dev, map->base, tmp___0); REGISTER_READ(dev, map->base); } else { } temp = REGISTER_READ(dev, map->conf); if ((int )temp < 0) { REGISTER_WRITE(dev, map->conf, temp & 2147483647U); REGISTER_READ(dev, map->conf); } else { } gma_wait_for_vblank(dev); __const_udelay(644250UL); temp = REGISTER_READ(dev, map->dpll); if ((int )temp < 0) { REGISTER_WRITE(dev, map->dpll, temp & 2147483647U); REGISTER_READ(dev, map->dpll); } else { } __const_udelay(644250UL); goto ldv_41772; } ldv_41772: ; if (((int )(dev->pdev)->device & 65520) == 3040) { (*((dev_priv->ops)->update_wm))(dev, crtc); } else { } REGISTER_WRITE(dev, 458800U, 16190U); return; } } int gma_crtc_cursor_set(struct drm_crtc *crtc , struct drm_file *file_priv , uint32_t handle , uint32_t width , uint32_t height ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; uint32_t control ; uint32_t base ; uint32_t temp ; size_t addr ; struct gtt_range *gt ; struct gtt_range *cursor_gt ; struct drm_gem_object *obj ; void *tmp_dst ; void *tmp_src ; int ret ; int i ; int cursor_pages ; bool tmp ; struct drm_gem_object const *__mptr___0 ; struct _ddebug descriptor ; long tmp___0 ; struct _ddebug descriptor___0 ; long tmp___1 ; struct drm_gem_object const *__mptr___1 ; bool tmp___2 ; struct drm_gem_object const *__mptr___2 ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; control = pipe == 0 ? 458880U : 458944U; base = pipe == 0 ? 458884U : 458948U; addr = 0UL; cursor_gt = gma_crtc->cursor_gt; ret = 0; if (handle == 0U) { temp = 0U; mutex_lock_nested(& dev->struct_mutex, 0U); tmp = gma_power_begin(dev, 0); if ((int )tmp) { REGISTER_WRITE(dev, control, temp); REGISTER_WRITE(dev, base, 0U); gma_power_end(dev); } else { } if ((unsigned long )gma_crtc->cursor_obj != (unsigned long )((struct drm_gem_object *)0)) { __mptr___0 = (struct drm_gem_object const *)gma_crtc->cursor_obj; gt = (struct gtt_range *)__mptr___0 + 0xffffffffffffffc0UL; psb_gtt_unpin(gt); drm_gem_object_unreference___1(gma_crtc->cursor_obj); gma_crtc->cursor_obj = (struct drm_gem_object *)0; } else { } mutex_unlock(& dev->struct_mutex); return (0); } else { } if (width != 64U || height != 64U) { descriptor.modname = "gma500_gfx"; descriptor.function = "gma_crtc_cursor_set"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gma_display.c"; descriptor.format = "We currently only support 64x64 cursors\n"; descriptor.lineno = 375U; descriptor.flags = 0U; tmp___0 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___0 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "We currently only support 64x64 cursors\n"); } else { } return (-22); } else { } mutex_lock_nested(& dev->struct_mutex, 0U); obj = drm_gem_object_lookup(dev, file_priv, handle); if ((unsigned long )obj == (unsigned long )((struct drm_gem_object *)0)) { ret = -2; goto unlock; } else { } if (obj->size < (size_t )((width * height) * 4U)) { descriptor___0.modname = "gma500_gfx"; descriptor___0.function = "gma_crtc_cursor_set"; descriptor___0.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/gma_display.c"; descriptor___0.format = "Buffer is too small\n"; descriptor___0.lineno = 387U; descriptor___0.flags = 0U; tmp___1 = ldv__builtin_expect((long )descriptor___0.flags & 1L, 0L); if (tmp___1 != 0L) { __dynamic_dev_dbg(& descriptor___0, (struct device const *)dev->dev, "Buffer is too small\n"); } else { } ret = -12; goto unref_cursor; } else { } __mptr___1 = (struct drm_gem_object const *)obj; gt = (struct gtt_range *)__mptr___1 + 0xffffffffffffffc0UL; ret = psb_gtt_pin(gt); if (ret != 0) { dev_err((struct device const *)dev->dev, "Can not pin down handle 0x%x\n", handle); goto unref_cursor; } else { } if ((int )(dev_priv->ops)->cursor_needs_phys != 0) { if ((unsigned long )cursor_gt == (unsigned long )((struct gtt_range *)0)) { dev_err((struct device const *)dev->dev, "No hardware cursor mem available"); ret = -12; goto unref_cursor; } else { } if (gt->npage > 4) { cursor_pages = 4; } else { cursor_pages = gt->npage; } tmp_dst = (void *)dev_priv->vram_addr + (unsigned long )cursor_gt->offset; i = 0; goto ldv_41809; ldv_41808: tmp_src = kmap(*(gt->pages + (unsigned long )i)); memcpy(tmp_dst, (void const *)tmp_src, 4096UL); kunmap(*(gt->pages + (unsigned long )i)); tmp_dst = tmp_dst + 4096UL; i = i + 1; ldv_41809: ; if (i < cursor_pages) { goto ldv_41808; } else { } addr = (size_t )gma_crtc->cursor_addr; } else { addr = (size_t )gt->offset; gma_crtc->cursor_addr = (uint32_t )addr; } temp = 0U; temp = (uint32_t )(pipe << 28) | temp; temp = temp | 67108903U; tmp___2 = gma_power_begin(dev, 0); if ((int )tmp___2) { REGISTER_WRITE(dev, control, temp); REGISTER_WRITE(dev, base, (uint32_t )addr); gma_power_end(dev); } else { } if ((unsigned long )gma_crtc->cursor_obj != (unsigned long )((struct drm_gem_object *)0)) { __mptr___2 = (struct drm_gem_object const *)gma_crtc->cursor_obj; gt = (struct gtt_range *)__mptr___2 + 0xffffffffffffffc0UL; psb_gtt_unpin(gt); drm_gem_object_unreference___1(gma_crtc->cursor_obj); } else { } gma_crtc->cursor_obj = obj; unlock: mutex_unlock(& dev->struct_mutex); return (ret); unref_cursor: drm_gem_object_unreference___1(obj); mutex_unlock(& dev->struct_mutex); return (ret); } } int gma_crtc_cursor_move(struct drm_crtc *crtc , int x , int y ) { struct drm_device *dev ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; uint32_t temp ; uint32_t addr ; bool tmp ; { dev = crtc->dev; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; temp = 0U; if (x < 0) { temp = temp | 32768U; x = - x; } else { } if (y < 0) { temp = temp | 2147483648U; y = - y; } else { } temp = ((uint32_t )x & 2047U) | temp; temp = (uint32_t )((y & 2047) << 16) | temp; addr = gma_crtc->cursor_addr; tmp = gma_power_begin(dev, 0); if ((int )tmp) { REGISTER_WRITE(dev, pipe == 0 ? 458888U : 458952U, temp); REGISTER_WRITE(dev, pipe == 0 ? 458884U : 458948U, addr); gma_power_end(dev); } else { } return (0); } } bool gma_encoder_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) { { return (1); } } bool gma_crtc_mode_fixup(struct drm_crtc *crtc , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) { { return (1); } } void gma_crtc_prepare(struct drm_crtc *crtc ) { struct drm_crtc_helper_funcs const *crtc_funcs ; { crtc_funcs = (struct drm_crtc_helper_funcs const *)crtc->helper_private; (*(crtc_funcs->dpms))(crtc, 3); return; } } void gma_crtc_commit(struct drm_crtc *crtc ) { struct drm_crtc_helper_funcs const *crtc_funcs ; { crtc_funcs = (struct drm_crtc_helper_funcs const *)crtc->helper_private; (*(crtc_funcs->dpms))(crtc, 0); return; } } void gma_crtc_disable(struct drm_crtc *crtc ) { struct gtt_range *gt ; struct drm_crtc_helper_funcs const *crtc_funcs ; struct drm_framebuffer const *__mptr ; { crtc_funcs = (struct drm_crtc_helper_funcs const *)crtc->helper_private; (*(crtc_funcs->dpms))(crtc, 3); if ((unsigned long )(crtc->primary)->fb != (unsigned long )((struct drm_framebuffer *)0)) { __mptr = (struct drm_framebuffer const *)(crtc->primary)->fb; gt = ((struct psb_framebuffer *)__mptr)->gtt; psb_gtt_unpin(gt); } else { } return; } } void gma_crtc_destroy(struct drm_crtc *crtc ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; kfree((void const *)gma_crtc->crtc_state); drm_crtc_cleanup(crtc); kfree((void const *)gma_crtc); return; } } int gma_crtc_set_config(struct drm_mode_set *set ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; int ret ; int tmp ; { dev = (set->crtc)->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; if (dev_priv->rpm_enabled == 0) { tmp = drm_crtc_helper_set_config(set); return (tmp); } else { } pm_runtime_forbid(& (dev->pdev)->dev); ret = drm_crtc_helper_set_config(set); pm_runtime_allow(& (dev->pdev)->dev); return (ret); } } void gma_crtc_save(struct drm_crtc *crtc ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct psb_intel_crtc_state *crtc_state ; struct psb_offset const *map ; uint32_t palette_reg ; int i ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; crtc_state = gma_crtc->crtc_state; map = dev_priv->regmap + (unsigned long )gma_crtc->pipe; if ((unsigned long )crtc_state == (unsigned long )((struct psb_intel_crtc_state *)0)) { dev_err((struct device const *)dev->dev, "No CRTC state found\n"); return; } else { } crtc_state->saveDSPCNTR = REGISTER_READ(dev, map->cntr); crtc_state->savePIPECONF = REGISTER_READ(dev, map->conf); crtc_state->savePIPESRC = REGISTER_READ(dev, map->src); crtc_state->saveFP0 = REGISTER_READ(dev, map->fp0); crtc_state->saveFP1 = REGISTER_READ(dev, map->fp1); crtc_state->saveDPLL = REGISTER_READ(dev, map->dpll); crtc_state->saveHTOTAL = REGISTER_READ(dev, map->htotal); crtc_state->saveHBLANK = REGISTER_READ(dev, map->hblank); crtc_state->saveHSYNC = REGISTER_READ(dev, map->hsync); crtc_state->saveVTOTAL = REGISTER_READ(dev, map->vtotal); crtc_state->saveVBLANK = REGISTER_READ(dev, map->vblank); crtc_state->saveVSYNC = REGISTER_READ(dev, map->vsync); crtc_state->saveDSPSTRIDE = REGISTER_READ(dev, map->stride); crtc_state->saveDSPSIZE = REGISTER_READ(dev, map->size); crtc_state->saveDSPPOS = REGISTER_READ(dev, map->pos); crtc_state->saveDSPBASE = REGISTER_READ(dev, map->base); palette_reg = map->palette; i = 0; goto ldv_41875; ldv_41874: crtc_state->savePalette[i] = REGISTER_READ(dev, (uint32_t )(i << 2) + palette_reg); i = i + 1; ldv_41875: ; if (i <= 255) { goto ldv_41874; } else { } return; } } void gma_crtc_restore(struct drm_crtc *crtc ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct psb_intel_crtc_state *crtc_state ; struct psb_offset const *map ; uint32_t palette_reg ; int i ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; crtc_state = gma_crtc->crtc_state; map = dev_priv->regmap + (unsigned long )gma_crtc->pipe; if ((unsigned long )crtc_state == (unsigned long )((struct psb_intel_crtc_state *)0)) { dev_err((struct device const *)dev->dev, "No crtc state\n"); return; } else { } if ((int )crtc_state->saveDPLL < 0) { REGISTER_WRITE(dev, map->dpll, crtc_state->saveDPLL & 2147483647U); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); } else { } REGISTER_WRITE(dev, map->fp0, crtc_state->saveFP0); REGISTER_READ(dev, map->fp0); REGISTER_WRITE(dev, map->fp1, crtc_state->saveFP1); REGISTER_READ(dev, map->fp1); REGISTER_WRITE(dev, map->dpll, crtc_state->saveDPLL); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); REGISTER_WRITE(dev, map->htotal, crtc_state->saveHTOTAL); REGISTER_WRITE(dev, map->hblank, crtc_state->saveHBLANK); REGISTER_WRITE(dev, map->hsync, crtc_state->saveHSYNC); REGISTER_WRITE(dev, map->vtotal, crtc_state->saveVTOTAL); REGISTER_WRITE(dev, map->vblank, crtc_state->saveVBLANK); REGISTER_WRITE(dev, map->vsync, crtc_state->saveVSYNC); REGISTER_WRITE(dev, map->stride, crtc_state->saveDSPSTRIDE); REGISTER_WRITE(dev, map->size, crtc_state->saveDSPSIZE); REGISTER_WRITE(dev, map->pos, crtc_state->saveDSPPOS); REGISTER_WRITE(dev, map->src, crtc_state->savePIPESRC); REGISTER_WRITE(dev, map->base, crtc_state->saveDSPBASE); REGISTER_WRITE(dev, map->conf, crtc_state->savePIPECONF); gma_wait_for_vblank(dev); REGISTER_WRITE(dev, map->cntr, crtc_state->saveDSPCNTR); REGISTER_WRITE(dev, map->base, crtc_state->saveDSPBASE); gma_wait_for_vblank(dev); palette_reg = map->palette; i = 0; goto ldv_41890; ldv_41889: REGISTER_WRITE(dev, (uint32_t )(i << 2) + palette_reg, crtc_state->savePalette[i]); i = i + 1; ldv_41890: ; if (i <= 255) { goto ldv_41889; } else { } return; } } void gma_encoder_prepare(struct drm_encoder *encoder ) { struct drm_encoder_helper_funcs const *encoder_funcs ; { encoder_funcs = (struct drm_encoder_helper_funcs const *)encoder->helper_private; (*(encoder_funcs->dpms))(encoder, 3); return; } } void gma_encoder_commit(struct drm_encoder *encoder ) { struct drm_encoder_helper_funcs const *encoder_funcs ; { encoder_funcs = (struct drm_encoder_helper_funcs const *)encoder->helper_private; (*(encoder_funcs->dpms))(encoder, 0); return; } } void gma_encoder_destroy(struct drm_encoder *encoder ) { struct gma_encoder *intel_encoder ; struct drm_encoder const *__mptr ; { __mptr = (struct drm_encoder const *)encoder; intel_encoder = (struct gma_encoder *)__mptr; drm_encoder_cleanup(encoder); kfree((void const *)intel_encoder); return; } } struct drm_encoder *gma_best_encoder(struct drm_connector *connector ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; return (& gma_encoder->base); } } void gma_connector_attach_encoder(struct gma_connector *connector , struct gma_encoder *encoder ) { { connector->encoder = encoder; drm_mode_connector_attach_encoder(& connector->base, & encoder->base); return; } } bool gma_pll_is_valid(struct drm_crtc *crtc , struct gma_limit_t const *limit , struct gma_clock_t *clock ) { { if (clock->p1 < (int )limit->p1.min || (int )limit->p1.max < clock->p1) { return (0); } else { } if (clock->p < (int )limit->p.min || (int )limit->p.max < clock->p) { return (0); } else { } if (clock->m2 < (int )limit->m2.min || (int )limit->m2.max < clock->m2) { return (0); } else { } if (clock->m1 < (int )limit->m1.min || (int )limit->m1.max < clock->m1) { return (0); } else { } if (clock->m1 <= clock->m2 && clock->m1 != 0) { return (0); } else { } if (clock->m < (int )limit->m.min || (int )limit->m.max < clock->m) { return (0); } else { } if (clock->n < (int )limit->n.min || (int )limit->n.max < clock->n) { return (0); } else { } if (clock->vco < (int )limit->vco.min || (int )limit->vco.max < clock->vco) { return (0); } else { } if (clock->dot < (int )limit->dot.min || (int )limit->dot.max < clock->dot) { return (0); } else { } return (1); } } bool gma_find_best_pll(struct gma_limit_t const *limit , struct drm_crtc *crtc , int target , int refclk , struct gma_clock_t *best_clock ) { struct drm_device *dev ; struct gma_clock_funcs const *clock_funcs ; struct drm_crtc const *__mptr ; struct gma_clock_t clock ; int err ; uint32_t tmp ; bool tmp___0 ; uint32_t tmp___1 ; int this_err ; bool tmp___2 ; int tmp___3 ; long ret ; int __x___0 ; { dev = crtc->dev; __mptr = (struct drm_crtc const *)crtc; clock_funcs = ((struct gma_crtc *)__mptr)->clock_funcs; err = target; tmp___0 = gma_pipe_has_type(crtc, 4); if ((int )tmp___0) { tmp___1 = REGISTER_READ(dev, 397696U); if ((int )tmp___1 < 0) { tmp = REGISTER_READ(dev, 397696U); if ((tmp & 48U) == 48U) { clock.p2 = limit->p2.p2_fast; } else { clock.p2 = limit->p2.p2_slow; } } else { goto _L; } } else _L: /* CIL Label */ if ((int )limit->p2.dot_limit > target) { clock.p2 = limit->p2.p2_slow; } else { clock.p2 = limit->p2.p2_fast; } memset((void *)best_clock, 0, 36UL); clock.m1 = limit->m1.min; goto ldv_41948; ldv_41947: clock.m2 = limit->m2.min; goto ldv_41945; ldv_41944: clock.n = limit->n.min; goto ldv_41942; ldv_41941: clock.p1 = limit->p1.min; goto ldv_41939; ldv_41938: (*(clock_funcs->clock))(refclk, & clock); tmp___2 = (*(clock_funcs->pll_is_valid))(crtc, limit, & clock); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { goto ldv_41933; } else { } __x___0 = clock.dot - target; ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); this_err = (int )ret; if (this_err < err) { *best_clock = clock; err = this_err; } else { } ldv_41933: clock.p1 = clock.p1 + 1; ldv_41939: ; if (clock.p1 <= (int )limit->p1.max) { goto ldv_41938; } else { } clock.n = clock.n + 1; ldv_41942: ; if (clock.n <= (int )limit->n.max) { goto ldv_41941; } else { } clock.m2 = clock.m2 + 1; ldv_41945: ; if ((clock.m2 < clock.m1 || clock.m1 == 0) && clock.m2 <= (int )limit->m2.max) { goto ldv_41944; } else { } clock.m1 = clock.m1 + 1; ldv_41948: ; if (clock.m1 <= (int )limit->m1.max) { goto ldv_41947; } else { } return (err != target); } } bool ldv_queue_work_on_173(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_174(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_175(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_176(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_177(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_187(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_189(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_188(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_191(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_190(struct workqueue_struct *ldv_func_arg1 ) ; void gma_get_core_freq(struct drm_device *dev ) { uint32_t clock ; struct pci_dev *pci_root ; struct pci_dev *tmp ; struct drm_psb_private *dev_priv ; { tmp = pci_get_bus_and_slot(0U, 0U); pci_root = tmp; dev_priv = (struct drm_psb_private *)dev->dev_private; pci_write_config_dword((struct pci_dev const *)pci_root, 208, 3489989376U); pci_read_config_dword((struct pci_dev const *)pci_root, 212, & clock); pci_dev_put(pci_root); switch (clock & 7U) { case 0U: dev_priv->core_freq = 100U; goto ldv_41523; case 1U: dev_priv->core_freq = 133U; goto ldv_41523; case 2U: dev_priv->core_freq = 150U; goto ldv_41523; case 3U: dev_priv->core_freq = 178U; goto ldv_41523; case 4U: dev_priv->core_freq = 200U; goto ldv_41523; case 5U: ; case 6U: ; case 7U: dev_priv->core_freq = 266U; goto ldv_41523; default: dev_priv->core_freq = 0U; } ldv_41523: ; return; } } bool ldv_queue_work_on_187(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_188(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_189(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_190(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_191(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static int ffs(int x ) { int r ; { __asm__ ("bsfl %1,%0": "=r" (r): "rm" (x), "0" (-1)); return (r + 1); } } bool ldv_queue_work_on_201(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_203(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_202(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_205(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_204(struct workqueue_struct *ldv_func_arg1 ) ; extern void drm_mode_set_crtcinfo(struct drm_display_mode * , int ) ; extern int drm_mode_crtc_set_gamma_size(struct drm_crtc * , int ) ; extern int drm_crtc_init(struct drm_device * , struct drm_crtc * , struct drm_crtc_funcs const * ) ; __inline static void drm_crtc_helper_add(struct drm_crtc *crtc , struct drm_crtc_helper_funcs const *funcs ) { { crtc->helper_private = (void const *)funcs; return; } } struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev , struct drm_crtc *crtc ) ; struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev , int pipe ) ; struct drm_crtc_helper_funcs const psb_intel_helper_funcs ; struct drm_crtc_funcs const psb_intel_crtc_funcs ; static struct gma_limit_t const psb_intel_limits[2U] = { {{20000, 400000}, {1400000, 2800000}, {1, 6}, {70, 120}, {8, 18}, {3, 7}, {5, 80}, {1, 8}, {200000, 10, 5}, & gma_find_best_pll}, {{20000, 400000}, {1400000, 2800000}, {1, 6}, {70, 120}, {8, 18}, {3, 7}, {7, 98}, {1, 8}, {112000, 14, 7}, & gma_find_best_pll}}; static struct gma_limit_t const *psb_intel_limit(struct drm_crtc *crtc , int refclk ) { struct gma_limit_t const *limit ; bool tmp ; { tmp = gma_pipe_has_type(crtc, 4); if ((int )tmp) { limit = (struct gma_limit_t const *)(& psb_intel_limits) + 1UL; } else { limit = (struct gma_limit_t const *)(& psb_intel_limits); } return (limit); } } static void psb_intel_clock(int refclk , struct gma_clock_t *clock ) { { clock->m = (clock->m1 * 5 + 10) + (clock->m2 + 2); clock->p = clock->p1 * clock->p2; clock->vco = (clock->m * refclk) / (clock->n + 2); clock->dot = clock->vco / clock->p; return; } } static int psb_intel_panel_fitter_pipe(struct drm_device *dev ) { u32 pfit_control ; { pfit_control = REGISTER_READ(dev, 397872U); if ((int )pfit_control >= 0) { return (-1); } else { } return (1); } } static int psb_intel_crtc_mode_set(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode , int x , int y , struct drm_framebuffer *old_fb ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct drm_crtc_helper_funcs const *crtc_funcs ; int pipe ; struct psb_offset const *map ; int refclk ; struct gma_clock_t clock ; u32 dpll ; u32 fp ; u32 dspcntr ; u32 pipeconf ; bool ok ; bool is_sdvo ; bool is_lvds ; bool is_tv ; struct drm_mode_config *mode_config ; struct drm_connector *connector ; struct gma_limit_t const *limit ; struct list_head const *__mptr___0 ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct list_head const *__mptr___1 ; int sdvo_pixel_multiply ; int tmp___0 ; u32 lvds ; uint32_t tmp___1 ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; crtc_funcs = (struct drm_crtc_helper_funcs const *)crtc->helper_private; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; dpll = 0U; fp = 0U; is_sdvo = 0; is_lvds = 0; is_tv = 0; mode_config = & dev->mode_config; if ((unsigned long )(crtc->primary)->fb == (unsigned long )((struct drm_framebuffer *)0)) { (*(crtc_funcs->mode_set_base))(crtc, x, y, old_fb); return (0); } else { } __mptr___0 = (struct list_head const *)mode_config->connector_list.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; goto ldv_41872; ldv_41871: tmp = gma_attached_encoder(connector); gma_encoder = tmp; if ((unsigned long )connector->encoder == (unsigned long )((struct drm_encoder *)0) || (unsigned long )(connector->encoder)->crtc != (unsigned long )crtc) { goto ldv_41866; } else { } switch (gma_encoder->type) { case 4: is_lvds = 1; goto ldv_41868; case 3: is_sdvo = 1; goto ldv_41868; case 5: is_tv = 1; goto ldv_41868; } ldv_41868: ; ldv_41866: __mptr___1 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___1 + 0xffffffffffffffe8UL; ldv_41872: ; if ((unsigned long )(& connector->head) != (unsigned long )(& mode_config->connector_list)) { goto ldv_41871; } else { } refclk = 96000; limit = (*((gma_crtc->clock_funcs)->limit))(crtc, refclk); ok = (*(limit->find_pll))(limit, crtc, adjusted_mode->clock, refclk, & clock); if (! ok) { drm_err("Couldn\'t find PLL settings for mode! target: %d, actual: %d", adjusted_mode->clock, clock.dot); return (0); } else { } fp = (u32 )(((clock.n << 16) | (clock.m1 << 8)) | clock.m2); dpll = 268435456U; if ((int )is_lvds) { dpll = dpll | 134217728U; dpll = dpll | 1073741824U; } else { dpll = dpll | 67108864U; } if ((int )is_sdvo) { sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; dpll = dpll | 1073741824U; dpll = (u32 )((sdvo_pixel_multiply + -1) << 4) | dpll; } else { } dpll = (u32 )((1 << (clock.p1 + -1)) << 16) | dpll; switch (clock.p2) { case 5: dpll = dpll | 16777216U; goto ldv_41876; case 7: dpll = dpll | 16777216U; goto ldv_41876; case 10: dpll = dpll; goto ldv_41876; case 14: dpll = dpll; goto ldv_41876; } ldv_41876: ; if ((int )is_tv) { dpll = dpll | 3U; } else { } dpll = dpll; pipeconf = REGISTER_READ(dev, map->conf); dspcntr = 1073741824U; if (pipe == 0) { dspcntr = dspcntr; } else { dspcntr = dspcntr | 16777216U; } dspcntr = dspcntr | 2147483648U; pipeconf = pipeconf | 2147483648U; dpll = dpll | 2147483648U; tmp___0 = psb_intel_panel_fitter_pipe(dev); if (tmp___0 == pipe) { REGISTER_WRITE(dev, 397872U, 0U); } else { } drm_mode_debug_printmodeline((struct drm_display_mode const *)mode); if ((int )dpll < 0) { REGISTER_WRITE(dev, map->fp0, fp); REGISTER_WRITE(dev, map->dpll, dpll & 2147483647U); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); } else { } if ((int )is_lvds) { tmp___1 = REGISTER_READ(dev, 397696U); lvds = tmp___1; lvds = lvds & 3221225471U; if (pipe == 1) { lvds = lvds | 1073741824U; } else { } lvds = lvds | 2147484416U; lvds = lvds & 4294967235U; if (clock.p2 == 7) { lvds = lvds | 60U; } else { } REGISTER_WRITE(dev, 397696U, lvds); REGISTER_READ(dev, 397696U); } else { } REGISTER_WRITE(dev, map->fp0, fp); REGISTER_WRITE(dev, map->dpll, dpll); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); REGISTER_WRITE(dev, map->dpll, dpll); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); REGISTER_WRITE(dev, map->htotal, (uint32_t )((adjusted_mode->crtc_hdisplay + -1) | ((adjusted_mode->crtc_htotal + -1) << 16))); REGISTER_WRITE(dev, map->hblank, (uint32_t )((adjusted_mode->crtc_hblank_start + -1) | ((adjusted_mode->crtc_hblank_end + -1) << 16))); REGISTER_WRITE(dev, map->hsync, (uint32_t )((adjusted_mode->crtc_hsync_start + -1) | ((adjusted_mode->crtc_hsync_end + -1) << 16))); REGISTER_WRITE(dev, map->vtotal, (uint32_t )((adjusted_mode->crtc_vdisplay + -1) | ((adjusted_mode->crtc_vtotal + -1) << 16))); REGISTER_WRITE(dev, map->vblank, (uint32_t )((adjusted_mode->crtc_vblank_start + -1) | ((adjusted_mode->crtc_vblank_end + -1) << 16))); REGISTER_WRITE(dev, map->vsync, (uint32_t )((adjusted_mode->crtc_vsync_start + -1) | ((adjusted_mode->crtc_vsync_end + -1) << 16))); REGISTER_WRITE(dev, map->size, (uint32_t )(((mode->vdisplay + -1) << 16) | (mode->hdisplay + -1))); REGISTER_WRITE(dev, map->pos, 0U); REGISTER_WRITE(dev, map->src, (uint32_t )(((mode->hdisplay + -1) << 16) | (mode->vdisplay + -1))); REGISTER_WRITE(dev, map->conf, pipeconf); REGISTER_READ(dev, map->conf); gma_wait_for_vblank(dev); REGISTER_WRITE(dev, map->cntr, dspcntr); (*(crtc_funcs->mode_set_base))(crtc, x, y, old_fb); gma_wait_for_vblank(dev); return (0); } } static int psb_intel_crtc_clock_get(struct drm_device *dev , struct drm_crtc *crtc ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct drm_psb_private *dev_priv ; int pipe ; struct psb_offset const *map ; u32 dpll ; u32 fp ; struct gma_clock_t clock ; bool is_lvds ; struct psb_pipe *p ; uint32_t tmp ; int tmp___0 ; bool tmp___1 ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; dev_priv = (struct drm_psb_private *)dev->dev_private; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; p = (struct psb_pipe *)(& dev_priv->regs.pipe) + (unsigned long )pipe; tmp___1 = gma_power_begin(dev, 0); if ((int )tmp___1) { dpll = REGISTER_READ(dev, map->dpll); if ((dpll & 256U) == 0U) { fp = REGISTER_READ(dev, map->fp0); } else { fp = REGISTER_READ(dev, map->fp1); } if (pipe == 1) { tmp = REGISTER_READ(dev, 397696U); if ((int )tmp < 0) { tmp___0 = 1; } else { tmp___0 = 0; } } else { tmp___0 = 0; } is_lvds = (bool )tmp___0; gma_power_end(dev); } else { dpll = p->dpll; if ((dpll & 256U) == 0U) { fp = p->fp0; } else { fp = p->fp1; } is_lvds = (bool )(pipe == 1 && (int )dev_priv->regs.__annonCompField80.psb.saveLVDS < 0); } clock.m1 = (int )((fp & 16128U) >> 8); clock.m2 = (int )fp & 63; clock.n = (int )((fp & 4128768U) >> 16); if ((int )is_lvds) { clock.p1 = ffs((int )((dpll & 4128768U) >> 16)); clock.p2 = 14; if ((dpll & 24576U) == 24576U) { psb_intel_clock(66000, & clock); } else { psb_intel_clock(48000, & clock); } } else { if ((dpll & 2097152U) != 0U) { clock.p1 = 2; } else { clock.p1 = (int )(((dpll & 2031616U) >> 16) + 2U); } if ((dpll & 8388608U) != 0U) { clock.p2 = 4; } else { clock.p2 = 2; } psb_intel_clock(48000, & clock); } return (clock.dot); } } struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev , struct drm_crtc *crtc ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; struct drm_display_mode *mode ; int htot ; int hsync ; int vtot ; int vsync ; struct drm_psb_private *dev_priv ; struct psb_pipe *p ; struct psb_offset const *map ; uint32_t tmp ; uint32_t tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; bool tmp___3 ; void *tmp___4 ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; dev_priv = (struct drm_psb_private *)dev->dev_private; p = (struct psb_pipe *)(& dev_priv->regs.pipe) + (unsigned long )pipe; map = dev_priv->regmap + (unsigned long )pipe; tmp___3 = gma_power_begin(dev, 0); if ((int )tmp___3) { tmp = REGISTER_READ(dev, map->htotal); htot = (int )tmp; tmp___0 = REGISTER_READ(dev, map->hsync); hsync = (int )tmp___0; tmp___1 = REGISTER_READ(dev, map->vtotal); vtot = (int )tmp___1; tmp___2 = REGISTER_READ(dev, map->vsync); vsync = (int )tmp___2; gma_power_end(dev); } else { htot = (int )p->htotal; hsync = (int )p->hsync; vtot = (int )p->vtotal; vsync = (int )p->vsync; } tmp___4 = kzalloc(208UL, 208U); mode = (struct drm_display_mode *)tmp___4; if ((unsigned long )mode == (unsigned long )((struct drm_display_mode *)0)) { return ((struct drm_display_mode *)0); } else { } mode->clock = psb_intel_crtc_clock_get(dev, crtc); mode->hdisplay = (htot & 65535) + 1; mode->htotal = (int )(((unsigned int )htot >> 16) + 1U); mode->hsync_start = (hsync & 65535) + 1; mode->hsync_end = (int )(((unsigned int )hsync >> 16) + 1U); mode->vdisplay = (vtot & 65535) + 1; mode->vtotal = (int )(((unsigned int )vtot >> 16) + 1U); mode->vsync_start = (vsync & 65535) + 1; mode->vsync_end = (int )(((unsigned int )vsync >> 16) + 1U); drm_mode_set_name(mode); drm_mode_set_crtcinfo(mode, 0); return (mode); } } struct drm_crtc_helper_funcs const psb_intel_helper_funcs = {& gma_crtc_dpms, & gma_crtc_prepare, & gma_crtc_commit, & gma_crtc_mode_fixup, & psb_intel_crtc_mode_set, 0, & gma_pipe_set_base, 0, 0, & gma_crtc_disable, 0, 0, 0, 0}; struct drm_crtc_funcs const psb_intel_crtc_funcs = {& gma_crtc_save, & gma_crtc_restore, 0, & gma_crtc_cursor_set, 0, & gma_crtc_cursor_move, & gma_crtc_gamma_set, & gma_crtc_destroy, & gma_crtc_set_config, 0, 0, 0, 0, 0, 0}; struct gma_clock_funcs const psb_clock_funcs = {& psb_intel_clock, & psb_intel_limit, & gma_pll_is_valid}; static void psb_intel_cursor_init(struct drm_device *dev , struct gma_crtc *gma_crtc ) { struct drm_psb_private *dev_priv ; u32 control[3U] ; u32 base[3U] ; struct gtt_range *cursor_gt ; { dev_priv = (struct drm_psb_private *)dev->dev_private; control[0] = 458880U; control[1] = 458944U; control[2] = 458976U; base[0] = 458884U; base[1] = 458948U; base[2] = 458980U; if ((int )(dev_priv->ops)->cursor_needs_phys != 0) { cursor_gt = psb_gtt_alloc_range(dev, 16384, "cursor", 1, 4096U); if ((unsigned long )cursor_gt == (unsigned long )((struct gtt_range *)0)) { gma_crtc->cursor_gt = (struct gtt_range *)0; goto out; } else { } gma_crtc->cursor_gt = cursor_gt; gma_crtc->cursor_addr = dev_priv->stolen_base + cursor_gt->offset; } else { gma_crtc->cursor_gt = (struct gtt_range *)0; } out: REGISTER_WRITE(dev, control[gma_crtc->pipe], 0U); REGISTER_WRITE(dev, base[gma_crtc->pipe], 0U); return; } } void psb_intel_crtc_init(struct drm_device *dev , int pipe , struct psb_intel_mode_device *mode_dev ) { struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; int i ; uint16_t *r_base ; uint16_t *g_base ; uint16_t *b_base ; void *tmp ; void *tmp___0 ; long tmp___1 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = kzalloc(2752UL, 208U); gma_crtc = (struct gma_crtc *)tmp; if ((unsigned long )gma_crtc == (unsigned long )((struct gma_crtc *)0)) { return; } else { } tmp___0 = kzalloc(1088UL, 208U); gma_crtc->crtc_state = (struct psb_intel_crtc_state *)tmp___0; if ((unsigned long )gma_crtc->crtc_state == (unsigned long )((struct psb_intel_crtc_state *)0)) { dev_err((struct device const *)dev->dev, "Crtc state error: No memory\n"); kfree((void const *)gma_crtc); return; } else { } drm_crtc_init(dev, & gma_crtc->base, (dev_priv->ops)->crtc_funcs); gma_crtc->clock_funcs = (dev_priv->ops)->clock_funcs; drm_mode_crtc_set_gamma_size(& gma_crtc->base, 256); gma_crtc->pipe = pipe; gma_crtc->plane = pipe; r_base = gma_crtc->base.gamma_store; g_base = r_base + 256UL; b_base = g_base + 256UL; i = 0; goto ldv_41936; ldv_41935: gma_crtc->lut_r[i] = (u8 )i; gma_crtc->lut_g[i] = (u8 )i; gma_crtc->lut_b[i] = (u8 )i; *(r_base + (unsigned long )i) = (int )((uint16_t )i) << 8U; *(g_base + (unsigned long )i) = (int )((uint16_t )i) << 8U; *(b_base + (unsigned long )i) = (int )((uint16_t )i) << 8U; gma_crtc->lut_adj[i] = 0U; i = i + 1; ldv_41936: ; if (i <= 255) { goto ldv_41935; } else { } gma_crtc->mode_dev = mode_dev; gma_crtc->cursor_addr = 0U; drm_crtc_helper_add(& gma_crtc->base, (dev_priv->ops)->crtc_helper); gma_crtc->mode_set.crtc = & gma_crtc->base; tmp___1 = ldv__builtin_expect((long )((unsigned int )pipe > 2U || (unsigned long )dev_priv->plane_to_crtc_mapping[gma_crtc->plane] != (unsigned long )((struct drm_crtc *)0)), 0L); if (tmp___1 != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_intel_display.c"), "i" (548), "i" (12UL)); ldv_41940: ; goto ldv_41940; } else { } dev_priv->plane_to_crtc_mapping[gma_crtc->plane] = & gma_crtc->base; dev_priv->pipe_to_crtc_mapping[gma_crtc->pipe] = & gma_crtc->base; gma_crtc->mode_set.connectors = (struct drm_connector **)gma_crtc + 1U; gma_crtc->mode_set.num_connectors = 0UL; psb_intel_cursor_init(dev, gma_crtc); gma_crtc->active = 1; return; } } struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev , int pipe ) { struct drm_crtc *crtc ; struct list_head const *__mptr ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr___0 ; struct list_head const *__mptr___1 ; { crtc = (struct drm_crtc *)0; __mptr = (struct list_head const *)dev->mode_config.crtc_list.next; crtc = (struct drm_crtc *)__mptr + 0xfffffffffffffff0UL; goto ldv_41955; ldv_41954: __mptr___0 = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr___0; if (gma_crtc->pipe == pipe) { goto ldv_41953; } else { } __mptr___1 = (struct list_head const *)crtc->head.next; crtc = (struct drm_crtc *)__mptr___1 + 0xfffffffffffffff0UL; ldv_41955: ; if ((unsigned long )(& crtc->head) != (unsigned long )(& dev->mode_config.crtc_list)) { goto ldv_41954; } else { } ldv_41953: ; return (crtc); } } int gma_connector_clones(struct drm_device *dev , int type_mask ) { int index_mask ; struct drm_connector *connector ; int entry ; struct list_head const *__mptr ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct list_head const *__mptr___0 ; { index_mask = 0; entry = 0; __mptr = (struct list_head const *)dev->mode_config.connector_list.next; connector = (struct drm_connector *)__mptr + 0xffffffffffffffe8UL; goto ldv_41969; ldv_41968: tmp = gma_attached_encoder(connector); gma_encoder = tmp; if ((type_mask >> gma_encoder->type) & 1) { index_mask = (1 << entry) | index_mask; } else { } entry = entry + 1; __mptr___0 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; ldv_41969: ; if ((unsigned long )(& connector->head) != (unsigned long )(& dev->mode_config.connector_list)) { goto ldv_41968; } else { } return (index_mask); } } extern int ldv_release_47(void) ; extern int ldv_connect_47(void) ; extern int ldv_probe_46(void) ; extern int ldv_bind_47(void) ; void ldv_initialize_drm_crtc_funcs_46(void) { void *tmp ; { tmp = ldv_init_zalloc(1160UL); psb_intel_crtc_funcs_group0 = (struct drm_crtc *)tmp; return; } } void ldv_initialize_gma_clock_funcs_45(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(1160UL); psb_clock_funcs_group0 = (struct drm_crtc *)tmp; tmp___0 = ldv_init_zalloc(36UL); psb_clock_funcs_group1 = (struct gma_clock_t *)tmp___0; return; } } void ldv_initialize_drm_crtc_helper_funcs_47(void) { void *tmp ; void *tmp___0 ; void *tmp___1 ; { tmp = ldv_init_zalloc(1160UL); psb_intel_helper_funcs_group0 = (struct drm_crtc *)tmp; tmp___0 = ldv_init_zalloc(168UL); psb_intel_helper_funcs_group1 = (struct drm_framebuffer *)tmp___0; tmp___1 = ldv_init_zalloc(208UL); psb_intel_helper_funcs_group2 = (struct drm_display_mode *)tmp___1; return; } } void ldv_main_exported_46(void) { uint32_t ldvarg125 ; int ldvarg130 ; struct drm_mode_set *ldvarg120 ; void *tmp ; uint32_t ldvarg129 ; u16 *ldvarg123 ; void *tmp___0 ; uint32_t ldvarg126 ; struct drm_file *ldvarg128 ; void *tmp___1 ; u16 *ldvarg122 ; void *tmp___2 ; u16 *ldvarg124 ; void *tmp___3 ; uint32_t ldvarg127 ; int ldvarg131 ; uint32_t ldvarg121 ; int tmp___4 ; { tmp = ldv_init_zalloc(48UL); ldvarg120 = (struct drm_mode_set *)tmp; tmp___0 = ldv_init_zalloc(2UL); ldvarg123 = (u16 *)tmp___0; tmp___1 = ldv_init_zalloc(744UL); ldvarg128 = (struct drm_file *)tmp___1; tmp___2 = ldv_init_zalloc(2UL); ldvarg122 = (u16 *)tmp___2; tmp___3 = ldv_init_zalloc(2UL); ldvarg124 = (u16 *)tmp___3; ldv_memset((void *)(& ldvarg125), 0, 4UL); ldv_memset((void *)(& ldvarg130), 0, 4UL); ldv_memset((void *)(& ldvarg129), 0, 4UL); ldv_memset((void *)(& ldvarg126), 0, 4UL); ldv_memset((void *)(& ldvarg127), 0, 4UL); ldv_memset((void *)(& ldvarg131), 0, 4UL); ldv_memset((void *)(& ldvarg121), 0, 4UL); tmp___4 = __VERIFIER_nondet_int(); switch (tmp___4) { case 0: ; if (ldv_state_variable_46 == 1) { gma_crtc_cursor_move(psb_intel_crtc_funcs_group0, ldvarg131, ldvarg130); ldv_state_variable_46 = 1; } else { } if (ldv_state_variable_46 == 2) { gma_crtc_cursor_move(psb_intel_crtc_funcs_group0, ldvarg131, ldvarg130); ldv_state_variable_46 = 2; } else { } goto ldv_42004; case 1: ; if (ldv_state_variable_46 == 1) { gma_crtc_cursor_set(psb_intel_crtc_funcs_group0, ldvarg128, ldvarg127, ldvarg126, ldvarg129); ldv_state_variable_46 = 1; } else { } if (ldv_state_variable_46 == 2) { gma_crtc_cursor_set(psb_intel_crtc_funcs_group0, ldvarg128, ldvarg127, ldvarg126, ldvarg129); ldv_state_variable_46 = 2; } else { } goto ldv_42004; case 2: ; if (ldv_state_variable_46 == 2) { gma_crtc_destroy(psb_intel_crtc_funcs_group0); ldv_state_variable_46 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42004; case 3: ; if (ldv_state_variable_46 == 1) { gma_crtc_save(psb_intel_crtc_funcs_group0); ldv_state_variable_46 = 1; } else { } if (ldv_state_variable_46 == 2) { gma_crtc_save(psb_intel_crtc_funcs_group0); ldv_state_variable_46 = 2; } else { } goto ldv_42004; case 4: ; if (ldv_state_variable_46 == 1) { gma_crtc_gamma_set(psb_intel_crtc_funcs_group0, ldvarg124, ldvarg123, ldvarg122, ldvarg125, ldvarg121); ldv_state_variable_46 = 1; } else { } if (ldv_state_variable_46 == 2) { gma_crtc_gamma_set(psb_intel_crtc_funcs_group0, ldvarg124, ldvarg123, ldvarg122, ldvarg125, ldvarg121); ldv_state_variable_46 = 2; } else { } goto ldv_42004; case 5: ; if (ldv_state_variable_46 == 1) { gma_crtc_restore(psb_intel_crtc_funcs_group0); ldv_state_variable_46 = 1; } else { } if (ldv_state_variable_46 == 2) { gma_crtc_restore(psb_intel_crtc_funcs_group0); ldv_state_variable_46 = 2; } else { } goto ldv_42004; case 6: ; if (ldv_state_variable_46 == 1) { gma_crtc_set_config(ldvarg120); ldv_state_variable_46 = 1; } else { } if (ldv_state_variable_46 == 2) { gma_crtc_set_config(ldvarg120); ldv_state_variable_46 = 2; } else { } goto ldv_42004; case 7: ; if (ldv_state_variable_46 == 1) { ldv_probe_46(); ldv_state_variable_46 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42004; default: ldv_stop(); } ldv_42004: ; return; } } void ldv_main_exported_45(void) { struct gma_limit_t *ldvarg210 ; void *tmp ; int ldvarg208 ; int ldvarg209 ; int tmp___0 ; { tmp = ldv_init_zalloc(88UL); ldvarg210 = (struct gma_limit_t *)tmp; ldv_memset((void *)(& ldvarg208), 0, 4UL); ldv_memset((void *)(& ldvarg209), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_45 == 1) { gma_pll_is_valid(psb_clock_funcs_group0, (struct gma_limit_t const *)ldvarg210, psb_clock_funcs_group1); ldv_state_variable_45 = 1; } else { } goto ldv_42020; case 1: ; if (ldv_state_variable_45 == 1) { psb_intel_clock(ldvarg209, psb_clock_funcs_group1); ldv_state_variable_45 = 1; } else { } goto ldv_42020; case 2: ; if (ldv_state_variable_45 == 1) { psb_intel_limit(psb_clock_funcs_group0, ldvarg208); ldv_state_variable_45 = 1; } else { } goto ldv_42020; default: ldv_stop(); } ldv_42020: ; return; } } void ldv_main_exported_47(void) { int ldvarg184 ; int ldvarg186 ; int ldvarg185 ; int ldvarg182 ; int ldvarg180 ; struct drm_display_mode *ldvarg181 ; void *tmp ; struct drm_display_mode *ldvarg183 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg181 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg183 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg184), 0, 4UL); ldv_memset((void *)(& ldvarg186), 0, 4UL); ldv_memset((void *)(& ldvarg185), 0, 4UL); ldv_memset((void *)(& ldvarg182), 0, 4UL); ldv_memset((void *)(& ldvarg180), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_47 == 1) { gma_pipe_set_base(psb_intel_helper_funcs_group0, ldvarg186, ldvarg185, psb_intel_helper_funcs_group1); ldv_state_variable_47 = 1; } else { } if (ldv_state_variable_47 == 3) { gma_pipe_set_base(psb_intel_helper_funcs_group0, ldvarg186, ldvarg185, psb_intel_helper_funcs_group1); ldv_state_variable_47 = 3; } else { } if (ldv_state_variable_47 == 2) { gma_pipe_set_base(psb_intel_helper_funcs_group0, ldvarg186, ldvarg185, psb_intel_helper_funcs_group1); ldv_state_variable_47 = 2; } else { } goto ldv_42035; case 1: ; if (ldv_state_variable_47 == 1) { gma_crtc_dpms(psb_intel_helper_funcs_group0, ldvarg184); ldv_state_variable_47 = 1; } else { } if (ldv_state_variable_47 == 3) { gma_crtc_dpms(psb_intel_helper_funcs_group0, ldvarg184); ldv_state_variable_47 = 3; } else { } if (ldv_state_variable_47 == 2) { gma_crtc_dpms(psb_intel_helper_funcs_group0, ldvarg184); ldv_state_variable_47 = 2; } else { } goto ldv_42035; case 2: ; if (ldv_state_variable_47 == 1) { gma_crtc_mode_fixup(psb_intel_helper_funcs_group0, (struct drm_display_mode const *)ldvarg183, psb_intel_helper_funcs_group2); ldv_state_variable_47 = 1; } else { } if (ldv_state_variable_47 == 3) { gma_crtc_mode_fixup(psb_intel_helper_funcs_group0, (struct drm_display_mode const *)ldvarg183, psb_intel_helper_funcs_group2); ldv_state_variable_47 = 3; } else { } if (ldv_state_variable_47 == 2) { gma_crtc_mode_fixup(psb_intel_helper_funcs_group0, (struct drm_display_mode const *)ldvarg183, psb_intel_helper_funcs_group2); ldv_state_variable_47 = 2; } else { } goto ldv_42035; case 3: ; if (ldv_state_variable_47 == 1) { gma_crtc_commit(psb_intel_helper_funcs_group0); ldv_state_variable_47 = 1; } else { } if (ldv_state_variable_47 == 3) { gma_crtc_commit(psb_intel_helper_funcs_group0); ldv_state_variable_47 = 3; } else { } if (ldv_state_variable_47 == 2) { gma_crtc_commit(psb_intel_helper_funcs_group0); ldv_state_variable_47 = 2; } else { } goto ldv_42035; case 4: ; if (ldv_state_variable_47 == 1) { psb_intel_crtc_mode_set(psb_intel_helper_funcs_group0, psb_intel_helper_funcs_group2, ldvarg181, ldvarg180, ldvarg182, psb_intel_helper_funcs_group1); ldv_state_variable_47 = 1; } else { } if (ldv_state_variable_47 == 3) { psb_intel_crtc_mode_set(psb_intel_helper_funcs_group0, psb_intel_helper_funcs_group2, ldvarg181, ldvarg180, ldvarg182, psb_intel_helper_funcs_group1); ldv_state_variable_47 = 3; } else { } if (ldv_state_variable_47 == 2) { psb_intel_crtc_mode_set(psb_intel_helper_funcs_group0, psb_intel_helper_funcs_group2, ldvarg181, ldvarg180, ldvarg182, psb_intel_helper_funcs_group1); ldv_state_variable_47 = 2; } else { } goto ldv_42035; case 5: ; if (ldv_state_variable_47 == 3) { gma_crtc_disable(psb_intel_helper_funcs_group0); ldv_state_variable_47 = 2; } else { } goto ldv_42035; case 6: ; if (ldv_state_variable_47 == 1) { gma_crtc_prepare(psb_intel_helper_funcs_group0); ldv_state_variable_47 = 1; } else { } if (ldv_state_variable_47 == 3) { gma_crtc_prepare(psb_intel_helper_funcs_group0); ldv_state_variable_47 = 3; } else { } if (ldv_state_variable_47 == 2) { gma_crtc_prepare(psb_intel_helper_funcs_group0); ldv_state_variable_47 = 2; } else { } goto ldv_42035; case 7: ; if (ldv_state_variable_47 == 2) { ldv_release_47(); ldv_state_variable_47 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42035; case 8: ; if (ldv_state_variable_47 == 1) { ldv_bind_47(); ldv_state_variable_47 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42035; case 9: ; if (ldv_state_variable_47 == 2) { ldv_connect_47(); ldv_state_variable_47 = 3; } else { } goto ldv_42035; default: ldv_stop(); } ldv_42035: ; return; } } bool ldv_queue_work_on_201(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_202(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_203(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_204(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_205(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; extern int strcmp(char const * , char const * ) ; bool ldv_queue_work_on_215(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_217(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_216(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_219(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_218(struct workqueue_struct *ldv_func_arg1 ) ; extern void dev_printk(char const * , struct device const * , char const * , ...) ; extern void _dev_info(struct device const * , char const * , ...) ; extern int i2c_transfer(struct i2c_adapter * , struct i2c_msg * , int ) ; extern void drm_mode_probed_add(struct drm_connector * , struct drm_display_mode * ) ; extern struct drm_display_mode *drm_mode_duplicate(struct drm_device * , struct drm_display_mode const * ) ; extern int drm_connector_init(struct drm_device * , struct drm_connector * , struct drm_connector_funcs const * , int ) ; extern int drm_connector_register(struct drm_connector * ) ; extern void drm_connector_unregister(struct drm_connector * ) ; extern void drm_connector_cleanup(struct drm_connector * ) ; extern int drm_encoder_init(struct drm_device * , struct drm_encoder * , struct drm_encoder_funcs const * , int ) ; extern int drm_object_property_set_value(struct drm_mode_object * , struct drm_property * , uint64_t ) ; extern int drm_object_property_get_value(struct drm_mode_object * , struct drm_property * , uint64_t * ) ; extern void drm_object_attach_property(struct drm_mode_object * , struct drm_property * , uint64_t ) ; extern bool drm_crtc_helper_set_mode(struct drm_crtc * , struct drm_display_mode * , int , int , struct drm_framebuffer * ) ; extern void drm_helper_connector_dpms(struct drm_connector * , int ) ; __inline static void drm_encoder_helper_add(struct drm_encoder *encoder , struct drm_encoder_helper_funcs const *funcs ) { { encoder->helper_private = (void const *)funcs; return; } } __inline static void drm_connector_helper_add(struct drm_connector *connector , struct drm_connector_helper_funcs const *funcs ) { { connector->helper_private = (void const *)funcs; return; } } extern int drm_helper_probe_single_connector_modes(struct drm_connector * , uint32_t , uint32_t ) ; int psb_intel_ddc_get_modes(struct drm_connector *connector , struct i2c_adapter *adapter ) ; void psb_intel_lvds_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) ; void psb_intel_lvds_set_brightness(struct drm_device *dev , int level ) ; bool psb_intel_lvds_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) ; int psb_intel_lvds_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) ; int psb_intel_lvds_set_property(struct drm_connector *connector , struct drm_property *property , uint64_t value ) ; void psb_intel_lvds_destroy(struct drm_connector *connector ) ; struct drm_encoder_funcs const psb_intel_lvds_enc_funcs ; struct drm_connector_helper_funcs const psb_intel_lvds_connector_helper_funcs ; struct drm_connector_funcs const psb_intel_lvds_connector_funcs ; static u32 psb_intel_lvds_get_max_backlight(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 ret ; bool tmp ; uint32_t tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = gma_power_begin(dev, 0); if ((int )tmp) { ret = REGISTER_READ(dev, 397908U); gma_power_end(dev); } else { ret = dev_priv->regs.saveBLC_PWM_CTL; } ret = ret >> 17; ret = ret * 2U; if (ret == 0U) { tmp___0 = REGISTER_READ(dev, 397908U); dev_err((struct device const *)dev->dev, "BL bug: Reg %08x save %08X\n", tmp___0, dev_priv->regs.saveBLC_PWM_CTL); } else { } return (ret); } } static int psb_lvds_i2c_set_brightness(struct drm_device *dev , unsigned int level ) { struct drm_psb_private *dev_priv ; struct psb_intel_i2c_chan *lvds_i2c_bus ; u8 out_buf[2U] ; unsigned int blc_i2c_brightness ; struct i2c_msg msgs[1U] ; struct _ddebug descriptor ; long tmp ; int tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; lvds_i2c_bus = dev_priv->lvds_i2c_bus; msgs[0].addr = (unsigned short )lvds_i2c_bus->slave_addr; msgs[0].flags = 0U; msgs[0].len = 2U; msgs[0].buf = (__u8 *)(& out_buf); blc_i2c_brightness = (level * 255U) / 100U & 255U; if ((unsigned int )*((unsigned char *)dev_priv->lvds_bl + 0UL) != 0U) { blc_i2c_brightness = 255U - blc_i2c_brightness; } else { } out_buf[0] = (dev_priv->lvds_bl)->brightnesscmd; out_buf[1] = (unsigned char )blc_i2c_brightness; tmp___0 = i2c_transfer(& lvds_i2c_bus->adapter, (struct i2c_msg *)(& msgs), 1); if (tmp___0 == 1) { descriptor.modname = "gma500_gfx"; descriptor.function = "psb_lvds_i2c_set_brightness"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_intel_lvds.c"; descriptor.format = "I2C set brightness.(command, value) (%d, %d)\n"; descriptor.lineno = 131U; descriptor.flags = 0U; tmp = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "I2C set brightness.(command, value) (%d, %d)\n", (int )(dev_priv->lvds_bl)->brightnesscmd, blc_i2c_brightness); } else { } return (0); } else { } dev_err((struct device const *)dev->dev, "I2C transfer error\n"); return (-1); } } static int psb_lvds_pwm_set_brightness(struct drm_device *dev , int level ) { struct drm_psb_private *dev_priv ; u32 max_pwm_blc ; u32 blc_pwm_duty_cycle ; long tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; max_pwm_blc = psb_intel_lvds_get_max_backlight(dev); tmp = ldv__builtin_expect(max_pwm_blc == 0U, 0L); if (tmp != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_intel_lvds.c"), "i" (151), "i" (12UL)); ldv_41578: ; goto ldv_41578; } else { } blc_pwm_duty_cycle = ((u32 )level * max_pwm_blc) / 100U; if ((unsigned int )*((unsigned char *)dev_priv->lvds_bl + 0UL) != 0U) { blc_pwm_duty_cycle = max_pwm_blc - blc_pwm_duty_cycle; } else { } blc_pwm_duty_cycle = blc_pwm_duty_cycle & 65534U; REGISTER_WRITE(dev, 397908U, (max_pwm_blc << 16) | blc_pwm_duty_cycle); _dev_info((struct device const *)dev->dev, "Backlight lvds set brightness %08x\n", (max_pwm_blc << 16) | blc_pwm_duty_cycle); return (0); } } void psb_intel_lvds_set_brightness(struct drm_device *dev , int level ) { struct drm_psb_private *dev_priv ; struct _ddebug descriptor ; long tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; descriptor.modname = "gma500_gfx"; descriptor.function = "psb_intel_lvds_set_brightness"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_intel_lvds.c"; descriptor.format = "backlight level is %d\n"; descriptor.lineno = 177U; descriptor.flags = 0U; tmp = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "backlight level is %d\n", level); } else { } if ((unsigned long )dev_priv->lvds_bl == (unsigned long )((struct bdb_lvds_backlight *)0)) { dev_err((struct device const *)dev->dev, "NO LVDS backlight info\n"); return; } else { } if ((unsigned int )*((unsigned char *)dev_priv->lvds_bl + 0UL) == 1U) { psb_lvds_i2c_set_brightness(dev, (unsigned int )level); } else { psb_lvds_pwm_set_brightness(dev, level); } return; } } static void psb_intel_lvds_set_backlight(struct drm_device *dev , int level ) { struct drm_psb_private *dev_priv ; u32 blc_pwm_ctl ; bool tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = gma_power_begin(dev, 0); if ((int )tmp) { blc_pwm_ctl = REGISTER_READ(dev, 397908U); blc_pwm_ctl = blc_pwm_ctl & 4294901760U; REGISTER_WRITE(dev, 397908U, blc_pwm_ctl | (u32 )level); dev_priv->regs.saveBLC_PWM_CTL = blc_pwm_ctl | (u32 )level; gma_power_end(dev); } else { blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL & 4294901760U; dev_priv->regs.saveBLC_PWM_CTL = blc_pwm_ctl | (u32 )level; } return; } } static void psb_intel_lvds_set_power(struct drm_device *dev , bool on ) { struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; u32 pp_status ; bool tmp ; int tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { dev_err((struct device const *)dev->dev, "set power, chip off!\n"); return; } else { } if ((int )on) { tmp___1 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___1 | 1U); ldv_41599: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status >= 0) { goto ldv_41599; } else { } psb_intel_lvds_set_backlight(dev, mode_dev->backlight_duty_cycle); } else { psb_intel_lvds_set_backlight(dev, 0); tmp___2 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___2 & 4294967294U); ldv_41601: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status < 0) { goto ldv_41601; } else { } } gma_power_end(dev); return; } } static void psb_intel_lvds_encoder_dpms(struct drm_encoder *encoder , int mode ) { struct drm_device *dev ; { dev = encoder->dev; if (mode == 0) { psb_intel_lvds_set_power(dev, 1); } else { psb_intel_lvds_set_power(dev, 0); } return; } } static void psb_intel_lvds_save(struct drm_connector *connector ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct psb_intel_lvds_priv *lvds_priv ; u32 tmp___0 ; struct _ddebug descriptor ; long tmp___1 ; { dev = connector->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = gma_attached_encoder(connector); gma_encoder = tmp; lvds_priv = (struct psb_intel_lvds_priv *)gma_encoder->dev_priv; lvds_priv->savePP_ON = REGISTER_READ(dev, 397832U); lvds_priv->savePP_OFF = REGISTER_READ(dev, 397836U); lvds_priv->saveLVDS = REGISTER_READ(dev, 397696U); lvds_priv->savePP_CONTROL = REGISTER_READ(dev, 397828U); lvds_priv->savePP_CYCLE = REGISTER_READ(dev, 397840U); lvds_priv->saveBLC_PWM_CTL = REGISTER_READ(dev, 397908U); lvds_priv->savePFIT_CONTROL = REGISTER_READ(dev, 397872U); lvds_priv->savePFIT_PGM_RATIOS = REGISTER_READ(dev, 397876U); dev_priv->backlight_duty_cycle = (int )dev_priv->regs.saveBLC_PWM_CTL & 65535; if (dev_priv->backlight_duty_cycle == 0) { tmp___0 = psb_intel_lvds_get_max_backlight(dev); dev_priv->backlight_duty_cycle = (int )tmp___0; } else { } descriptor.modname = "gma500_gfx"; descriptor.function = "psb_intel_lvds_save"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_intel_lvds.c"; descriptor.format = "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n"; descriptor.lineno = 302U; descriptor.flags = 0U; tmp___1 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___1 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n", lvds_priv->savePP_ON, lvds_priv->savePP_OFF, lvds_priv->saveLVDS, lvds_priv->savePP_CONTROL, lvds_priv->savePP_CYCLE, lvds_priv->saveBLC_PWM_CTL); } else { } return; } } static void psb_intel_lvds_restore(struct drm_connector *connector ) { struct drm_device *dev ; u32 pp_status ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct psb_intel_lvds_priv *lvds_priv ; struct _ddebug descriptor ; long tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; { dev = connector->dev; tmp = gma_attached_encoder(connector); gma_encoder = tmp; lvds_priv = (struct psb_intel_lvds_priv *)gma_encoder->dev_priv; descriptor.modname = "gma500_gfx"; descriptor.function = "psb_intel_lvds_restore"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_intel_lvds.c"; descriptor.format = "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n"; descriptor.lineno = 319U; descriptor.flags = 0U; tmp___0 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___0 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "(0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x)\n", lvds_priv->savePP_ON, lvds_priv->savePP_OFF, lvds_priv->saveLVDS, lvds_priv->savePP_CONTROL, lvds_priv->savePP_CYCLE, lvds_priv->saveBLC_PWM_CTL); } else { } REGISTER_WRITE(dev, 397908U, lvds_priv->saveBLC_PWM_CTL); REGISTER_WRITE(dev, 397872U, lvds_priv->savePFIT_CONTROL); REGISTER_WRITE(dev, 397876U, lvds_priv->savePFIT_PGM_RATIOS); REGISTER_WRITE(dev, 397832U, lvds_priv->savePP_ON); REGISTER_WRITE(dev, 397836U, lvds_priv->savePP_OFF); REGISTER_WRITE(dev, 397840U, lvds_priv->savePP_CYCLE); REGISTER_WRITE(dev, 397828U, lvds_priv->savePP_CONTROL); REGISTER_WRITE(dev, 397696U, lvds_priv->saveLVDS); if ((int )lvds_priv->savePP_CONTROL & 1) { tmp___1 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___1 | 1U); ldv_41626: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status >= 0) { goto ldv_41626; } else { } } else { tmp___2 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___2 & 4294967294U); ldv_41628: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status < 0) { goto ldv_41628; } else { } } return; } } int psb_intel_lvds_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) { struct drm_psb_private *dev_priv ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct drm_display_mode *fixed_mode ; { dev_priv = (struct drm_psb_private *)(connector->dev)->dev_private; tmp = gma_attached_encoder(connector); gma_encoder = tmp; fixed_mode = dev_priv->mode_dev.panel_fixed_mode; if (gma_encoder->type == 8) { fixed_mode = dev_priv->mode_dev.panel_fixed_mode2; } else { } if ((mode->flags & 32U) != 0U) { return (8); } else { } if ((mode->flags & 16U) != 0U) { return (7); } else { } if ((unsigned long )fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { if (mode->hdisplay > fixed_mode->hdisplay) { return (29); } else { } if (mode->vdisplay > fixed_mode->vdisplay) { return (29); } else { } } else { } return (0); } } bool psb_intel_lvds_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct drm_encoder *tmp_encoder ; struct drm_display_mode *panel_fixed_mode ; struct gma_encoder *gma_encoder ; struct drm_encoder const *__mptr___0 ; struct list_head const *__mptr___1 ; struct list_head const *__mptr___2 ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; __mptr = (struct drm_crtc const *)encoder->crtc; gma_crtc = (struct gma_crtc *)__mptr; panel_fixed_mode = mode_dev->panel_fixed_mode; __mptr___0 = (struct drm_encoder const *)encoder; gma_encoder = (struct gma_encoder *)__mptr___0; if (gma_encoder->type == 8) { panel_fixed_mode = mode_dev->panel_fixed_mode2; } else { } if (((int )(dev->pdev)->device & 65520) != 16640 && gma_crtc->pipe == 0) { printk("\vCan\'t support LVDS on pipe A\n"); return (0); } else { } if (((int )(dev->pdev)->device & 65520) == 16640 && gma_crtc->pipe != 0) { printk("\vMust use PIPE A\n"); return (0); } else { } __mptr___1 = (struct list_head const *)dev->mode_config.encoder_list.next; tmp_encoder = (struct drm_encoder *)__mptr___1 + 0xfffffffffffffff8UL; goto ldv_41658; ldv_41657: ; if ((unsigned long )tmp_encoder != (unsigned long )encoder && (unsigned long )tmp_encoder->crtc == (unsigned long )encoder->crtc) { printk("\vCan\'t enable LVDS and another encoder on the same pipe\n"); return (0); } else { } __mptr___2 = (struct list_head const *)tmp_encoder->head.next; tmp_encoder = (struct drm_encoder *)__mptr___2 + 0xfffffffffffffff8UL; ldv_41658: ; if ((unsigned long )(& tmp_encoder->head) != (unsigned long )(& dev->mode_config.encoder_list)) { goto ldv_41657; } else { } if ((unsigned long )panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; adjusted_mode->hsync_start = panel_fixed_mode->hsync_start; adjusted_mode->hsync_end = panel_fixed_mode->hsync_end; adjusted_mode->htotal = panel_fixed_mode->htotal; adjusted_mode->vdisplay = panel_fixed_mode->vdisplay; adjusted_mode->vsync_start = panel_fixed_mode->vsync_start; adjusted_mode->vsync_end = panel_fixed_mode->vsync_end; adjusted_mode->vtotal = panel_fixed_mode->vtotal; adjusted_mode->clock = panel_fixed_mode->clock; drm_mode_set_crtcinfo(adjusted_mode, 1); } else { } return (1); } } static void psb_intel_lvds_prepare(struct drm_encoder *encoder ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; bool tmp ; int tmp___0 ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return; } else { } mode_dev->saveBLC_PWM_CTL = REGISTER_READ(dev, 397908U); mode_dev->backlight_duty_cycle = (int )mode_dev->saveBLC_PWM_CTL & 65535; psb_intel_lvds_set_power(dev, 0); gma_power_end(dev); return; } } static void psb_intel_lvds_commit(struct drm_encoder *encoder ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; u32 tmp ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; if (mode_dev->backlight_duty_cycle == 0) { tmp = psb_intel_lvds_get_max_backlight(dev); mode_dev->backlight_duty_cycle = (int )tmp; } else { } psb_intel_lvds_set_power(dev, 1); return; } } static void psb_intel_lvds_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; u32 pfit_control ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; if (mode->hdisplay != adjusted_mode->hdisplay || mode->vdisplay != adjusted_mode->vdisplay) { pfit_control = 2147485280U; } else { pfit_control = 0U; } if ((unsigned int )*((unsigned char *)dev_priv + 864UL) != 0U) { pfit_control = pfit_control | 8U; } else { } REGISTER_WRITE(dev, 397872U, pfit_control); return; } } static enum drm_connector_status psb_intel_lvds_detect(struct drm_connector *connector , bool force ) { { return (1); } } static int psb_intel_lvds_get_modes(struct drm_connector *connector ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct psb_intel_lvds_priv *lvds_priv ; int ret ; struct drm_display_mode *mode ; struct drm_display_mode *tmp___0 ; { dev = connector->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; tmp = gma_attached_encoder(connector); gma_encoder = tmp; lvds_priv = (struct psb_intel_lvds_priv *)gma_encoder->dev_priv; ret = 0; if (((int )(dev->pdev)->device & 65520) != 16640) { ret = psb_intel_ddc_get_modes(connector, & (lvds_priv->i2c_bus)->adapter); } else { } if (ret != 0) { return (ret); } else { } connector->display_info.min_vfreq = 0U; connector->display_info.max_vfreq = 200U; connector->display_info.min_hfreq = 0U; connector->display_info.max_hfreq = 200U; if ((unsigned long )mode_dev->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { tmp___0 = drm_mode_duplicate(dev, (struct drm_display_mode const *)mode_dev->panel_fixed_mode); mode = tmp___0; drm_mode_probed_add(connector, mode); return (1); } else { } return (0); } } void psb_intel_lvds_destroy(struct drm_connector *connector ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct psb_intel_lvds_priv *lvds_priv ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; lvds_priv = (struct psb_intel_lvds_priv *)gma_encoder->dev_priv; if ((unsigned long )lvds_priv->ddc_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { psb_intel_i2c_destroy(lvds_priv->ddc_bus); } else { } drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree((void const *)connector); return; } } int psb_intel_lvds_set_property(struct drm_connector *connector , struct drm_property *property , uint64_t value ) { struct drm_encoder *encoder ; struct gma_crtc *crtc ; struct drm_crtc const *__mptr ; uint64_t curval ; int tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; int tmp___3 ; struct drm_encoder_helper_funcs const *hfuncs ; int tmp___4 ; int tmp___5 ; int tmp___6 ; { encoder = connector->encoder; if ((unsigned long )encoder == (unsigned long )((struct drm_encoder *)0)) { return (-1); } else { } tmp___6 = strcmp((char const *)(& property->name), "scaling mode"); if (tmp___6 == 0) { __mptr = (struct drm_crtc const *)encoder->crtc; crtc = (struct gma_crtc *)__mptr; if ((unsigned long )crtc == (unsigned long )((struct gma_crtc *)0)) { goto set_prop_error; } else { } switch (value) { case 1ULL: ; goto ldv_41711; case 2ULL: ; goto ldv_41711; case 3ULL: ; goto ldv_41711; default: ; goto set_prop_error; } ldv_41711: tmp = drm_object_property_get_value(& connector->base, property, & curval); if (tmp != 0) { goto set_prop_error; } else { } if (curval == value) { goto set_prop_done; } else { } tmp___0 = drm_object_property_set_value(& connector->base, property, value); if (tmp___0 != 0) { goto set_prop_error; } else { } if (crtc->saved_mode.hdisplay != 0 && crtc->saved_mode.vdisplay != 0) { tmp___1 = drm_crtc_helper_set_mode(encoder->crtc, & crtc->saved_mode, (encoder->crtc)->x, (encoder->crtc)->y, ((encoder->crtc)->primary)->fb); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { goto set_prop_error; } else { } } else { } } else { tmp___5 = strcmp((char const *)(& property->name), "backlight"); if (tmp___5 == 0) { tmp___3 = drm_object_property_set_value(& connector->base, property, value); if (tmp___3 != 0) { goto set_prop_error; } else { gma_backlight_set(encoder->dev, (int )value); } } else { tmp___4 = strcmp((char const *)(& property->name), "DPMS"); if (tmp___4 == 0) { hfuncs = (struct drm_encoder_helper_funcs const *)encoder->helper_private; (*(hfuncs->dpms))(encoder, (int )value); } else { } } } set_prop_done: ; return (0); set_prop_error: ; return (-1); } } static struct drm_encoder_helper_funcs const psb_intel_lvds_helper_funcs = {& psb_intel_lvds_encoder_dpms, 0, 0, & psb_intel_lvds_mode_fixup, & psb_intel_lvds_prepare, & psb_intel_lvds_commit, & psb_intel_lvds_mode_set, 0, 0, 0, 0, 0}; struct drm_connector_helper_funcs const psb_intel_lvds_connector_helper_funcs = {& psb_intel_lvds_get_modes, (enum drm_mode_status (*)(struct drm_connector * , struct drm_display_mode * ))(& psb_intel_lvds_mode_valid), & gma_best_encoder}; struct drm_connector_funcs const psb_intel_lvds_connector_funcs = {& drm_helper_connector_dpms, & psb_intel_lvds_save, & psb_intel_lvds_restore, 0, & psb_intel_lvds_detect, & drm_helper_probe_single_connector_modes, & psb_intel_lvds_set_property, & psb_intel_lvds_destroy, 0, 0, 0, 0, 0}; static void psb_intel_lvds_enc_destroy(struct drm_encoder *encoder ) { { drm_encoder_cleanup(encoder); return; } } struct drm_encoder_funcs const psb_intel_lvds_enc_funcs = {0, & psb_intel_lvds_enc_destroy}; void psb_intel_lvds_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) { struct gma_encoder *gma_encoder ; struct gma_connector *gma_connector ; struct psb_intel_lvds_priv *lvds_priv ; struct drm_connector *connector ; struct drm_encoder *encoder ; struct drm_display_mode *scan ; struct drm_crtc *crtc ; struct drm_psb_private *dev_priv ; u32 lvds ; int pipe ; void *tmp ; void *tmp___0 ; void *tmp___1 ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = kzalloc(152UL, 208U); gma_encoder = (struct gma_encoder *)tmp; if ((unsigned long )gma_encoder == (unsigned long )((struct gma_encoder *)0)) { dev_err((struct device const *)dev->dev, "gma_encoder allocation error\n"); return; } else { } tmp___0 = kzalloc(944UL, 208U); gma_connector = (struct gma_connector *)tmp___0; if ((unsigned long )gma_connector == (unsigned long )((struct gma_connector *)0)) { dev_err((struct device const *)dev->dev, "gma_connector allocation error\n"); goto failed_encoder; } else { } tmp___1 = kzalloc(48UL, 208U); lvds_priv = (struct psb_intel_lvds_priv *)tmp___1; if ((unsigned long )lvds_priv == (unsigned long )((struct psb_intel_lvds_priv *)0)) { dev_err((struct device const *)dev->dev, "LVDS private allocation error\n"); goto failed_connector; } else { } gma_encoder->dev_priv = (void *)lvds_priv; connector = & gma_connector->base; encoder = & gma_encoder->base; drm_connector_init(dev, connector, & psb_intel_lvds_connector_funcs, 7); drm_encoder_init(dev, encoder, & psb_intel_lvds_enc_funcs, 3); gma_connector_attach_encoder(gma_connector, gma_encoder); gma_encoder->type = 4; drm_encoder_helper_add(encoder, & psb_intel_lvds_helper_funcs); drm_connector_helper_add(connector, & psb_intel_lvds_connector_helper_funcs); connector->display_info.subpixel_order = 1; connector->interlace_allowed = 0; connector->doublescan_allowed = 0; drm_object_attach_property(& connector->base, dev->mode_config.scaling_mode_property, 1ULL); drm_object_attach_property(& connector->base, dev_priv->backlight_property, 100ULL); lvds_priv->i2c_bus = psb_intel_i2c_create(dev, 20500U, "LVDSBLC_B"); if ((unsigned long )lvds_priv->i2c_bus == (unsigned long )((struct psb_intel_i2c_chan *)0)) { dev_printk("\v", (struct device const *)(& (dev->pdev)->dev), "I2C bus registration failed.\n"); goto failed_blc_i2c; } else { } (lvds_priv->i2c_bus)->slave_addr = 44U; dev_priv->lvds_i2c_bus = lvds_priv->i2c_bus; lvds_priv->ddc_bus = psb_intel_i2c_create(dev, 20504U, "LVDSDDC_C"); if ((unsigned long )lvds_priv->ddc_bus == (unsigned long )((struct psb_intel_i2c_chan *)0)) { dev_printk("\v", (struct device const *)(& (dev->pdev)->dev), "DDC bus registration failed.\n"); goto failed_ddc; } else { } mutex_lock_nested(& dev->mode_config.mutex, 0U); psb_intel_ddc_get_modes(connector, & (lvds_priv->ddc_bus)->adapter); __mptr = (struct list_head const *)connector->probed_modes.next; scan = (struct drm_display_mode *)__mptr; goto ldv_41748; ldv_41747: ; if ((scan->type & 8U) != 0U) { mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)scan); goto out; } else { } __mptr___0 = (struct list_head const *)scan->head.next; scan = (struct drm_display_mode *)__mptr___0; ldv_41748: ; if ((unsigned long )(& scan->head) != (unsigned long )(& connector->probed_modes)) { goto ldv_41747; } else { } if ((unsigned long )mode_dev->vbt_mode != (unsigned long )((struct drm_display_mode *)0)) { mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)mode_dev->vbt_mode); } else { } if ((unsigned long )mode_dev->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { if ((unsigned long )dev_priv->lfp_lvds_vbt_mode != (unsigned long )((struct drm_display_mode *)0)) { mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)dev_priv->lfp_lvds_vbt_mode); } else { } } else { } lvds = REGISTER_READ(dev, 397696U); pipe = (lvds & 1073741824U) != 0U; crtc = psb_intel_get_crtc_from_pipe(dev, pipe); if ((unsigned long )crtc != (unsigned long )((struct drm_crtc *)0) && (int )lvds < 0) { mode_dev->panel_fixed_mode = psb_intel_crtc_mode_get(dev, crtc); if ((unsigned long )mode_dev->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { (mode_dev->panel_fixed_mode)->type = (mode_dev->panel_fixed_mode)->type | 8U; goto out; } else { } } else { } if ((unsigned long )mode_dev->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { dev_err((struct device const *)dev->dev, "Found no modes on the lvds, ignoring the LVDS\n"); goto failed_find; } else { } out: mutex_unlock(& dev->mode_config.mutex); drm_connector_register(connector); return; failed_find: mutex_unlock(& dev->mode_config.mutex); if ((unsigned long )lvds_priv->ddc_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { psb_intel_i2c_destroy(lvds_priv->ddc_bus); } else { } failed_ddc: ; if ((unsigned long )lvds_priv->i2c_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { psb_intel_i2c_destroy(lvds_priv->i2c_bus); } else { } failed_blc_i2c: drm_encoder_cleanup(encoder); drm_connector_cleanup(connector); failed_connector: kfree((void const *)gma_connector); failed_encoder: kfree((void const *)gma_encoder); return; } } extern int ldv_probe_41(void) ; extern int ldv_probe_42(void) ; void ldv_initialize_drm_encoder_helper_funcs_44(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(96UL); psb_intel_lvds_helper_funcs_group0 = (struct drm_encoder *)tmp; tmp___0 = ldv_init_zalloc(208UL); psb_intel_lvds_helper_funcs_group1 = (struct drm_display_mode *)tmp___0; return; } } void ldv_initialize_drm_connector_helper_funcs_43(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); psb_intel_lvds_connector_helper_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_initialize_drm_connector_funcs_42(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); psb_intel_lvds_connector_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_main_exported_42(void) { bool ldvarg115 ; struct drm_property *ldvarg114 ; void *tmp ; uint64_t ldvarg113 ; uint32_t ldvarg112 ; int ldvarg116 ; uint32_t ldvarg111 ; int tmp___0 ; { tmp = ldv_init_zalloc(104UL); ldvarg114 = (struct drm_property *)tmp; ldv_memset((void *)(& ldvarg115), 0, 1UL); ldv_memset((void *)(& ldvarg113), 0, 8UL); ldv_memset((void *)(& ldvarg112), 0, 4UL); ldv_memset((void *)(& ldvarg116), 0, 4UL); ldv_memset((void *)(& ldvarg111), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_42 == 1) { drm_helper_connector_dpms(psb_intel_lvds_connector_funcs_group0, ldvarg116); ldv_state_variable_42 = 1; } else { } if (ldv_state_variable_42 == 2) { drm_helper_connector_dpms(psb_intel_lvds_connector_funcs_group0, ldvarg116); ldv_state_variable_42 = 2; } else { } goto ldv_41774; case 1: ; if (ldv_state_variable_42 == 1) { psb_intel_lvds_detect(psb_intel_lvds_connector_funcs_group0, (int )ldvarg115); ldv_state_variable_42 = 1; } else { } if (ldv_state_variable_42 == 2) { psb_intel_lvds_detect(psb_intel_lvds_connector_funcs_group0, (int )ldvarg115); ldv_state_variable_42 = 2; } else { } goto ldv_41774; case 2: ; if (ldv_state_variable_42 == 1) { psb_intel_lvds_set_property(psb_intel_lvds_connector_funcs_group0, ldvarg114, ldvarg113); ldv_state_variable_42 = 1; } else { } if (ldv_state_variable_42 == 2) { psb_intel_lvds_set_property(psb_intel_lvds_connector_funcs_group0, ldvarg114, ldvarg113); ldv_state_variable_42 = 2; } else { } goto ldv_41774; case 3: ; if (ldv_state_variable_42 == 2) { psb_intel_lvds_destroy(psb_intel_lvds_connector_funcs_group0); ldv_state_variable_42 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41774; case 4: ; if (ldv_state_variable_42 == 1) { psb_intel_lvds_save(psb_intel_lvds_connector_funcs_group0); ldv_state_variable_42 = 1; } else { } if (ldv_state_variable_42 == 2) { psb_intel_lvds_save(psb_intel_lvds_connector_funcs_group0); ldv_state_variable_42 = 2; } else { } goto ldv_41774; case 5: ; if (ldv_state_variable_42 == 1) { psb_intel_lvds_restore(psb_intel_lvds_connector_funcs_group0); ldv_state_variable_42 = 1; } else { } if (ldv_state_variable_42 == 2) { psb_intel_lvds_restore(psb_intel_lvds_connector_funcs_group0); ldv_state_variable_42 = 2; } else { } goto ldv_41774; case 6: ; if (ldv_state_variable_42 == 1) { drm_helper_probe_single_connector_modes(psb_intel_lvds_connector_funcs_group0, ldvarg112, ldvarg111); ldv_state_variable_42 = 1; } else { } if (ldv_state_variable_42 == 2) { drm_helper_probe_single_connector_modes(psb_intel_lvds_connector_funcs_group0, ldvarg112, ldvarg111); ldv_state_variable_42 = 2; } else { } goto ldv_41774; case 7: ; if (ldv_state_variable_42 == 1) { ldv_probe_42(); ldv_state_variable_42 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41774; default: ldv_stop(); } ldv_41774: ; return; } } void ldv_main_exported_43(void) { struct drm_display_mode *ldvarg212 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(208UL); ldvarg212 = (struct drm_display_mode *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_43 == 1) { psb_intel_lvds_get_modes(psb_intel_lvds_connector_helper_funcs_group0); ldv_state_variable_43 = 1; } else { } goto ldv_41788; case 1: ; if (ldv_state_variable_43 == 1) { psb_intel_lvds_mode_valid(psb_intel_lvds_connector_helper_funcs_group0, ldvarg212); ldv_state_variable_43 = 1; } else { } goto ldv_41788; case 2: ; if (ldv_state_variable_43 == 1) { gma_best_encoder(psb_intel_lvds_connector_helper_funcs_group0); ldv_state_variable_43 = 1; } else { } goto ldv_41788; default: ldv_stop(); } ldv_41788: ; return; } } void ldv_main_exported_44(void) { struct drm_display_mode *ldvarg25 ; void *tmp ; struct drm_display_mode *ldvarg26 ; void *tmp___0 ; int ldvarg27 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg25 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg26 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg27), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_44 == 1) { psb_intel_lvds_encoder_dpms(psb_intel_lvds_helper_funcs_group0, ldvarg27); ldv_state_variable_44 = 1; } else { } goto ldv_41799; case 1: ; if (ldv_state_variable_44 == 1) { psb_intel_lvds_mode_fixup(psb_intel_lvds_helper_funcs_group0, (struct drm_display_mode const *)ldvarg26, psb_intel_lvds_helper_funcs_group1); ldv_state_variable_44 = 1; } else { } goto ldv_41799; case 2: ; if (ldv_state_variable_44 == 1) { psb_intel_lvds_commit(psb_intel_lvds_helper_funcs_group0); ldv_state_variable_44 = 1; } else { } goto ldv_41799; case 3: ; if (ldv_state_variable_44 == 1) { psb_intel_lvds_mode_set(psb_intel_lvds_helper_funcs_group0, psb_intel_lvds_helper_funcs_group1, ldvarg25); ldv_state_variable_44 = 1; } else { } goto ldv_41799; case 4: ; if (ldv_state_variable_44 == 1) { psb_intel_lvds_prepare(psb_intel_lvds_helper_funcs_group0); ldv_state_variable_44 = 1; } else { } goto ldv_41799; default: ldv_stop(); } ldv_41799: ; return; } } void ldv_main_exported_41(void) { struct drm_encoder *ldvarg172 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(96UL); ldvarg172 = (struct drm_encoder *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_41 == 2) { psb_intel_lvds_enc_destroy(ldvarg172); ldv_state_variable_41 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41810; case 1: ; if (ldv_state_variable_41 == 1) { ldv_probe_41(); ldv_state_variable_41 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41810; default: ldv_stop(); } ldv_41810: ; return; } } bool ldv_queue_work_on_215(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_216(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_217(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_218(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_219(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_229(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_231(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_230(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_233(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_232(struct workqueue_struct *ldv_func_arg1 ) ; extern struct edid *drm_get_edid(struct drm_connector * , struct i2c_adapter * ) ; extern int drm_add_edid_modes(struct drm_connector * , struct edid * ) ; extern int drm_mode_connector_update_edid_property(struct drm_connector * , struct edid const * ) ; bool psb_intel_ddc_probe(struct i2c_adapter *adapter ) ; bool psb_intel_ddc_probe(struct i2c_adapter *adapter ) { u8 out_buf[2U] ; u8 buf[2U] ; int ret ; struct i2c_msg msgs[2U] ; { out_buf[0] = 0U; out_buf[1] = 0U; msgs[0].addr = 80U; msgs[0].flags = 0U; msgs[0].len = 1U; msgs[0].buf = (__u8 *)(& out_buf); msgs[1].addr = 80U; msgs[1].flags = 1U; msgs[1].len = 1U; msgs[1].buf = (__u8 *)(& buf); ret = i2c_transfer(adapter, (struct i2c_msg *)(& msgs), 2); if (ret == 2) { return (1); } else { } return (0); } } int psb_intel_ddc_get_modes(struct drm_connector *connector , struct i2c_adapter *adapter ) { struct edid *edid ; int ret ; { ret = 0; edid = drm_get_edid(connector, adapter); if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { drm_mode_connector_update_edid_property(connector, (struct edid const *)edid); ret = drm_add_edid_modes(connector, edid); kfree((void const *)edid); } else { } return (ret); } } bool ldv_queue_work_on_229(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_230(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_231(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_232(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_233(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } void *__builtin_alloca(unsigned long ) ; __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static int list_empty(struct list_head const *head ) { { return ((unsigned long )((struct list_head const *)head->next) == (unsigned long )head); } } bool ldv_queue_work_on_243(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_245(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_244(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_247(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_246(struct workqueue_struct *ldv_func_arg1 ) ; extern void drm_mode_destroy(struct drm_device * , struct drm_display_mode * ) ; extern struct drm_property *drm_property_create(struct drm_device * , int , char const * , int ) ; extern int drm_property_add_enum(struct drm_property * , int , uint64_t , char const * ) ; extern bool drm_detect_hdmi_monitor(struct edid * ) ; extern bool drm_detect_monitor_audio(struct edid * ) ; __inline static void psb_intel_mode_set_pixel_multiplier(struct drm_display_mode *mode , int multiplier ) { { mode->clock = mode->clock * multiplier; mode->private_flags = mode->private_flags | multiplier; return; } } __inline static int psb_intel_mode_get_pixel_multiplier(struct drm_display_mode const *mode ) { { return ((int )mode->private_flags & 15); } } bool psb_intel_sdvo_init(struct drm_device *dev , int sdvo_reg ) ; __inline static uint32_t REGISTER_READ_AUX(struct drm_device *dev , uint32_t reg ) { struct drm_psb_private *dev_priv ; unsigned int tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = ioread32((void *)dev_priv->aux_reg + (unsigned long )reg); return (tmp); } } __inline static uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev , uint32_t reg , int aux ) { uint32_t val ; { if (aux != 0) { val = REGISTER_READ_AUX(dev, reg); } else { val = REGISTER_READ(dev, reg); } return (val); } } __inline static void REGISTER_WRITE_AUX(struct drm_device *dev , uint32_t reg , uint32_t val ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; iowrite32(val, (void *)dev_priv->aux_reg + (unsigned long )reg); return; } } __inline static void REGISTER_WRITE_WITH_AUX(struct drm_device *dev , uint32_t reg , uint32_t val , int aux ) { { if (aux != 0) { REGISTER_WRITE_AUX(dev, reg, val); } else { REGISTER_WRITE(dev, reg, val); } return; } } static char const *tv_format_names[19U] = { "NTSC_M", "NTSC_J", "NTSC_443", "PAL_B", "PAL_D", "PAL_G", "PAL_H", "PAL_I", "PAL_M", "PAL_N", "PAL_NC", "PAL_60", "SECAM_B", "SECAM_D", "SECAM_G", "SECAM_K", "SECAM_K1", "SECAM_L", "SECAM_60"}; static struct psb_intel_sdvo *to_psb_intel_sdvo(struct drm_encoder *encoder ) { struct drm_encoder const *__mptr ; { __mptr = (struct drm_encoder const *)encoder; return ((struct psb_intel_sdvo *)__mptr); } } static struct psb_intel_sdvo *intel_attached_sdvo(struct drm_connector *connector ) { struct gma_encoder const *__mptr ; struct gma_encoder *tmp ; { tmp = gma_attached_encoder(connector); __mptr = (struct gma_encoder const *)tmp; return ((struct psb_intel_sdvo *)__mptr); } } static struct psb_intel_sdvo_connector *to_psb_intel_sdvo_connector(struct drm_connector *connector ) { struct gma_connector const *__mptr ; struct drm_connector const *__mptr___0 ; { __mptr___0 = (struct drm_connector const *)connector; __mptr = (struct gma_connector const *)((struct gma_connector *)__mptr___0); return ((struct psb_intel_sdvo_connector *)__mptr); } } static bool psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo , uint16_t flags ) ; static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_connector *psb_intel_sdvo_connector , int type ) ; static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ) ; static void psb_intel_sdvo_write_sdvox(struct psb_intel_sdvo *psb_intel_sdvo , u32 val ) { struct drm_device *dev ; u32 bval ; u32 cval ; int i ; int j ; int need_aux ; { dev = psb_intel_sdvo->base.base.dev; bval = val; cval = val; need_aux = ((int )(dev->pdev)->device & 65520) == 16640; j = 0; goto ldv_42091; ldv_42090: ; if (psb_intel_sdvo->sdvo_reg == 397632) { cval = REGISTER_READ_WITH_AUX(dev, 397664U, j); } else { bval = REGISTER_READ_WITH_AUX(dev, 397632U, j); } i = 0; goto ldv_42088; ldv_42087: REGISTER_WRITE_WITH_AUX(dev, 397632U, bval, j); REGISTER_READ_WITH_AUX(dev, 397632U, j); REGISTER_WRITE_WITH_AUX(dev, 397664U, cval, j); REGISTER_READ_WITH_AUX(dev, 397664U, j); i = i + 1; ldv_42088: ; if (i <= 1) { goto ldv_42087; } else { } j = j + 1; ldv_42091: ; if (j <= need_aux) { goto ldv_42090; } else { } return; } } static bool psb_intel_sdvo_read_byte(struct psb_intel_sdvo *psb_intel_sdvo , u8 addr , u8 *ch ) { struct i2c_msg msgs[2U] ; int ret ; long tmp ; { msgs[0].addr = (unsigned short )psb_intel_sdvo->slave_addr; msgs[0].flags = 0U; msgs[0].len = 1U; msgs[0].buf = & addr; msgs[1].addr = (unsigned short )psb_intel_sdvo->slave_addr; msgs[1].flags = 1U; msgs[1].len = 1U; msgs[1].buf = ch; ret = i2c_transfer(psb_intel_sdvo->i2c, (struct i2c_msg *)(& msgs), 2); if (ret == 2) { return (1); } else { } tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("psb_intel_sdvo_read_byte", "i2c transfer returned %d\n", ret); } else { } return (0); } } static struct _sdvo_cmd_name const sdvo_cmd_names[107U] = { {1U, "SDVO_CMD_RESET"}, {2U, "SDVO_CMD_GET_DEVICE_CAPS"}, {134U, "SDVO_CMD_GET_FIRMWARE_REV"}, {3U, "SDVO_CMD_GET_TRAINED_INPUTS"}, {4U, "SDVO_CMD_GET_ACTIVE_OUTPUTS"}, {5U, "SDVO_CMD_SET_ACTIVE_OUTPUTS"}, {6U, "SDVO_CMD_GET_IN_OUT_MAP"}, {7U, "SDVO_CMD_SET_IN_OUT_MAP"}, {11U, "SDVO_CMD_GET_ATTACHED_DISPLAYS"}, {12U, "SDVO_CMD_GET_HOT_PLUG_SUPPORT"}, {13U, "SDVO_CMD_SET_ACTIVE_HOT_PLUG"}, {14U, "SDVO_CMD_GET_ACTIVE_HOT_PLUG"}, {15U, "SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE"}, {16U, "SDVO_CMD_SET_TARGET_INPUT"}, {17U, "SDVO_CMD_SET_TARGET_OUTPUT"}, {18U, "SDVO_CMD_GET_INPUT_TIMINGS_PART1"}, {19U, "SDVO_CMD_GET_INPUT_TIMINGS_PART2"}, {20U, "SDVO_CMD_SET_INPUT_TIMINGS_PART1"}, {21U, "SDVO_CMD_SET_INPUT_TIMINGS_PART2"}, {20U, "SDVO_CMD_SET_INPUT_TIMINGS_PART1"}, {22U, "SDVO_CMD_SET_OUTPUT_TIMINGS_PART1"}, {23U, "SDVO_CMD_SET_OUTPUT_TIMINGS_PART2"}, {24U, "SDVO_CMD_GET_OUTPUT_TIMINGS_PART1"}, {25U, "SDVO_CMD_GET_OUTPUT_TIMINGS_PART2"}, {26U, "SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING"}, {27U, "SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1"}, {28U, "SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2"}, {29U, "SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE"}, {30U, "SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE"}, {31U, "SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS"}, {32U, "SDVO_CMD_GET_CLOCK_RATE_MULT"}, {33U, "SDVO_CMD_SET_CLOCK_RATE_MULT"}, {39U, "SDVO_CMD_GET_SUPPORTED_TV_FORMATS"}, {40U, "SDVO_CMD_GET_TV_FORMAT"}, {41U, "SDVO_CMD_SET_TV_FORMAT"}, {42U, "SDVO_CMD_GET_SUPPORTED_POWER_STATES"}, {43U, "SDVO_CMD_GET_POWER_STATE"}, {44U, "SDVO_CMD_SET_ENCODER_POWER_STATE"}, {125U, "SDVO_CMD_SET_DISPLAY_POWER_STATE"}, {122U, "SDVO_CMD_SET_CONTROL_BUS_SWITCH"}, {131U, "SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT"}, {133U, "SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT"}, {132U, "SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS"}, {103U, "SDVO_CMD_GET_MAX_HPOS"}, {104U, "SDVO_CMD_GET_HPOS"}, {105U, "SDVO_CMD_SET_HPOS"}, {106U, "SDVO_CMD_GET_MAX_VPOS"}, {107U, "SDVO_CMD_GET_VPOS"}, {108U, "SDVO_CMD_SET_VPOS"}, {85U, "SDVO_CMD_GET_MAX_SATURATION"}, {86U, "SDVO_CMD_GET_SATURATION"}, {87U, "SDVO_CMD_SET_SATURATION"}, {88U, "SDVO_CMD_GET_MAX_HUE"}, {89U, "SDVO_CMD_GET_HUE"}, {90U, "SDVO_CMD_SET_HUE"}, {94U, "SDVO_CMD_GET_MAX_CONTRAST"}, {95U, "SDVO_CMD_GET_CONTRAST"}, {96U, "SDVO_CMD_SET_CONTRAST"}, {91U, "SDVO_CMD_GET_MAX_BRIGHTNESS"}, {92U, "SDVO_CMD_GET_BRIGHTNESS"}, {93U, "SDVO_CMD_SET_BRIGHTNESS"}, {97U, "SDVO_CMD_GET_MAX_OVERSCAN_H"}, {98U, "SDVO_CMD_GET_OVERSCAN_H"}, {99U, "SDVO_CMD_SET_OVERSCAN_H"}, {100U, "SDVO_CMD_GET_MAX_OVERSCAN_V"}, {101U, "SDVO_CMD_GET_OVERSCAN_V"}, {102U, "SDVO_CMD_SET_OVERSCAN_V"}, {77U, "SDVO_CMD_GET_MAX_FLICKER_FILTER"}, {78U, "SDVO_CMD_GET_FLICKER_FILTER"}, {79U, "SDVO_CMD_SET_FLICKER_FILTER"}, {123U, "SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE"}, {80U, "SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE"}, {81U, "SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE"}, {82U, "SDVO_CMD_GET_MAX_FLICKER_FILTER_2D"}, {83U, "SDVO_CMD_GET_FLICKER_FILTER_2D"}, {84U, "SDVO_CMD_SET_FLICKER_FILTER_2D"}, {109U, "SDVO_CMD_GET_MAX_SHARPNESS"}, {110U, "SDVO_CMD_GET_SHARPNESS"}, {111U, "SDVO_CMD_SET_SHARPNESS"}, {112U, "SDVO_CMD_GET_DOT_CRAWL"}, {113U, "SDVO_CMD_SET_DOT_CRAWL"}, {116U, "SDVO_CMD_GET_MAX_TV_CHROMA_FILTER"}, {117U, "SDVO_CMD_GET_TV_CHROMA_FILTER"}, {118U, "SDVO_CMD_SET_TV_CHROMA_FILTER"}, {119U, "SDVO_CMD_GET_MAX_TV_LUMA_FILTER"}, {120U, "SDVO_CMD_GET_TV_LUMA_FILTER"}, {121U, "SDVO_CMD_SET_TV_LUMA_FILTER"}, {157U, "SDVO_CMD_GET_SUPP_ENCODE"}, {158U, "SDVO_CMD_GET_ENCODE"}, {159U, "SDVO_CMD_SET_ENCODE"}, {139U, "SDVO_CMD_SET_PIXEL_REPLI"}, {140U, "SDVO_CMD_GET_PIXEL_REPLI"}, {141U, "SDVO_CMD_GET_COLORIMETRY_CAP"}, {142U, "SDVO_CMD_SET_COLORIMETRY"}, {143U, "SDVO_CMD_GET_COLORIMETRY"}, {144U, "SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER"}, {145U, "SDVO_CMD_SET_AUDIO_STAT"}, {146U, "SDVO_CMD_GET_AUDIO_STAT"}, {148U, "SDVO_CMD_GET_HBUF_INDEX"}, {147U, "SDVO_CMD_SET_HBUF_INDEX"}, {149U, "SDVO_CMD_GET_HBUF_INFO"}, {151U, "SDVO_CMD_GET_HBUF_AV_SPLIT"}, {150U, "SDVO_CMD_SET_HBUF_AV_SPLIT"}, {155U, "SDVO_CMD_GET_HBUF_TXRATE"}, {154U, "SDVO_CMD_SET_HBUF_TXRATE"}, {152U, "SDVO_CMD_SET_HBUF_DATA"}, {153U, "SDVO_CMD_GET_HBUF_DATA"}}; static void psb_intel_sdvo_debug_write(struct psb_intel_sdvo *psb_intel_sdvo , u8 cmd , void const *args , int args_len ) { int i ; long tmp ; long tmp___0 ; long tmp___1 ; long tmp___2 ; long tmp___3 ; long tmp___4 ; { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("psb_intel_sdvo_debug_write", "%s: W: %02X ", psb_intel_sdvo->sdvo_reg == 397632 ? (char *)"SDVOB" : (char *)"SDVOC", (int )cmd); } else { } i = 0; goto ldv_42114; ldv_42113: tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_debug_write", "%02X ", (int )*((u8 *)args + (unsigned long )i)); } else { } i = i + 1; ldv_42114: ; if (i < args_len) { goto ldv_42113; } else { } goto ldv_42117; ldv_42116: tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_debug_write", " "); } else { } i = i + 1; ldv_42117: ; if (i <= 7) { goto ldv_42116; } else { } i = 0; goto ldv_42123; ldv_42122: ; if ((int )((unsigned char )sdvo_cmd_names[i].cmd) == (int )cmd) { tmp___2 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_debug_write", "(%s)", sdvo_cmd_names[i].name); } else { } goto ldv_42121; } else { } i = i + 1; ldv_42123: ; if ((unsigned int )i <= 106U) { goto ldv_42122; } else { } ldv_42121: ; if (i == 107) { tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_debug_write", "(%02X)", (int )cmd); } else { } } else { } tmp___4 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_debug_write", "\n"); } else { } return; } } static char const *cmd_status_names[7U] = { "Power on", "Success", "Not supported", "Invalid arg", "Pending", "Target not specified", "Scaling not supported"}; static bool psb_intel_sdvo_write_cmd(struct psb_intel_sdvo *psb_intel_sdvo , u8 cmd , void const *args , int args_len ) { u8 *buf ; unsigned long __lengthofbuf ; void *tmp ; u8 status ; struct i2c_msg *msgs ; unsigned long __lengthofmsgs ; void *tmp___0 ; int i ; int ret ; long tmp___1 ; long tmp___2 ; { __lengthofbuf = (unsigned long )((long )((args_len + 1) * 2)); tmp = __builtin_alloca(sizeof(*buf) * __lengthofbuf); buf = (u8 *)tmp; __lengthofmsgs = (unsigned long )((long )(args_len + 3)); tmp___0 = __builtin_alloca(sizeof(*msgs) * __lengthofmsgs); msgs = (struct i2c_msg *)tmp___0; psb_intel_sdvo_debug_write(psb_intel_sdvo, (int )cmd, args, args_len); i = 0; goto ldv_42139; ldv_42138: (msgs + i)->addr = (__u16 )psb_intel_sdvo->slave_addr; (msgs + i)->flags = 0U; (msgs + i)->len = 2U; (msgs + i)->buf = (__u8 *)(& buf) + (unsigned long )(i * 2); *(buf + i * 2) = 7U - (unsigned int )((u8 )i); *(buf + (i * 2 + 1)) = *((u8 *)args + (unsigned long )i); i = i + 1; ldv_42139: ; if (i < args_len) { goto ldv_42138; } else { } (msgs + i)->addr = (__u16 )psb_intel_sdvo->slave_addr; (msgs + i)->flags = 0U; (msgs + i)->len = 2U; (msgs + i)->buf = (__u8 *)(& buf) + (unsigned long )(i * 2); *(buf + i * 2) = 8U; *(buf + (i * 2 + 1)) = cmd; status = 9U; (msgs + (i + 1))->addr = (__u16 )psb_intel_sdvo->slave_addr; (msgs + (i + 1))->flags = 0U; (msgs + (i + 1))->len = 1U; (msgs + (i + 1))->buf = & status; (msgs + (i + 2))->addr = (__u16 )psb_intel_sdvo->slave_addr; (msgs + (i + 2))->flags = 1U; (msgs + (i + 2))->len = 1U; (msgs + (i + 2))->buf = & status; ret = i2c_transfer(psb_intel_sdvo->i2c, (struct i2c_msg *)(& msgs), i + 3); if (ret < 0) { tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_write_cmd", "I2c transfer returned %d\n", ret); } else { } return (0); } else { } if (i + 3 != ret) { tmp___2 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_write_cmd", "I2c transfer returned %d/%d\n", ret, i + 3); } else { } return (0); } else { } return (1); } } static bool psb_intel_sdvo_read_response(struct psb_intel_sdvo *psb_intel_sdvo , void *response , int response_len ) { u8 retry ; u8 status ; int i ; long tmp ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; u8 tmp___4 ; long tmp___5 ; long tmp___6 ; bool tmp___7 ; int tmp___8 ; long tmp___9 ; long tmp___10 ; long tmp___11 ; { retry = 5U; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("psb_intel_sdvo_read_response", "%s: R: ", psb_intel_sdvo->sdvo_reg == 397632 ? (char *)"SDVOB" : (char *)"SDVOC"); } else { } tmp___0 = psb_intel_sdvo_read_byte(psb_intel_sdvo, 9, & status); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { goto log_fail; } else { } goto ldv_42153; ldv_42152: __const_udelay(64425UL); tmp___2 = psb_intel_sdvo_read_byte(psb_intel_sdvo, 9, & status); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { goto log_fail; } else { } ldv_42153: ; if ((unsigned int )status == 4U || (unsigned int )status == 5U) { tmp___4 = retry; retry = (u8 )((int )retry - 1); if ((unsigned int )tmp___4 != 0U) { goto ldv_42152; } else { goto ldv_42154; } } else { } ldv_42154: ; if ((unsigned int )status <= 6U) { tmp___5 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___5 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_read_response", "(%s)", cmd_status_names[(int )status]); } else { } } else { tmp___6 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___6 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_read_response", "(??? %d)", (int )status); } else { } } if ((unsigned int )status != 1U) { goto log_fail; } else { } i = 0; goto ldv_42156; ldv_42155: tmp___7 = psb_intel_sdvo_read_byte(psb_intel_sdvo, (int )((unsigned int )((u8 )i) + 10U), (u8 *)response + (unsigned long )i); if (tmp___7) { tmp___8 = 0; } else { tmp___8 = 1; } if (tmp___8) { goto log_fail; } else { } tmp___9 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___9 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_read_response", " %02X", (int )*((u8 *)response + (unsigned long )i)); } else { } i = i + 1; ldv_42156: ; if (i < response_len) { goto ldv_42155; } else { } tmp___10 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___10 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_read_response", "\n"); } else { } return (1); log_fail: tmp___11 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___11 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_read_response", "... failed\n"); } else { } return (0); } } static int psb_intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode ) { { if (mode->clock > 99999) { return (1); } else if (mode->clock > 49999) { return (2); } else { return (4); } } } static bool psb_intel_sdvo_set_control_bus_switch(struct psb_intel_sdvo *psb_intel_sdvo , u8 ddc_bus ) { bool tmp ; { tmp = psb_intel_sdvo_write_cmd(psb_intel_sdvo, 122, (void const *)(& ddc_bus), 1); return (tmp); } } static bool psb_intel_sdvo_set_value(struct psb_intel_sdvo *psb_intel_sdvo , u8 cmd , void const *data , int len ) { bool tmp ; int tmp___0 ; bool tmp___1 ; { tmp = psb_intel_sdvo_write_cmd(psb_intel_sdvo, (int )cmd, data, len); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } tmp___1 = psb_intel_sdvo_read_response(psb_intel_sdvo, (void *)0, 0); return (tmp___1); } } static bool psb_intel_sdvo_get_value(struct psb_intel_sdvo *psb_intel_sdvo , u8 cmd , void *value , int len ) { bool tmp ; int tmp___0 ; bool tmp___1 ; { tmp = psb_intel_sdvo_write_cmd(psb_intel_sdvo, (int )cmd, (void const *)0, 0); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } tmp___1 = psb_intel_sdvo_read_response(psb_intel_sdvo, value, len); return (tmp___1); } } static bool psb_intel_sdvo_set_target_input(struct psb_intel_sdvo *psb_intel_sdvo ) { struct psb_intel_sdvo_set_target_input_args targets ; bool tmp ; { targets.target_1 = 0U; targets.pad = (unsigned char)0; tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, 16, (void const *)(& targets), 1); return (tmp); } } static bool psb_intel_sdvo_get_trained_inputs(struct psb_intel_sdvo *psb_intel_sdvo , bool *input_1 , bool *input_2 ) { struct psb_intel_sdvo_get_trained_inputs_response response ; bool tmp ; int tmp___0 ; { tmp = psb_intel_sdvo_get_value(psb_intel_sdvo, 3, (void *)(& response), 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } *input_1 = (int )response.input0_trained != 0; *input_2 = (int )response.input1_trained != 0; return (1); } } static bool psb_intel_sdvo_set_active_outputs(struct psb_intel_sdvo *psb_intel_sdvo , u16 outputs ) { bool tmp ; { tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, 5, (void const *)(& outputs), 2); return (tmp); } } static bool psb_intel_sdvo_get_input_pixel_clock_range(struct psb_intel_sdvo *psb_intel_sdvo , int *clock_min , int *clock_max ) { struct psb_intel_sdvo_pixel_clock_range clocks ; bool tmp ; int tmp___0 ; { tmp = psb_intel_sdvo_get_value(psb_intel_sdvo, 29, (void *)(& clocks), 4); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } *clock_min = (int )clocks.min * 10; *clock_max = (int )clocks.max * 10; return (1); } } static bool psb_intel_sdvo_set_target_output(struct psb_intel_sdvo *psb_intel_sdvo , u16 outputs ) { bool tmp ; { tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, 17, (void const *)(& outputs), 2); return (tmp); } } static bool psb_intel_sdvo_set_timing(struct psb_intel_sdvo *psb_intel_sdvo , u8 cmd , struct psb_intel_sdvo_dtd *dtd ) { bool tmp ; bool tmp___0 ; int tmp___1 ; { tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, (int )cmd, (void const *)(& dtd->part1), 8); if ((int )tmp) { tmp___0 = psb_intel_sdvo_set_value(psb_intel_sdvo, (int )((unsigned int )cmd + 1U), (void const *)(& dtd->part2), 8); if ((int )tmp___0) { tmp___1 = 1; } else { tmp___1 = 0; } } else { tmp___1 = 0; } return ((bool )tmp___1); } } static bool psb_intel_sdvo_set_input_timing(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_dtd *dtd ) { bool tmp ; { tmp = psb_intel_sdvo_set_timing(psb_intel_sdvo, 20, dtd); return (tmp); } } static bool psb_intel_sdvo_set_output_timing(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_dtd *dtd ) { bool tmp ; { tmp = psb_intel_sdvo_set_timing(psb_intel_sdvo, 22, dtd); return (tmp); } } static bool psb_intel_sdvo_create_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo , uint16_t clock , uint16_t width , uint16_t height ) { struct psb_intel_sdvo_preferred_input_timing_args args ; bool tmp ; { memset((void *)(& args), 0, 7UL); args.clock = clock; args.width = width; args.height = height; args.interlace = 0U; if ((int )psb_intel_sdvo->is_lvds && ((psb_intel_sdvo->sdvo_lvds_fixed_mode)->hdisplay != (int )width || (psb_intel_sdvo->sdvo_lvds_fixed_mode)->vdisplay != (int )height)) { args.scaled = 1U; } else { } tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, 26, (void const *)(& args), 7); return (tmp); } } static bool psb_intel_sdvo_get_preferred_input_timing(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_dtd *dtd ) { bool tmp ; bool tmp___0 ; int tmp___1 ; { tmp = psb_intel_sdvo_get_value(psb_intel_sdvo, 27, (void *)(& dtd->part1), 8); if ((int )tmp) { tmp___0 = psb_intel_sdvo_get_value(psb_intel_sdvo, 28, (void *)(& dtd->part2), 8); if ((int )tmp___0) { tmp___1 = 1; } else { tmp___1 = 0; } } else { tmp___1 = 0; } return ((bool )tmp___1); } } static bool psb_intel_sdvo_set_clock_rate_mult(struct psb_intel_sdvo *psb_intel_sdvo , u8 val ) { bool tmp ; { tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, 33, (void const *)(& val), 1); return (tmp); } } static void psb_intel_sdvo_get_dtd_from_mode(struct psb_intel_sdvo_dtd *dtd , struct drm_display_mode const *mode ) { uint16_t width ; uint16_t height ; uint16_t h_blank_len ; uint16_t h_sync_len ; uint16_t v_blank_len ; uint16_t v_sync_len ; uint16_t h_sync_offset ; uint16_t v_sync_offset ; { width = (uint16_t )mode->crtc_hdisplay; height = (uint16_t )mode->crtc_vdisplay; h_blank_len = (int )((uint16_t )mode->crtc_hblank_end) - (int )((uint16_t )mode->crtc_hblank_start); h_sync_len = (int )((uint16_t )mode->crtc_hsync_end) - (int )((uint16_t )mode->crtc_hsync_start); v_blank_len = (int )((uint16_t )mode->crtc_vblank_end) - (int )((uint16_t )mode->crtc_vblank_start); v_sync_len = (int )((uint16_t )mode->crtc_vsync_end) - (int )((uint16_t )mode->crtc_vsync_start); h_sync_offset = (int )((uint16_t )mode->crtc_hsync_start) - (int )((uint16_t )mode->crtc_hblank_start); v_sync_offset = (int )((uint16_t )mode->crtc_vsync_start) - (int )((uint16_t )mode->crtc_vblank_start); dtd->part1.clock = (u16 )((int )mode->clock / 10); dtd->part1.h_active = (u8 )width; dtd->part1.h_blank = (u8 )h_blank_len; dtd->part1.h_high = (u8 )((int )((signed char )(((int )width >> 8) << 4)) | ((int )((signed char )((int )h_blank_len >> 8)) & 15)); dtd->part1.v_active = (u8 )height; dtd->part1.v_blank = (u8 )v_blank_len; dtd->part1.v_high = (u8 )((int )((signed char )(((int )height >> 8) << 4)) | ((int )((signed char )((int )v_blank_len >> 8)) & 15)); dtd->part2.h_sync_off = (u8 )h_sync_offset; dtd->part2.h_sync_width = (u8 )h_sync_len; dtd->part2.v_sync_off_width = (u8 )((int )((signed char )((int )v_sync_offset << 4)) | ((int )((signed char )v_sync_len) & 15)); dtd->part2.sync_off_width_high = (u8 )((((int )((signed char )(((int )h_sync_offset & 768) >> 2)) | (int )((signed char )(((int )h_sync_len & 768) >> 4))) | (int )((signed char )(((int )v_sync_offset & 48) >> 2))) | (int )((signed char )(((int )v_sync_len & 48) >> 4))); dtd->part2.dtd_flags = 24U; if ((int )mode->flags & 1) { dtd->part2.dtd_flags = (u8 )((unsigned int )dtd->part2.dtd_flags | 2U); } else { } if (((unsigned int )mode->flags & 4U) != 0U) { dtd->part2.dtd_flags = (u8 )((unsigned int )dtd->part2.dtd_flags | 4U); } else { } dtd->part2.sdvo_flags = 0U; dtd->part2.v_sync_off_high = (unsigned int )((u8 )v_sync_offset) & 192U; dtd->part2.reserved = 0U; return; } } static void psb_intel_sdvo_get_mode_from_dtd(struct drm_display_mode *mode , struct psb_intel_sdvo_dtd const *dtd ) { { mode->hdisplay = (int )dtd->part1.h_active; mode->hdisplay = mode->hdisplay + ((((int )((unsigned char )dtd->part1.h_high) >> 4) & 15) << 8); mode->hsync_start = mode->hdisplay + (int )dtd->part2.h_sync_off; mode->hsync_start = mode->hsync_start + (((int )dtd->part2.sync_off_width_high & 192) << 2); mode->hsync_end = mode->hsync_start + (int )dtd->part2.h_sync_width; mode->hsync_end = mode->hsync_end + (((int )dtd->part2.sync_off_width_high & 48) << 4); mode->htotal = mode->hdisplay + (int )dtd->part1.h_blank; mode->htotal = mode->htotal + (((int )dtd->part1.h_high & 15) << 8); mode->vdisplay = (int )dtd->part1.v_active; mode->vdisplay = mode->vdisplay + ((((int )((unsigned char )dtd->part1.v_high) >> 4) & 15) << 8); mode->vsync_start = mode->vdisplay; mode->vsync_start = mode->vsync_start + (((int )((unsigned char )dtd->part2.v_sync_off_width) >> 4) & 15); mode->vsync_start = mode->vsync_start + (((int )dtd->part2.sync_off_width_high & 12) << 2); mode->vsync_start = mode->vsync_start + ((int )dtd->part2.v_sync_off_high & 192); mode->vsync_end = mode->vsync_start + ((int )dtd->part2.v_sync_off_width & 15); mode->vsync_end = mode->vsync_end + (((int )dtd->part2.sync_off_width_high & 3) << 4); mode->vtotal = mode->vdisplay + (int )dtd->part1.v_blank; mode->vtotal = mode->vtotal + (((int )dtd->part1.v_high & 15) << 8); mode->clock = (int )dtd->part1.clock * 10; mode->flags = mode->flags & 4294967290U; if (((int )dtd->part2.dtd_flags & 2) != 0) { mode->flags = mode->flags | 1U; } else { } if (((int )dtd->part2.dtd_flags & 4) != 0) { mode->flags = mode->flags | 4U; } else { } return; } } static bool psb_intel_sdvo_check_supp_encode(struct psb_intel_sdvo *psb_intel_sdvo ) { struct psb_intel_sdvo_encode encode ; bool tmp ; { tmp = psb_intel_sdvo_get_value(psb_intel_sdvo, 157, (void *)(& encode), 2); return (tmp); } } static bool psb_intel_sdvo_set_encode(struct psb_intel_sdvo *psb_intel_sdvo , uint8_t mode ) { bool tmp ; { tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, 159, (void const *)(& mode), 1); return (tmp); } } static bool psb_intel_sdvo_set_colorimetry(struct psb_intel_sdvo *psb_intel_sdvo , uint8_t mode ) { bool tmp ; { tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, 142, (void const *)(& mode), 1); return (tmp); } } static bool psb_intel_sdvo_set_avi_infoframe(struct psb_intel_sdvo *psb_intel_sdvo ) { { printk("\016[drm] HDMI is not supported yet"); return (0); } } static bool psb_intel_sdvo_set_tv_format(struct psb_intel_sdvo *psb_intel_sdvo ) { struct psb_intel_sdvo_tv_format format ; uint32_t format_map ; unsigned long _min1 ; unsigned long _min2 ; bool tmp ; { format_map = (uint32_t )(1 << psb_intel_sdvo->tv_format_index); memset((void *)(& format), 0, 6UL); _min1 = 6UL; _min2 = 4UL; memcpy((void *)(& format), (void const *)(& format_map), _min1 < _min2 ? _min1 : _min2); tmp = psb_intel_sdvo_set_value(psb_intel_sdvo, 41, (void const *)(& format), 6); return (tmp); } } static bool psb_intel_sdvo_set_output_timings_from_mode(struct psb_intel_sdvo *psb_intel_sdvo , struct drm_display_mode const *mode ) { struct psb_intel_sdvo_dtd output_dtd ; bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; { tmp = psb_intel_sdvo_set_target_output(psb_intel_sdvo, (int )psb_intel_sdvo->attached_output); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } psb_intel_sdvo_get_dtd_from_mode(& output_dtd, mode); tmp___1 = psb_intel_sdvo_set_output_timing(psb_intel_sdvo, & output_dtd); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (0); } else { } return (1); } } static bool psb_intel_sdvo_set_input_timings_for_mode(struct psb_intel_sdvo *psb_intel_sdvo , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) { bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; bool tmp___3 ; int tmp___4 ; { tmp = psb_intel_sdvo_set_target_input(psb_intel_sdvo); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } tmp___1 = psb_intel_sdvo_create_preferred_input_timing(psb_intel_sdvo, (int )((uint16_t )((int )mode->clock / 10)), (int )((uint16_t )mode->hdisplay), (int )((uint16_t )mode->vdisplay)); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (0); } else { } tmp___3 = psb_intel_sdvo_get_preferred_input_timing(psb_intel_sdvo, & psb_intel_sdvo->input_dtd); if (tmp___3) { tmp___4 = 0; } else { tmp___4 = 1; } if (tmp___4) { return (0); } else { } psb_intel_sdvo_get_mode_from_dtd(adjusted_mode, (struct psb_intel_sdvo_dtd const *)(& psb_intel_sdvo->input_dtd)); drm_mode_set_crtcinfo(adjusted_mode, 0); return (1); } } static bool psb_intel_sdvo_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) { struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; int multiplier ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; { tmp = to_psb_intel_sdvo(encoder); psb_intel_sdvo = tmp; if ((int )psb_intel_sdvo->is_tv) { tmp___0 = psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, mode); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return (0); } else { } psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo, mode, adjusted_mode); } else if ((int )psb_intel_sdvo->is_lvds) { tmp___2 = psb_intel_sdvo_set_output_timings_from_mode(psb_intel_sdvo, (struct drm_display_mode const *)psb_intel_sdvo->sdvo_lvds_fixed_mode); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { return (0); } else { } psb_intel_sdvo_set_input_timings_for_mode(psb_intel_sdvo, mode, adjusted_mode); } else { } multiplier = psb_intel_sdvo_get_pixel_multiplier(adjusted_mode); psb_intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); return (1); } } static void psb_intel_sdvo_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct drm_crtc *crtc ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; u32 sdvox ; struct psb_intel_sdvo_in_out_map in_out ; struct psb_intel_sdvo_dtd input_dtd ; int pixel_multiplier ; int tmp___0 ; int rate ; int need_aux ; bool tmp___1 ; int tmp___2 ; bool tmp___3 ; int tmp___4 ; bool tmp___5 ; int tmp___6 ; bool tmp___7 ; int tmp___8 ; bool tmp___9 ; int tmp___10 ; { dev = encoder->dev; crtc = encoder->crtc; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; tmp = to_psb_intel_sdvo(encoder); psb_intel_sdvo = tmp; tmp___0 = psb_intel_mode_get_pixel_multiplier((struct drm_display_mode const *)adjusted_mode); pixel_multiplier = tmp___0; need_aux = ((int )(dev->pdev)->device & 65520) == 16640; if ((unsigned long )mode == (unsigned long )((struct drm_display_mode *)0)) { return; } else { } in_out.in0 = psb_intel_sdvo->attached_output; in_out.in1 = 0U; psb_intel_sdvo_set_value(psb_intel_sdvo, 7, (void const *)(& in_out), 4); tmp___1 = psb_intel_sdvo_set_target_output(psb_intel_sdvo, (int )psb_intel_sdvo->attached_output); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return; } else { } if ((int )psb_intel_sdvo->is_tv || (int )psb_intel_sdvo->is_lvds) { input_dtd = psb_intel_sdvo->input_dtd; } else { tmp___3 = psb_intel_sdvo_set_target_output(psb_intel_sdvo, (int )psb_intel_sdvo->attached_output); if (tmp___3) { tmp___4 = 0; } else { tmp___4 = 1; } if (tmp___4) { return; } else { } psb_intel_sdvo_get_dtd_from_mode(& input_dtd, (struct drm_display_mode const *)adjusted_mode); psb_intel_sdvo_set_output_timing(psb_intel_sdvo, & input_dtd); } tmp___5 = psb_intel_sdvo_set_target_input(psb_intel_sdvo); if (tmp___5) { tmp___6 = 0; } else { tmp___6 = 1; } if (tmp___6) { return; } else { } if ((int )psb_intel_sdvo->has_hdmi_monitor) { psb_intel_sdvo_set_encode(psb_intel_sdvo, 1); psb_intel_sdvo_set_colorimetry(psb_intel_sdvo, 0); psb_intel_sdvo_set_avi_infoframe(psb_intel_sdvo); } else { psb_intel_sdvo_set_encode(psb_intel_sdvo, 0); } if ((int )psb_intel_sdvo->is_tv) { tmp___7 = psb_intel_sdvo_set_tv_format(psb_intel_sdvo); if (tmp___7) { tmp___8 = 0; } else { tmp___8 = 1; } if (tmp___8) { return; } else { } } else { } psb_intel_sdvo_set_input_timing(psb_intel_sdvo, & input_dtd); switch (pixel_multiplier) { default: ; case 1: rate = 1; goto ldv_42314; case 2: rate = 2; goto ldv_42314; case 4: rate = 8; goto ldv_42314; } ldv_42314: tmp___9 = psb_intel_sdvo_set_clock_rate_mult(psb_intel_sdvo, (int )((u8 )rate)); if (tmp___9) { tmp___10 = 0; } else { tmp___10 = 1; } if (tmp___10) { return; } else { } if (need_aux != 0) { sdvox = REGISTER_READ_AUX(dev, (uint32_t )psb_intel_sdvo->sdvo_reg); } else { sdvox = REGISTER_READ(dev, (uint32_t )psb_intel_sdvo->sdvo_reg); } switch (psb_intel_sdvo->sdvo_reg) { case 397632: sdvox = sdvox & 212992U; goto ldv_42318; case 397664: sdvox = sdvox & 131072U; goto ldv_42318; } ldv_42318: sdvox = sdvox | 4718720U; if (gma_crtc->pipe == 1) { sdvox = sdvox | 1073741824U; } else { } if ((int )psb_intel_sdvo->has_hdmi_audio) { sdvox = sdvox | 64U; } else { } if ((int )((signed char )input_dtd.part2.sdvo_flags) < 0) { sdvox = sdvox | 536870912U; } else { } psb_intel_sdvo_write_sdvox(psb_intel_sdvo, sdvox); return; } } static void psb_intel_sdvo_dpms(struct drm_encoder *encoder , int mode ) { struct drm_device *dev ; struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; u32 temp ; int i ; int need_aux ; long tmp___0 ; long tmp___1 ; long tmp___2 ; bool input1 ; bool input2 ; u8 status ; bool tmp___3 ; long tmp___4 ; { dev = encoder->dev; tmp = to_psb_intel_sdvo(encoder); psb_intel_sdvo = tmp; need_aux = ((int )(dev->pdev)->device & 65520) == 16640; switch (mode) { case 0: tmp___0 = ldv__builtin_expect((long )((int )drm_debug) & 1L, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_dpms", "DPMS_ON"); } else { } goto ldv_42331; case 3: tmp___1 = ldv__builtin_expect((long )((int )drm_debug) & 1L, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_dpms", "DPMS_OFF"); } else { } goto ldv_42331; default: tmp___2 = ldv__builtin_expect((long )((int )drm_debug) & 1L, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_dpms", "DPMS: %d", mode); } else { } } ldv_42331: ; if (mode != 0) { psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, 0); if (mode == 3) { if (need_aux != 0) { temp = REGISTER_READ_AUX(dev, (uint32_t )psb_intel_sdvo->sdvo_reg); } else { temp = REGISTER_READ(dev, (uint32_t )psb_intel_sdvo->sdvo_reg); } if ((int )temp < 0) { psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp & 2147483647U); } else { } } else { } } else { if (need_aux != 0) { temp = REGISTER_READ_AUX(dev, (uint32_t )psb_intel_sdvo->sdvo_reg); } else { temp = REGISTER_READ(dev, (uint32_t )psb_intel_sdvo->sdvo_reg); } if ((int )temp >= 0) { psb_intel_sdvo_write_sdvox(psb_intel_sdvo, temp | 2147483648U); } else { } i = 0; goto ldv_42338; ldv_42337: gma_wait_for_vblank(dev); i = i + 1; ldv_42338: ; if (i <= 1) { goto ldv_42337; } else { } tmp___3 = psb_intel_sdvo_get_trained_inputs(psb_intel_sdvo, & input1, & input2); status = (u8 )tmp___3; if ((unsigned int )status == 1U && ! input1) { tmp___4 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_dpms", "First %s output reported failure to sync\n", psb_intel_sdvo->sdvo_reg == 397632 ? (char *)"SDVOB" : (char *)"SDVOC"); } else { } } else { } psb_intel_sdvo_set_active_outputs(psb_intel_sdvo, (int )psb_intel_sdvo->attached_output); } return; } } static int psb_intel_sdvo_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) { struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; { tmp = intel_attached_sdvo(connector); psb_intel_sdvo = tmp; if ((mode->flags & 32U) != 0U) { return (8); } else { } if (psb_intel_sdvo->pixel_clock_min > mode->clock) { return (16); } else { } if (psb_intel_sdvo->pixel_clock_max < mode->clock) { return (15); } else { } if ((int )psb_intel_sdvo->is_lvds) { if (mode->hdisplay > (psb_intel_sdvo->sdvo_lvds_fixed_mode)->hdisplay) { return (29); } else { } if (mode->vdisplay > (psb_intel_sdvo->sdvo_lvds_fixed_mode)->vdisplay) { return (29); } else { } } else { } return (0); } } static bool psb_intel_sdvo_get_capabilities(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_caps *caps ) { bool tmp ; int tmp___0 ; long tmp___1 ; { tmp = psb_intel_sdvo_get_value(psb_intel_sdvo, 2, (void *)caps, 8); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_get_capabilities", "SDVO capabilities:\n vendor_id: %d\n device_id: %d\n device_rev_id: %d\n sdvo_version_major: %d\n sdvo_version_minor: %d\n sdvo_inputs_mask: %d\n smooth_scaling: %d\n sharp_scaling: %d\n up_scaling: %d\n down_scaling: %d\n stall_support: %d\n output_flags: %d\n", (int )caps->vendor_id, (int )caps->device_id, (int )caps->device_rev_id, (int )caps->sdvo_version_major, (int )caps->sdvo_version_minor, (int )caps->sdvo_inputs_mask, (int )caps->smooth_scaling, (int )caps->sharp_scaling, (int )caps->up_scaling, (int )caps->down_scaling, (int )caps->stall_support, (int )caps->output_flags); } else { } return (1); } } static bool psb_intel_sdvo_multifunc_encoder(struct psb_intel_sdvo *psb_intel_sdvo ) { int caps ; { caps = (int )psb_intel_sdvo->caps.output_flags & 15; return ((- caps & caps) != 0); } } static struct edid *psb_intel_sdvo_get_edid(struct drm_connector *connector ) { struct psb_intel_sdvo *sdvo ; struct psb_intel_sdvo *tmp ; struct edid *tmp___0 ; { tmp = intel_attached_sdvo(connector); sdvo = tmp; tmp___0 = drm_get_edid(connector, & sdvo->ddc); return (tmp___0); } } static struct edid *psb_intel_sdvo_get_analog_edid(struct drm_connector *connector ) { struct drm_psb_private *dev_priv ; struct edid *tmp ; { dev_priv = (struct drm_psb_private *)(connector->dev)->dev_private; tmp = drm_get_edid(connector, & (dev_priv->gmbus + (unsigned long )dev_priv->crt_ddc_pin)->adapter); return (tmp); } } static enum drm_connector_status psb_intel_sdvo_hdmi_sink_detect(struct drm_connector *connector ) { struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; enum drm_connector_status status ; struct edid *edid ; u8 ddc ; u8 saved_ddc ; bool tmp___0 ; struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; struct psb_intel_sdvo_connector *tmp___1 ; { tmp = intel_attached_sdvo(connector); psb_intel_sdvo = tmp; edid = psb_intel_sdvo_get_edid(connector); if ((unsigned long )edid == (unsigned long )((struct edid *)0)) { tmp___0 = psb_intel_sdvo_multifunc_encoder(psb_intel_sdvo); if ((int )tmp___0) { saved_ddc = psb_intel_sdvo->ddc_bus; ddc = (u8 )((int )psb_intel_sdvo->ddc_bus >> 1); goto ldv_42372; ldv_42371: psb_intel_sdvo->ddc_bus = ddc; edid = psb_intel_sdvo_get_edid(connector); if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { goto ldv_42370; } else { } ddc = (u8 )((int )ddc >> 1); ldv_42372: ; if ((unsigned int )ddc > 1U) { goto ldv_42371; } else { } ldv_42370: ; if ((unsigned long )edid == (unsigned long )((struct edid *)0)) { psb_intel_sdvo->ddc_bus = saved_ddc; } else { } } else { } } else { } if ((unsigned long )edid == (unsigned long )((struct edid *)0)) { edid = psb_intel_sdvo_get_analog_edid(connector); } else { } status = 3; if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { if ((int )((signed char )edid->input) < 0) { status = 1; if ((int )psb_intel_sdvo->is_hdmi) { psb_intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); psb_intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); } else { } } else { status = 2; } kfree((void const *)edid); } else { } if ((unsigned int )status == 1U) { tmp___1 = to_psb_intel_sdvo_connector(connector); psb_intel_sdvo_connector = tmp___1; if (psb_intel_sdvo_connector->force_audio != 0) { psb_intel_sdvo->has_hdmi_audio = psb_intel_sdvo_connector->force_audio > 0; } else { } } else { } return (status); } } static enum drm_connector_status psb_intel_sdvo_detect(struct drm_connector *connector , bool force ) { uint16_t response ; struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; struct psb_intel_sdvo_connector *tmp___0 ; enum drm_connector_status ret ; bool tmp___1 ; int tmp___2 ; unsigned long __ms ; unsigned long tmp___3 ; bool tmp___4 ; int tmp___5 ; long tmp___6 ; struct edid *edid ; { tmp = intel_attached_sdvo(connector); psb_intel_sdvo = tmp; tmp___0 = to_psb_intel_sdvo_connector(connector); psb_intel_sdvo_connector = tmp___0; tmp___1 = psb_intel_sdvo_write_cmd(psb_intel_sdvo, 11, (void const *)0, 0); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (3); } else { } if (((int )psb_intel_sdvo->caps.output_flags & 12) != 0) { __ms = 30UL; goto ldv_42384; ldv_42383: __const_udelay(4295000UL); ldv_42384: tmp___3 = __ms; __ms = __ms - 1UL; if (tmp___3 != 0UL) { goto ldv_42383; } else { } } else { } tmp___4 = psb_intel_sdvo_read_response(psb_intel_sdvo, (void *)(& response), 2); if (tmp___4) { tmp___5 = 0; } else { tmp___5 = 1; } if (tmp___5) { return (3); } else { } tmp___6 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___6 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_detect", "SDVO response %d %d [%x]\n", (int )response & 255, (int )response >> 8, (int )psb_intel_sdvo_connector->output_flag); } else { } if ((unsigned int )response == 0U) { return (2); } else { } psb_intel_sdvo->attached_output = response; psb_intel_sdvo->has_hdmi_monitor = 0; psb_intel_sdvo->has_hdmi_audio = 0; if ((unsigned int )((int )psb_intel_sdvo_connector->output_flag & (int )response) == 0U) { ret = 2; } else if (((int )psb_intel_sdvo_connector->output_flag & 257) != 0) { ret = psb_intel_sdvo_hdmi_sink_detect(connector); } else { edid = psb_intel_sdvo_get_edid(connector); if ((unsigned long )edid == (unsigned long )((struct edid *)0)) { edid = psb_intel_sdvo_get_analog_edid(connector); } else { } if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { if ((int )((signed char )edid->input) < 0) { ret = 2; } else { ret = 1; } kfree((void const *)edid); } else { ret = 1; } } if ((unsigned int )ret == 1U) { psb_intel_sdvo->is_tv = 0; psb_intel_sdvo->is_lvds = 0; psb_intel_sdvo->base.needs_tv_clock = 0; if (((int )response & 12) != 0) { psb_intel_sdvo->is_tv = 1; psb_intel_sdvo->base.needs_tv_clock = 1; } else { } if (((int )response & 16448) != 0) { psb_intel_sdvo->is_lvds = (unsigned long )psb_intel_sdvo->sdvo_lvds_fixed_mode != (unsigned long )((struct drm_display_mode *)0); } else { } } else { } return (ret); } } static void psb_intel_sdvo_get_ddc_modes(struct drm_connector *connector ) { struct edid *edid ; struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; struct psb_intel_sdvo_connector *tmp ; bool monitor_is_digital ; bool connector_is_digital ; { edid = psb_intel_sdvo_get_edid(connector); if ((unsigned long )edid == (unsigned long )((struct edid *)0)) { edid = psb_intel_sdvo_get_analog_edid(connector); } else { } if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { tmp = to_psb_intel_sdvo_connector(connector); psb_intel_sdvo_connector = tmp; monitor_is_digital = (int )((signed char )edid->input) < 0; connector_is_digital = ((int )psb_intel_sdvo_connector->output_flag & 257) != 0; if ((int )connector_is_digital == (int )monitor_is_digital) { drm_mode_connector_update_edid_property(connector, (struct edid const *)edid); drm_add_edid_modes(connector, edid); } else { } kfree((void const *)edid); } else { } return; } } static struct drm_display_mode const sdvo_tv_modes[19U] = { {{0, 0}, {0U, 3739147998U, 0}, {'3', '2', '0', 'x', '2', '0', '0', '\000'}, 0, 64U, 5815, 320, 321, 384, 416, 0, 200, 201, 232, 233, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'3', '2', '0', 'x', '2', '4', '0', '\000'}, 0, 64U, 6814, 320, 321, 384, 416, 0, 240, 241, 272, 273, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'4', '0', '0', 'x', '3', '0', '0', '\000'}, 0, 64U, 9910, 400, 401, 464, 496, 0, 300, 301, 332, 333, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'6', '4', '0', 'x', '3', '5', '0', '\000'}, 0, 64U, 16913, 640, 641, 704, 736, 0, 350, 351, 382, 383, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'6', '4', '0', 'x', '4', '0', '0', '\000'}, 0, 64U, 19121, 640, 641, 704, 736, 0, 400, 401, 432, 433, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'6', '4', '0', 'x', '4', '8', '0', '\000'}, 0, 64U, 22654, 640, 641, 704, 736, 0, 480, 481, 512, 513, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'7', '0', '4', 'x', '4', '8', '0', '\000'}, 0, 64U, 24624, 704, 705, 768, 800, 0, 480, 481, 512, 513, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'7', '0', '4', 'x', '5', '7', '6', '\000'}, 0, 64U, 29232, 704, 705, 768, 800, 0, 576, 577, 608, 609, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'7', '2', '0', 'x', '3', '5', '0', '\000'}, 0, 64U, 18751, 720, 721, 784, 816, 0, 350, 351, 382, 383, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'7', '2', '0', 'x', '4', '0', '0', '\000'}, 0, 64U, 21199, 720, 721, 784, 816, 0, 400, 401, 432, 433, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'7', '2', '0', 'x', '4', '8', '0', '\000'}, 0, 64U, 25116, 720, 721, 784, 816, 0, 480, 481, 512, 513, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'7', '2', '0', 'x', '5', '4', '0', '\000'}, 0, 64U, 28054, 720, 721, 784, 816, 0, 540, 541, 572, 573, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'7', '2', '0', 'x', '5', '7', '6', '\000'}, 0, 64U, 29816, 720, 721, 784, 816, 0, 576, 577, 608, 609, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'7', '6', '8', 'x', '5', '7', '6', '\000'}, 0, 64U, 31570, 768, 769, 832, 864, 0, 576, 577, 608, 609, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'8', '0', '0', 'x', '6', '0', '0', '\000'}, 0, 64U, 34030, 800, 801, 864, 896, 0, 600, 601, 632, 633, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'8', '3', '2', 'x', '6', '2', '4', '\000'}, 0, 64U, 36581, 832, 833, 896, 928, 0, 624, 625, 656, 657, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'9', '2', '0', 'x', '7', '6', '6', '\000'}, 0, 64U, 48707, 920, 921, 984, 1016, 0, 766, 767, 798, 799, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'1', '0', '2', '4', 'x', '7', '6', '8', '\000'}, 0, 64U, 53827, 1024, 1025, 1088, 1120, 0, 768, 769, 800, 801, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, {{0, 0}, {0U, 3739147998U, 0}, {'1', '2', '8', '0', 'x', '1', '0', '2', '4', '\000'}, 0, 64U, 87265, 1280, 1281, 1344, 1376, 0, 1024, 1025, 1056, 1057, 0, 5U, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}; static void psb_intel_sdvo_get_tv_modes(struct drm_connector *connector ) { struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; struct psb_intel_sdvo_sdtv_resolution_request tv_res ; uint32_t reply ; uint32_t format_map ; int i ; unsigned long _min1 ; unsigned long _min2 ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; bool tmp___4 ; int tmp___5 ; struct drm_display_mode *nmode ; { tmp = intel_attached_sdvo(connector); psb_intel_sdvo = tmp; reply = 0U; format_map = 0U; format_map = (uint32_t )(1 << psb_intel_sdvo->tv_format_index); _min1 = 4UL; _min2 = 3UL; memcpy((void *)(& tv_res), (void const *)(& format_map), _min1 < _min2 ? _min1 : _min2); tmp___0 = psb_intel_sdvo_set_target_output(psb_intel_sdvo, (int )psb_intel_sdvo->attached_output); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return; } else { } tmp___2 = psb_intel_sdvo_write_cmd(psb_intel_sdvo, 131, (void const *)(& tv_res), 3); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { return; } else { } tmp___4 = psb_intel_sdvo_read_response(psb_intel_sdvo, (void *)(& reply), 3); if (tmp___4) { tmp___5 = 0; } else { tmp___5 = 1; } if (tmp___5) { return; } else { } i = 0; goto ldv_42411; ldv_42410: ; if (((uint32_t )(1 << i) & reply) != 0U) { nmode = drm_mode_duplicate(connector->dev, (struct drm_display_mode const *)(& sdvo_tv_modes) + (unsigned long )i); if ((unsigned long )nmode != (unsigned long )((struct drm_display_mode *)0)) { drm_mode_probed_add(connector, nmode); } else { } } else { } i = i + 1; ldv_42411: ; if ((unsigned int )i <= 18U) { goto ldv_42410; } else { } return; } } static void psb_intel_sdvo_get_lvds_modes(struct drm_connector *connector ) { struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; struct drm_psb_private *dev_priv ; struct drm_display_mode *newmode ; int tmp___0 ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; { tmp = intel_attached_sdvo(connector); psb_intel_sdvo = tmp; dev_priv = (struct drm_psb_private *)(connector->dev)->dev_private; psb_intel_ddc_get_modes(connector, psb_intel_sdvo->i2c); tmp___0 = list_empty((struct list_head const *)(& connector->probed_modes)); if (tmp___0 == 0) { goto end; } else { } if ((unsigned long )dev_priv->sdvo_lvds_vbt_mode != (unsigned long )((struct drm_display_mode *)0)) { newmode = drm_mode_duplicate(connector->dev, (struct drm_display_mode const *)dev_priv->sdvo_lvds_vbt_mode); if ((unsigned long )newmode != (unsigned long )((struct drm_display_mode *)0)) { newmode->type = 72U; drm_mode_probed_add(connector, newmode); } else { } } else { } end: __mptr = (struct list_head const *)connector->probed_modes.next; newmode = (struct drm_display_mode *)__mptr; goto ldv_42426; ldv_42425: ; if ((newmode->type & 8U) != 0U) { psb_intel_sdvo->sdvo_lvds_fixed_mode = drm_mode_duplicate(connector->dev, (struct drm_display_mode const *)newmode); drm_mode_set_crtcinfo(psb_intel_sdvo->sdvo_lvds_fixed_mode, 0); psb_intel_sdvo->is_lvds = 1; goto ldv_42424; } else { } __mptr___0 = (struct list_head const *)newmode->head.next; newmode = (struct drm_display_mode *)__mptr___0; ldv_42426: ; if ((unsigned long )(& newmode->head) != (unsigned long )(& connector->probed_modes)) { goto ldv_42425; } else { } ldv_42424: ; return; } } static int psb_intel_sdvo_get_modes(struct drm_connector *connector ) { struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; struct psb_intel_sdvo_connector *tmp ; int tmp___0 ; { tmp = to_psb_intel_sdvo_connector(connector); psb_intel_sdvo_connector = tmp; if (((int )psb_intel_sdvo_connector->output_flag & 12) != 0) { psb_intel_sdvo_get_tv_modes(connector); } else if (((int )psb_intel_sdvo_connector->output_flag & 16448) != 0) { psb_intel_sdvo_get_lvds_modes(connector); } else { psb_intel_sdvo_get_ddc_modes(connector); } tmp___0 = list_empty((struct list_head const *)(& connector->probed_modes)); return (tmp___0 == 0); } } static void psb_intel_sdvo_destroy(struct drm_connector *connector ) { { drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree((void const *)connector); return; } } static bool psb_intel_sdvo_detect_hdmi_audio(struct drm_connector *connector ) { struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; struct edid *edid ; bool has_audio ; { tmp = intel_attached_sdvo(connector); psb_intel_sdvo = tmp; has_audio = 0; if (! psb_intel_sdvo->is_hdmi) { return (0); } else { } edid = psb_intel_sdvo_get_edid(connector); if ((unsigned long )edid != (unsigned long )((struct edid *)0) && (int )((signed char )edid->input) < 0) { has_audio = drm_detect_monitor_audio(edid); } else { } return (has_audio); } } static int psb_intel_sdvo_set_property(struct drm_connector *connector , struct drm_property *property , uint64_t val ) { struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; struct psb_intel_sdvo_connector *tmp___0 ; struct drm_psb_private *dev_priv ; uint16_t temp_value ; uint8_t cmd ; int ret ; int i ; bool has_audio ; bool tmp___1 ; int tmp___2 ; struct drm_crtc *crtc ; { tmp = intel_attached_sdvo(connector); psb_intel_sdvo = tmp; tmp___0 = to_psb_intel_sdvo_connector(connector); psb_intel_sdvo_connector = tmp___0; dev_priv = (struct drm_psb_private *)(connector->dev)->dev_private; ret = drm_object_property_set_value(& connector->base, property, val); if (ret != 0) { return (ret); } else { } if ((unsigned long )dev_priv->force_audio_property == (unsigned long )property) { i = (int )val; if (psb_intel_sdvo_connector->force_audio == i) { return (0); } else { } psb_intel_sdvo_connector->force_audio = i; if (i == 0) { has_audio = psb_intel_sdvo_detect_hdmi_audio(connector); } else { has_audio = i > 0; } if ((int )psb_intel_sdvo->has_hdmi_audio == (int )has_audio) { return (0); } else { } psb_intel_sdvo->has_hdmi_audio = has_audio; goto done; } else { } if ((unsigned long )dev_priv->broadcast_rgb_property == (unsigned long )property) { if ((uint64_t )(psb_intel_sdvo->color_range != 0U) == val) { return (0); } else { } psb_intel_sdvo->color_range = val != 0ULL ? 256U : 0U; goto done; } else { } if ((unsigned long )psb_intel_sdvo_connector->tv_format == (unsigned long )property) { if (val > 18ULL) { return (-22); } else { } if (psb_intel_sdvo->tv_format_index == (int )psb_intel_sdvo_connector->tv_format_supported[val]) { return (0); } else { } psb_intel_sdvo->tv_format_index = (int )psb_intel_sdvo_connector->tv_format_supported[val]; goto done; } else if (((int )psb_intel_sdvo_connector->output_flag & 16460) != 0) { temp_value = (uint16_t )val; if ((unsigned long )psb_intel_sdvo_connector->left == (unsigned long )property) { drm_object_property_set_value(& connector->base, psb_intel_sdvo_connector->right, val); if (psb_intel_sdvo_connector->left_margin == (u32 )temp_value) { return (0); } else { } psb_intel_sdvo_connector->left_margin = (u32 )temp_value; psb_intel_sdvo_connector->right_margin = (u32 )temp_value; temp_value = (int )((uint16_t )psb_intel_sdvo_connector->max_hscan) - (int )((uint16_t )psb_intel_sdvo_connector->left_margin); cmd = 99U; goto set_value; } else if ((unsigned long )psb_intel_sdvo_connector->right == (unsigned long )property) { drm_object_property_set_value(& connector->base, psb_intel_sdvo_connector->left, val); if (psb_intel_sdvo_connector->right_margin == (u32 )temp_value) { return (0); } else { } psb_intel_sdvo_connector->left_margin = (u32 )temp_value; psb_intel_sdvo_connector->right_margin = (u32 )temp_value; temp_value = (int )((uint16_t )psb_intel_sdvo_connector->max_hscan) - (int )((uint16_t )psb_intel_sdvo_connector->left_margin); cmd = 99U; goto set_value; } else if ((unsigned long )psb_intel_sdvo_connector->top == (unsigned long )property) { drm_object_property_set_value(& connector->base, psb_intel_sdvo_connector->bottom, val); if (psb_intel_sdvo_connector->top_margin == (u32 )temp_value) { return (0); } else { } psb_intel_sdvo_connector->top_margin = (u32 )temp_value; psb_intel_sdvo_connector->bottom_margin = (u32 )temp_value; temp_value = (int )((uint16_t )psb_intel_sdvo_connector->max_vscan) - (int )((uint16_t )psb_intel_sdvo_connector->top_margin); cmd = 102U; goto set_value; } else if ((unsigned long )psb_intel_sdvo_connector->bottom == (unsigned long )property) { drm_object_property_set_value(& connector->base, psb_intel_sdvo_connector->top, val); if (psb_intel_sdvo_connector->bottom_margin == (u32 )temp_value) { return (0); } else { } psb_intel_sdvo_connector->top_margin = (u32 )temp_value; psb_intel_sdvo_connector->bottom_margin = (u32 )temp_value; temp_value = (int )((uint16_t )psb_intel_sdvo_connector->max_vscan) - (int )((uint16_t )psb_intel_sdvo_connector->top_margin); cmd = 102U; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->hpos == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_hpos == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_hpos < (u32 )temp_value) { return (-22); } else { } cmd = 105U; psb_intel_sdvo_connector->cur_hpos = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->vpos == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_vpos == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_vpos < (u32 )temp_value) { return (-22); } else { } cmd = 108U; psb_intel_sdvo_connector->cur_vpos = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->saturation == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_saturation == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_saturation < (u32 )temp_value) { return (-22); } else { } cmd = 87U; psb_intel_sdvo_connector->cur_saturation = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->contrast == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_contrast == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_contrast < (u32 )temp_value) { return (-22); } else { } cmd = 96U; psb_intel_sdvo_connector->cur_contrast = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->hue == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_hue == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_hue < (u32 )temp_value) { return (-22); } else { } cmd = 90U; psb_intel_sdvo_connector->cur_hue = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->brightness == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_brightness == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_brightness < (u32 )temp_value) { return (-22); } else { } cmd = 93U; psb_intel_sdvo_connector->cur_brightness = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->sharpness == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_sharpness == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_sharpness < (u32 )temp_value) { return (-22); } else { } cmd = 111U; psb_intel_sdvo_connector->cur_sharpness = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->flicker_filter == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_flicker_filter == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_flicker_filter < (u32 )temp_value) { return (-22); } else { } cmd = 79U; psb_intel_sdvo_connector->cur_flicker_filter = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->flicker_filter_2d == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_flicker_filter_2d == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_flicker_filter_2d < (u32 )temp_value) { return (-22); } else { } cmd = 84U; psb_intel_sdvo_connector->cur_flicker_filter_2d = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->flicker_filter_adaptive == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_flicker_filter_adaptive == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_flicker_filter_adaptive < (u32 )temp_value) { return (-22); } else { } cmd = 81U; psb_intel_sdvo_connector->cur_flicker_filter_adaptive = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->tv_chroma_filter == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_tv_chroma_filter == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_tv_chroma_filter < (u32 )temp_value) { return (-22); } else { } cmd = 118U; psb_intel_sdvo_connector->cur_tv_chroma_filter = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->tv_luma_filter == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_tv_luma_filter == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_tv_luma_filter < (u32 )temp_value) { return (-22); } else { } cmd = 121U; psb_intel_sdvo_connector->cur_tv_luma_filter = (u32 )temp_value; goto set_value; } else { } if ((unsigned long )psb_intel_sdvo_connector->dot_crawl == (unsigned long )property) { if (psb_intel_sdvo_connector->cur_dot_crawl == (u32 )temp_value) { return (0); } else { } if (psb_intel_sdvo_connector->max_dot_crawl < (u32 )temp_value) { return (-22); } else { } cmd = 113U; psb_intel_sdvo_connector->cur_dot_crawl = (u32 )temp_value; goto set_value; } else { } } else { } return (-22); set_value: tmp___1 = psb_intel_sdvo_set_value(psb_intel_sdvo, (int )cmd, (void const *)(& temp_value), 2); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (-5); } else { } done: ; if ((unsigned long )psb_intel_sdvo->base.base.crtc != (unsigned long )((struct drm_crtc *)0)) { crtc = psb_intel_sdvo->base.base.crtc; drm_crtc_helper_set_mode(crtc, & crtc->mode, crtc->x, crtc->y, (crtc->primary)->fb); } else { } return (0); } } static void psb_intel_sdvo_save(struct drm_connector *connector ) { struct drm_device *dev ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct psb_intel_sdvo *sdvo ; struct psb_intel_sdvo *tmp___0 ; { dev = connector->dev; tmp = gma_attached_encoder(connector); gma_encoder = tmp; tmp___0 = to_psb_intel_sdvo(& gma_encoder->base); sdvo = tmp___0; sdvo->saveSDVO = REGISTER_READ(dev, (uint32_t )sdvo->sdvo_reg); return; } } static void psb_intel_sdvo_restore(struct drm_connector *connector ) { struct drm_device *dev ; struct drm_encoder *encoder ; struct gma_encoder *tmp ; struct psb_intel_sdvo *sdvo ; struct psb_intel_sdvo *tmp___0 ; struct drm_crtc *crtc ; { dev = connector->dev; tmp = gma_attached_encoder(connector); encoder = & tmp->base; tmp___0 = to_psb_intel_sdvo(encoder); sdvo = tmp___0; crtc = encoder->crtc; REGISTER_WRITE(dev, (uint32_t )sdvo->sdvo_reg, sdvo->saveSDVO); if ((unsigned int )connector->status == 1U) { drm_crtc_helper_set_mode(crtc, & crtc->mode, crtc->x, crtc->y, (struct drm_framebuffer *)0); } else { } return; } } static struct drm_encoder_helper_funcs const psb_intel_sdvo_helper_funcs = {& psb_intel_sdvo_dpms, 0, 0, & psb_intel_sdvo_mode_fixup, & gma_encoder_prepare, & gma_encoder_commit, & psb_intel_sdvo_mode_set, 0, 0, 0, 0, 0}; static struct drm_connector_funcs const psb_intel_sdvo_connector_funcs = {& drm_helper_connector_dpms, & psb_intel_sdvo_save, & psb_intel_sdvo_restore, 0, & psb_intel_sdvo_detect, & drm_helper_probe_single_connector_modes, & psb_intel_sdvo_set_property, & psb_intel_sdvo_destroy, 0, 0, 0, 0, 0}; static struct drm_connector_helper_funcs const psb_intel_sdvo_connector_helper_funcs = {& psb_intel_sdvo_get_modes, (enum drm_mode_status (*)(struct drm_connector * , struct drm_display_mode * ))(& psb_intel_sdvo_mode_valid), & gma_best_encoder}; static void psb_intel_sdvo_enc_destroy(struct drm_encoder *encoder ) { struct psb_intel_sdvo *psb_intel_sdvo ; struct psb_intel_sdvo *tmp ; { tmp = to_psb_intel_sdvo(encoder); psb_intel_sdvo = tmp; if ((unsigned long )psb_intel_sdvo->sdvo_lvds_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { drm_mode_destroy(encoder->dev, psb_intel_sdvo->sdvo_lvds_fixed_mode); } else { } i2c_del_adapter(& psb_intel_sdvo->ddc); gma_encoder_destroy(encoder); return; } } static struct drm_encoder_funcs const psb_intel_sdvo_enc_funcs = {0, & psb_intel_sdvo_enc_destroy}; static void psb_intel_sdvo_guess_ddc_bus(struct psb_intel_sdvo *sdvo ) { { sdvo->ddc_bus = 2U; return; } } static void psb_intel_sdvo_select_ddc_bus(struct drm_psb_private *dev_priv , struct psb_intel_sdvo *sdvo , u32 reg ) { struct sdvo_device_mapping *mapping ; { if (reg == 397632U) { mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings); } else { mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings) + 1UL; } if ((unsigned int )mapping->initialized != 0U) { sdvo->ddc_bus = (uint8_t )(1 << ((int )mapping->ddc_pin >> 4)); } else { psb_intel_sdvo_guess_ddc_bus(sdvo); } return; } } static void psb_intel_sdvo_select_i2c_bus(struct drm_psb_private *dev_priv , struct psb_intel_sdvo *sdvo , u32 reg ) { struct sdvo_device_mapping *mapping ; u8 pin ; u8 speed ; { if (reg == 397632U) { mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings); } else { mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings) + 1UL; } pin = 5U; speed = 3U; if ((unsigned int )mapping->initialized != 0U) { pin = mapping->i2c_pin; speed = mapping->i2c_speed; } else { } if ((unsigned int )pin <= 7U) { sdvo->i2c = & (dev_priv->gmbus + (unsigned long )pin)->adapter; gma_intel_gmbus_set_speed(sdvo->i2c, (int )speed); gma_intel_gmbus_force_bit(sdvo->i2c, 1); } else { sdvo->i2c = & (dev_priv->gmbus + 5UL)->adapter; } return; } } static bool psb_intel_sdvo_is_hdmi_connector(struct psb_intel_sdvo *psb_intel_sdvo , int device ) { bool tmp ; { tmp = psb_intel_sdvo_check_supp_encode(psb_intel_sdvo); return (tmp); } } static u8 psb_intel_sdvo_get_slave_addr(struct drm_device *dev , int sdvo_reg ) { struct drm_psb_private *dev_priv ; struct sdvo_device_mapping *my_mapping ; struct sdvo_device_mapping *other_mapping ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if (sdvo_reg == 397632) { my_mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings); other_mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings) + 1UL; } else { my_mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings) + 1UL; other_mapping = (struct sdvo_device_mapping *)(& dev_priv->sdvo_mappings); } if ((unsigned int )my_mapping->slave_addr != 0U) { return (my_mapping->slave_addr); } else { } if ((unsigned int )other_mapping->slave_addr != 0U) { if ((unsigned int )other_mapping->slave_addr == 112U) { return (114U); } else { return (112U); } } else { } if (sdvo_reg == 397632) { return (112U); } else { return (114U); } } } static void psb_intel_sdvo_connector_init(struct psb_intel_sdvo_connector *connector , struct psb_intel_sdvo *encoder ) { { drm_connector_init(encoder->base.base.dev, & connector->base.base, & psb_intel_sdvo_connector_funcs, connector->base.base.connector_type); drm_connector_helper_add(& connector->base.base, & psb_intel_sdvo_connector_helper_funcs); connector->base.base.interlace_allowed = 0; connector->base.base.doublescan_allowed = 0; connector->base.base.display_info.subpixel_order = 1; gma_connector_attach_encoder(& connector->base, & encoder->base); drm_connector_register(& connector->base.base); return; } } static void psb_intel_sdvo_add_hdmi_properties(struct psb_intel_sdvo_connector *connector ) { { return; } } static bool psb_intel_sdvo_dvi_init(struct psb_intel_sdvo *psb_intel_sdvo , int device ) { struct drm_encoder *encoder ; struct drm_connector *connector ; struct gma_connector *intel_connector ; struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; void *tmp ; bool tmp___0 ; { encoder = & psb_intel_sdvo->base.base; tmp = kzalloc(1248UL, 208U); psb_intel_sdvo_connector = (struct psb_intel_sdvo_connector *)tmp; if ((unsigned long )psb_intel_sdvo_connector == (unsigned long )((struct psb_intel_sdvo_connector *)0)) { return (0); } else { } if (device == 0) { psb_intel_sdvo->controlled_output = (uint16_t )((unsigned int )psb_intel_sdvo->controlled_output | 1U); psb_intel_sdvo_connector->output_flag = 1U; } else if (device == 1) { psb_intel_sdvo->controlled_output = (uint16_t )((unsigned int )psb_intel_sdvo->controlled_output | 256U); psb_intel_sdvo_connector->output_flag = 256U; } else { } intel_connector = & psb_intel_sdvo_connector->base; connector = & intel_connector->base; encoder->encoder_type = 2; connector->connector_type = 3; tmp___0 = psb_intel_sdvo_is_hdmi_connector(psb_intel_sdvo, device); if ((int )tmp___0) { connector->connector_type = 11; psb_intel_sdvo->is_hdmi = 1; } else { } psb_intel_sdvo->base.clone_mask = 576; psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); if ((int )psb_intel_sdvo->is_hdmi) { psb_intel_sdvo_add_hdmi_properties(psb_intel_sdvo_connector); } else { } return (1); } } static bool psb_intel_sdvo_tv_init(struct psb_intel_sdvo *psb_intel_sdvo , int type ) { struct drm_encoder *encoder ; struct drm_connector *connector ; struct gma_connector *intel_connector ; struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; void *tmp ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; { encoder = & psb_intel_sdvo->base.base; tmp = kzalloc(1248UL, 208U); psb_intel_sdvo_connector = (struct psb_intel_sdvo_connector *)tmp; if ((unsigned long )psb_intel_sdvo_connector == (unsigned long )((struct psb_intel_sdvo_connector *)0)) { return (0); } else { } intel_connector = & psb_intel_sdvo_connector->base; connector = & intel_connector->base; encoder->encoder_type = 4; connector->connector_type = 6; psb_intel_sdvo->controlled_output = (uint16_t )((int )((short )psb_intel_sdvo->controlled_output) | (int )((short )type)); psb_intel_sdvo_connector->output_flag = (uint16_t )type; psb_intel_sdvo->is_tv = 1; psb_intel_sdvo->base.needs_tv_clock = 1; psb_intel_sdvo->base.clone_mask = 128; psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); tmp___0 = psb_intel_sdvo_tv_create_property(psb_intel_sdvo, psb_intel_sdvo_connector, type); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { goto err; } else { } tmp___2 = psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { goto err; } else { } return (1); err: psb_intel_sdvo_destroy(connector); return (0); } } static bool psb_intel_sdvo_analog_init(struct psb_intel_sdvo *psb_intel_sdvo , int device ) { struct drm_encoder *encoder ; struct drm_connector *connector ; struct gma_connector *intel_connector ; struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; void *tmp ; { encoder = & psb_intel_sdvo->base.base; tmp = kzalloc(1248UL, 208U); psb_intel_sdvo_connector = (struct psb_intel_sdvo_connector *)tmp; if ((unsigned long )psb_intel_sdvo_connector == (unsigned long )((struct psb_intel_sdvo_connector *)0)) { return (0); } else { } intel_connector = & psb_intel_sdvo_connector->base; connector = & intel_connector->base; connector->polled = 2U; encoder->encoder_type = 1; connector->connector_type = 1; if (device == 0) { psb_intel_sdvo->controlled_output = (uint16_t )((unsigned int )psb_intel_sdvo->controlled_output | 2U); psb_intel_sdvo_connector->output_flag = 2U; } else if (device == 1) { psb_intel_sdvo->controlled_output = (uint16_t )((unsigned int )psb_intel_sdvo->controlled_output | 512U); psb_intel_sdvo_connector->output_flag = 512U; } else { } psb_intel_sdvo->base.clone_mask = 576; psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); return (1); } } static bool psb_intel_sdvo_lvds_init(struct psb_intel_sdvo *psb_intel_sdvo , int device ) { struct drm_encoder *encoder ; struct drm_connector *connector ; struct gma_connector *intel_connector ; struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ; void *tmp ; bool tmp___0 ; int tmp___1 ; { encoder = & psb_intel_sdvo->base.base; tmp = kzalloc(1248UL, 208U); psb_intel_sdvo_connector = (struct psb_intel_sdvo_connector *)tmp; if ((unsigned long )psb_intel_sdvo_connector == (unsigned long )((struct psb_intel_sdvo_connector *)0)) { return (0); } else { } intel_connector = & psb_intel_sdvo_connector->base; connector = & intel_connector->base; encoder->encoder_type = 3; connector->connector_type = 7; if (device == 0) { psb_intel_sdvo->controlled_output = (uint16_t )((unsigned int )psb_intel_sdvo->controlled_output | 64U); psb_intel_sdvo_connector->output_flag = 64U; } else if (device == 1) { psb_intel_sdvo->controlled_output = (uint16_t )((unsigned int )psb_intel_sdvo->controlled_output | 16384U); psb_intel_sdvo_connector->output_flag = 16384U; } else { } psb_intel_sdvo->base.clone_mask = 768; psb_intel_sdvo_connector_init(psb_intel_sdvo_connector, psb_intel_sdvo); tmp___0 = psb_intel_sdvo_create_enhance_property(psb_intel_sdvo, psb_intel_sdvo_connector); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { goto err; } else { } return (1); err: psb_intel_sdvo_destroy(connector); return (0); } } static bool psb_intel_sdvo_output_setup(struct psb_intel_sdvo *psb_intel_sdvo , uint16_t flags ) { bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; bool tmp___3 ; int tmp___4 ; bool tmp___5 ; int tmp___6 ; bool tmp___7 ; int tmp___8 ; bool tmp___9 ; int tmp___10 ; bool tmp___11 ; int tmp___12 ; bool tmp___13 ; int tmp___14 ; unsigned char bytes[2U] ; long tmp___15 ; { psb_intel_sdvo->is_tv = 0; psb_intel_sdvo->base.needs_tv_clock = 0; psb_intel_sdvo->is_lvds = 0; if ((int )flags & 1) { tmp = psb_intel_sdvo_dvi_init(psb_intel_sdvo, 0); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } } else { } if (((int )flags & 257) == 257) { tmp___1 = psb_intel_sdvo_dvi_init(psb_intel_sdvo, 1); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (0); } else { } } else { } if (((int )flags & 8) != 0) { tmp___3 = psb_intel_sdvo_tv_init(psb_intel_sdvo, 8); if (tmp___3) { tmp___4 = 0; } else { tmp___4 = 1; } if (tmp___4) { return (0); } else { } } else { } if (((int )flags & 4) != 0) { tmp___5 = psb_intel_sdvo_tv_init(psb_intel_sdvo, 4); if (tmp___5) { tmp___6 = 0; } else { tmp___6 = 1; } if (tmp___6) { return (0); } else { } } else { } if (((int )flags & 2) != 0) { tmp___7 = psb_intel_sdvo_analog_init(psb_intel_sdvo, 0); if (tmp___7) { tmp___8 = 0; } else { tmp___8 = 1; } if (tmp___8) { return (0); } else { } } else { } if (((int )flags & 514) == 514) { tmp___9 = psb_intel_sdvo_analog_init(psb_intel_sdvo, 1); if (tmp___9) { tmp___10 = 0; } else { tmp___10 = 1; } if (tmp___10) { return (0); } else { } } else { } if (((int )flags & 64) != 0) { tmp___11 = psb_intel_sdvo_lvds_init(psb_intel_sdvo, 0); if (tmp___11) { tmp___12 = 0; } else { tmp___12 = 1; } if (tmp___12) { return (0); } else { } } else { } if (((int )flags & 16448) == 16448) { tmp___13 = psb_intel_sdvo_lvds_init(psb_intel_sdvo, 1); if (tmp___13) { tmp___14 = 0; } else { tmp___14 = 1; } if (tmp___14) { return (0); } else { } } else { } if (((int )flags & 17231) == 0) { psb_intel_sdvo->controlled_output = 0U; memcpy((void *)(& bytes), (void const *)(& psb_intel_sdvo->caps.output_flags), 2UL); tmp___15 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___15 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_output_setup", "%s: Unknown SDVO output type (0x%02x%02x)\n", psb_intel_sdvo->sdvo_reg == 397632 ? (char *)"SDVOB" : (char *)"SDVOC", (int )bytes[0], (int )bytes[1]); } else { } return (0); } else { } psb_intel_sdvo->base.crtc_mask = 3; return (1); } } static bool psb_intel_sdvo_tv_create_property(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_connector *psb_intel_sdvo_connector , int type ) { struct drm_device *dev ; struct psb_intel_sdvo_tv_format format ; uint32_t format_map ; uint32_t i ; bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; unsigned long _min1 ; unsigned long _min2 ; int tmp___3 ; { dev = psb_intel_sdvo->base.base.dev; tmp = psb_intel_sdvo_set_target_output(psb_intel_sdvo, (int )((u16 )type)); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } tmp___1 = psb_intel_sdvo_get_value(psb_intel_sdvo, 39, (void *)(& format), 6); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (0); } else { } _min1 = 4UL; _min2 = 6UL; memcpy((void *)(& format_map), (void const *)(& format), _min1 < _min2 ? _min1 : _min2); if (format_map == 0U) { return (0); } else { } psb_intel_sdvo_connector->format_supported_num = 0; i = 0U; goto ldv_42565; ldv_42564: ; if (((uint32_t )(1 << (int )i) & format_map) != 0U) { tmp___3 = psb_intel_sdvo_connector->format_supported_num; psb_intel_sdvo_connector->format_supported_num = psb_intel_sdvo_connector->format_supported_num + 1; psb_intel_sdvo_connector->tv_format_supported[tmp___3] = (u8 )i; } else { } i = i + 1U; ldv_42565: ; if (i <= 18U) { goto ldv_42564; } else { } psb_intel_sdvo_connector->tv_format = drm_property_create(dev, 8, "mode", psb_intel_sdvo_connector->format_supported_num); if ((unsigned long )psb_intel_sdvo_connector->tv_format == (unsigned long )((struct drm_property *)0)) { return (0); } else { } i = 0U; goto ldv_42568; ldv_42567: drm_property_add_enum(psb_intel_sdvo_connector->tv_format, (int )i, (uint64_t )i, tv_format_names[(int )psb_intel_sdvo_connector->tv_format_supported[i]]); i = i + 1U; ldv_42568: ; if ((uint32_t )psb_intel_sdvo_connector->format_supported_num > i) { goto ldv_42567; } else { } psb_intel_sdvo->tv_format_index = (int )psb_intel_sdvo_connector->tv_format_supported[0]; drm_object_attach_property(& psb_intel_sdvo_connector->base.base.base, psb_intel_sdvo_connector->tv_format, 0ULL); return (1); } } static bool psb_intel_sdvo_create_enhance_property_tv(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_connector *psb_intel_sdvo_connector , struct psb_intel_sdvo_enhancements_reply enhancements ) { struct drm_device *dev ; struct drm_connector *connector ; uint16_t response ; uint16_t data_value[2U] ; bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; long tmp___3 ; bool tmp___4 ; int tmp___5 ; bool tmp___6 ; int tmp___7 ; long tmp___8 ; bool tmp___9 ; int tmp___10 ; bool tmp___11 ; int tmp___12 ; long tmp___13 ; bool tmp___14 ; int tmp___15 ; bool tmp___16 ; int tmp___17 ; long tmp___18 ; bool tmp___19 ; int tmp___20 ; bool tmp___21 ; int tmp___22 ; long tmp___23 ; bool tmp___24 ; int tmp___25 ; bool tmp___26 ; int tmp___27 ; long tmp___28 ; bool tmp___29 ; int tmp___30 ; bool tmp___31 ; int tmp___32 ; long tmp___33 ; bool tmp___34 ; int tmp___35 ; bool tmp___36 ; int tmp___37 ; long tmp___38 ; bool tmp___39 ; int tmp___40 ; bool tmp___41 ; int tmp___42 ; long tmp___43 ; bool tmp___44 ; int tmp___45 ; bool tmp___46 ; int tmp___47 ; long tmp___48 ; bool tmp___49 ; int tmp___50 ; bool tmp___51 ; int tmp___52 ; long tmp___53 ; bool tmp___54 ; int tmp___55 ; bool tmp___56 ; int tmp___57 ; long tmp___58 ; bool tmp___59 ; int tmp___60 ; bool tmp___61 ; int tmp___62 ; long tmp___63 ; bool tmp___64 ; int tmp___65 ; bool tmp___66 ; int tmp___67 ; long tmp___68 ; bool tmp___69 ; int tmp___70 ; long tmp___71 ; { dev = psb_intel_sdvo->base.base.dev; connector = & psb_intel_sdvo_connector->base.base; if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp = psb_intel_sdvo_get_value(psb_intel_sdvo, 97, (void *)(& data_value), 4); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } tmp___1 = psb_intel_sdvo_get_value(psb_intel_sdvo, 98, (void *)(& response), 2); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (0); } else { } psb_intel_sdvo_connector->max_hscan = (u32 )data_value[0]; psb_intel_sdvo_connector->left_margin = (u32 )((int )data_value[0] - (int )response); psb_intel_sdvo_connector->right_margin = psb_intel_sdvo_connector->left_margin; psb_intel_sdvo_connector->left = drm_property_create_range(dev, 0, "left_margin", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->left == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->left, (uint64_t )psb_intel_sdvo_connector->left_margin); psb_intel_sdvo_connector->right = drm_property_create_range(dev, 0, "right_margin", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->right == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->right, (uint64_t )psb_intel_sdvo_connector->right_margin); tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "h_overscan: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 1UL) != 0U) { tmp___4 = psb_intel_sdvo_get_value(psb_intel_sdvo, 100, (void *)(& data_value), 4); if (tmp___4) { tmp___5 = 0; } else { tmp___5 = 1; } if (tmp___5) { return (0); } else { } tmp___6 = psb_intel_sdvo_get_value(psb_intel_sdvo, 101, (void *)(& response), 2); if (tmp___6) { tmp___7 = 0; } else { tmp___7 = 1; } if (tmp___7) { return (0); } else { } psb_intel_sdvo_connector->max_vscan = (u32 )data_value[0]; psb_intel_sdvo_connector->top_margin = (u32 )((int )data_value[0] - (int )response); psb_intel_sdvo_connector->bottom_margin = psb_intel_sdvo_connector->top_margin; psb_intel_sdvo_connector->top = drm_property_create_range(dev, 0, "top_margin", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->top == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->top, (uint64_t )psb_intel_sdvo_connector->top_margin); psb_intel_sdvo_connector->bottom = drm_property_create_range(dev, 0, "bottom_margin", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->bottom == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->bottom, (uint64_t )psb_intel_sdvo_connector->bottom_margin); tmp___8 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___8 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "v_overscan: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 1UL) != 0U) { tmp___9 = psb_intel_sdvo_get_value(psb_intel_sdvo, 103, (void *)(& data_value), 4); if (tmp___9) { tmp___10 = 0; } else { tmp___10 = 1; } if (tmp___10) { return (0); } else { tmp___11 = psb_intel_sdvo_get_value(psb_intel_sdvo, 104, (void *)(& response), 2); if (tmp___11) { tmp___12 = 0; } else { tmp___12 = 1; } if (tmp___12) { return (0); } else { } } psb_intel_sdvo_connector->max_hpos = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_hpos = (u32 )response; psb_intel_sdvo_connector->hpos = drm_property_create_range(dev, 0, "hpos", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->hpos == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->hpos, (uint64_t )psb_intel_sdvo_connector->cur_hpos); tmp___13 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___13 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "hpos: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 1UL) != 0U) { tmp___14 = psb_intel_sdvo_get_value(psb_intel_sdvo, 106, (void *)(& data_value), 4); if (tmp___14) { tmp___15 = 0; } else { tmp___15 = 1; } if (tmp___15) { return (0); } else { tmp___16 = psb_intel_sdvo_get_value(psb_intel_sdvo, 107, (void *)(& response), 2); if (tmp___16) { tmp___17 = 0; } else { tmp___17 = 1; } if (tmp___17) { return (0); } else { } } psb_intel_sdvo_connector->max_vpos = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_vpos = (u32 )response; psb_intel_sdvo_connector->vpos = drm_property_create_range(dev, 0, "vpos", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->vpos == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->vpos, (uint64_t )psb_intel_sdvo_connector->cur_vpos); tmp___18 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___18 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "vpos: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp___19 = psb_intel_sdvo_get_value(psb_intel_sdvo, 85, (void *)(& data_value), 4); if (tmp___19) { tmp___20 = 0; } else { tmp___20 = 1; } if (tmp___20) { return (0); } else { tmp___21 = psb_intel_sdvo_get_value(psb_intel_sdvo, 86, (void *)(& response), 2); if (tmp___21) { tmp___22 = 0; } else { tmp___22 = 1; } if (tmp___22) { return (0); } else { } } psb_intel_sdvo_connector->max_saturation = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_saturation = (u32 )response; psb_intel_sdvo_connector->saturation = drm_property_create_range(dev, 0, "saturation", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->saturation == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->saturation, (uint64_t )psb_intel_sdvo_connector->cur_saturation); tmp___23 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___23 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "saturation: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp___24 = psb_intel_sdvo_get_value(psb_intel_sdvo, 94, (void *)(& data_value), 4); if (tmp___24) { tmp___25 = 0; } else { tmp___25 = 1; } if (tmp___25) { return (0); } else { tmp___26 = psb_intel_sdvo_get_value(psb_intel_sdvo, 95, (void *)(& response), 2); if (tmp___26) { tmp___27 = 0; } else { tmp___27 = 1; } if (tmp___27) { return (0); } else { } } psb_intel_sdvo_connector->max_contrast = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_contrast = (u32 )response; psb_intel_sdvo_connector->contrast = drm_property_create_range(dev, 0, "contrast", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->contrast == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->contrast, (uint64_t )psb_intel_sdvo_connector->cur_contrast); tmp___28 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___28 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "contrast: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp___29 = psb_intel_sdvo_get_value(psb_intel_sdvo, 88, (void *)(& data_value), 4); if (tmp___29) { tmp___30 = 0; } else { tmp___30 = 1; } if (tmp___30) { return (0); } else { tmp___31 = psb_intel_sdvo_get_value(psb_intel_sdvo, 89, (void *)(& response), 2); if (tmp___31) { tmp___32 = 0; } else { tmp___32 = 1; } if (tmp___32) { return (0); } else { } } psb_intel_sdvo_connector->max_hue = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_hue = (u32 )response; psb_intel_sdvo_connector->hue = drm_property_create_range(dev, 0, "hue", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->hue == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->hue, (uint64_t )psb_intel_sdvo_connector->cur_hue); tmp___33 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___33 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "hue: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 1UL) != 0U) { tmp___34 = psb_intel_sdvo_get_value(psb_intel_sdvo, 109, (void *)(& data_value), 4); if (tmp___34) { tmp___35 = 0; } else { tmp___35 = 1; } if (tmp___35) { return (0); } else { tmp___36 = psb_intel_sdvo_get_value(psb_intel_sdvo, 110, (void *)(& response), 2); if (tmp___36) { tmp___37 = 0; } else { tmp___37 = 1; } if (tmp___37) { return (0); } else { } } psb_intel_sdvo_connector->max_sharpness = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_sharpness = (u32 )response; psb_intel_sdvo_connector->sharpness = drm_property_create_range(dev, 0, "sharpness", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->sharpness == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->sharpness, (uint64_t )psb_intel_sdvo_connector->cur_sharpness); tmp___38 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___38 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "sharpness: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp___39 = psb_intel_sdvo_get_value(psb_intel_sdvo, 91, (void *)(& data_value), 4); if (tmp___39) { tmp___40 = 0; } else { tmp___40 = 1; } if (tmp___40) { return (0); } else { tmp___41 = psb_intel_sdvo_get_value(psb_intel_sdvo, 92, (void *)(& response), 2); if (tmp___41) { tmp___42 = 0; } else { tmp___42 = 1; } if (tmp___42) { return (0); } else { } } psb_intel_sdvo_connector->max_brightness = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_brightness = (u32 )response; psb_intel_sdvo_connector->brightness = drm_property_create_range(dev, 0, "brightness", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->brightness == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->brightness, (uint64_t )psb_intel_sdvo_connector->cur_brightness); tmp___43 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___43 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "brightness: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp___44 = psb_intel_sdvo_get_value(psb_intel_sdvo, 77, (void *)(& data_value), 4); if (tmp___44) { tmp___45 = 0; } else { tmp___45 = 1; } if (tmp___45) { return (0); } else { tmp___46 = psb_intel_sdvo_get_value(psb_intel_sdvo, 78, (void *)(& response), 2); if (tmp___46) { tmp___47 = 0; } else { tmp___47 = 1; } if (tmp___47) { return (0); } else { } } psb_intel_sdvo_connector->max_flicker_filter = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_flicker_filter = (u32 )response; psb_intel_sdvo_connector->flicker_filter = drm_property_create_range(dev, 0, "flicker_filter", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->flicker_filter == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->flicker_filter, (uint64_t )psb_intel_sdvo_connector->cur_flicker_filter); tmp___48 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___48 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "flicker_filter: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp___49 = psb_intel_sdvo_get_value(psb_intel_sdvo, 123, (void *)(& data_value), 4); if (tmp___49) { tmp___50 = 0; } else { tmp___50 = 1; } if (tmp___50) { return (0); } else { tmp___51 = psb_intel_sdvo_get_value(psb_intel_sdvo, 80, (void *)(& response), 2); if (tmp___51) { tmp___52 = 0; } else { tmp___52 = 1; } if (tmp___52) { return (0); } else { } } psb_intel_sdvo_connector->max_flicker_filter_adaptive = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_flicker_filter_adaptive = (u32 )response; psb_intel_sdvo_connector->flicker_filter_adaptive = drm_property_create_range(dev, 0, "flicker_filter_adaptive", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->flicker_filter_adaptive == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->flicker_filter_adaptive, (uint64_t )psb_intel_sdvo_connector->cur_flicker_filter_adaptive); tmp___53 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___53 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "flicker_filter_adaptive: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp___54 = psb_intel_sdvo_get_value(psb_intel_sdvo, 82, (void *)(& data_value), 4); if (tmp___54) { tmp___55 = 0; } else { tmp___55 = 1; } if (tmp___55) { return (0); } else { tmp___56 = psb_intel_sdvo_get_value(psb_intel_sdvo, 83, (void *)(& response), 2); if (tmp___56) { tmp___57 = 0; } else { tmp___57 = 1; } if (tmp___57) { return (0); } else { } } psb_intel_sdvo_connector->max_flicker_filter_2d = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_flicker_filter_2d = (u32 )response; psb_intel_sdvo_connector->flicker_filter_2d = drm_property_create_range(dev, 0, "flicker_filter_2d", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->flicker_filter_2d == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->flicker_filter_2d, (uint64_t )psb_intel_sdvo_connector->cur_flicker_filter_2d); tmp___58 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___58 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "flicker_filter_2d: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 1UL) != 0U) { tmp___59 = psb_intel_sdvo_get_value(psb_intel_sdvo, 116, (void *)(& data_value), 4); if (tmp___59) { tmp___60 = 0; } else { tmp___60 = 1; } if (tmp___60) { return (0); } else { tmp___61 = psb_intel_sdvo_get_value(psb_intel_sdvo, 117, (void *)(& response), 2); if (tmp___61) { tmp___62 = 0; } else { tmp___62 = 1; } if (tmp___62) { return (0); } else { } } psb_intel_sdvo_connector->max_tv_chroma_filter = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_tv_chroma_filter = (u32 )response; psb_intel_sdvo_connector->tv_chroma_filter = drm_property_create_range(dev, 0, "tv_chroma_filter", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->tv_chroma_filter == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->tv_chroma_filter, (uint64_t )psb_intel_sdvo_connector->cur_tv_chroma_filter); tmp___63 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___63 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "tv_chroma_filter: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 1UL) != 0U) { tmp___64 = psb_intel_sdvo_get_value(psb_intel_sdvo, 119, (void *)(& data_value), 4); if (tmp___64) { tmp___65 = 0; } else { tmp___65 = 1; } if (tmp___65) { return (0); } else { tmp___66 = psb_intel_sdvo_get_value(psb_intel_sdvo, 120, (void *)(& response), 2); if (tmp___66) { tmp___67 = 0; } else { tmp___67 = 1; } if (tmp___67) { return (0); } else { } } psb_intel_sdvo_connector->max_tv_luma_filter = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_tv_luma_filter = (u32 )response; psb_intel_sdvo_connector->tv_luma_filter = drm_property_create_range(dev, 0, "tv_luma_filter", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->tv_luma_filter == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->tv_luma_filter, (uint64_t )psb_intel_sdvo_connector->cur_tv_luma_filter); tmp___68 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___68 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "tv_luma_filter: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } if ((unsigned int )*((unsigned char *)(& enhancements) + 1UL) != 0U) { tmp___69 = psb_intel_sdvo_get_value(psb_intel_sdvo, 112, (void *)(& response), 2); if (tmp___69) { tmp___70 = 0; } else { tmp___70 = 1; } if (tmp___70) { return (0); } else { } psb_intel_sdvo_connector->max_dot_crawl = 1U; psb_intel_sdvo_connector->cur_dot_crawl = (u32 )response & 1U; psb_intel_sdvo_connector->dot_crawl = drm_property_create_range(dev, 0, "dot_crawl", 0ULL, 1ULL); if ((unsigned long )psb_intel_sdvo_connector->dot_crawl == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->dot_crawl, (uint64_t )psb_intel_sdvo_connector->cur_dot_crawl); tmp___71 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___71 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_tv", "dot crawl: current %d\n", (int )response); } else { } } else { } return (1); } } static bool psb_intel_sdvo_create_enhance_property_lvds(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_connector *psb_intel_sdvo_connector , struct psb_intel_sdvo_enhancements_reply enhancements ) { struct drm_device *dev ; struct drm_connector *connector ; uint16_t response ; uint16_t data_value[2U] ; bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; long tmp___3 ; { dev = psb_intel_sdvo->base.base.dev; connector = & psb_intel_sdvo_connector->base.base; if ((unsigned int )*((unsigned char *)(& enhancements) + 0UL) != 0U) { tmp = psb_intel_sdvo_get_value(psb_intel_sdvo, 91, (void *)(& data_value), 4); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { tmp___1 = psb_intel_sdvo_get_value(psb_intel_sdvo, 92, (void *)(& response), 2); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (0); } else { } } psb_intel_sdvo_connector->max_brightness = (u32 )data_value[0]; psb_intel_sdvo_connector->cur_brightness = (u32 )response; psb_intel_sdvo_connector->brightness = drm_property_create_range(dev, 0, "brightness", 0ULL, (uint64_t )data_value[0]); if ((unsigned long )psb_intel_sdvo_connector->brightness == (unsigned long )((struct drm_property *)0)) { return (0); } else { } drm_object_attach_property(& connector->base, psb_intel_sdvo_connector->brightness, (uint64_t )psb_intel_sdvo_connector->cur_brightness); tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property_lvds", "brightness: max %d, default %d, current %d\n", (int )data_value[0], (int )data_value[1], (int )response); } else { } } else { } return (1); } } static bool psb_intel_sdvo_create_enhance_property(struct psb_intel_sdvo *psb_intel_sdvo , struct psb_intel_sdvo_connector *psb_intel_sdvo_connector ) { union __anonunion_enhancements_280 enhancements ; long tmp ; bool tmp___0 ; bool tmp___1 ; { enhancements.response = 0U; psb_intel_sdvo_get_value(psb_intel_sdvo, 132, (void *)(& enhancements), 2); if ((unsigned int )enhancements.response == 0U) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("psb_intel_sdvo_create_enhance_property", "No enhancement is supported\n"); } else { } return (1); } else { } if (((int )psb_intel_sdvo_connector->output_flag & 12) != 0) { tmp___0 = psb_intel_sdvo_create_enhance_property_tv(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply); return (tmp___0); } else if (((int )psb_intel_sdvo_connector->output_flag & 16448) != 0) { tmp___1 = psb_intel_sdvo_create_enhance_property_lvds(psb_intel_sdvo, psb_intel_sdvo_connector, enhancements.reply); return (tmp___1); } else { return (1); } } } static int psb_intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter , struct i2c_msg *msgs , int num ) { struct psb_intel_sdvo *sdvo ; bool tmp ; int tmp___0 ; int tmp___1 ; { sdvo = (struct psb_intel_sdvo *)adapter->algo_data; tmp = psb_intel_sdvo_set_control_bus_switch(sdvo, (int )sdvo->ddc_bus); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (-5); } else { } tmp___1 = (*(((sdvo->i2c)->algo)->master_xfer))(sdvo->i2c, msgs, num); return (tmp___1); } } static u32 psb_intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter ) { struct psb_intel_sdvo *sdvo ; u32 tmp ; { sdvo = (struct psb_intel_sdvo *)adapter->algo_data; tmp = (*(((sdvo->i2c)->algo)->functionality))(sdvo->i2c); return (tmp); } } static struct i2c_algorithm const psb_intel_sdvo_ddc_proxy = {& psb_intel_sdvo_ddc_proxy_xfer, 0, & psb_intel_sdvo_ddc_proxy_func, 0, 0}; static bool psb_intel_sdvo_init_ddc_proxy(struct psb_intel_sdvo *sdvo , struct drm_device *dev ) { int tmp ; { sdvo->ddc.owner = & __this_module; sdvo->ddc.class = 8U; snprintf((char *)(& sdvo->ddc.name), 20UL, "SDVO DDC proxy"); sdvo->ddc.dev.parent = & (dev->pdev)->dev; sdvo->ddc.algo_data = (void *)sdvo; sdvo->ddc.algo = & psb_intel_sdvo_ddc_proxy; tmp = i2c_add_adapter(& sdvo->ddc); return (tmp == 0); } } bool psb_intel_sdvo_init(struct drm_device *dev , int sdvo_reg ) { struct drm_psb_private *dev_priv ; struct gma_encoder *gma_encoder ; struct psb_intel_sdvo *psb_intel_sdvo ; int i ; void *tmp ; u8 tmp___0 ; bool tmp___1 ; int tmp___2 ; u8 byte ; long tmp___3 ; bool tmp___4 ; int tmp___5 ; bool tmp___6 ; int tmp___7 ; long tmp___8 ; bool tmp___9 ; int tmp___10 ; bool tmp___11 ; int tmp___12 ; bool tmp___13 ; int tmp___14 ; long tmp___15 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = kzalloc(2184UL, 208U); psb_intel_sdvo = (struct psb_intel_sdvo *)tmp; if ((unsigned long )psb_intel_sdvo == (unsigned long )((struct psb_intel_sdvo *)0)) { return (0); } else { } psb_intel_sdvo->sdvo_reg = sdvo_reg; tmp___0 = psb_intel_sdvo_get_slave_addr(dev, sdvo_reg); psb_intel_sdvo->slave_addr = (u8 )((int )tmp___0 >> 1); psb_intel_sdvo_select_i2c_bus(dev_priv, psb_intel_sdvo, (u32 )sdvo_reg); tmp___1 = psb_intel_sdvo_init_ddc_proxy(psb_intel_sdvo, dev); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { kfree((void const *)psb_intel_sdvo); return (0); } else { } gma_encoder = & psb_intel_sdvo->base; gma_encoder->type = 3; drm_encoder_init(dev, & gma_encoder->base, & psb_intel_sdvo_enc_funcs, 0); i = 0; goto ldv_42626; ldv_42625: tmp___4 = psb_intel_sdvo_read_byte(psb_intel_sdvo, (int )((u8 )i), & byte); if (tmp___4) { tmp___5 = 0; } else { tmp___5 = 1; } if (tmp___5) { tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_init", "No SDVO device found on SDVO%c\n", sdvo_reg == 397632 ? 66 : 67); } else { } goto err; } else { } i = i + 1; ldv_42626: ; if (i <= 63) { goto ldv_42625; } else { } if (sdvo_reg == 397632) { dev_priv->hotplug_supported_mask = dev_priv->hotplug_supported_mask | 64U; } else { dev_priv->hotplug_supported_mask = dev_priv->hotplug_supported_mask | 128U; } drm_encoder_helper_add(& gma_encoder->base, & psb_intel_sdvo_helper_funcs); tmp___6 = psb_intel_sdvo_get_capabilities(psb_intel_sdvo, & psb_intel_sdvo->caps); if (tmp___6) { tmp___7 = 0; } else { tmp___7 = 1; } if (tmp___7) { goto err; } else { } tmp___9 = psb_intel_sdvo_output_setup(psb_intel_sdvo, (int )psb_intel_sdvo->caps.output_flags); if (tmp___9) { tmp___10 = 0; } else { tmp___10 = 1; } if (tmp___10) { tmp___8 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___8 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_init", "SDVO output failed to setup on SDVO%c\n", sdvo_reg == 397632 ? 66 : 67); } else { } goto err; } else { } psb_intel_sdvo_select_ddc_bus(dev_priv, psb_intel_sdvo, (u32 )sdvo_reg); tmp___11 = psb_intel_sdvo_set_target_input(psb_intel_sdvo); if (tmp___11) { tmp___12 = 0; } else { tmp___12 = 1; } if (tmp___12) { goto err; } else { } tmp___13 = psb_intel_sdvo_get_input_pixel_clock_range(psb_intel_sdvo, & psb_intel_sdvo->pixel_clock_min, & psb_intel_sdvo->pixel_clock_max); if (tmp___13) { tmp___14 = 0; } else { tmp___14 = 1; } if (tmp___14) { goto err; } else { } tmp___15 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___15 != 0L) { drm_ut_debug_printk("psb_intel_sdvo_init", "%s device VID/DID: %02X:%02X.%02X, clock range %dMHz - %dMHz, input 1: %c, input 2: %c, output 1: %c, output 2: %c\n", psb_intel_sdvo->sdvo_reg == 397632 ? (char *)"SDVOB" : (char *)"SDVOC", (int )psb_intel_sdvo->caps.vendor_id, (int )psb_intel_sdvo->caps.device_id, (int )psb_intel_sdvo->caps.device_rev_id, psb_intel_sdvo->pixel_clock_min / 1000, psb_intel_sdvo->pixel_clock_max / 1000, (int )psb_intel_sdvo->caps.sdvo_inputs_mask & 1 ? 89 : 78, ((int )psb_intel_sdvo->caps.sdvo_inputs_mask & 2) != 0 ? 89 : 78, ((int )psb_intel_sdvo->caps.output_flags & 3) != 0 ? 89 : 78, ((int )psb_intel_sdvo->caps.output_flags & 768) != 0 ? 89 : 78); } else { } return (1); err: drm_encoder_cleanup(& gma_encoder->base); i2c_del_adapter(& psb_intel_sdvo->ddc); kfree((void const *)psb_intel_sdvo); return (0); } } extern int ldv_probe_37(void) ; extern int ldv_probe_39(void) ; void ldv_initialize_i2c_algorithm_36(void) { void *tmp ; { tmp = ldv_init_zalloc(1936UL); psb_intel_sdvo_ddc_proxy_group0 = (struct i2c_adapter *)tmp; return; } } void ldv_initialize_drm_connector_funcs_39(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); psb_intel_sdvo_connector_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_initialize_drm_encoder_helper_funcs_40(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(96UL); psb_intel_sdvo_helper_funcs_group0 = (struct drm_encoder *)tmp; tmp___0 = ldv_init_zalloc(208UL); psb_intel_sdvo_helper_funcs_group1 = (struct drm_display_mode *)tmp___0; return; } } void ldv_initialize_drm_connector_helper_funcs_38(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); psb_intel_sdvo_connector_helper_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_main_exported_38(void) { struct drm_display_mode *ldvarg188 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(208UL); ldvarg188 = (struct drm_display_mode *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_38 == 1) { psb_intel_sdvo_get_modes(psb_intel_sdvo_connector_helper_funcs_group0); ldv_state_variable_38 = 1; } else { } goto ldv_42649; case 1: ; if (ldv_state_variable_38 == 1) { psb_intel_sdvo_mode_valid(psb_intel_sdvo_connector_helper_funcs_group0, ldvarg188); ldv_state_variable_38 = 1; } else { } goto ldv_42649; case 2: ; if (ldv_state_variable_38 == 1) { gma_best_encoder(psb_intel_sdvo_connector_helper_funcs_group0); ldv_state_variable_38 = 1; } else { } goto ldv_42649; default: ldv_stop(); } ldv_42649: ; return; } } void ldv_main_exported_39(void) { uint32_t ldvarg148 ; int ldvarg152 ; uint64_t ldvarg149 ; bool ldvarg151 ; struct drm_property *ldvarg150 ; void *tmp ; uint32_t ldvarg147 ; int tmp___0 ; { tmp = ldv_init_zalloc(104UL); ldvarg150 = (struct drm_property *)tmp; ldv_memset((void *)(& ldvarg148), 0, 4UL); ldv_memset((void *)(& ldvarg152), 0, 4UL); ldv_memset((void *)(& ldvarg149), 0, 8UL); ldv_memset((void *)(& ldvarg151), 0, 1UL); ldv_memset((void *)(& ldvarg147), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_39 == 1) { drm_helper_connector_dpms(psb_intel_sdvo_connector_funcs_group0, ldvarg152); ldv_state_variable_39 = 1; } else { } if (ldv_state_variable_39 == 2) { drm_helper_connector_dpms(psb_intel_sdvo_connector_funcs_group0, ldvarg152); ldv_state_variable_39 = 2; } else { } goto ldv_42663; case 1: ; if (ldv_state_variable_39 == 1) { psb_intel_sdvo_detect(psb_intel_sdvo_connector_funcs_group0, (int )ldvarg151); ldv_state_variable_39 = 1; } else { } if (ldv_state_variable_39 == 2) { psb_intel_sdvo_detect(psb_intel_sdvo_connector_funcs_group0, (int )ldvarg151); ldv_state_variable_39 = 2; } else { } goto ldv_42663; case 2: ; if (ldv_state_variable_39 == 1) { psb_intel_sdvo_set_property(psb_intel_sdvo_connector_funcs_group0, ldvarg150, ldvarg149); ldv_state_variable_39 = 1; } else { } if (ldv_state_variable_39 == 2) { psb_intel_sdvo_set_property(psb_intel_sdvo_connector_funcs_group0, ldvarg150, ldvarg149); ldv_state_variable_39 = 2; } else { } goto ldv_42663; case 3: ; if (ldv_state_variable_39 == 2) { psb_intel_sdvo_destroy(psb_intel_sdvo_connector_funcs_group0); ldv_state_variable_39 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42663; case 4: ; if (ldv_state_variable_39 == 1) { psb_intel_sdvo_save(psb_intel_sdvo_connector_funcs_group0); ldv_state_variable_39 = 1; } else { } if (ldv_state_variable_39 == 2) { psb_intel_sdvo_save(psb_intel_sdvo_connector_funcs_group0); ldv_state_variable_39 = 2; } else { } goto ldv_42663; case 5: ; if (ldv_state_variable_39 == 1) { psb_intel_sdvo_restore(psb_intel_sdvo_connector_funcs_group0); ldv_state_variable_39 = 1; } else { } if (ldv_state_variable_39 == 2) { psb_intel_sdvo_restore(psb_intel_sdvo_connector_funcs_group0); ldv_state_variable_39 = 2; } else { } goto ldv_42663; case 6: ; if (ldv_state_variable_39 == 1) { drm_helper_probe_single_connector_modes(psb_intel_sdvo_connector_funcs_group0, ldvarg148, ldvarg147); ldv_state_variable_39 = 1; } else { } if (ldv_state_variable_39 == 2) { drm_helper_probe_single_connector_modes(psb_intel_sdvo_connector_funcs_group0, ldvarg148, ldvarg147); ldv_state_variable_39 = 2; } else { } goto ldv_42663; case 7: ; if (ldv_state_variable_39 == 1) { ldv_probe_39(); ldv_state_variable_39 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42663; default: ldv_stop(); } ldv_42663: ; return; } } void ldv_main_exported_40(void) { struct drm_display_mode *ldvarg72 ; void *tmp ; int ldvarg74 ; struct drm_display_mode *ldvarg73 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg72 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg73 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg74), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_40 == 1) { psb_intel_sdvo_dpms(psb_intel_sdvo_helper_funcs_group0, ldvarg74); ldv_state_variable_40 = 1; } else { } goto ldv_42679; case 1: ; if (ldv_state_variable_40 == 1) { psb_intel_sdvo_mode_fixup(psb_intel_sdvo_helper_funcs_group0, (struct drm_display_mode const *)ldvarg73, psb_intel_sdvo_helper_funcs_group1); ldv_state_variable_40 = 1; } else { } goto ldv_42679; case 2: ; if (ldv_state_variable_40 == 1) { gma_encoder_commit(psb_intel_sdvo_helper_funcs_group0); ldv_state_variable_40 = 1; } else { } goto ldv_42679; case 3: ; if (ldv_state_variable_40 == 1) { psb_intel_sdvo_mode_set(psb_intel_sdvo_helper_funcs_group0, psb_intel_sdvo_helper_funcs_group1, ldvarg72); ldv_state_variable_40 = 1; } else { } goto ldv_42679; case 4: ; if (ldv_state_variable_40 == 1) { gma_encoder_prepare(psb_intel_sdvo_helper_funcs_group0); ldv_state_variable_40 = 1; } else { } goto ldv_42679; default: ldv_stop(); } ldv_42679: ; return; } } void ldv_main_exported_36(void) { int ldvarg153 ; struct i2c_msg *ldvarg154 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(16UL); ldvarg154 = (struct i2c_msg *)tmp; ldv_memset((void *)(& ldvarg153), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_36 == 1) { psb_intel_sdvo_ddc_proxy_xfer(psb_intel_sdvo_ddc_proxy_group0, ldvarg154, ldvarg153); ldv_state_variable_36 = 1; } else { } goto ldv_42691; case 1: ; if (ldv_state_variable_36 == 1) { psb_intel_sdvo_ddc_proxy_func(psb_intel_sdvo_ddc_proxy_group0); ldv_state_variable_36 = 1; } else { } goto ldv_42691; default: ldv_stop(); } ldv_42691: ; return; } } void ldv_main_exported_37(void) { struct drm_encoder *ldvarg211 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(96UL); ldvarg211 = (struct drm_encoder *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_37 == 2) { psb_intel_sdvo_enc_destroy(ldvarg211); ldv_state_variable_37 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42699; case 1: ; if (ldv_state_variable_37 == 1) { ldv_probe_37(); ldv_state_variable_37 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42699; default: ldv_stop(); } ldv_42699: ; return; } } bool ldv_queue_work_on_243(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_244(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_245(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_246(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_247(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static int timer_pending(struct timer_list const *timer ) { { return ((unsigned long )timer->entry.pprev != (unsigned long )((struct hlist_node **/* const */)0)); } } extern void add_timer(struct timer_list * ) ; extern int del_timer_sync(struct timer_list * ) ; int ldv_del_timer_sync_262(struct timer_list *ldv_func_arg1 ) ; bool ldv_queue_work_on_257(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_259(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_258(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_261(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_260(struct workqueue_struct *ldv_func_arg1 ) ; __inline static unsigned int readl(void const volatile *addr ) { unsigned int ret ; { __asm__ volatile ("movl %1,%0": "=r" (ret): "m" (*((unsigned int volatile *)addr)): "memory"); return (ret); } } void activate_pending_timer_4(struct timer_list *timer , unsigned long data , int pending_flag ) ; void choose_timer_4(struct timer_list *timer ) ; void disable_suitable_timer_4(struct timer_list *timer ) ; int reg_timer_4(struct timer_list *timer ) ; void psb_lid_timer_init(struct drm_psb_private *dev_priv ) ; void psb_lid_timer_takedown(struct drm_psb_private *dev_priv ) ; static void psb_lid_timer_func(unsigned long data ) { struct drm_psb_private *dev_priv ; struct drm_device *dev ; struct timer_list *lid_timer ; unsigned long irq_flags ; u32 *lid_state ; u32 pp_status ; unsigned int tmp ; uint32_t tmp___0 ; long tmp___1 ; uint32_t tmp___2 ; uint32_t tmp___3 ; unsigned int tmp___4 ; raw_spinlock_t *tmp___5 ; int tmp___6 ; { dev_priv = (struct drm_psb_private *)data; dev = dev_priv->dev; lid_timer = & dev_priv->lid_timer; lid_state = dev_priv->opregion.lid_state; tmp = readl((void const volatile *)lid_state); if (tmp == dev_priv->lid_last_state) { goto lid_timer_schedule; } else { } tmp___4 = readl((void const volatile *)lid_state); if ((int )tmp___4 & 1) { tmp___0 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___0 | 1U); ldv_41558: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status >= 0 && (pp_status & 805306368U) != 0U) { goto ldv_41558; } else { } tmp___2 = REGISTER_READ(dev, 397824U); if ((int )tmp___2 < 0) { psb_intel_lvds_set_brightness(dev, 100); } else { tmp___1 = ldv__builtin_expect((long )((int )drm_debug) & 1L, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("psb_lid_timer_func", "LVDS panel never powered up"); } else { } return; } } else { psb_intel_lvds_set_brightness(dev, 0); tmp___3 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___3 & 4294967294U); ldv_41561: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status >= 0) { goto ldv_41561; } else { } } dev_priv->lid_last_state = readl((void const volatile *)lid_state); lid_timer_schedule: tmp___5 = spinlock_check(& dev_priv->lid_lock); irq_flags = _raw_spin_lock_irqsave(tmp___5); tmp___6 = timer_pending((struct timer_list const *)lid_timer); if (tmp___6 == 0) { lid_timer->expires = (unsigned long )jiffies + 25UL; add_timer(lid_timer); } else { } spin_unlock_irqrestore(& dev_priv->lid_lock, irq_flags); return; } } void psb_lid_timer_init(struct drm_psb_private *dev_priv ) { struct timer_list *lid_timer ; unsigned long irq_flags ; struct lock_class_key __key ; raw_spinlock_t *tmp ; { lid_timer = & dev_priv->lid_timer; spinlock_check(& dev_priv->lid_lock); __raw_spin_lock_init(& dev_priv->lid_lock.__annonCompField18.rlock, "&(&dev_priv->lid_lock)->rlock", & __key); tmp = spinlock_check(& dev_priv->lid_lock); irq_flags = _raw_spin_lock_irqsave(tmp); reg_timer_4(lid_timer); lid_timer->data = (unsigned long )dev_priv; lid_timer->function = & psb_lid_timer_func; lid_timer->expires = (unsigned long )jiffies + 25UL; add_timer(lid_timer); spin_unlock_irqrestore(& dev_priv->lid_lock, irq_flags); return; } } void psb_lid_timer_takedown(struct drm_psb_private *dev_priv ) { { ldv_del_timer_sync_262(& dev_priv->lid_timer); return; } } void activate_pending_timer_4(struct timer_list *timer , unsigned long data , int pending_flag ) { { if ((unsigned long )ldv_timer_list_4 == (unsigned long )timer) { if (ldv_timer_state_4 == 2 || pending_flag != 0) { ldv_timer_list_4 = timer; ldv_timer_list_4->data = data; ldv_timer_state_4 = 1; } else { } return; } else { } reg_timer_4(timer); ldv_timer_list_4->data = data; return; } } void choose_timer_4(struct timer_list *timer ) { { LDV_IN_INTERRUPT = 2; (*(timer->function))(timer->data); LDV_IN_INTERRUPT = 1; ldv_timer_state_4 = 2; return; } } void disable_suitable_timer_4(struct timer_list *timer ) { { if ((unsigned long )timer == (unsigned long )ldv_timer_list_4) { ldv_timer_state_4 = 0; return; } else { } return; } } int reg_timer_4(struct timer_list *timer ) { { ldv_timer_list_4 = timer; ldv_timer_state_4 = 1; return (0); } } bool ldv_queue_work_on_257(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_258(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_259(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_260(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_261(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } int ldv_del_timer_sync_262(struct timer_list *ldv_func_arg1 ) { ldv_func_ret_type___3 ldv_func_res ; int tmp ; { tmp = del_timer_sync(ldv_func_arg1); ldv_func_res = tmp; disable_suitable_timer_4(ldv_func_arg1); return (ldv_func_res); } } bool ldv_queue_work_on_273(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_275(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_274(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_277(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_276(struct workqueue_struct *ldv_func_arg1 ) ; extern bool drm_handle_vblank(struct drm_device * , int ) ; void psb_intel_opregion_asle_intr(struct drm_device *dev ) ; int psb_irq_enable_dpst(struct drm_device *dev ) ; int psb_irq_disable_dpst(struct drm_device *dev ) ; void psb_irq_turn_on_dpst(struct drm_device *dev ) ; void psb_irq_turn_off_dpst(struct drm_device *dev ) ; void psb_enable_pipestat(struct drm_psb_private *dev_priv , int pipe , u32 mask ) ; void psb_disable_pipestat(struct drm_psb_private *dev_priv , int pipe , u32 mask ) ; int mdfld_enable_te(struct drm_device *dev , int pipe ) ; void mdfld_disable_te(struct drm_device *dev , int pipe ) ; __inline static u32 psb_pipestat(int pipe ) { { if (pipe == 0) { return (458788U); } else { } if (pipe == 1) { return (462884U); } else { } if (pipe == 2) { return (466980U); } else { } __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_irq.c"), "i" (46), "i" (12UL)); ldv_41627: ; goto ldv_41627; } } __inline static u32 mid_pipe_event(int pipe ) { { if (pipe == 0) { return (64U); } else { } if (pipe == 1) { return (16U); } else { } if (pipe == 2) { return (4U); } else { } __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_irq.c"), "i" (58), "i" (12UL)); ldv_41631: ; goto ldv_41631; } } __inline static u32 mid_pipeconf(int pipe ) { { if (pipe == 0) { return (458760U); } else { } if (pipe == 1) { return (462856U); } else { } if (pipe == 2) { return (466952U); } else { } __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/psb_irq.c"), "i" (82), "i" (12UL)); ldv_41639: ; goto ldv_41639; } } void psb_enable_pipestat(struct drm_psb_private *dev_priv , int pipe , u32 mask ) { u32 reg ; u32 tmp ; u32 writeVal ; unsigned int tmp___0 ; bool tmp___1 ; { if ((dev_priv->pipestat[pipe] & mask) != mask) { tmp = psb_pipestat(pipe); reg = tmp; dev_priv->pipestat[pipe] = dev_priv->pipestat[pipe] | mask; tmp___1 = gma_power_begin(dev_priv->dev, 0); if ((int )tmp___1) { tmp___0 = ioread32((void *)dev_priv->vdc_reg + (unsigned long )reg); writeVal = tmp___0; writeVal = ((mask >> 16) | mask) | writeVal; iowrite32(writeVal, (void *)dev_priv->vdc_reg + (unsigned long )reg); ioread32((void *)dev_priv->vdc_reg + (unsigned long )reg); gma_power_end(dev_priv->dev); } else { } } else { } return; } } void psb_disable_pipestat(struct drm_psb_private *dev_priv , int pipe , u32 mask ) { u32 reg ; u32 tmp ; u32 writeVal ; unsigned int tmp___0 ; bool tmp___1 ; { if ((dev_priv->pipestat[pipe] & mask) != 0U) { tmp = psb_pipestat(pipe); reg = tmp; dev_priv->pipestat[pipe] = dev_priv->pipestat[pipe] & ~ mask; tmp___1 = gma_power_begin(dev_priv->dev, 0); if ((int )tmp___1) { tmp___0 = ioread32((void *)dev_priv->vdc_reg + (unsigned long )reg); writeVal = tmp___0; writeVal = ~ mask & writeVal; iowrite32(writeVal, (void *)dev_priv->vdc_reg + (unsigned long )reg); ioread32((void *)dev_priv->vdc_reg + (unsigned long )reg); gma_power_end(dev_priv->dev); } else { } } else { } return; } } static void mid_enable_pipe_event(struct drm_psb_private *dev_priv , int pipe ) { u32 pipe_event ; u32 tmp ; bool tmp___0 ; { tmp___0 = gma_power_begin(dev_priv->dev, 0); if ((int )tmp___0) { tmp = mid_pipe_event(pipe); pipe_event = tmp; dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask | pipe_event; iowrite32(~ dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8360U); iowrite32(dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8352U); gma_power_end(dev_priv->dev); } else { } return; } } static void mid_disable_pipe_event(struct drm_psb_private *dev_priv , int pipe ) { u32 pipe_event ; u32 tmp ; bool tmp___0 ; { if (dev_priv->pipestat[pipe] == 0U) { tmp___0 = gma_power_begin(dev_priv->dev, 0); if ((int )tmp___0) { tmp = mid_pipe_event(pipe); pipe_event = tmp; dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask & ~ pipe_event; iowrite32(~ dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8360U); iowrite32(dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8352U); gma_power_end(dev_priv->dev); } else { } } else { } return; } } static void mid_pipe_event_handler(struct drm_device *dev , int pipe ) { struct drm_psb_private *dev_priv ; uint32_t pipe_stat_val ; uint32_t pipe_stat_reg ; u32 tmp ; uint32_t pipe_enable ; uint32_t pipe_status ; uint32_t pipe_clear ; uint32_t i ; unsigned int tmp___0 ; unsigned int tmp___1 ; unsigned int tmp___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; pipe_stat_val = 0U; tmp = psb_pipestat(pipe); pipe_stat_reg = tmp; pipe_enable = dev_priv->pipestat[pipe]; pipe_status = dev_priv->pipestat[pipe] >> 16; i = 0U; spin_lock(& dev_priv->irqmask_lock); pipe_stat_val = ioread32((void *)dev_priv->vdc_reg + (unsigned long )pipe_stat_reg); pipe_stat_val = (pipe_enable | pipe_status) & pipe_stat_val; pipe_stat_val = (pipe_stat_val >> 16) & pipe_stat_val; spin_unlock(& dev_priv->irqmask_lock); i = 0U; goto ldv_41677; ldv_41676: tmp___0 = ioread32((void *)dev_priv->vdc_reg + (unsigned long )pipe_stat_reg); iowrite32(tmp___0, (void *)dev_priv->vdc_reg + (unsigned long )pipe_stat_reg); tmp___1 = ioread32((void *)dev_priv->vdc_reg + (unsigned long )pipe_stat_reg); pipe_clear = tmp___1 & pipe_status; if (pipe_clear == 0U) { goto ldv_41675; } else { } i = i + 1U; ldv_41677: ; if (i <= 65534U) { goto ldv_41676; } else { } ldv_41675: ; if (pipe_clear != 0U) { tmp___2 = ioread32((void *)dev_priv->vdc_reg + (unsigned long )pipe_stat_reg); dev_err((struct device const *)dev->dev, "%s, can\'t clear status bits for pipe %d, its value = 0x%x.\n", "mid_pipe_event_handler", pipe, tmp___2); } else { } if ((pipe_stat_val & 2U) != 0U) { drm_handle_vblank(dev, pipe); } else { } if (((unsigned long )pipe_stat_val & 64UL) != 0UL) { drm_handle_vblank(dev, pipe); } else { } return; } } static void psb_vdc_interrupt(struct drm_device *dev , uint32_t vdc_stat ) { { if ((int )vdc_stat & 1) { psb_intel_opregion_asle_intr(dev); } else { } if ((vdc_stat & 128U) != 0U) { mid_pipe_event_handler(dev, 0); } else { } if ((vdc_stat & 32U) != 0U) { mid_pipe_event_handler(dev, 1); } else { } return; } } static void psb_sgx_interrupt(struct drm_device *dev , u32 stat_1 , u32 stat_2 ) { struct drm_psb_private *dev_priv ; u32 val ; u32 addr ; int error ; { dev_priv = (struct drm_psb_private *)dev->dev_private; error = 0; if ((stat_1 & 134217728U) != 0U) { val = ioread32((void *)dev_priv->sgx_reg + 3588U); } else { } if ((stat_2 & 16U) != 0U) { val = ioread32((void *)dev_priv->sgx_reg + 3076U); addr = ioread32((void *)dev_priv->sgx_reg + 3080U); if (val != 0U) { if ((val & 16384U) != 0U) { drm_err("SGX MMU page fault:"); } else { drm_err("SGX MMU read / write protection fault:"); } if ((val & 2U) != 0U) { drm_err("\tCache requestor"); } else { } if ((val & 4U) != 0U) { drm_err("\tTA requestor"); } else { } if ((val & 8U) != 0U) { drm_err("\tVDM requestor"); } else { } if ((val & 16U) != 0U) { drm_err("\t2D requestor"); } else { } if ((val & 32U) != 0U) { drm_err("\tPBE requestor"); } else { } if ((val & 64U) != 0U) { drm_err("\tTSP requestor"); } else { } if ((val & 128U) != 0U) { drm_err("\tISP requestor"); } else { } if ((val & 256U) != 0U) { drm_err("\tUSSEPDS requestor"); } else { } if ((val & 512U) != 0U) { drm_err("\tHost requestor"); } else { } drm_err("\tMMU failing address is 0x%08x.\n", addr); error = 1; } else { } } else { } iowrite32(stat_1, (void *)dev_priv->sgx_reg + 308U); iowrite32(stat_2, (void *)dev_priv->sgx_reg + 276U); ioread32((void *)dev_priv->sgx_reg + 276U); return; } } irqreturn_t psb_irq_handler(int irq , void *arg ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; uint32_t vdc_stat ; uint32_t dsp_int ; uint32_t sgx_int ; uint32_t hotplug_int ; u32 sgx_stat_1 ; u32 sgx_stat_2 ; int handled ; bool tmp ; uint32_t tmp___0 ; { dev = (struct drm_device *)arg; dev_priv = (struct drm_psb_private *)dev->dev_private; dsp_int = 0U; sgx_int = 0U; hotplug_int = 0U; handled = 0; spin_lock(& dev_priv->irqmask_lock); vdc_stat = ioread32((void *)dev_priv->vdc_reg + 8356U); if ((vdc_stat & 161U) != 0U) { dsp_int = 1U; } else { } if ((vdc_stat & 262144U) != 0U) { sgx_int = 1U; } else { } if ((vdc_stat & 131072U) != 0U) { hotplug_int = 1U; } else { } vdc_stat = dev_priv->vdc_irq_mask & vdc_stat; spin_unlock(& dev_priv->irqmask_lock); if (dsp_int != 0U) { tmp = gma_power_is_on(dev); if ((int )tmp) { psb_vdc_interrupt(dev, vdc_stat); handled = 1; } else { } } else { } if (sgx_int != 0U) { sgx_stat_1 = ioread32((void *)dev_priv->sgx_reg + 300U); sgx_stat_2 = ioread32((void *)dev_priv->sgx_reg + 280U); psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2); handled = 1; } else { } if (hotplug_int != 0U && (unsigned long )(dev_priv->ops)->hotplug != (unsigned long )((int (*/* const */)(struct drm_device * ))0)) { handled = (*((dev_priv->ops)->hotplug))(dev); tmp___0 = REGISTER_READ(dev, 397588U); REGISTER_WRITE(dev, 397588U, tmp___0); } else { } iowrite32(vdc_stat, (void *)dev_priv->vdc_reg + 8356U); ioread32((void *)dev_priv->vdc_reg + 8356U); __asm__ volatile ("lfence": : : "memory"); if (handled == 0) { return (0); } else { } return (1); } } void psb_irq_preinstall(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; raw_spinlock_t *tmp ; bool tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp); tmp___0 = gma_power_is_on(dev); if ((int )tmp___0) { iowrite32(4294967295U, (void *)dev_priv->vdc_reg + 8344U); iowrite32(0U, (void *)dev_priv->vdc_reg + 8360U); iowrite32(0U, (void *)dev_priv->vdc_reg + 8352U); iowrite32(0U, (void *)dev_priv->sgx_reg + 304U); ioread32((void *)dev_priv->sgx_reg + 304U); } else { } if ((int )(dev->vblank)->enabled) { dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask | 128U; } else { } if ((int )(dev->vblank + 1UL)->enabled) { dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask | 32U; } else { } if ((unsigned long )(dev_priv->ops)->hotplug != (unsigned long )((int (*/* const */)(struct drm_device * ))0)) { dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask | 131072U; } else { } dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask | 262145U; iowrite32(~ dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8360U); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return; } } int psb_irq_postinstall(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; raw_spinlock_t *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp); iowrite32(16U, (void *)dev_priv->sgx_reg + 272U); iowrite32(134217728U, (void *)dev_priv->sgx_reg + 304U); ioread32((void *)dev_priv->sgx_reg + 304U); iowrite32(dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8352U); iowrite32(4294967295U, (void *)dev_priv->vdc_reg + 8344U); if ((int )(dev->vblank)->enabled) { psb_enable_pipestat(dev_priv, 0, 131072U); } else { psb_disable_pipestat(dev_priv, 0, 131072U); } if ((int )(dev->vblank + 1UL)->enabled) { psb_enable_pipestat(dev_priv, 1, 131072U); } else { psb_disable_pipestat(dev_priv, 1, 131072U); } if ((int )(dev->vblank + 2UL)->enabled) { psb_enable_pipestat(dev_priv, 2, 131072U); } else { psb_disable_pipestat(dev_priv, 2, 131072U); } if ((unsigned long )(dev_priv->ops)->hotplug_enable != (unsigned long )((void (*/* const */)(struct drm_device * , bool ))0)) { (*((dev_priv->ops)->hotplug_enable))(dev, 1); } else { } spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return (0); } } void psb_irq_uninstall(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; raw_spinlock_t *tmp ; unsigned int tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp); if ((unsigned long )(dev_priv->ops)->hotplug_enable != (unsigned long )((void (*/* const */)(struct drm_device * , bool ))0)) { (*((dev_priv->ops)->hotplug_enable))(dev, 0); } else { } iowrite32(4294967295U, (void *)dev_priv->vdc_reg + 8344U); if ((int )(dev->vblank)->enabled) { psb_disable_pipestat(dev_priv, 0, 131072U); } else { } if ((int )(dev->vblank + 1UL)->enabled) { psb_disable_pipestat(dev_priv, 1, 131072U); } else { } if ((int )(dev->vblank + 2UL)->enabled) { psb_disable_pipestat(dev_priv, 2, 131072U); } else { } dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask & 1835008U; iowrite32(~ dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8360U); iowrite32(dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8352U); __asm__ volatile ("sfence": : : "memory"); tmp___0 = ioread32((void *)dev_priv->vdc_reg + 8356U); iowrite32(tmp___0, (void *)dev_priv->vdc_reg + 8356U); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return; } } void psb_irq_turn_on_dpst(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 hist_reg ; u32 pwm_reg ; bool tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = gma_power_begin(dev, 0); if ((int )tmp) { iowrite32(2147483648U, (void *)dev_priv->vdc_reg + 397920U); hist_reg = ioread32((void *)dev_priv->vdc_reg + 397920U); iowrite32(2147483648U, (void *)dev_priv->vdc_reg + 397928U); hist_reg = ioread32((void *)dev_priv->vdc_reg + 397928U); iowrite32(2147549440U, (void *)dev_priv->vdc_reg + 397904U); pwm_reg = ioread32((void *)dev_priv->vdc_reg + 397904U); iowrite32(pwm_reg | 50331648U, (void *)dev_priv->vdc_reg + 397904U); pwm_reg = ioread32((void *)dev_priv->vdc_reg + 397904U); psb_enable_pipestat(dev_priv, 0, 8388608U); hist_reg = ioread32((void *)dev_priv->vdc_reg + 397928U); iowrite32(hist_reg | 1073741824U, (void *)dev_priv->vdc_reg + 397928U); pwm_reg = ioread32((void *)dev_priv->vdc_reg + 397904U); iowrite32(pwm_reg | 2181103872U, (void *)dev_priv->vdc_reg + 397904U); gma_power_end(dev); } else { } return; } } int psb_irq_enable_dpst(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; raw_spinlock_t *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp); mid_enable_pipe_event(dev_priv, 0); psb_irq_turn_on_dpst(dev); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return (0); } } void psb_irq_turn_off_dpst(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 hist_reg ; u32 pwm_reg ; bool tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = gma_power_begin(dev, 0); if ((int )tmp) { iowrite32(0U, (void *)dev_priv->vdc_reg + 397928U); hist_reg = ioread32((void *)dev_priv->vdc_reg + 397928U); psb_disable_pipestat(dev_priv, 0, 8388608U); pwm_reg = ioread32((void *)dev_priv->vdc_reg + 397904U); iowrite32(pwm_reg & 4278190079U, (void *)dev_priv->vdc_reg + 397904U); pwm_reg = ioread32((void *)dev_priv->vdc_reg + 397904U); gma_power_end(dev); } else { } return; } } int psb_irq_disable_dpst(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; raw_spinlock_t *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp); mid_disable_pipe_event(dev_priv, 0); psb_irq_turn_off_dpst(dev); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return (0); } } int psb_enable_vblank(struct drm_device *dev , int pipe ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; uint32_t reg_val ; uint32_t pipeconf_reg ; u32 tmp ; int tmp___0 ; bool tmp___1 ; raw_spinlock_t *tmp___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; reg_val = 0U; tmp = mid_pipeconf(pipe); pipeconf_reg = tmp; if (((int )(dev->pdev)->device & 65528) == 304) { tmp___0 = mdfld_enable_te(dev, pipe); return (tmp___0); } else { } tmp___1 = gma_power_begin(dev, 0); if ((int )tmp___1) { reg_val = REGISTER_READ(dev, pipeconf_reg); gma_power_end(dev); } else { } if ((int )reg_val >= 0) { return (-22); } else { } tmp___2 = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp___2); if (pipe == 0) { dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask | 128U; } else if (pipe == 1) { dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask | 32U; } else { } iowrite32(~ dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8360U); iowrite32(dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8352U); psb_enable_pipestat(dev_priv, pipe, 131072U); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return (0); } } void psb_disable_vblank(struct drm_device *dev , int pipe ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; raw_spinlock_t *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if (((int )(dev->pdev)->device & 65528) == 304) { mdfld_disable_te(dev, pipe); } else { } tmp = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp); if (pipe == 0) { dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask & 4294967167U; } else if (pipe == 1) { dev_priv->vdc_irq_mask = dev_priv->vdc_irq_mask & 4294967263U; } else { } iowrite32(~ dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8360U); iowrite32(dev_priv->vdc_irq_mask, (void *)dev_priv->vdc_reg + 8352U); psb_disable_pipestat(dev_priv, pipe, 131072U); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return; } } int mdfld_enable_te(struct drm_device *dev , int pipe ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; uint32_t reg_val ; uint32_t pipeconf_reg ; u32 tmp ; bool tmp___0 ; raw_spinlock_t *tmp___1 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; reg_val = 0U; tmp = mid_pipeconf(pipe); pipeconf_reg = tmp; tmp___0 = gma_power_begin(dev, 0); if ((int )tmp___0) { reg_val = REGISTER_READ(dev, pipeconf_reg); gma_power_end(dev); } else { } if ((int )reg_val >= 0) { return (-22); } else { } tmp___1 = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp___1); mid_enable_pipe_event(dev_priv, pipe); psb_enable_pipestat(dev_priv, pipe, 4194304U); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return (0); } } void mdfld_disable_te(struct drm_device *dev , int pipe ) { struct drm_psb_private *dev_priv ; unsigned long irqflags ; raw_spinlock_t *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if (! dev_priv->dsr_enable) { return; } else { } tmp = spinlock_check(& dev_priv->irqmask_lock); irqflags = _raw_spin_lock_irqsave(tmp); mid_disable_pipe_event(dev_priv, pipe); psb_disable_pipestat(dev_priv, pipe, 4194304U); spin_unlock_irqrestore(& dev_priv->irqmask_lock, irqflags); return; } } u32 psb_get_vblank_counter(struct drm_device *dev , int pipe ) { uint32_t high_frame ; uint32_t low_frame ; uint32_t pipeconf_reg ; uint32_t reg_val ; uint32_t high1 ; uint32_t high2 ; uint32_t low ; uint32_t count ; bool tmp ; int tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; uint32_t tmp___3 ; { high_frame = 458816U; low_frame = 458820U; pipeconf_reg = 458760U; reg_val = 0U; high1 = 0U; high2 = 0U; low = 0U; count = 0U; switch (pipe) { case 0: ; goto ldv_41810; case 1: high_frame = 462912U; low_frame = 462916U; pipeconf_reg = 462856U; goto ldv_41810; case 2: high_frame = 467008U; low_frame = 467012U; pipeconf_reg = 466952U; goto ldv_41810; default: dev_err((struct device const *)dev->dev, "%s, invalid pipe.\n", "psb_get_vblank_counter"); return (0U); } ldv_41810: tmp = gma_power_begin(dev, 0); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0U); } else { } reg_val = REGISTER_READ(dev, pipeconf_reg); if ((int )reg_val >= 0) { dev_err((struct device const *)dev->dev, "trying to get vblank count for disabled pipe %d\n", pipe); goto psb_get_vblank_counter_exit; } else { } ldv_41816: tmp___1 = REGISTER_READ(dev, high_frame); high1 = tmp___1 & 65535U; tmp___2 = REGISTER_READ(dev, low_frame); low = tmp___2 >> 24; tmp___3 = REGISTER_READ(dev, high_frame); high2 = tmp___3 & 65535U; if (high1 != high2) { goto ldv_41816; } else { } count = (high1 << 8) | low; psb_get_vblank_counter_exit: gma_power_end(dev); return (count); } } bool ldv_queue_work_on_273(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_274(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_275(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_276(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_277(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_287(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_289(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_288(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_291(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_290(struct workqueue_struct *ldv_func_arg1 ) ; extern void drm_modeset_lock_all(struct drm_device * ) ; extern void drm_modeset_unlock_all(struct drm_device * ) ; extern bool drm_helper_crtc_in_use(struct drm_crtc * ) ; void psb_intel_opregion_init(struct drm_device *dev ) ; static int psb_output_init(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; psb_intel_lvds_init(dev, & dev_priv->mode_dev); psb_intel_sdvo_init(dev, 397632); return (0); } } static void psb_init_pm(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 gating ; unsigned int tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = ioread32((void *)dev_priv->sgx_reg); gating = tmp; gating = gating & 4294967292U; gating = gating | 1U; iowrite32(gating, (void *)dev_priv->sgx_reg); ioread32((void *)dev_priv->sgx_reg); return; } } static int psb_save_display_registers(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct drm_crtc *crtc ; struct drm_connector *connector ; struct psb_state *regs ; struct list_head const *__mptr ; bool tmp ; struct list_head const *__mptr___0 ; struct list_head const *__mptr___1 ; struct list_head const *__mptr___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; regs = & dev_priv->regs.__annonCompField80.psb; regs->saveDSPARB = ioread32((void *)dev_priv->vdc_reg + 458800U); regs->saveDSPFW1 = ioread32((void *)dev_priv->vdc_reg + 458804U); regs->saveDSPFW2 = ioread32((void *)dev_priv->vdc_reg + 458808U); regs->saveDSPFW3 = ioread32((void *)dev_priv->vdc_reg + 458812U); regs->saveDSPFW4 = ioread32((void *)dev_priv->vdc_reg + 458832U); regs->saveDSPFW5 = ioread32((void *)dev_priv->vdc_reg + 458836U); regs->saveDSPFW6 = ioread32((void *)dev_priv->vdc_reg + 458840U); regs->saveCHICKENBIT = ioread32((void *)dev_priv->vdc_reg + 459776U); drm_modeset_lock_all(dev); __mptr = (struct list_head const *)dev->mode_config.crtc_list.next; crtc = (struct drm_crtc *)__mptr + 0xfffffffffffffff0UL; goto ldv_41568; ldv_41567: tmp = drm_helper_crtc_in_use(crtc); if ((int )tmp) { (*((crtc->funcs)->save))(crtc); } else { } __mptr___0 = (struct list_head const *)crtc->head.next; crtc = (struct drm_crtc *)__mptr___0 + 0xfffffffffffffff0UL; ldv_41568: ; if ((unsigned long )(& crtc->head) != (unsigned long )(& dev->mode_config.crtc_list)) { goto ldv_41567; } else { } __mptr___1 = (struct list_head const *)dev->mode_config.connector_list.next; connector = (struct drm_connector *)__mptr___1 + 0xffffffffffffffe8UL; goto ldv_41575; ldv_41574: ; if ((unsigned long )(connector->funcs)->save != (unsigned long )((void (*/* const */)(struct drm_connector * ))0)) { (*((connector->funcs)->save))(connector); } else { } __mptr___2 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___2 + 0xffffffffffffffe8UL; ldv_41575: ; if ((unsigned long )(& connector->head) != (unsigned long )(& dev->mode_config.connector_list)) { goto ldv_41574; } else { } drm_modeset_unlock_all(dev); return (0); } } static int psb_restore_display_registers(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct drm_crtc *crtc ; struct drm_connector *connector ; struct psb_state *regs ; struct list_head const *__mptr ; bool tmp ; struct list_head const *__mptr___0 ; struct list_head const *__mptr___1 ; struct list_head const *__mptr___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; regs = & dev_priv->regs.__annonCompField80.psb; iowrite32(regs->saveDSPARB, (void *)dev_priv->vdc_reg + 458800U); iowrite32(regs->saveDSPFW1, (void *)dev_priv->vdc_reg + 458804U); iowrite32(regs->saveDSPFW2, (void *)dev_priv->vdc_reg + 458808U); iowrite32(regs->saveDSPFW3, (void *)dev_priv->vdc_reg + 458812U); iowrite32(regs->saveDSPFW4, (void *)dev_priv->vdc_reg + 458832U); iowrite32(regs->saveDSPFW5, (void *)dev_priv->vdc_reg + 458836U); iowrite32(regs->saveDSPFW6, (void *)dev_priv->vdc_reg + 458840U); iowrite32(regs->saveCHICKENBIT, (void *)dev_priv->vdc_reg + 459776U); iowrite32(2147483648U, (void *)dev_priv->vdc_reg + 463872U); drm_modeset_lock_all(dev); __mptr = (struct list_head const *)dev->mode_config.crtc_list.next; crtc = (struct drm_crtc *)__mptr + 0xfffffffffffffff0UL; goto ldv_41589; ldv_41588: tmp = drm_helper_crtc_in_use(crtc); if ((int )tmp) { (*((crtc->funcs)->restore))(crtc); } else { } __mptr___0 = (struct list_head const *)crtc->head.next; crtc = (struct drm_crtc *)__mptr___0 + 0xfffffffffffffff0UL; ldv_41589: ; if ((unsigned long )(& crtc->head) != (unsigned long )(& dev->mode_config.crtc_list)) { goto ldv_41588; } else { } __mptr___1 = (struct list_head const *)dev->mode_config.connector_list.next; connector = (struct drm_connector *)__mptr___1 + 0xffffffffffffffe8UL; goto ldv_41596; ldv_41595: ; if ((unsigned long )(connector->funcs)->restore != (unsigned long )((void (*/* const */)(struct drm_connector * ))0)) { (*((connector->funcs)->restore))(connector); } else { } __mptr___2 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___2 + 0xffffffffffffffe8UL; ldv_41596: ; if ((unsigned long )(& connector->head) != (unsigned long )(& dev->mode_config.connector_list)) { goto ldv_41595; } else { } drm_modeset_unlock_all(dev); return (0); } } static int psb_power_down(struct drm_device *dev ) { { return (0); } } static int psb_power_up(struct drm_device *dev ) { { return (0); } } static struct psb_offset const psb_regmap[2U] = { {24640U, 24644U, 459136U, 458760U, 393244U, 24596U, 0U, 393216U, 393220U, 393224U, 393228U, 393232U, 393236U, 459144U, 459152U, 459148U, 459164U, 459140U, 459140U, 458788U, 459140U, 459172U, 40960U}, {24648U, 24652U, 463232U, 462856U, 397340U, 24600U, 0U, 397312U, 397316U, 397320U, 397324U, 397328U, 397332U, 463240U, 463248U, 463244U, 463260U, 463236U, 463236U, 462884U, 463236U, 463268U, 43008U}}; static int psb_chip_setup(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; dev_priv->regmap = (struct psb_offset const *)(& psb_regmap); gma_get_core_freq(dev); gma_intel_setup_gmbus(dev); psb_intel_opregion_init(dev); psb_intel_init_bios(dev); return (0); } } static void psb_chip_teardown(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; psb_lid_timer_takedown(dev_priv); gma_intel_teardown_gmbus(dev); return; } } struct psb_ops const psb_chip_ops = {"Poulsbo", 1U, 2, 2, 262144, 1, 2, 1, 1, & psb_intel_helper_funcs, & psb_intel_crtc_funcs, & psb_clock_funcs, & psb_chip_setup, & psb_chip_teardown, 0, & psb_output_init, 0, 0, & psb_init_pm, & psb_save_display_registers, & psb_restore_display_registers, & psb_power_up, & psb_power_down, 0, 0, 0, 0}; void ldv_initialize_psb_ops_35(void) { void *tmp ; { tmp = ldv_init_zalloc(3320UL); psb_chip_ops_group0 = (struct drm_device *)tmp; return; } } void ldv_main_exported_35(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ; if (ldv_state_variable_35 == 1) { psb_chip_teardown(psb_chip_ops_group0); ldv_state_variable_35 = 1; } else { } goto ldv_41621; case 1: ; if (ldv_state_variable_35 == 1) { psb_chip_setup(psb_chip_ops_group0); ldv_state_variable_35 = 1; } else { } goto ldv_41621; case 2: ; if (ldv_state_variable_35 == 1) { psb_init_pm(psb_chip_ops_group0); ldv_state_variable_35 = 1; } else { } goto ldv_41621; case 3: ; if (ldv_state_variable_35 == 1) { psb_save_display_registers(psb_chip_ops_group0); ldv_state_variable_35 = 1; } else { } goto ldv_41621; case 4: ; if (ldv_state_variable_35 == 1) { psb_restore_display_registers(psb_chip_ops_group0); ldv_state_variable_35 = 1; } else { } goto ldv_41621; case 5: ; if (ldv_state_variable_35 == 1) { psb_power_down(psb_chip_ops_group0); ldv_state_variable_35 = 1; } else { } goto ldv_41621; case 6: ; if (ldv_state_variable_35 == 1) { psb_output_init(psb_chip_ops_group0); ldv_state_variable_35 = 1; } else { } goto ldv_41621; case 7: ; if (ldv_state_variable_35 == 1) { psb_power_up(psb_chip_ops_group0); ldv_state_variable_35 = 1; } else { } goto ldv_41621; default: ldv_stop(); } ldv_41621: ; return; } } bool ldv_queue_work_on_287(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_288(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_289(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_290(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_291(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_301(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_303(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_302(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_305(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_304(struct workqueue_struct *ldv_func_arg1 ) ; __inline static void memcpy_fromio(void *dst , void const volatile *src , size_t count ) { { memcpy(dst, (void const *)src, count); return; } } extern void dev_warn(struct device const * , char const * , ...) ; int mid_chip_setup(struct drm_device *dev ) ; static void mid_get_fuse_settings(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct pci_dev *pci_root ; struct pci_dev *tmp ; uint32_t fuse_value ; uint32_t fuse_value_tmp ; int __ret_warn_on ; long tmp___0 ; struct _ddebug descriptor ; long tmp___1 ; struct _ddebug descriptor___0 ; long tmp___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = pci_get_bus_and_slot(0U, 0U); pci_root = tmp; fuse_value = 0U; fuse_value_tmp = 0U; if ((unsigned long )pci_root == (unsigned long )((struct pci_dev *)0)) { __ret_warn_on = 1; tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/mid_bios.c", 48); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return; } else { } pci_write_config_dword((struct pci_dev const *)pci_root, 208, 3498116608U); pci_read_config_dword((struct pci_dev const *)pci_root, 212, & fuse_value); if (((int )(dev->pdev)->device & 65520) == 16640) { dev_priv->iLVDS_enable = fuse_value & 2048U; } else { } printk("\016[drm] internal display is %s\n", dev_priv->iLVDS_enable != 0U ? (char *)"LVDS display" : (char *)"MIPI display"); if (dev_priv->iLVDS_enable != 0U) { dev_priv->is_lvds_on = 1; dev_priv->is_mipi_on = 0; } else { dev_priv->is_mipi_on = 1; dev_priv->is_lvds_on = 0; } dev_priv->video_device_fuse = fuse_value; pci_write_config_dword((struct pci_dev const *)pci_root, 208, 3498117376U); pci_read_config_dword((struct pci_dev const *)pci_root, 212, & fuse_value); descriptor.modname = "gma500_gfx"; descriptor.function = "mid_get_fuse_settings"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/mid_bios.c"; descriptor.format = "SKU values is 0x%x.\n"; descriptor.lineno = 77U; descriptor.flags = 0U; tmp___1 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___1 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "SKU values is 0x%x.\n", fuse_value); } else { } fuse_value_tmp = (fuse_value & 28672U) >> 12; dev_priv->fuse_reg_value = fuse_value; switch (fuse_value_tmp) { case 0U: dev_priv->core_freq = 200U; goto ldv_41530; case 1U: dev_priv->core_freq = 100U; goto ldv_41530; case 2U: dev_priv->core_freq = 166U; goto ldv_41530; default: dev_warn((struct device const *)dev->dev, "Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp); dev_priv->core_freq = 0U; } ldv_41530: descriptor___0.modname = "gma500_gfx"; descriptor___0.function = "mid_get_fuse_settings"; descriptor___0.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/mid_bios.c"; descriptor___0.format = "LNC core clk is %dMHz.\n"; descriptor___0.lineno = 97U; descriptor___0.flags = 0U; tmp___2 = ldv__builtin_expect((long )descriptor___0.flags & 1L, 0L); if (tmp___2 != 0L) { __dynamic_dev_dbg(& descriptor___0, (struct device const *)dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq); } else { } pci_dev_put(pci_root); return; } } static void mid_get_pci_revID(struct drm_psb_private *dev_priv ) { uint32_t platform_rev_id ; struct pci_dev *pci_gfx_root ; struct pci_dev *tmp ; int __ret_warn_on ; long tmp___0 ; struct _ddebug descriptor ; long tmp___1 ; { platform_rev_id = 0U; tmp = pci_get_bus_and_slot(0U, 16U); pci_gfx_root = tmp; if ((unsigned long )pci_gfx_root == (unsigned long )((struct pci_dev *)0)) { __ret_warn_on = 1; tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/mid_bios.c", 110); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return; } else { } pci_read_config_dword((struct pci_dev const *)pci_gfx_root, 8, & platform_rev_id); dev_priv->platform_rev_id = (unsigned char )platform_rev_id; pci_dev_put(pci_gfx_root); descriptor.modname = "gma500_gfx"; descriptor.function = "mid_get_pci_revID"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/mid_bios.c"; descriptor.format = "platform_rev_id is %x\n"; descriptor.lineno = 117U; descriptor.flags = 0U; tmp___1 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___1 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)(dev_priv->dev)->dev, "platform_rev_id is %x\n", (int )dev_priv->platform_rev_id); } else { } return; } } static int read_vbt_r0(u32 addr , struct vbt_r0 *vbt ) { void *vbt_virtual ; { vbt_virtual = ioremap((resource_size_t )addr, 7UL); if ((unsigned long )vbt_virtual == (unsigned long )((void *)0)) { return (-1); } else { } memcpy_fromio((void *)vbt, (void const volatile *)vbt_virtual, 7UL); iounmap((void volatile *)vbt_virtual); return (0); } } static int read_vbt_r10(u32 addr , struct vbt_r10 *vbt ) { void *vbt_virtual ; { vbt_virtual = ioremap((resource_size_t )addr, 16UL); if ((unsigned long )vbt_virtual == (unsigned long )((void *)0)) { return (-1); } else { } memcpy_fromio((void *)vbt, (void const volatile *)vbt_virtual, 16UL); iounmap((void volatile *)vbt_virtual); return (0); } } static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv , u32 addr ) { struct vbt_r0 vbt ; void *gct_virtual ; struct gct_r0 gct ; u8 bpi ; int tmp ; { tmp = read_vbt_r0(addr, & vbt); if (tmp != 0) { return (-1); } else { } gct_virtual = ioremap((resource_size_t )((unsigned long )addr + 7UL), (unsigned long )vbt.size - 7UL); if ((unsigned long )gct_virtual == (unsigned long )((void *)0)) { return (-1); } else { } memcpy_fromio((void *)(& gct), (void const volatile *)gct_virtual, 161UL); iounmap((void volatile *)gct_virtual); bpi = gct.__annonCompField77.PD.BootPanelIndex; dev_priv->gct_data.bpi = bpi; dev_priv->gct_data.pt = gct.__annonCompField77.PD.PanelType; dev_priv->gct_data.DTD = gct.panel[(int )bpi].DTD; dev_priv->gct_data.Panel_Port_Control = gct.panel[(int )bpi].Panel_Port_Control; dev_priv->gct_data.Panel_MIPI_Display_Descriptor = gct.panel[(int )bpi].Panel_MIPI_Display_Descriptor; return (0); } } static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv , u32 addr ) { struct vbt_r0 vbt ; void *gct_virtual ; struct gct_r1 gct ; u8 bpi ; int tmp ; { tmp = read_vbt_r0(addr, & vbt); if (tmp != 0) { return (-1); } else { } gct_virtual = ioremap((resource_size_t )((unsigned long )addr + 7UL), (unsigned long )vbt.size - 7UL); if ((unsigned long )gct_virtual == (unsigned long )((void *)0)) { return (-1); } else { } memcpy_fromio((void *)(& gct), (void const volatile *)gct_virtual, 153UL); iounmap((void volatile *)gct_virtual); bpi = gct.__annonCompField78.PD.BootPanelIndex; dev_priv->gct_data.bpi = bpi; dev_priv->gct_data.pt = gct.__annonCompField78.PD.PanelType; dev_priv->gct_data.DTD = gct.panel[(int )bpi].DTD; dev_priv->gct_data.Panel_Port_Control = gct.panel[(int )bpi].Panel_Port_Control; dev_priv->gct_data.Panel_MIPI_Display_Descriptor = gct.panel[(int )bpi].Panel_MIPI_Display_Descriptor; return (0); } } static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv , u32 addr ) { struct vbt_r10 vbt ; void *gct_virtual ; struct gct_r10 *gct ; struct oaktrail_timing_info *dp_ti ; struct gct_r10_timing_info *ti ; int ret ; int tmp ; void *tmp___0 ; { dp_ti = & dev_priv->gct_data.DTD; ret = -1; tmp = read_vbt_r10(addr, & vbt); if (tmp != 0) { return (-1); } else { } tmp___0 = kmalloc((unsigned long )vbt.panel_count * 28UL, 208U); gct = (struct gct_r10 *)tmp___0; if ((unsigned long )gct == (unsigned long )((struct gct_r10 *)0)) { return (-1); } else { } gct_virtual = ioremap((resource_size_t )((unsigned long )addr + 16UL), (unsigned long )vbt.panel_count * 28UL); if ((unsigned long )gct_virtual == (unsigned long )((void *)0)) { goto out; } else { } memcpy_fromio((void *)gct, (void const volatile *)gct_virtual, 28UL); iounmap((void volatile *)gct_virtual); dev_priv->gct_data.bpi = vbt.primary_panel_idx; dev_priv->gct_data.Panel_MIPI_Display_Descriptor = (gct + (unsigned long )vbt.primary_panel_idx)->Panel_MIPI_Display_Descriptor; ti = & (gct + (unsigned long )vbt.primary_panel_idx)->DTD; dp_ti->pixel_clock = ti->pixel_clock; dp_ti->hactive_hi = ti->hactive_hi; dp_ti->hactive_lo = ti->hactive_lo; dp_ti->hblank_hi = ti->hblank_hi; dp_ti->hblank_lo = ti->hblank_lo; dp_ti->hsync_offset_hi = ti->hsync_offset_hi; dp_ti->hsync_offset_lo = ti->hsync_offset_lo; dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi; dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo; dp_ti->vactive_hi = ti->vactive_hi; dp_ti->vactive_lo = ti->vactive_lo; dp_ti->vblank_hi = ti->vblank_hi; dp_ti->vblank_lo = ti->vblank_lo; dp_ti->vsync_offset_hi = ti->vsync_offset_hi; dp_ti->vsync_offset_lo = ti->vsync_offset_lo; dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi; dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo; ret = 0; out: kfree((void const *)gct); return (ret); } } static void mid_get_vbt_data(struct drm_psb_private *dev_priv ) { struct drm_device *dev ; u32 addr ; u8 *vbt_virtual ; struct mid_vbt_header vbt_header ; struct pci_dev *pci_gfx_root ; struct pci_dev *tmp ; int ret ; struct _ddebug descriptor ; long tmp___0 ; void *tmp___1 ; int tmp___2 ; struct _ddebug descriptor___0 ; long tmp___3 ; { dev = dev_priv->dev; tmp = pci_get_bus_and_slot(0U, 16U); pci_gfx_root = tmp; ret = -1; pci_read_config_dword((struct pci_dev const *)pci_gfx_root, 252, & addr); pci_dev_put(pci_gfx_root); descriptor.modname = "gma500_gfx"; descriptor.function = "mid_get_vbt_data"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/mid_bios.c"; descriptor.format = "drm platform config address is %x\n"; descriptor.lineno = 291U; descriptor.flags = 0U; tmp___0 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___0 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "drm platform config address is %x\n", addr); } else { } if (addr == 0U) { goto out; } else { } tmp___1 = ioremap((resource_size_t )addr, 5UL); vbt_virtual = (u8 *)tmp___1; if ((unsigned long )vbt_virtual == (unsigned long )((u8 *)0U)) { goto out; } else { } memcpy_fromio((void *)(& vbt_header), (void const volatile *)vbt_virtual, 5UL); iounmap((void volatile *)vbt_virtual); tmp___2 = memcmp((void const *)(& vbt_header.signature), (void const *)"$GCT", 4UL); if (tmp___2 != 0) { goto out; } else { } descriptor___0.modname = "gma500_gfx"; descriptor___0.function = "mid_get_vbt_data"; descriptor___0.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/mid_bios.c"; descriptor___0.format = "GCT revision is %02x\n"; descriptor___0.lineno = 307U; descriptor___0.flags = 0U; tmp___3 = ldv__builtin_expect((long )descriptor___0.flags & 1L, 0L); if (tmp___3 != 0L) { __dynamic_dev_dbg(& descriptor___0, (struct device const *)dev->dev, "GCT revision is %02x\n", (int )vbt_header.revision); } else { } switch ((int )vbt_header.revision) { case 0: ret = mid_get_vbt_data_r0(dev_priv, addr); goto ldv_41610; case 1: ret = mid_get_vbt_data_r1(dev_priv, addr); goto ldv_41610; case 16: ret = mid_get_vbt_data_r10(dev_priv, addr); goto ldv_41610; default: dev_err((struct device const *)dev->dev, "Unknown revision of GCT!\n"); } ldv_41610: ; out: ; if (ret != 0) { dev_err((struct device const *)dev->dev, "Unable to read GCT!"); } else { dev_priv->has_gct = 1; } return; } } int mid_chip_setup(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; mid_get_fuse_settings(dev); mid_get_vbt_data(dev_priv); mid_get_pci_revID(dev_priv); return (0); } } bool ldv_queue_work_on_301(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_302(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_303(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_304(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_305(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static void INIT_LIST_HEAD(struct list_head *list ) { { list->next = list; list->prev = list; return; } } extern void lockdep_init_map(struct lockdep_map * , char const * , struct lock_class_key * , int ) ; extern void __init_work(struct work_struct * , int ) ; extern struct workqueue_struct *system_wq ; bool ldv_queue_work_on_315(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_317(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_316(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_319(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_318(struct workqueue_struct *ldv_func_arg1 ) ; extern bool cancel_work_sync(struct work_struct * ) ; bool ldv_cancel_work_sync_320(struct work_struct *ldv_func_arg1 ) ; __inline static bool queue_work(struct workqueue_struct *wq , struct work_struct *work ) { bool tmp ; { tmp = ldv_queue_work_on_315(8192, wq, work); return (tmp); } } __inline static bool schedule_work(struct work_struct *work ) { bool tmp ; { tmp = queue_work(system_wq, work); return (tmp); } } extern void *ioremap_cache(resource_size_t , unsigned long ) ; void invoke_work_2(void) ; void disable_work_2(struct work_struct *work ) ; void call_and_disable_work_2(struct work_struct *work ) ; extern int register_acpi_notifier(struct notifier_block * ) ; extern int unregister_acpi_notifier(struct notifier_block * ) ; __inline static void *acpi_os_ioremap(acpi_physical_address phys , acpi_size size ) { void *tmp ; { tmp = ioremap_cache(phys, (unsigned long )size); return (tmp); } } static struct psb_intel_opregion *system_opregion ; static u32 asle_set_backlight(struct drm_device *dev , u32 bclp ) { struct drm_psb_private *dev_priv ; struct opregion_asle *asle ; struct backlight_device *bd ; long tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; asle = dev_priv->opregion.asle; bd = dev_priv->backlight_device; tmp = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("asle_set_backlight", "asle set backlight %x\n", bclp); } else { } if ((int )bclp >= 0) { return (4096U); } else { } if ((unsigned long )bd == (unsigned long )((struct backlight_device *)0)) { return (4096U); } else { } bclp = bclp & 2147483647U; if (bclp > 255U) { return (4096U); } else { } asle->cblv = (bclp * 100U) / 255U | 2147483648U; return (0U); } } static void psb_intel_opregion_asle_work(struct work_struct *work ) { struct psb_intel_opregion *opregion ; struct work_struct const *__mptr ; struct drm_psb_private *dev_priv ; struct psb_intel_opregion const *__mptr___0 ; struct opregion_asle *asle ; u32 asle_stat ; u32 asle_req ; long tmp ; u32 tmp___0 ; { __mptr = (struct work_struct const *)work; opregion = (struct psb_intel_opregion *)__mptr + 0xffffffffffffffd0UL; __mptr___0 = (struct psb_intel_opregion const *)opregion; dev_priv = (struct drm_psb_private *)__mptr___0 + 0xffffffffffffed40UL; asle = opregion->asle; asle_stat = 0U; if ((unsigned long )asle == (unsigned long )((struct opregion_asle *)0)) { return; } else { } asle_req = asle->aslc & 15U; if (asle_req == 0U) { tmp = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("psb_intel_opregion_asle_work", "non asle set request??\n"); } else { } return; } else { } if ((asle_req & 2U) != 0U) { tmp___0 = asle_set_backlight(dev_priv->dev, asle->bclp); asle_stat = tmp___0 | asle_stat; } else { } asle->aslc = asle_stat; return; } } void psb_intel_opregion_asle_intr(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if ((unsigned long )dev_priv->opregion.asle != (unsigned long )((struct opregion_asle *)0)) { schedule_work(& dev_priv->opregion.asle_work); } else { } return; } } void psb_intel_opregion_enable_asle(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct opregion_asle *asle ; { dev_priv = (struct drm_psb_private *)dev->dev_private; asle = dev_priv->opregion.asle; if ((unsigned long )asle != (unsigned long )((struct opregion_asle *)0) && (unsigned long )system_opregion != (unsigned long )((struct psb_intel_opregion *)0)) { psb_enable_pipestat(dev_priv, 0, 4194304U); psb_enable_pipestat(dev_priv, 1, 4194304U); asle->tche = 15U; asle->ardy = 1U; } else { } return; } } static int psb_intel_opregion_video_event(struct notifier_block *nb , unsigned long val , void *data ) { struct opregion_acpi *acpi ; { if ((unsigned long )system_opregion == (unsigned long )((struct psb_intel_opregion *)0)) { return (0); } else { } acpi = system_opregion->acpi; acpi->csts = 0U; return (1); } } static struct notifier_block psb_intel_opregion_notifier = {& psb_intel_opregion_video_event, 0, 0}; void psb_intel_opregion_init(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_intel_opregion *opregion ; { dev_priv = (struct drm_psb_private *)dev->dev_private; opregion = & dev_priv->opregion; if ((unsigned long )opregion->header == (unsigned long )((struct opregion_header *)0)) { return; } else { } if ((unsigned long )opregion->acpi != (unsigned long )((struct opregion_acpi *)0)) { (opregion->acpi)->csts = 0U; (opregion->acpi)->drdy = 1U; system_opregion = opregion; register_acpi_notifier(& psb_intel_opregion_notifier); } else { } return; } } void psb_intel_opregion_fini(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_intel_opregion *opregion ; { dev_priv = (struct drm_psb_private *)dev->dev_private; opregion = & dev_priv->opregion; if ((unsigned long )opregion->header == (unsigned long )((struct opregion_header *)0)) { return; } else { } if ((unsigned long )opregion->acpi != (unsigned long )((struct opregion_acpi *)0)) { (opregion->acpi)->drdy = 0U; system_opregion = (struct psb_intel_opregion *)0; unregister_acpi_notifier(& psb_intel_opregion_notifier); } else { } ldv_cancel_work_sync_320(& opregion->asle_work); iounmap((void volatile *)opregion->header); opregion->header = (struct opregion_header *)0; opregion->acpi = (struct opregion_acpi *)0; opregion->swsci = (struct opregion_swsci *)0; opregion->asle = (struct opregion_asle *)0; opregion->vbt = (void *)0; return; } } int psb_intel_opregion_setup(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_intel_opregion *opregion ; u32 opregion_phy ; u32 mboxes ; void *base ; int err ; long tmp ; struct lock_class_key __key ; atomic_long_t __constr_expr_0 ; long tmp___0 ; long tmp___1 ; int tmp___2 ; long tmp___3 ; long tmp___4 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; opregion = & dev_priv->opregion; err = 0; pci_read_config_dword((struct pci_dev const *)dev->pdev, 252, & opregion_phy); if (opregion_phy == 0U) { tmp = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("psb_intel_opregion_setup", "ACPI Opregion not supported\n"); } else { } return (-524); } else { } __init_work(& opregion->asle_work, 0); __constr_expr_0.counter = 137438953408L; opregion->asle_work.data = __constr_expr_0; lockdep_init_map(& opregion->asle_work.lockdep_map, "(&opregion->asle_work)", & __key, 0); INIT_LIST_HEAD(& opregion->asle_work.entry); opregion->asle_work.func = & psb_intel_opregion_asle_work; tmp___0 = ldv__builtin_expect((long )((int )drm_debug) & 1L, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("psb_intel_opregion_setup", "OpRegion detected at 0x%8x\n", opregion_phy); } else { } base = acpi_os_ioremap((acpi_physical_address )opregion_phy, 8192ULL); if ((unsigned long )base == (unsigned long )((void *)0)) { return (-12); } else { } tmp___2 = memcmp((void const *)base, (void const *)"IntelGraphicsMem", 16UL); if (tmp___2 != 0) { tmp___1 = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("psb_intel_opregion_setup", "opregion signature mismatch\n"); } else { } err = -22; goto err_out; } else { } opregion->header = (struct opregion_header *)base; opregion->vbt = base + 1024UL; opregion->lid_state = (u32 *)base + 428U; mboxes = (opregion->header)->mboxes; if ((int )mboxes & 1) { tmp___3 = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("psb_intel_opregion_setup", "Public ACPI methods supported\n"); } else { } opregion->acpi = (struct opregion_acpi *)base + 256U; } else { } if ((mboxes & 4U) != 0U) { tmp___4 = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("psb_intel_opregion_setup", "ASLE supported\n"); } else { } opregion->asle = (struct opregion_asle *)base + 768U; } else { } return (0); err_out: iounmap((void volatile *)base); return (err); } } void call_and_disable_all_2(int state ) { { if (ldv_work_2_0 == state) { call_and_disable_work_2(ldv_work_struct_2_0); } else { } if (ldv_work_2_1 == state) { call_and_disable_work_2(ldv_work_struct_2_1); } else { } if (ldv_work_2_2 == state) { call_and_disable_work_2(ldv_work_struct_2_2); } else { } if (ldv_work_2_3 == state) { call_and_disable_work_2(ldv_work_struct_2_3); } else { } return; } } void invoke_work_2(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ; if (ldv_work_2_0 == 2 || ldv_work_2_0 == 3) { ldv_work_2_0 = 4; psb_intel_opregion_asle_work(ldv_work_struct_2_0); ldv_work_2_0 = 1; } else { } goto ldv_45367; case 1: ; if (ldv_work_2_1 == 2 || ldv_work_2_1 == 3) { ldv_work_2_1 = 4; psb_intel_opregion_asle_work(ldv_work_struct_2_0); ldv_work_2_1 = 1; } else { } goto ldv_45367; case 2: ; if (ldv_work_2_2 == 2 || ldv_work_2_2 == 3) { ldv_work_2_2 = 4; psb_intel_opregion_asle_work(ldv_work_struct_2_0); ldv_work_2_2 = 1; } else { } goto ldv_45367; case 3: ; if (ldv_work_2_3 == 2 || ldv_work_2_3 == 3) { ldv_work_2_3 = 4; psb_intel_opregion_asle_work(ldv_work_struct_2_0); ldv_work_2_3 = 1; } else { } goto ldv_45367; default: ldv_stop(); } ldv_45367: ; return; } } void work_init_2(void) { { ldv_work_2_0 = 0; ldv_work_2_1 = 0; ldv_work_2_2 = 0; ldv_work_2_3 = 0; return; } } void activate_work_2(struct work_struct *work , int state ) { { if (ldv_work_2_0 == 0) { ldv_work_struct_2_0 = work; ldv_work_2_0 = state; return; } else { } if (ldv_work_2_1 == 0) { ldv_work_struct_2_1 = work; ldv_work_2_1 = state; return; } else { } if (ldv_work_2_2 == 0) { ldv_work_struct_2_2 = work; ldv_work_2_2 = state; return; } else { } if (ldv_work_2_3 == 0) { ldv_work_struct_2_3 = work; ldv_work_2_3 = state; return; } else { } return; } } void disable_work_2(struct work_struct *work ) { { if ((ldv_work_2_0 == 3 || ldv_work_2_0 == 2) && (unsigned long )ldv_work_struct_2_0 == (unsigned long )work) { ldv_work_2_0 = 1; } else { } if ((ldv_work_2_1 == 3 || ldv_work_2_1 == 2) && (unsigned long )ldv_work_struct_2_1 == (unsigned long )work) { ldv_work_2_1 = 1; } else { } if ((ldv_work_2_2 == 3 || ldv_work_2_2 == 2) && (unsigned long )ldv_work_struct_2_2 == (unsigned long )work) { ldv_work_2_2 = 1; } else { } if ((ldv_work_2_3 == 3 || ldv_work_2_3 == 2) && (unsigned long )ldv_work_struct_2_3 == (unsigned long )work) { ldv_work_2_3 = 1; } else { } return; } } void call_and_disable_work_2(struct work_struct *work ) { { if ((ldv_work_2_0 == 2 || ldv_work_2_0 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_2_0) { psb_intel_opregion_asle_work(work); ldv_work_2_0 = 1; return; } else { } if ((ldv_work_2_1 == 2 || ldv_work_2_1 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_2_1) { psb_intel_opregion_asle_work(work); ldv_work_2_1 = 1; return; } else { } if ((ldv_work_2_2 == 2 || ldv_work_2_2 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_2_2) { psb_intel_opregion_asle_work(work); ldv_work_2_2 = 1; return; } else { } if ((ldv_work_2_3 == 2 || ldv_work_2_3 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_2_3) { psb_intel_opregion_asle_work(work); ldv_work_2_3 = 1; return; } else { } return; } } void ldv_main_exported_34(void) { unsigned long ldvarg194 ; struct notifier_block *ldvarg192 ; void *tmp ; void *ldvarg193 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(24UL); ldvarg192 = (struct notifier_block *)tmp; tmp___0 = ldv_init_zalloc(1UL); ldvarg193 = tmp___0; ldv_memset((void *)(& ldvarg194), 0, 8UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_34 == 1) { psb_intel_opregion_video_event(ldvarg192, ldvarg194, ldvarg193); ldv_state_variable_34 = 1; } else { } goto ldv_45394; default: ldv_stop(); } ldv_45394: ; return; } } bool ldv_queue_work_on_315(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_316(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_317(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_318(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_319(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_cancel_work_sync_320(struct work_struct *ldv_func_arg1 ) { ldv_func_ret_type___4 ldv_func_res ; bool tmp ; { tmp = cancel_work_sync(ldv_func_arg1); ldv_func_res = tmp; disable_work_2(ldv_func_arg1); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_331(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_333(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_332(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_335(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_334(struct workqueue_struct *ldv_func_arg1 ) ; __inline static bool queue_work___0(struct workqueue_struct *wq , struct work_struct *work ) { bool tmp ; { tmp = ldv_queue_work_on_331(8192, wq, work); return (tmp); } } __inline static bool schedule_work___0(struct work_struct *work ) { bool tmp ; { tmp = queue_work___0(system_wq, work); return (tmp); } } __inline static void outb(unsigned char value , int port ) { { __asm__ volatile ("outb %b0, %w1": : "a" (value), "Nd" (port)); return; } } __inline static unsigned char inb(int port ) { unsigned char value ; { __asm__ volatile ("inb %w1, %b0": "=a" (value): "Nd" (port)); return (value); } } __inline static void outl(unsigned int value , int port ) { { __asm__ volatile ("outl %0, %w1": : "a" (value), "Nd" (port)); return; } } __inline static unsigned int inl(int port ) { unsigned int value ; { __asm__ volatile ("inl %w1, %0": "=a" (value): "Nd" (port)); return (value); } } void activate_work_3(struct work_struct *work , int state ) ; void call_and_disable_work_3(struct work_struct *work ) ; void disable_work_3(struct work_struct *work ) ; void invoke_work_3(void) ; void call_and_disable_all_3(int state ) ; extern int pci_bus_read_config_byte(struct pci_bus * , unsigned int , int , u8 * ) ; extern int pci_bus_write_config_byte(struct pci_bus * , unsigned int , int , u8 ) ; __inline static int pci_read_config_byte(struct pci_dev const *dev , int where , u8 *val ) { int tmp ; { tmp = pci_bus_read_config_byte(dev->bus, dev->devfn, where, val); return (tmp); } } __inline static int pci_write_config_byte(struct pci_dev const *dev , int where , u8 val ) { int tmp ; { tmp = pci_bus_write_config_byte(dev->bus, dev->devfn, where, (int )val); return (tmp); } } extern int pci_enable_msi_range(struct pci_dev * , int , int ) ; __inline static int pci_enable_msi_exact(struct pci_dev *dev , int nvec ) { int rc ; int tmp ; { tmp = pci_enable_msi_range(dev, nvec, nvec); rc = tmp; if (rc < 0) { return (rc); } else { } return (0); } } extern void drm_mode_config_reset(struct drm_device * ) ; extern void drm_helper_resume_force_mode(struct drm_device * ) ; extern bool drm_helper_hpd_irq_event(struct drm_device * ) ; void cdv_intel_dp_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev , int output_reg ) ; void cdv_intel_attach_force_audio_property(struct drm_connector *connector ) ; void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector ) ; struct drm_crtc_helper_funcs const cdv_intel_helper_funcs ; struct drm_crtc_funcs const cdv_intel_crtc_funcs ; struct gma_clock_funcs const cdv_clock_funcs ; void cdv_intel_crt_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) ; void cdv_intel_lvds_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) ; void cdv_hdmi_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev , int reg ) ; void cdv_update_wm(struct drm_device *dev , struct drm_crtc *crtc ) ; void cdv_disable_sr(struct drm_device *dev ) ; static void cdv_disable_vga(struct drm_device *dev ) { u8 sr1 ; u32 vga_reg ; { vga_reg = 463872U; outb(1, 964); sr1 = inb(965); outb((int )((unsigned int )sr1 | 32U), 965); __const_udelay(1288500UL); REGISTER_WRITE(dev, vga_reg, 2147483648U); REGISTER_READ(dev, vga_reg); return; } } static int cdv_output_init(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; uint32_t tmp ; uint32_t tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; drm_mode_create_scaling_mode_property(dev); cdv_disable_vga(dev); cdv_intel_crt_init(dev, & dev_priv->mode_dev); cdv_intel_lvds_init(dev, & dev_priv->mode_dev); tmp___0 = REGISTER_READ(dev, 397632U); if ((tmp___0 & 4U) != 0U) { cdv_hdmi_init(dev, & dev_priv->mode_dev, 397632); tmp = REGISTER_READ(dev, 409856U); if ((tmp & 4U) != 0U) { cdv_intel_dp_init(dev, & dev_priv->mode_dev, 409856); } else { } } else { } tmp___2 = REGISTER_READ(dev, 397664U); if ((tmp___2 & 4U) != 0U) { cdv_hdmi_init(dev, & dev_priv->mode_dev, 397664); tmp___1 = REGISTER_READ(dev, 410112U); if ((tmp___1 & 4U) != 0U) { cdv_intel_dp_init(dev, & dev_priv->mode_dev, 410112); } else { } } else { } return (0); } } __inline static u32 CDV_MSG_READ32(uint port , uint offset ) { int mcr ; uint32_t ret_val ; struct pci_dev *pci_root ; struct pci_dev *tmp ; { mcr = (int )(((port << 16) | (offset << 8)) | 268435456U); ret_val = 0U; tmp = pci_get_bus_and_slot(0U, 0U); pci_root = tmp; pci_write_config_dword((struct pci_dev const *)pci_root, 208, (u32 )mcr); pci_read_config_dword((struct pci_dev const *)pci_root, 212, & ret_val); pci_dev_put(pci_root); return (ret_val); } } __inline static void CDV_MSG_WRITE32(uint port , uint offset , u32 value ) { int mcr ; struct pci_dev *pci_root ; struct pci_dev *tmp ; { mcr = (int )(((port << 16) | (offset << 8)) | 285212912U); tmp = pci_get_bus_and_slot(0U, 0U); pci_root = tmp; pci_write_config_dword((struct pci_dev const *)pci_root, 212, value); pci_write_config_dword((struct pci_dev const *)pci_root, 208, (u32 )mcr); pci_dev_put(pci_root); return; } } static void cdv_init_pm(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 pwr_cnt ; int i ; u32 tmp ; u32 tmp___0 ; u32 pwr_sts ; unsigned int tmp___1 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = CDV_MSG_READ32(4U, 122U); dev_priv->apm_base = (uint16_t )tmp; tmp___0 = CDV_MSG_READ32(4U, 120U); dev_priv->ospm_base = tmp___0 & 65535U; pwr_cnt = inl((int )dev_priv->apm_base); pwr_cnt = pwr_cnt & 4294967292U; pwr_cnt = pwr_cnt | 2U; outl(pwr_cnt, (int )dev_priv->apm_base); i = 0; goto ldv_41598; ldv_41597: tmp___1 = inl((int )dev_priv->apm_base + 4); pwr_sts = tmp___1; if ((pwr_sts & 3U) == 0U) { return; } else { } __const_udelay(42950UL); i = i + 1; ldv_41598: ; if (i <= 4) { goto ldv_41597; } else { } dev_err((struct device const *)dev->dev, "GPU: power management timed out.\n"); return; } } static void cdv_errata(struct drm_device *dev ) { { CDV_MSG_WRITE32(3U, 48U, 134377736U); return; } } static int cdv_save_display_registers(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_save_area *regs ; struct drm_connector *connector ; struct _ddebug descriptor ; long tmp ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; regs = & dev_priv->regs; descriptor.modname = "gma500_gfx"; descriptor.function = "cdv_save_display_registers"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/cdv_device.c"; descriptor.format = "Saving GPU registers.\n"; descriptor.lineno = 270U; descriptor.flags = 0U; tmp = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "Saving GPU registers.\n"); } else { } pci_read_config_byte((struct pci_dev const *)dev->pdev, 244, & regs->__annonCompField80.cdv.saveLBB); regs->__annonCompField80.cdv.saveDSPCLK_GATE_D = REGISTER_READ(dev, 25088U); regs->__annonCompField80.cdv.saveRAMCLK_GATE_D = REGISTER_READ(dev, 25104U); regs->__annonCompField80.cdv.saveDSPARB = REGISTER_READ(dev, 458800U); regs->__annonCompField80.cdv.saveDSPFW[0] = REGISTER_READ(dev, 458804U); regs->__annonCompField80.cdv.saveDSPFW[1] = REGISTER_READ(dev, 458808U); regs->__annonCompField80.cdv.saveDSPFW[2] = REGISTER_READ(dev, 458812U); regs->__annonCompField80.cdv.saveDSPFW[3] = REGISTER_READ(dev, 458832U); regs->__annonCompField80.cdv.saveDSPFW[4] = REGISTER_READ(dev, 458836U); regs->__annonCompField80.cdv.saveDSPFW[5] = REGISTER_READ(dev, 458840U); regs->__annonCompField80.cdv.saveADPA = REGISTER_READ(dev, 397568U); regs->__annonCompField80.cdv.savePP_CONTROL = REGISTER_READ(dev, 397828U); regs->__annonCompField80.cdv.savePFIT_PGM_RATIOS = REGISTER_READ(dev, 397876U); regs->saveBLC_PWM_CTL = REGISTER_READ(dev, 397908U); regs->saveBLC_PWM_CTL2 = REGISTER_READ(dev, 397904U); regs->__annonCompField80.cdv.saveLVDS = REGISTER_READ(dev, 397696U); regs->__annonCompField80.cdv.savePFIT_CONTROL = REGISTER_READ(dev, 397872U); regs->__annonCompField80.cdv.savePP_ON_DELAYS = REGISTER_READ(dev, 397832U); regs->__annonCompField80.cdv.savePP_OFF_DELAYS = REGISTER_READ(dev, 397836U); regs->__annonCompField80.cdv.savePP_CYCLE = REGISTER_READ(dev, 397840U); regs->__annonCompField80.cdv.saveVGACNTRL = REGISTER_READ(dev, 463872U); regs->__annonCompField80.cdv.saveIER = REGISTER_READ(dev, 8352U); regs->__annonCompField80.cdv.saveIMR = REGISTER_READ(dev, 8360U); __mptr = (struct list_head const *)dev->mode_config.connector_list.next; connector = (struct drm_connector *)__mptr + 0xffffffffffffffe8UL; goto ldv_41616; ldv_41615: (*((connector->funcs)->dpms))(connector, 3); __mptr___0 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; ldv_41616: ; if ((unsigned long )(& connector->head) != (unsigned long )(& dev->mode_config.connector_list)) { goto ldv_41615; } else { } return (0); } } static int cdv_restore_display_registers(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_save_area *regs ; struct drm_connector *connector ; u32 temp ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; regs = & dev_priv->regs; pci_write_config_byte((struct pci_dev const *)dev->pdev, 244, (int )regs->__annonCompField80.cdv.saveLBB); REGISTER_WRITE(dev, 25088U, regs->__annonCompField80.cdv.saveDSPCLK_GATE_D); REGISTER_WRITE(dev, 25104U, regs->__annonCompField80.cdv.saveRAMCLK_GATE_D); REGISTER_WRITE(dev, 8464U, 0U); REGISTER_WRITE(dev, 8464U, 5U); temp = REGISTER_READ(dev, 24596U); if ((temp & 536870912U) == 0U) { REGISTER_WRITE(dev, 24596U, temp | 536870912U); REGISTER_READ(dev, 24596U); } else { } temp = REGISTER_READ(dev, 24600U); if ((temp & 536870912U) == 0U) { REGISTER_WRITE(dev, 24600U, temp | 536870912U); REGISTER_READ(dev, 24600U); } else { } __const_udelay(2147500UL); REGISTER_WRITE(dev, 458804U, regs->__annonCompField80.cdv.saveDSPFW[0]); REGISTER_WRITE(dev, 458808U, regs->__annonCompField80.cdv.saveDSPFW[1]); REGISTER_WRITE(dev, 458812U, regs->__annonCompField80.cdv.saveDSPFW[2]); REGISTER_WRITE(dev, 458832U, regs->__annonCompField80.cdv.saveDSPFW[3]); REGISTER_WRITE(dev, 458836U, regs->__annonCompField80.cdv.saveDSPFW[4]); REGISTER_WRITE(dev, 458840U, regs->__annonCompField80.cdv.saveDSPFW[5]); REGISTER_WRITE(dev, 458800U, regs->__annonCompField80.cdv.saveDSPARB); REGISTER_WRITE(dev, 397568U, regs->__annonCompField80.cdv.saveADPA); REGISTER_WRITE(dev, 397904U, regs->saveBLC_PWM_CTL2); REGISTER_WRITE(dev, 397696U, regs->__annonCompField80.cdv.saveLVDS); REGISTER_WRITE(dev, 397872U, regs->__annonCompField80.cdv.savePFIT_CONTROL); REGISTER_WRITE(dev, 397876U, regs->__annonCompField80.cdv.savePFIT_PGM_RATIOS); REGISTER_WRITE(dev, 397908U, regs->saveBLC_PWM_CTL); REGISTER_WRITE(dev, 397832U, regs->__annonCompField80.cdv.savePP_ON_DELAYS); REGISTER_WRITE(dev, 397836U, regs->__annonCompField80.cdv.savePP_OFF_DELAYS); REGISTER_WRITE(dev, 397840U, regs->__annonCompField80.cdv.savePP_CYCLE); REGISTER_WRITE(dev, 397828U, regs->__annonCompField80.cdv.savePP_CONTROL); REGISTER_WRITE(dev, 463872U, regs->__annonCompField80.cdv.saveVGACNTRL); REGISTER_WRITE(dev, 8352U, regs->__annonCompField80.cdv.saveIER); REGISTER_WRITE(dev, 8360U, regs->__annonCompField80.cdv.saveIMR); cdv_errata(dev); drm_mode_config_reset(dev); __mptr = (struct list_head const *)dev->mode_config.connector_list.next; connector = (struct drm_connector *)__mptr + 0xffffffffffffffe8UL; goto ldv_41630; ldv_41629: (*((connector->funcs)->dpms))(connector, 0); __mptr___0 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; ldv_41630: ; if ((unsigned long )(& connector->head) != (unsigned long )(& dev->mode_config.connector_list)) { goto ldv_41629; } else { } drm_helper_resume_force_mode(dev); return (0); } } static int cdv_power_down(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 pwr_cnt ; u32 pwr_mask ; u32 pwr_sts ; int tries ; int tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tries = 5; pwr_cnt = inl((int )dev_priv->apm_base); pwr_cnt = pwr_cnt & 4294967292U; pwr_cnt = pwr_cnt | 1U; pwr_mask = 3U; outl(pwr_cnt, (int )dev_priv->apm_base); goto ldv_41641; ldv_41640: pwr_sts = inl((int )dev_priv->apm_base + 4); if ((pwr_sts & pwr_mask) == 3U) { return (0); } else { } __const_udelay(42950UL); ldv_41641: tmp = tries; tries = tries - 1; if (tmp != 0) { goto ldv_41640; } else { } return (0); } } static int cdv_power_up(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 pwr_cnt ; u32 pwr_mask ; u32 pwr_sts ; int tries ; int tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tries = 5; pwr_cnt = inl((int )dev_priv->apm_base); pwr_cnt = pwr_cnt & 4294967292U; pwr_cnt = pwr_cnt | 2U; pwr_mask = 3U; outl(pwr_cnt, (int )dev_priv->apm_base); goto ldv_41652; ldv_41651: pwr_sts = inl((int )dev_priv->apm_base + 4); if ((pwr_sts & pwr_mask) == 0U) { return (0); } else { } __const_udelay(42950UL); ldv_41652: tmp = tries; tries = tries - 1; if (tmp != 0) { goto ldv_41651; } else { } return (0); } } static void cdv_hotplug_work_func(struct work_struct *work ) { struct drm_psb_private *dev_priv ; struct work_struct const *__mptr ; struct drm_device *dev ; { __mptr = (struct work_struct const *)work; dev_priv = (struct drm_psb_private *)__mptr + 0xffffffffffffee58UL; dev = dev_priv->dev; drm_helper_hpd_irq_event(dev); return; } } static int cdv_hotplug_event(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; uint32_t tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; schedule_work___0(& dev_priv->hotplug_work); tmp = REGISTER_READ(dev, 397588U); REGISTER_WRITE(dev, 397588U, tmp); return (1); } } static void cdv_hotplug_enable(struct drm_device *dev , bool on ) { u32 hotplug ; uint32_t tmp ; uint32_t tmp___0 ; { if ((int )on) { tmp = REGISTER_READ(dev, 397584U); hotplug = tmp; hotplug = hotplug | 939524608U; REGISTER_WRITE(dev, 397584U, hotplug); } else { REGISTER_WRITE(dev, 397584U, 0U); tmp___0 = REGISTER_READ(dev, 397588U); REGISTER_WRITE(dev, 397588U, tmp___0); } return; } } static char const *force_audio_names[3U] = { "off", "auto", "on"}; void cdv_intel_attach_force_audio_property(struct drm_connector *connector ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct drm_property *prop ; int i ; { dev = connector->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; prop = dev_priv->force_audio_property; if ((unsigned long )prop == (unsigned long )((struct drm_property *)0)) { prop = drm_property_create(dev, 8, "audio", 3); if ((unsigned long )prop == (unsigned long )((struct drm_property *)0)) { return; } else { } i = 0; goto ldv_41683; ldv_41682: drm_property_add_enum(prop, i, (uint64_t )(i + -1), force_audio_names[i]); i = i + 1; ldv_41683: ; if ((unsigned int )i <= 2U) { goto ldv_41682; } else { } dev_priv->force_audio_property = prop; } else { } drm_object_attach_property(& connector->base, prop, 0ULL); return; } } static char const *broadcast_rgb_names[2U] = { "Full", "Limited 16:235"}; void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct drm_property *prop ; int i ; { dev = connector->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; prop = dev_priv->broadcast_rgb_property; if ((unsigned long )prop == (unsigned long )((struct drm_property *)0)) { prop = drm_property_create(dev, 8, "Broadcast RGB", 2); if ((unsigned long )prop == (unsigned long )((struct drm_property *)0)) { return; } else { } i = 0; goto ldv_41698; ldv_41697: drm_property_add_enum(prop, i, (uint64_t )i, broadcast_rgb_names[i]); i = i + 1; ldv_41698: ; if ((unsigned int )i <= 1U) { goto ldv_41697; } else { } dev_priv->broadcast_rgb_property = prop; } else { } drm_object_attach_property(& connector->base, prop, 0ULL); return; } } static struct psb_offset const cdv_regmap[2U] = { {24640U, 24644U, 459136U, 458760U, 393244U, 24596U, 24604U, 393216U, 393220U, 393224U, 393228U, 393232U, 393236U, 459144U, 459152U, 459148U, 459164U, 459140U, 459140U, 458788U, 459140U, 459172U, 40960U}, {24648U, 24652U, 463232U, 462856U, 397340U, 24600U, 24608U, 397312U, 397316U, 397320U, 397324U, 397328U, 397332U, 463240U, 463248U, 463244U, 463260U, 463236U, 463236U, 462884U, 463236U, 463268U, 43008U}}; static int cdv_chip_setup(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct lock_class_key __key ; atomic_long_t __constr_expr_0 ; int tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; __init_work(& dev_priv->hotplug_work, 0); __constr_expr_0.counter = 137438953408L; dev_priv->hotplug_work.data = __constr_expr_0; lockdep_init_map(& dev_priv->hotplug_work.lockdep_map, "(&dev_priv->hotplug_work)", & __key, 0); INIT_LIST_HEAD(& dev_priv->hotplug_work.entry); dev_priv->hotplug_work.func = & cdv_hotplug_work_func; tmp = pci_enable_msi_exact(dev->pdev, 1); if (tmp != 0) { dev_warn((struct device const *)dev->dev, "Enabling MSI failed!\n"); } else { } dev_priv->regmap = (struct psb_offset const *)(& cdv_regmap); gma_get_core_freq(dev); psb_intel_opregion_init(dev); psb_intel_init_bios(dev); cdv_hotplug_enable(dev, 0); return (0); } } struct psb_ops const cdv_chip_ops = {"GMA3600/3650", 0U, 2, 2, 524288, 3, 2, 1, 0, & cdv_intel_helper_funcs, & cdv_intel_crtc_funcs, & cdv_clock_funcs, & cdv_chip_setup, 0, & cdv_errata, & cdv_output_init, & cdv_hotplug_event, & cdv_hotplug_enable, & cdv_init_pm, & cdv_save_display_registers, & cdv_restore_display_registers, & cdv_power_up, & cdv_power_down, & cdv_update_wm, & cdv_disable_sr, 0, 0}; void work_init_3(void) { { ldv_work_3_0 = 0; ldv_work_3_1 = 0; ldv_work_3_2 = 0; ldv_work_3_3 = 0; return; } } void activate_work_3(struct work_struct *work , int state ) { { if (ldv_work_3_0 == 0) { ldv_work_struct_3_0 = work; ldv_work_3_0 = state; return; } else { } if (ldv_work_3_1 == 0) { ldv_work_struct_3_1 = work; ldv_work_3_1 = state; return; } else { } if (ldv_work_3_2 == 0) { ldv_work_struct_3_2 = work; ldv_work_3_2 = state; return; } else { } if (ldv_work_3_3 == 0) { ldv_work_struct_3_3 = work; ldv_work_3_3 = state; return; } else { } return; } } void ldv_initialize_psb_ops_33(void) { void *tmp ; { tmp = ldv_init_zalloc(3320UL); cdv_chip_ops_group0 = (struct drm_device *)tmp; return; } } void call_and_disable_work_3(struct work_struct *work ) { { if ((ldv_work_3_0 == 2 || ldv_work_3_0 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_3_0) { cdv_hotplug_work_func(work); ldv_work_3_0 = 1; return; } else { } if ((ldv_work_3_1 == 2 || ldv_work_3_1 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_3_1) { cdv_hotplug_work_func(work); ldv_work_3_1 = 1; return; } else { } if ((ldv_work_3_2 == 2 || ldv_work_3_2 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_3_2) { cdv_hotplug_work_func(work); ldv_work_3_2 = 1; return; } else { } if ((ldv_work_3_3 == 2 || ldv_work_3_3 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_3_3) { cdv_hotplug_work_func(work); ldv_work_3_3 = 1; return; } else { } return; } } void disable_work_3(struct work_struct *work ) { { if ((ldv_work_3_0 == 3 || ldv_work_3_0 == 2) && (unsigned long )ldv_work_struct_3_0 == (unsigned long )work) { ldv_work_3_0 = 1; } else { } if ((ldv_work_3_1 == 3 || ldv_work_3_1 == 2) && (unsigned long )ldv_work_struct_3_1 == (unsigned long )work) { ldv_work_3_1 = 1; } else { } if ((ldv_work_3_2 == 3 || ldv_work_3_2 == 2) && (unsigned long )ldv_work_struct_3_2 == (unsigned long )work) { ldv_work_3_2 = 1; } else { } if ((ldv_work_3_3 == 3 || ldv_work_3_3 == 2) && (unsigned long )ldv_work_struct_3_3 == (unsigned long )work) { ldv_work_3_3 = 1; } else { } return; } } void invoke_work_3(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ; if (ldv_work_3_0 == 2 || ldv_work_3_0 == 3) { ldv_work_3_0 = 4; cdv_hotplug_work_func(ldv_work_struct_3_0); ldv_work_3_0 = 1; } else { } goto ldv_41732; case 1: ; if (ldv_work_3_1 == 2 || ldv_work_3_1 == 3) { ldv_work_3_1 = 4; cdv_hotplug_work_func(ldv_work_struct_3_0); ldv_work_3_1 = 1; } else { } goto ldv_41732; case 2: ; if (ldv_work_3_2 == 2 || ldv_work_3_2 == 3) { ldv_work_3_2 = 4; cdv_hotplug_work_func(ldv_work_struct_3_0); ldv_work_3_2 = 1; } else { } goto ldv_41732; case 3: ; if (ldv_work_3_3 == 2 || ldv_work_3_3 == 3) { ldv_work_3_3 = 4; cdv_hotplug_work_func(ldv_work_struct_3_0); ldv_work_3_3 = 1; } else { } goto ldv_41732; default: ldv_stop(); } ldv_41732: ; return; } } void call_and_disable_all_3(int state ) { { if (ldv_work_3_0 == state) { call_and_disable_work_3(ldv_work_struct_3_0); } else { } if (ldv_work_3_1 == state) { call_and_disable_work_3(ldv_work_struct_3_1); } else { } if (ldv_work_3_2 == state) { call_and_disable_work_3(ldv_work_struct_3_2); } else { } if (ldv_work_3_3 == state) { call_and_disable_work_3(ldv_work_struct_3_3); } else { } return; } } void ldv_main_exported_33(void) { struct drm_crtc *ldvarg0 ; void *tmp ; bool ldvarg1 ; int tmp___0 ; { tmp = ldv_init_zalloc(1160UL); ldvarg0 = (struct drm_crtc *)tmp; ldv_memset((void *)(& ldvarg1), 0, 1UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_33 == 1) { cdv_chip_setup(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 1: ; if (ldv_state_variable_33 == 1) { cdv_errata(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 2: ; if (ldv_state_variable_33 == 1) { cdv_init_pm(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 3: ; if (ldv_state_variable_33 == 1) { cdv_disable_sr(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 4: ; if (ldv_state_variable_33 == 1) { cdv_hotplug_enable(cdv_chip_ops_group0, (int )ldvarg1); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 5: ; if (ldv_state_variable_33 == 1) { cdv_hotplug_event(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 6: ; if (ldv_state_variable_33 == 1) { cdv_save_display_registers(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 7: ; if (ldv_state_variable_33 == 1) { cdv_restore_display_registers(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 8: ; if (ldv_state_variable_33 == 1) { cdv_update_wm(cdv_chip_ops_group0, ldvarg0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 9: ; if (ldv_state_variable_33 == 1) { cdv_power_down(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 10: ; if (ldv_state_variable_33 == 1) { cdv_output_init(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; case 11: ; if (ldv_state_variable_33 == 1) { cdv_power_up(cdv_chip_ops_group0); ldv_state_variable_33 = 1; } else { } goto ldv_41746; default: ldv_stop(); } ldv_41746: ; return; } } bool ldv_queue_work_on_331(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_332(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_333(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_334(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_335(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_345(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_347(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_346(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_349(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_348(struct workqueue_struct *ldv_func_arg1 ) ; static void cdv_intel_crt_dpms(struct drm_encoder *encoder , int mode ) { struct drm_device *dev ; u32 temp ; u32 reg ; { dev = encoder->dev; reg = 397568U; temp = REGISTER_READ(dev, reg); temp = temp & 4294964223U; temp = temp & 2147483647U; switch (mode) { case 0: temp = temp | 2147483648U; goto ldv_41573; case 1: temp = temp | 2147484672U; goto ldv_41573; case 2: temp = temp | 2147485696U; goto ldv_41573; case 3: temp = temp | 3072U; goto ldv_41573; } ldv_41573: REGISTER_WRITE(dev, reg, temp); return; } } static int cdv_intel_crt_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) { { if ((mode->flags & 32U) != 0U) { return (8); } else { } if (mode->clock <= 19999) { return (16); } else { } if (mode->clock > 355000) { return (15); } else { } return (0); } } static void cdv_intel_crt_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct drm_crtc *crtc ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int dpll_md_reg ; u32 adpa ; u32 dpll_md ; u32 adpa_reg ; { dev = encoder->dev; crtc = encoder->crtc; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; if (gma_crtc->pipe == 0) { dpll_md_reg = 24604; } else { dpll_md_reg = 24608; } adpa_reg = 397568U; dpll_md = REGISTER_READ(dev, (uint32_t )dpll_md_reg); REGISTER_WRITE(dev, (uint32_t )dpll_md_reg, dpll_md & 4294951167U); adpa = 0U; if ((int )adjusted_mode->flags & 1) { adpa = adpa | 8U; } else { } if ((adjusted_mode->flags & 4U) != 0U) { adpa = adpa | 16U; } else { } if (gma_crtc->pipe == 0) { adpa = adpa; } else { adpa = adpa | 1073741824U; } REGISTER_WRITE(dev, adpa_reg, adpa); return; } } static bool cdv_intel_crt_detect_hotplug(struct drm_connector *connector , bool force ) { struct drm_device *dev ; u32 hotplug_en ; int i ; int tries ; int ret ; u32 orig ; unsigned long timeout ; unsigned long tmp ; uint32_t tmp___0 ; uint32_t tmp___1 ; { dev = connector->dev; tries = 0; ret = 0; tries = 2; hotplug_en = REGISTER_READ(dev, 397584U); orig = hotplug_en; hotplug_en = hotplug_en & 4294967047U; hotplug_en = hotplug_en | 8U; hotplug_en = hotplug_en | 256U; hotplug_en = hotplug_en | 32U; i = 0; goto ldv_41615; ldv_41614: REGISTER_WRITE(dev, 397584U, hotplug_en); tmp = msecs_to_jiffies(1000U); timeout = tmp + (unsigned long )jiffies; ldv_41613: tmp___0 = REGISTER_READ(dev, 397584U); if ((tmp___0 & 8U) == 0U) { goto ldv_41606; } else { } msleep(1U); if ((long )((unsigned long )jiffies - timeout) < 0L) { goto ldv_41613; } else { } ldv_41606: i = i + 1; ldv_41615: ; if (i < tries) { goto ldv_41614; } else { } tmp___1 = REGISTER_READ(dev, 397588U); if ((tmp___1 & 768U) != 0U) { ret = 1; } else { } REGISTER_WRITE(dev, 397588U, 2048U); REGISTER_WRITE(dev, 397584U, orig); return (ret != 0); } } static enum drm_connector_status cdv_intel_crt_detect(struct drm_connector *connector , bool force ) { bool tmp ; { tmp = cdv_intel_crt_detect_hotplug(connector, (int )force); if ((int )tmp) { return (1); } else { return (2); } } } static void cdv_intel_crt_destroy(struct drm_connector *connector ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; psb_intel_i2c_destroy(gma_encoder->ddc_bus); drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree((void const *)connector); return; } } static int cdv_intel_crt_get_modes(struct drm_connector *connector ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; int tmp___0 ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; tmp___0 = psb_intel_ddc_get_modes(connector, & (gma_encoder->ddc_bus)->adapter); return (tmp___0); } } static int cdv_intel_crt_set_property(struct drm_connector *connector , struct drm_property *property , uint64_t value ) { { return (0); } } static struct drm_encoder_helper_funcs const cdv_intel_crt_helper_funcs = {& cdv_intel_crt_dpms, 0, 0, & gma_encoder_mode_fixup, & gma_encoder_prepare, & gma_encoder_commit, & cdv_intel_crt_mode_set, 0, 0, 0, 0, 0}; static struct drm_connector_funcs const cdv_intel_crt_connector_funcs = {& drm_helper_connector_dpms, 0, 0, 0, & cdv_intel_crt_detect, & drm_helper_probe_single_connector_modes, & cdv_intel_crt_set_property, & cdv_intel_crt_destroy, 0, 0, 0, 0, 0}; static struct drm_connector_helper_funcs const cdv_intel_crt_connector_helper_funcs = {& cdv_intel_crt_get_modes, (enum drm_mode_status (*)(struct drm_connector * , struct drm_display_mode * ))(& cdv_intel_crt_mode_valid), & gma_best_encoder}; static void cdv_intel_crt_enc_destroy(struct drm_encoder *encoder ) { { drm_encoder_cleanup(encoder); return; } } static struct drm_encoder_funcs const cdv_intel_crt_enc_funcs = {0, & cdv_intel_crt_enc_destroy}; void cdv_intel_crt_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) { struct gma_connector *gma_connector ; struct gma_encoder *gma_encoder ; struct drm_connector *connector ; struct drm_encoder *encoder ; u32 i2c_reg ; void *tmp ; void *tmp___0 ; { tmp = kzalloc(152UL, 208U); gma_encoder = (struct gma_encoder *)tmp; if ((unsigned long )gma_encoder == (unsigned long )((struct gma_encoder *)0)) { return; } else { } tmp___0 = kzalloc(944UL, 208U); gma_connector = (struct gma_connector *)tmp___0; if ((unsigned long )gma_connector == (unsigned long )((struct gma_connector *)0)) { goto failed_connector; } else { } connector = & gma_connector->base; connector->polled = 1U; drm_connector_init(dev, connector, & cdv_intel_crt_connector_funcs, 1); encoder = & gma_encoder->base; drm_encoder_init(dev, encoder, & cdv_intel_crt_enc_funcs, 1); gma_connector_attach_encoder(gma_connector, gma_encoder); i2c_reg = 20496U; gma_encoder->ddc_bus = psb_intel_i2c_create(dev, i2c_reg, "CRTDDC_A"); if ((unsigned long )gma_encoder->ddc_bus == (unsigned long )((struct psb_intel_i2c_chan *)0)) { dev_printk("\v", (struct device const *)(& (dev->pdev)->dev), "DDC bus registration failed.\n"); goto failed_ddc; } else { } gma_encoder->type = 1; connector->interlace_allowed = 0; connector->doublescan_allowed = 0; drm_encoder_helper_add(encoder, & cdv_intel_crt_helper_funcs); drm_connector_helper_add(connector, & cdv_intel_crt_connector_helper_funcs); drm_connector_register(connector); return; failed_ddc: drm_encoder_cleanup(& gma_encoder->base); drm_connector_cleanup(& gma_connector->base); kfree((void const *)gma_connector); failed_connector: kfree((void const *)gma_encoder); return; } } extern int ldv_probe_31(void) ; extern int ldv_probe_29(void) ; void ldv_initialize_drm_encoder_helper_funcs_32(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(96UL); cdv_intel_crt_helper_funcs_group0 = (struct drm_encoder *)tmp; tmp___0 = ldv_init_zalloc(208UL); cdv_intel_crt_helper_funcs_group1 = (struct drm_display_mode *)tmp___0; return; } } void ldv_initialize_drm_connector_funcs_31(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); cdv_intel_crt_connector_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_initialize_drm_connector_helper_funcs_30(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); cdv_intel_crt_connector_helper_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_main_exported_32(void) { struct drm_display_mode *ldvarg2 ; void *tmp ; struct drm_display_mode *ldvarg3 ; void *tmp___0 ; int ldvarg4 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg2 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg3 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg4), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_32 == 1) { cdv_intel_crt_dpms(cdv_intel_crt_helper_funcs_group0, ldvarg4); ldv_state_variable_32 = 1; } else { } goto ldv_41672; case 1: ; if (ldv_state_variable_32 == 1) { gma_encoder_mode_fixup(cdv_intel_crt_helper_funcs_group0, (struct drm_display_mode const *)ldvarg3, cdv_intel_crt_helper_funcs_group1); ldv_state_variable_32 = 1; } else { } goto ldv_41672; case 2: ; if (ldv_state_variable_32 == 1) { gma_encoder_commit(cdv_intel_crt_helper_funcs_group0); ldv_state_variable_32 = 1; } else { } goto ldv_41672; case 3: ; if (ldv_state_variable_32 == 1) { cdv_intel_crt_mode_set(cdv_intel_crt_helper_funcs_group0, cdv_intel_crt_helper_funcs_group1, ldvarg2); ldv_state_variable_32 = 1; } else { } goto ldv_41672; case 4: ; if (ldv_state_variable_32 == 1) { gma_encoder_prepare(cdv_intel_crt_helper_funcs_group0); ldv_state_variable_32 = 1; } else { } goto ldv_41672; default: ldv_stop(); } ldv_41672: ; return; } } void ldv_main_exported_30(void) { struct drm_display_mode *ldvarg18 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(208UL); ldvarg18 = (struct drm_display_mode *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_30 == 1) { cdv_intel_crt_get_modes(cdv_intel_crt_connector_helper_funcs_group0); ldv_state_variable_30 = 1; } else { } goto ldv_41683; case 1: ; if (ldv_state_variable_30 == 1) { cdv_intel_crt_mode_valid(cdv_intel_crt_connector_helper_funcs_group0, ldvarg18); ldv_state_variable_30 = 1; } else { } goto ldv_41683; case 2: ; if (ldv_state_variable_30 == 1) { gma_best_encoder(cdv_intel_crt_connector_helper_funcs_group0); ldv_state_variable_30 = 1; } else { } goto ldv_41683; default: ldv_stop(); } ldv_41683: ; return; } } void ldv_main_exported_31(void) { uint32_t ldvarg99 ; bool ldvarg103 ; uint32_t ldvarg100 ; uint64_t ldvarg101 ; struct drm_property *ldvarg102 ; void *tmp ; int ldvarg104 ; int tmp___0 ; { tmp = ldv_init_zalloc(104UL); ldvarg102 = (struct drm_property *)tmp; ldv_memset((void *)(& ldvarg99), 0, 4UL); ldv_memset((void *)(& ldvarg103), 0, 1UL); ldv_memset((void *)(& ldvarg100), 0, 4UL); ldv_memset((void *)(& ldvarg101), 0, 8UL); ldv_memset((void *)(& ldvarg104), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_31 == 1) { drm_helper_connector_dpms(cdv_intel_crt_connector_funcs_group0, ldvarg104); ldv_state_variable_31 = 1; } else { } if (ldv_state_variable_31 == 2) { drm_helper_connector_dpms(cdv_intel_crt_connector_funcs_group0, ldvarg104); ldv_state_variable_31 = 2; } else { } goto ldv_41697; case 1: ; if (ldv_state_variable_31 == 1) { cdv_intel_crt_detect(cdv_intel_crt_connector_funcs_group0, (int )ldvarg103); ldv_state_variable_31 = 1; } else { } if (ldv_state_variable_31 == 2) { cdv_intel_crt_detect(cdv_intel_crt_connector_funcs_group0, (int )ldvarg103); ldv_state_variable_31 = 2; } else { } goto ldv_41697; case 2: ; if (ldv_state_variable_31 == 1) { cdv_intel_crt_set_property(cdv_intel_crt_connector_funcs_group0, ldvarg102, ldvarg101); ldv_state_variable_31 = 1; } else { } if (ldv_state_variable_31 == 2) { cdv_intel_crt_set_property(cdv_intel_crt_connector_funcs_group0, ldvarg102, ldvarg101); ldv_state_variable_31 = 2; } else { } goto ldv_41697; case 3: ; if (ldv_state_variable_31 == 2) { cdv_intel_crt_destroy(cdv_intel_crt_connector_funcs_group0); ldv_state_variable_31 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41697; case 4: ; if (ldv_state_variable_31 == 1) { drm_helper_probe_single_connector_modes(cdv_intel_crt_connector_funcs_group0, ldvarg100, ldvarg99); ldv_state_variable_31 = 1; } else { } if (ldv_state_variable_31 == 2) { drm_helper_probe_single_connector_modes(cdv_intel_crt_connector_funcs_group0, ldvarg100, ldvarg99); ldv_state_variable_31 = 2; } else { } goto ldv_41697; case 5: ; if (ldv_state_variable_31 == 1) { ldv_probe_31(); ldv_state_variable_31 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41697; default: ldv_stop(); } ldv_41697: ; return; } } void ldv_main_exported_29(void) { struct drm_encoder *ldvarg138 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(96UL); ldvarg138 = (struct drm_encoder *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_29 == 2) { cdv_intel_crt_enc_destroy(ldvarg138); ldv_state_variable_29 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41709; case 1: ; if (ldv_state_variable_29 == 1) { ldv_probe_29(); ldv_state_variable_29 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41709; default: ldv_stop(); } ldv_41709: ; return; } } bool ldv_queue_work_on_345(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_346(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_347(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_348(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_349(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_359(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_361(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_360(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_363(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_362(struct workqueue_struct *ldv_func_arg1 ) ; void cdv_intel_dp_set_m_n(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) ; int cdv_sb_read(struct drm_device *dev , u32 reg , u32 *val ) ; int cdv_sb_write(struct drm_device *dev , u32 reg , u32 val ) ; void cdv_sb_reset(struct drm_device *dev ) ; struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev , struct drm_crtc *crtc ) ; static bool cdv_intel_find_dp_pll(struct gma_limit_t const *limit , struct drm_crtc *crtc , int target , int refclk , struct gma_clock_t *best_clock ) ; static struct gma_limit_t const cdv_intel_limits[6U] = { {{20000, 115500}, {1800000, 3600000}, {2, 6}, {60, 160}, {0, 0}, {58, 158}, {28, 140}, {2, 10}, {200000, 14, 14}, & gma_find_best_pll}, {{20000, 115500}, {1800000, 3600000}, {2, 6}, {60, 160}, {0, 0}, {58, 158}, {28, 140}, {2, 10}, {200000, 14, 14}, & gma_find_best_pll}, {{20000, 400000}, {1809000, 3564000}, {1, 1}, {67, 132}, {0, 0}, {65, 130}, {5, 90}, {1, 9}, {225000, 10, 5}, & gma_find_best_pll}, {{20000, 400000}, {1800000, 3600000}, {2, 6}, {60, 160}, {0, 0}, {58, 158}, {5, 100}, {1, 10}, {225000, 10, 5}, & gma_find_best_pll}, {{160000, 272000}, {1809000, 3564000}, {1, 1}, {67, 132}, {0, 0}, {65, 130}, {5, 90}, {1, 9}, {225000, 10, 10}, & cdv_intel_find_dp_pll}, {{160000, 272000}, {1800000, 3600000}, {2, 6}, {60, 164}, {0, 0}, {58, 162}, {5, 100}, {1, 10}, {225000, 10, 10}, & cdv_intel_find_dp_pll}}; int cdv_sb_read(struct drm_device *dev , u32 reg , u32 *val ) { int ret ; unsigned long timeout__ ; unsigned long tmp ; int ret__ ; int pscr_ret__ ; void const *__vpp_verify ; int pfo_ret__ ; int pfo_ret_____0 ; int pfo_ret_____1 ; int pfo_ret_____2 ; int tmp___0 ; uint32_t tmp___1 ; unsigned long timeout_____0 ; unsigned long tmp___2 ; int ret_____0 ; int pscr_ret_____0 ; void const *__vpp_verify___0 ; int pfo_ret_____3 ; int pfo_ret_____4 ; int pfo_ret_____5 ; int pfo_ret_____6 ; int tmp___3 ; uint32_t tmp___4 ; { tmp = msecs_to_jiffies(1000U); timeout__ = tmp + (unsigned long )jiffies; ret__ = 0; goto ldv_41755; ldv_41754: ; if ((long )(timeout__ - (unsigned long )jiffies) < 0L) { ret__ = -110; goto ldv_41712; } else { } __vpp_verify = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret__): "m" (cpu_number)); goto ldv_41718; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41718; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41718; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41718; default: __bad_percpu_size(); } ldv_41718: pscr_ret__ = pfo_ret__; goto ldv_41724; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41728; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41728; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41728; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41728; default: __bad_percpu_size(); } ldv_41728: pscr_ret__ = pfo_ret_____0; goto ldv_41724; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41737; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41737; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41737; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41737; default: __bad_percpu_size(); } ldv_41737: pscr_ret__ = pfo_ret_____1; goto ldv_41724; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41746; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41746; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41746; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41746; default: __bad_percpu_size(); } ldv_41746: pscr_ret__ = pfo_ret_____2; goto ldv_41724; default: __bad_size_call_parameter(); goto ldv_41724; } ldv_41724: tmp___0 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret__ != tmp___0) { msleep(1U); } else { } ldv_41755: tmp___1 = REGISTER_READ(dev, 8448U); if ((int )tmp___1 & 1) { goto ldv_41754; } else { } ldv_41712: ret = ret__; if (ret != 0) { drm_err("timeout waiting for SB to idle before read\n"); return (ret); } else { } REGISTER_WRITE(dev, 8456U, reg); REGISTER_WRITE(dev, 8448U, 35056U); tmp___2 = msecs_to_jiffies(1000U); timeout_____0 = tmp___2 + (unsigned long )jiffies; ret_____0 = 0; goto ldv_41808; ldv_41807: ; if ((long )(timeout_____0 - (unsigned long )jiffies) < 0L) { ret_____0 = -110; goto ldv_41765; } else { } __vpp_verify___0 = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41771; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41771; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41771; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41771; default: __bad_percpu_size(); } ldv_41771: pscr_ret_____0 = pfo_ret_____3; goto ldv_41777; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41781; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41781; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41781; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41781; default: __bad_percpu_size(); } ldv_41781: pscr_ret_____0 = pfo_ret_____4; goto ldv_41777; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41790; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41790; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41790; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41790; default: __bad_percpu_size(); } ldv_41790: pscr_ret_____0 = pfo_ret_____5; goto ldv_41777; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41799; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41799; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41799; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41799; default: __bad_percpu_size(); } ldv_41799: pscr_ret_____0 = pfo_ret_____6; goto ldv_41777; default: __bad_size_call_parameter(); goto ldv_41777; } ldv_41777: tmp___3 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret_____0 != tmp___3) { msleep(1U); } else { } ldv_41808: tmp___4 = REGISTER_READ(dev, 8448U); if ((int )tmp___4 & 1) { goto ldv_41807; } else { } ldv_41765: ret = ret_____0; if (ret != 0) { drm_err("timeout waiting for SB to idle after read\n"); return (ret); } else { } *val = REGISTER_READ(dev, 8452U); return (0); } } int cdv_sb_write(struct drm_device *dev , u32 reg , u32 val ) { int ret ; bool dpio_debug ; u32 temp ; long tmp ; int tmp___0 ; long tmp___1 ; unsigned long timeout__ ; unsigned long tmp___2 ; int ret__ ; int pscr_ret__ ; void const *__vpp_verify ; int pfo_ret__ ; int pfo_ret_____0 ; int pfo_ret_____1 ; int pfo_ret_____2 ; int tmp___3 ; uint32_t tmp___4 ; unsigned long timeout_____0 ; unsigned long tmp___5 ; int ret_____0 ; int pscr_ret_____0 ; void const *__vpp_verify___0 ; int pfo_ret_____3 ; int pfo_ret_____4 ; int pfo_ret_____5 ; int pfo_ret_____6 ; int tmp___6 ; uint32_t tmp___7 ; long tmp___8 ; int tmp___9 ; { dpio_debug = 1; if ((int )dpio_debug) { tmp___0 = cdv_sb_read(dev, reg, & temp); if (tmp___0 == 0) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_sb_write", "0x%08x: 0x%08x (before)\n", reg, temp); } else { } } else { } tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("cdv_sb_write", "0x%08x: 0x%08x\n", reg, val); } else { } } else { } tmp___2 = msecs_to_jiffies(1000U); timeout__ = tmp___2 + (unsigned long )jiffies; ret__ = 0; goto ldv_41870; ldv_41869: ; if ((long )(timeout__ - (unsigned long )jiffies) < 0L) { ret__ = -110; goto ldv_41827; } else { } __vpp_verify = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret__): "m" (cpu_number)); goto ldv_41833; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41833; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41833; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41833; default: __bad_percpu_size(); } ldv_41833: pscr_ret__ = pfo_ret__; goto ldv_41839; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41843; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41843; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41843; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41843; default: __bad_percpu_size(); } ldv_41843: pscr_ret__ = pfo_ret_____0; goto ldv_41839; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41852; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41852; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41852; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41852; default: __bad_percpu_size(); } ldv_41852: pscr_ret__ = pfo_ret_____1; goto ldv_41839; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41861; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41861; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41861; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41861; default: __bad_percpu_size(); } ldv_41861: pscr_ret__ = pfo_ret_____2; goto ldv_41839; default: __bad_size_call_parameter(); goto ldv_41839; } ldv_41839: tmp___3 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret__ != tmp___3) { msleep(1U); } else { } ldv_41870: tmp___4 = REGISTER_READ(dev, 8448U); if ((int )tmp___4 & 1) { goto ldv_41869; } else { } ldv_41827: ret = ret__; if (ret != 0) { drm_err("timeout waiting for SB to idle before write\n"); return (ret); } else { } REGISTER_WRITE(dev, 8456U, reg); REGISTER_WRITE(dev, 8452U, val); REGISTER_WRITE(dev, 8448U, 100592U); tmp___5 = msecs_to_jiffies(1000U); timeout_____0 = tmp___5 + (unsigned long )jiffies; ret_____0 = 0; goto ldv_41923; ldv_41922: ; if ((long )(timeout_____0 - (unsigned long )jiffies) < 0L) { ret_____0 = -110; goto ldv_41880; } else { } __vpp_verify___0 = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41886; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41886; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41886; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____3): "m" (cpu_number)); goto ldv_41886; default: __bad_percpu_size(); } ldv_41886: pscr_ret_____0 = pfo_ret_____3; goto ldv_41892; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41896; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41896; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41896; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____4): "m" (cpu_number)); goto ldv_41896; default: __bad_percpu_size(); } ldv_41896: pscr_ret_____0 = pfo_ret_____4; goto ldv_41892; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41905; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41905; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41905; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____5): "m" (cpu_number)); goto ldv_41905; default: __bad_percpu_size(); } ldv_41905: pscr_ret_____0 = pfo_ret_____5; goto ldv_41892; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41914; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41914; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41914; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____6): "m" (cpu_number)); goto ldv_41914; default: __bad_percpu_size(); } ldv_41914: pscr_ret_____0 = pfo_ret_____6; goto ldv_41892; default: __bad_size_call_parameter(); goto ldv_41892; } ldv_41892: tmp___6 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret_____0 != tmp___6) { msleep(1U); } else { } ldv_41923: tmp___7 = REGISTER_READ(dev, 8448U); if ((int )tmp___7 & 1) { goto ldv_41922; } else { } ldv_41880: ret = ret_____0; if (ret != 0) { drm_err("timeout waiting for SB to idle after write\n"); return (ret); } else { } if ((int )dpio_debug) { tmp___9 = cdv_sb_read(dev, reg, & temp); if (tmp___9 == 0) { tmp___8 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___8 != 0L) { drm_ut_debug_printk("cdv_sb_write", "0x%08x: 0x%08x (after)\n", reg, temp); } else { } } else { } } else { } return (0); } } void cdv_sb_reset(struct drm_device *dev ) { { REGISTER_WRITE(dev, 8464U, 0U); REGISTER_READ(dev, 8464U); REGISTER_WRITE(dev, 8464U, 5U); return; } } static int cdv_dpll_set_clock_cdv(struct drm_device *dev , struct drm_crtc *crtc , struct gma_clock_t *clock , bool is_lvds , u32 ddi_select ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; u32 m ; u32 n_vco ; u32 p ; int ret ; int dpll_reg ; int ref_sfr ; u32 ref_value ; u32 lane_reg ; u32 lane_value ; long tmp ; long tmp___0 ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; ret = 0; dpll_reg = pipe == 0 ? 24596 : 24600; ref_sfr = pipe == 0 ? 32784 : 32816; cdv_sb_reset(dev); REGISTER_WRITE(dev, (uint32_t )dpll_reg, 805306368U); __const_udelay(429500UL); ref_value = 6858497U; cdv_sb_write(dev, (u32 )(pipe * 32 + 32792), ref_value); ret = cdv_sb_read(dev, (u32 )ref_sfr, & ref_value); if (ret != 0) { return (ret); } else { } ref_value = ref_value & 4294942719U; if ((pipe == 1 && ! is_lvds) && (ddi_select & 32768U) == 0U) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_dpll_set_clock_cdv", "use DPLLA for pipe B\n"); } else { } ref_value = ref_value | 16384U; } else { tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("cdv_dpll_set_clock_cdv", "use their DPLL for pipe A/B\n"); } else { } ref_value = ref_value | 8192U; } ret = cdv_sb_write(dev, (u32 )ref_sfr, ref_value); if (ret != 0) { return (ret); } else { } ret = cdv_sb_read(dev, (u32 )(pipe * 32 + 32776), & m); if (ret != 0) { return (ret); } else { } m = m & 16777215U; m = (u32 )(clock->m2 << 24) | m; ret = cdv_sb_write(dev, (u32 )(pipe * 32 + 32776), m); if (ret != 0) { return (ret); } else { } ret = cdv_sb_read(dev, (u32 )(pipe * 32 + 32788), & n_vco); if (ret != 0) { return (ret); } else { } n_vco = n_vco & 65535U; n_vco = n_vco | 263U; n_vco = n_vco & 16777215U; n_vco = (u32 )(clock->n << 26) | n_vco; if (clock->vco <= 2249999) { n_vco = n_vco | 33554432U; n_vco = n_vco; } else if (clock->vco <= 2749999) { n_vco = n_vco | 16777216U; n_vco = n_vco | 1073741824U; } else if (clock->vco <= 3299999) { n_vco = n_vco; n_vco = n_vco | 2147483648U; } else { n_vco = n_vco; n_vco = n_vco | 3221225472U; } ret = cdv_sb_write(dev, (u32 )(pipe * 32 + 32788), n_vco); if (ret != 0) { return (ret); } else { } ret = cdv_sb_read(dev, (u32 )(pipe * 32 + 32796), & p); if (ret != 0) { return (ret); } else { } p = p & 1073680383U; p = ((u32 )(clock->p1 << 12) & 65535U) | p; switch (clock->p2) { case 5: p = p | 1073741824U; goto ldv_41950; case 10: p = p; goto ldv_41950; case 14: p = p | 2147483648U; goto ldv_41950; case 7: p = p | 3221225472U; goto ldv_41950; default: drm_err("Bad P2 clock: %d\n", clock->p2); return (-22); } ldv_41950: ret = cdv_sb_write(dev, (u32 )(pipe * 32 + 32796), p); if (ret != 0) { return (ret); } else { } if (ddi_select != 0U) { if ((ddi_select & 3U) == 1U) { lane_reg = 288U; cdv_sb_read(dev, lane_reg, & lane_value); lane_value = lane_value & 4287627263U; lane_value = lane_value | 3145728U; cdv_sb_write(dev, lane_reg, lane_value); lane_reg = 544U; cdv_sb_read(dev, lane_reg, & lane_value); lane_value = lane_value & 4287627263U; lane_value = lane_value | 3145728U; cdv_sb_write(dev, lane_reg, lane_value); } else { lane_reg = 8992U; cdv_sb_read(dev, lane_reg, & lane_value); lane_value = lane_value & 4287627263U; lane_value = lane_value | 3145728U; cdv_sb_write(dev, lane_reg, lane_value); lane_reg = 9248U; cdv_sb_read(dev, lane_reg, & lane_value); lane_value = lane_value & 4287627263U; lane_value = lane_value | 3145728U; cdv_sb_write(dev, lane_reg, lane_value); } } else { } return (0); } } static struct gma_limit_t const *cdv_intel_limit(struct drm_crtc *crtc , int refclk ) { struct gma_limit_t const *limit ; bool tmp ; bool tmp___0 ; bool tmp___1 ; { tmp___1 = gma_pipe_has_type(crtc, 4); if ((int )tmp___1) { if (refclk == 96000) { limit = (struct gma_limit_t const *)(& cdv_intel_limits); } else { limit = (struct gma_limit_t const *)(& cdv_intel_limits) + 1UL; } } else { tmp = gma_pipe_has_type(crtc, 9); if ((int )tmp) { goto _L; } else { tmp___0 = gma_pipe_has_type(crtc, 10); if ((int )tmp___0) { _L: /* CIL Label */ if (refclk == 27000) { limit = (struct gma_limit_t const *)(& cdv_intel_limits) + 4UL; } else { limit = (struct gma_limit_t const *)(& cdv_intel_limits) + 5UL; } } else if (refclk == 27000) { limit = (struct gma_limit_t const *)(& cdv_intel_limits) + 2UL; } else { limit = (struct gma_limit_t const *)(& cdv_intel_limits) + 3UL; } } } return (limit); } } static void cdv_intel_clock(int refclk , struct gma_clock_t *clock ) { { clock->m = clock->m2 + 2; clock->p = clock->p1 * clock->p2; clock->vco = (clock->m * refclk) / clock->n; clock->dot = clock->vco / clock->p; return; } } static bool cdv_intel_find_dp_pll(struct gma_limit_t const *limit , struct drm_crtc *crtc , int target , int refclk , struct gma_clock_t *best_clock ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct gma_clock_t clock ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; switch (refclk) { case 27000: ; if (target <= 199999) { clock.p1 = 2; clock.p2 = 10; clock.n = 1; clock.m1 = 0; clock.m2 = 118; } else { clock.p1 = 1; clock.p2 = 10; clock.n = 1; clock.m1 = 0; clock.m2 = 98; } goto ldv_41976; case 100000: ; if (target <= 199999) { clock.p1 = 2; clock.p2 = 10; clock.n = 5; clock.m1 = 0; clock.m2 = 160; } else { clock.p1 = 1; clock.p2 = 10; clock.n = 5; clock.m1 = 0; clock.m2 = 133; } goto ldv_41976; default: ; return (0); } ldv_41976: (*((gma_crtc->clock_funcs)->clock))(refclk, & clock); memcpy((void *)best_clock, (void const *)(& clock), 36UL); return (1); } } static bool cdv_intel_pipe_enabled(struct drm_device *dev , int pipe ) { struct drm_crtc *crtc ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; { dev_priv = (struct drm_psb_private *)dev->dev_private; gma_crtc = (struct gma_crtc *)0; crtc = dev_priv->pipe_to_crtc_mapping[pipe]; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; if ((unsigned long )(crtc->primary)->fb == (unsigned long )((struct drm_framebuffer *)0) || ! gma_crtc->active) { return (0); } else { } return (1); } } void cdv_disable_sr(struct drm_device *dev ) { uint32_t tmp ; uint32_t tmp___0 ; { tmp___0 = REGISTER_READ(dev, 8416U); if ((tmp___0 & 32768U) != 0U) { tmp = REGISTER_READ(dev, 8416U); REGISTER_WRITE(dev, 8416U, tmp & 4294934527U); REGISTER_READ(dev, 8416U); gma_wait_for_vblank(dev); REGISTER_WRITE(dev, 196608U, 0U); REGISTER_READ(dev, 196608U); gma_wait_for_vblank(dev); } else { } return; } } void cdv_update_wm(struct drm_device *dev , struct drm_crtc *crtc ) { struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; u32 fw ; bool tmp ; bool tmp___0 ; bool tmp___1 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; tmp___0 = cdv_intel_pipe_enabled(dev, 0); tmp___1 = cdv_intel_pipe_enabled(dev, 1); if ((int )tmp___0 != (int )tmp___1) { fw = REGISTER_READ(dev, 458804U); fw = fw & 8388607U; fw = fw | 1056964608U; fw = fw & 4290838527U; fw = fw | 262144U; REGISTER_WRITE(dev, 458804U, fw); fw = REGISTER_READ(dev, 458808U); fw = fw & 4294951167U; fw = fw | 1536U; fw = fw & 4294967168U; fw = fw | 8U; REGISTER_WRITE(dev, 458808U, fw); REGISTER_WRITE(dev, 458812U, 905969664U); if (gma_crtc->pipe == 1) { tmp = gma_pipe_has_type(crtc, 4); if ((int )tmp) { REGISTER_WRITE(dev, 458836U, 262960U); } else { fw = 50594564U; REGISTER_WRITE(dev, 458836U, fw); } } else { fw = 50594564U; REGISTER_WRITE(dev, 458836U, fw); } REGISTER_WRITE(dev, 458840U, 16U); gma_wait_for_vblank(dev); REGISTER_WRITE(dev, 8416U, 32768U); REGISTER_READ(dev, 8416U); gma_wait_for_vblank(dev); } else { REGISTER_WRITE(dev, 458804U, 1065879560U); REGISTER_WRITE(dev, 458808U, 184680962U); REGISTER_WRITE(dev, 458812U, 603979776U); REGISTER_WRITE(dev, 458832U, 134414850U); REGISTER_WRITE(dev, 458836U, 16843009U); REGISTER_WRITE(dev, 458840U, 464U); gma_wait_for_vblank(dev); (*((dev_priv->ops)->disable_sr))(dev); } return; } } static int cdv_intel_panel_fitter_pipe(struct drm_device *dev ) { u32 pfit_control ; { pfit_control = REGISTER_READ(dev, 397872U); if ((int )pfit_control >= 0) { return (-1); } else { } return ((int )(pfit_control >> 29) & 3); } } static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode , int x , int y , struct drm_framebuffer *old_fb ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; struct psb_offset const *map ; int refclk ; struct gma_clock_t clock ; u32 dpll ; u32 dspcntr ; u32 pipeconf ; bool ok ; bool is_crt ; bool is_lvds ; bool is_tv ; bool is_hdmi ; bool is_dp ; struct drm_mode_config *mode_config ; struct drm_connector *connector ; struct gma_limit_t const *limit ; u32 ddi_select ; bool is_edp___0 ; struct list_head const *__mptr___0 ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct list_head const *__mptr___1 ; long tmp___0 ; uint32_t tmp___1 ; u32 lvds ; uint32_t tmp___2 ; int tmp___3 ; long tmp___4 ; uint32_t tmp___5 ; uint32_t tmp___6 ; int sdvo_pixel_multiply ; struct drm_crtc_helper_funcs const *crtc_funcs ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; dpll = 0U; is_crt = 0; is_lvds = 0; is_tv = 0; is_hdmi = 0; is_dp = 0; mode_config = & dev->mode_config; ddi_select = 0U; is_edp___0 = 0; __mptr___0 = (struct list_head const *)mode_config->connector_list.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; goto ldv_42050; ldv_42049: tmp = gma_attached_encoder(connector); gma_encoder = tmp; if ((unsigned long )connector->encoder == (unsigned long )((struct drm_encoder *)0) || (unsigned long )(connector->encoder)->crtc != (unsigned long )crtc) { goto ldv_42040; } else { } ddi_select = gma_encoder->ddi_select; switch (gma_encoder->type) { case 4: is_lvds = 1; goto ldv_42042; case 5: is_tv = 1; goto ldv_42042; case 1: is_crt = 1; goto ldv_42042; case 6: is_hdmi = 1; goto ldv_42042; case 9: is_dp = 1; goto ldv_42042; case 10: is_edp___0 = 1; goto ldv_42042; default: drm_err("invalid output type.\n"); return (0); } ldv_42042: ; ldv_42040: __mptr___1 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___1 + 0xffffffffffffffe8UL; ldv_42050: ; if ((unsigned long )(& connector->head) != (unsigned long )(& mode_config->connector_list)) { goto ldv_42049; } else { } if ((int )dev_priv->dplla_96mhz) { refclk = 96000; } else { refclk = 27000; } if ((int )is_dp || (int )is_edp___0) { if (pipe == 0) { refclk = 27000; } else { refclk = 100000; } } else { } if ((int )is_lvds && (unsigned int )*((unsigned char *)dev_priv + 864UL) != 0U) { refclk = dev_priv->lvds_ssc_freq * 1000; tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("cdv_intel_crtc_mode_set", "Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); } else { } } else { } drm_mode_debug_printmodeline((struct drm_display_mode const *)adjusted_mode); limit = (*((gma_crtc->clock_funcs)->limit))(crtc, refclk); ok = (*(limit->find_pll))(limit, crtc, adjusted_mode->clock, refclk, & clock); if (! ok) { drm_err("Couldn\'t find PLL settings for mode! target: %d, actual: %d", adjusted_mode->clock, clock.dot); return (0); } else { } dpll = 268435456U; if ((int )is_tv) { dpll = dpll | 3U; } else { } if ((int )is_dp || (int )is_edp___0) { cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode); } else { REGISTER_WRITE(dev, (uint32_t )(pipe * 4096 + 458832), 0U); REGISTER_WRITE(dev, (uint32_t )(pipe * 4096 + 458836), 0U); REGISTER_WRITE(dev, (uint32_t )(pipe * 4096 + 458848), 0U); REGISTER_WRITE(dev, (uint32_t )(pipe * 4096 + 458852), 0U); } dpll = dpll | 536870912U; pipeconf = REGISTER_READ(dev, map->conf); pipeconf = pipeconf & 4294967071U; if ((int )is_edp___0) { switch (dev_priv->edp.bpp) { case 24: pipeconf = pipeconf; goto ldv_42054; case 18: pipeconf = pipeconf | 64U; goto ldv_42054; case 30: pipeconf = pipeconf | 32U; goto ldv_42054; default: pipeconf = pipeconf; goto ldv_42054; } ldv_42054: ; } else if ((int )is_lvds) { tmp___1 = REGISTER_READ(dev, 397696U); if ((tmp___1 & 192U) == 192U) { pipeconf = pipeconf; } else { pipeconf = pipeconf | 64U; } } else { pipeconf = pipeconf; } dspcntr = 1073741824U; if (pipe == 0) { dspcntr = dspcntr; } else { dspcntr = dspcntr | 16777216U; } dspcntr = dspcntr | 2147483648U; pipeconf = pipeconf | 2147483648U; REGISTER_WRITE(dev, map->dpll, dpll | 805306368U); REGISTER_READ(dev, map->dpll); cdv_dpll_set_clock_cdv(dev, crtc, & clock, (int )is_lvds, ddi_select); __const_udelay(644250UL); if ((int )is_lvds) { tmp___2 = REGISTER_READ(dev, 397696U); lvds = tmp___2; lvds = lvds | 3221226240U; if (clock.p2 == 7) { lvds = lvds | 60U; } else { lvds = lvds & 4294967235U; } REGISTER_WRITE(dev, 397696U, lvds); REGISTER_READ(dev, 397696U); } else { } dpll = dpll | 2147483648U; tmp___3 = cdv_intel_panel_fitter_pipe(dev); if (tmp___3 == pipe) { REGISTER_WRITE(dev, 397872U, 0U); } else { } tmp___4 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("cdv_intel_crtc_mode_set", "Mode for pipe %c:\n", pipe == 0 ? 65 : 66); } else { } drm_mode_debug_printmodeline((struct drm_display_mode const *)mode); tmp___5 = REGISTER_READ(dev, map->dpll); REGISTER_WRITE(dev, map->dpll, (tmp___5 & 2147450879U) | 2147483648U); REGISTER_READ(dev, map->dpll); __const_udelay(644250UL); tmp___6 = REGISTER_READ(dev, map->dpll); if ((tmp___6 & 32768U) == 0U) { dev_err((struct device const *)dev->dev, "Failed to get DPLL lock\n"); return (-16); } else { } sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; REGISTER_WRITE(dev, map->dpll_md, (uint32_t )((sdvo_pixel_multiply + -1) << 8)); REGISTER_WRITE(dev, map->htotal, (uint32_t )((adjusted_mode->crtc_hdisplay + -1) | ((adjusted_mode->crtc_htotal + -1) << 16))); REGISTER_WRITE(dev, map->hblank, (uint32_t )((adjusted_mode->crtc_hblank_start + -1) | ((adjusted_mode->crtc_hblank_end + -1) << 16))); REGISTER_WRITE(dev, map->hsync, (uint32_t )((adjusted_mode->crtc_hsync_start + -1) | ((adjusted_mode->crtc_hsync_end + -1) << 16))); REGISTER_WRITE(dev, map->vtotal, (uint32_t )((adjusted_mode->crtc_vdisplay + -1) | ((adjusted_mode->crtc_vtotal + -1) << 16))); REGISTER_WRITE(dev, map->vblank, (uint32_t )((adjusted_mode->crtc_vblank_start + -1) | ((adjusted_mode->crtc_vblank_end + -1) << 16))); REGISTER_WRITE(dev, map->vsync, (uint32_t )((adjusted_mode->crtc_vsync_start + -1) | ((adjusted_mode->crtc_vsync_end + -1) << 16))); REGISTER_WRITE(dev, map->size, (uint32_t )(((mode->vdisplay + -1) << 16) | (mode->hdisplay + -1))); REGISTER_WRITE(dev, map->pos, 0U); REGISTER_WRITE(dev, map->src, (uint32_t )(((mode->hdisplay + -1) << 16) | (mode->vdisplay + -1))); REGISTER_WRITE(dev, map->conf, pipeconf); REGISTER_READ(dev, map->conf); gma_wait_for_vblank(dev); REGISTER_WRITE(dev, map->cntr, dspcntr); crtc_funcs = (struct drm_crtc_helper_funcs const *)crtc->helper_private; (*(crtc_funcs->mode_set_base))(crtc, x, y, old_fb); gma_wait_for_vblank(dev); return (0); } } static void i8xx_clock(int refclk , struct gma_clock_t *clock ) { { clock->m = (clock->m1 * 5 + 10) + (clock->m2 + 2); clock->p = clock->p1 * clock->p2; clock->vco = (clock->m * refclk) / (clock->n + 2); clock->dot = clock->vco / clock->p; return; } } static int cdv_intel_crtc_clock_get(struct drm_device *dev , struct drm_crtc *crtc ) { struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; struct psb_offset const *map ; u32 dpll ; u32 fp ; struct gma_clock_t clock ; bool is_lvds ; struct psb_pipe *p ; uint32_t tmp ; int tmp___0 ; bool tmp___1 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; p = (struct psb_pipe *)(& dev_priv->regs.pipe) + (unsigned long )pipe; tmp___1 = gma_power_begin(dev, 0); if ((int )tmp___1) { dpll = REGISTER_READ(dev, map->dpll); if ((dpll & 256U) == 0U) { fp = REGISTER_READ(dev, map->fp0); } else { fp = REGISTER_READ(dev, map->fp1); } if (pipe == 1) { tmp = REGISTER_READ(dev, 397696U); if ((int )tmp < 0) { tmp___0 = 1; } else { tmp___0 = 0; } } else { tmp___0 = 0; } is_lvds = (bool )tmp___0; gma_power_end(dev); } else { dpll = p->dpll; if ((dpll & 256U) == 0U) { fp = p->fp0; } else { fp = p->fp1; } is_lvds = (bool )(pipe == 1 && (int )dev_priv->regs.__annonCompField80.psb.saveLVDS < 0); } clock.m1 = (int )((fp & 16128U) >> 8); clock.m2 = (int )fp & 63; clock.n = (int )((fp & 4128768U) >> 16); if ((int )is_lvds) { clock.p1 = ffs((int )((dpll & 4128768U) >> 16)); if (clock.p1 == 0) { clock.p1 = 4; dev_err((struct device const *)dev->dev, "PLL %d\n", dpll); } else { } clock.p2 = 14; if ((dpll & 24576U) == 24576U) { i8xx_clock(66000, & clock); } else { i8xx_clock(48000, & clock); } } else { if ((dpll & 2097152U) != 0U) { clock.p1 = 2; } else { clock.p1 = (int )(((dpll & 2031616U) >> 16) + 2U); } if ((dpll & 8388608U) != 0U) { clock.p2 = 4; } else { clock.p2 = 2; } i8xx_clock(48000, & clock); } return (clock.dot); } } struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev , struct drm_crtc *crtc ) { struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; struct drm_psb_private *dev_priv ; struct psb_pipe *p ; struct psb_offset const *map ; struct drm_display_mode *mode ; int htot ; int hsync ; int vtot ; int vsync ; uint32_t tmp ; uint32_t tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; bool tmp___3 ; void *tmp___4 ; { __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; dev_priv = (struct drm_psb_private *)dev->dev_private; p = (struct psb_pipe *)(& dev_priv->regs.pipe) + (unsigned long )pipe; map = dev_priv->regmap + (unsigned long )pipe; tmp___3 = gma_power_begin(dev, 0); if ((int )tmp___3) { tmp = REGISTER_READ(dev, map->htotal); htot = (int )tmp; tmp___0 = REGISTER_READ(dev, map->hsync); hsync = (int )tmp___0; tmp___1 = REGISTER_READ(dev, map->vtotal); vtot = (int )tmp___1; tmp___2 = REGISTER_READ(dev, map->vsync); vsync = (int )tmp___2; gma_power_end(dev); } else { htot = (int )p->htotal; hsync = (int )p->hsync; vtot = (int )p->vtotal; vsync = (int )p->vsync; } tmp___4 = kzalloc(208UL, 208U); mode = (struct drm_display_mode *)tmp___4; if ((unsigned long )mode == (unsigned long )((struct drm_display_mode *)0)) { return ((struct drm_display_mode *)0); } else { } mode->clock = cdv_intel_crtc_clock_get(dev, crtc); mode->hdisplay = (htot & 65535) + 1; mode->htotal = (int )(((unsigned int )htot >> 16) + 1U); mode->hsync_start = (hsync & 65535) + 1; mode->hsync_end = (int )(((unsigned int )hsync >> 16) + 1U); mode->vdisplay = (vtot & 65535) + 1; mode->vtotal = (int )(((unsigned int )vtot >> 16) + 1U); mode->vsync_start = (vsync & 65535) + 1; mode->vsync_end = (int )(((unsigned int )vsync >> 16) + 1U); drm_mode_set_name(mode); drm_mode_set_crtcinfo(mode, 0); return (mode); } } struct drm_crtc_helper_funcs const cdv_intel_helper_funcs = {& gma_crtc_dpms, & gma_crtc_prepare, & gma_crtc_commit, & gma_crtc_mode_fixup, & cdv_intel_crtc_mode_set, 0, & gma_pipe_set_base, 0, 0, & gma_crtc_disable, 0, 0, 0, 0}; struct drm_crtc_funcs const cdv_intel_crtc_funcs = {& gma_crtc_save, & gma_crtc_restore, 0, & gma_crtc_cursor_set, 0, & gma_crtc_cursor_move, & gma_crtc_gamma_set, & gma_crtc_destroy, & gma_crtc_set_config, 0, 0, 0, 0, 0, 0}; struct gma_clock_funcs const cdv_clock_funcs = {& cdv_intel_clock, & cdv_intel_limit, & gma_pll_is_valid}; extern int ldv_connect_28(void) ; extern int ldv_bind_28(void) ; extern int ldv_probe_27(void) ; extern int ldv_release_28(void) ; void ldv_initialize_drm_crtc_funcs_27(void) { void *tmp ; { tmp = ldv_init_zalloc(1160UL); cdv_intel_crtc_funcs_group0 = (struct drm_crtc *)tmp; return; } } void ldv_initialize_gma_clock_funcs_26(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(1160UL); cdv_clock_funcs_group0 = (struct drm_crtc *)tmp; tmp___0 = ldv_init_zalloc(36UL); cdv_clock_funcs_group1 = (struct gma_clock_t *)tmp___0; return; } } void ldv_initialize_drm_crtc_helper_funcs_28(void) { void *tmp ; void *tmp___0 ; void *tmp___1 ; { tmp = ldv_init_zalloc(1160UL); cdv_intel_helper_funcs_group0 = (struct drm_crtc *)tmp; tmp___0 = ldv_init_zalloc(168UL); cdv_intel_helper_funcs_group1 = (struct drm_framebuffer *)tmp___0; tmp___1 = ldv_init_zalloc(208UL); cdv_intel_helper_funcs_group2 = (struct drm_display_mode *)tmp___1; return; } } void ldv_main_exported_27(void) { uint32_t ldvarg47 ; uint32_t ldvarg44 ; u16 *ldvarg40 ; void *tmp ; int ldvarg48 ; struct drm_file *ldvarg46 ; void *tmp___0 ; int ldvarg49 ; struct drm_mode_set *ldvarg38 ; void *tmp___1 ; u16 *ldvarg42 ; void *tmp___2 ; uint32_t ldvarg43 ; u16 *ldvarg41 ; void *tmp___3 ; uint32_t ldvarg39 ; uint32_t ldvarg45 ; int tmp___4 ; { tmp = ldv_init_zalloc(2UL); ldvarg40 = (u16 *)tmp; tmp___0 = ldv_init_zalloc(744UL); ldvarg46 = (struct drm_file *)tmp___0; tmp___1 = ldv_init_zalloc(48UL); ldvarg38 = (struct drm_mode_set *)tmp___1; tmp___2 = ldv_init_zalloc(2UL); ldvarg42 = (u16 *)tmp___2; tmp___3 = ldv_init_zalloc(2UL); ldvarg41 = (u16 *)tmp___3; ldv_memset((void *)(& ldvarg47), 0, 4UL); ldv_memset((void *)(& ldvarg44), 0, 4UL); ldv_memset((void *)(& ldvarg48), 0, 4UL); ldv_memset((void *)(& ldvarg49), 0, 4UL); ldv_memset((void *)(& ldvarg43), 0, 4UL); ldv_memset((void *)(& ldvarg39), 0, 4UL); ldv_memset((void *)(& ldvarg45), 0, 4UL); tmp___4 = __VERIFIER_nondet_int(); switch (tmp___4) { case 0: ; if (ldv_state_variable_27 == 1) { gma_crtc_cursor_move(cdv_intel_crtc_funcs_group0, ldvarg49, ldvarg48); ldv_state_variable_27 = 1; } else { } if (ldv_state_variable_27 == 2) { gma_crtc_cursor_move(cdv_intel_crtc_funcs_group0, ldvarg49, ldvarg48); ldv_state_variable_27 = 2; } else { } goto ldv_42132; case 1: ; if (ldv_state_variable_27 == 1) { gma_crtc_cursor_set(cdv_intel_crtc_funcs_group0, ldvarg46, ldvarg45, ldvarg44, ldvarg47); ldv_state_variable_27 = 1; } else { } if (ldv_state_variable_27 == 2) { gma_crtc_cursor_set(cdv_intel_crtc_funcs_group0, ldvarg46, ldvarg45, ldvarg44, ldvarg47); ldv_state_variable_27 = 2; } else { } goto ldv_42132; case 2: ; if (ldv_state_variable_27 == 2) { gma_crtc_destroy(cdv_intel_crtc_funcs_group0); ldv_state_variable_27 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42132; case 3: ; if (ldv_state_variable_27 == 1) { gma_crtc_save(cdv_intel_crtc_funcs_group0); ldv_state_variable_27 = 1; } else { } if (ldv_state_variable_27 == 2) { gma_crtc_save(cdv_intel_crtc_funcs_group0); ldv_state_variable_27 = 2; } else { } goto ldv_42132; case 4: ; if (ldv_state_variable_27 == 1) { gma_crtc_gamma_set(cdv_intel_crtc_funcs_group0, ldvarg42, ldvarg41, ldvarg40, ldvarg43, ldvarg39); ldv_state_variable_27 = 1; } else { } if (ldv_state_variable_27 == 2) { gma_crtc_gamma_set(cdv_intel_crtc_funcs_group0, ldvarg42, ldvarg41, ldvarg40, ldvarg43, ldvarg39); ldv_state_variable_27 = 2; } else { } goto ldv_42132; case 5: ; if (ldv_state_variable_27 == 1) { gma_crtc_restore(cdv_intel_crtc_funcs_group0); ldv_state_variable_27 = 1; } else { } if (ldv_state_variable_27 == 2) { gma_crtc_restore(cdv_intel_crtc_funcs_group0); ldv_state_variable_27 = 2; } else { } goto ldv_42132; case 6: ; if (ldv_state_variable_27 == 1) { gma_crtc_set_config(ldvarg38); ldv_state_variable_27 = 1; } else { } if (ldv_state_variable_27 == 2) { gma_crtc_set_config(ldvarg38); ldv_state_variable_27 = 2; } else { } goto ldv_42132; case 7: ; if (ldv_state_variable_27 == 1) { ldv_probe_27(); ldv_state_variable_27 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42132; default: ldv_stop(); } ldv_42132: ; return; } } void ldv_main_exported_28(void) { struct drm_display_mode *ldvarg56 ; void *tmp ; int ldvarg59 ; int ldvarg55 ; int ldvarg53 ; struct drm_display_mode *ldvarg54 ; void *tmp___0 ; int ldvarg58 ; int ldvarg57 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg56 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg54 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg59), 0, 4UL); ldv_memset((void *)(& ldvarg55), 0, 4UL); ldv_memset((void *)(& ldvarg53), 0, 4UL); ldv_memset((void *)(& ldvarg58), 0, 4UL); ldv_memset((void *)(& ldvarg57), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_28 == 1) { gma_pipe_set_base(cdv_intel_helper_funcs_group0, ldvarg59, ldvarg58, cdv_intel_helper_funcs_group1); ldv_state_variable_28 = 1; } else { } if (ldv_state_variable_28 == 3) { gma_pipe_set_base(cdv_intel_helper_funcs_group0, ldvarg59, ldvarg58, cdv_intel_helper_funcs_group1); ldv_state_variable_28 = 3; } else { } if (ldv_state_variable_28 == 2) { gma_pipe_set_base(cdv_intel_helper_funcs_group0, ldvarg59, ldvarg58, cdv_intel_helper_funcs_group1); ldv_state_variable_28 = 2; } else { } goto ldv_42152; case 1: ; if (ldv_state_variable_28 == 1) { gma_crtc_dpms(cdv_intel_helper_funcs_group0, ldvarg57); ldv_state_variable_28 = 1; } else { } if (ldv_state_variable_28 == 3) { gma_crtc_dpms(cdv_intel_helper_funcs_group0, ldvarg57); ldv_state_variable_28 = 3; } else { } if (ldv_state_variable_28 == 2) { gma_crtc_dpms(cdv_intel_helper_funcs_group0, ldvarg57); ldv_state_variable_28 = 2; } else { } goto ldv_42152; case 2: ; if (ldv_state_variable_28 == 1) { gma_crtc_mode_fixup(cdv_intel_helper_funcs_group0, (struct drm_display_mode const *)ldvarg56, cdv_intel_helper_funcs_group2); ldv_state_variable_28 = 1; } else { } if (ldv_state_variable_28 == 3) { gma_crtc_mode_fixup(cdv_intel_helper_funcs_group0, (struct drm_display_mode const *)ldvarg56, cdv_intel_helper_funcs_group2); ldv_state_variable_28 = 3; } else { } if (ldv_state_variable_28 == 2) { gma_crtc_mode_fixup(cdv_intel_helper_funcs_group0, (struct drm_display_mode const *)ldvarg56, cdv_intel_helper_funcs_group2); ldv_state_variable_28 = 2; } else { } goto ldv_42152; case 3: ; if (ldv_state_variable_28 == 1) { gma_crtc_commit(cdv_intel_helper_funcs_group0); ldv_state_variable_28 = 1; } else { } if (ldv_state_variable_28 == 3) { gma_crtc_commit(cdv_intel_helper_funcs_group0); ldv_state_variable_28 = 3; } else { } if (ldv_state_variable_28 == 2) { gma_crtc_commit(cdv_intel_helper_funcs_group0); ldv_state_variable_28 = 2; } else { } goto ldv_42152; case 4: ; if (ldv_state_variable_28 == 1) { cdv_intel_crtc_mode_set(cdv_intel_helper_funcs_group0, cdv_intel_helper_funcs_group2, ldvarg54, ldvarg53, ldvarg55, cdv_intel_helper_funcs_group1); ldv_state_variable_28 = 1; } else { } if (ldv_state_variable_28 == 3) { cdv_intel_crtc_mode_set(cdv_intel_helper_funcs_group0, cdv_intel_helper_funcs_group2, ldvarg54, ldvarg53, ldvarg55, cdv_intel_helper_funcs_group1); ldv_state_variable_28 = 3; } else { } if (ldv_state_variable_28 == 2) { cdv_intel_crtc_mode_set(cdv_intel_helper_funcs_group0, cdv_intel_helper_funcs_group2, ldvarg54, ldvarg53, ldvarg55, cdv_intel_helper_funcs_group1); ldv_state_variable_28 = 2; } else { } goto ldv_42152; case 5: ; if (ldv_state_variable_28 == 3) { gma_crtc_disable(cdv_intel_helper_funcs_group0); ldv_state_variable_28 = 2; } else { } goto ldv_42152; case 6: ; if (ldv_state_variable_28 == 1) { gma_crtc_prepare(cdv_intel_helper_funcs_group0); ldv_state_variable_28 = 1; } else { } if (ldv_state_variable_28 == 3) { gma_crtc_prepare(cdv_intel_helper_funcs_group0); ldv_state_variable_28 = 3; } else { } if (ldv_state_variable_28 == 2) { gma_crtc_prepare(cdv_intel_helper_funcs_group0); ldv_state_variable_28 = 2; } else { } goto ldv_42152; case 7: ; if (ldv_state_variable_28 == 2) { ldv_release_28(); ldv_state_variable_28 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42152; case 8: ; if (ldv_state_variable_28 == 1) { ldv_bind_28(); ldv_state_variable_28 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42152; case 9: ; if (ldv_state_variable_28 == 2) { ldv_connect_28(); ldv_state_variable_28 = 3; } else { } goto ldv_42152; default: ldv_stop(); } ldv_42152: ; return; } } void ldv_main_exported_26(void) { struct gma_limit_t *ldvarg12 ; void *tmp ; int ldvarg10 ; int ldvarg11 ; int tmp___0 ; { tmp = ldv_init_zalloc(88UL); ldvarg12 = (struct gma_limit_t *)tmp; ldv_memset((void *)(& ldvarg10), 0, 4UL); ldv_memset((void *)(& ldvarg11), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_26 == 1) { gma_pll_is_valid(cdv_clock_funcs_group0, (struct gma_limit_t const *)ldvarg12, cdv_clock_funcs_group1); ldv_state_variable_26 = 1; } else { } goto ldv_42170; case 1: ; if (ldv_state_variable_26 == 1) { cdv_intel_clock(ldvarg11, cdv_clock_funcs_group1); ldv_state_variable_26 = 1; } else { } goto ldv_42170; case 2: ; if (ldv_state_variable_26 == 1) { cdv_intel_limit(cdv_clock_funcs_group0, ldvarg10); ldv_state_variable_26 = 1; } else { } goto ldv_42170; default: ldv_stop(); } ldv_42170: ; return; } } bool ldv_queue_work_on_359(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_360(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_361(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_362(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_363(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_373(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_375(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_374(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_377(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_376(struct workqueue_struct *ldv_func_arg1 ) ; static void cdv_hdmi_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct gma_encoder *gma_encoder ; struct drm_encoder const *__mptr ; struct mid_intel_hdmi_priv *hdmi_priv ; u32 hdmib ; struct drm_crtc *crtc ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr___0 ; { dev = encoder->dev; __mptr = (struct drm_encoder const *)encoder; gma_encoder = (struct gma_encoder *)__mptr; hdmi_priv = (struct mid_intel_hdmi_priv *)gma_encoder->dev_priv; crtc = encoder->crtc; __mptr___0 = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr___0; hdmib = 2048U; if ((adjusted_mode->flags & 4U) != 0U) { hdmib = hdmib | 16U; } else { } if ((int )adjusted_mode->flags & 1) { hdmib = hdmib | 8U; } else { } if (gma_crtc->pipe == 1) { hdmib = hdmib | 1073741824U; } else { } if ((int )hdmi_priv->has_hdmi_audio) { hdmib = hdmib | 64U; hdmib = hdmib | 512U; } else { } REGISTER_WRITE(dev, hdmi_priv->hdmi_reg, hdmib); REGISTER_READ(dev, hdmi_priv->hdmi_reg); return; } } static void cdv_hdmi_dpms(struct drm_encoder *encoder , int mode ) { struct drm_device *dev ; struct gma_encoder *gma_encoder ; struct drm_encoder const *__mptr ; struct mid_intel_hdmi_priv *hdmi_priv ; u32 hdmib ; { dev = encoder->dev; __mptr = (struct drm_encoder const *)encoder; gma_encoder = (struct gma_encoder *)__mptr; hdmi_priv = (struct mid_intel_hdmi_priv *)gma_encoder->dev_priv; hdmib = REGISTER_READ(dev, hdmi_priv->hdmi_reg); if (mode != 0) { REGISTER_WRITE(dev, hdmi_priv->hdmi_reg, hdmib & 2147483647U); } else { REGISTER_WRITE(dev, hdmi_priv->hdmi_reg, hdmib | 2147483648U); } REGISTER_READ(dev, hdmi_priv->hdmi_reg); return; } } static void cdv_hdmi_save(struct drm_connector *connector ) { struct drm_device *dev ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct mid_intel_hdmi_priv *hdmi_priv ; { dev = connector->dev; tmp = gma_attached_encoder(connector); gma_encoder = tmp; hdmi_priv = (struct mid_intel_hdmi_priv *)gma_encoder->dev_priv; hdmi_priv->save_HDMIB = REGISTER_READ(dev, hdmi_priv->hdmi_reg); return; } } static void cdv_hdmi_restore(struct drm_connector *connector ) { struct drm_device *dev ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct mid_intel_hdmi_priv *hdmi_priv ; { dev = connector->dev; tmp = gma_attached_encoder(connector); gma_encoder = tmp; hdmi_priv = (struct mid_intel_hdmi_priv *)gma_encoder->dev_priv; REGISTER_WRITE(dev, hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB); REGISTER_READ(dev, hdmi_priv->hdmi_reg); return; } } static enum drm_connector_status cdv_hdmi_detect(struct drm_connector *connector , bool force ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct mid_intel_hdmi_priv *hdmi_priv ; struct edid *edid ; enum drm_connector_status status ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; hdmi_priv = (struct mid_intel_hdmi_priv *)gma_encoder->dev_priv; edid = (struct edid *)0; status = 2; edid = drm_get_edid(connector, & (gma_encoder->i2c_bus)->adapter); hdmi_priv->has_hdmi_sink = 0; hdmi_priv->has_hdmi_audio = 0; if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { if ((int )((signed char )edid->input) < 0) { status = 1; hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid); hdmi_priv->has_hdmi_audio = drm_detect_monitor_audio(edid); } else { } kfree((void const *)edid); } else { } return (status); } } static int cdv_hdmi_set_property(struct drm_connector *connector , struct drm_property *property , uint64_t value ) { struct drm_encoder *encoder ; struct gma_crtc *crtc ; struct drm_crtc const *__mptr ; bool centre ; uint64_t curValue ; int tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; struct drm_encoder_helper_funcs const *helpers ; int tmp___3 ; { encoder = connector->encoder; tmp___3 = strcmp((char const *)(& property->name), "scaling mode"); if (tmp___3 == 0 && (unsigned long )encoder != (unsigned long )((struct drm_encoder *)0)) { __mptr = (struct drm_crtc const *)encoder->crtc; crtc = (struct gma_crtc *)__mptr; if ((unsigned long )crtc == (unsigned long )((struct gma_crtc *)0)) { return (-1); } else { } switch (value) { case 1ULL: ; goto ldv_41789; case 2ULL: ; goto ldv_41789; case 3ULL: ; goto ldv_41789; default: ; return (-1); } ldv_41789: tmp = drm_object_property_get_value(& connector->base, property, & curValue); if (tmp != 0) { return (-1); } else { } if (curValue == value) { return (0); } else { } tmp___0 = drm_object_property_set_value(& connector->base, property, value); if (tmp___0 != 0) { return (-1); } else { } centre = (bool )(curValue == 2ULL || value == 2ULL); if (crtc->saved_mode.hdisplay != 0 && crtc->saved_mode.vdisplay != 0) { if ((int )centre) { tmp___1 = drm_crtc_helper_set_mode(encoder->crtc, & crtc->saved_mode, (encoder->crtc)->x, (encoder->crtc)->y, ((encoder->crtc)->primary)->fb); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (-1); } else { } } else { helpers = (struct drm_encoder_helper_funcs const *)encoder->helper_private; (*(helpers->mode_set))(encoder, & crtc->saved_mode, & crtc->saved_adjusted_mode); } } else { } } else { } return (0); } } static int cdv_hdmi_get_modes(struct drm_connector *connector ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct edid *edid ; int ret ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; edid = (struct edid *)0; ret = 0; edid = drm_get_edid(connector, & (gma_encoder->i2c_bus)->adapter); if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { drm_mode_connector_update_edid_property(connector, (struct edid const *)edid); ret = drm_add_edid_modes(connector, edid); kfree((void const *)edid); } else { } return (ret); } } static int cdv_hdmi_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) { { if (mode->clock > 165000) { return (15); } else { } if (mode->clock <= 19999) { return (15); } else { } if ((mode->flags & 32U) != 0U) { return (8); } else { } if ((mode->flags & 16U) != 0U) { return (7); } else { } return (0); } } static void cdv_hdmi_destroy(struct drm_connector *connector ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; if ((unsigned long )gma_encoder->i2c_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { psb_intel_i2c_destroy(gma_encoder->i2c_bus); } else { } drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree((void const *)connector); return; } } static struct drm_encoder_helper_funcs const cdv_hdmi_helper_funcs = {& cdv_hdmi_dpms, 0, 0, & gma_encoder_mode_fixup, & gma_encoder_prepare, & gma_encoder_commit, & cdv_hdmi_mode_set, 0, 0, 0, 0, 0}; static struct drm_connector_helper_funcs const cdv_hdmi_connector_helper_funcs = {& cdv_hdmi_get_modes, (enum drm_mode_status (*)(struct drm_connector * , struct drm_display_mode * ))(& cdv_hdmi_mode_valid), & gma_best_encoder}; static struct drm_connector_funcs const cdv_hdmi_connector_funcs = {& drm_helper_connector_dpms, & cdv_hdmi_save, & cdv_hdmi_restore, 0, & cdv_hdmi_detect, & drm_helper_probe_single_connector_modes, & cdv_hdmi_set_property, & cdv_hdmi_destroy, 0, 0, 0, 0, 0}; void cdv_hdmi_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev , int reg ) { struct gma_encoder *gma_encoder ; struct gma_connector *gma_connector ; struct drm_connector *connector ; struct drm_encoder *encoder ; struct mid_intel_hdmi_priv *hdmi_priv ; int ddc_bus ; void *tmp ; void *tmp___0 ; void *tmp___1 ; { tmp = kzalloc(152UL, 208U); gma_encoder = (struct gma_encoder *)tmp; if ((unsigned long )gma_encoder == (unsigned long )((struct gma_encoder *)0)) { return; } else { } tmp___0 = kzalloc(944UL, 208U); gma_connector = (struct gma_connector *)tmp___0; if ((unsigned long )gma_connector == (unsigned long )((struct gma_connector *)0)) { goto err_connector; } else { } tmp___1 = kzalloc(40UL, 208U); hdmi_priv = (struct mid_intel_hdmi_priv *)tmp___1; if ((unsigned long )hdmi_priv == (unsigned long )((struct mid_intel_hdmi_priv *)0)) { goto err_priv; } else { } connector = & gma_connector->base; connector->polled = 1U; encoder = & gma_encoder->base; drm_connector_init(dev, connector, & cdv_hdmi_connector_funcs, 3); drm_encoder_init(dev, encoder, & psb_intel_lvds_enc_funcs, 2); gma_connector_attach_encoder(gma_connector, gma_encoder); gma_encoder->type = 6; hdmi_priv->hdmi_reg = (u32 )reg; hdmi_priv->has_hdmi_sink = 0; gma_encoder->dev_priv = (void *)hdmi_priv; drm_encoder_helper_add(encoder, & cdv_hdmi_helper_funcs); drm_connector_helper_add(connector, & cdv_hdmi_connector_helper_funcs); connector->display_info.subpixel_order = 1; connector->interlace_allowed = 0; connector->doublescan_allowed = 0; drm_object_attach_property(& connector->base, dev->mode_config.scaling_mode_property, 1ULL); switch (reg) { case 397632: ddc_bus = 20512; gma_encoder->ddi_select = 1U; goto ldv_41825; case 397664: ddc_bus = 20508; gma_encoder->ddi_select = 2U; goto ldv_41825; default: drm_err("unknown reg 0x%x for HDMI\n", reg); goto failed_ddc; } ldv_41825: gma_encoder->i2c_bus = psb_intel_i2c_create(dev, (u32 const )ddc_bus, reg == 397632 ? "HDMIB" : "HDMIC"); if ((unsigned long )gma_encoder->i2c_bus == (unsigned long )((struct psb_intel_i2c_chan *)0)) { dev_err((struct device const *)dev->dev, "No ddc adapter available!\n"); goto failed_ddc; } else { } hdmi_priv->hdmi_i2c_adapter = & (gma_encoder->i2c_bus)->adapter; hdmi_priv->dev = dev; drm_connector_register(connector); return; failed_ddc: drm_encoder_cleanup(encoder); drm_connector_cleanup(connector); err_priv: kfree((void const *)gma_connector); err_connector: kfree((void const *)gma_encoder); return; } } extern int ldv_probe_23(void) ; void ldv_initialize_drm_connector_helper_funcs_24(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); cdv_hdmi_connector_helper_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_initialize_drm_encoder_helper_funcs_25(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(96UL); cdv_hdmi_helper_funcs_group0 = (struct drm_encoder *)tmp; tmp___0 = ldv_init_zalloc(208UL); cdv_hdmi_helper_funcs_group1 = (struct drm_display_mode *)tmp___0; return; } } void ldv_initialize_drm_connector_funcs_23(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); cdv_hdmi_connector_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_main_exported_25(void) { struct drm_display_mode *ldvarg50 ; void *tmp ; int ldvarg52 ; struct drm_display_mode *ldvarg51 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg50 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg51 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg52), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_25 == 1) { cdv_hdmi_dpms(cdv_hdmi_helper_funcs_group0, ldvarg52); ldv_state_variable_25 = 1; } else { } goto ldv_41847; case 1: ; if (ldv_state_variable_25 == 1) { gma_encoder_mode_fixup(cdv_hdmi_helper_funcs_group0, (struct drm_display_mode const *)ldvarg51, cdv_hdmi_helper_funcs_group1); ldv_state_variable_25 = 1; } else { } goto ldv_41847; case 2: ; if (ldv_state_variable_25 == 1) { gma_encoder_commit(cdv_hdmi_helper_funcs_group0); ldv_state_variable_25 = 1; } else { } goto ldv_41847; case 3: ; if (ldv_state_variable_25 == 1) { cdv_hdmi_mode_set(cdv_hdmi_helper_funcs_group0, cdv_hdmi_helper_funcs_group1, ldvarg50); ldv_state_variable_25 = 1; } else { } goto ldv_41847; case 4: ; if (ldv_state_variable_25 == 1) { gma_encoder_prepare(cdv_hdmi_helper_funcs_group0); ldv_state_variable_25 = 1; } else { } goto ldv_41847; default: ldv_stop(); } ldv_41847: ; return; } } void ldv_main_exported_24(void) { struct drm_display_mode *ldvarg95 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(208UL); ldvarg95 = (struct drm_display_mode *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_24 == 1) { cdv_hdmi_get_modes(cdv_hdmi_connector_helper_funcs_group0); ldv_state_variable_24 = 1; } else { } goto ldv_41858; case 1: ; if (ldv_state_variable_24 == 1) { cdv_hdmi_mode_valid(cdv_hdmi_connector_helper_funcs_group0, ldvarg95); ldv_state_variable_24 = 1; } else { } goto ldv_41858; case 2: ; if (ldv_state_variable_24 == 1) { gma_best_encoder(cdv_hdmi_connector_helper_funcs_group0); ldv_state_variable_24 = 1; } else { } goto ldv_41858; default: ldv_stop(); } ldv_41858: ; return; } } void ldv_main_exported_23(void) { uint32_t ldvarg132 ; uint32_t ldvarg133 ; struct drm_property *ldvarg135 ; void *tmp ; uint64_t ldvarg134 ; int ldvarg137 ; bool ldvarg136 ; int tmp___0 ; { tmp = ldv_init_zalloc(104UL); ldvarg135 = (struct drm_property *)tmp; ldv_memset((void *)(& ldvarg132), 0, 4UL); ldv_memset((void *)(& ldvarg133), 0, 4UL); ldv_memset((void *)(& ldvarg134), 0, 8UL); ldv_memset((void *)(& ldvarg137), 0, 4UL); ldv_memset((void *)(& ldvarg136), 0, 1UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_23 == 1) { drm_helper_connector_dpms(cdv_hdmi_connector_funcs_group0, ldvarg137); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { drm_helper_connector_dpms(cdv_hdmi_connector_funcs_group0, ldvarg137); ldv_state_variable_23 = 2; } else { } goto ldv_41872; case 1: ; if (ldv_state_variable_23 == 1) { cdv_hdmi_detect(cdv_hdmi_connector_funcs_group0, (int )ldvarg136); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { cdv_hdmi_detect(cdv_hdmi_connector_funcs_group0, (int )ldvarg136); ldv_state_variable_23 = 2; } else { } goto ldv_41872; case 2: ; if (ldv_state_variable_23 == 1) { cdv_hdmi_set_property(cdv_hdmi_connector_funcs_group0, ldvarg135, ldvarg134); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { cdv_hdmi_set_property(cdv_hdmi_connector_funcs_group0, ldvarg135, ldvarg134); ldv_state_variable_23 = 2; } else { } goto ldv_41872; case 3: ; if (ldv_state_variable_23 == 2) { cdv_hdmi_destroy(cdv_hdmi_connector_funcs_group0); ldv_state_variable_23 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41872; case 4: ; if (ldv_state_variable_23 == 1) { cdv_hdmi_save(cdv_hdmi_connector_funcs_group0); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { cdv_hdmi_save(cdv_hdmi_connector_funcs_group0); ldv_state_variable_23 = 2; } else { } goto ldv_41872; case 5: ; if (ldv_state_variable_23 == 1) { cdv_hdmi_restore(cdv_hdmi_connector_funcs_group0); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { cdv_hdmi_restore(cdv_hdmi_connector_funcs_group0); ldv_state_variable_23 = 2; } else { } goto ldv_41872; case 6: ; if (ldv_state_variable_23 == 1) { drm_helper_probe_single_connector_modes(cdv_hdmi_connector_funcs_group0, ldvarg133, ldvarg132); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { drm_helper_probe_single_connector_modes(cdv_hdmi_connector_funcs_group0, ldvarg133, ldvarg132); ldv_state_variable_23 = 2; } else { } goto ldv_41872; case 7: ; if (ldv_state_variable_23 == 1) { ldv_probe_23(); ldv_state_variable_23 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41872; default: ldv_stop(); } ldv_41872: ; return; } } bool ldv_queue_work_on_373(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_374(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_375(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_376(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_377(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_387(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_389(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_388(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_391(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_390(struct workqueue_struct *ldv_func_arg1 ) ; static u32 cdv_intel_lvds_get_max_backlight(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 retval ; uint32_t tmp ; bool tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp___0 = gma_power_begin(dev, 0); if ((int )tmp___0) { tmp = REGISTER_READ(dev, 397908U); retval = (tmp >> 17) * 2U; gma_power_end(dev); } else { retval = (dev_priv->regs.saveBLC_PWM_CTL >> 17) * 2U; } return (retval); } } static void cdv_intel_lvds_set_backlight(struct drm_device *dev , int level ) { struct drm_psb_private *dev_priv ; u32 blc_pwm_ctl ; uint32_t tmp ; bool tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp___0 = gma_power_begin(dev, 0); if ((int )tmp___0) { tmp = REGISTER_READ(dev, 397908U); blc_pwm_ctl = tmp & 4294901760U; REGISTER_WRITE(dev, 397908U, blc_pwm_ctl | (u32 )level); gma_power_end(dev); } else { blc_pwm_ctl = dev_priv->regs.saveBLC_PWM_CTL & 4294901760U; dev_priv->regs.saveBLC_PWM_CTL = blc_pwm_ctl | (u32 )level; } return; } } static void cdv_intel_lvds_set_power(struct drm_device *dev , struct drm_encoder *encoder , bool on ) { struct drm_psb_private *dev_priv ; u32 pp_status ; bool tmp ; int tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return; } else { } if ((int )on) { tmp___1 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___1 | 1U); ldv_41706: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status >= 0) { goto ldv_41706; } else { } cdv_intel_lvds_set_backlight(dev, dev_priv->mode_dev.backlight_duty_cycle); } else { cdv_intel_lvds_set_backlight(dev, 0); tmp___2 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___2 & 4294967294U); ldv_41708: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status < 0) { goto ldv_41708; } else { } } gma_power_end(dev); return; } } static void cdv_intel_lvds_encoder_dpms(struct drm_encoder *encoder , int mode ) { struct drm_device *dev ; { dev = encoder->dev; if (mode == 0) { cdv_intel_lvds_set_power(dev, encoder, 1); } else { cdv_intel_lvds_set_power(dev, encoder, 0); } return; } } static void cdv_intel_lvds_save(struct drm_connector *connector ) { { return; } } static void cdv_intel_lvds_restore(struct drm_connector *connector ) { { return; } } static int cdv_intel_lvds_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct drm_display_mode *fixed_mode ; { dev = connector->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; fixed_mode = dev_priv->mode_dev.panel_fixed_mode; if ((mode->flags & 32U) != 0U) { return (8); } else { } if ((mode->flags & 16U) != 0U) { return (7); } else { } if ((unsigned long )fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { if (mode->hdisplay > fixed_mode->hdisplay) { return (29); } else { } if (mode->vdisplay > fixed_mode->vdisplay) { return (29); } else { } } else { } return (0); } } static bool cdv_intel_lvds_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; struct drm_encoder *tmp_encoder ; struct drm_display_mode *panel_fixed_mode ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; panel_fixed_mode = mode_dev->panel_fixed_mode; __mptr = (struct list_head const *)dev->mode_config.encoder_list.next; tmp_encoder = (struct drm_encoder *)__mptr + 0xfffffffffffffff8UL; goto ldv_41743; ldv_41742: ; if ((unsigned long )tmp_encoder != (unsigned long )encoder && (unsigned long )tmp_encoder->crtc == (unsigned long )encoder->crtc) { printk("\vCan\'t enable LVDS and another encoder on the same pipe\n"); return (0); } else { } __mptr___0 = (struct list_head const *)tmp_encoder->head.next; tmp_encoder = (struct drm_encoder *)__mptr___0 + 0xfffffffffffffff8UL; ldv_41743: ; if ((unsigned long )(& tmp_encoder->head) != (unsigned long )(& dev->mode_config.encoder_list)) { goto ldv_41742; } else { } if ((unsigned long )panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; adjusted_mode->hsync_start = panel_fixed_mode->hsync_start; adjusted_mode->hsync_end = panel_fixed_mode->hsync_end; adjusted_mode->htotal = panel_fixed_mode->htotal; adjusted_mode->vdisplay = panel_fixed_mode->vdisplay; adjusted_mode->vsync_start = panel_fixed_mode->vsync_start; adjusted_mode->vsync_end = panel_fixed_mode->vsync_end; adjusted_mode->vtotal = panel_fixed_mode->vtotal; adjusted_mode->clock = panel_fixed_mode->clock; drm_mode_set_crtcinfo(adjusted_mode, 1); } else { } return (1); } } static void cdv_intel_lvds_prepare(struct drm_encoder *encoder ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; bool tmp ; int tmp___0 ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return; } else { } mode_dev->saveBLC_PWM_CTL = REGISTER_READ(dev, 397908U); mode_dev->backlight_duty_cycle = (int )mode_dev->saveBLC_PWM_CTL & 65535; cdv_intel_lvds_set_power(dev, encoder, 0); gma_power_end(dev); return; } } static void cdv_intel_lvds_commit(struct drm_encoder *encoder ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; u32 tmp ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; if (mode_dev->backlight_duty_cycle == 0) { tmp = cdv_intel_lvds_get_max_backlight(dev); mode_dev->backlight_duty_cycle = (int )tmp; } else { } cdv_intel_lvds_set_power(dev, encoder, 1); return; } } static void cdv_intel_lvds_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; u32 pfit_control ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)encoder->crtc; gma_crtc = (struct gma_crtc *)__mptr; if (mode->hdisplay != adjusted_mode->hdisplay || mode->vdisplay != adjusted_mode->vdisplay) { pfit_control = 2147485280U; } else { pfit_control = 0U; } pfit_control = (u32 )(gma_crtc->pipe << 29) | pfit_control; if ((unsigned int )*((unsigned char *)dev_priv + 864UL) != 0U) { pfit_control = pfit_control | 8U; } else { } REGISTER_WRITE(dev, 397872U, pfit_control); return; } } static enum drm_connector_status cdv_intel_lvds_detect(struct drm_connector *connector , bool force ) { { return (1); } } static int cdv_intel_lvds_get_modes(struct drm_connector *connector ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct psb_intel_mode_device *mode_dev ; int ret ; struct drm_display_mode *mode ; struct drm_display_mode *tmp___0 ; { dev = connector->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = gma_attached_encoder(connector); gma_encoder = tmp; mode_dev = & dev_priv->mode_dev; ret = psb_intel_ddc_get_modes(connector, & (gma_encoder->i2c_bus)->adapter); if (ret != 0) { return (ret); } else { } connector->display_info.min_vfreq = 0U; connector->display_info.max_vfreq = 200U; connector->display_info.min_hfreq = 0U; connector->display_info.max_hfreq = 200U; if ((unsigned long )mode_dev->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { tmp___0 = drm_mode_duplicate(dev, (struct drm_display_mode const *)mode_dev->panel_fixed_mode); mode = tmp___0; drm_mode_probed_add(connector, mode); return (1); } else { } return (0); } } static void cdv_intel_lvds_destroy(struct drm_connector *connector ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; if ((unsigned long )gma_encoder->i2c_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { psb_intel_i2c_destroy(gma_encoder->i2c_bus); } else { } drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree((void const *)connector); return; } } static int cdv_intel_lvds_set_property(struct drm_connector *connector , struct drm_property *property , uint64_t value ) { struct drm_encoder *encoder ; struct gma_crtc *crtc ; struct drm_crtc const *__mptr ; uint64_t curValue ; int tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; int tmp___3 ; struct drm_encoder_helper_funcs const *helpers ; int tmp___4 ; int tmp___5 ; int tmp___6 ; { encoder = connector->encoder; tmp___6 = strcmp((char const *)(& property->name), "scaling mode"); if (tmp___6 == 0 && (unsigned long )encoder != (unsigned long )((struct drm_encoder *)0)) { __mptr = (struct drm_crtc const *)encoder->crtc; crtc = (struct gma_crtc *)__mptr; if ((unsigned long )crtc == (unsigned long )((struct gma_crtc *)0)) { return (-1); } else { } switch (value) { case 1ULL: ; goto ldv_41796; case 2ULL: ; goto ldv_41796; case 3ULL: ; goto ldv_41796; default: ; return (-1); } ldv_41796: tmp = drm_object_property_get_value(& connector->base, property, & curValue); if (tmp != 0) { return (-1); } else { } if (curValue == value) { return (0); } else { } tmp___0 = drm_object_property_set_value(& connector->base, property, value); if (tmp___0 != 0) { return (-1); } else { } if (crtc->saved_mode.hdisplay != 0 && crtc->saved_mode.vdisplay != 0) { tmp___1 = drm_crtc_helper_set_mode(encoder->crtc, & crtc->saved_mode, (encoder->crtc)->x, (encoder->crtc)->y, ((encoder->crtc)->primary)->fb); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (-1); } else { } } else { } } else { tmp___5 = strcmp((char const *)(& property->name), "backlight"); if (tmp___5 == 0 && (unsigned long )encoder != (unsigned long )((struct drm_encoder *)0)) { tmp___3 = drm_object_property_set_value(& connector->base, property, value); if (tmp___3 != 0) { return (-1); } else { gma_backlight_set(encoder->dev, (int )value); } } else { tmp___4 = strcmp((char const *)(& property->name), "DPMS"); if (tmp___4 == 0 && (unsigned long )encoder != (unsigned long )((struct drm_encoder *)0)) { helpers = (struct drm_encoder_helper_funcs const *)encoder->helper_private; (*(helpers->dpms))(encoder, (int )value); } else { } } } return (0); } } static struct drm_encoder_helper_funcs const cdv_intel_lvds_helper_funcs = {& cdv_intel_lvds_encoder_dpms, 0, 0, & cdv_intel_lvds_mode_fixup, & cdv_intel_lvds_prepare, & cdv_intel_lvds_commit, & cdv_intel_lvds_mode_set, 0, 0, 0, 0, 0}; static struct drm_connector_helper_funcs const cdv_intel_lvds_connector_helper_funcs = {& cdv_intel_lvds_get_modes, (enum drm_mode_status (*)(struct drm_connector * , struct drm_display_mode * ))(& cdv_intel_lvds_mode_valid), & gma_best_encoder}; static struct drm_connector_funcs const cdv_intel_lvds_connector_funcs = {& drm_helper_connector_dpms, & cdv_intel_lvds_save, & cdv_intel_lvds_restore, 0, & cdv_intel_lvds_detect, & drm_helper_probe_single_connector_modes, & cdv_intel_lvds_set_property, & cdv_intel_lvds_destroy, 0, 0, 0, 0, 0}; static void cdv_intel_lvds_enc_destroy(struct drm_encoder *encoder ) { { drm_encoder_cleanup(encoder); return; } } static struct drm_encoder_funcs const cdv_intel_lvds_enc_funcs = {0, & cdv_intel_lvds_enc_destroy}; static bool lvds_is_present_in_vbt(struct drm_device *dev , u8 *i2c_pin ) { struct drm_psb_private *dev_priv ; int i ; struct child_device_config *child ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if (dev_priv->child_dev_num == 0) { return (1); } else { } i = 0; goto ldv_41817; ldv_41816: child = dev_priv->child_dev + (unsigned long )i; if ((unsigned int )child->device_type != 4130U && (unsigned int )child->device_type != 34U) { goto ldv_41815; } else { } if ((unsigned int )child->i2c_pin != 0U) { *i2c_pin = child->i2c_pin; } else { } if ((unsigned int )child->addin_offset != 0U) { return (1); } else { } if ((unsigned long )dev_priv->opregion.vbt != (unsigned long )((void *)0)) { return (1); } else { } ldv_41815: i = i + 1; ldv_41817: ; if (dev_priv->child_dev_num > i) { goto ldv_41816; } else { } return (0); } } void cdv_intel_lvds_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) { struct gma_encoder *gma_encoder ; struct gma_connector *gma_connector ; struct cdv_intel_lvds_priv *lvds_priv ; struct drm_connector *connector ; struct drm_encoder *encoder ; struct drm_display_mode *scan ; struct drm_crtc *crtc ; struct drm_psb_private *dev_priv ; u32 lvds ; int pipe ; u8 pin ; long tmp ; bool tmp___0 ; int tmp___1 ; void *tmp___2 ; void *tmp___3 ; void *tmp___4 ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; long tmp___5 ; u32 pwm ; { dev_priv = (struct drm_psb_private *)dev->dev_private; pin = 3U; tmp___0 = lvds_is_present_in_vbt(dev, & pin); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_lvds_init", "LVDS is not present in VBT\n"); } else { } return; } else { } tmp___2 = kzalloc(152UL, 208U); gma_encoder = (struct gma_encoder *)tmp___2; if ((unsigned long )gma_encoder == (unsigned long )((struct gma_encoder *)0)) { return; } else { } tmp___3 = kzalloc(944UL, 208U); gma_connector = (struct gma_connector *)tmp___3; if ((unsigned long )gma_connector == (unsigned long )((struct gma_connector *)0)) { goto failed_connector; } else { } tmp___4 = kzalloc(32UL, 208U); lvds_priv = (struct cdv_intel_lvds_priv *)tmp___4; if ((unsigned long )lvds_priv == (unsigned long )((struct cdv_intel_lvds_priv *)0)) { goto failed_lvds_priv; } else { } gma_encoder->dev_priv = (void *)lvds_priv; connector = & gma_connector->base; encoder = & gma_encoder->base; drm_connector_init(dev, connector, & cdv_intel_lvds_connector_funcs, 7); drm_encoder_init(dev, encoder, & cdv_intel_lvds_enc_funcs, 3); gma_connector_attach_encoder(gma_connector, gma_encoder); gma_encoder->type = 4; drm_encoder_helper_add(encoder, & cdv_intel_lvds_helper_funcs); drm_connector_helper_add(connector, & cdv_intel_lvds_connector_helper_funcs); connector->display_info.subpixel_order = 1; connector->interlace_allowed = 0; connector->doublescan_allowed = 0; drm_object_attach_property(& connector->base, dev->mode_config.scaling_mode_property, 1ULL); drm_object_attach_property(& connector->base, dev_priv->backlight_property, 100ULL); gma_encoder->i2c_bus = psb_intel_i2c_create(dev, 20500U, "LVDSBLC_B"); if ((unsigned long )gma_encoder->i2c_bus == (unsigned long )((struct psb_intel_i2c_chan *)0)) { dev_printk("\v", (struct device const *)(& (dev->pdev)->dev), "I2C bus registration failed.\n"); goto failed_blc_i2c; } else { } (gma_encoder->i2c_bus)->slave_addr = 44U; dev_priv->lvds_i2c_bus = gma_encoder->i2c_bus; gma_encoder->ddc_bus = psb_intel_i2c_create(dev, 20504U, "LVDSDDC_C"); if ((unsigned long )gma_encoder->ddc_bus == (unsigned long )((struct psb_intel_i2c_chan *)0)) { dev_printk("\v", (struct device const *)(& (dev->pdev)->dev), "DDC bus registration failed.\n"); goto failed_ddc; } else { } mutex_lock_nested(& dev->mode_config.mutex, 0U); psb_intel_ddc_get_modes(connector, & (gma_encoder->ddc_bus)->adapter); __mptr = (struct list_head const *)connector->probed_modes.next; scan = (struct drm_display_mode *)__mptr; goto ldv_41845; ldv_41844: ; if ((scan->type & 8U) != 0U) { mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)scan); goto out; } else { } __mptr___0 = (struct list_head const *)scan->head.next; scan = (struct drm_display_mode *)__mptr___0; ldv_41845: ; if ((unsigned long )(& scan->head) != (unsigned long )(& connector->probed_modes)) { goto ldv_41844; } else { } if ((unsigned long )dev_priv->lfp_lvds_vbt_mode != (unsigned long )((struct drm_display_mode *)0)) { mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)dev_priv->lfp_lvds_vbt_mode); if ((unsigned long )mode_dev->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { (mode_dev->panel_fixed_mode)->type = (mode_dev->panel_fixed_mode)->type | 8U; goto out; } else { } } else { } lvds = REGISTER_READ(dev, 397696U); pipe = (lvds & 1073741824U) != 0U; crtc = psb_intel_get_crtc_from_pipe(dev, pipe); if ((unsigned long )crtc != (unsigned long )((struct drm_crtc *)0) && (int )lvds < 0) { mode_dev->panel_fixed_mode = cdv_intel_crtc_mode_get(dev, crtc); if ((unsigned long )mode_dev->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { (mode_dev->panel_fixed_mode)->type = (mode_dev->panel_fixed_mode)->type | 8U; goto out; } else { } } else { } if ((unsigned long )mode_dev->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { tmp___5 = ldv__builtin_expect((long )((int )drm_debug) & 1L, 0L); if (tmp___5 != 0L) { drm_ut_debug_printk("cdv_intel_lvds_init", "Found no modes on the lvds, ignoring the LVDS\n"); } else { } goto failed_find; } else { } pwm = REGISTER_READ(dev, 397904U); if (pipe == 1) { pwm = pwm | 536870912U; } else { pwm = pwm & 3758096383U; } pwm = pwm | 2147483648U; REGISTER_WRITE(dev, 397904U, pwm); out: mutex_unlock(& dev->mode_config.mutex); drm_connector_register(connector); return; failed_find: mutex_unlock(& dev->mode_config.mutex); printk("\vFailed find\n"); if ((unsigned long )gma_encoder->ddc_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { psb_intel_i2c_destroy(gma_encoder->ddc_bus); } else { } failed_ddc: printk("\vFailed DDC\n"); if ((unsigned long )gma_encoder->i2c_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { psb_intel_i2c_destroy(gma_encoder->i2c_bus); } else { } failed_blc_i2c: printk("\vFailed BLC\n"); drm_encoder_cleanup(encoder); drm_connector_cleanup(connector); kfree((void const *)lvds_priv); failed_lvds_priv: kfree((void const *)gma_connector); failed_connector: kfree((void const *)gma_encoder); return; } } extern int ldv_probe_19(void) ; extern int ldv_probe_20(void) ; void ldv_initialize_drm_encoder_helper_funcs_22(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(96UL); cdv_intel_lvds_helper_funcs_group0 = (struct drm_encoder *)tmp; tmp___0 = ldv_init_zalloc(208UL); cdv_intel_lvds_helper_funcs_group1 = (struct drm_display_mode *)tmp___0; return; } } void ldv_initialize_drm_connector_funcs_20(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); cdv_intel_lvds_connector_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_initialize_drm_connector_helper_funcs_21(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); cdv_intel_lvds_connector_helper_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_main_exported_22(void) { struct drm_display_mode *ldvarg118 ; void *tmp ; struct drm_display_mode *ldvarg117 ; void *tmp___0 ; int ldvarg119 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg118 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg117 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg119), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_22 == 1) { cdv_intel_lvds_encoder_dpms(cdv_intel_lvds_helper_funcs_group0, ldvarg119); ldv_state_variable_22 = 1; } else { } goto ldv_41869; case 1: ; if (ldv_state_variable_22 == 1) { cdv_intel_lvds_mode_fixup(cdv_intel_lvds_helper_funcs_group0, (struct drm_display_mode const *)ldvarg118, cdv_intel_lvds_helper_funcs_group1); ldv_state_variable_22 = 1; } else { } goto ldv_41869; case 2: ; if (ldv_state_variable_22 == 1) { cdv_intel_lvds_commit(cdv_intel_lvds_helper_funcs_group0); ldv_state_variable_22 = 1; } else { } goto ldv_41869; case 3: ; if (ldv_state_variable_22 == 1) { cdv_intel_lvds_mode_set(cdv_intel_lvds_helper_funcs_group0, cdv_intel_lvds_helper_funcs_group1, ldvarg117); ldv_state_variable_22 = 1; } else { } goto ldv_41869; case 4: ; if (ldv_state_variable_22 == 1) { cdv_intel_lvds_prepare(cdv_intel_lvds_helper_funcs_group0); ldv_state_variable_22 = 1; } else { } goto ldv_41869; default: ldv_stop(); } ldv_41869: ; return; } } void ldv_main_exported_21(void) { struct drm_display_mode *ldvarg5 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(208UL); ldvarg5 = (struct drm_display_mode *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_21 == 1) { cdv_intel_lvds_get_modes(cdv_intel_lvds_connector_helper_funcs_group0); ldv_state_variable_21 = 1; } else { } goto ldv_41880; case 1: ; if (ldv_state_variable_21 == 1) { cdv_intel_lvds_mode_valid(cdv_intel_lvds_connector_helper_funcs_group0, ldvarg5); ldv_state_variable_21 = 1; } else { } goto ldv_41880; case 2: ; if (ldv_state_variable_21 == 1) { gma_best_encoder(cdv_intel_lvds_connector_helper_funcs_group0); ldv_state_variable_21 = 1; } else { } goto ldv_41880; default: ldv_stop(); } ldv_41880: ; return; } } void ldv_main_exported_19(void) { struct drm_encoder *ldvarg213 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(96UL); ldvarg213 = (struct drm_encoder *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_19 == 2) { cdv_intel_lvds_enc_destroy(ldvarg213); ldv_state_variable_19 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41889; case 1: ; if (ldv_state_variable_19 == 1) { ldv_probe_19(); ldv_state_variable_19 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41889; default: ldv_stop(); } ldv_41889: ; return; } } void ldv_main_exported_20(void) { uint32_t ldvarg75 ; uint32_t ldvarg76 ; struct drm_property *ldvarg78 ; void *tmp ; int ldvarg80 ; bool ldvarg79 ; uint64_t ldvarg77 ; int tmp___0 ; { tmp = ldv_init_zalloc(104UL); ldvarg78 = (struct drm_property *)tmp; ldv_memset((void *)(& ldvarg75), 0, 4UL); ldv_memset((void *)(& ldvarg76), 0, 4UL); ldv_memset((void *)(& ldvarg80), 0, 4UL); ldv_memset((void *)(& ldvarg79), 0, 1UL); ldv_memset((void *)(& ldvarg77), 0, 8UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_20 == 1) { drm_helper_connector_dpms(cdv_intel_lvds_connector_funcs_group0, ldvarg80); ldv_state_variable_20 = 1; } else { } if (ldv_state_variable_20 == 2) { drm_helper_connector_dpms(cdv_intel_lvds_connector_funcs_group0, ldvarg80); ldv_state_variable_20 = 2; } else { } goto ldv_41902; case 1: ; if (ldv_state_variable_20 == 1) { cdv_intel_lvds_detect(cdv_intel_lvds_connector_funcs_group0, (int )ldvarg79); ldv_state_variable_20 = 1; } else { } if (ldv_state_variable_20 == 2) { cdv_intel_lvds_detect(cdv_intel_lvds_connector_funcs_group0, (int )ldvarg79); ldv_state_variable_20 = 2; } else { } goto ldv_41902; case 2: ; if (ldv_state_variable_20 == 1) { cdv_intel_lvds_set_property(cdv_intel_lvds_connector_funcs_group0, ldvarg78, ldvarg77); ldv_state_variable_20 = 1; } else { } if (ldv_state_variable_20 == 2) { cdv_intel_lvds_set_property(cdv_intel_lvds_connector_funcs_group0, ldvarg78, ldvarg77); ldv_state_variable_20 = 2; } else { } goto ldv_41902; case 3: ; if (ldv_state_variable_20 == 2) { cdv_intel_lvds_destroy(cdv_intel_lvds_connector_funcs_group0); ldv_state_variable_20 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41902; case 4: ; if (ldv_state_variable_20 == 1) { cdv_intel_lvds_save(cdv_intel_lvds_connector_funcs_group0); ldv_state_variable_20 = 1; } else { } if (ldv_state_variable_20 == 2) { cdv_intel_lvds_save(cdv_intel_lvds_connector_funcs_group0); ldv_state_variable_20 = 2; } else { } goto ldv_41902; case 5: ; if (ldv_state_variable_20 == 1) { cdv_intel_lvds_restore(cdv_intel_lvds_connector_funcs_group0); ldv_state_variable_20 = 1; } else { } if (ldv_state_variable_20 == 2) { cdv_intel_lvds_restore(cdv_intel_lvds_connector_funcs_group0); ldv_state_variable_20 = 2; } else { } goto ldv_41902; case 6: ; if (ldv_state_variable_20 == 1) { drm_helper_probe_single_connector_modes(cdv_intel_lvds_connector_funcs_group0, ldvarg76, ldvarg75); ldv_state_variable_20 = 1; } else { } if (ldv_state_variable_20 == 2) { drm_helper_probe_single_connector_modes(cdv_intel_lvds_connector_funcs_group0, ldvarg76, ldvarg75); ldv_state_variable_20 = 2; } else { } goto ldv_41902; case 7: ; if (ldv_state_variable_20 == 1) { ldv_probe_20(); ldv_state_variable_20 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41902; default: ldv_stop(); } ldv_41902: ; return; } } bool ldv_queue_work_on_387(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_388(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_389(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_390(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_391(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; extern char *strncpy(char * , char const * , __kernel_size_t ) ; bool ldv_queue_work_on_401(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_403(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_402(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_405(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_404(struct workqueue_struct *ldv_func_arg1 ) ; static int i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter , int mode , uint8_t write_byte , uint8_t *read_byte ) { struct i2c_algo_dp_aux_data *algo_data ; int ret ; { algo_data = (struct i2c_algo_dp_aux_data *)adapter->algo_data; ret = (*(algo_data->aux_ch))(adapter, mode, (int )write_byte, read_byte); return (ret); } } static int i2c_algo_dp_aux_address(struct i2c_adapter *adapter , u16 address , bool reading ) { struct i2c_algo_dp_aux_data *algo_data ; int mode ; int ret ; { algo_data = (struct i2c_algo_dp_aux_data *)adapter->algo_data; mode = 1; if ((int )reading) { mode = mode | 4; } else { mode = mode | 2; } algo_data->address = address; algo_data->running = 1; ret = i2c_algo_dp_aux_transaction(adapter, mode, 0, (uint8_t *)0U); return (ret); } } static void i2c_algo_dp_aux_stop(struct i2c_adapter *adapter , bool reading ) { struct i2c_algo_dp_aux_data *algo_data ; int mode ; { algo_data = (struct i2c_algo_dp_aux_data *)adapter->algo_data; mode = 8; if ((int )reading) { mode = mode | 4; } else { mode = mode | 2; } if ((int )algo_data->running) { i2c_algo_dp_aux_transaction(adapter, mode, 0, (uint8_t *)0U); algo_data->running = 0; } else { } return; } } static int i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter , u8 byte ) { struct i2c_algo_dp_aux_data *algo_data ; int ret ; { algo_data = (struct i2c_algo_dp_aux_data *)adapter->algo_data; if (! algo_data->running) { return (-5); } else { } ret = i2c_algo_dp_aux_transaction(adapter, 2, (int )byte, (uint8_t *)0U); return (ret); } } static int i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter , u8 *byte_ret ) { struct i2c_algo_dp_aux_data *algo_data ; int ret ; { algo_data = (struct i2c_algo_dp_aux_data *)adapter->algo_data; if (! algo_data->running) { return (-5); } else { } ret = i2c_algo_dp_aux_transaction(adapter, 4, 0, byte_ret); return (ret); } } static int i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter , struct i2c_msg *msgs , int num ) { int ret ; bool reading ; int m ; int b ; u16 len ; u8 *buf ; long tmp ; { ret = 0; reading = 0; m = 0; goto ldv_41605; ldv_41604: len = (msgs + (unsigned long )m)->len; buf = (msgs + (unsigned long )m)->buf; reading = ((int )(msgs + (unsigned long )m)->flags & 1) != 0; ret = i2c_algo_dp_aux_address(adapter, (int )(msgs + (unsigned long )m)->addr, (int )reading); if (ret < 0) { goto ldv_41597; } else { } if ((int )reading) { b = 0; goto ldv_41600; ldv_41599: ret = i2c_algo_dp_aux_get_byte(adapter, buf + (unsigned long )b); if (ret < 0) { goto ldv_41598; } else { } b = b + 1; ldv_41600: ; if ((int )len > b) { goto ldv_41599; } else { } ldv_41598: ; } else { b = 0; goto ldv_41603; ldv_41602: ret = i2c_algo_dp_aux_put_byte(adapter, (int )*(buf + (unsigned long )b)); if (ret < 0) { goto ldv_41601; } else { } b = b + 1; ldv_41603: ; if ((int )len > b) { goto ldv_41602; } else { } ldv_41601: ; } if (ret < 0) { goto ldv_41597; } else { } m = m + 1; ldv_41605: ; if (m < num) { goto ldv_41604; } else { } ldv_41597: ; if (ret >= 0) { ret = num; } else { } i2c_algo_dp_aux_stop(adapter, (int )reading); tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("i2c_algo_dp_aux_xfer", "dp_aux_xfer return %d\n", ret); } else { } return (ret); } } static u32 i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter ) { { return (268402699U); } } static struct i2c_algorithm const i2c_dp_aux_algo = {& i2c_algo_dp_aux_xfer, 0, & i2c_algo_dp_aux_functionality, 0, 0}; static void i2c_dp_aux_reset_bus(struct i2c_adapter *adapter ) { { i2c_algo_dp_aux_address(adapter, 0, 0); i2c_algo_dp_aux_stop(adapter, 0); return; } } static int i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter ) { { adapter->algo = & i2c_dp_aux_algo; adapter->retries = 3; i2c_dp_aux_reset_bus(adapter); return (0); } } static int i2c_dp_aux_add_bus(struct i2c_adapter *adapter ) { int error ; { error = i2c_dp_aux_prepare_bus(adapter); if (error != 0) { return (error); } else { } error = i2c_add_adapter(adapter); return (error); } } static struct ddi_regoff ddi_DP_train_table[2U] = { {33068U, 33060U, 33108U, 33096U, 33100U, 33104U, 33112U}, {33324U, 33316U, 33364U, 33352U, 33356U, 33360U, 33368U}}; static uint32_t dp_vswing_premph_table[8U] = { 1429440852U, 16384U, 1431144788U, 8192U, 1432783188U, 0U, 1436205268U, 24576U}; static bool is_edp(struct gma_encoder *encoder ) { { return (encoder->type == 10); } } static void cdv_intel_dp_start_link_train(struct gma_encoder *encoder ) ; static void cdv_intel_dp_complete_link_train(struct gma_encoder *encoder ) ; static void cdv_intel_dp_link_down(struct gma_encoder *encoder ) ; static int cdv_intel_dp_max_lane_count(struct gma_encoder *encoder ) { struct cdv_intel_dp *intel_dp ; int max_lane_count ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; max_lane_count = 4; if ((unsigned int )intel_dp->dpcd[0] > 16U) { max_lane_count = (int )intel_dp->dpcd[2] & 31; switch (max_lane_count) { case 1: ; case 2: ; case 4: ; goto ldv_41670; default: max_lane_count = 4; } ldv_41670: ; } else { } return (max_lane_count); } } static int cdv_intel_dp_max_link_bw(struct gma_encoder *encoder ) { struct cdv_intel_dp *intel_dp ; int max_link_bw ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; max_link_bw = (int )intel_dp->dpcd[1]; switch (max_link_bw) { case 6: ; case 10: ; goto ldv_41679; default: max_link_bw = 6; goto ldv_41679; } ldv_41679: ; return (max_link_bw); } } static int cdv_intel_dp_link_clock(uint8_t link_bw ) { { if ((unsigned int )link_bw == 10U) { return (270000); } else { return (162000); } } } static int cdv_intel_dp_link_required(int pixel_clock , int bpp ) { { return ((pixel_clock * bpp + 7) / 8); } } static int cdv_intel_dp_max_data_rate(int max_link_clock , int max_lanes ) { { return (((max_link_clock * max_lanes) * 19) / 20); } } static void cdv_intel_edp_panel_vdd_on(struct gma_encoder *intel_encoder ) { struct drm_device *dev ; struct cdv_intel_dp *intel_dp ; u32 pp ; long tmp ; long tmp___0 ; { dev = intel_encoder->base.dev; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; if ((int )intel_dp->panel_on) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_edp_panel_vdd_on", "Skip VDD on because of panel on\n"); } else { } return; } else { } tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("cdv_intel_edp_panel_vdd_on", "\n"); } else { } pp = REGISTER_READ(dev, 397828U); pp = pp | 8U; REGISTER_WRITE(dev, 397828U, pp); REGISTER_READ(dev, 397828U); msleep((unsigned int )intel_dp->panel_power_up_delay); return; } } static void cdv_intel_edp_panel_vdd_off(struct gma_encoder *intel_encoder ) { struct drm_device *dev ; u32 pp ; long tmp ; { dev = intel_encoder->base.dev; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_edp_panel_vdd_off", "\n"); } else { } pp = REGISTER_READ(dev, 397828U); pp = pp & 4294967287U; REGISTER_WRITE(dev, 397828U, pp); REGISTER_READ(dev, 397828U); return; } } static bool cdv_intel_edp_panel_on(struct gma_encoder *intel_encoder ) { struct drm_device *dev ; struct cdv_intel_dp *intel_dp ; u32 pp ; u32 idle_on_mask ; long tmp ; uint32_t tmp___0 ; long tmp___1 ; unsigned long timeout__ ; unsigned long tmp___2 ; int ret__ ; int pscr_ret__ ; void const *__vpp_verify ; int pfo_ret__ ; int pfo_ret_____0 ; int pfo_ret_____1 ; int pfo_ret_____2 ; int tmp___3 ; uint32_t tmp___4 ; { dev = intel_encoder->base.dev; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; idle_on_mask = 2147483648U; if ((int )intel_dp->panel_on) { return (1); } else { } tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_edp_panel_on", "\n"); } else { } pp = REGISTER_READ(dev, 397828U); pp = pp & 65535U; pp = pp | 2882338817U; REGISTER_WRITE(dev, 397828U, pp); REGISTER_READ(dev, 397828U); tmp___2 = msecs_to_jiffies(1000U); timeout__ = tmp___2 + (unsigned long )jiffies; ret__ = 0; goto ldv_41764; ldv_41763: ; if ((long )(timeout__ - (unsigned long )jiffies) < 0L) { ret__ = -110; goto ldv_41721; } else { } __vpp_verify = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret__): "m" (cpu_number)); goto ldv_41727; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41727; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41727; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41727; default: __bad_percpu_size(); } ldv_41727: pscr_ret__ = pfo_ret__; goto ldv_41733; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41737; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41737; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41737; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41737; default: __bad_percpu_size(); } ldv_41737: pscr_ret__ = pfo_ret_____0; goto ldv_41733; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41746; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41746; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41746; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41746; default: __bad_percpu_size(); } ldv_41746: pscr_ret__ = pfo_ret_____1; goto ldv_41733; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41755; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41755; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41755; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41755; default: __bad_percpu_size(); } ldv_41755: pscr_ret__ = pfo_ret_____2; goto ldv_41733; default: __bad_size_call_parameter(); goto ldv_41733; } ldv_41733: tmp___3 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret__ != tmp___3) { msleep(1U); } else { } ldv_41764: tmp___4 = REGISTER_READ(dev, 397824U); if ((tmp___4 & idle_on_mask) != idle_on_mask) { goto ldv_41763; } else { } ldv_41721: ; if (ret__ != 0) { tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { tmp___0 = REGISTER_READ(dev, 397824U); drm_ut_debug_printk("cdv_intel_edp_panel_on", "Error in Powering up eDP panel, status %x\n", tmp___0); } else { } intel_dp->panel_on = 0; } else { intel_dp->panel_on = 1; } msleep((unsigned int )intel_dp->panel_power_up_delay); return (0); } } static void cdv_intel_edp_panel_off(struct gma_encoder *intel_encoder ) { struct drm_device *dev ; u32 pp ; u32 idle_off_mask ; struct cdv_intel_dp *intel_dp ; long tmp ; uint32_t tmp___0 ; long tmp___1 ; long tmp___2 ; unsigned long timeout__ ; unsigned long tmp___3 ; int ret__ ; int pscr_ret__ ; void const *__vpp_verify ; int pfo_ret__ ; int pfo_ret_____0 ; int pfo_ret_____1 ; int pfo_ret_____2 ; int tmp___4 ; uint32_t tmp___5 ; long tmp___6 ; { dev = intel_encoder->base.dev; idle_off_mask = 2147483648U; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_edp_panel_off", "\n"); } else { } pp = REGISTER_READ(dev, 397828U); if ((pp & 1U) == 0U) { return; } else { } intel_dp->panel_on = 0; pp = pp & 65535U; pp = pp & 4294967294U; pp = pp & 4294967287U; pp = pp & 4294967291U; REGISTER_WRITE(dev, 397828U, pp); REGISTER_READ(dev, 397828U); tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { tmp___0 = REGISTER_READ(dev, 397824U); drm_ut_debug_printk("cdv_intel_edp_panel_off", "PP_STATUS %x\n", tmp___0); } else { } tmp___3 = msecs_to_jiffies(1000U); timeout__ = tmp___3 + (unsigned long )jiffies; ret__ = 0; goto ldv_41825; ldv_41824: ; if ((long )(timeout__ - (unsigned long )jiffies) < 0L) { ret__ = -110; goto ldv_41782; } else { } __vpp_verify = (void const *)0; switch (4UL) { case 1UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret__): "m" (cpu_number)); goto ldv_41788; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41788; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41788; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret__): "m" (cpu_number)); goto ldv_41788; default: __bad_percpu_size(); } ldv_41788: pscr_ret__ = pfo_ret__; goto ldv_41794; case 2UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41798; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41798; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41798; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____0): "m" (cpu_number)); goto ldv_41798; default: __bad_percpu_size(); } ldv_41798: pscr_ret__ = pfo_ret_____0; goto ldv_41794; case 4UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41807; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41807; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41807; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____1): "m" (cpu_number)); goto ldv_41807; default: __bad_percpu_size(); } ldv_41807: pscr_ret__ = pfo_ret_____1; goto ldv_41794; case 8UL: ; switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41816; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41816; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41816; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret_____2): "m" (cpu_number)); goto ldv_41816; default: __bad_percpu_size(); } ldv_41816: pscr_ret__ = pfo_ret_____2; goto ldv_41794; default: __bad_size_call_parameter(); goto ldv_41794; } ldv_41794: tmp___4 = atomic_read((atomic_t const *)(& kgdb_active)); if (pscr_ret__ != tmp___4) { msleep(1U); } else { } ldv_41825: tmp___5 = REGISTER_READ(dev, 397824U); if ((tmp___5 & idle_off_mask) != 0U) { goto ldv_41824; } else { } ldv_41782: ; if (ret__ != 0) { tmp___2 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("cdv_intel_edp_panel_off", "Error in turning off Panel\n"); } else { } } else { } msleep((unsigned int )intel_dp->panel_power_cycle_delay); tmp___6 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___6 != 0L) { drm_ut_debug_printk("cdv_intel_edp_panel_off", "Over\n"); } else { } return; } } static void cdv_intel_edp_backlight_on(struct gma_encoder *intel_encoder ) { struct drm_device *dev ; u32 pp ; long tmp ; { dev = intel_encoder->base.dev; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_edp_backlight_on", "\n"); } else { } msleep(300U); pp = REGISTER_READ(dev, 397828U); pp = pp | 4U; REGISTER_WRITE(dev, 397828U, pp); gma_backlight_enable(dev); return; } } static void cdv_intel_edp_backlight_off(struct gma_encoder *intel_encoder ) { struct drm_device *dev ; struct cdv_intel_dp *intel_dp ; u32 pp ; long tmp ; { dev = intel_encoder->base.dev; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_edp_backlight_off", "\n"); } else { } gma_backlight_disable(dev); msleep(10U); pp = REGISTER_READ(dev, 397828U); pp = pp & 4294967291U; REGISTER_WRITE(dev, 397828U, pp); msleep((unsigned int )intel_dp->backlight_off_delay); return; } } static int cdv_intel_dp_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) { struct gma_encoder *encoder ; struct gma_encoder *tmp ; struct cdv_intel_dp *intel_dp ; int max_link_clock ; int tmp___0 ; int tmp___1 ; int max_lanes ; int tmp___2 ; struct drm_psb_private *dev_priv ; bool tmp___3 ; bool tmp___4 ; int tmp___5 ; int tmp___6 ; int tmp___7 ; int tmp___8 ; int tmp___9 ; bool tmp___10 ; { tmp = gma_attached_encoder(connector); encoder = tmp; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; tmp___0 = cdv_intel_dp_max_link_bw(encoder); tmp___1 = cdv_intel_dp_link_clock((int )((uint8_t )tmp___0)); max_link_clock = tmp___1; tmp___2 = cdv_intel_dp_max_lane_count(encoder); max_lanes = tmp___2; dev_priv = (struct drm_psb_private *)(connector->dev)->dev_private; tmp___3 = is_edp(encoder); if ((int )tmp___3 && (unsigned long )intel_dp->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { if (mode->hdisplay > (intel_dp->panel_fixed_mode)->hdisplay) { return (29); } else { } if (mode->vdisplay > (intel_dp->panel_fixed_mode)->vdisplay) { return (29); } else { } } else { } tmp___4 = is_edp(encoder); if (tmp___4) { tmp___5 = 0; } else { tmp___5 = 1; } if (tmp___5) { tmp___6 = cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp); tmp___7 = cdv_intel_dp_max_data_rate(max_link_clock, max_lanes); if (tmp___6 > tmp___7) { return (15); } else { } } else { } tmp___10 = is_edp(encoder); if ((int )tmp___10) { tmp___8 = cdv_intel_dp_link_required(mode->clock, 24); tmp___9 = cdv_intel_dp_max_data_rate(max_link_clock, max_lanes); if (tmp___8 > tmp___9) { return (15); } else { } } else { } if (mode->clock <= 9999) { return (16); } else { } return (0); } } static uint32_t pack_aux(uint8_t *src , int src_bytes ) { int i ; uint32_t v ; { v = 0U; if (src_bytes > 4) { src_bytes = 4; } else { } i = 0; goto ldv_41856; ldv_41855: v = ((unsigned int )*(src + (unsigned long )i) << (3 - i) * 8) | v; i = i + 1; ldv_41856: ; if (i < src_bytes) { goto ldv_41855; } else { } return (v); } } static void unpack_aux(uint32_t src , uint8_t *dst , int dst_bytes ) { int i ; { if (dst_bytes > 4) { dst_bytes = 4; } else { } i = 0; goto ldv_41865; ldv_41864: *(dst + (unsigned long )i) = (uint8_t )(src >> (3 - i) * 8); i = i + 1; ldv_41865: ; if (i < dst_bytes) { goto ldv_41864; } else { } return; } } static int cdv_intel_dp_aux_ch(struct gma_encoder *encoder , uint8_t *send , int send_bytes , uint8_t *recv , int recv_size ) { struct cdv_intel_dp *intel_dp ; uint32_t output_reg ; struct drm_device *dev ; uint32_t ch_ctl ; uint32_t ch_data ; int i ; int recv_bytes ; uint32_t status ; uint32_t aux_clock_divider ; int try ; int precharge ; bool tmp ; uint32_t tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; long tmp___3 ; uint32_t tmp___4 ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; output_reg = intel_dp->output_reg; dev = encoder->base.dev; ch_ctl = output_reg + 16U; ch_data = ch_ctl + 4U; aux_clock_divider = 100U; precharge = 4; tmp = is_edp(encoder); if ((int )tmp) { precharge = 10; } else { } tmp___1 = REGISTER_READ(dev, ch_ctl); if ((int )tmp___1 < 0) { tmp___0 = REGISTER_READ(dev, ch_ctl); drm_err("dp_aux_ch not started status 0x%08x\n", tmp___0); return (-16); } else { } try = 0; goto ldv_41892; ldv_41891: i = 0; goto ldv_41886; ldv_41885: tmp___2 = pack_aux(send + (unsigned long )i, send_bytes - i); REGISTER_WRITE(dev, ch_data + (uint32_t )i, tmp___2); i = i + 4; ldv_41886: ; if (i < send_bytes) { goto ldv_41885; } else { } REGISTER_WRITE(dev, ch_ctl, ((uint32_t )(((long )(send_bytes << 20) | (-0x7FFFFFFF-1)) | (long )(precharge << 16)) | aux_clock_divider) | 1375731712U); ldv_41889: status = REGISTER_READ(dev, ch_ctl); if ((int )status >= 0) { goto ldv_41888; } else { } __const_udelay(429500UL); goto ldv_41889; ldv_41888: REGISTER_WRITE(dev, ch_ctl, status | 1375731712U); if ((status & 1073741824U) != 0U) { goto ldv_41890; } else { } try = try + 1; ldv_41892: ; if (try <= 4) { goto ldv_41891; } else { } ldv_41890: ; if ((status & 1073741824U) == 0U) { drm_err("dp_aux_ch not done status 0x%08x\n", status); return (-16); } else { } if ((status & 33554432U) != 0U) { drm_err("dp_aux_ch receive error status 0x%08x\n", status); return (-5); } else { } if ((status & 268435456U) != 0U) { tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("cdv_intel_dp_aux_ch", "dp_aux_ch timeout status 0x%08x\n", status); } else { } return (-110); } else { } recv_bytes = (int )((status & 32505856U) >> 20); if (recv_bytes > recv_size) { recv_bytes = recv_size; } else { } i = 0; goto ldv_41895; ldv_41894: tmp___4 = REGISTER_READ(dev, ch_data + (uint32_t )i); unpack_aux(tmp___4, recv + (unsigned long )i, recv_bytes - i); i = i + 4; ldv_41895: ; if (i < recv_bytes) { goto ldv_41894; } else { } return (recv_bytes); } } static int cdv_intel_dp_aux_native_write(struct gma_encoder *encoder , uint16_t address , uint8_t *send , int send_bytes ) { int ret ; uint8_t msg[20U] ; int msg_bytes ; uint8_t ack ; { if (send_bytes > 16) { return (-1); } else { } msg[0] = 128U; msg[1] = (uint8_t )((int )address >> 8); msg[2] = (uint8_t )address; msg[3] = (unsigned int )((uint8_t )send_bytes) + 255U; memcpy((void *)(& msg) + 4U, (void const *)send, (size_t )send_bytes); msg_bytes = send_bytes + 4; ldv_41908: ret = cdv_intel_dp_aux_ch(encoder, (uint8_t *)(& msg), msg_bytes, & ack, 1); if (ret < 0) { return (ret); } else { } ack = (uint8_t )((int )ack >> 4); if (((int )ack & 3) == 0) { goto ldv_41907; } else if (((int )ack & 3) == 2) { __const_udelay(429500UL); } else { return (-5); } goto ldv_41908; ldv_41907: ; return (send_bytes); } } static int cdv_intel_dp_aux_native_write_1(struct gma_encoder *encoder , uint16_t address , uint8_t byte ) { int tmp ; { tmp = cdv_intel_dp_aux_native_write(encoder, (int )address, & byte, 1); return (tmp); } } static int cdv_intel_dp_aux_native_read(struct gma_encoder *encoder , uint16_t address , uint8_t *recv , int recv_bytes ) { uint8_t msg[4U] ; int msg_bytes ; uint8_t reply[20U] ; int reply_bytes ; uint8_t ack ; int ret ; { msg[0] = 144U; msg[1] = (uint8_t )((int )address >> 8); msg[2] = (uint8_t )address; msg[3] = (unsigned int )((uint8_t )recv_bytes) + 255U; msg_bytes = 4; reply_bytes = recv_bytes + 1; ldv_41926: ret = cdv_intel_dp_aux_ch(encoder, (uint8_t *)(& msg), msg_bytes, (uint8_t *)(& reply), reply_bytes); if (ret == 0) { return (-71); } else { } if (ret < 0) { return (ret); } else { } ack = (uint8_t )((int )reply[0] >> 4); if (((int )ack & 3) == 0) { memcpy((void *)recv, (void const *)(& reply) + 1U, (size_t )(ret + -1)); return (ret + -1); } else if (((int )ack & 3) == 2) { __const_udelay(429500UL); } else { return (-5); } goto ldv_41926; } } static int cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter , int mode , uint8_t write_byte , uint8_t *read_byte ) { struct i2c_algo_dp_aux_data *algo_data ; struct cdv_intel_dp *intel_dp ; struct i2c_adapter const *__mptr ; struct gma_encoder *encoder ; uint16_t address ; uint8_t msg[5U] ; uint8_t reply[2U] ; unsigned int retry ; int msg_bytes ; int reply_bytes ; int ret ; long tmp ; long tmp___0 ; long tmp___1 ; long tmp___2 ; { algo_data = (struct i2c_algo_dp_aux_data *)adapter->algo_data; __mptr = (struct i2c_adapter const *)adapter; intel_dp = (struct cdv_intel_dp *)__mptr + 0xffffffffffffffd0UL; encoder = intel_dp->encoder; address = algo_data->address; if ((mode & 4) != 0) { msg[0] = 16U; } else { msg[0] = 0U; } if ((mode & 8) == 0) { msg[0] = (uint8_t )((unsigned int )msg[0] | 64U); } else { } msg[1] = (uint8_t )((int )address >> 8); msg[2] = (uint8_t )address; switch (mode) { case 2: msg[3] = 0U; msg[4] = write_byte; msg_bytes = 5; reply_bytes = 1; goto ldv_41946; case 4: msg[3] = 0U; msg_bytes = 4; reply_bytes = 2; goto ldv_41946; default: msg_bytes = 3; reply_bytes = 1; goto ldv_41946; } ldv_41946: retry = 0U; goto ldv_41962; ldv_41961: ret = cdv_intel_dp_aux_ch(encoder, (uint8_t *)(& msg), msg_bytes, (uint8_t *)(& reply), reply_bytes); if (ret < 0) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dp_i2c_aux_ch", "aux_ch failed %d\n", ret); } else { } return (ret); } else { } switch (((int )reply[0] >> 4) & 3) { case 0: ; goto ldv_41951; case 1: tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("cdv_intel_dp_i2c_aux_ch", "aux_ch native nack\n"); } else { } return (-121); case 2: __const_udelay(429500UL); goto ldv_41954; default: drm_err("aux_ch invalid native reply 0x%02x\n", (int )reply[0]); return (-121); } ldv_41951: ; switch (((int )reply[0] >> 4) & 12) { case 0: ; if (mode == 4) { *read_byte = reply[1]; } else { } return (reply_bytes + -1); case 4: tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("cdv_intel_dp_i2c_aux_ch", "aux_i2c nack\n"); } else { } return (-121); case 8: tmp___2 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("cdv_intel_dp_i2c_aux_ch", "aux_i2c defer\n"); } else { } __const_udelay(429500UL); goto ldv_41959; default: drm_err("aux_i2c invalid reply 0x%02x\n", (int )reply[0]); return (-121); } ldv_41959: ; ldv_41954: retry = retry + 1U; ldv_41962: ; if (retry <= 4U) { goto ldv_41961; } else { } drm_err("too many retries, giving up\n"); return (-121); } } static int cdv_intel_dp_i2c_init(struct gma_connector *connector , struct gma_encoder *encoder , char const *name ) { struct cdv_intel_dp *intel_dp ; int ret ; long tmp ; bool tmp___0 ; bool tmp___1 ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dp_i2c_init", "i2c_init %s\n", name); } else { } intel_dp->algo.running = 0; intel_dp->algo.address = 0U; intel_dp->algo.aux_ch = & cdv_intel_dp_i2c_aux_ch; memset((void *)(& intel_dp->adapter), 0, 1936UL); intel_dp->adapter.owner = & __this_module; intel_dp->adapter.class = 8U; strncpy((char *)(& intel_dp->adapter.name), name, 47UL); intel_dp->adapter.name[47UL] = 0; intel_dp->adapter.algo_data = (void *)(& intel_dp->algo); intel_dp->adapter.dev.parent = connector->base.kdev; tmp___0 = is_edp(encoder); if ((int )tmp___0) { cdv_intel_edp_panel_vdd_on(encoder); } else { } ret = i2c_dp_aux_add_bus(& intel_dp->adapter); tmp___1 = is_edp(encoder); if ((int )tmp___1) { cdv_intel_edp_panel_vdd_off(encoder); } else { } return (ret); } } static void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode , struct drm_display_mode *adjusted_mode ) { { adjusted_mode->hdisplay = fixed_mode->hdisplay; adjusted_mode->hsync_start = fixed_mode->hsync_start; adjusted_mode->hsync_end = fixed_mode->hsync_end; adjusted_mode->htotal = fixed_mode->htotal; adjusted_mode->vdisplay = fixed_mode->vdisplay; adjusted_mode->vsync_start = fixed_mode->vsync_start; adjusted_mode->vsync_end = fixed_mode->vsync_end; adjusted_mode->vtotal = fixed_mode->vtotal; adjusted_mode->clock = fixed_mode->clock; drm_mode_set_crtcinfo(adjusted_mode, 1); return; } } static bool cdv_intel_dp_mode_fixup(struct drm_encoder *encoder , struct drm_display_mode const *mode , struct drm_display_mode *adjusted_mode ) { struct drm_psb_private *dev_priv ; struct gma_encoder *intel_encoder ; struct drm_encoder const *__mptr ; struct cdv_intel_dp *intel_dp ; int lane_count ; int clock ; int max_lane_count ; int tmp ; int max_clock ; int tmp___0 ; int bws[2U] ; int refclock ; int bpp ; bool tmp___1 ; int link_avail ; int tmp___2 ; int tmp___3 ; long tmp___4 ; int tmp___5 ; long tmp___6 ; bool tmp___7 ; { dev_priv = (struct drm_psb_private *)(encoder->dev)->dev_private; __mptr = (struct drm_encoder const *)encoder; intel_encoder = (struct gma_encoder *)__mptr; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; tmp = cdv_intel_dp_max_lane_count(intel_encoder); max_lane_count = tmp; tmp___0 = cdv_intel_dp_max_link_bw(intel_encoder); max_clock = tmp___0 == 10; bws[0] = 6; bws[1] = 10; refclock = mode->clock; bpp = 24; tmp___1 = is_edp(intel_encoder); if ((int )tmp___1 && (unsigned long )intel_dp->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode); refclock = (intel_dp->panel_fixed_mode)->clock; bpp = dev_priv->edp.bpp; } else { } lane_count = 1; goto ldv_41999; ldv_41998: clock = max_clock; goto ldv_41996; ldv_41995: tmp___2 = cdv_intel_dp_link_clock((int )((uint8_t )bws[clock])); tmp___3 = cdv_intel_dp_max_data_rate(tmp___2, lane_count); link_avail = tmp___3; tmp___5 = cdv_intel_dp_link_required(refclock, bpp); if (tmp___5 <= link_avail) { intel_dp->link_bw = (uint8_t )bws[clock]; intel_dp->lane_count = (uint8_t )lane_count; adjusted_mode->clock = cdv_intel_dp_link_clock((int )intel_dp->link_bw); tmp___4 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("cdv_intel_dp_mode_fixup", "Display port link bw %02x lane count %d clock %d\n", (int )intel_dp->link_bw, (int )intel_dp->lane_count, adjusted_mode->clock); } else { } return (1); } else { } clock = clock - 1; ldv_41996: ; if (clock >= 0) { goto ldv_41995; } else { } lane_count = lane_count << 1; ldv_41999: ; if (lane_count <= max_lane_count) { goto ldv_41998; } else { } tmp___7 = is_edp(intel_encoder); if ((int )tmp___7) { intel_dp->lane_count = (uint8_t )max_lane_count; intel_dp->link_bw = (uint8_t )bws[max_clock]; adjusted_mode->clock = cdv_intel_dp_link_clock((int )intel_dp->link_bw); tmp___6 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___6 != 0L) { drm_ut_debug_printk("cdv_intel_dp_mode_fixup", "Force picking display port link bw %02x lane count %d clock %d\n", (int )intel_dp->link_bw, (int )intel_dp->lane_count, adjusted_mode->clock); } else { } return (1); } else { } return (0); } } static void cdv_intel_reduce_ratio(uint32_t *num , uint32_t *den ) { uint64_t value ; uint64_t m ; uint32_t __base ; uint32_t __rem ; { m = (uint64_t )*num; value = m * 8388608ULL; __base = *den; __rem = (uint32_t )(value % (uint64_t )__base); value = value / (uint64_t )__base; m = (uint64_t )__rem; *num = (uint32_t )value; *den = 8388608U; return; } } static void cdv_intel_dp_compute_m_n(int bpp , int nlanes , int pixel_clock , int link_clock , struct cdv_intel_dp_m_n *m_n ) { { m_n->tu = 64U; m_n->gmch_m = (uint32_t )((pixel_clock * bpp + 7) >> 3); m_n->gmch_n = (uint32_t )(link_clock * nlanes); cdv_intel_reduce_ratio(& m_n->gmch_m, & m_n->gmch_n); m_n->link_m = (uint32_t )pixel_clock; m_n->link_n = (uint32_t )link_clock; cdv_intel_reduce_ratio(& m_n->link_m, & m_n->link_n); return; } } void cdv_intel_dp_set_m_n(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct drm_mode_config *mode_config ; struct drm_encoder *encoder ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int lane_count ; int bpp ; struct cdv_intel_dp_m_n m_n ; int pipe ; struct list_head const *__mptr___0 ; struct gma_encoder *intel_encoder ; struct cdv_intel_dp *intel_dp ; struct drm_encoder const *__mptr___1 ; bool tmp ; struct list_head const *__mptr___2 ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_config = & dev->mode_config; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; lane_count = 4; bpp = 24; pipe = gma_crtc->pipe; __mptr___0 = (struct list_head const *)mode_config->encoder_list.next; encoder = (struct drm_encoder *)__mptr___0 + 0xfffffffffffffff8UL; goto ldv_42050; ldv_42049: ; if ((unsigned long )encoder->crtc != (unsigned long )crtc) { goto ldv_42045; } else { } __mptr___1 = (struct drm_encoder const *)encoder; intel_encoder = (struct gma_encoder *)__mptr___1; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; if (intel_encoder->type == 9) { lane_count = (int )intel_dp->lane_count; goto ldv_42048; } else { tmp = is_edp(intel_encoder); if ((int )tmp) { lane_count = (int )intel_dp->lane_count; bpp = dev_priv->edp.bpp; goto ldv_42048; } else { } } ldv_42045: __mptr___2 = (struct list_head const *)encoder->head.next; encoder = (struct drm_encoder *)__mptr___2 + 0xfffffffffffffff8UL; ldv_42050: ; if ((unsigned long )(& encoder->head) != (unsigned long )(& mode_config->encoder_list)) { goto ldv_42049; } else { } ldv_42048: cdv_intel_dp_compute_m_n(bpp, lane_count, mode->clock, adjusted_mode->clock, & m_n); REGISTER_WRITE(dev, (uint32_t )(pipe * 4096 + 458832), ((m_n.tu - 1U) << 25) | m_n.gmch_m); REGISTER_WRITE(dev, (uint32_t )(pipe * 4096 + 458836), m_n.gmch_n); REGISTER_WRITE(dev, (uint32_t )(pipe * 4096 + 458848), m_n.link_m); REGISTER_WRITE(dev, (uint32_t )(pipe * 4096 + 458852), m_n.link_n); return; } } static void cdv_intel_dp_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct gma_encoder *intel_encoder ; struct drm_encoder const *__mptr ; struct drm_crtc *crtc ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr___0 ; struct cdv_intel_dp *intel_dp ; struct drm_device *dev ; long tmp ; uint32_t pfit_control ; bool tmp___0 ; { __mptr = (struct drm_encoder const *)encoder; intel_encoder = (struct gma_encoder *)__mptr; crtc = encoder->crtc; __mptr___0 = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr___0; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; dev = encoder->dev; intel_dp->DP = 0U; intel_dp->DP = intel_dp->DP | intel_dp->color_range; if ((int )adjusted_mode->flags & 1) { intel_dp->DP = intel_dp->DP | 8U; } else { } if ((adjusted_mode->flags & 4U) != 0U) { intel_dp->DP = intel_dp->DP | 16U; } else { } intel_dp->DP = intel_dp->DP | 805306368U; switch ((int )intel_dp->lane_count) { case 1: intel_dp->DP = intel_dp->DP; goto ldv_42066; case 2: intel_dp->DP = intel_dp->DP | 524288U; goto ldv_42066; case 4: intel_dp->DP = intel_dp->DP | 1572864U; goto ldv_42066; } ldv_42066: ; if ((int )intel_dp->has_audio) { intel_dp->DP = intel_dp->DP | 64U; } else { } memset((void *)(& intel_dp->link_configuration), 0, 9UL); intel_dp->link_configuration[0] = intel_dp->link_bw; intel_dp->link_configuration[1] = intel_dp->lane_count; if ((unsigned int )intel_dp->dpcd[0] > 16U && (int )((signed char )intel_dp->dpcd[2]) < 0) { intel_dp->link_configuration[1] = (uint8_t )((unsigned int )intel_dp->link_configuration[1] | 128U); intel_dp->DP = intel_dp->DP | 262144U; } else { } if (gma_crtc->pipe == 1) { intel_dp->DP = intel_dp->DP | 1073741824U; } else { } REGISTER_WRITE(dev, intel_dp->output_reg, intel_dp->DP | 2147483648U); tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dp_mode_set", "DP expected reg is %x\n", intel_dp->DP); } else { } tmp___0 = is_edp(intel_encoder); if ((int )tmp___0) { cdv_intel_edp_panel_on(intel_encoder); if (mode->hdisplay != adjusted_mode->hdisplay || mode->vdisplay != adjusted_mode->vdisplay) { pfit_control = 2147483648U; } else { pfit_control = 0U; } pfit_control = (uint32_t )(gma_crtc->pipe << 29) | pfit_control; REGISTER_WRITE(dev, 397872U, pfit_control); } else { } return; } } static void cdv_intel_dp_sink_dpms(struct gma_encoder *encoder , int mode ) { struct cdv_intel_dp *intel_dp ; int ret ; int i ; long tmp ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; if ((unsigned int )intel_dp->dpcd[0] <= 16U) { return; } else { } if (mode != 0) { ret = cdv_intel_dp_aux_native_write_1(encoder, 1536, 2); if (ret != 1) { tmp = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dp_sink_dpms", "failed to write sink power state\n"); } else { } } else { } } else { i = 0; goto ldv_42081; ldv_42080: ret = cdv_intel_dp_aux_native_write_1(encoder, 1536, 1); if (ret == 1) { goto ldv_42079; } else { } __const_udelay(4295000UL); i = i + 1; ldv_42081: ; if (i <= 2) { goto ldv_42080; } else { } ldv_42079: ; } return; } } static void cdv_intel_dp_prepare(struct drm_encoder *encoder ) { struct gma_encoder *intel_encoder ; struct drm_encoder const *__mptr ; int edp ; bool tmp ; { __mptr = (struct drm_encoder const *)encoder; intel_encoder = (struct gma_encoder *)__mptr; tmp = is_edp(intel_encoder); edp = (int )tmp; if (edp != 0) { cdv_intel_edp_backlight_off(intel_encoder); cdv_intel_edp_panel_off(intel_encoder); cdv_intel_edp_panel_vdd_on(intel_encoder); } else { } cdv_intel_dp_sink_dpms(intel_encoder, 0); cdv_intel_dp_link_down(intel_encoder); if (edp != 0) { cdv_intel_edp_panel_vdd_off(intel_encoder); } else { } return; } } static void cdv_intel_dp_commit(struct drm_encoder *encoder ) { struct gma_encoder *intel_encoder ; struct drm_encoder const *__mptr ; int edp ; bool tmp ; { __mptr = (struct drm_encoder const *)encoder; intel_encoder = (struct gma_encoder *)__mptr; tmp = is_edp(intel_encoder); edp = (int )tmp; if (edp != 0) { cdv_intel_edp_panel_on(intel_encoder); } else { } cdv_intel_dp_start_link_train(intel_encoder); cdv_intel_dp_complete_link_train(intel_encoder); if (edp != 0) { cdv_intel_edp_backlight_on(intel_encoder); } else { } return; } } static void cdv_intel_dp_dpms(struct drm_encoder *encoder , int mode ) { struct gma_encoder *intel_encoder ; struct drm_encoder const *__mptr ; struct cdv_intel_dp *intel_dp ; struct drm_device *dev ; uint32_t dp_reg ; uint32_t tmp ; int edp ; bool tmp___0 ; { __mptr = (struct drm_encoder const *)encoder; intel_encoder = (struct gma_encoder *)__mptr; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; dev = encoder->dev; tmp = REGISTER_READ(dev, intel_dp->output_reg); dp_reg = tmp; tmp___0 = is_edp(intel_encoder); edp = (int )tmp___0; if (mode != 0) { if (edp != 0) { cdv_intel_edp_backlight_off(intel_encoder); cdv_intel_edp_panel_vdd_on(intel_encoder); } else { } cdv_intel_dp_sink_dpms(intel_encoder, mode); cdv_intel_dp_link_down(intel_encoder); if (edp != 0) { cdv_intel_edp_panel_vdd_off(intel_encoder); cdv_intel_edp_panel_off(intel_encoder); } else { } } else { if (edp != 0) { cdv_intel_edp_panel_on(intel_encoder); } else { } cdv_intel_dp_sink_dpms(intel_encoder, mode); if ((int )dp_reg >= 0) { cdv_intel_dp_start_link_train(intel_encoder); cdv_intel_dp_complete_link_train(intel_encoder); } else { } if (edp != 0) { cdv_intel_edp_backlight_on(intel_encoder); } else { } } return; } } static bool cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder , uint16_t address , uint8_t *recv , int recv_bytes ) { int ret ; int i ; { i = 0; goto ldv_42116; ldv_42115: ret = cdv_intel_dp_aux_native_read(encoder, (int )address, recv, recv_bytes); if (ret == recv_bytes) { return (1); } else { } __const_udelay(4295000UL); i = i + 1; ldv_42116: ; if (i <= 2) { goto ldv_42115; } else { } return (0); } } static bool cdv_intel_dp_get_link_status(struct gma_encoder *encoder ) { struct cdv_intel_dp *intel_dp ; bool tmp ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; tmp = cdv_intel_dp_aux_native_read_retry(encoder, 514, (uint8_t *)(& intel_dp->link_status), 6); return (tmp); } } static uint8_t cdv_intel_dp_link_status(uint8_t *link_status , int r ) { { return (*(link_status + ((unsigned long )r + 0xfffffffffffffdfeUL))); } } static uint8_t cdv_intel_get_adjust_request_voltage(uint8_t *link_status , int lane ) { int i ; int s ; uint8_t l ; uint8_t tmp ; { i = (lane >> 1) + 518; s = lane & 1 ? 4 : 0; tmp = cdv_intel_dp_link_status(link_status, i); l = tmp; return ((unsigned int )((uint8_t )((int )l >> s)) & 3U); } } static uint8_t cdv_intel_get_adjust_request_pre_emphasis(uint8_t *link_status , int lane ) { int i ; int s ; uint8_t l ; uint8_t tmp ; { i = (lane >> 1) + 518; s = lane & 1 ? 6 : 2; tmp = cdv_intel_dp_link_status(link_status, i); l = tmp; return (((unsigned int )((uint8_t )((int )l >> s)) & 3U) << 3U); } } static void cdv_intel_get_adjust_train(struct gma_encoder *encoder ) { struct cdv_intel_dp *intel_dp ; uint8_t v ; uint8_t p ; int lane ; uint8_t this_v ; uint8_t tmp ; uint8_t this_p ; uint8_t tmp___0 ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; v = 0U; p = 0U; lane = 0; goto ldv_42150; ldv_42149: tmp = cdv_intel_get_adjust_request_voltage((uint8_t *)(& intel_dp->link_status), lane); this_v = tmp; tmp___0 = cdv_intel_get_adjust_request_pre_emphasis((uint8_t *)(& intel_dp->link_status), lane); this_p = tmp___0; if ((int )this_v > (int )v) { v = this_v; } else { } if ((int )this_p > (int )p) { p = this_p; } else { } lane = lane + 1; ldv_42150: ; if ((int )intel_dp->lane_count > lane) { goto ldv_42149; } else { } if ((unsigned int )v > 2U) { v = 7U; } else { } if ((unsigned int )p == 24U) { p = (uint8_t )((unsigned int )p | 32U); } else { } lane = 0; goto ldv_42153; ldv_42152: intel_dp->train_set[lane] = (uint8_t )((int )v | (int )p); lane = lane + 1; ldv_42153: ; if (lane <= 3) { goto ldv_42152; } else { } return; } } static uint8_t cdv_intel_get_lane_status(uint8_t *link_status , int lane ) { int i ; int s ; uint8_t l ; uint8_t tmp ; { i = (lane >> 1) + 514; s = (lane & 1) * 4; tmp = cdv_intel_dp_link_status(link_status, i); l = tmp; return ((unsigned int )((uint8_t )((int )l >> s)) & 15U); } } static bool cdv_intel_clock_recovery_ok(uint8_t *link_status , int lane_count ) { int lane ; uint8_t lane_status ; { lane = 0; goto ldv_42169; ldv_42168: lane_status = cdv_intel_get_lane_status(link_status, lane); if (((int )lane_status & 1) == 0) { return (0); } else { } lane = lane + 1; ldv_42169: ; if (lane < lane_count) { goto ldv_42168; } else { } return (1); } } static bool cdv_intel_channel_eq_ok(struct gma_encoder *encoder ) { struct cdv_intel_dp *intel_dp ; uint8_t lane_align ; uint8_t lane_status ; int lane ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; lane_align = cdv_intel_dp_link_status((uint8_t *)(& intel_dp->link_status), 516); if (((int )lane_align & 1) == 0) { return (0); } else { } lane = 0; goto ldv_42179; ldv_42178: lane_status = cdv_intel_get_lane_status((uint8_t *)(& intel_dp->link_status), lane); if (((int )lane_status & 7) != 7) { return (0); } else { } lane = lane + 1; ldv_42179: ; if ((int )intel_dp->lane_count > lane) { goto ldv_42178; } else { } return (1); } } static bool cdv_intel_dp_set_link_train(struct gma_encoder *encoder , uint32_t dp_reg_value , uint8_t dp_train_pat ) { struct drm_device *dev ; int ret ; struct cdv_intel_dp *intel_dp ; long tmp ; { dev = encoder->base.dev; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; REGISTER_WRITE(dev, intel_dp->output_reg, dp_reg_value); REGISTER_READ(dev, intel_dp->output_reg); ret = cdv_intel_dp_aux_native_write_1(encoder, 258, (int )dp_train_pat); if (ret != 1) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dp_set_link_train", "Failure in setting link pattern %x\n", (int )dp_train_pat); } else { } return (0); } else { } return (1); } } static bool cdv_intel_dplink_set_level(struct gma_encoder *encoder , uint8_t dp_train_pat ) { int ret ; struct cdv_intel_dp *intel_dp ; long tmp ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; ret = cdv_intel_dp_aux_native_write(encoder, 259, (uint8_t *)(& intel_dp->train_set), (int )intel_dp->lane_count); if ((int )intel_dp->lane_count != ret) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dplink_set_level", "Failure in setting level %d, lane_cnt= %d\n", (int )intel_dp->train_set[0], (int )intel_dp->lane_count); } else { } return (0); } else { } return (1); } } static void cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder , uint8_t signal_level ) { struct drm_device *dev ; struct cdv_intel_dp *intel_dp ; struct ddi_regoff *ddi_reg ; int vswing ; int premph ; int index ; long tmp ; { dev = encoder->base.dev; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; if (intel_dp->output_reg == 409856U) { ddi_reg = (struct ddi_regoff *)(& ddi_DP_train_table); } else { ddi_reg = (struct ddi_regoff *)(& ddi_DP_train_table) + 1UL; } vswing = (int )signal_level & 3; premph = ((int )signal_level & 24) >> 3; if (vswing + premph > 3) { return; } else { } return; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dp_set_vswing_premph", "Test2\n"); } else { } cdv_sb_reset(dev); cdv_sb_write(dev, ddi_reg->VSwing5, 84226362U); cdv_sb_write(dev, ddi_reg->VSwing1, 1128292437U); index = (vswing + premph) * 2; if (premph == 1 && vswing == 1) { cdv_sb_write(dev, ddi_reg->VSwing2, 1433635156U); } else { cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]); } if (vswing + premph == 3) { cdv_sb_write(dev, ddi_reg->VSwing3, 1887445056U); } else { cdv_sb_write(dev, ddi_reg->VSwing3, 1082138688U); } cdv_sb_write(dev, ddi_reg->VSwing1, 3275776085U); cdv_sb_write(dev, ddi_reg->PreEmph1, 520290368U); index = premph * 2 + 1; cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]); return; } } static void cdv_intel_dp_start_link_train(struct gma_encoder *encoder ) { struct drm_device *dev ; struct cdv_intel_dp *intel_dp ; int i ; uint8_t voltage ; bool clock_recovery ; int tries ; u32 reg ; uint32_t DP ; long tmp ; long tmp___0 ; long tmp___1 ; long tmp___2 ; bool tmp___3 ; int tmp___4 ; bool tmp___5 ; int tmp___6 ; long tmp___7 ; long tmp___8 ; bool tmp___9 ; long tmp___10 ; { dev = encoder->base.dev; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; clock_recovery = 0; DP = intel_dp->DP; DP = DP | 2147483648U; DP = DP & 3489660927U; reg = DP; reg = reg; REGISTER_WRITE(dev, intel_dp->output_reg, reg); REGISTER_READ(dev, intel_dp->output_reg); gma_wait_for_vblank(dev); tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dp_start_link_train", "Link config\n"); } else { } cdv_intel_dp_aux_native_write(encoder, 256, (uint8_t *)(& intel_dp->link_configuration), 2); memset((void *)(& intel_dp->train_set), 0, 4UL); voltage = 0U; tries = 0; clock_recovery = 0; tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("cdv_intel_dp_start_link_train", "Start train\n"); } else { } reg = DP; ldv_42224: tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("cdv_intel_dp_start_link_train", "DP Link Train Set %x, Link_config %x, %x\n", (int )intel_dp->train_set[0], (int )intel_dp->link_configuration[0], (int )intel_dp->link_configuration[1]); } else { } tmp___3 = cdv_intel_dp_set_link_train(encoder, reg, 1); if (tmp___3) { tmp___4 = 0; } else { tmp___4 = 1; } if (tmp___4) { tmp___2 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___2 != 0L) { drm_ut_debug_printk("cdv_intel_dp_start_link_train", "Failure in aux-transfer setting pattern 1\n"); } else { } } else { } cdv_intel_dp_set_vswing_premph(encoder, (int )intel_dp->train_set[0]); cdv_intel_dplink_set_level(encoder, 1); __const_udelay(859000UL); tmp___5 = cdv_intel_dp_get_link_status(encoder); if (tmp___5) { tmp___6 = 0; } else { tmp___6 = 1; } if (tmp___6) { goto ldv_42220; } else { } tmp___7 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___7 != 0L) { drm_ut_debug_printk("cdv_intel_dp_start_link_train", "DP Link status %x, %x, %x, %x, %x, %x\n", (int )intel_dp->link_status[0], (int )intel_dp->link_status[1], (int )intel_dp->link_status[2], (int )intel_dp->link_status[3], (int )intel_dp->link_status[4], (int )intel_dp->link_status[5]); } else { } tmp___9 = cdv_intel_clock_recovery_ok((uint8_t *)(& intel_dp->link_status), (int )intel_dp->lane_count); if ((int )tmp___9) { tmp___8 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___8 != 0L) { drm_ut_debug_printk("cdv_intel_dp_start_link_train", "PT1 train is done\n"); } else { } clock_recovery = 1; goto ldv_42220; } else { } i = 0; goto ldv_42223; ldv_42222: ; if (((int )intel_dp->train_set[i] & 4) == 0) { goto ldv_42221; } else { } i = i + 1; ldv_42223: ; if ((int )intel_dp->lane_count > i) { goto ldv_42222; } else { } ldv_42221: ; if ((int )intel_dp->lane_count == i) { goto ldv_42220; } else { } if (((int )intel_dp->train_set[0] & 3) == (int )voltage) { tries = tries + 1; if (tries == 5) { goto ldv_42220; } else { } } else { tries = 0; } voltage = (unsigned int )intel_dp->train_set[0] & 3U; cdv_intel_get_adjust_train(encoder); goto ldv_42224; ldv_42220: ; if (! clock_recovery) { tmp___10 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___10 != 0L) { drm_ut_debug_printk("cdv_intel_dp_start_link_train", "failure in DP patter 1 training, train set %x\n", (int )intel_dp->train_set[0]); } else { } } else { } intel_dp->DP = DP; return; } } static void cdv_intel_dp_complete_link_train(struct gma_encoder *encoder ) { struct drm_device *dev ; struct cdv_intel_dp *intel_dp ; bool channel_eq ; int tries ; int cr_tries ; u32 reg ; uint32_t DP ; long tmp ; long tmp___0 ; long tmp___1 ; bool tmp___2 ; int tmp___3 ; bool tmp___4 ; int tmp___5 ; long tmp___6 ; bool tmp___7 ; int tmp___8 ; long tmp___9 ; bool tmp___10 ; { dev = encoder->base.dev; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; channel_eq = 0; DP = intel_dp->DP; tries = 0; cr_tries = 0; channel_eq = 0; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("cdv_intel_dp_complete_link_train", "\n"); } else { } reg = DP | 268435456U; ldv_42238: tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("cdv_intel_dp_complete_link_train", "DP Link Train Set %x, Link_config %x, %x\n", (int )intel_dp->train_set[0], (int )intel_dp->link_configuration[0], (int )intel_dp->link_configuration[1]); } else { } tmp___2 = cdv_intel_dp_set_link_train(encoder, reg, 2); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { tmp___1 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___1 != 0L) { drm_ut_debug_printk("cdv_intel_dp_complete_link_train", "Failure in aux-transfer setting pattern 2\n"); } else { } } else { } if (cr_tries > 5) { drm_err("failed to train DP, aborting\n"); cdv_intel_dp_link_down(encoder); goto ldv_42236; } else { } cdv_intel_dp_set_vswing_premph(encoder, (int )intel_dp->train_set[0]); cdv_intel_dplink_set_level(encoder, 2); __const_udelay(4295000UL); tmp___4 = cdv_intel_dp_get_link_status(encoder); if (tmp___4) { tmp___5 = 0; } else { tmp___5 = 1; } if (tmp___5) { goto ldv_42236; } else { } tmp___6 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___6 != 0L) { drm_ut_debug_printk("cdv_intel_dp_complete_link_train", "DP Link status %x, %x, %x, %x, %x, %x\n", (int )intel_dp->link_status[0], (int )intel_dp->link_status[1], (int )intel_dp->link_status[2], (int )intel_dp->link_status[3], (int )intel_dp->link_status[4], (int )intel_dp->link_status[5]); } else { } tmp___7 = cdv_intel_clock_recovery_ok((uint8_t *)(& intel_dp->link_status), (int )intel_dp->lane_count); if (tmp___7) { tmp___8 = 0; } else { tmp___8 = 1; } if (tmp___8) { cdv_intel_dp_start_link_train(encoder); cr_tries = cr_tries + 1; goto ldv_42237; } else { } tmp___10 = cdv_intel_channel_eq_ok(encoder); if ((int )tmp___10) { tmp___9 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___9 != 0L) { drm_ut_debug_printk("cdv_intel_dp_complete_link_train", "PT2 train is done\n"); } else { } channel_eq = 1; goto ldv_42236; } else { } if (tries > 5) { cdv_intel_dp_link_down(encoder); cdv_intel_dp_start_link_train(encoder); tries = 0; cr_tries = cr_tries + 1; goto ldv_42237; } else { } cdv_intel_get_adjust_train(encoder); tries = tries + 1; ldv_42237: ; goto ldv_42238; ldv_42236: reg = DP | 805306368U; REGISTER_WRITE(dev, intel_dp->output_reg, reg); REGISTER_READ(dev, intel_dp->output_reg); cdv_intel_dp_aux_native_write_1(encoder, 258, 0); return; } } static void cdv_intel_dp_link_down(struct gma_encoder *encoder ) { struct drm_device *dev ; struct cdv_intel_dp *intel_dp ; uint32_t DP ; uint32_t tmp ; long tmp___0 ; { dev = encoder->base.dev; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; DP = intel_dp->DP; tmp = REGISTER_READ(dev, intel_dp->output_reg); if ((int )tmp >= 0) { return; } else { } tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("cdv_intel_dp_link_down", "\n"); } else { } DP = DP & 3489660927U; REGISTER_WRITE(dev, intel_dp->output_reg, DP | 536870912U); REGISTER_READ(dev, intel_dp->output_reg); msleep(17U); REGISTER_WRITE(dev, intel_dp->output_reg, DP & 2147483647U); REGISTER_READ(dev, intel_dp->output_reg); return; } } static enum drm_connector_status cdv_dp_detect(struct gma_encoder *encoder ) { struct cdv_intel_dp *intel_dp ; enum drm_connector_status status ; int tmp ; long tmp___0 ; { intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; status = 2; tmp = cdv_intel_dp_aux_native_read(encoder, 0, (uint8_t *)(& intel_dp->dpcd), 4); if (tmp == 4) { if ((unsigned int )intel_dp->dpcd[0] != 0U) { status = 1; } else { } } else { } if ((unsigned int )status == 1U) { tmp___0 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("cdv_dp_detect", "DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n", (int )intel_dp->dpcd[0], (int )intel_dp->dpcd[1], (int )intel_dp->dpcd[2], (int )intel_dp->dpcd[3]); } else { } } else { } return (status); } } static enum drm_connector_status cdv_intel_dp_detect(struct drm_connector *connector , bool force ) { struct gma_encoder *encoder ; struct gma_encoder *tmp ; struct cdv_intel_dp *intel_dp ; enum drm_connector_status status ; struct edid *edid ; int edp ; bool tmp___0 ; { tmp = gma_attached_encoder(connector); encoder = tmp; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; edid = (struct edid *)0; tmp___0 = is_edp(encoder); edp = (int )tmp___0; intel_dp->has_audio = 0; if (edp != 0) { cdv_intel_edp_panel_vdd_on(encoder); } else { } status = cdv_dp_detect(encoder); if ((unsigned int )status != 1U) { if (edp != 0) { cdv_intel_edp_panel_vdd_off(encoder); } else { } return (status); } else { } if (intel_dp->force_audio != 0) { intel_dp->has_audio = intel_dp->force_audio > 0; } else { edid = drm_get_edid(connector, & intel_dp->adapter); if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { intel_dp->has_audio = drm_detect_monitor_audio(edid); kfree((void const *)edid); } else { } } if (edp != 0) { cdv_intel_edp_panel_vdd_off(encoder); } else { } return (1); } } static int cdv_intel_dp_get_modes(struct drm_connector *connector ) { struct gma_encoder *intel_encoder ; struct gma_encoder *tmp ; struct cdv_intel_dp *intel_dp ; struct edid *edid ; int ret ; int edp ; bool tmp___0 ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct drm_display_mode *newmode ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; struct drm_display_mode *mode ; bool tmp___1 ; { tmp = gma_attached_encoder(connector); intel_encoder = tmp; intel_dp = (struct cdv_intel_dp *)intel_encoder->dev_priv; edid = (struct edid *)0; ret = 0; tmp___0 = is_edp(intel_encoder); edp = (int )tmp___0; edid = drm_get_edid(connector, & intel_dp->adapter); if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { drm_mode_connector_update_edid_property(connector, (struct edid const *)edid); ret = drm_add_edid_modes(connector, edid); kfree((void const *)edid); } else { } tmp___1 = is_edp(intel_encoder); if ((int )tmp___1) { dev = connector->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; cdv_intel_edp_panel_vdd_off(intel_encoder); if (ret != 0) { if (edp != 0 && (unsigned long )intel_dp->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { __mptr = (struct list_head const *)connector->probed_modes.next; newmode = (struct drm_display_mode *)__mptr; goto ldv_42278; ldv_42277: ; if ((newmode->type & 8U) != 0U) { intel_dp->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)newmode); goto ldv_42276; } else { } __mptr___0 = (struct list_head const *)newmode->head.next; newmode = (struct drm_display_mode *)__mptr___0; ldv_42278: ; if ((unsigned long )(& newmode->head) != (unsigned long )(& connector->probed_modes)) { goto ldv_42277; } else { } ldv_42276: ; } else { } return (ret); } else { } if ((unsigned long )intel_dp->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0) && (unsigned long )dev_priv->lfp_lvds_vbt_mode != (unsigned long )((struct drm_display_mode *)0)) { intel_dp->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)dev_priv->lfp_lvds_vbt_mode); if ((unsigned long )intel_dp->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { (intel_dp->panel_fixed_mode)->type = (intel_dp->panel_fixed_mode)->type | 8U; } else { } } else { } if ((unsigned long )intel_dp->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)intel_dp->panel_fixed_mode); drm_mode_probed_add(connector, mode); return (1); } else { } } else { } return (ret); } } static bool cdv_intel_dp_detect_audio(struct drm_connector *connector ) { struct gma_encoder *encoder ; struct gma_encoder *tmp ; struct cdv_intel_dp *intel_dp ; struct edid *edid ; bool has_audio ; int edp ; bool tmp___0 ; { tmp = gma_attached_encoder(connector); encoder = tmp; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; has_audio = 0; tmp___0 = is_edp(encoder); edp = (int )tmp___0; if (edp != 0) { cdv_intel_edp_panel_vdd_on(encoder); } else { } edid = drm_get_edid(connector, & intel_dp->adapter); if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { has_audio = drm_detect_monitor_audio(edid); kfree((void const *)edid); } else { } if (edp != 0) { cdv_intel_edp_panel_vdd_off(encoder); } else { } return (has_audio); } } static int cdv_intel_dp_set_property(struct drm_connector *connector , struct drm_property *property , uint64_t val ) { struct drm_psb_private *dev_priv ; struct gma_encoder *encoder ; struct gma_encoder *tmp ; struct cdv_intel_dp *intel_dp ; int ret ; int i ; bool has_audio ; struct drm_crtc *crtc ; { dev_priv = (struct drm_psb_private *)(connector->dev)->dev_private; tmp = gma_attached_encoder(connector); encoder = tmp; intel_dp = (struct cdv_intel_dp *)encoder->dev_priv; ret = drm_object_property_set_value(& connector->base, property, val); if (ret != 0) { return (ret); } else { } if ((unsigned long )dev_priv->force_audio_property == (unsigned long )property) { i = (int )val; if (intel_dp->force_audio == i) { return (0); } else { } intel_dp->force_audio = i; if (i == 0) { has_audio = cdv_intel_dp_detect_audio(connector); } else { has_audio = i > 0; } if ((int )intel_dp->has_audio == (int )has_audio) { return (0); } else { } intel_dp->has_audio = has_audio; goto done; } else { } if ((unsigned long )dev_priv->broadcast_rgb_property == (unsigned long )property) { if ((uint64_t )(intel_dp->color_range != 0U) == val) { return (0); } else { } intel_dp->color_range = val != 0ULL ? 256U : 0U; goto done; } else { } return (-22); done: ; if ((unsigned long )encoder->base.crtc != (unsigned long )((struct drm_crtc *)0)) { crtc = encoder->base.crtc; drm_crtc_helper_set_mode(crtc, & crtc->mode, crtc->x, crtc->y, (crtc->primary)->fb); } else { } return (0); } } static void cdv_intel_dp_destroy(struct drm_connector *connector ) { struct gma_encoder *gma_encoder ; struct gma_encoder *tmp ; struct cdv_intel_dp *intel_dp ; bool tmp___0 ; { tmp = gma_attached_encoder(connector); gma_encoder = tmp; intel_dp = (struct cdv_intel_dp *)gma_encoder->dev_priv; tmp___0 = is_edp(gma_encoder); if ((int )tmp___0) { if ((unsigned long )intel_dp->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { kfree((void const *)intel_dp->panel_fixed_mode); intel_dp->panel_fixed_mode = (struct drm_display_mode *)0; } else { } } else { } i2c_del_adapter(& intel_dp->adapter); drm_connector_unregister(connector); drm_connector_cleanup(connector); kfree((void const *)connector); return; } } static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder ) { { drm_encoder_cleanup(encoder); return; } } static struct drm_encoder_helper_funcs const cdv_intel_dp_helper_funcs = {& cdv_intel_dp_dpms, 0, 0, & cdv_intel_dp_mode_fixup, & cdv_intel_dp_prepare, & cdv_intel_dp_commit, & cdv_intel_dp_mode_set, 0, 0, 0, 0, 0}; static struct drm_connector_funcs const cdv_intel_dp_connector_funcs = {& drm_helper_connector_dpms, 0, 0, 0, & cdv_intel_dp_detect, & drm_helper_probe_single_connector_modes, & cdv_intel_dp_set_property, & cdv_intel_dp_destroy, 0, 0, 0, 0, 0}; static struct drm_connector_helper_funcs const cdv_intel_dp_connector_helper_funcs = {& cdv_intel_dp_get_modes, (enum drm_mode_status (*)(struct drm_connector * , struct drm_display_mode * ))(& cdv_intel_dp_mode_valid), & gma_best_encoder}; static struct drm_encoder_funcs const cdv_intel_dp_enc_funcs = {0, & cdv_intel_dp_encoder_destroy}; static void cdv_intel_dp_add_properties(struct drm_connector *connector ) { { cdv_intel_attach_force_audio_property(connector); cdv_intel_attach_broadcast_rgb_property(connector); return; } } static bool cdv_intel_dpc_is_edp(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct child_device_config *p_child ; int i ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if (dev_priv->child_dev_num == 0) { return (0); } else { } i = 0; goto ldv_42323; ldv_42322: p_child = dev_priv->child_dev + (unsigned long )i; if ((unsigned int )p_child->dvo_port == 8U && (unsigned int )p_child->device_type == 30918U) { return (1); } else { } i = i + 1; ldv_42323: ; if (dev_priv->child_dev_num > i) { goto ldv_42322; } else { } return (0); } } static void cdv_disable_intel_clock_gating(struct drm_device *dev ) { u32 reg_value ; { reg_value = REGISTER_READ(dev, 25088U); reg_value = reg_value | 1124083776U; REGISTER_WRITE(dev, 25088U, reg_value); __const_udelay(2147500UL); return; } } void cdv_intel_dp_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev , int output_reg ) { struct gma_encoder *gma_encoder ; struct gma_connector *gma_connector ; struct drm_connector *connector ; struct drm_encoder *encoder ; struct cdv_intel_dp *intel_dp ; char const *name ; int type ; void *tmp ; void *tmp___0 ; void *tmp___1 ; bool tmp___2 ; int ret ; struct edp_power_seq cur ; u32 pp_on ; u32 pp_off ; u32 pp_div ; u32 pwm_ctrl ; long tmp___3 ; long tmp___4 ; long tmp___5 ; long tmp___6 ; bool tmp___7 ; { name = (char const *)0; type = 10; tmp = kzalloc(152UL, 208U); gma_encoder = (struct gma_encoder *)tmp; if ((unsigned long )gma_encoder == (unsigned long )((struct gma_encoder *)0)) { return; } else { } tmp___0 = kzalloc(944UL, 208U); gma_connector = (struct gma_connector *)tmp___0; if ((unsigned long )gma_connector == (unsigned long )((struct gma_connector *)0)) { goto err_connector; } else { } tmp___1 = kzalloc(2048UL, 208U); intel_dp = (struct cdv_intel_dp *)tmp___1; if ((unsigned long )intel_dp == (unsigned long )((struct cdv_intel_dp *)0)) { goto err_priv; } else { } if (output_reg == 410112) { tmp___2 = cdv_intel_dpc_is_edp(dev); if ((int )tmp___2) { type = 14; } else { } } else { } connector = & gma_connector->base; encoder = & gma_encoder->base; drm_connector_init(dev, connector, & cdv_intel_dp_connector_funcs, type); drm_encoder_init(dev, encoder, & cdv_intel_dp_enc_funcs, 2); gma_connector_attach_encoder(gma_connector, gma_encoder); if (type == 10) { gma_encoder->type = 9; } else { gma_encoder->type = 10; } gma_encoder->dev_priv = (void *)intel_dp; intel_dp->encoder = gma_encoder; intel_dp->output_reg = (uint32_t )output_reg; drm_encoder_helper_add(encoder, & cdv_intel_dp_helper_funcs); drm_connector_helper_add(connector, & cdv_intel_dp_connector_helper_funcs); connector->polled = 1U; connector->interlace_allowed = 0; connector->doublescan_allowed = 0; drm_connector_register(connector); switch (output_reg) { case 409856: name = "DPDDC-B"; gma_encoder->ddi_select = 32769U; goto ldv_42344; case 410112: name = "DPDDC-C"; gma_encoder->ddi_select = 32770U; goto ldv_42344; } ldv_42344: cdv_disable_intel_clock_gating(dev); cdv_intel_dp_i2c_init(gma_connector, gma_encoder, name); cdv_intel_dp_add_properties(connector); tmp___7 = is_edp(gma_encoder); if ((int )tmp___7) { pp_on = REGISTER_READ(dev, 397828U); pp_on = pp_on & 65535U; pp_on = pp_on | 2882338816U; REGISTER_WRITE(dev, 397828U, pp_on); pwm_ctrl = REGISTER_READ(dev, 397904U); pwm_ctrl = pwm_ctrl | 536870912U; REGISTER_WRITE(dev, 397904U, pwm_ctrl); pp_on = REGISTER_READ(dev, 397832U); pp_off = REGISTER_READ(dev, 397836U); pp_div = REGISTER_READ(dev, 397840U); cur.t1_t3 = (u16 )((pp_on & 536805376U) >> 16); cur.t8 = (unsigned int )((u16 )pp_on) & 8191U; cur.t9 = (unsigned int )((u16 )pp_off) & 8191U; cur.t10 = (u16 )((pp_off & 536805376U) >> 16); cur.t11_t12 = (unsigned int )((u16 )pp_div) & 31U; tmp___3 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___3 != 0L) { drm_ut_debug_printk("cdv_intel_dp_init", "cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", (int )cur.t1_t3, (int )cur.t8, (int )cur.t9, (int )cur.t10, (int )cur.t11_t12); } else { } intel_dp->panel_power_up_delay = (int )((unsigned int )cur.t1_t3 / 10U); intel_dp->backlight_on_delay = (int )((unsigned int )cur.t8 / 10U); intel_dp->backlight_off_delay = (int )((unsigned int )cur.t9 / 10U); intel_dp->panel_power_down_delay = (int )((unsigned int )cur.t10 / 10U); intel_dp->panel_power_cycle_delay = ((int )cur.t11_t12 + -1) * 100; tmp___4 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___4 != 0L) { drm_ut_debug_printk("cdv_intel_dp_init", "panel power up delay %d, power down delay %d, power cycle delay %d\n", intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, intel_dp->panel_power_cycle_delay); } else { } tmp___5 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___5 != 0L) { drm_ut_debug_printk("cdv_intel_dp_init", "backlight on delay %d, off delay %d\n", intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); } else { } cdv_intel_edp_panel_vdd_on(gma_encoder); ret = cdv_intel_dp_aux_native_read(gma_encoder, 0, (uint8_t *)(& intel_dp->dpcd), 4); cdv_intel_edp_panel_vdd_off(gma_encoder); if (ret == 0) { printk("\016[drm] failed to retrieve link info, disabling eDP\n"); cdv_intel_dp_encoder_destroy(encoder); cdv_intel_dp_destroy(connector); goto err_priv; } else { tmp___6 = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp___6 != 0L) { drm_ut_debug_printk("cdv_intel_dp_init", "DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n", (int )intel_dp->dpcd[0], (int )intel_dp->dpcd[1], (int )intel_dp->dpcd[2], (int )intel_dp->dpcd[3]); } else { } } } else { } return; err_priv: kfree((void const *)gma_connector); err_connector: kfree((void const *)gma_encoder); return; } } extern int ldv_probe_16(void) ; extern int ldv_probe_14(void) ; void ldv_initialize_i2c_algorithm_18(void) { void *tmp ; { tmp = ldv_init_zalloc(1936UL); i2c_dp_aux_algo_group0 = (struct i2c_adapter *)tmp; return; } } void ldv_initialize_drm_encoder_helper_funcs_17(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(96UL); cdv_intel_dp_helper_funcs_group0 = (struct drm_encoder *)tmp; tmp___0 = ldv_init_zalloc(208UL); cdv_intel_dp_helper_funcs_group1 = (struct drm_display_mode *)tmp___0; return; } } void ldv_initialize_drm_connector_funcs_16(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); cdv_intel_dp_connector_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_initialize_drm_connector_helper_funcs_15(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); cdv_intel_dp_connector_helper_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_main_exported_18(void) { int ldvarg16 ; struct i2c_msg *ldvarg17 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(16UL); ldvarg17 = (struct i2c_msg *)tmp; ldv_memset((void *)(& ldvarg16), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_18 == 1) { i2c_algo_dp_aux_xfer(i2c_dp_aux_algo_group0, ldvarg17, ldvarg16); ldv_state_variable_18 = 1; } else { } goto ldv_42375; case 1: ; if (ldv_state_variable_18 == 1) { i2c_algo_dp_aux_functionality(i2c_dp_aux_algo_group0); ldv_state_variable_18 = 1; } else { } goto ldv_42375; default: ldv_stop(); } ldv_42375: ; return; } } void ldv_main_exported_16(void) { uint32_t ldvarg19 ; struct drm_property *ldvarg22 ; void *tmp ; bool ldvarg23 ; uint32_t ldvarg20 ; uint64_t ldvarg21 ; int ldvarg24 ; int tmp___0 ; { tmp = ldv_init_zalloc(104UL); ldvarg22 = (struct drm_property *)tmp; ldv_memset((void *)(& ldvarg19), 0, 4UL); ldv_memset((void *)(& ldvarg23), 0, 1UL); ldv_memset((void *)(& ldvarg20), 0, 4UL); ldv_memset((void *)(& ldvarg21), 0, 8UL); ldv_memset((void *)(& ldvarg24), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_16 == 1) { drm_helper_connector_dpms(cdv_intel_dp_connector_funcs_group0, ldvarg24); ldv_state_variable_16 = 1; } else { } if (ldv_state_variable_16 == 2) { drm_helper_connector_dpms(cdv_intel_dp_connector_funcs_group0, ldvarg24); ldv_state_variable_16 = 2; } else { } goto ldv_42388; case 1: ; if (ldv_state_variable_16 == 1) { cdv_intel_dp_detect(cdv_intel_dp_connector_funcs_group0, (int )ldvarg23); ldv_state_variable_16 = 1; } else { } if (ldv_state_variable_16 == 2) { cdv_intel_dp_detect(cdv_intel_dp_connector_funcs_group0, (int )ldvarg23); ldv_state_variable_16 = 2; } else { } goto ldv_42388; case 2: ; if (ldv_state_variable_16 == 1) { cdv_intel_dp_set_property(cdv_intel_dp_connector_funcs_group0, ldvarg22, ldvarg21); ldv_state_variable_16 = 1; } else { } if (ldv_state_variable_16 == 2) { cdv_intel_dp_set_property(cdv_intel_dp_connector_funcs_group0, ldvarg22, ldvarg21); ldv_state_variable_16 = 2; } else { } goto ldv_42388; case 3: ; if (ldv_state_variable_16 == 2) { cdv_intel_dp_destroy(cdv_intel_dp_connector_funcs_group0); ldv_state_variable_16 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42388; case 4: ; if (ldv_state_variable_16 == 1) { drm_helper_probe_single_connector_modes(cdv_intel_dp_connector_funcs_group0, ldvarg20, ldvarg19); ldv_state_variable_16 = 1; } else { } if (ldv_state_variable_16 == 2) { drm_helper_probe_single_connector_modes(cdv_intel_dp_connector_funcs_group0, ldvarg20, ldvarg19); ldv_state_variable_16 = 2; } else { } goto ldv_42388; case 5: ; if (ldv_state_variable_16 == 1) { ldv_probe_16(); ldv_state_variable_16 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42388; default: ldv_stop(); } ldv_42388: ; return; } } void ldv_main_exported_17(void) { int ldvarg15 ; struct drm_display_mode *ldvarg13 ; void *tmp ; struct drm_display_mode *ldvarg14 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg13 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg14 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg15), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_17 == 1) { cdv_intel_dp_dpms(cdv_intel_dp_helper_funcs_group0, ldvarg15); ldv_state_variable_17 = 1; } else { } goto ldv_42402; case 1: ; if (ldv_state_variable_17 == 1) { cdv_intel_dp_mode_fixup(cdv_intel_dp_helper_funcs_group0, (struct drm_display_mode const *)ldvarg14, cdv_intel_dp_helper_funcs_group1); ldv_state_variable_17 = 1; } else { } goto ldv_42402; case 2: ; if (ldv_state_variable_17 == 1) { cdv_intel_dp_commit(cdv_intel_dp_helper_funcs_group0); ldv_state_variable_17 = 1; } else { } goto ldv_42402; case 3: ; if (ldv_state_variable_17 == 1) { cdv_intel_dp_mode_set(cdv_intel_dp_helper_funcs_group0, cdv_intel_dp_helper_funcs_group1, ldvarg13); ldv_state_variable_17 = 1; } else { } goto ldv_42402; case 4: ; if (ldv_state_variable_17 == 1) { cdv_intel_dp_prepare(cdv_intel_dp_helper_funcs_group0); ldv_state_variable_17 = 1; } else { } goto ldv_42402; default: ldv_stop(); } ldv_42402: ; return; } } void ldv_main_exported_15(void) { struct drm_display_mode *ldvarg187 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(208UL); ldvarg187 = (struct drm_display_mode *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_15 == 1) { cdv_intel_dp_get_modes(cdv_intel_dp_connector_helper_funcs_group0); ldv_state_variable_15 = 1; } else { } goto ldv_42413; case 1: ; if (ldv_state_variable_15 == 1) { cdv_intel_dp_mode_valid(cdv_intel_dp_connector_helper_funcs_group0, ldvarg187); ldv_state_variable_15 = 1; } else { } goto ldv_42413; case 2: ; if (ldv_state_variable_15 == 1) { gma_best_encoder(cdv_intel_dp_connector_helper_funcs_group0); ldv_state_variable_15 = 1; } else { } goto ldv_42413; default: ldv_stop(); } ldv_42413: ; return; } } void ldv_main_exported_14(void) { struct drm_encoder *ldvarg81 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(96UL); ldvarg81 = (struct drm_encoder *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_14 == 2) { cdv_intel_dp_encoder_destroy(ldvarg81); ldv_state_variable_14 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_42422; case 1: ; if (ldv_state_variable_14 == 1) { ldv_probe_14(); ldv_state_variable_14 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_42422; default: ldv_stop(); } ldv_42422: ; return; } } bool ldv_queue_work_on_401(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_402(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_403(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_404(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_405(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_415(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_417(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_416(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_419(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_418(struct workqueue_struct *ldv_func_arg1 ) ; void oaktrail_lvds_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) ; void oaktrail_hdmi_setup(struct drm_device *dev ) ; void oaktrail_hdmi_teardown(struct drm_device *dev ) ; void oaktrail_hdmi_save(struct drm_device *dev ) ; void oaktrail_hdmi_restore(struct drm_device *dev ) ; void oaktrail_hdmi_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) ; struct drm_crtc_helper_funcs const oaktrail_helper_funcs ; static int oaktrail_output_init(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; if (dev_priv->iLVDS_enable != 0U) { oaktrail_lvds_init(dev, & dev_priv->mode_dev); } else { dev_err((struct device const *)dev->dev, "DSI is not supported\n"); } if ((unsigned long )dev_priv->hdmi_priv != (unsigned long )((struct oaktrail_hdmi_dev *)0)) { oaktrail_hdmi_init(dev, & dev_priv->mode_dev); } else { } psb_intel_sdvo_init(dev, 397632); return (0); } } static int oaktrail_save_display_registers(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_save_area *regs ; struct psb_pipe *p ; int i ; u32 pp_stat ; { dev_priv = (struct drm_psb_private *)dev->dev_private; regs = & dev_priv->regs; p = (struct psb_pipe *)(& regs->pipe); regs->__annonCompField80.psb.saveDSPARB = ioread32((void *)dev_priv->vdc_reg + 458800U); regs->__annonCompField80.psb.saveDSPFW1 = ioread32((void *)dev_priv->vdc_reg + 458804U); regs->__annonCompField80.psb.saveDSPFW2 = ioread32((void *)dev_priv->vdc_reg + 458808U); regs->__annonCompField80.psb.saveDSPFW3 = ioread32((void *)dev_priv->vdc_reg + 458812U); regs->__annonCompField80.psb.saveDSPFW4 = ioread32((void *)dev_priv->vdc_reg + 458832U); regs->__annonCompField80.psb.saveDSPFW5 = ioread32((void *)dev_priv->vdc_reg + 458836U); regs->__annonCompField80.psb.saveDSPFW6 = ioread32((void *)dev_priv->vdc_reg + 458840U); regs->__annonCompField80.psb.saveCHICKENBIT = ioread32((void *)dev_priv->vdc_reg + 459776U); p->conf = ioread32((void *)dev_priv->vdc_reg + 458760U); p->src = ioread32((void *)dev_priv->vdc_reg + 393244U); p->fp0 = ioread32((void *)dev_priv->vdc_reg + 61504U); p->fp1 = ioread32((void *)dev_priv->vdc_reg + 61508U); p->dpll = ioread32((void *)dev_priv->vdc_reg + 61460U); p->htotal = ioread32((void *)dev_priv->vdc_reg + 393216U); p->hblank = ioread32((void *)dev_priv->vdc_reg + 393220U); p->hsync = ioread32((void *)dev_priv->vdc_reg + 393224U); p->vtotal = ioread32((void *)dev_priv->vdc_reg + 393228U); p->vblank = ioread32((void *)dev_priv->vdc_reg + 393232U); p->vsync = ioread32((void *)dev_priv->vdc_reg + 393236U); regs->__annonCompField80.psb.saveBCLRPAT_A = ioread32((void *)dev_priv->vdc_reg + 393248U); p->cntr = ioread32((void *)dev_priv->vdc_reg + 459136U); p->stride = ioread32((void *)dev_priv->vdc_reg + 459144U); p->addr = ioread32((void *)dev_priv->vdc_reg + 459140U); p->surf = ioread32((void *)dev_priv->vdc_reg + 459164U); p->linoff = ioread32((void *)dev_priv->vdc_reg + 459140U); p->tileoff = ioread32((void *)dev_priv->vdc_reg + 459172U); regs->__annonCompField80.psb.saveDSPACURSOR_CTRL = ioread32((void *)dev_priv->vdc_reg + 458880U); regs->__annonCompField80.psb.saveDSPACURSOR_BASE = ioread32((void *)dev_priv->vdc_reg + 458884U); regs->__annonCompField80.psb.saveDSPACURSOR_POS = ioread32((void *)dev_priv->vdc_reg + 458888U); i = 0; goto ldv_41834; ldv_41833: p->palette[i] = ioread32((void *)dev_priv->vdc_reg + (unsigned long )((i << 2) + 40960)); i = i + 1; ldv_41834: ; if (i <= 255) { goto ldv_41833; } else { } if ((unsigned long )dev_priv->hdmi_priv != (unsigned long )((struct oaktrail_hdmi_dev *)0)) { oaktrail_hdmi_save(dev); } else { } regs->__annonCompField80.psb.savePERF_MODE = ioread32((void *)dev_priv->vdc_reg + 8436U); regs->__annonCompField80.psb.savePP_CONTROL = ioread32((void *)dev_priv->vdc_reg + 397828U); regs->__annonCompField80.psb.savePFIT_PGM_RATIOS = ioread32((void *)dev_priv->vdc_reg + 397876U); regs->__annonCompField80.psb.savePFIT_AUTO_RATIOS = ioread32((void *)dev_priv->vdc_reg + 397880U); regs->saveBLC_PWM_CTL = ioread32((void *)dev_priv->vdc_reg + 397908U); regs->saveBLC_PWM_CTL2 = ioread32((void *)dev_priv->vdc_reg + 397904U); regs->__annonCompField80.psb.saveLVDS = ioread32((void *)dev_priv->vdc_reg + 397696U); regs->__annonCompField80.psb.savePFIT_CONTROL = ioread32((void *)dev_priv->vdc_reg + 397872U); regs->__annonCompField80.psb.savePP_ON_DELAYS = ioread32((void *)dev_priv->vdc_reg + 397832U); regs->__annonCompField80.psb.savePP_OFF_DELAYS = ioread32((void *)dev_priv->vdc_reg + 397836U); regs->__annonCompField80.psb.savePP_DIVISOR = ioread32((void *)dev_priv->vdc_reg + 397840U); regs->__annonCompField80.psb.saveOV_OVADD = ioread32((void *)dev_priv->vdc_reg + 196608U); regs->__annonCompField80.psb.saveOV_OGAMC0 = ioread32((void *)dev_priv->vdc_reg + 196644U); regs->__annonCompField80.psb.saveOV_OGAMC1 = ioread32((void *)dev_priv->vdc_reg + 196640U); regs->__annonCompField80.psb.saveOV_OGAMC2 = ioread32((void *)dev_priv->vdc_reg + 196636U); regs->__annonCompField80.psb.saveOV_OGAMC3 = ioread32((void *)dev_priv->vdc_reg + 196632U); regs->__annonCompField80.psb.saveOV_OGAMC4 = ioread32((void *)dev_priv->vdc_reg + 196628U); regs->__annonCompField80.psb.saveOV_OGAMC5 = ioread32((void *)dev_priv->vdc_reg + 196624U); regs->__annonCompField80.psb.saveHISTOGRAM_INT_CONTROL_REG = ioread32((void *)dev_priv->vdc_reg + 397928U); regs->__annonCompField80.psb.saveHISTOGRAM_LOGIC_CONTROL_REG = ioread32((void *)dev_priv->vdc_reg + 397920U); regs->__annonCompField80.psb.savePWM_CONTROL_LOGIC = ioread32((void *)dev_priv->vdc_reg + 397904U); if (dev_priv->iLVDS_enable != 0U) { iowrite32(0U, (void *)dev_priv->vdc_reg + 397828U); ldv_41836: pp_stat = ioread32((void *)dev_priv->vdc_reg + 397824U); if ((int )pp_stat < 0) { goto ldv_41836; } else { } iowrite32(1476395008U, (void *)dev_priv->vdc_reg + 459136U); iowrite32(0U, (void *)dev_priv->vdc_reg + 459164U); msleep(4U); iowrite32(0U, (void *)dev_priv->vdc_reg + 458760U); msleep(8U); iowrite32(0U, (void *)dev_priv->vdc_reg + 61460U); } else { } return (0); } } static int oaktrail_restore_display_registers(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct psb_save_area *regs ; struct psb_pipe *p ; u32 pp_stat ; int i ; { dev_priv = (struct drm_psb_private *)dev->dev_private; regs = & dev_priv->regs; p = (struct psb_pipe *)(& regs->pipe); iowrite32(regs->__annonCompField80.psb.saveDSPARB, (void *)dev_priv->vdc_reg + 458800U); iowrite32(regs->__annonCompField80.psb.saveDSPFW1, (void *)dev_priv->vdc_reg + 458804U); iowrite32(regs->__annonCompField80.psb.saveDSPFW2, (void *)dev_priv->vdc_reg + 458808U); iowrite32(regs->__annonCompField80.psb.saveDSPFW3, (void *)dev_priv->vdc_reg + 458812U); iowrite32(regs->__annonCompField80.psb.saveDSPFW4, (void *)dev_priv->vdc_reg + 458832U); iowrite32(regs->__annonCompField80.psb.saveDSPFW5, (void *)dev_priv->vdc_reg + 458836U); iowrite32(regs->__annonCompField80.psb.saveDSPFW6, (void *)dev_priv->vdc_reg + 458840U); iowrite32(regs->__annonCompField80.psb.saveCHICKENBIT, (void *)dev_priv->vdc_reg + 459776U); iowrite32(2147483648U, (void *)dev_priv->vdc_reg + 463872U); iowrite32(p->fp0, (void *)dev_priv->vdc_reg + 61504U); iowrite32(p->fp1, (void *)dev_priv->vdc_reg + 61508U); iowrite32(p->dpll, (void *)dev_priv->vdc_reg + 61460U); __const_udelay(644250UL); iowrite32(p->htotal, (void *)dev_priv->vdc_reg + 393216U); iowrite32(p->hblank, (void *)dev_priv->vdc_reg + 393220U); iowrite32(p->hsync, (void *)dev_priv->vdc_reg + 393224U); iowrite32(p->vtotal, (void *)dev_priv->vdc_reg + 393228U); iowrite32(p->vblank, (void *)dev_priv->vdc_reg + 393232U); iowrite32(p->vsync, (void *)dev_priv->vdc_reg + 393236U); iowrite32(p->src, (void *)dev_priv->vdc_reg + 393244U); iowrite32(regs->__annonCompField80.psb.saveBCLRPAT_A, (void *)dev_priv->vdc_reg + 393248U); iowrite32(regs->__annonCompField80.psb.savePERF_MODE, (void *)dev_priv->vdc_reg + 8436U); if (dev_priv->iLVDS_enable != 0U) { iowrite32(p->conf, (void *)dev_priv->vdc_reg + 458760U); } else { } iowrite32(p->linoff, (void *)dev_priv->vdc_reg + 459140U); iowrite32(p->stride, (void *)dev_priv->vdc_reg + 459144U); iowrite32(p->tileoff, (void *)dev_priv->vdc_reg + 459172U); iowrite32(p->cntr, (void *)dev_priv->vdc_reg + 459136U); iowrite32(p->surf, (void *)dev_priv->vdc_reg + 459164U); iowrite32(regs->__annonCompField80.psb.saveDSPACURSOR_CTRL, (void *)dev_priv->vdc_reg + 458880U); iowrite32(regs->__annonCompField80.psb.saveDSPACURSOR_POS, (void *)dev_priv->vdc_reg + 458888U); iowrite32(regs->__annonCompField80.psb.saveDSPACURSOR_BASE, (void *)dev_priv->vdc_reg + 458884U); i = 0; goto ldv_41847; ldv_41846: iowrite32(p->palette[i], (void *)dev_priv->vdc_reg + (unsigned long )((i << 2) + 40960)); i = i + 1; ldv_41847: ; if (i <= 255) { goto ldv_41846; } else { } if ((unsigned long )dev_priv->hdmi_priv != (unsigned long )((struct oaktrail_hdmi_dev *)0)) { oaktrail_hdmi_restore(dev); } else { } if (dev_priv->iLVDS_enable != 0U) { iowrite32(regs->saveBLC_PWM_CTL2, (void *)dev_priv->vdc_reg + 397904U); iowrite32(regs->__annonCompField80.psb.saveLVDS, (void *)dev_priv->vdc_reg + 397696U); iowrite32(regs->__annonCompField80.psb.savePFIT_CONTROL, (void *)dev_priv->vdc_reg + 397872U); iowrite32(regs->__annonCompField80.psb.savePFIT_PGM_RATIOS, (void *)dev_priv->vdc_reg + 397876U); iowrite32(regs->__annonCompField80.psb.savePFIT_AUTO_RATIOS, (void *)dev_priv->vdc_reg + 397880U); iowrite32(regs->saveBLC_PWM_CTL, (void *)dev_priv->vdc_reg + 397908U); iowrite32(regs->__annonCompField80.psb.savePP_ON_DELAYS, (void *)dev_priv->vdc_reg + 397832U); iowrite32(regs->__annonCompField80.psb.savePP_OFF_DELAYS, (void *)dev_priv->vdc_reg + 397836U); iowrite32(regs->__annonCompField80.psb.savePP_DIVISOR, (void *)dev_priv->vdc_reg + 397840U); iowrite32(regs->__annonCompField80.psb.savePP_CONTROL, (void *)dev_priv->vdc_reg + 397828U); } else { } ldv_41849: pp_stat = ioread32((void *)dev_priv->vdc_reg + 397824U); if ((pp_stat & 134217728U) != 0U) { goto ldv_41849; } else { } ldv_41851: pp_stat = ioread32((void *)dev_priv->vdc_reg + 397824U); if ((pp_stat & 268435456U) != 0U) { goto ldv_41851; } else { } iowrite32(regs->__annonCompField80.psb.saveOV_OVADD, (void *)dev_priv->vdc_reg + 196608U); iowrite32(regs->__annonCompField80.psb.saveOV_OGAMC0, (void *)dev_priv->vdc_reg + 196644U); iowrite32(regs->__annonCompField80.psb.saveOV_OGAMC1, (void *)dev_priv->vdc_reg + 196640U); iowrite32(regs->__annonCompField80.psb.saveOV_OGAMC2, (void *)dev_priv->vdc_reg + 196636U); iowrite32(regs->__annonCompField80.psb.saveOV_OGAMC3, (void *)dev_priv->vdc_reg + 196632U); iowrite32(regs->__annonCompField80.psb.saveOV_OGAMC4, (void *)dev_priv->vdc_reg + 196628U); iowrite32(regs->__annonCompField80.psb.saveOV_OGAMC5, (void *)dev_priv->vdc_reg + 196624U); iowrite32(regs->__annonCompField80.psb.saveHISTOGRAM_INT_CONTROL_REG, (void *)dev_priv->vdc_reg + 397928U); iowrite32(regs->__annonCompField80.psb.saveHISTOGRAM_LOGIC_CONTROL_REG, (void *)dev_priv->vdc_reg + 397920U); iowrite32(regs->__annonCompField80.psb.savePWM_CONTROL_LOGIC, (void *)dev_priv->vdc_reg + 397904U); return (0); } } static int oaktrail_power_down(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 pwr_mask ; u32 pwr_sts ; { dev_priv = (struct drm_psb_private *)dev->dev_private; pwr_mask = 12U; outl(pwr_mask, (int )(dev_priv->ospm_base + 32U)); ldv_41860: pwr_sts = inl((int )(dev_priv->ospm_base + 48U)); if ((pwr_sts & pwr_mask) == pwr_mask) { goto ldv_41859; } else { __const_udelay(42950UL); } goto ldv_41860; ldv_41859: ; return (0); } } static int oaktrail_power_up(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 pwr_mask ; u32 pwr_sts ; u32 pwr_cnt ; { dev_priv = (struct drm_psb_private *)dev->dev_private; pwr_mask = 12U; pwr_cnt = inl((int )(dev_priv->ospm_base + 32U)); pwr_cnt = ~ pwr_mask & pwr_cnt; outl(pwr_cnt, (int )(dev_priv->ospm_base + 32U)); ldv_41869: pwr_sts = inl((int )(dev_priv->ospm_base + 48U)); if ((pwr_sts & pwr_mask) == 0U) { goto ldv_41868; } else { __const_udelay(42950UL); } goto ldv_41869; ldv_41868: ; return (0); } } static struct psb_offset const oaktrail_regmap[2U] = { {61504U, 61508U, 459136U, 458760U, 393244U, 61460U, 0U, 393216U, 393220U, 393224U, 393228U, 393232U, 393236U, 459144U, 459152U, 459148U, 459164U, 459164U, 459164U, 458788U, 459140U, 459172U, 40960U}, {24648U, 24652U, 463232U, 462856U, 397340U, 24600U, 0U, 397312U, 397316U, 397320U, 397324U, 397328U, 397332U, 463240U, 463248U, 463244U, 463260U, 463236U, 463236U, 462884U, 463236U, 463268U, 43008U}}; static int oaktrail_chip_setup(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; int ret ; int tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = pci_enable_msi_exact(dev->pdev, 1); if (tmp != 0) { dev_warn((struct device const *)dev->dev, "Enabling MSI failed!\n"); } else { } dev_priv->regmap = (struct psb_offset const *)(& oaktrail_regmap); ret = mid_chip_setup(dev); if (ret < 0) { return (ret); } else { } if (! dev_priv->has_gct) { psb_intel_opregion_init(dev); psb_intel_init_bios(dev); } else { } gma_intel_setup_gmbus(dev); oaktrail_hdmi_setup(dev); return (0); } } static void oaktrail_teardown(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; { dev_priv = (struct drm_psb_private *)dev->dev_private; gma_intel_teardown_gmbus(dev); oaktrail_hdmi_teardown(dev); if (! dev_priv->has_gct) { psb_intel_destroy_bios(dev); } else { } return; } } struct psb_ops const oaktrail_chip_ops = {"Oaktrail", 1U, 2, 2, 524288, 2, 1, 2, 0, & oaktrail_helper_funcs, & psb_intel_crtc_funcs, 0, & oaktrail_chip_setup, & oaktrail_teardown, 0, & oaktrail_output_init, 0, 0, 0, & oaktrail_save_display_registers, & oaktrail_restore_display_registers, & oaktrail_power_up, & oaktrail_power_down, 0, 0, 0, 1}; void ldv_initialize_psb_ops_13(void) { void *tmp ; { tmp = ldv_init_zalloc(3320UL); oaktrail_chip_ops_group0 = (struct drm_device *)tmp; return; } } void ldv_main_exported_13(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ; if (ldv_state_variable_13 == 1) { oaktrail_teardown(oaktrail_chip_ops_group0); ldv_state_variable_13 = 1; } else { } goto ldv_41888; case 1: ; if (ldv_state_variable_13 == 1) { oaktrail_chip_setup(oaktrail_chip_ops_group0); ldv_state_variable_13 = 1; } else { } goto ldv_41888; case 2: ; if (ldv_state_variable_13 == 1) { oaktrail_save_display_registers(oaktrail_chip_ops_group0); ldv_state_variable_13 = 1; } else { } goto ldv_41888; case 3: ; if (ldv_state_variable_13 == 1) { oaktrail_restore_display_registers(oaktrail_chip_ops_group0); ldv_state_variable_13 = 1; } else { } goto ldv_41888; case 4: ; if (ldv_state_variable_13 == 1) { oaktrail_power_down(oaktrail_chip_ops_group0); ldv_state_variable_13 = 1; } else { } goto ldv_41888; case 5: ; if (ldv_state_variable_13 == 1) { oaktrail_output_init(oaktrail_chip_ops_group0); ldv_state_variable_13 = 1; } else { } goto ldv_41888; case 6: ; if (ldv_state_variable_13 == 1) { oaktrail_power_up(oaktrail_chip_ops_group0); ldv_state_variable_13 = 1; } else { } goto ldv_41888; default: ldv_stop(); } ldv_41888: ; return; } } bool ldv_queue_work_on_415(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_416(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_417(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_418(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_419(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_429(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_431(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_430(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_433(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_432(struct workqueue_struct *ldv_func_arg1 ) ; int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode , int x , int y , struct drm_framebuffer *old_fb ) ; void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc , int mode ) ; static bool mrst_lvds_find_best_pll(struct gma_limit_t const *limit , struct drm_crtc *crtc , int target , int refclk , struct gma_clock_t *best_clock ) ; static bool mrst_sdvo_find_best_pll(struct gma_limit_t const *limit , struct drm_crtc *crtc , int target , int refclk , struct gma_clock_t *best_clock ) ; static struct gma_limit_t const mrst_limits[4U] = { {{19750, 120000}, {0, 0}, {0, 0}, {20, 34}, {0, 0}, {0, 0}, {0, 0}, {2, 8}, {0, 0, 0}, & mrst_lvds_find_best_pll}, {{19750, 120000}, {0, 0}, {0, 0}, {12, 20}, {0, 0}, {0, 0}, {0, 0}, {2, 7}, {0, 0, 0}, & mrst_lvds_find_best_pll}, {{19750, 120000}, {0, 0}, {0, 0}, {10, 17}, {0, 0}, {0, 0}, {0, 0}, {2, 8}, {0, 0, 0}, & mrst_lvds_find_best_pll}, {{0, 0}, {1400000, 2800000}, {3, 7}, {80, 137}, {0, 0}, {0, 0}, {0, 0}, {1, 2}, {200000, 10, 10}, & mrst_sdvo_find_best_pll}}; static u32 const oaktrail_m_converts[26U] = { 43U, 21U, 42U, 53U, 26U, 13U, 38U, 51U, 25U, 44U, 54U, 59U, 29U, 46U, 55U, 27U, 45U, 22U, 11U, 37U, 18U, 9U, 36U, 50U, 57U, 28U}; static struct gma_limit_t const *mrst_limit(struct drm_crtc *crtc , int refclk ) { struct gma_limit_t const *limit ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; bool tmp ; bool tmp___0 ; bool tmp___1 ; { limit = (struct gma_limit_t const *)0; dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; tmp___0 = gma_pipe_has_type(crtc, 4); if ((int )tmp___0) { goto _L; } else { tmp___1 = gma_pipe_has_type(crtc, 7); if ((int )tmp___1) { _L: /* CIL Label */ switch (dev_priv->core_freq) { case 100U: limit = (struct gma_limit_t const *)(& mrst_limits); goto ldv_41692; case 166U: limit = (struct gma_limit_t const *)(& mrst_limits) + 1UL; goto ldv_41692; case 200U: limit = (struct gma_limit_t const *)(& mrst_limits) + 2UL; goto ldv_41692; } ldv_41692: ; } else { tmp = gma_pipe_has_type(crtc, 3); if ((int )tmp) { limit = (struct gma_limit_t const *)(& mrst_limits) + 3UL; } else { limit = (struct gma_limit_t const *)0; dev_err((struct device const *)dev->dev, "mrst_limit Wrong display type.\n"); } } } return (limit); } } static void mrst_lvds_clock(int refclk , struct gma_clock_t *clock ) { { clock->dot = (clock->m * refclk) / (clock->p1 * 14); return; } } static void mrst_print_pll(struct gma_clock_t *clock ) { long tmp ; { tmp = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("mrst_print_pll", "dotclock=%d, m=%d, m1=%d, m2=%d, n=%d, p1=%d, p2=%d\n", clock->dot, clock->m, clock->m1, clock->m2, clock->n, clock->p1, clock->p2); } else { } return; } } static bool mrst_sdvo_find_best_pll(struct gma_limit_t const *limit , struct drm_crtc *crtc , int target , int refclk , struct gma_clock_t *best_clock ) { struct gma_clock_t clock ; u32 target_vco ; u32 actual_freq ; s32 freq_error ; s32 min_error ; { min_error = 100000; memset((void *)best_clock, 0, 36UL); clock.m = limit->m.min; goto ldv_41724; ldv_41723: clock.n = limit->n.min; goto ldv_41720; ldv_41719: clock.p1 = limit->p1.min; goto ldv_41718; ldv_41717: clock.p = clock.p1 * (int )limit->p2.p2_slow; target_vco = (u32 )(clock.p * target); if ((u32 )limit->vco.max < target_vco) { goto ldv_41715; } else { } if ((u32 )limit->vco.min > target_vco) { goto ldv_41716; } else { } actual_freq = (u32 )((clock.m * refclk) / (clock.n * clock.p)); freq_error = (s32 )(10000U - (u32 )(target * 10000) / actual_freq); if (- min_error > freq_error) { goto ldv_41715; } else { } if (freq_error < 0) { freq_error = - freq_error; } else { } if (freq_error < min_error) { min_error = freq_error; *best_clock = clock; } else { } ldv_41716: clock.p1 = clock.p1 + 1; ldv_41718: ; if (clock.p1 <= (int )limit->p1.max) { goto ldv_41717; } else { } ldv_41715: clock.n = clock.n + 1; ldv_41720: ; if (clock.n <= (int )limit->n.max) { goto ldv_41719; } else { } if (min_error == 0) { goto ldv_41722; } else { } clock.m = clock.m + 1; ldv_41724: ; if (clock.m <= (int )limit->m.max) { goto ldv_41723; } else { } ldv_41722: ; return (min_error == 0); } } static bool mrst_lvds_find_best_pll(struct gma_limit_t const *limit , struct drm_crtc *crtc , int target , int refclk , struct gma_clock_t *best_clock ) { struct gma_clock_t clock ; int err ; int this_err ; long ret ; int __x___0 ; { err = target; memset((void *)best_clock, 0, 36UL); clock.m = limit->m.min; goto ldv_41743; ldv_41742: clock.p1 = limit->p1.min; goto ldv_41740; ldv_41739: mrst_lvds_clock(refclk, & clock); __x___0 = clock.dot - target; ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); this_err = (int )ret; if (this_err < err) { *best_clock = clock; err = this_err; } else { } clock.p1 = clock.p1 + 1; ldv_41740: ; if (clock.p1 <= (int )limit->p1.max) { goto ldv_41739; } else { } clock.m = clock.m + 1; ldv_41743: ; if (clock.m <= (int )limit->m.max) { goto ldv_41742; } else { } return (err != target); } } static void oaktrail_crtc_dpms(struct drm_crtc *crtc , int mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; int pipe ; struct psb_offset const *map ; u32 temp ; int i ; int need_aux ; bool tmp ; bool tmp___0 ; bool tmp___1 ; int tmp___2 ; uint32_t tmp___3 ; uint32_t tmp___4 ; uint32_t tmp___5 ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; tmp = gma_pipe_has_type(crtc, 3); need_aux = (int )tmp; tmp___0 = gma_pipe_has_type(crtc, 6); if ((int )tmp___0) { oaktrail_crtc_hdmi_dpms(crtc, mode); return; } else { } tmp___1 = gma_power_begin(dev, 1); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return; } else { } switch (mode) { case 0: ; case 1: ; case 2: i = 0; goto ldv_41763; ldv_41762: temp = REGISTER_READ_WITH_AUX(dev, map->dpll, i); if ((int )temp >= 0) { REGISTER_WRITE_WITH_AUX(dev, map->dpll, temp, i); REGISTER_READ_WITH_AUX(dev, map->dpll, i); __const_udelay(644250UL); REGISTER_WRITE_WITH_AUX(dev, map->dpll, temp | 2147483648U, i); REGISTER_READ_WITH_AUX(dev, map->dpll, i); __const_udelay(644250UL); REGISTER_WRITE_WITH_AUX(dev, map->dpll, temp | 2147483648U, i); REGISTER_READ_WITH_AUX(dev, map->dpll, i); __const_udelay(644250UL); } else { } temp = REGISTER_READ_WITH_AUX(dev, map->conf, i); if ((int )temp >= 0) { REGISTER_WRITE_WITH_AUX(dev, map->conf, temp | 2147483648U, i); } else { } temp = REGISTER_READ_WITH_AUX(dev, map->cntr, i); if ((int )temp >= 0) { REGISTER_WRITE_WITH_AUX(dev, map->cntr, temp | 2147483648U, i); tmp___3 = REGISTER_READ_WITH_AUX(dev, map->base, i); REGISTER_WRITE_WITH_AUX(dev, map->base, tmp___3, i); } else { } i = i + 1; ldv_41763: ; if (i <= need_aux) { goto ldv_41762; } else { } gma_crtc_load_lut(crtc); goto ldv_41765; case 3: i = 0; goto ldv_41768; ldv_41767: REGISTER_WRITE_WITH_AUX(dev, 463872U, 2147483648U, i); temp = REGISTER_READ_WITH_AUX(dev, map->cntr, i); if ((int )temp < 0) { REGISTER_WRITE_WITH_AUX(dev, map->cntr, temp & 2147483647U, i); tmp___4 = REGISTER_READ(dev, map->base); REGISTER_WRITE_WITH_AUX(dev, map->base, tmp___4, i); REGISTER_READ_WITH_AUX(dev, map->base, i); } else { } temp = REGISTER_READ_WITH_AUX(dev, map->conf, i); if ((int )temp < 0) { REGISTER_WRITE_WITH_AUX(dev, map->conf, temp & 2147483647U, i); REGISTER_READ_WITH_AUX(dev, map->conf, i); } else { } gma_wait_for_vblank(dev); temp = REGISTER_READ_WITH_AUX(dev, map->dpll, i); if ((int )temp < 0) { REGISTER_WRITE_WITH_AUX(dev, map->dpll, temp & 2147483647U, i); REGISTER_READ_WITH_AUX(dev, map->dpll, i); } else { } __const_udelay(644250UL); i = i + 1; ldv_41768: ; if (i <= need_aux) { goto ldv_41767; } else { } goto ldv_41765; } ldv_41765: REGISTER_WRITE(dev, 458800U, 16256U); REGISTER_WRITE(dev, 458804U, 1066337284U); REGISTER_WRITE(dev, 458808U, 67374852U); REGISTER_WRITE(dev, 458812U, 0U); REGISTER_WRITE(dev, 458832U, 67372036U); REGISTER_WRITE(dev, 458836U, 67372036U); REGISTER_WRITE(dev, 458840U, 120U); tmp___5 = REGISTER_READ(dev, 459776U); REGISTER_WRITE(dev, 459776U, tmp___5 | 49216U); gma_power_end(dev); return; } } static int oaktrail_panel_fitter_pipe(struct drm_device *dev ) { u32 pfit_control ; { pfit_control = REGISTER_READ(dev, 397872U); if ((int )pfit_control >= 0) { return (-1); } else { } return ((int )(pfit_control >> 29) & 3); } } static int oaktrail_crtc_mode_set(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode , int x , int y , struct drm_framebuffer *old_fb ) { struct drm_device *dev ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct drm_psb_private *dev_priv ; int pipe ; struct psb_offset const *map ; int refclk ; struct gma_clock_t clock ; struct gma_limit_t const *limit ; u32 dpll ; u32 fp ; u32 dspcntr ; u32 pipeconf ; bool ok ; bool is_sdvo ; bool is_lvds ; bool is_mipi ; struct drm_mode_config *mode_config ; struct gma_encoder *gma_encoder ; uint64_t scalingType ; struct drm_connector *connector ; int i ; int need_aux ; bool tmp ; int tmp___0 ; bool tmp___1 ; bool tmp___2 ; int tmp___3 ; struct list_head const *__mptr___0 ; struct list_head const *__mptr___1 ; int tmp___4 ; int offsetX ; int offsetY ; struct drm_crtc_helper_funcs const *crtc_funcs ; int sdvo_pixel_multiply ; { dev = crtc->dev; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; dev_priv = (struct drm_psb_private *)dev->dev_private; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; refclk = 0; dpll = 0U; fp = 0U; is_sdvo = 0; is_lvds = 0; is_mipi = 0; mode_config = & dev->mode_config; gma_encoder = (struct gma_encoder *)0; scalingType = 1ULL; tmp = gma_pipe_has_type(crtc, 3); need_aux = (int )tmp; tmp___1 = gma_pipe_has_type(crtc, 6); if ((int )tmp___1) { tmp___0 = oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb); return (tmp___0); } else { } tmp___2 = gma_power_begin(dev, 1); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { return (0); } else { } memcpy((void *)(& gma_crtc->saved_mode), (void const *)mode, 208UL); memcpy((void *)(& gma_crtc->saved_adjusted_mode), (void const *)adjusted_mode, 208UL); __mptr___0 = (struct list_head const *)mode_config->connector_list.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; goto ldv_41816; ldv_41815: ; if ((unsigned long )connector->encoder == (unsigned long )((struct drm_encoder *)0) || (unsigned long )(connector->encoder)->crtc != (unsigned long )crtc) { goto ldv_41810; } else { } gma_encoder = gma_attached_encoder(connector); switch (gma_encoder->type) { case 4: is_lvds = 1; goto ldv_41812; case 3: is_sdvo = 1; goto ldv_41812; case 7: is_mipi = 1; goto ldv_41812; } ldv_41812: ; ldv_41810: __mptr___1 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___1 + 0xffffffffffffffe8UL; ldv_41816: ; if ((unsigned long )(& connector->head) != (unsigned long )(& mode_config->connector_list)) { goto ldv_41815; } else { } i = 0; goto ldv_41819; ldv_41818: REGISTER_WRITE_WITH_AUX(dev, 463872U, 2147483648U, i); i = i + 1; ldv_41819: ; if (i <= need_aux) { goto ldv_41818; } else { } tmp___4 = oaktrail_panel_fitter_pipe(dev); if (tmp___4 == pipe) { REGISTER_WRITE(dev, 397872U, 0U); } else { } i = 0; goto ldv_41822; ldv_41821: REGISTER_WRITE_WITH_AUX(dev, map->src, (uint32_t )(((mode->crtc_hdisplay + -1) << 16) | (mode->crtc_vdisplay + -1)), i); i = i + 1; ldv_41822: ; if (i <= need_aux) { goto ldv_41821; } else { } if ((unsigned long )gma_encoder != (unsigned long )((struct gma_encoder *)0)) { drm_object_property_get_value(& connector->base, dev->mode_config.scaling_mode_property, & scalingType); } else { } if (scalingType == 2ULL) { offsetX = 0; offsetY = 0; offsetX = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; offsetY = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; i = 0; goto ldv_41827; ldv_41826: REGISTER_WRITE_WITH_AUX(dev, map->htotal, (uint32_t )((mode->crtc_hdisplay + -1) | ((adjusted_mode->crtc_htotal + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->vtotal, (uint32_t )((mode->crtc_vdisplay + -1) | ((adjusted_mode->crtc_vtotal + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->hblank, (uint32_t )(((adjusted_mode->crtc_hblank_start - offsetX) + -1) | (((adjusted_mode->crtc_hblank_end - offsetX) + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->hsync, (uint32_t )(((adjusted_mode->crtc_hsync_start - offsetX) + -1) | (((adjusted_mode->crtc_hsync_end - offsetX) + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->vblank, (uint32_t )(((adjusted_mode->crtc_vblank_start - offsetY) + -1) | (((adjusted_mode->crtc_vblank_end - offsetY) + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->vsync, (uint32_t )(((adjusted_mode->crtc_vsync_start - offsetY) + -1) | (((adjusted_mode->crtc_vsync_end - offsetY) + -1) << 16)), i); i = i + 1; ldv_41827: ; if (i <= need_aux) { goto ldv_41826; } else { } } else { i = 0; goto ldv_41830; ldv_41829: REGISTER_WRITE_WITH_AUX(dev, map->htotal, (uint32_t )((adjusted_mode->crtc_hdisplay + -1) | ((adjusted_mode->crtc_htotal + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->vtotal, (uint32_t )((adjusted_mode->crtc_vdisplay + -1) | ((adjusted_mode->crtc_vtotal + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->hblank, (uint32_t )((adjusted_mode->crtc_hblank_start + -1) | ((adjusted_mode->crtc_hblank_end + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->hsync, (uint32_t )((adjusted_mode->crtc_hsync_start + -1) | ((adjusted_mode->crtc_hsync_end + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->vblank, (uint32_t )((adjusted_mode->crtc_vblank_start + -1) | ((adjusted_mode->crtc_vblank_end + -1) << 16)), i); REGISTER_WRITE_WITH_AUX(dev, map->vsync, (uint32_t )((adjusted_mode->crtc_vsync_start + -1) | ((adjusted_mode->crtc_vsync_end + -1) << 16)), i); i = i + 1; ldv_41830: ; if (i <= need_aux) { goto ldv_41829; } else { } } crtc_funcs = (struct drm_crtc_helper_funcs const *)crtc->helper_private; (*(crtc_funcs->mode_set_base))(crtc, x, y, old_fb); pipeconf = REGISTER_READ(dev, map->conf); dspcntr = REGISTER_READ(dev, map->cntr); dspcntr = dspcntr | 1073741824U; if (pipe == 0) { dspcntr = dspcntr; } else { dspcntr = dspcntr | 16777216U; } if ((int )is_mipi) { goto oaktrail_crtc_mode_set_exit; } else { } dpll = 0U; refclk = (int )is_sdvo ? 96000 : (int )(dev_priv->core_freq * 1000U); limit = mrst_limit(crtc, refclk); ok = (*(limit->find_pll))(limit, crtc, adjusted_mode->clock, refclk, & clock); if ((int )is_sdvo) { clock.p1 = (int )(1L << (clock.p1 + -1)); clock.m = clock.m + -2; clock.n = (int )(1L << (clock.n + -1)); } else { } if (! ok) { drm_err("Failed to find proper PLL settings"); } else { } mrst_print_pll(& clock); if ((int )is_sdvo) { fp = (u32 )((clock.n << 16) | clock.m); } else { fp = oaktrail_m_converts[clock.m + -10] << 8; } dpll = dpll | 268435456U; dpll = dpll | 2147483648U; if ((int )is_lvds) { dpll = dpll | 134217728U; } else { dpll = dpll | 67108864U; } if ((int )is_sdvo) { sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; dpll = dpll | 1073741824U; dpll = (u32 )((sdvo_pixel_multiply + -1) << 4) | dpll; } else { } if ((int )is_sdvo) { dpll = (u32 )(clock.p1 << 16) | dpll; } else { dpll = (u32 )((1 << (clock.p1 + -2)) << 17) | dpll; } dpll = dpll | 2147483648U; if ((int )dpll < 0) { i = 0; goto ldv_41836; ldv_41835: REGISTER_WRITE_WITH_AUX(dev, map->fp0, fp, i); REGISTER_WRITE_WITH_AUX(dev, map->dpll, dpll & 2147483647U, i); REGISTER_READ_WITH_AUX(dev, map->dpll, i); __const_udelay(644250UL); i = i + 1; ldv_41836: ; if (i <= need_aux) { goto ldv_41835; } else { } } else { } i = 0; goto ldv_41839; ldv_41838: REGISTER_WRITE_WITH_AUX(dev, map->fp0, fp, i); REGISTER_WRITE_WITH_AUX(dev, map->dpll, dpll, i); REGISTER_READ_WITH_AUX(dev, map->dpll, i); __const_udelay(644250UL); REGISTER_WRITE_WITH_AUX(dev, map->dpll, dpll, i); REGISTER_READ_WITH_AUX(dev, map->dpll, i); __const_udelay(644250UL); REGISTER_WRITE_WITH_AUX(dev, map->conf, pipeconf, i); REGISTER_READ_WITH_AUX(dev, map->conf, i); gma_wait_for_vblank(dev); REGISTER_WRITE_WITH_AUX(dev, map->cntr, dspcntr, i); gma_wait_for_vblank(dev); i = i + 1; ldv_41839: ; if (i <= need_aux) { goto ldv_41838; } else { } oaktrail_crtc_mode_set_exit: gma_power_end(dev); return (0); } } static int oaktrail_pipe_set_base(struct drm_crtc *crtc , int x , int y , struct drm_framebuffer *old_fb ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_crtc *gma_crtc ; struct drm_crtc const *__mptr ; struct psb_framebuffer *psbfb ; struct drm_framebuffer const *__mptr___0 ; int pipe ; struct psb_offset const *map ; unsigned long start ; unsigned long offset ; u32 dspcntr ; int ret ; struct _ddebug descriptor ; long tmp ; bool tmp___0 ; int tmp___1 ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_crtc const *)crtc; gma_crtc = (struct gma_crtc *)__mptr; __mptr___0 = (struct drm_framebuffer const *)(crtc->primary)->fb; psbfb = (struct psb_framebuffer *)__mptr___0; pipe = gma_crtc->pipe; map = dev_priv->regmap + (unsigned long )pipe; ret = 0; if ((unsigned long )(crtc->primary)->fb == (unsigned long )((struct drm_framebuffer *)0)) { descriptor.modname = "gma500_gfx"; descriptor.function = "oaktrail_pipe_set_base"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/oaktrail_crtc.c"; descriptor.format = "No FB bound\n"; descriptor.lineno = 612U; descriptor.flags = 0U; tmp = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "No FB bound\n"); } else { } return (0); } else { } tmp___0 = gma_power_begin(dev, 1); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return (0); } else { } start = (unsigned long )(psbfb->gtt)->offset; offset = (unsigned long )(((crtc->primary)->fb)->pitches[0] * (unsigned int )y + (unsigned int )((((crtc->primary)->fb)->bits_per_pixel / 8) * x)); REGISTER_WRITE(dev, map->stride, ((crtc->primary)->fb)->pitches[0]); dspcntr = REGISTER_READ(dev, map->cntr); dspcntr = dspcntr & 3288334335U; switch (((crtc->primary)->fb)->bits_per_pixel) { case 8: dspcntr = dspcntr | 134217728U; goto ldv_41864; case 16: ; if (((crtc->primary)->fb)->depth == 15U) { dspcntr = dspcntr | 268435456U; } else { dspcntr = dspcntr | 335544320U; } goto ldv_41864; case 24: ; case 32: dspcntr = dspcntr | 402653184U; goto ldv_41864; default: dev_err((struct device const *)dev->dev, "Unknown color depth\n"); ret = -22; goto pipe_set_base_exit; } ldv_41864: REGISTER_WRITE(dev, map->cntr, dspcntr); REGISTER_WRITE(dev, map->base, (uint32_t )offset); REGISTER_READ(dev, map->base); REGISTER_WRITE(dev, map->surf, (uint32_t )start); REGISTER_READ(dev, map->surf); pipe_set_base_exit: gma_power_end(dev); return (ret); } } struct drm_crtc_helper_funcs const oaktrail_helper_funcs = {& oaktrail_crtc_dpms, & gma_crtc_prepare, & gma_crtc_commit, & gma_crtc_mode_fixup, & oaktrail_crtc_mode_set, 0, & oaktrail_pipe_set_base, 0, 0, 0, 0, 0, 0, 0}; struct gma_clock_funcs const mrst_clock_funcs = {& mrst_lvds_clock, & mrst_limit, & gma_pll_is_valid}; void ldv_initialize_drm_crtc_helper_funcs_12(void) { void *tmp ; void *tmp___0 ; void *tmp___1 ; { tmp = ldv_init_zalloc(1160UL); oaktrail_helper_funcs_group0 = (struct drm_crtc *)tmp; tmp___0 = ldv_init_zalloc(168UL); oaktrail_helper_funcs_group1 = (struct drm_framebuffer *)tmp___0; tmp___1 = ldv_init_zalloc(208UL); oaktrail_helper_funcs_group2 = (struct drm_display_mode *)tmp___1; return; } } void ldv_initialize_gma_clock_funcs_11(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(1160UL); mrst_clock_funcs_group0 = (struct drm_crtc *)tmp; tmp___0 = ldv_init_zalloc(36UL); mrst_clock_funcs_group1 = (struct gma_clock_t *)tmp___0; return; } } void ldv_main_exported_11(void) { struct gma_limit_t *ldvarg107 ; void *tmp ; int ldvarg105 ; int ldvarg106 ; int tmp___0 ; { tmp = ldv_init_zalloc(88UL); ldvarg107 = (struct gma_limit_t *)tmp; ldv_memset((void *)(& ldvarg105), 0, 4UL); ldv_memset((void *)(& ldvarg106), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_11 == 1) { gma_pll_is_valid(mrst_clock_funcs_group0, (struct gma_limit_t const *)ldvarg107, mrst_clock_funcs_group1); ldv_state_variable_11 = 1; } else { } goto ldv_41885; case 1: ; if (ldv_state_variable_11 == 1) { mrst_lvds_clock(ldvarg106, mrst_clock_funcs_group1); ldv_state_variable_11 = 1; } else { } goto ldv_41885; case 2: ; if (ldv_state_variable_11 == 1) { mrst_limit(mrst_clock_funcs_group0, ldvarg105); ldv_state_variable_11 = 1; } else { } goto ldv_41885; default: ldv_stop(); } ldv_41885: ; return; } } void ldv_main_exported_12(void) { int ldvarg179 ; int ldvarg173 ; int ldvarg178 ; struct drm_display_mode *ldvarg176 ; void *tmp ; struct drm_display_mode *ldvarg174 ; void *tmp___0 ; int ldvarg175 ; int ldvarg177 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg176 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg174 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg179), 0, 4UL); ldv_memset((void *)(& ldvarg173), 0, 4UL); ldv_memset((void *)(& ldvarg178), 0, 4UL); ldv_memset((void *)(& ldvarg175), 0, 4UL); ldv_memset((void *)(& ldvarg177), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_12 == 1) { oaktrail_pipe_set_base(oaktrail_helper_funcs_group0, ldvarg179, ldvarg178, oaktrail_helper_funcs_group1); ldv_state_variable_12 = 1; } else { } goto ldv_41900; case 1: ; if (ldv_state_variable_12 == 1) { oaktrail_crtc_dpms(oaktrail_helper_funcs_group0, ldvarg177); ldv_state_variable_12 = 1; } else { } goto ldv_41900; case 2: ; if (ldv_state_variable_12 == 1) { gma_crtc_mode_fixup(oaktrail_helper_funcs_group0, (struct drm_display_mode const *)ldvarg176, oaktrail_helper_funcs_group2); ldv_state_variable_12 = 1; } else { } goto ldv_41900; case 3: ; if (ldv_state_variable_12 == 1) { gma_crtc_commit(oaktrail_helper_funcs_group0); ldv_state_variable_12 = 1; } else { } goto ldv_41900; case 4: ; if (ldv_state_variable_12 == 1) { oaktrail_crtc_mode_set(oaktrail_helper_funcs_group0, oaktrail_helper_funcs_group2, ldvarg174, ldvarg173, ldvarg175, oaktrail_helper_funcs_group1); ldv_state_variable_12 = 1; } else { } goto ldv_41900; case 5: ; if (ldv_state_variable_12 == 1) { gma_crtc_prepare(oaktrail_helper_funcs_group0); ldv_state_variable_12 = 1; } else { } goto ldv_41900; default: ldv_stop(); } ldv_41900: ; return; } } bool ldv_queue_work_on_429(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_430(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_431(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_432(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_433(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_443(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_445(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_444(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_447(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_446(struct workqueue_struct *ldv_func_arg1 ) ; extern struct i2c_adapter *i2c_get_adapter(int ) ; __inline static int pm_request_idle(struct device *dev ) { int tmp ; { tmp = __pm_runtime_idle(dev, 1); return (tmp); } } void oaktrail_lvds_i2c_init(struct drm_encoder *encoder ) ; static void oaktrail_lvds_set_power(struct drm_device *dev , struct gma_encoder *gma_encoder , bool on ) { u32 pp_status ; struct drm_psb_private *dev_priv ; bool tmp ; int tmp___0 ; uint32_t tmp___1 ; uint32_t tmp___2 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return; } else { } if ((int )on) { tmp___1 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___1 | 1U); ldv_41655: pp_status = REGISTER_READ(dev, 397824U); if ((pp_status & 3221225472U) == 1073741824U) { goto ldv_41655; } else { } dev_priv->is_lvds_on = 1; if ((unsigned long )(dev_priv->ops)->lvds_bl_power != (unsigned long )((void (*/* const */)(struct drm_device * , bool ))0)) { (*((dev_priv->ops)->lvds_bl_power))(dev, 1); } else { } } else { if ((unsigned long )(dev_priv->ops)->lvds_bl_power != (unsigned long )((void (*/* const */)(struct drm_device * , bool ))0)) { (*((dev_priv->ops)->lvds_bl_power))(dev, 0); } else { } tmp___2 = REGISTER_READ(dev, 397828U); REGISTER_WRITE(dev, 397828U, tmp___2 & 4294967294U); ldv_41657: pp_status = REGISTER_READ(dev, 397824U); if ((int )pp_status < 0) { goto ldv_41657; } else { } dev_priv->is_lvds_on = 0; pm_request_idle(& (dev->pdev)->dev); } gma_power_end(dev); return; } } static void oaktrail_lvds_dpms(struct drm_encoder *encoder , int mode ) { struct drm_device *dev ; struct gma_encoder *gma_encoder ; struct drm_encoder const *__mptr ; { dev = encoder->dev; __mptr = (struct drm_encoder const *)encoder; gma_encoder = (struct gma_encoder *)__mptr; if (mode == 0) { oaktrail_lvds_set_power(dev, gma_encoder, 1); } else { oaktrail_lvds_set_power(dev, gma_encoder, 0); } return; } } static void oaktrail_lvds_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct psb_intel_mode_device *mode_dev ; struct drm_mode_config *mode_config ; struct drm_connector *connector ; struct drm_crtc *crtc ; u32 lvds_port ; uint64_t v ; bool tmp ; int tmp___0 ; uint32_t tmp___1 ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; mode_dev = & dev_priv->mode_dev; mode_config = & dev->mode_config; connector = (struct drm_connector *)0; crtc = encoder->crtc; v = 1ULL; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return; } else { } tmp___1 = REGISTER_READ(dev, 397696U); lvds_port = (tmp___1 & 1073709055U) | 2147516416U; if ((int )mode_dev->panel_wants_dither || (unsigned int )*((unsigned char *)dev_priv + 864UL) != 0U) { lvds_port = lvds_port | 33554432U; } else { } REGISTER_WRITE(dev, 397696U, lvds_port); __mptr = (struct list_head const *)mode_config->connector_list.next; connector = (struct drm_connector *)__mptr + 0xffffffffffffffe8UL; goto ldv_41686; ldv_41685: ; if ((unsigned long )connector->encoder == (unsigned long )((struct drm_encoder *)0) || (unsigned long )(connector->encoder)->crtc != (unsigned long )crtc) { } else { } __mptr___0 = (struct list_head const *)connector->head.next; connector = (struct drm_connector *)__mptr___0 + 0xffffffffffffffe8UL; ldv_41686: ; if ((unsigned long )(& connector->head) != (unsigned long )(& mode_config->connector_list)) { goto ldv_41685; } else { } if ((unsigned long )connector == (unsigned long )((struct drm_connector *)0)) { drm_err("Couldn\'t find connector when setting mode"); return; } else { } drm_object_property_get_value(& connector->base, dev->mode_config.scaling_mode_property, & v); if (v == 2ULL) { REGISTER_WRITE(dev, 397872U, 0U); } else if (v == 3ULL) { if (mode->vdisplay != adjusted_mode->crtc_vdisplay || mode->hdisplay != adjusted_mode->crtc_hdisplay) { if (adjusted_mode->crtc_hdisplay * mode->vdisplay == mode->hdisplay * adjusted_mode->crtc_vdisplay) { REGISTER_WRITE(dev, 397872U, 2147483648U); } else if (adjusted_mode->crtc_hdisplay * mode->vdisplay > mode->hdisplay * adjusted_mode->crtc_vdisplay) { REGISTER_WRITE(dev, 397872U, 2281701376U); } else { REGISTER_WRITE(dev, 397872U, 2348810240U); } } else { REGISTER_WRITE(dev, 397872U, 2147483648U); } } else { REGISTER_WRITE(dev, 397872U, 2147483648U); } gma_power_end(dev); return; } } static void oaktrail_lvds_prepare(struct drm_encoder *encoder ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_encoder *gma_encoder ; struct drm_encoder const *__mptr ; struct psb_intel_mode_device *mode_dev ; bool tmp ; int tmp___0 ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_encoder const *)encoder; gma_encoder = (struct gma_encoder *)__mptr; mode_dev = & dev_priv->mode_dev; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return; } else { } mode_dev->saveBLC_PWM_CTL = REGISTER_READ(dev, 397908U); mode_dev->backlight_duty_cycle = (int )mode_dev->saveBLC_PWM_CTL & 65535; oaktrail_lvds_set_power(dev, gma_encoder, 0); gma_power_end(dev); return; } } static u32 oaktrail_lvds_get_max_backlight(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; u32 ret ; uint32_t tmp ; bool tmp___0 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp___0 = gma_power_begin(dev, 0); if ((int )tmp___0) { tmp = REGISTER_READ(dev, 397908U); ret = (tmp >> 17) * 2U; gma_power_end(dev); } else { ret = (dev_priv->regs.saveBLC_PWM_CTL >> 17) * 2U; } return (ret); } } static void oaktrail_lvds_commit(struct drm_encoder *encoder ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct gma_encoder *gma_encoder ; struct drm_encoder const *__mptr ; struct psb_intel_mode_device *mode_dev ; u32 tmp ; { dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; __mptr = (struct drm_encoder const *)encoder; gma_encoder = (struct gma_encoder *)__mptr; mode_dev = & dev_priv->mode_dev; if (mode_dev->backlight_duty_cycle == 0) { tmp = oaktrail_lvds_get_max_backlight(dev); mode_dev->backlight_duty_cycle = (int )tmp; } else { } oaktrail_lvds_set_power(dev, gma_encoder, 1); return; } } static struct drm_encoder_helper_funcs const oaktrail_lvds_helper_funcs = {& oaktrail_lvds_dpms, 0, 0, & psb_intel_lvds_mode_fixup, & oaktrail_lvds_prepare, & oaktrail_lvds_commit, & oaktrail_lvds_mode_set, 0, 0, 0, 0, 0}; static void oaktrail_lvds_get_configuration_mode(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) { struct drm_display_mode *mode ; struct drm_psb_private *dev_priv ; struct oaktrail_timing_info *ti ; void *tmp ; { mode = (struct drm_display_mode *)0; dev_priv = (struct drm_psb_private *)dev->dev_private; ti = & dev_priv->gct_data.DTD; mode_dev->panel_fixed_mode = (struct drm_display_mode *)0; if ((int )dev_priv->has_gct) { tmp = kzalloc(208UL, 208U); mode = (struct drm_display_mode *)tmp; if ((unsigned long )mode == (unsigned long )((struct drm_display_mode *)0)) { return; } else { } mode->hdisplay = ((int )ti->hactive_hi << 8) | (int )ti->hactive_lo; mode->vdisplay = ((int )ti->vactive_hi << 8) | (int )ti->vactive_lo; mode->hsync_start = mode->hdisplay + (((int )ti->hsync_offset_hi << 8) | (int )ti->hsync_offset_lo); mode->hsync_end = mode->hsync_start + (((int )ti->hsync_pulse_width_hi << 8) | (int )ti->hsync_pulse_width_lo); mode->htotal = mode->hdisplay + (((int )ti->hblank_hi << 8) | (int )ti->hblank_lo); mode->vsync_start = mode->vdisplay + (((int )ti->vsync_offset_hi << 4) | (int )ti->vsync_offset_lo); mode->vsync_end = mode->vsync_start + (((int )ti->vsync_pulse_width_hi << 4) | (int )ti->vsync_pulse_width_lo); mode->vtotal = mode->vdisplay + (((int )ti->vblank_hi << 8) | (int )ti->vblank_lo); mode->clock = (int )ti->pixel_clock * 10; mode_dev->panel_fixed_mode = mode; } else { } if ((unsigned long )mode_dev->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0) && (unsigned long )mode_dev->vbt_mode != (unsigned long )((struct drm_display_mode *)0)) { mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)mode_dev->vbt_mode); } else { } if ((unsigned long )mode_dev->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { if ((unsigned long )dev_priv->lfp_lvds_vbt_mode != (unsigned long )((struct drm_display_mode *)0)) { mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)dev_priv->lfp_lvds_vbt_mode); } else { } } else { } if ((unsigned long )mode_dev->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { return; } else { } drm_mode_set_name(mode_dev->panel_fixed_mode); drm_mode_set_crtcinfo(mode_dev->panel_fixed_mode, 0); return; } } void oaktrail_lvds_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) { struct gma_encoder *gma_encoder ; struct gma_connector *gma_connector ; struct drm_connector *connector ; struct drm_encoder *encoder ; struct drm_psb_private *dev_priv ; struct edid *edid ; struct i2c_adapter *i2c_adap ; struct drm_display_mode *scan ; void *tmp ; void *tmp___0 ; struct list_head const *__mptr ; struct list_head const *__mptr___0 ; struct _ddebug descriptor ; long tmp___1 ; { dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = kzalloc(152UL, 208U); gma_encoder = (struct gma_encoder *)tmp; if ((unsigned long )gma_encoder == (unsigned long )((struct gma_encoder *)0)) { return; } else { } tmp___0 = kzalloc(944UL, 208U); gma_connector = (struct gma_connector *)tmp___0; if ((unsigned long )gma_connector == (unsigned long )((struct gma_connector *)0)) { goto failed_connector; } else { } connector = & gma_connector->base; encoder = & gma_encoder->base; dev_priv->is_lvds_on = 1; drm_connector_init(dev, connector, & psb_intel_lvds_connector_funcs, 7); drm_encoder_init(dev, encoder, & psb_intel_lvds_enc_funcs, 3); gma_connector_attach_encoder(gma_connector, gma_encoder); gma_encoder->type = 4; drm_encoder_helper_add(encoder, & oaktrail_lvds_helper_funcs); drm_connector_helper_add(connector, & psb_intel_lvds_connector_helper_funcs); connector->display_info.subpixel_order = 1; connector->interlace_allowed = 0; connector->doublescan_allowed = 0; drm_object_attach_property(& connector->base, dev->mode_config.scaling_mode_property, 1ULL); drm_object_attach_property(& connector->base, dev_priv->backlight_property, 100ULL); mode_dev->panel_wants_dither = 0; if ((int )dev_priv->has_gct) { mode_dev->panel_wants_dither = (dev_priv->gct_data.Panel_Port_Control & 33554432U) != 0U; } else { } if ((unsigned int )*((unsigned char *)dev_priv + 864UL) != 0U) { mode_dev->panel_wants_dither = 1; } else { } edid = (struct edid *)0; mutex_lock_nested(& dev->mode_config.mutex, 0U); i2c_adap = i2c_get_adapter((dev_priv->ops)->i2c_bus); if ((unsigned long )i2c_adap != (unsigned long )((struct i2c_adapter *)0)) { edid = drm_get_edid(connector, i2c_adap); } else { } if ((unsigned long )edid == (unsigned long )((struct edid *)0) && (unsigned int )dev_priv->lpc_gpio_base != 0U) { oaktrail_lvds_i2c_init(encoder); if ((unsigned long )gma_encoder->ddc_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { i2c_adap = & (gma_encoder->ddc_bus)->adapter; edid = drm_get_edid(connector, i2c_adap); } else { } } else { } if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { drm_mode_connector_update_edid_property(connector, (struct edid const *)edid); drm_add_edid_modes(connector, edid); kfree((void const *)edid); __mptr = (struct list_head const *)connector->probed_modes.next; scan = (struct drm_display_mode *)__mptr; goto ldv_41738; ldv_41737: ; if ((scan->type & 8U) != 0U) { mode_dev->panel_fixed_mode = drm_mode_duplicate(dev, (struct drm_display_mode const *)scan); goto out; } else { } __mptr___0 = (struct list_head const *)scan->head.next; scan = (struct drm_display_mode *)__mptr___0; ldv_41738: ; if ((unsigned long )(& scan->head) != (unsigned long )(& connector->probed_modes)) { goto ldv_41737; } else { } } else { dev_err((struct device const *)dev->dev, "No ddc adapter available!\n"); } oaktrail_lvds_get_configuration_mode(dev, mode_dev); if ((unsigned long )mode_dev->panel_fixed_mode != (unsigned long )((struct drm_display_mode *)0)) { (mode_dev->panel_fixed_mode)->type = (mode_dev->panel_fixed_mode)->type | 8U; goto out; } else { } if ((unsigned long )mode_dev->panel_fixed_mode == (unsigned long )((struct drm_display_mode *)0)) { dev_err((struct device const *)dev->dev, "Found no modes on the lvds, ignoring the LVDS\n"); goto failed_find; } else { } out: mutex_unlock(& dev->mode_config.mutex); drm_connector_register(connector); return; failed_find: mutex_unlock(& dev->mode_config.mutex); descriptor.modname = "gma500_gfx"; descriptor.function = "oaktrail_lvds_init"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/10068/dscv_tempdir/dscv/ri/08_1a/drivers/gpu/drm/gma500/oaktrail_lvds.c"; descriptor.format = "No LVDS modes found, disabling.\n"; descriptor.lineno = 418U; descriptor.flags = 0U; tmp___1 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___1 != 0L) { __dynamic_dev_dbg(& descriptor, (struct device const *)dev->dev, "No LVDS modes found, disabling.\n"); } else { } if ((unsigned long )gma_encoder->ddc_bus != (unsigned long )((struct psb_intel_i2c_chan *)0)) { psb_intel_i2c_destroy(gma_encoder->ddc_bus); gma_encoder->ddc_bus = (struct psb_intel_i2c_chan *)0; } else { } drm_encoder_cleanup(encoder); drm_connector_cleanup(connector); kfree((void const *)gma_connector); failed_connector: kfree((void const *)gma_encoder); return; } } void ldv_initialize_drm_encoder_helper_funcs_10(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(96UL); oaktrail_lvds_helper_funcs_group0 = (struct drm_encoder *)tmp; tmp___0 = ldv_init_zalloc(208UL); oaktrail_lvds_helper_funcs_group1 = (struct drm_display_mode *)tmp___0; return; } } void ldv_main_exported_10(void) { struct drm_display_mode *ldvarg96 ; void *tmp ; struct drm_display_mode *ldvarg97 ; void *tmp___0 ; int ldvarg98 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg96 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg97 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg98), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_10 == 1) { oaktrail_lvds_dpms(oaktrail_lvds_helper_funcs_group0, ldvarg98); ldv_state_variable_10 = 1; } else { } goto ldv_41753; case 1: ; if (ldv_state_variable_10 == 1) { psb_intel_lvds_mode_fixup(oaktrail_lvds_helper_funcs_group0, (struct drm_display_mode const *)ldvarg97, oaktrail_lvds_helper_funcs_group1); ldv_state_variable_10 = 1; } else { } goto ldv_41753; case 2: ; if (ldv_state_variable_10 == 1) { oaktrail_lvds_commit(oaktrail_lvds_helper_funcs_group0); ldv_state_variable_10 = 1; } else { } goto ldv_41753; case 3: ; if (ldv_state_variable_10 == 1) { oaktrail_lvds_mode_set(oaktrail_lvds_helper_funcs_group0, oaktrail_lvds_helper_funcs_group1, ldvarg96); ldv_state_variable_10 = 1; } else { } goto ldv_41753; case 4: ; if (ldv_state_variable_10 == 1) { oaktrail_lvds_prepare(oaktrail_lvds_helper_funcs_group0); ldv_state_variable_10 = 1; } else { } goto ldv_41753; default: ldv_stop(); } ldv_41753: ; return; } } bool ldv_queue_work_on_443(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_444(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_445(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_446(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_447(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_457(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_459(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_458(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_461(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_460(struct workqueue_struct *ldv_func_arg1 ) ; static int get_clock___1(void *data ) { struct psb_intel_i2c_chan *chan ; u32 val ; u32 tmp ; unsigned int tmp___0 ; { chan = (struct psb_intel_i2c_chan *)data; val = inl((int )(chan->reg + 36U)); val = val | 8U; outl(val, (int )(chan->reg + 36U)); tmp = inl((int )(chan->reg + 40U)); tmp___0 = inl((int )(chan->reg + 40U)); val = (tmp___0 & 8U) != 0U; return ((int )val); } } static int get_data___1(void *data ) { struct psb_intel_i2c_chan *chan ; u32 val ; u32 tmp ; unsigned int tmp___0 ; { chan = (struct psb_intel_i2c_chan *)data; val = inl((int )(chan->reg + 36U)); val = val | 16U; outl(val, (int )(chan->reg + 36U)); tmp = inl((int )(chan->reg + 40U)); tmp___0 = inl((int )(chan->reg + 40U)); val = (tmp___0 & 16U) != 0U; return ((int )val); } } static void set_clock___1(void *data , int state_high ) { struct psb_intel_i2c_chan *chan ; u32 val ; { chan = (struct psb_intel_i2c_chan *)data; if (state_high != 0) { val = inl((int )(chan->reg + 36U)); val = val | 8U; outl(val, (int )(chan->reg + 36U)); } else { val = inl((int )(chan->reg + 36U)); val = val & 4294967287U; outl(val, (int )(chan->reg + 36U)); val = inl((int )(chan->reg + 40U)); val = val & 4294967287U; outl(val, (int )(chan->reg + 40U)); } return; } } static void set_data___1(void *data , int state_high ) { struct psb_intel_i2c_chan *chan ; u32 val ; { chan = (struct psb_intel_i2c_chan *)data; if (state_high != 0) { val = inl((int )(chan->reg + 36U)); val = val | 16U; outl(val, (int )(chan->reg + 36U)); } else { val = inl((int )(chan->reg + 36U)); val = val & 4294967279U; outl(val, (int )(chan->reg + 36U)); val = inl((int )(chan->reg + 40U)); val = val & 4294967279U; outl(val, (int )(chan->reg + 40U)); } return; } } void oaktrail_lvds_i2c_init(struct drm_encoder *encoder ) { struct drm_device *dev ; struct gma_encoder *gma_encoder ; struct drm_encoder const *__mptr ; struct drm_psb_private *dev_priv ; struct psb_intel_i2c_chan *chan ; void *tmp ; unsigned long tmp___0 ; int tmp___1 ; { dev = encoder->dev; __mptr = (struct drm_encoder const *)encoder; gma_encoder = (struct gma_encoder *)__mptr; dev_priv = (struct drm_psb_private *)dev->dev_private; tmp = kzalloc(2024UL, 208U); chan = (struct psb_intel_i2c_chan *)tmp; if ((unsigned long )chan == (unsigned long )((struct psb_intel_i2c_chan *)0)) { return; } else { } chan->drm_dev = dev; chan->reg = (u32 )dev_priv->lpc_gpio_base; strncpy((char *)(& chan->adapter.name), "gma500 LPC", 19UL); chan->adapter.owner = & __this_module; chan->adapter.algo_data = (void *)(& chan->algo); chan->adapter.dev.parent = & (dev->pdev)->dev; chan->algo.setsda = & set_data___1; chan->algo.setscl = & set_clock___1; chan->algo.getsda = & get_data___1; chan->algo.getscl = & get_clock___1; chan->algo.udelay = 100; tmp___0 = usecs_to_jiffies(2200U); chan->algo.timeout = (int )tmp___0; chan->algo.data = (void *)chan; i2c_set_adapdata(& chan->adapter, (void *)chan); set_data___1((void *)chan, 1); set_clock___1((void *)chan, 1); __const_udelay(214750UL); tmp___1 = i2c_bit_add_bus(& chan->adapter); if (tmp___1 != 0) { kfree((void const *)chan); return; } else { } gma_encoder->ddc_bus = chan; return; } } bool ldv_queue_work_on_457(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_458(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_459(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_460(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_461(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_queue_work_on_471(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_473(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_472(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_475(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_474(struct workqueue_struct *ldv_func_arg1 ) ; __inline static void writel(unsigned int val , void volatile *addr ) { { __asm__ volatile ("movl %0,%1": : "r" (val), "m" (*((unsigned int volatile *)addr)): "memory"); return; } } extern struct pci_dev *pci_get_device(unsigned int , unsigned int , struct pci_dev * ) ; __inline static void pci_set_drvdata(struct pci_dev *pdev , void *data ) { { dev_set_drvdata(& pdev->dev, data); return; } } int oaktrail_hdmi_i2c_init(struct pci_dev *dev ) ; void oaktrail_hdmi_i2c_exit(struct pci_dev *dev ) ; static struct oaktrail_hdmi_limit const oaktrail_hdmi_limit = {{320000, 1650000}, {1, 15}, {1, 64}, {2, 4095}}; static void oaktrail_hdmi_audio_enable(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct oaktrail_hdmi_dev *hdmi_dev ; { dev_priv = (struct drm_psb_private *)dev->dev_private; hdmi_dev = dev_priv->hdmi_priv; writel(103U, (void volatile *)hdmi_dev->regs + 4096U); readl((void const volatile *)hdmi_dev->regs + 4096U); writel(16U, (void volatile *)hdmi_dev->regs + 20904U); readl((void const volatile *)hdmi_dev->regs + 20904U); writel(1U, (void volatile *)hdmi_dev->regs + 16384U); readl((void const volatile *)hdmi_dev->regs + 16384U); return; } } static void oaktrail_hdmi_audio_disable(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct oaktrail_hdmi_dev *hdmi_dev ; { dev_priv = (struct drm_psb_private *)dev->dev_private; hdmi_dev = dev_priv->hdmi_priv; writel(0U, (void volatile *)hdmi_dev->regs + 20904U); readl((void const volatile *)hdmi_dev->regs + 20904U); writel(0U, (void volatile *)hdmi_dev->regs + 16384U); readl((void const volatile *)hdmi_dev->regs + 16384U); writel(71U, (void volatile *)hdmi_dev->regs + 4096U); readl((void const volatile *)hdmi_dev->regs + 4096U); return; } } static unsigned int htotal_calculate(struct drm_display_mode *mode ) { u32 htotal ; u32 new_crtc_htotal ; long tmp ; { htotal = (u32 )((mode->crtc_hdisplay + -1) | ((mode->crtc_htotal + -1) << 16)); new_crtc_htotal = (u32 )(((mode->crtc_htotal + -1) * 200000) / mode->clock); tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("htotal_calculate", "new crtc htotal 0x%4x\n", new_crtc_htotal); } else { } return ((u32 )(mode->crtc_hdisplay + -1) | (new_crtc_htotal << 16)); } } static void oaktrail_hdmi_find_dpll(struct drm_crtc *crtc , int target , int refclk , struct oaktrail_hdmi_clock *best_clock ) { int np_min ; int np_max ; int nr_min ; int nr_max ; int np ; int nr ; int nf ; int __x ; int __d ; long tmp ; { np_min = (((int )oaktrail_hdmi_limit.vco.min + target * 10) + -1) / (target * 10); np_max = (int )oaktrail_hdmi_limit.vco.max / (target * 10); if ((int )oaktrail_hdmi_limit.np.min > np_min) { np_min = oaktrail_hdmi_limit.np.min; } else { } if ((int )oaktrail_hdmi_limit.np.max < np_max) { np_max = oaktrail_hdmi_limit.np.max; } else { } nr_min = ((refclk * 1000 + (target * 10) * np_max) + -1) / ((target * 10) * np_max); nr_max = ((refclk * 1000 + (target * 10) * np_min) + -1) / ((target * 10) * np_min); if ((int )oaktrail_hdmi_limit.nr.min > nr_min) { nr_min = oaktrail_hdmi_limit.nr.min; } else { } if ((int )oaktrail_hdmi_limit.nr.max < nr_max) { nr_max = oaktrail_hdmi_limit.nr.max; } else { } np = ((refclk * 1000 + (target * 10) * nr_max) + -1) / ((target * 10) * nr_max); nr = ((refclk * 1000 + (target * 10) * np) + -1) / ((target * 10) * np); __x = ((target * 10) * np) * nr; __d = refclk; nf = __x > 0 ? (__d / 2 + __x) / __d : (__x - __d / 2) / __d; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("oaktrail_hdmi_find_dpll", "np, nr, nf %d %d %d\n", np, nr, nf); } else { } best_clock->np = np; best_clock->nr = nr + -1; best_clock->nf = nf << 14; return; } } static void scu_busy_loop(void *scu_base ) { u32 status ; u32 loop_count ; long tmp ; { status = 0U; loop_count = 0U; status = readl((void const volatile *)scu_base + 4U); goto ldv_41598; ldv_41597: __const_udelay(4295UL); status = readl((void const volatile *)scu_base + 4U); loop_count = loop_count + 1U; if (loop_count > 1000U) { tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("scu_busy_loop", "SCU IPC timed out"); } else { } return; } else { } ldv_41598: ; if ((int )status & 1) { goto ldv_41597; } else { } return; } } static void oaktrail_hdmi_reset(struct drm_device *dev ) { void *base ; unsigned long scu_ipc_mmio ; int scu_len ; { scu_ipc_mmio = 4279353344UL; scu_len = 1024; base = ioremap((unsigned long long )scu_ipc_mmio, (unsigned long )scu_len); if ((unsigned long )base == (unsigned long )((void *)0)) { drm_err("failed to map scu mmio\n"); return; } else { } writel(4279357720U, (void volatile *)base + 12U); writel(2147483615U, (void volatile *)base + 128U); writel(270341U, (void volatile *)base); scu_busy_loop(base); writel(4279357720U, (void volatile *)base + 12U); writel(2147483647U, (void volatile *)base + 128U); writel(270341U, (void volatile *)base); scu_busy_loop(base); iounmap((void volatile *)base); return; } } int oaktrail_crtc_hdmi_mode_set(struct drm_crtc *crtc , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode , int x , int y , struct drm_framebuffer *old_fb ) { struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct oaktrail_hdmi_dev *hdmi_dev ; int pipe ; int htot_reg ; int hblank_reg ; int hsync_reg ; int vtot_reg ; int vblank_reg ; int vsync_reg ; int dspsize_reg ; int dsppos_reg ; int pipesrc_reg ; int pipeconf_reg ; int refclk ; struct oaktrail_hdmi_clock clock ; u32 dspcntr ; u32 pipeconf ; u32 dpll ; u32 temp ; int dspcntr_reg ; bool tmp ; int tmp___0 ; struct drm_crtc_helper_funcs const *crtc_funcs ; { dev = crtc->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; hdmi_dev = dev_priv->hdmi_priv; pipe = 1; htot_reg = pipe == 0 ? 393216 : 397312; hblank_reg = pipe == 0 ? 393220 : 397316; hsync_reg = pipe == 0 ? 393224 : 397320; vtot_reg = pipe == 0 ? 393228 : 397324; vblank_reg = pipe == 0 ? 393232 : 397328; vsync_reg = pipe == 0 ? 393236 : 397332; dspsize_reg = pipe == 0 ? 459152 : 463248; dsppos_reg = pipe == 0 ? 459148 : 463244; pipesrc_reg = pipe == 0 ? 393244 : 397340; pipeconf_reg = pipe == 0 ? 458760 : 462856; dspcntr_reg = 463232; tmp = gma_power_begin(dev, 1); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } REGISTER_WRITE(dev, 463872U, 2147483648U); dpll = REGISTER_READ(dev, 24576U); if ((dpll & 16U) == 0U) { REGISTER_WRITE(dev, 24576U, dpll | 24U); REGISTER_WRITE(dev, 24580U, 0U); REGISTER_WRITE(dev, 24592U, 1U); } else { } __const_udelay(644250UL); oaktrail_hdmi_reset(dev); refclk = 25000; oaktrail_hdmi_find_dpll(crtc, adjusted_mode->clock, refclk, & clock); dpll = REGISTER_READ(dev, 24576U); dpll = dpll & 4293984255U; dpll = dpll & 4294967271U; REGISTER_WRITE(dev, 24576U, 8U); REGISTER_WRITE(dev, 24580U, (uint32_t )((clock.nf << 6) | clock.nr)); REGISTER_WRITE(dev, 24588U, (uint32_t )((clock.nf >> 14) + -1)); REGISTER_WRITE(dev, 24576U, ((u32 )(clock.np << 16) | dpll) | 3U); REGISTER_WRITE(dev, 24596U, 2147483648U); REGISTER_WRITE(dev, 24584U, 2147811586U); __const_udelay(644250UL); writel(509U, (void volatile *)hdmi_dev->regs + 4100U); writel(1U, (void volatile *)hdmi_dev->regs + 8192U); writel(0U, (void volatile *)hdmi_dev->regs + 8200U); writel(8U, (void volatile *)hdmi_dev->regs + 12592U); writel(25167888U, (void volatile *)hdmi_dev->regs + 4124U); temp = htotal_calculate(adjusted_mode); REGISTER_WRITE(dev, (uint32_t )htot_reg, temp); REGISTER_WRITE(dev, (uint32_t )hblank_reg, (uint32_t )((adjusted_mode->crtc_hblank_start + -1) | ((adjusted_mode->crtc_hblank_end + -1) << 16))); REGISTER_WRITE(dev, (uint32_t )hsync_reg, (uint32_t )((adjusted_mode->crtc_hsync_start + -1) | ((adjusted_mode->crtc_hsync_end + -1) << 16))); REGISTER_WRITE(dev, (uint32_t )vtot_reg, (uint32_t )((adjusted_mode->crtc_vdisplay + -1) | ((adjusted_mode->crtc_vtotal + -1) << 16))); REGISTER_WRITE(dev, (uint32_t )vblank_reg, (uint32_t )((adjusted_mode->crtc_vblank_start + -1) | ((adjusted_mode->crtc_vblank_end + -1) << 16))); REGISTER_WRITE(dev, (uint32_t )vsync_reg, (uint32_t )((adjusted_mode->crtc_vsync_start + -1) | ((adjusted_mode->crtc_vsync_end + -1) << 16))); REGISTER_WRITE(dev, (uint32_t )pipesrc_reg, (uint32_t )(((mode->crtc_hdisplay + -1) << 16) | (mode->crtc_vdisplay + -1))); REGISTER_WRITE(dev, 12544U, (uint32_t )((adjusted_mode->crtc_hdisplay + -1) | ((adjusted_mode->crtc_htotal + -1) << 16))); REGISTER_WRITE(dev, 12548U, (uint32_t )((adjusted_mode->crtc_hblank_start + -1) | ((adjusted_mode->crtc_hblank_end + -1) << 16))); REGISTER_WRITE(dev, 12552U, (uint32_t )((adjusted_mode->crtc_hsync_start + -1) | ((adjusted_mode->crtc_hsync_end + -1) << 16))); REGISTER_WRITE(dev, 12556U, (uint32_t )((adjusted_mode->crtc_vdisplay + -1) | ((adjusted_mode->crtc_vtotal + -1) << 16))); REGISTER_WRITE(dev, 12560U, (uint32_t )((adjusted_mode->crtc_vblank_start + -1) | ((adjusted_mode->crtc_vblank_end + -1) << 16))); REGISTER_WRITE(dev, 12564U, (uint32_t )((adjusted_mode->crtc_vsync_start + -1) | ((adjusted_mode->crtc_vsync_end + -1) << 16))); REGISTER_WRITE(dev, 12572U, (uint32_t )(((mode->crtc_hdisplay + -1) << 16) | (mode->crtc_vdisplay + -1))); temp = (u32 )(adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start); writel((u32 )((adjusted_mode->crtc_hdisplay + -1) << 16) | temp, (void volatile *)hdmi_dev->regs + 12544U); REGISTER_WRITE(dev, (uint32_t )dspsize_reg, (uint32_t )(((mode->vdisplay + -1) << 16) | (mode->hdisplay + -1))); REGISTER_WRITE(dev, (uint32_t )dsppos_reg, 0U); crtc_funcs = (struct drm_crtc_helper_funcs const *)crtc->helper_private; (*(crtc_funcs->mode_set_base))(crtc, x, y, old_fb); dspcntr = REGISTER_READ(dev, (uint32_t )dspcntr_reg); dspcntr = dspcntr | 1073741824U; dspcntr = dspcntr | 16777216U; dspcntr = dspcntr | 2147483648U; pipeconf = REGISTER_READ(dev, (uint32_t )pipeconf_reg); pipeconf = pipeconf | 2147483648U; REGISTER_WRITE(dev, (uint32_t )pipeconf_reg, pipeconf); REGISTER_READ(dev, (uint32_t )pipeconf_reg); REGISTER_WRITE(dev, 14344U, pipeconf); REGISTER_READ(dev, 14344U); gma_wait_for_vblank(dev); REGISTER_WRITE(dev, (uint32_t )dspcntr_reg, dspcntr); gma_wait_for_vblank(dev); gma_power_end(dev); return (0); } } void oaktrail_crtc_hdmi_dpms(struct drm_crtc *crtc , int mode ) { struct drm_device *dev ; u32 temp ; long tmp ; uint32_t tmp___0 ; uint32_t tmp___1 ; { dev = crtc->dev; tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("oaktrail_crtc_hdmi_dpms", "%s %d\n", "oaktrail_crtc_hdmi_dpms", mode); } else { } switch (mode) { case 3: REGISTER_WRITE(dev, 463872U, 2147483648U); temp = REGISTER_READ(dev, 463232U); if ((int )temp < 0) { REGISTER_WRITE(dev, 463232U, temp & 2147483647U); REGISTER_READ(dev, 463232U); tmp___0 = REGISTER_READ(dev, 463260U); REGISTER_WRITE(dev, 463260U, tmp___0); REGISTER_READ(dev, 463260U); } else { } temp = REGISTER_READ(dev, 462856U); if ((int )temp < 0) { REGISTER_WRITE(dev, 462856U, temp & 2147483647U); REGISTER_READ(dev, 462856U); } else { } temp = REGISTER_READ(dev, 14344U); if ((int )temp < 0) { REGISTER_WRITE(dev, 14344U, temp & 2147483647U); REGISTER_READ(dev, 14344U); } else { } __const_udelay(644250UL); temp = REGISTER_READ(dev, 24576U); if ((temp & 16U) == 0U) { REGISTER_WRITE(dev, 24576U, temp | 24U); REGISTER_WRITE(dev, 24592U, 1U); } else { } __const_udelay(644250UL); goto ldv_41644; case 0: ; case 1: ; case 2: temp = REGISTER_READ(dev, 24576U); if ((temp & 16U) != 0U) { REGISTER_WRITE(dev, 24576U, temp & 4294967271U); temp = REGISTER_READ(dev, 24584U); REGISTER_WRITE(dev, 24584U, temp | 2147483906U); REGISTER_READ(dev, 24584U); } else { } __const_udelay(644250UL); temp = REGISTER_READ(dev, 462856U); if ((int )temp >= 0) { REGISTER_WRITE(dev, 462856U, temp | 2147483648U); REGISTER_READ(dev, 462856U); } else { } temp = REGISTER_READ(dev, 14344U); if ((int )temp >= 0) { REGISTER_WRITE(dev, 14344U, temp | 2147483648U); REGISTER_READ(dev, 14344U); } else { } gma_wait_for_vblank(dev); temp = REGISTER_READ(dev, 463232U); if ((int )temp >= 0) { REGISTER_WRITE(dev, 463232U, temp | 2147483648U); tmp___1 = REGISTER_READ(dev, 463260U); REGISTER_WRITE(dev, 463260U, tmp___1); REGISTER_READ(dev, 463260U); } else { } gma_crtc_load_lut(crtc); } ldv_41644: REGISTER_WRITE(dev, 458800U, 16319U); REGISTER_WRITE(dev, 458804U, 1065880074U); REGISTER_WRITE(dev, 458808U, 184944648U); REGISTER_WRITE(dev, 458832U, 134415364U); REGISTER_WRITE(dev, 458836U, 67372036U); REGISTER_WRITE(dev, 459776U, 16384U); return; } } static void oaktrail_hdmi_dpms(struct drm_encoder *encoder , int mode ) { int dpms_mode ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct oaktrail_hdmi_dev *hdmi_dev ; u32 temp ; { dpms_mode = -1; dev = encoder->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; hdmi_dev = dev_priv->hdmi_priv; if (dpms_mode == mode) { return; } else { } if (mode != 0) { temp = 0U; } else { temp = 153U; } dpms_mode = mode; writel(temp, (void volatile *)hdmi_dev->regs + 12288U); return; } } static int oaktrail_hdmi_mode_valid(struct drm_connector *connector , struct drm_display_mode *mode ) { { if (mode->clock > 165000) { return (15); } else { } if (mode->clock <= 19999) { return (16); } else { } if ((mode->flags & 32U) != 0U) { return (8); } else { } return (0); } } static enum drm_connector_status oaktrail_hdmi_detect(struct drm_connector *connector , bool force ) { enum drm_connector_status status ; struct drm_device *dev ; struct drm_psb_private *dev_priv ; struct oaktrail_hdmi_dev *hdmi_dev ; u32 temp ; long tmp ; { dev = connector->dev; dev_priv = (struct drm_psb_private *)dev->dev_private; hdmi_dev = dev_priv->hdmi_priv; temp = readl((void const volatile *)hdmi_dev->regs + 4104U); tmp = ldv__builtin_expect((drm_debug & 4U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("oaktrail_hdmi_detect", "HDMI_HSR %x\n", temp); } else { } if ((int )temp & 1) { status = 1; } else { status = 2; } return (status); } } static unsigned char const raw_edid[128U] = { 0U, 255U, 255U, 255U, 255U, 255U, 255U, 0U, 16U, 172U, 47U, 160U, 83U, 85U, 51U, 48U, 22U, 19U, 1U, 3U, 14U, 58U, 36U, 120U, 234U, 233U, 245U, 172U, 81U, 48U, 180U, 37U, 17U, 80U, 84U, 165U, 75U, 0U, 129U, 128U, 169U, 64U, 113U, 79U, 179U, 0U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 40U, 60U, 128U, 160U, 112U, 176U, 35U, 64U, 48U, 32U, 54U, 0U, 70U, 108U, 33U, 0U, 0U, 26U, 0U, 0U, 0U, 255U, 0U, 71U, 78U, 55U, 50U, 49U, 57U, 53U, 82U, 48U, 51U, 85U, 83U, 10U, 0U, 0U, 0U, 252U, 0U, 68U, 69U, 76U, 76U, 32U, 50U, 55U, 48U, 57U, 87U, 10U, 32U, 32U, 0U, 0U, 0U, 253U, 0U, 56U, 76U, 30U, 83U, 17U, 0U, 10U, 32U, 32U, 32U, 32U, 32U, 32U, 0U, 141U}; static int oaktrail_hdmi_get_modes(struct drm_connector *connector ) { struct i2c_adapter *i2c_adap ; struct edid *edid ; int ret ; { ret = 0; i2c_adap = i2c_get_adapter(3); if ((unsigned long )i2c_adap == (unsigned long )((struct i2c_adapter *)0)) { drm_err("No ddc adapter available!\n"); edid = (struct edid *)(& raw_edid); } else { edid = (struct edid *)(& raw_edid); } if ((unsigned long )edid != (unsigned long )((struct edid *)0)) { drm_mode_connector_update_edid_property(connector, (struct edid const *)edid); ret = drm_add_edid_modes(connector, edid); } else { } return (ret); } } static void oaktrail_hdmi_mode_set(struct drm_encoder *encoder , struct drm_display_mode *mode , struct drm_display_mode *adjusted_mode ) { struct drm_device *dev ; { dev = encoder->dev; oaktrail_hdmi_audio_enable(dev); return; } } static void oaktrail_hdmi_destroy(struct drm_connector *connector ) { { return; } } static struct drm_encoder_helper_funcs const oaktrail_hdmi_helper_funcs = {& oaktrail_hdmi_dpms, 0, 0, & gma_encoder_mode_fixup, & gma_encoder_prepare, & gma_encoder_commit, & oaktrail_hdmi_mode_set, 0, 0, 0, 0, 0}; static struct drm_connector_helper_funcs const oaktrail_hdmi_connector_helper_funcs = {& oaktrail_hdmi_get_modes, (enum drm_mode_status (*)(struct drm_connector * , struct drm_display_mode * ))(& oaktrail_hdmi_mode_valid), & gma_best_encoder}; static struct drm_connector_funcs const oaktrail_hdmi_connector_funcs = {& drm_helper_connector_dpms, 0, 0, 0, & oaktrail_hdmi_detect, & drm_helper_probe_single_connector_modes, 0, & oaktrail_hdmi_destroy, 0, 0, 0, 0, 0}; static void oaktrail_hdmi_enc_destroy(struct drm_encoder *encoder ) { { drm_encoder_cleanup(encoder); return; } } static struct drm_encoder_funcs const oaktrail_hdmi_enc_funcs = {0, & oaktrail_hdmi_enc_destroy}; void oaktrail_hdmi_init(struct drm_device *dev , struct psb_intel_mode_device *mode_dev ) { struct gma_encoder *gma_encoder ; struct gma_connector *gma_connector ; struct drm_connector *connector ; struct drm_encoder *encoder ; void *tmp ; void *tmp___0 ; { tmp = kzalloc(152UL, 208U); gma_encoder = (struct gma_encoder *)tmp; if ((unsigned long )gma_encoder == (unsigned long )((struct gma_encoder *)0)) { return; } else { } tmp___0 = kzalloc(944UL, 208U); gma_connector = (struct gma_connector *)tmp___0; if ((unsigned long )gma_connector == (unsigned long )((struct gma_connector *)0)) { goto failed_connector; } else { } connector = & gma_connector->base; encoder = & gma_encoder->base; drm_connector_init(dev, connector, & oaktrail_hdmi_connector_funcs, 3); drm_encoder_init(dev, encoder, & oaktrail_hdmi_enc_funcs, 2); gma_connector_attach_encoder(gma_connector, gma_encoder); gma_encoder->type = 6; drm_encoder_helper_add(encoder, & oaktrail_hdmi_helper_funcs); drm_connector_helper_add(connector, & oaktrail_hdmi_connector_helper_funcs); connector->display_info.subpixel_order = 1; connector->interlace_allowed = 0; connector->doublescan_allowed = 0; drm_connector_register(connector); _dev_info((struct device const *)dev->dev, "HDMI initialised.\n"); return; failed_connector: kfree((void const *)gma_encoder); return; } } void oaktrail_hdmi_setup(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct pci_dev *pdev ; struct oaktrail_hdmi_dev *hdmi_dev ; int ret ; void *tmp ; { dev_priv = (struct drm_psb_private *)dev->dev_private; pdev = pci_get_device(32902U, 2061U, (struct pci_dev *)0); if ((unsigned long )pdev == (unsigned long )((struct pci_dev *)0)) { return; } else { } tmp = kzalloc(96UL, 208U); hdmi_dev = (struct oaktrail_hdmi_dev *)tmp; if ((unsigned long )hdmi_dev == (unsigned long )((struct oaktrail_hdmi_dev *)0)) { dev_err((struct device const *)dev->dev, "failed to allocate memory\n"); goto out; } else { } ret = pci_enable_device(pdev); if (ret != 0) { dev_err((struct device const *)dev->dev, "failed to enable hdmi controller\n"); goto free; } else { } hdmi_dev->mmio = (unsigned int )pdev->resource[0].start; hdmi_dev->mmio_len = pdev->resource[0].start != 0ULL || pdev->resource[0].end != pdev->resource[0].start ? ((unsigned int )pdev->resource[0].end - (unsigned int )pdev->resource[0].start) + 1U : 0U; hdmi_dev->regs = ioremap((resource_size_t )hdmi_dev->mmio, (unsigned long )hdmi_dev->mmio_len); if ((unsigned long )hdmi_dev->regs == (unsigned long )((void *)0)) { dev_err((struct device const *)dev->dev, "failed to map hdmi mmio\n"); goto free; } else { } hdmi_dev->dev = pdev; pci_set_drvdata(pdev, (void *)hdmi_dev); ret = oaktrail_hdmi_i2c_init(hdmi_dev->dev); if (ret != 0) { dev_err((struct device const *)dev->dev, "HDMI I2C initialization failed\n"); } else { } dev_priv->hdmi_priv = hdmi_dev; oaktrail_hdmi_audio_disable(dev); _dev_info((struct device const *)dev->dev, "HDMI hardware present.\n"); return; free: kfree((void const *)hdmi_dev); out: ; return; } } void oaktrail_hdmi_teardown(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct oaktrail_hdmi_dev *hdmi_dev ; struct pci_dev *pdev ; { dev_priv = (struct drm_psb_private *)dev->dev_private; hdmi_dev = dev_priv->hdmi_priv; if ((unsigned long )hdmi_dev != (unsigned long )((struct oaktrail_hdmi_dev *)0)) { pdev = hdmi_dev->dev; pci_set_drvdata(pdev, (void *)0); oaktrail_hdmi_i2c_exit(pdev); iounmap((void volatile *)hdmi_dev->regs); kfree((void const *)hdmi_dev); pci_dev_put(pdev); } else { } return; } } void oaktrail_hdmi_save(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct oaktrail_hdmi_dev *hdmi_dev ; struct psb_state *regs ; struct psb_pipe *pipeb ; int i ; { dev_priv = (struct drm_psb_private *)dev->dev_private; hdmi_dev = dev_priv->hdmi_priv; regs = & dev_priv->regs.__annonCompField80.psb; pipeb = (struct psb_pipe *)(& dev_priv->regs.pipe) + 1UL; hdmi_dev->saveDPLL_CTRL = ioread32((void *)dev_priv->vdc_reg + 24576U); hdmi_dev->saveDPLL_DIV_CTRL = ioread32((void *)dev_priv->vdc_reg + 24580U); hdmi_dev->saveDPLL_ADJUST = ioread32((void *)dev_priv->vdc_reg + 24588U); hdmi_dev->saveDPLL_UPDATE = ioread32((void *)dev_priv->vdc_reg + 24596U); hdmi_dev->saveDPLL_CLK_ENABLE = ioread32((void *)dev_priv->vdc_reg + 24584U); pipeb->conf = ioread32((void *)dev_priv->vdc_reg + 462856U); pipeb->src = ioread32((void *)dev_priv->vdc_reg + 397340U); pipeb->htotal = ioread32((void *)dev_priv->vdc_reg + 397312U); pipeb->hblank = ioread32((void *)dev_priv->vdc_reg + 397316U); pipeb->hsync = ioread32((void *)dev_priv->vdc_reg + 397320U); pipeb->vtotal = ioread32((void *)dev_priv->vdc_reg + 397324U); pipeb->vblank = ioread32((void *)dev_priv->vdc_reg + 397328U); pipeb->vsync = ioread32((void *)dev_priv->vdc_reg + 397332U); hdmi_dev->savePCH_PIPEBCONF = ioread32((void *)dev_priv->vdc_reg + 14344U); hdmi_dev->savePCH_PIPEBSRC = ioread32((void *)dev_priv->vdc_reg + 12572U); hdmi_dev->savePCH_HTOTAL_B = ioread32((void *)dev_priv->vdc_reg + 12544U); hdmi_dev->savePCH_HBLANK_B = ioread32((void *)dev_priv->vdc_reg + 12548U); hdmi_dev->savePCH_HSYNC_B = ioread32((void *)dev_priv->vdc_reg + 12552U); hdmi_dev->savePCH_VTOTAL_B = ioread32((void *)dev_priv->vdc_reg + 12556U); hdmi_dev->savePCH_VBLANK_B = ioread32((void *)dev_priv->vdc_reg + 12560U); hdmi_dev->savePCH_VSYNC_B = ioread32((void *)dev_priv->vdc_reg + 12564U); pipeb->cntr = ioread32((void *)dev_priv->vdc_reg + 463232U); pipeb->stride = ioread32((void *)dev_priv->vdc_reg + 463240U); pipeb->addr = ioread32((void *)dev_priv->vdc_reg + 463236U); pipeb->surf = ioread32((void *)dev_priv->vdc_reg + 463260U); pipeb->linoff = ioread32((void *)dev_priv->vdc_reg + 463236U); pipeb->tileoff = ioread32((void *)dev_priv->vdc_reg + 463268U); regs->saveDSPBCURSOR_CTRL = ioread32((void *)dev_priv->vdc_reg + 458944U); regs->saveDSPBCURSOR_BASE = ioread32((void *)dev_priv->vdc_reg + 458948U); regs->saveDSPBCURSOR_POS = ioread32((void *)dev_priv->vdc_reg + 458952U); i = 0; goto ldv_41728; ldv_41727: pipeb->palette[i] = ioread32((void *)dev_priv->vdc_reg + (unsigned long )((i << 2) + 43008)); i = i + 1; ldv_41728: ; if (i <= 255) { goto ldv_41727; } else { } return; } } void oaktrail_hdmi_restore(struct drm_device *dev ) { struct drm_psb_private *dev_priv ; struct oaktrail_hdmi_dev *hdmi_dev ; struct psb_state *regs ; struct psb_pipe *pipeb ; int i ; { dev_priv = (struct drm_psb_private *)dev->dev_private; hdmi_dev = dev_priv->hdmi_priv; regs = & dev_priv->regs.__annonCompField80.psb; pipeb = (struct psb_pipe *)(& dev_priv->regs.pipe) + 1UL; iowrite32(hdmi_dev->saveDPLL_CTRL, (void *)dev_priv->vdc_reg + 24576U); iowrite32(hdmi_dev->saveDPLL_DIV_CTRL, (void *)dev_priv->vdc_reg + 24580U); iowrite32(hdmi_dev->saveDPLL_ADJUST, (void *)dev_priv->vdc_reg + 24588U); iowrite32(hdmi_dev->saveDPLL_UPDATE, (void *)dev_priv->vdc_reg + 24596U); iowrite32(hdmi_dev->saveDPLL_CLK_ENABLE, (void *)dev_priv->vdc_reg + 24584U); __const_udelay(644250UL); iowrite32(pipeb->src, (void *)dev_priv->vdc_reg + 397340U); iowrite32(pipeb->htotal, (void *)dev_priv->vdc_reg + 397312U); iowrite32(pipeb->hblank, (void *)dev_priv->vdc_reg + 397316U); iowrite32(pipeb->hsync, (void *)dev_priv->vdc_reg + 397320U); iowrite32(pipeb->vtotal, (void *)dev_priv->vdc_reg + 397324U); iowrite32(pipeb->vblank, (void *)dev_priv->vdc_reg + 397328U); iowrite32(pipeb->vsync, (void *)dev_priv->vdc_reg + 397332U); iowrite32(hdmi_dev->savePCH_PIPEBSRC, (void *)dev_priv->vdc_reg + 12572U); iowrite32(hdmi_dev->savePCH_HTOTAL_B, (void *)dev_priv->vdc_reg + 12544U); iowrite32(hdmi_dev->savePCH_HBLANK_B, (void *)dev_priv->vdc_reg + 12548U); iowrite32(hdmi_dev->savePCH_HSYNC_B, (void *)dev_priv->vdc_reg + 12552U); iowrite32(hdmi_dev->savePCH_VTOTAL_B, (void *)dev_priv->vdc_reg + 12556U); iowrite32(hdmi_dev->savePCH_VBLANK_B, (void *)dev_priv->vdc_reg + 12560U); iowrite32(hdmi_dev->savePCH_VSYNC_B, (void *)dev_priv->vdc_reg + 12564U); iowrite32(pipeb->conf, (void *)dev_priv->vdc_reg + 462856U); iowrite32(hdmi_dev->savePCH_PIPEBCONF, (void *)dev_priv->vdc_reg + 14344U); iowrite32(pipeb->linoff, (void *)dev_priv->vdc_reg + 463236U); iowrite32(pipeb->stride, (void *)dev_priv->vdc_reg + 463240U); iowrite32(pipeb->tileoff, (void *)dev_priv->vdc_reg + 463268U); iowrite32(pipeb->cntr, (void *)dev_priv->vdc_reg + 463232U); iowrite32(pipeb->surf, (void *)dev_priv->vdc_reg + 463260U); iowrite32(regs->saveDSPBCURSOR_CTRL, (void *)dev_priv->vdc_reg + 458944U); iowrite32(regs->saveDSPBCURSOR_POS, (void *)dev_priv->vdc_reg + 458952U); iowrite32(regs->saveDSPBCURSOR_BASE, (void *)dev_priv->vdc_reg + 458948U); i = 0; goto ldv_41739; ldv_41738: iowrite32(pipeb->palette[i], (void *)dev_priv->vdc_reg + (unsigned long )((i << 2) + 43008)); i = i + 1; ldv_41739: ; if (i <= 255) { goto ldv_41738; } else { } return; } } extern int ldv_probe_7(void) ; extern int ldv_probe_6(void) ; void ldv_initialize_drm_connector_helper_funcs_8(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); oaktrail_hdmi_connector_helper_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_initialize_drm_encoder_helper_funcs_9(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(96UL); oaktrail_hdmi_helper_funcs_group0 = (struct drm_encoder *)tmp; tmp___0 = ldv_init_zalloc(208UL); oaktrail_hdmi_helper_funcs_group1 = (struct drm_display_mode *)tmp___0; return; } } void ldv_initialize_drm_connector_funcs_7(void) { void *tmp ; { tmp = ldv_init_zalloc(936UL); oaktrail_hdmi_connector_funcs_group0 = (struct drm_connector *)tmp; return; } } void ldv_main_exported_8(void) { struct drm_display_mode *ldvarg189 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(208UL); ldvarg189 = (struct drm_display_mode *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_8 == 1) { oaktrail_hdmi_get_modes(oaktrail_hdmi_connector_helper_funcs_group0); ldv_state_variable_8 = 1; } else { } goto ldv_41759; case 1: ; if (ldv_state_variable_8 == 1) { oaktrail_hdmi_mode_valid(oaktrail_hdmi_connector_helper_funcs_group0, ldvarg189); ldv_state_variable_8 = 1; } else { } goto ldv_41759; case 2: ; if (ldv_state_variable_8 == 1) { gma_best_encoder(oaktrail_hdmi_connector_helper_funcs_group0); ldv_state_variable_8 = 1; } else { } goto ldv_41759; default: ldv_stop(); } ldv_41759: ; return; } } void ldv_main_exported_6(void) { struct drm_encoder *ldvarg139 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(96UL); ldvarg139 = (struct drm_encoder *)tmp; tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_6 == 2) { oaktrail_hdmi_enc_destroy(ldvarg139); ldv_state_variable_6 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41768; case 1: ; if (ldv_state_variable_6 == 1) { ldv_probe_6(); ldv_state_variable_6 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41768; default: ldv_stop(); } ldv_41768: ; return; } } void ldv_main_exported_7(void) { uint32_t ldvarg6 ; int ldvarg9 ; uint32_t ldvarg7 ; bool ldvarg8 ; int tmp ; { ldv_memset((void *)(& ldvarg6), 0, 4UL); ldv_memset((void *)(& ldvarg9), 0, 4UL); ldv_memset((void *)(& ldvarg7), 0, 4UL); ldv_memset((void *)(& ldvarg8), 0, 1UL); tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ; if (ldv_state_variable_7 == 1) { drm_helper_connector_dpms(oaktrail_hdmi_connector_funcs_group0, ldvarg9); ldv_state_variable_7 = 1; } else { } if (ldv_state_variable_7 == 2) { drm_helper_connector_dpms(oaktrail_hdmi_connector_funcs_group0, ldvarg9); ldv_state_variable_7 = 2; } else { } goto ldv_41779; case 1: ; if (ldv_state_variable_7 == 1) { oaktrail_hdmi_detect(oaktrail_hdmi_connector_funcs_group0, (int )ldvarg8); ldv_state_variable_7 = 1; } else { } if (ldv_state_variable_7 == 2) { oaktrail_hdmi_detect(oaktrail_hdmi_connector_funcs_group0, (int )ldvarg8); ldv_state_variable_7 = 2; } else { } goto ldv_41779; case 2: ; if (ldv_state_variable_7 == 2) { oaktrail_hdmi_destroy(oaktrail_hdmi_connector_funcs_group0); ldv_state_variable_7 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_41779; case 3: ; if (ldv_state_variable_7 == 1) { drm_helper_probe_single_connector_modes(oaktrail_hdmi_connector_funcs_group0, ldvarg7, ldvarg6); ldv_state_variable_7 = 1; } else { } if (ldv_state_variable_7 == 2) { drm_helper_probe_single_connector_modes(oaktrail_hdmi_connector_funcs_group0, ldvarg7, ldvarg6); ldv_state_variable_7 = 2; } else { } goto ldv_41779; case 4: ; if (ldv_state_variable_7 == 1) { ldv_probe_7(); ldv_state_variable_7 = 2; ref_cnt = ref_cnt + 1; } else { } goto ldv_41779; default: ldv_stop(); } ldv_41779: ; return; } } void ldv_main_exported_9(void) { int ldvarg158 ; struct drm_display_mode *ldvarg157 ; void *tmp ; struct drm_display_mode *ldvarg156 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(208UL); ldvarg157 = (struct drm_display_mode *)tmp; tmp___0 = ldv_init_zalloc(208UL); ldvarg156 = (struct drm_display_mode *)tmp___0; ldv_memset((void *)(& ldvarg158), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_9 == 1) { oaktrail_hdmi_dpms(oaktrail_hdmi_helper_funcs_group0, ldvarg158); ldv_state_variable_9 = 1; } else { } goto ldv_41792; case 1: ; if (ldv_state_variable_9 == 1) { gma_encoder_mode_fixup(oaktrail_hdmi_helper_funcs_group0, (struct drm_display_mode const *)ldvarg157, oaktrail_hdmi_helper_funcs_group1); ldv_state_variable_9 = 1; } else { } goto ldv_41792; case 2: ; if (ldv_state_variable_9 == 1) { gma_encoder_commit(oaktrail_hdmi_helper_funcs_group0); ldv_state_variable_9 = 1; } else { } goto ldv_41792; case 3: ; if (ldv_state_variable_9 == 1) { oaktrail_hdmi_mode_set(oaktrail_hdmi_helper_funcs_group0, oaktrail_hdmi_helper_funcs_group1, ldvarg156); ldv_state_variable_9 = 1; } else { } goto ldv_41792; case 4: ; if (ldv_state_variable_9 == 1) { gma_encoder_prepare(oaktrail_hdmi_helper_funcs_group0); ldv_state_variable_9 = 1; } else { } goto ldv_41792; default: ldv_stop(); } ldv_41792: ; return; } } bool ldv_queue_work_on_471(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_472(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_473(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_474(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_475(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; extern void __init_waitqueue_head(wait_queue_head_t * , char const * , struct lock_class_key * ) ; __inline static void init_completion(struct completion *x ) { struct lock_class_key __key ; { x->done = 0U; __init_waitqueue_head(& x->wait, "&x->wait", & __key); return; } } __inline static void reinit_completion(struct completion *x ) { { x->done = 0U; return; } } extern long wait_for_completion_interruptible_timeout(struct completion * , unsigned long ) ; extern void complete(struct completion * ) ; bool ldv_queue_work_on_485(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_487(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_486(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_489(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_488(struct workqueue_struct *ldv_func_arg1 ) ; int reg_check_1(irqreturn_t (*handler)(int , void * ) ) ; void disable_suitable_irq_1(int line , void *data ) ; void activate_suitable_irq_1(int line , void *data ) ; void choose_interrupt_1(void) ; int ldv_irq_1(int state , int line , void *data ) ; __inline static void *i2c_get_adapdata(struct i2c_adapter const *dev ) { void *tmp ; { tmp = dev_get_drvdata(& dev->dev); return (tmp); } } extern int i2c_add_numbered_adapter(struct i2c_adapter * ) ; extern int request_threaded_irq(unsigned int , irqreturn_t (*)(int , void * ) , irqreturn_t (*)(int , void * ) , unsigned long , char const * , void * ) ; __inline static int request_irq(unsigned int irq , irqreturn_t (*handler)(int , void * ) , unsigned long flags , char const *name , void *dev ) { int tmp ; { tmp = request_threaded_irq(irq, handler, (irqreturn_t (*)(int , void * ))0, flags, name, dev); return (tmp); } } __inline static int ldv_request_irq_490(unsigned int irq , irqreturn_t (*handler)(int , void * ) , unsigned long flags , char const *name , void *dev ) ; extern void free_irq(unsigned int , void * ) ; void ldv_free_irq_491(unsigned int ldv_func_arg1 , void *ldv_func_arg2 ) ; static void hdmi_i2c_irq_enable(struct oaktrail_hdmi_dev *hdmi_dev ) { u32 temp ; { temp = readl((void const volatile *)hdmi_dev->regs + 4100U); temp = temp | 28U; writel(temp, (void volatile *)hdmi_dev->regs + 4100U); readl((void const volatile *)hdmi_dev->regs + 4100U); return; } } static void hdmi_i2c_irq_disable(struct oaktrail_hdmi_dev *hdmi_dev ) { { writel(0U, (void volatile *)hdmi_dev->regs + 4100U); readl((void const volatile *)hdmi_dev->regs + 4100U); return; } } static int xfer_read(struct i2c_adapter *adap , struct i2c_msg *pmsg ) { struct oaktrail_hdmi_dev *hdmi_dev ; void *tmp ; struct hdmi_i2c_dev *i2c_dev ; u32 temp ; { tmp = i2c_get_adapdata((struct i2c_adapter const *)adap); hdmi_dev = (struct oaktrail_hdmi_dev *)tmp; i2c_dev = hdmi_dev->i2c_dev; i2c_dev->status = 0; i2c_dev->msg = pmsg; i2c_dev->buf_offset = 0; reinit_completion(& i2c_dev->complete); temp = (u32 )(((int )pmsg->len << 20) | 13); writel(temp, (void volatile *)hdmi_dev->regs + 4672U); readl((void const volatile *)hdmi_dev->regs + 4672U); goto ldv_41564; ldv_41563: wait_for_completion_interruptible_timeout(& i2c_dev->complete, 2500UL); ldv_41564: ; if (i2c_dev->status != 2) { goto ldv_41563; } else { } return (0); } } static int xfer_write(struct i2c_adapter *adap , struct i2c_msg *pmsg ) { { return (0); } } static int oaktrail_hdmi_i2c_access(struct i2c_adapter *adap , struct i2c_msg *pmsg , int num ) { struct oaktrail_hdmi_dev *hdmi_dev ; void *tmp ; struct hdmi_i2c_dev *i2c_dev ; int i ; { tmp = i2c_get_adapdata((struct i2c_adapter const *)adap); hdmi_dev = (struct oaktrail_hdmi_dev *)tmp; i2c_dev = hdmi_dev->i2c_dev; mutex_lock_nested(& i2c_dev->i2c_lock, 0U); writel(34656U, (void volatile *)hdmi_dev->regs + 4352U); hdmi_i2c_irq_enable(hdmi_dev); i = 0; goto ldv_41579; ldv_41578: ; if ((unsigned int )pmsg->len != 0U && (unsigned long )pmsg->buf != (unsigned long )((__u8 *)0U)) { if ((int )pmsg->flags & 1) { xfer_read(adap, pmsg); } else { xfer_write(adap, pmsg); } } else { } pmsg = pmsg + 1; i = i + 1; ldv_41579: ; if (i < num) { goto ldv_41578; } else { } hdmi_i2c_irq_disable(hdmi_dev); mutex_unlock(& i2c_dev->i2c_lock); return (i); } } static u32 oaktrail_hdmi_i2c_func(struct i2c_adapter *adapter ) { { return (3U); } } static struct i2c_algorithm const oaktrail_hdmi_i2c_algorithm = {& oaktrail_hdmi_i2c_access, 0, & oaktrail_hdmi_i2c_func, 0, 0}; static struct i2c_adapter oaktrail_hdmi_i2c_adapter = {& __this_module, 8U, & oaktrail_hdmi_i2c_algorithm, 0, {{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}, {0}, 0, 0, 0, 0, 0, 0, 0}, 0, 0, {0, 0, {0, {0, 0}, 0, 0, 0, 0, {{0}}, {{{0L}, {0, 0}, 0, {0, {0, 0}, 0, 0, 0UL}}, {{0, 0}, 0UL, 0, 0UL, 0U, 0, 0, 0, {(char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0}, {0, {0, 0}, 0, 0, 0UL}}, 0, 0}, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0}, 0, 0, {{0}, {{{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}}}, {0, 0}, 0, 0, {0, {0, 0}, 0, 0, 0UL}}, 0, 0, 0, 0, {{0}, (unsigned char)0, (unsigned char)0, (_Bool)0, (_Bool)0, (_Bool)0, (_Bool)0, (_Bool)0, (_Bool)0, (_Bool)0, {{{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}}}, {0, 0}, {0U, {{{{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}}}, {0, 0}}}, 0, (_Bool)0, (_Bool)0, {{0, 0}, 0UL, 0, 0UL, 0U, 0, 0, 0, {(char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0, (char)0}, {0, {0, 0}, 0, 0, 0UL}}, 0UL, {{0L}, {0, 0}, 0, {0, {0, 0}, 0, 0, 0UL}}, {{{{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}}}, {0, 0}}, 0, {0}, {0}, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, (unsigned char)0, 0, 0, 0, 0, 0UL, 0UL, 0UL, 0UL, 0, 0, 0}, 0, 0, 0, 0, 0ULL, 0UL, 0, {0, 0}, 0, 0, {0, 0}, 0, 0, 0U, 0U, {{{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}}}, {0, 0}, {0, {0, 0}, {{0}}}, 0, 0, 0, 0, (_Bool)0, (_Bool)0}, 3, {'o', 'a', 'k', 't', 'r', 'a', 'i', 'l', '_', 'h', 'd', 'm', 'i', '_', 'i', '2', 'c', '\000'}, {0U, {{{{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}}}, {0, 0}}}, {{0}, {{{{{0}}, 0U, 0U, 0, {0, {0, 0}, 0, 0, 0UL}}}}, {0, 0}, 0, 0, {0, {0, 0}, 0, 0, 0UL}}, {0, 0}, 0, 0}; static void hdmi_i2c_read(struct oaktrail_hdmi_dev *hdmi_dev ) { struct hdmi_i2c_dev *i2c_dev ; struct i2c_msg *msg ; u8 *buf ; u32 temp ; int i ; int offset ; { i2c_dev = hdmi_dev->i2c_dev; msg = i2c_dev->msg; buf = msg->buf; offset = i2c_dev->buf_offset; i = 0; goto ldv_41596; ldv_41595: temp = readl((void const volatile *)hdmi_dev->regs + (unsigned long )((i + 1152) * 4)); memcpy((void *)buf + (unsigned long )(i * 4 + offset), (void const *)(& temp), 4UL); i = i + 1; ldv_41596: ; if (i <= 15) { goto ldv_41595; } else { } i2c_dev->buf_offset = i2c_dev->buf_offset + 64; temp = readl((void const volatile *)hdmi_dev->regs + 4108U); writel(temp | 8U, (void volatile *)hdmi_dev->regs + 4108U); readl((void const volatile *)hdmi_dev->regs + 4108U); temp = readl((void const volatile *)hdmi_dev->regs + 4672U); writel(temp | 2U, (void volatile *)hdmi_dev->regs + 4672U); readl((void const volatile *)hdmi_dev->regs + 4672U); i2c_dev->status = 1; return; } } static void hdmi_i2c_transaction_done(struct oaktrail_hdmi_dev *hdmi_dev ) { struct hdmi_i2c_dev *i2c_dev ; u32 temp ; { i2c_dev = hdmi_dev->i2c_dev; temp = readl((void const volatile *)hdmi_dev->regs + 4108U); writel(temp | 4U, (void volatile *)hdmi_dev->regs + 4108U); readl((void const volatile *)hdmi_dev->regs + 4108U); temp = readl((void const volatile *)hdmi_dev->regs + 4672U); writel(temp & 4294967294U, (void volatile *)hdmi_dev->regs + 4672U); readl((void const volatile *)hdmi_dev->regs + 4672U); i2c_dev->status = 2; return; } } static irqreturn_t oaktrail_hdmi_i2c_handler(int this_irq , void *dev ) { struct oaktrail_hdmi_dev *hdmi_dev ; struct hdmi_i2c_dev *i2c_dev ; u32 stat ; { hdmi_dev = (struct oaktrail_hdmi_dev *)dev; i2c_dev = hdmi_dev->i2c_dev; stat = readl((void const volatile *)hdmi_dev->regs + 4108U); if ((int )stat & 1) { writel(stat | 1U, (void volatile *)hdmi_dev->regs + 4108U); readl((void const volatile *)hdmi_dev->regs + 4108U); } else { } if ((stat & 8U) != 0U) { hdmi_i2c_read(hdmi_dev); } else { } if ((stat & 4U) != 0U) { hdmi_i2c_transaction_done(hdmi_dev); } else { } complete(& i2c_dev->complete); return (1); } } static void oaktrail_hdmi_i2c_gpio_fix(void) { void *base ; unsigned int gpio_base ; int gpio_len ; u32 temp ; long tmp ; long tmp___0 ; { gpio_base = 4279418880U; gpio_len = 4096; base = ioremap((unsigned long long )gpio_base, (unsigned long )gpio_len); if ((unsigned long )base == (unsigned long )((void *)0)) { drm_err("gpio ioremap fail\n"); return; } else { } temp = readl((void const volatile *)base + 68U); tmp = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp != 0L) { drm_ut_debug_printk("oaktrail_hdmi_i2c_gpio_fix", "old gpio val %x\n", temp); } else { } writel(temp | 2560U, (void volatile *)base + 68U); temp = readl((void const volatile *)base + 68U); tmp___0 = ldv__builtin_expect((drm_debug & 2U) != 0U, 0L); if (tmp___0 != 0L) { drm_ut_debug_printk("oaktrail_hdmi_i2c_gpio_fix", "new gpio val %x\n", temp); } else { } iounmap((void volatile *)base); return; } } int oaktrail_hdmi_i2c_init(struct pci_dev *dev ) { struct oaktrail_hdmi_dev *hdmi_dev ; struct hdmi_i2c_dev *i2c_dev ; int ret ; void *tmp ; void *tmp___0 ; struct lock_class_key __key ; { tmp = pci_get_drvdata(dev); hdmi_dev = (struct oaktrail_hdmi_dev *)tmp; tmp___0 = kzalloc(288UL, 208U); i2c_dev = (struct hdmi_i2c_dev *)tmp___0; if ((unsigned long )i2c_dev == (unsigned long )((struct hdmi_i2c_dev *)0)) { drm_err("Can\'t allocate interface\n"); ret = -12; goto exit; } else { } i2c_dev->adap = & oaktrail_hdmi_i2c_adapter; i2c_dev->status = 0; init_completion(& i2c_dev->complete); __mutex_init(& i2c_dev->i2c_lock, "&i2c_dev->i2c_lock", & __key); i2c_set_adapdata(& oaktrail_hdmi_i2c_adapter, (void *)hdmi_dev); hdmi_dev->i2c_dev = i2c_dev; oaktrail_hdmi_i2c_gpio_fix(); ret = ldv_request_irq_490(dev->irq, & oaktrail_hdmi_i2c_handler, 128UL, (char const *)(& oaktrail_hdmi_i2c_adapter.name), (void *)hdmi_dev); if (ret != 0) { drm_err("Failed to request IRQ for I2C controller\n"); goto err; } else { } ret = i2c_add_numbered_adapter(& oaktrail_hdmi_i2c_adapter); return (ret); err: kfree((void const *)i2c_dev); exit: ; return (ret); } } void oaktrail_hdmi_i2c_exit(struct pci_dev *dev ) { struct oaktrail_hdmi_dev *hdmi_dev ; struct hdmi_i2c_dev *i2c_dev ; void *tmp ; { tmp = pci_get_drvdata(dev); hdmi_dev = (struct oaktrail_hdmi_dev *)tmp; i2c_del_adapter(& oaktrail_hdmi_i2c_adapter); i2c_dev = hdmi_dev->i2c_dev; kfree((void const *)i2c_dev); ldv_free_irq_491(dev->irq, (void *)hdmi_dev); return; } } int reg_check_1(irqreturn_t (*handler)(int , void * ) ) { { if ((unsigned long )handler == (unsigned long )(& oaktrail_hdmi_i2c_handler)) { return (1); } else { } return (0); } } void disable_suitable_irq_1(int line , void *data ) { { if (ldv_irq_1_0 != 0 && line == ldv_irq_line_1_0) { ldv_irq_1_0 = 0; return; } else { } if (ldv_irq_1_1 != 0 && line == ldv_irq_line_1_1) { ldv_irq_1_1 = 0; return; } else { } if (ldv_irq_1_2 != 0 && line == ldv_irq_line_1_2) { ldv_irq_1_2 = 0; return; } else { } if (ldv_irq_1_3 != 0 && line == ldv_irq_line_1_3) { ldv_irq_1_3 = 0; return; } else { } return; } } void activate_suitable_irq_1(int line , void *data ) { { if (ldv_irq_1_0 == 0) { ldv_irq_line_1_0 = line; ldv_irq_data_1_0 = data; ldv_irq_1_0 = 1; return; } else { } if (ldv_irq_1_1 == 0) { ldv_irq_line_1_1 = line; ldv_irq_data_1_1 = data; ldv_irq_1_1 = 1; return; } else { } if (ldv_irq_1_2 == 0) { ldv_irq_line_1_2 = line; ldv_irq_data_1_2 = data; ldv_irq_1_2 = 1; return; } else { } if (ldv_irq_1_3 == 0) { ldv_irq_line_1_3 = line; ldv_irq_data_1_3 = data; ldv_irq_1_3 = 1; return; } else { } return; } } void choose_interrupt_1(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ldv_irq_1_0 = ldv_irq_1(ldv_irq_1_0, ldv_irq_line_1_0, ldv_irq_data_1_0); goto ldv_41649; case 1: ldv_irq_1_0 = ldv_irq_1(ldv_irq_1_1, ldv_irq_line_1_1, ldv_irq_data_1_1); goto ldv_41649; case 2: ldv_irq_1_0 = ldv_irq_1(ldv_irq_1_2, ldv_irq_line_1_2, ldv_irq_data_1_2); goto ldv_41649; case 3: ldv_irq_1_0 = ldv_irq_1(ldv_irq_1_3, ldv_irq_line_1_3, ldv_irq_data_1_3); goto ldv_41649; default: ldv_stop(); } ldv_41649: ; return; } } void ldv_initialize_i2c_algorithm_5(void) { void *tmp ; { tmp = ldv_init_zalloc(1936UL); oaktrail_hdmi_i2c_algorithm_group0 = (struct i2c_adapter *)tmp; return; } } int ldv_irq_1(int state , int line , void *data ) { irqreturn_t irq_retval ; int tmp ; int tmp___0 ; { tmp = __VERIFIER_nondet_int(); irq_retval = (irqreturn_t )tmp; if (state != 0) { tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (state == 1) { LDV_IN_INTERRUPT = 2; irq_retval = oaktrail_hdmi_i2c_handler(line, data); LDV_IN_INTERRUPT = 1; return (state); } else { } goto ldv_41664; default: ldv_stop(); } ldv_41664: ; } else { } return (state); } } void ldv_main_exported_5(void) { int ldvarg216 ; struct i2c_msg *ldvarg217 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(16UL); ldvarg217 = (struct i2c_msg *)tmp; ldv_memset((void *)(& ldvarg216), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_5 == 1) { oaktrail_hdmi_i2c_access(oaktrail_hdmi_i2c_algorithm_group0, ldvarg217, ldvarg216); ldv_state_variable_5 = 1; } else { } goto ldv_41672; case 1: ; if (ldv_state_variable_5 == 1) { oaktrail_hdmi_i2c_func(oaktrail_hdmi_i2c_algorithm_group0); ldv_state_variable_5 = 1; } else { } goto ldv_41672; default: ldv_stop(); } ldv_41672: ; return; } } bool ldv_queue_work_on_485(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_486(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_487(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_488(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_489(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static int ldv_request_irq_490(unsigned int irq , irqreturn_t (*handler)(int , void * ) , unsigned long flags , char const *name , void *dev ) { ldv_func_ret_type___3 ldv_func_res ; int tmp ; int tmp___0 ; { tmp = request_irq(irq, handler, flags, name, dev); ldv_func_res = tmp; tmp___0 = reg_check_1(handler); if (tmp___0 != 0 && ldv_func_res == 0) { activate_suitable_irq_1((int )irq, dev); } else { } return (ldv_func_res); } } void ldv_free_irq_491(unsigned int ldv_func_arg1 , void *ldv_func_arg2 ) { { free_irq(ldv_func_arg1, ldv_func_arg2); disable_suitable_irq_1((int )ldv_func_arg1, ldv_func_arg2); return; } } extern void *memset(void * , int , size_t ) ; __inline static void ldv_error(void) { { ERROR: ; __VERIFIER_error(); } } bool ldv_is_err(void const *ptr ) { { return ((unsigned long )ptr > 2012UL); } } void *ldv_err_ptr(long error ) { { return ((void *)(2012L - error)); } } long ldv_ptr_err(void const *ptr ) { { return ((long )(2012UL - (unsigned long )ptr)); } } bool ldv_is_err_or_null(void const *ptr ) { bool tmp ; int tmp___0 ; { if ((unsigned long )ptr == (unsigned long )((void const *)0)) { tmp___0 = 1; } else { tmp = ldv_is_err(ptr); if ((int )tmp) { tmp___0 = 1; } else { tmp___0 = 0; } } return ((bool )tmp___0); } } int ldv_module_refcounter = 1; void ldv_module_get(struct module *module ) { { if ((unsigned long )module != (unsigned long )((struct module *)0)) { ldv_module_refcounter = ldv_module_refcounter + 1; } else { } return; } } int ldv_try_module_get(struct module *module ) { int module_get_succeeded ; { if ((unsigned long )module != (unsigned long )((struct module *)0)) { module_get_succeeded = ldv_undef_int(); if (module_get_succeeded == 1) { ldv_module_refcounter = ldv_module_refcounter + 1; return (1); } else { return (0); } } else { } return (0); } } void ldv_module_put(struct module *module ) { { if ((unsigned long )module != (unsigned long )((struct module *)0)) { if (ldv_module_refcounter <= 1) { ldv_error(); } else { } ldv_module_refcounter = ldv_module_refcounter - 1; } else { } return; } } void ldv_module_put_and_exit(void) { { ldv_module_put((struct module *)1); LDV_STOP: ; goto LDV_STOP; } } unsigned int ldv_module_refcount(void) { { return ((unsigned int )(ldv_module_refcounter + -1)); } } void ldv_check_final_state(void) { { if (ldv_module_refcounter != 1) { ldv_error(); } else { } return; } }