extern void __VERIFIER_error() __attribute__ ((__noreturn__)); /* Generated by CIL v. 1.5.1 */ /* print_CIL_Input is false */ typedef unsigned char __u8; typedef unsigned short __u16; typedef int __s32; typedef unsigned int __u32; typedef unsigned long long __u64; typedef signed char s8; typedef unsigned char u8; typedef short s16; typedef unsigned short u16; typedef int s32; typedef unsigned int u32; typedef long long s64; typedef unsigned long long u64; typedef long __kernel_long_t; typedef unsigned long __kernel_ulong_t; typedef int __kernel_pid_t; typedef unsigned int __kernel_uid32_t; typedef unsigned int __kernel_gid32_t; typedef __kernel_ulong_t __kernel_size_t; typedef __kernel_long_t __kernel_ssize_t; typedef long long __kernel_loff_t; typedef __kernel_long_t __kernel_time_t; typedef __kernel_long_t __kernel_clock_t; typedef int __kernel_timer_t; typedef int __kernel_clockid_t; typedef __u16 __le16; typedef __u16 __be16; typedef __u32 __le32; typedef __u32 __be32; typedef __u32 __wsum; struct kernel_symbol { unsigned long value ; char const *name ; }; struct module; typedef __u32 __kernel_dev_t; typedef __kernel_dev_t dev_t; typedef unsigned short umode_t; typedef __kernel_pid_t pid_t; typedef __kernel_clockid_t clockid_t; typedef _Bool bool; typedef __kernel_uid32_t uid_t; typedef __kernel_gid32_t gid_t; typedef __kernel_loff_t loff_t; typedef __kernel_size_t size_t; typedef __kernel_ssize_t ssize_t; typedef __kernel_time_t time_t; typedef unsigned int uint; typedef __s32 int32_t; typedef __u8 uint8_t; typedef __u32 uint32_t; typedef __u64 uint64_t; typedef unsigned long sector_t; typedef unsigned long blkcnt_t; typedef u64 dma_addr_t; typedef unsigned int gfp_t; typedef unsigned int fmode_t; typedef unsigned int oom_flags_t; typedef u64 phys_addr_t; typedef phys_addr_t resource_size_t; typedef unsigned long irq_hw_number_t; struct __anonstruct_atomic_t_6 { int counter ; }; typedef struct __anonstruct_atomic_t_6 atomic_t; struct __anonstruct_atomic64_t_7 { long counter ; }; typedef struct __anonstruct_atomic64_t_7 atomic64_t; struct list_head { struct list_head *next ; struct list_head *prev ; }; struct hlist_node; struct hlist_head { struct hlist_node *first ; }; struct hlist_node { struct hlist_node *next ; struct hlist_node **pprev ; }; struct callback_head { struct callback_head *next ; void (*func)(struct callback_head * ) ; }; struct pt_regs { unsigned long r15 ; unsigned long r14 ; unsigned long r13 ; unsigned long r12 ; unsigned long bp ; unsigned long bx ; unsigned long r11 ; unsigned long r10 ; unsigned long r9 ; unsigned long r8 ; unsigned long ax ; unsigned long cx ; unsigned long dx ; unsigned long si ; unsigned long di ; unsigned long orig_ax ; unsigned long ip ; unsigned long cs ; unsigned long flags ; unsigned long sp ; unsigned long ss ; }; struct __anonstruct____missing_field_name_9 { unsigned int a ; unsigned int b ; }; struct __anonstruct____missing_field_name_10 { u16 limit0 ; u16 base0 ; unsigned char base1 ; unsigned char type : 4 ; unsigned char s : 1 ; unsigned char dpl : 2 ; unsigned char p : 1 ; unsigned char limit : 4 ; unsigned char avl : 1 ; unsigned char l : 1 ; unsigned char d : 1 ; unsigned char g : 1 ; unsigned char base2 ; }; union __anonunion____missing_field_name_8 { struct __anonstruct____missing_field_name_9 __annonCompField4 ; struct __anonstruct____missing_field_name_10 __annonCompField5 ; }; struct desc_struct { union __anonunion____missing_field_name_8 __annonCompField6 ; }; typedef unsigned long pteval_t; typedef unsigned long pgdval_t; typedef unsigned long pgprotval_t; struct __anonstruct_pte_t_11 { pteval_t pte ; }; typedef struct __anonstruct_pte_t_11 pte_t; struct pgprot { pgprotval_t pgprot ; }; typedef struct pgprot pgprot_t; struct __anonstruct_pgd_t_12 { pgdval_t pgd ; }; typedef struct __anonstruct_pgd_t_12 pgd_t; struct page; typedef struct page *pgtable_t; struct file; struct seq_file; struct thread_struct; struct mm_struct; struct task_struct; struct cpumask; struct qspinlock { atomic_t val ; }; typedef struct qspinlock arch_spinlock_t; struct qrwlock { atomic_t cnts ; arch_spinlock_t lock ; }; typedef struct qrwlock arch_rwlock_t; typedef void (*ctor_fn_t)(void); struct device; struct net_device; struct file_operations; struct completion; struct bug_entry { int bug_addr_disp ; int file_disp ; unsigned short line ; unsigned short flags ; }; struct timespec; struct compat_timespec; struct __anonstruct_futex_16 { u32 *uaddr ; u32 val ; u32 flags ; u32 bitset ; u64 time ; u32 *uaddr2 ; }; struct __anonstruct_nanosleep_17 { clockid_t clockid ; struct timespec *rmtp ; struct compat_timespec *compat_rmtp ; u64 expires ; }; struct pollfd; struct __anonstruct_poll_18 { struct pollfd *ufds ; int nfds ; int has_timeout ; unsigned long tv_sec ; unsigned long tv_nsec ; }; union __anonunion____missing_field_name_15 { struct __anonstruct_futex_16 futex ; struct __anonstruct_nanosleep_17 nanosleep ; struct __anonstruct_poll_18 poll ; }; struct restart_block { long (*fn)(struct restart_block * ) ; union __anonunion____missing_field_name_15 __annonCompField7 ; }; struct kernel_vm86_regs { struct pt_regs pt ; unsigned short es ; unsigned short __esh ; unsigned short ds ; unsigned short __dsh ; unsigned short fs ; unsigned short __fsh ; unsigned short gs ; unsigned short __gsh ; }; union __anonunion____missing_field_name_19 { struct pt_regs *regs ; struct kernel_vm86_regs *vm86 ; }; struct math_emu_info { long ___orig_eip ; union __anonunion____missing_field_name_19 __annonCompField8 ; }; struct cpumask { unsigned long bits[128U] ; }; typedef struct cpumask cpumask_t; typedef struct cpumask *cpumask_var_t; struct fregs_state { u32 cwd ; u32 swd ; u32 twd ; u32 fip ; u32 fcs ; u32 foo ; u32 fos ; u32 st_space[20U] ; u32 status ; }; struct __anonstruct____missing_field_name_29 { u64 rip ; u64 rdp ; }; struct __anonstruct____missing_field_name_30 { u32 fip ; u32 fcs ; u32 foo ; u32 fos ; }; union __anonunion____missing_field_name_28 { struct __anonstruct____missing_field_name_29 __annonCompField12 ; struct __anonstruct____missing_field_name_30 __annonCompField13 ; }; union __anonunion____missing_field_name_31 { u32 padding1[12U] ; u32 sw_reserved[12U] ; }; struct fxregs_state { u16 cwd ; u16 swd ; u16 twd ; u16 fop ; union __anonunion____missing_field_name_28 __annonCompField14 ; u32 mxcsr ; u32 mxcsr_mask ; u32 st_space[32U] ; u32 xmm_space[64U] ; u32 padding[12U] ; union __anonunion____missing_field_name_31 __annonCompField15 ; }; struct swregs_state { u32 cwd ; u32 swd ; u32 twd ; u32 fip ; u32 fcs ; u32 foo ; u32 fos ; u32 st_space[20U] ; u8 ftop ; u8 changed ; u8 lookahead ; u8 no_update ; u8 rm ; u8 alimit ; struct math_emu_info *info ; u32 entry_eip ; }; struct xstate_header { u64 xfeatures ; u64 xcomp_bv ; u64 reserved[6U] ; }; struct xregs_state { struct fxregs_state i387 ; struct xstate_header header ; u8 __reserved[464U] ; }; union fpregs_state { struct fregs_state fsave ; struct fxregs_state fxsave ; struct swregs_state soft ; struct xregs_state xsave ; }; struct fpu { union fpregs_state state ; unsigned int last_cpu ; unsigned char fpstate_active ; unsigned char fpregs_active ; unsigned char counter ; }; struct seq_operations; struct perf_event; struct thread_struct { struct desc_struct tls_array[3U] ; unsigned long sp0 ; unsigned long sp ; unsigned short es ; unsigned short ds ; unsigned short fsindex ; unsigned short gsindex ; unsigned long fs ; unsigned long gs ; struct fpu fpu ; struct perf_event *ptrace_bps[4U] ; unsigned long debugreg6 ; unsigned long ptrace_dr7 ; unsigned long cr2 ; unsigned long trap_nr ; unsigned long error_code ; unsigned long *io_bitmap_ptr ; unsigned long iopl ; unsigned int io_bitmap_max ; }; typedef atomic64_t atomic_long_t; struct lockdep_map; struct stack_trace { unsigned int nr_entries ; unsigned int max_entries ; unsigned long *entries ; int skip ; }; struct lockdep_subclass_key { char __one_byte ; }; struct lock_class_key { struct lockdep_subclass_key subkeys[8U] ; }; struct lock_class { struct list_head hash_entry ; struct list_head lock_entry ; struct lockdep_subclass_key *key ; unsigned int subclass ; unsigned int dep_gen_id ; unsigned long usage_mask ; struct stack_trace usage_traces[13U] ; struct list_head locks_after ; struct list_head locks_before ; unsigned int version ; unsigned long ops ; char const *name ; int name_version ; unsigned long contention_point[4U] ; unsigned long contending_point[4U] ; }; struct lockdep_map { struct lock_class_key *key ; struct lock_class *class_cache[2U] ; char const *name ; int cpu ; unsigned long ip ; }; struct held_lock { u64 prev_chain_key ; unsigned long acquire_ip ; struct lockdep_map *instance ; struct lockdep_map *nest_lock ; u64 waittime_stamp ; u64 holdtime_stamp ; unsigned short class_idx : 13 ; unsigned char irq_context : 2 ; unsigned char trylock : 1 ; unsigned char read : 2 ; unsigned char check : 1 ; unsigned char hardirqs_off : 1 ; unsigned short references : 12 ; unsigned int pin_count ; }; struct raw_spinlock { arch_spinlock_t raw_lock ; unsigned int magic ; unsigned int owner_cpu ; void *owner ; struct lockdep_map dep_map ; }; typedef struct raw_spinlock raw_spinlock_t; struct __anonstruct____missing_field_name_35 { u8 __padding[24U] ; struct lockdep_map dep_map ; }; union __anonunion____missing_field_name_34 { struct raw_spinlock rlock ; struct __anonstruct____missing_field_name_35 __annonCompField17 ; }; struct spinlock { union __anonunion____missing_field_name_34 __annonCompField18 ; }; typedef struct spinlock spinlock_t; struct __anonstruct_rwlock_t_36 { arch_rwlock_t raw_lock ; unsigned int magic ; unsigned int owner_cpu ; void *owner ; struct lockdep_map dep_map ; }; typedef struct __anonstruct_rwlock_t_36 rwlock_t; struct seqcount { unsigned int sequence ; struct lockdep_map dep_map ; }; typedef struct seqcount seqcount_t; struct __anonstruct_seqlock_t_45 { struct seqcount seqcount ; spinlock_t lock ; }; typedef struct __anonstruct_seqlock_t_45 seqlock_t; struct timespec { __kernel_time_t tv_sec ; long tv_nsec ; }; struct user_namespace; struct __anonstruct_kuid_t_46 { uid_t val ; }; typedef struct __anonstruct_kuid_t_46 kuid_t; struct __anonstruct_kgid_t_47 { gid_t val ; }; typedef struct __anonstruct_kgid_t_47 kgid_t; struct kstat { u64 ino ; dev_t dev ; umode_t mode ; unsigned int nlink ; kuid_t uid ; kgid_t gid ; dev_t rdev ; loff_t size ; struct timespec atime ; struct timespec mtime ; struct timespec ctime ; unsigned long blksize ; unsigned long long blocks ; }; struct vm_area_struct; struct __wait_queue; typedef struct __wait_queue wait_queue_t; struct __wait_queue { unsigned int flags ; void *private ; int (*func)(wait_queue_t * , unsigned int , int , void * ) ; struct list_head task_list ; }; struct __wait_queue_head { spinlock_t lock ; struct list_head task_list ; }; typedef struct __wait_queue_head wait_queue_head_t; struct __anonstruct_nodemask_t_48 { unsigned long bits[16U] ; }; typedef struct __anonstruct_nodemask_t_48 nodemask_t; struct optimistic_spin_queue { atomic_t tail ; }; struct mutex { atomic_t count ; spinlock_t wait_lock ; struct list_head wait_list ; struct task_struct *owner ; void *magic ; struct lockdep_map dep_map ; }; struct mutex_waiter { struct list_head list ; struct task_struct *task ; void *magic ; }; struct rw_semaphore; struct rw_semaphore { long count ; struct list_head wait_list ; raw_spinlock_t wait_lock ; struct optimistic_spin_queue osq ; struct task_struct *owner ; struct lockdep_map dep_map ; }; struct completion { unsigned int done ; wait_queue_head_t wait ; }; union ktime { s64 tv64 ; }; typedef union ktime ktime_t; struct notifier_block; struct timer_list { struct hlist_node entry ; unsigned long expires ; void (*function)(unsigned long ) ; unsigned long data ; u32 flags ; int slack ; int start_pid ; void *start_site ; char start_comm[16U] ; struct lockdep_map lockdep_map ; }; struct hrtimer; enum hrtimer_restart; struct rb_node { unsigned long __rb_parent_color ; struct rb_node *rb_right ; struct rb_node *rb_left ; }; struct rb_root { struct rb_node *rb_node ; }; struct ctl_table; struct nsproxy; struct ctl_table_root; struct ctl_table_header; struct ctl_dir; typedef int proc_handler(struct ctl_table * , int , void * , size_t * , loff_t * ); struct ctl_table_poll { atomic_t event ; wait_queue_head_t wait ; }; struct ctl_table { char const *procname ; void *data ; int maxlen ; umode_t mode ; struct ctl_table *child ; proc_handler *proc_handler ; struct ctl_table_poll *poll ; void *extra1 ; void *extra2 ; }; struct ctl_node { struct rb_node node ; struct ctl_table_header *header ; }; struct __anonstruct____missing_field_name_50 { struct ctl_table *ctl_table ; int used ; int count ; int nreg ; }; union __anonunion____missing_field_name_49 { struct __anonstruct____missing_field_name_50 __annonCompField19 ; struct callback_head rcu ; }; struct ctl_table_set; struct ctl_table_header { union __anonunion____missing_field_name_49 __annonCompField20 ; struct completion *unregistering ; struct ctl_table *ctl_table_arg ; struct ctl_table_root *root ; struct ctl_table_set *set ; struct ctl_dir *parent ; struct ctl_node *node ; }; struct ctl_dir { struct ctl_table_header header ; struct rb_root root ; }; struct ctl_table_set { int (*is_seen)(struct ctl_table_set * ) ; struct ctl_dir dir ; }; struct ctl_table_root { struct ctl_table_set default_set ; struct ctl_table_set *(*lookup)(struct ctl_table_root * , struct nsproxy * ) ; int (*permissions)(struct ctl_table_header * , struct ctl_table * ) ; }; struct workqueue_struct; struct work_struct; struct work_struct { atomic_long_t data ; struct list_head entry ; void (*func)(struct work_struct * ) ; struct lockdep_map lockdep_map ; }; struct delayed_work { struct work_struct work ; struct timer_list timer ; struct workqueue_struct *wq ; int cpu ; }; struct notifier_block { int (*notifier_call)(struct notifier_block * , unsigned long , void * ) ; struct notifier_block *next ; int priority ; }; struct resource { resource_size_t start ; resource_size_t end ; char const *name ; unsigned long flags ; struct resource *parent ; struct resource *sibling ; struct resource *child ; }; struct pci_dev; struct pm_message { int event ; }; typedef struct pm_message pm_message_t; struct dev_pm_ops { int (*prepare)(struct device * ) ; void (*complete)(struct device * ) ; int (*suspend)(struct device * ) ; int (*resume)(struct device * ) ; int (*freeze)(struct device * ) ; int (*thaw)(struct device * ) ; int (*poweroff)(struct device * ) ; int (*restore)(struct device * ) ; int (*suspend_late)(struct device * ) ; int (*resume_early)(struct device * ) ; int (*freeze_late)(struct device * ) ; int (*thaw_early)(struct device * ) ; int (*poweroff_late)(struct device * ) ; int (*restore_early)(struct device * ) ; int (*suspend_noirq)(struct device * ) ; int (*resume_noirq)(struct device * ) ; int (*freeze_noirq)(struct device * ) ; int (*thaw_noirq)(struct device * ) ; int (*poweroff_noirq)(struct device * ) ; int (*restore_noirq)(struct device * ) ; int (*runtime_suspend)(struct device * ) ; int (*runtime_resume)(struct device * ) ; int (*runtime_idle)(struct device * ) ; }; enum rpm_status { RPM_ACTIVE = 0, RPM_RESUMING = 1, RPM_SUSPENDED = 2, RPM_SUSPENDING = 3 } ; enum rpm_request { RPM_REQ_NONE = 0, RPM_REQ_IDLE = 1, RPM_REQ_SUSPEND = 2, RPM_REQ_AUTOSUSPEND = 3, RPM_REQ_RESUME = 4 } ; struct wakeup_source; struct wake_irq; struct pm_subsys_data { spinlock_t lock ; unsigned int refcount ; struct list_head clock_list ; }; struct dev_pm_qos; struct dev_pm_info { pm_message_t power_state ; unsigned char can_wakeup : 1 ; unsigned char async_suspend : 1 ; bool is_prepared ; bool is_suspended ; bool is_noirq_suspended ; bool is_late_suspended ; bool ignore_children ; bool early_init ; bool direct_complete ; spinlock_t lock ; struct list_head entry ; struct completion completion ; struct wakeup_source *wakeup ; bool wakeup_path ; bool syscore ; struct timer_list suspend_timer ; unsigned long timer_expires ; struct work_struct work ; wait_queue_head_t wait_queue ; struct wake_irq *wakeirq ; atomic_t usage_count ; atomic_t child_count ; unsigned char disable_depth : 3 ; unsigned char idle_notification : 1 ; unsigned char request_pending : 1 ; unsigned char deferred_resume : 1 ; unsigned char run_wake : 1 ; unsigned char runtime_auto : 1 ; unsigned char no_callbacks : 1 ; unsigned char irq_safe : 1 ; unsigned char use_autosuspend : 1 ; unsigned char timer_autosuspends : 1 ; unsigned char memalloc_noio : 1 ; enum rpm_request request ; enum rpm_status runtime_status ; int runtime_error ; int autosuspend_delay ; unsigned long last_busy ; unsigned long active_jiffies ; unsigned long suspended_jiffies ; unsigned long accounting_timestamp ; struct pm_subsys_data *subsys_data ; void (*set_latency_tolerance)(struct device * , s32 ) ; struct dev_pm_qos *qos ; }; struct dev_pm_domain { struct dev_pm_ops ops ; void (*detach)(struct device * , bool ) ; int (*activate)(struct device * ) ; void (*sync)(struct device * ) ; void (*dismiss)(struct device * ) ; }; struct pci_bus; struct __anonstruct_mm_context_t_115 { void *ldt ; int size ; unsigned short ia32_compat ; struct mutex lock ; void *vdso ; atomic_t perf_rdpmc_allowed ; }; typedef struct __anonstruct_mm_context_t_115 mm_context_t; struct bio_vec; struct llist_node; struct llist_node { struct llist_node *next ; }; struct cred; struct inode; struct arch_uprobe_task { unsigned long saved_scratch_register ; unsigned int saved_trap_nr ; unsigned int saved_tf ; }; enum uprobe_task_state { UTASK_RUNNING = 0, UTASK_SSTEP = 1, UTASK_SSTEP_ACK = 2, UTASK_SSTEP_TRAPPED = 3 } ; struct __anonstruct____missing_field_name_148 { struct arch_uprobe_task autask ; unsigned long vaddr ; }; struct __anonstruct____missing_field_name_149 { struct callback_head dup_xol_work ; unsigned long dup_xol_addr ; }; union __anonunion____missing_field_name_147 { struct __anonstruct____missing_field_name_148 __annonCompField33 ; struct __anonstruct____missing_field_name_149 __annonCompField34 ; }; struct uprobe; struct return_instance; struct uprobe_task { enum uprobe_task_state state ; union __anonunion____missing_field_name_147 __annonCompField35 ; struct uprobe *active_uprobe ; unsigned long xol_vaddr ; struct return_instance *return_instances ; unsigned int depth ; }; struct xol_area; struct uprobes_state { struct xol_area *xol_area ; }; struct address_space; struct mem_cgroup; typedef void compound_page_dtor(struct page * ); union __anonunion____missing_field_name_150 { struct address_space *mapping ; void *s_mem ; }; union __anonunion____missing_field_name_152 { unsigned long index ; void *freelist ; bool pfmemalloc ; }; struct __anonstruct____missing_field_name_156 { unsigned short inuse ; unsigned short objects : 15 ; unsigned char frozen : 1 ; }; union __anonunion____missing_field_name_155 { atomic_t _mapcount ; struct __anonstruct____missing_field_name_156 __annonCompField38 ; int units ; }; struct __anonstruct____missing_field_name_154 { union __anonunion____missing_field_name_155 __annonCompField39 ; atomic_t _count ; }; union __anonunion____missing_field_name_153 { unsigned long counters ; struct __anonstruct____missing_field_name_154 __annonCompField40 ; unsigned int active ; }; struct __anonstruct____missing_field_name_151 { union __anonunion____missing_field_name_152 __annonCompField37 ; union __anonunion____missing_field_name_153 __annonCompField41 ; }; struct __anonstruct____missing_field_name_158 { struct page *next ; int pages ; int pobjects ; }; struct slab; struct __anonstruct____missing_field_name_159 { compound_page_dtor *compound_dtor ; unsigned long compound_order ; }; union __anonunion____missing_field_name_157 { struct list_head lru ; struct __anonstruct____missing_field_name_158 __annonCompField43 ; struct slab *slab_page ; struct callback_head callback_head ; struct __anonstruct____missing_field_name_159 __annonCompField44 ; pgtable_t pmd_huge_pte ; }; struct kmem_cache; union __anonunion____missing_field_name_160 { unsigned long private ; spinlock_t *ptl ; struct kmem_cache *slab_cache ; struct page *first_page ; }; struct page { unsigned long flags ; union __anonunion____missing_field_name_150 __annonCompField36 ; struct __anonstruct____missing_field_name_151 __annonCompField42 ; union __anonunion____missing_field_name_157 __annonCompField45 ; union __anonunion____missing_field_name_160 __annonCompField46 ; struct mem_cgroup *mem_cgroup ; }; struct page_frag { struct page *page ; __u32 offset ; __u32 size ; }; struct __anonstruct_shared_161 { struct rb_node rb ; unsigned long rb_subtree_last ; }; struct anon_vma; struct vm_operations_struct; struct mempolicy; struct vm_area_struct { unsigned long vm_start ; unsigned long vm_end ; struct vm_area_struct *vm_next ; struct vm_area_struct *vm_prev ; struct rb_node vm_rb ; unsigned long rb_subtree_gap ; struct mm_struct *vm_mm ; pgprot_t vm_page_prot ; unsigned long vm_flags ; struct __anonstruct_shared_161 shared ; struct list_head anon_vma_chain ; struct anon_vma *anon_vma ; struct vm_operations_struct const *vm_ops ; unsigned long vm_pgoff ; struct file *vm_file ; void *vm_private_data ; struct mempolicy *vm_policy ; }; struct core_thread { struct task_struct *task ; struct core_thread *next ; }; struct core_state { atomic_t nr_threads ; struct core_thread dumper ; struct completion startup ; }; struct task_rss_stat { int events ; int count[3U] ; }; struct mm_rss_stat { atomic_long_t count[3U] ; }; struct kioctx_table; struct linux_binfmt; struct mmu_notifier_mm; struct mm_struct { struct vm_area_struct *mmap ; struct rb_root mm_rb ; u32 vmacache_seqnum ; unsigned long (*get_unmapped_area)(struct file * , unsigned long , unsigned long , unsigned long , unsigned long ) ; unsigned long mmap_base ; unsigned long mmap_legacy_base ; unsigned long task_size ; unsigned long highest_vm_end ; pgd_t *pgd ; atomic_t mm_users ; atomic_t mm_count ; atomic_long_t nr_ptes ; atomic_long_t nr_pmds ; int map_count ; spinlock_t page_table_lock ; struct rw_semaphore mmap_sem ; struct list_head mmlist ; unsigned long hiwater_rss ; unsigned long hiwater_vm ; unsigned long total_vm ; unsigned long locked_vm ; unsigned long pinned_vm ; unsigned long shared_vm ; unsigned long exec_vm ; unsigned long stack_vm ; unsigned long def_flags ; unsigned long start_code ; unsigned long end_code ; unsigned long start_data ; unsigned long end_data ; unsigned long start_brk ; unsigned long brk ; unsigned long start_stack ; unsigned long arg_start ; unsigned long arg_end ; unsigned long env_start ; unsigned long env_end ; unsigned long saved_auxv[46U] ; struct mm_rss_stat rss_stat ; struct linux_binfmt *binfmt ; cpumask_var_t cpu_vm_mask_var ; mm_context_t context ; unsigned long flags ; struct core_state *core_state ; spinlock_t ioctx_lock ; struct kioctx_table *ioctx_table ; struct task_struct *owner ; struct file *exe_file ; struct mmu_notifier_mm *mmu_notifier_mm ; struct cpumask cpumask_allocation ; unsigned long numa_next_scan ; unsigned long numa_scan_offset ; int numa_scan_seq ; bool tlb_flush_pending ; struct uprobes_state uprobes_state ; void *bd_addr ; }; typedef __u64 Elf64_Addr; typedef __u16 Elf64_Half; typedef __u32 Elf64_Word; typedef __u64 Elf64_Xword; struct elf64_sym { Elf64_Word st_name ; unsigned char st_info ; unsigned char st_other ; Elf64_Half st_shndx ; Elf64_Addr st_value ; Elf64_Xword st_size ; }; typedef struct elf64_sym Elf64_Sym; union __anonunion____missing_field_name_166 { unsigned long bitmap[4U] ; struct callback_head callback_head ; }; struct idr_layer { int prefix ; int layer ; struct idr_layer *ary[256U] ; int count ; union __anonunion____missing_field_name_166 __annonCompField47 ; }; struct idr { struct idr_layer *hint ; struct idr_layer *top ; int layers ; int cur ; spinlock_t lock ; int id_free_cnt ; struct idr_layer *id_free ; }; struct ida_bitmap { long nr_busy ; unsigned long bitmap[15U] ; }; struct ida { struct idr idr ; struct ida_bitmap *free_bitmap ; }; struct dentry; struct iattr; struct super_block; struct file_system_type; struct kernfs_open_node; struct kernfs_iattrs; struct kernfs_root; struct kernfs_elem_dir { unsigned long subdirs ; struct rb_root children ; struct kernfs_root *root ; }; struct kernfs_node; struct kernfs_elem_symlink { struct kernfs_node *target_kn ; }; struct kernfs_ops; struct kernfs_elem_attr { struct kernfs_ops const *ops ; struct kernfs_open_node *open ; loff_t size ; struct kernfs_node *notify_next ; }; union __anonunion____missing_field_name_171 { struct kernfs_elem_dir dir ; struct kernfs_elem_symlink symlink ; struct kernfs_elem_attr attr ; }; struct kernfs_node { atomic_t count ; atomic_t active ; struct lockdep_map dep_map ; struct kernfs_node *parent ; char const *name ; struct rb_node rb ; void const *ns ; unsigned int hash ; union __anonunion____missing_field_name_171 __annonCompField48 ; void *priv ; unsigned short flags ; umode_t mode ; unsigned int ino ; struct kernfs_iattrs *iattr ; }; struct kernfs_syscall_ops { int (*remount_fs)(struct kernfs_root * , int * , char * ) ; int (*show_options)(struct seq_file * , struct kernfs_root * ) ; int (*mkdir)(struct kernfs_node * , char const * , umode_t ) ; int (*rmdir)(struct kernfs_node * ) ; int (*rename)(struct kernfs_node * , struct kernfs_node * , char const * ) ; }; struct kernfs_root { struct kernfs_node *kn ; unsigned int flags ; struct ida ino_ida ; struct kernfs_syscall_ops *syscall_ops ; struct list_head supers ; wait_queue_head_t deactivate_waitq ; }; struct kernfs_open_file { struct kernfs_node *kn ; struct file *file ; void *priv ; struct mutex mutex ; int event ; struct list_head list ; char *prealloc_buf ; size_t atomic_write_len ; bool mmapped ; struct vm_operations_struct const *vm_ops ; }; struct kernfs_ops { int (*seq_show)(struct seq_file * , void * ) ; void *(*seq_start)(struct seq_file * , loff_t * ) ; void *(*seq_next)(struct seq_file * , void * , loff_t * ) ; void (*seq_stop)(struct seq_file * , void * ) ; ssize_t (*read)(struct kernfs_open_file * , char * , size_t , loff_t ) ; size_t atomic_write_len ; bool prealloc ; ssize_t (*write)(struct kernfs_open_file * , char * , size_t , loff_t ) ; int (*mmap)(struct kernfs_open_file * , struct vm_area_struct * ) ; struct lock_class_key lockdep_key ; }; struct sock; struct kobject; enum kobj_ns_type { KOBJ_NS_TYPE_NONE = 0, KOBJ_NS_TYPE_NET = 1, KOBJ_NS_TYPES = 2 } ; struct kobj_ns_type_operations { enum kobj_ns_type type ; bool (*current_may_mount)(void) ; void *(*grab_current_ns)(void) ; void const *(*netlink_ns)(struct sock * ) ; void const *(*initial_ns)(void) ; void (*drop_ns)(void * ) ; }; struct bin_attribute; struct attribute { char const *name ; umode_t mode ; bool ignore_lockdep ; struct lock_class_key *key ; struct lock_class_key skey ; }; struct attribute_group { char const *name ; umode_t (*is_visible)(struct kobject * , struct attribute * , int ) ; struct attribute **attrs ; struct bin_attribute **bin_attrs ; }; struct bin_attribute { struct attribute attr ; size_t size ; void *private ; ssize_t (*read)(struct file * , struct kobject * , struct bin_attribute * , char * , loff_t , size_t ) ; ssize_t (*write)(struct file * , struct kobject * , struct bin_attribute * , char * , loff_t , size_t ) ; int (*mmap)(struct file * , struct kobject * , struct bin_attribute * , struct vm_area_struct * ) ; }; struct sysfs_ops { ssize_t (*show)(struct kobject * , struct attribute * , char * ) ; ssize_t (*store)(struct kobject * , struct attribute * , char const * , size_t ) ; }; struct kref { atomic_t refcount ; }; struct kset; struct kobj_type; struct kobject { char const *name ; struct list_head entry ; struct kobject *parent ; struct kset *kset ; struct kobj_type *ktype ; struct kernfs_node *sd ; struct kref kref ; struct delayed_work release ; unsigned char state_initialized : 1 ; unsigned char state_in_sysfs : 1 ; unsigned char state_add_uevent_sent : 1 ; unsigned char state_remove_uevent_sent : 1 ; unsigned char uevent_suppress : 1 ; }; struct kobj_type { void (*release)(struct kobject * ) ; struct sysfs_ops const *sysfs_ops ; struct attribute **default_attrs ; struct kobj_ns_type_operations const *(*child_ns_type)(struct kobject * ) ; void const *(*namespace)(struct kobject * ) ; }; struct kobj_uevent_env { char *argv[3U] ; char *envp[32U] ; int envp_idx ; char buf[2048U] ; int buflen ; }; struct kset_uevent_ops { int (* const filter)(struct kset * , struct kobject * ) ; char const *(* const name)(struct kset * , struct kobject * ) ; int (* const uevent)(struct kset * , struct kobject * , struct kobj_uevent_env * ) ; }; struct kset { struct list_head list ; spinlock_t list_lock ; struct kobject kobj ; struct kset_uevent_ops const *uevent_ops ; }; struct kernel_param; struct kernel_param_ops { unsigned int flags ; int (*set)(char const * , struct kernel_param const * ) ; int (*get)(char * , struct kernel_param const * ) ; void (*free)(void * ) ; }; struct kparam_string; struct kparam_array; union __anonunion____missing_field_name_172 { void *arg ; struct kparam_string const *str ; struct kparam_array const *arr ; }; struct kernel_param { char const *name ; struct module *mod ; struct kernel_param_ops const *ops ; u16 const perm ; s8 level ; u8 flags ; union __anonunion____missing_field_name_172 __annonCompField49 ; }; struct kparam_string { unsigned int maxlen ; char *string ; }; struct kparam_array { unsigned int max ; unsigned int elemsize ; unsigned int *num ; struct kernel_param_ops const *ops ; void *elem ; }; struct latch_tree_node { struct rb_node node[2U] ; }; struct mod_arch_specific { }; struct module_param_attrs; struct module_kobject { struct kobject kobj ; struct module *mod ; struct kobject *drivers_dir ; struct module_param_attrs *mp ; struct completion *kobj_completion ; }; struct module_attribute { struct attribute attr ; ssize_t (*show)(struct module_attribute * , struct module_kobject * , char * ) ; ssize_t (*store)(struct module_attribute * , struct module_kobject * , char const * , size_t ) ; void (*setup)(struct module * , char const * ) ; int (*test)(struct module * ) ; void (*free)(struct module * ) ; }; struct exception_table_entry; enum module_state { MODULE_STATE_LIVE = 0, MODULE_STATE_COMING = 1, MODULE_STATE_GOING = 2, MODULE_STATE_UNFORMED = 3 } ; struct mod_tree_node { struct module *mod ; struct latch_tree_node node ; }; struct module_sect_attrs; struct module_notes_attrs; struct tracepoint; struct trace_event_call; struct trace_enum_map; struct module { enum module_state state ; struct list_head list ; char name[56U] ; struct module_kobject mkobj ; struct module_attribute *modinfo_attrs ; char const *version ; char const *srcversion ; struct kobject *holders_dir ; struct kernel_symbol const *syms ; unsigned long const *crcs ; unsigned int num_syms ; struct mutex param_lock ; struct kernel_param *kp ; unsigned int num_kp ; unsigned int num_gpl_syms ; struct kernel_symbol const *gpl_syms ; unsigned long const *gpl_crcs ; struct kernel_symbol const *unused_syms ; unsigned long const *unused_crcs ; unsigned int num_unused_syms ; unsigned int num_unused_gpl_syms ; struct kernel_symbol const *unused_gpl_syms ; unsigned long const *unused_gpl_crcs ; bool sig_ok ; bool async_probe_requested ; struct kernel_symbol const *gpl_future_syms ; unsigned long const *gpl_future_crcs ; unsigned int num_gpl_future_syms ; unsigned int num_exentries ; struct exception_table_entry *extable ; int (*init)(void) ; void *module_init ; void *module_core ; unsigned int init_size ; unsigned int core_size ; unsigned int init_text_size ; unsigned int core_text_size ; struct mod_tree_node mtn_core ; struct mod_tree_node mtn_init ; unsigned int init_ro_size ; unsigned int core_ro_size ; struct mod_arch_specific arch ; unsigned int taints ; unsigned int num_bugs ; struct list_head bug_list ; struct bug_entry *bug_table ; Elf64_Sym *symtab ; Elf64_Sym *core_symtab ; unsigned int num_symtab ; unsigned int core_num_syms ; char *strtab ; char *core_strtab ; struct module_sect_attrs *sect_attrs ; struct module_notes_attrs *notes_attrs ; char *args ; void *percpu ; unsigned int percpu_size ; unsigned int num_tracepoints ; struct tracepoint * const *tracepoints_ptrs ; unsigned int num_trace_bprintk_fmt ; char const **trace_bprintk_fmt_start ; struct trace_event_call **trace_events ; unsigned int num_trace_events ; struct trace_enum_map **trace_enums ; unsigned int num_trace_enums ; unsigned int num_ftrace_callsites ; unsigned long *ftrace_callsites ; bool klp_alive ; struct list_head source_list ; struct list_head target_list ; void (*exit)(void) ; atomic_t refcnt ; ctor_fn_t (**ctors)(void) ; unsigned int num_ctors ; }; struct kernel_cap_struct { __u32 cap[2U] ; }; typedef struct kernel_cap_struct kernel_cap_t; struct plist_node { int prio ; struct list_head prio_list ; struct list_head node_list ; }; typedef unsigned long cputime_t; struct sem_undo_list; struct sysv_sem { struct sem_undo_list *undo_list ; }; struct user_struct; struct sysv_shm { struct list_head shm_clist ; }; struct __anonstruct_sigset_t_180 { unsigned long sig[1U] ; }; typedef struct __anonstruct_sigset_t_180 sigset_t; struct siginfo; typedef void __signalfn_t(int ); typedef __signalfn_t *__sighandler_t; typedef void __restorefn_t(void); typedef __restorefn_t *__sigrestore_t; union sigval { int sival_int ; void *sival_ptr ; }; typedef union sigval sigval_t; struct __anonstruct__kill_182 { __kernel_pid_t _pid ; __kernel_uid32_t _uid ; }; struct __anonstruct__timer_183 { __kernel_timer_t _tid ; int _overrun ; char _pad[0U] ; sigval_t _sigval ; int _sys_private ; }; struct __anonstruct__rt_184 { __kernel_pid_t _pid ; __kernel_uid32_t _uid ; sigval_t _sigval ; }; struct __anonstruct__sigchld_185 { __kernel_pid_t _pid ; __kernel_uid32_t _uid ; int _status ; __kernel_clock_t _utime ; __kernel_clock_t _stime ; }; struct __anonstruct__addr_bnd_187 { void *_lower ; void *_upper ; }; struct __anonstruct__sigfault_186 { void *_addr ; short _addr_lsb ; struct __anonstruct__addr_bnd_187 _addr_bnd ; }; struct __anonstruct__sigpoll_188 { long _band ; int _fd ; }; struct __anonstruct__sigsys_189 { void *_call_addr ; int _syscall ; unsigned int _arch ; }; union __anonunion__sifields_181 { int _pad[28U] ; struct __anonstruct__kill_182 _kill ; struct __anonstruct__timer_183 _timer ; struct __anonstruct__rt_184 _rt ; struct __anonstruct__sigchld_185 _sigchld ; struct __anonstruct__sigfault_186 _sigfault ; struct __anonstruct__sigpoll_188 _sigpoll ; struct __anonstruct__sigsys_189 _sigsys ; }; struct siginfo { int si_signo ; int si_errno ; int si_code ; union __anonunion__sifields_181 _sifields ; }; typedef struct siginfo siginfo_t; struct sigpending { struct list_head list ; sigset_t signal ; }; struct sigaction { __sighandler_t sa_handler ; unsigned long sa_flags ; __sigrestore_t sa_restorer ; sigset_t sa_mask ; }; struct k_sigaction { struct sigaction sa ; }; enum pid_type { PIDTYPE_PID = 0, PIDTYPE_PGID = 1, PIDTYPE_SID = 2, PIDTYPE_MAX = 3 } ; struct pid_namespace; struct upid { int nr ; struct pid_namespace *ns ; struct hlist_node pid_chain ; }; struct pid { atomic_t count ; unsigned int level ; struct hlist_head tasks[3U] ; struct callback_head rcu ; struct upid numbers[1U] ; }; struct pid_link { struct hlist_node node ; struct pid *pid ; }; struct percpu_counter { raw_spinlock_t lock ; s64 count ; struct list_head list ; s32 *counters ; }; struct seccomp_filter; struct seccomp { int mode ; struct seccomp_filter *filter ; }; struct rt_mutex_waiter; struct rlimit { __kernel_ulong_t rlim_cur ; __kernel_ulong_t rlim_max ; }; struct timerqueue_node { struct rb_node node ; ktime_t expires ; }; struct timerqueue_head { struct rb_root head ; struct timerqueue_node *next ; }; struct hrtimer_clock_base; struct hrtimer_cpu_base; enum hrtimer_restart { HRTIMER_NORESTART = 0, HRTIMER_RESTART = 1 } ; struct hrtimer { struct timerqueue_node node ; ktime_t _softexpires ; enum hrtimer_restart (*function)(struct hrtimer * ) ; struct hrtimer_clock_base *base ; unsigned long state ; int start_pid ; void *start_site ; char start_comm[16U] ; }; struct hrtimer_clock_base { struct hrtimer_cpu_base *cpu_base ; int index ; clockid_t clockid ; struct timerqueue_head active ; ktime_t (*get_time)(void) ; ktime_t offset ; }; struct hrtimer_cpu_base { raw_spinlock_t lock ; seqcount_t seq ; struct hrtimer *running ; unsigned int cpu ; unsigned int active_bases ; unsigned int clock_was_set_seq ; bool migration_enabled ; bool nohz_active ; unsigned char in_hrtirq : 1 ; unsigned char hres_active : 1 ; unsigned char hang_detected : 1 ; ktime_t expires_next ; struct hrtimer *next_timer ; unsigned int nr_events ; unsigned int nr_retries ; unsigned int nr_hangs ; unsigned int max_hang_time ; struct hrtimer_clock_base clock_base[4U] ; }; struct task_io_accounting { u64 rchar ; u64 wchar ; u64 syscr ; u64 syscw ; u64 read_bytes ; u64 write_bytes ; u64 cancelled_write_bytes ; }; struct latency_record { unsigned long backtrace[12U] ; unsigned int count ; unsigned long time ; unsigned long max ; }; struct assoc_array_ptr; struct assoc_array { struct assoc_array_ptr *root ; unsigned long nr_leaves_on_tree ; }; typedef int32_t key_serial_t; typedef uint32_t key_perm_t; struct key; struct signal_struct; struct key_type; struct keyring_index_key { struct key_type *type ; char const *description ; size_t desc_len ; }; union __anonunion____missing_field_name_196 { struct list_head graveyard_link ; struct rb_node serial_node ; }; struct key_user; union __anonunion____missing_field_name_197 { time_t expiry ; time_t revoked_at ; }; struct __anonstruct____missing_field_name_199 { struct key_type *type ; char *description ; }; union __anonunion____missing_field_name_198 { struct keyring_index_key index_key ; struct __anonstruct____missing_field_name_199 __annonCompField52 ; }; union __anonunion_type_data_200 { struct list_head link ; unsigned long x[2U] ; void *p[2U] ; int reject_error ; }; union __anonunion_payload_202 { unsigned long value ; void *rcudata ; void *data ; void *data2[2U] ; }; union __anonunion____missing_field_name_201 { union __anonunion_payload_202 payload ; struct assoc_array keys ; }; struct key { atomic_t usage ; key_serial_t serial ; union __anonunion____missing_field_name_196 __annonCompField50 ; struct rw_semaphore sem ; struct key_user *user ; void *security ; union __anonunion____missing_field_name_197 __annonCompField51 ; time_t last_used_at ; kuid_t uid ; kgid_t gid ; key_perm_t perm ; unsigned short quotalen ; unsigned short datalen ; unsigned long flags ; union __anonunion____missing_field_name_198 __annonCompField53 ; union __anonunion_type_data_200 type_data ; union __anonunion____missing_field_name_201 __annonCompField54 ; }; struct audit_context; struct group_info { atomic_t usage ; int ngroups ; int nblocks ; kgid_t small_block[32U] ; kgid_t *blocks[0U] ; }; struct cred { atomic_t usage ; atomic_t subscribers ; void *put_addr ; unsigned int magic ; kuid_t uid ; kgid_t gid ; kuid_t suid ; kgid_t sgid ; kuid_t euid ; kgid_t egid ; kuid_t fsuid ; kgid_t fsgid ; unsigned int securebits ; kernel_cap_t cap_inheritable ; kernel_cap_t cap_permitted ; kernel_cap_t cap_effective ; kernel_cap_t cap_bset ; unsigned char jit_keyring ; struct key *session_keyring ; struct key *process_keyring ; struct key *thread_keyring ; struct key *request_key_auth ; void *security ; struct user_struct *user ; struct user_namespace *user_ns ; struct group_info *group_info ; struct callback_head rcu ; }; struct percpu_ref; typedef void percpu_ref_func_t(struct percpu_ref * ); struct percpu_ref { atomic_long_t count ; unsigned long percpu_count_ptr ; percpu_ref_func_t *release ; percpu_ref_func_t *confirm_switch ; bool force_atomic ; struct callback_head rcu ; }; struct cgroup; struct cgroup_root; struct cgroup_subsys; struct cgroup_taskset; struct cgroup_subsys_state { struct cgroup *cgroup ; struct cgroup_subsys *ss ; struct percpu_ref refcnt ; struct cgroup_subsys_state *parent ; struct list_head sibling ; struct list_head children ; int id ; unsigned int flags ; u64 serial_nr ; struct callback_head callback_head ; struct work_struct destroy_work ; }; struct css_set { atomic_t refcount ; struct hlist_node hlist ; struct list_head tasks ; struct list_head mg_tasks ; struct list_head cgrp_links ; struct cgroup *dfl_cgrp ; struct cgroup_subsys_state *subsys[12U] ; struct list_head mg_preload_node ; struct list_head mg_node ; struct cgroup *mg_src_cgrp ; struct css_set *mg_dst_cset ; struct list_head e_cset_node[12U] ; struct callback_head callback_head ; }; struct cgroup { struct cgroup_subsys_state self ; unsigned long flags ; int id ; int populated_cnt ; struct kernfs_node *kn ; struct kernfs_node *procs_kn ; struct kernfs_node *populated_kn ; unsigned int subtree_control ; unsigned int child_subsys_mask ; struct cgroup_subsys_state *subsys[12U] ; struct cgroup_root *root ; struct list_head cset_links ; struct list_head e_csets[12U] ; struct list_head pidlists ; struct mutex pidlist_mutex ; wait_queue_head_t offline_waitq ; struct work_struct release_agent_work ; }; struct cgroup_root { struct kernfs_root *kf_root ; unsigned int subsys_mask ; int hierarchy_id ; struct cgroup cgrp ; atomic_t nr_cgrps ; struct list_head root_list ; unsigned int flags ; struct idr cgroup_idr ; char release_agent_path[4096U] ; char name[64U] ; }; struct cftype { char name[64U] ; int private ; umode_t mode ; size_t max_write_len ; unsigned int flags ; struct cgroup_subsys *ss ; struct list_head node ; struct kernfs_ops *kf_ops ; u64 (*read_u64)(struct cgroup_subsys_state * , struct cftype * ) ; s64 (*read_s64)(struct cgroup_subsys_state * , struct cftype * ) ; int (*seq_show)(struct seq_file * , void * ) ; void *(*seq_start)(struct seq_file * , loff_t * ) ; void *(*seq_next)(struct seq_file * , void * , loff_t * ) ; void (*seq_stop)(struct seq_file * , void * ) ; int (*write_u64)(struct cgroup_subsys_state * , struct cftype * , u64 ) ; int (*write_s64)(struct cgroup_subsys_state * , struct cftype * , s64 ) ; ssize_t (*write)(struct kernfs_open_file * , char * , size_t , loff_t ) ; struct lock_class_key lockdep_key ; }; struct cgroup_subsys { struct cgroup_subsys_state *(*css_alloc)(struct cgroup_subsys_state * ) ; int (*css_online)(struct cgroup_subsys_state * ) ; void (*css_offline)(struct cgroup_subsys_state * ) ; void (*css_released)(struct cgroup_subsys_state * ) ; void (*css_free)(struct cgroup_subsys_state * ) ; void (*css_reset)(struct cgroup_subsys_state * ) ; void (*css_e_css_changed)(struct cgroup_subsys_state * ) ; int (*can_attach)(struct cgroup_subsys_state * , struct cgroup_taskset * ) ; void (*cancel_attach)(struct cgroup_subsys_state * , struct cgroup_taskset * ) ; void (*attach)(struct cgroup_subsys_state * , struct cgroup_taskset * ) ; void (*fork)(struct task_struct * ) ; void (*exit)(struct cgroup_subsys_state * , struct cgroup_subsys_state * , struct task_struct * ) ; void (*bind)(struct cgroup_subsys_state * ) ; int disabled ; int early_init ; bool broken_hierarchy ; bool warned_broken_hierarchy ; int id ; char const *name ; struct cgroup_root *root ; struct idr css_idr ; struct list_head cfts ; struct cftype *dfl_cftypes ; struct cftype *legacy_cftypes ; unsigned int depends_on ; }; struct futex_pi_state; struct robust_list_head; struct bio_list; struct fs_struct; struct perf_event_context; struct blk_plug; struct nameidata; struct cfs_rq; struct task_group; struct sighand_struct { atomic_t count ; struct k_sigaction action[64U] ; spinlock_t siglock ; wait_queue_head_t signalfd_wqh ; }; struct pacct_struct { int ac_flag ; long ac_exitcode ; unsigned long ac_mem ; cputime_t ac_utime ; cputime_t ac_stime ; unsigned long ac_minflt ; unsigned long ac_majflt ; }; struct cpu_itimer { cputime_t expires ; cputime_t incr ; u32 error ; u32 incr_error ; }; struct cputime { cputime_t utime ; cputime_t stime ; }; struct task_cputime { cputime_t utime ; cputime_t stime ; unsigned long long sum_exec_runtime ; }; struct task_cputime_atomic { atomic64_t utime ; atomic64_t stime ; atomic64_t sum_exec_runtime ; }; struct thread_group_cputimer { struct task_cputime_atomic cputime_atomic ; int running ; }; struct autogroup; struct tty_struct; struct taskstats; struct tty_audit_buf; struct signal_struct { atomic_t sigcnt ; atomic_t live ; int nr_threads ; struct list_head thread_head ; wait_queue_head_t wait_chldexit ; struct task_struct *curr_target ; struct sigpending shared_pending ; int group_exit_code ; int notify_count ; struct task_struct *group_exit_task ; int group_stop_count ; unsigned int flags ; unsigned char is_child_subreaper : 1 ; unsigned char has_child_subreaper : 1 ; int posix_timer_id ; struct list_head posix_timers ; struct hrtimer real_timer ; struct pid *leader_pid ; ktime_t it_real_incr ; struct cpu_itimer it[2U] ; struct thread_group_cputimer cputimer ; struct task_cputime cputime_expires ; struct list_head cpu_timers[3U] ; struct pid *tty_old_pgrp ; int leader ; struct tty_struct *tty ; struct autogroup *autogroup ; seqlock_t stats_lock ; cputime_t utime ; cputime_t stime ; cputime_t cutime ; cputime_t cstime ; cputime_t gtime ; cputime_t cgtime ; struct cputime prev_cputime ; unsigned long nvcsw ; unsigned long nivcsw ; unsigned long cnvcsw ; unsigned long cnivcsw ; unsigned long min_flt ; unsigned long maj_flt ; unsigned long cmin_flt ; unsigned long cmaj_flt ; unsigned long inblock ; unsigned long oublock ; unsigned long cinblock ; unsigned long coublock ; unsigned long maxrss ; unsigned long cmaxrss ; struct task_io_accounting ioac ; unsigned long long sum_sched_runtime ; struct rlimit rlim[16U] ; struct pacct_struct pacct ; struct taskstats *stats ; unsigned int audit_tty ; unsigned int audit_tty_log_passwd ; struct tty_audit_buf *tty_audit_buf ; oom_flags_t oom_flags ; short oom_score_adj ; short oom_score_adj_min ; struct mutex cred_guard_mutex ; }; struct user_struct { atomic_t __count ; atomic_t processes ; atomic_t sigpending ; atomic_t inotify_watches ; atomic_t inotify_devs ; atomic_t fanotify_listeners ; atomic_long_t epoll_watches ; unsigned long mq_bytes ; unsigned long locked_shm ; struct key *uid_keyring ; struct key *session_keyring ; struct hlist_node uidhash_node ; kuid_t uid ; atomic_long_t locked_vm ; }; struct backing_dev_info; struct reclaim_state; struct sched_info { unsigned long pcount ; unsigned long long run_delay ; unsigned long long last_arrival ; unsigned long long last_queued ; }; struct task_delay_info { spinlock_t lock ; unsigned int flags ; u64 blkio_start ; u64 blkio_delay ; u64 swapin_delay ; u32 blkio_count ; u32 swapin_count ; u64 freepages_start ; u64 freepages_delay ; u32 freepages_count ; }; struct wake_q_node { struct wake_q_node *next ; }; struct io_context; struct pipe_inode_info; struct uts_namespace; struct load_weight { unsigned long weight ; u32 inv_weight ; }; struct sched_avg { u64 last_runnable_update ; s64 decay_count ; unsigned long load_avg_contrib ; unsigned long utilization_avg_contrib ; u32 runnable_avg_sum ; u32 avg_period ; u32 running_avg_sum ; }; struct sched_statistics { u64 wait_start ; u64 wait_max ; u64 wait_count ; u64 wait_sum ; u64 iowait_count ; u64 iowait_sum ; u64 sleep_start ; u64 sleep_max ; s64 sum_sleep_runtime ; u64 block_start ; u64 block_max ; u64 exec_max ; u64 slice_max ; u64 nr_migrations_cold ; u64 nr_failed_migrations_affine ; u64 nr_failed_migrations_running ; u64 nr_failed_migrations_hot ; u64 nr_forced_migrations ; u64 nr_wakeups ; u64 nr_wakeups_sync ; u64 nr_wakeups_migrate ; u64 nr_wakeups_local ; u64 nr_wakeups_remote ; u64 nr_wakeups_affine ; u64 nr_wakeups_affine_attempts ; u64 nr_wakeups_passive ; u64 nr_wakeups_idle ; }; struct sched_entity { struct load_weight load ; struct rb_node run_node ; struct list_head group_node ; unsigned int on_rq ; u64 exec_start ; u64 sum_exec_runtime ; u64 vruntime ; u64 prev_sum_exec_runtime ; u64 nr_migrations ; struct sched_statistics statistics ; int depth ; struct sched_entity *parent ; struct cfs_rq *cfs_rq ; struct cfs_rq *my_q ; struct sched_avg avg ; }; struct rt_rq; struct sched_rt_entity { struct list_head run_list ; unsigned long timeout ; unsigned long watchdog_stamp ; unsigned int time_slice ; struct sched_rt_entity *back ; struct sched_rt_entity *parent ; struct rt_rq *rt_rq ; struct rt_rq *my_q ; }; struct sched_dl_entity { struct rb_node rb_node ; u64 dl_runtime ; u64 dl_deadline ; u64 dl_period ; u64 dl_bw ; s64 runtime ; u64 deadline ; unsigned int flags ; int dl_throttled ; int dl_new ; int dl_boosted ; int dl_yielded ; struct hrtimer dl_timer ; }; struct memcg_oom_info { struct mem_cgroup *memcg ; gfp_t gfp_mask ; int order ; unsigned char may_oom : 1 ; }; struct sched_class; struct files_struct; struct compat_robust_list_head; struct numa_group; struct ftrace_ret_stack; struct task_struct { long volatile state ; void *stack ; atomic_t usage ; unsigned int flags ; unsigned int ptrace ; struct llist_node wake_entry ; int on_cpu ; struct task_struct *last_wakee ; unsigned long wakee_flips ; unsigned long wakee_flip_decay_ts ; int wake_cpu ; int on_rq ; int prio ; int static_prio ; int normal_prio ; unsigned int rt_priority ; struct sched_class const *sched_class ; struct sched_entity se ; struct sched_rt_entity rt ; struct task_group *sched_task_group ; struct sched_dl_entity dl ; struct hlist_head preempt_notifiers ; unsigned int btrace_seq ; unsigned int policy ; int nr_cpus_allowed ; cpumask_t cpus_allowed ; unsigned long rcu_tasks_nvcsw ; bool rcu_tasks_holdout ; struct list_head rcu_tasks_holdout_list ; int rcu_tasks_idle_cpu ; struct sched_info sched_info ; struct list_head tasks ; struct plist_node pushable_tasks ; struct rb_node pushable_dl_tasks ; struct mm_struct *mm ; struct mm_struct *active_mm ; u32 vmacache_seqnum ; struct vm_area_struct *vmacache[4U] ; struct task_rss_stat rss_stat ; int exit_state ; int exit_code ; int exit_signal ; int pdeath_signal ; unsigned long jobctl ; unsigned int personality ; unsigned char in_execve : 1 ; unsigned char in_iowait : 1 ; unsigned char sched_reset_on_fork : 1 ; unsigned char sched_contributes_to_load : 1 ; unsigned char sched_migrated : 1 ; unsigned char memcg_kmem_skip_account : 1 ; unsigned char brk_randomized : 1 ; unsigned long atomic_flags ; struct restart_block restart_block ; pid_t pid ; pid_t tgid ; struct task_struct *real_parent ; struct task_struct *parent ; struct list_head children ; struct list_head sibling ; struct task_struct *group_leader ; struct list_head ptraced ; struct list_head ptrace_entry ; struct pid_link pids[3U] ; struct list_head thread_group ; struct list_head thread_node ; struct completion *vfork_done ; int *set_child_tid ; int *clear_child_tid ; cputime_t utime ; cputime_t stime ; cputime_t utimescaled ; cputime_t stimescaled ; cputime_t gtime ; struct cputime prev_cputime ; unsigned long nvcsw ; unsigned long nivcsw ; u64 start_time ; u64 real_start_time ; unsigned long min_flt ; unsigned long maj_flt ; struct task_cputime cputime_expires ; struct list_head cpu_timers[3U] ; struct cred const *real_cred ; struct cred const *cred ; char comm[16U] ; struct nameidata *nameidata ; struct sysv_sem sysvsem ; struct sysv_shm sysvshm ; unsigned long last_switch_count ; struct thread_struct thread ; struct fs_struct *fs ; struct files_struct *files ; struct nsproxy *nsproxy ; struct signal_struct *signal ; struct sighand_struct *sighand ; sigset_t blocked ; sigset_t real_blocked ; sigset_t saved_sigmask ; struct sigpending pending ; unsigned long sas_ss_sp ; size_t sas_ss_size ; int (*notifier)(void * ) ; void *notifier_data ; sigset_t *notifier_mask ; struct callback_head *task_works ; struct audit_context *audit_context ; kuid_t loginuid ; unsigned int sessionid ; struct seccomp seccomp ; u32 parent_exec_id ; u32 self_exec_id ; spinlock_t alloc_lock ; raw_spinlock_t pi_lock ; struct wake_q_node wake_q ; struct rb_root pi_waiters ; struct rb_node *pi_waiters_leftmost ; struct rt_mutex_waiter *pi_blocked_on ; struct mutex_waiter *blocked_on ; unsigned int irq_events ; unsigned long hardirq_enable_ip ; unsigned long hardirq_disable_ip ; unsigned int hardirq_enable_event ; unsigned int hardirq_disable_event ; int hardirqs_enabled ; int hardirq_context ; unsigned long softirq_disable_ip ; unsigned long softirq_enable_ip ; unsigned int softirq_disable_event ; unsigned int softirq_enable_event ; int softirqs_enabled ; int softirq_context ; u64 curr_chain_key ; int lockdep_depth ; unsigned int lockdep_recursion ; struct held_lock held_locks[48U] ; gfp_t lockdep_reclaim_gfp ; void *journal_info ; struct bio_list *bio_list ; struct blk_plug *plug ; struct reclaim_state *reclaim_state ; struct backing_dev_info *backing_dev_info ; struct io_context *io_context ; unsigned long ptrace_message ; siginfo_t *last_siginfo ; struct task_io_accounting ioac ; u64 acct_rss_mem1 ; u64 acct_vm_mem1 ; cputime_t acct_timexpd ; nodemask_t mems_allowed ; seqcount_t mems_allowed_seq ; int cpuset_mem_spread_rotor ; int cpuset_slab_spread_rotor ; struct css_set *cgroups ; struct list_head cg_list ; struct robust_list_head *robust_list ; struct compat_robust_list_head *compat_robust_list ; struct list_head pi_state_list ; struct futex_pi_state *pi_state_cache ; struct perf_event_context *perf_event_ctxp[2U] ; struct mutex perf_event_mutex ; struct list_head perf_event_list ; struct mempolicy *mempolicy ; short il_next ; short pref_node_fork ; int numa_scan_seq ; unsigned int numa_scan_period ; unsigned int numa_scan_period_max ; int numa_preferred_nid ; unsigned long numa_migrate_retry ; u64 node_stamp ; u64 last_task_numa_placement ; u64 last_sum_exec_runtime ; struct callback_head numa_work ; struct list_head numa_entry ; struct numa_group *numa_group ; unsigned long *numa_faults ; unsigned long total_numa_faults ; unsigned long numa_faults_locality[3U] ; unsigned long numa_pages_migrated ; struct callback_head rcu ; struct pipe_inode_info *splice_pipe ; struct page_frag task_frag ; struct task_delay_info *delays ; int make_it_fail ; int nr_dirtied ; int nr_dirtied_pause ; unsigned long dirty_paused_when ; int latency_record_count ; struct latency_record latency_record[32U] ; unsigned long timer_slack_ns ; unsigned long default_timer_slack_ns ; unsigned int kasan_depth ; int curr_ret_stack ; struct ftrace_ret_stack *ret_stack ; unsigned long long ftrace_timestamp ; atomic_t trace_overrun ; atomic_t tracing_graph_pause ; unsigned long trace ; unsigned long trace_recursion ; struct memcg_oom_info memcg_oom ; struct uprobe_task *utask ; unsigned int sequential_io ; unsigned int sequential_io_avg ; unsigned long task_state_change ; int pagefault_disabled ; }; enum irqreturn { IRQ_NONE = 0, IRQ_HANDLED = 1, IRQ_WAKE_THREAD = 2 } ; typedef enum irqreturn irqreturn_t; struct ieee80211_hw; struct bcma_device; struct iovec { void *iov_base ; __kernel_size_t iov_len ; }; struct kvec { void *iov_base ; size_t iov_len ; }; union __anonunion____missing_field_name_217 { struct iovec const *iov ; struct kvec const *kvec ; struct bio_vec const *bvec ; }; struct iov_iter { int type ; size_t iov_offset ; size_t count ; union __anonunion____missing_field_name_217 __annonCompField58 ; unsigned long nr_segs ; }; typedef unsigned short __kernel_sa_family_t; typedef __kernel_sa_family_t sa_family_t; struct sockaddr { sa_family_t sa_family ; char sa_data[14U] ; }; struct kiocb; struct msghdr { void *msg_name ; int msg_namelen ; struct iov_iter msg_iter ; void *msg_control ; __kernel_size_t msg_controllen ; unsigned int msg_flags ; struct kiocb *msg_iocb ; }; struct irq_desc; enum ldv_17630 { SS_FREE = 0, SS_UNCONNECTED = 1, SS_CONNECTING = 2, SS_CONNECTED = 3, SS_DISCONNECTING = 4 } ; typedef enum ldv_17630 socket_state; struct poll_table_struct; struct net; struct fasync_struct; struct socket_wq { wait_queue_head_t wait ; struct fasync_struct *fasync_list ; struct callback_head rcu ; }; struct proto_ops; struct socket { socket_state state ; short type ; unsigned long flags ; struct socket_wq *wq ; struct file *file ; struct sock *sk ; struct proto_ops const *ops ; }; struct proto_ops { int family ; struct module *owner ; int (*release)(struct socket * ) ; int (*bind)(struct socket * , struct sockaddr * , int ) ; int (*connect)(struct socket * , struct sockaddr * , int , int ) ; int (*socketpair)(struct socket * , struct socket * ) ; int (*accept)(struct socket * , struct socket * , int ) ; int (*getname)(struct socket * , struct sockaddr * , int * , int ) ; unsigned int (*poll)(struct file * , struct socket * , struct poll_table_struct * ) ; int (*ioctl)(struct socket * , unsigned int , unsigned long ) ; int (*compat_ioctl)(struct socket * , unsigned int , unsigned long ) ; int (*listen)(struct socket * , int ) ; int (*shutdown)(struct socket * , int ) ; int (*setsockopt)(struct socket * , int , int , char * , unsigned int ) ; int (*getsockopt)(struct socket * , int , int , char * , int * ) ; int (*compat_setsockopt)(struct socket * , int , int , char * , unsigned int ) ; int (*compat_getsockopt)(struct socket * , int , int , char * , int * ) ; int (*sendmsg)(struct socket * , struct msghdr * , size_t ) ; int (*recvmsg)(struct socket * , struct msghdr * , size_t , int ) ; int (*mmap)(struct file * , struct socket * , struct vm_area_struct * ) ; ssize_t (*sendpage)(struct socket * , struct page * , int , size_t , int ) ; ssize_t (*splice_read)(struct socket * , loff_t * , struct pipe_inode_info * , size_t , unsigned int ) ; int (*set_peek_off)(struct sock * , int ) ; }; struct exception_table_entry { int insn ; int fixup ; }; struct in6_addr; struct sk_buff; struct klist_node; struct klist_node { void *n_klist ; struct list_head n_node ; struct kref n_ref ; }; struct path; struct seq_file { char *buf ; size_t size ; size_t from ; size_t count ; size_t pad_until ; loff_t index ; loff_t read_pos ; u64 version ; struct mutex lock ; struct seq_operations const *op ; int poll_event ; struct user_namespace *user_ns ; void *private ; }; struct seq_operations { void *(*start)(struct seq_file * , loff_t * ) ; void (*stop)(struct seq_file * , void * ) ; void *(*next)(struct seq_file * , void * , loff_t * ) ; int (*show)(struct seq_file * , void * ) ; }; struct pinctrl; struct pinctrl_state; struct dev_pin_info { struct pinctrl *p ; struct pinctrl_state *default_state ; struct pinctrl_state *sleep_state ; struct pinctrl_state *idle_state ; }; struct dma_map_ops; struct dev_archdata { struct dma_map_ops *dma_ops ; void *iommu ; }; struct pdev_archdata { }; struct device_private; struct device_driver; struct driver_private; struct class; struct subsys_private; struct bus_type; struct device_node; struct fwnode_handle; struct iommu_ops; struct iommu_group; struct device_attribute; struct bus_type { char const *name ; char const *dev_name ; struct device *dev_root ; struct device_attribute *dev_attrs ; struct attribute_group const **bus_groups ; struct attribute_group const **dev_groups ; struct attribute_group const **drv_groups ; int (*match)(struct device * , struct device_driver * ) ; int (*uevent)(struct device * , struct kobj_uevent_env * ) ; int (*probe)(struct device * ) ; int (*remove)(struct device * ) ; void (*shutdown)(struct device * ) ; int (*online)(struct device * ) ; int (*offline)(struct device * ) ; int (*suspend)(struct device * , pm_message_t ) ; int (*resume)(struct device * ) ; struct dev_pm_ops const *pm ; struct iommu_ops const *iommu_ops ; struct subsys_private *p ; struct lock_class_key lock_key ; }; struct device_type; enum probe_type { PROBE_DEFAULT_STRATEGY = 0, PROBE_PREFER_ASYNCHRONOUS = 1, PROBE_FORCE_SYNCHRONOUS = 2 } ; struct of_device_id; struct acpi_device_id; struct device_driver { char const *name ; struct bus_type *bus ; struct module *owner ; char const *mod_name ; bool suppress_bind_attrs ; enum probe_type probe_type ; struct of_device_id const *of_match_table ; struct acpi_device_id const *acpi_match_table ; int (*probe)(struct device * ) ; int (*remove)(struct device * ) ; void (*shutdown)(struct device * ) ; int (*suspend)(struct device * , pm_message_t ) ; int (*resume)(struct device * ) ; struct attribute_group const **groups ; struct dev_pm_ops const *pm ; struct driver_private *p ; }; struct class_attribute; struct class { char const *name ; struct module *owner ; struct class_attribute *class_attrs ; struct attribute_group const **dev_groups ; struct kobject *dev_kobj ; int (*dev_uevent)(struct device * , struct kobj_uevent_env * ) ; char *(*devnode)(struct device * , umode_t * ) ; void (*class_release)(struct class * ) ; void (*dev_release)(struct device * ) ; int (*suspend)(struct device * , pm_message_t ) ; int (*resume)(struct device * ) ; struct kobj_ns_type_operations const *ns_type ; void const *(*namespace)(struct device * ) ; struct dev_pm_ops const *pm ; struct subsys_private *p ; }; struct class_attribute { struct attribute attr ; ssize_t (*show)(struct class * , struct class_attribute * , char * ) ; ssize_t (*store)(struct class * , struct class_attribute * , char const * , size_t ) ; }; struct device_type { char const *name ; struct attribute_group const **groups ; int (*uevent)(struct device * , struct kobj_uevent_env * ) ; char *(*devnode)(struct device * , umode_t * , kuid_t * , kgid_t * ) ; void (*release)(struct device * ) ; struct dev_pm_ops const *pm ; }; struct device_attribute { struct attribute attr ; ssize_t (*show)(struct device * , struct device_attribute * , char * ) ; ssize_t (*store)(struct device * , struct device_attribute * , char const * , size_t ) ; }; struct device_dma_parameters { unsigned int max_segment_size ; unsigned long segment_boundary_mask ; }; struct dma_coherent_mem; struct cma; struct device { struct device *parent ; struct device_private *p ; struct kobject kobj ; char const *init_name ; struct device_type const *type ; struct mutex mutex ; struct bus_type *bus ; struct device_driver *driver ; void *platform_data ; void *driver_data ; struct dev_pm_info power ; struct dev_pm_domain *pm_domain ; struct dev_pin_info *pins ; int numa_node ; u64 *dma_mask ; u64 coherent_dma_mask ; unsigned long dma_pfn_offset ; struct device_dma_parameters *dma_parms ; struct list_head dma_pools ; struct dma_coherent_mem *dma_mem ; struct cma *cma_area ; struct dev_archdata archdata ; struct device_node *of_node ; struct fwnode_handle *fwnode ; dev_t devt ; u32 id ; spinlock_t devres_lock ; struct list_head devres_head ; struct klist_node knode_class ; struct class *class ; struct attribute_group const **groups ; void (*release)(struct device * ) ; struct iommu_group *iommu_group ; bool offline_disabled ; bool offline ; }; struct wakeup_source { char const *name ; struct list_head entry ; spinlock_t lock ; struct wake_irq *wakeirq ; struct timer_list timer ; unsigned long timer_expires ; ktime_t total_time ; ktime_t max_time ; ktime_t last_time ; ktime_t start_prevent_time ; ktime_t prevent_sleep_time ; unsigned long event_count ; unsigned long active_count ; unsigned long relax_count ; unsigned long expire_count ; unsigned long wakeup_count ; bool active ; bool autosleep_enabled ; }; struct dma_attrs { unsigned long flags[1U] ; }; enum dma_data_direction { DMA_BIDIRECTIONAL = 0, DMA_TO_DEVICE = 1, DMA_FROM_DEVICE = 2, DMA_NONE = 3 } ; struct shrink_control { gfp_t gfp_mask ; unsigned long nr_to_scan ; int nid ; struct mem_cgroup *memcg ; }; struct shrinker { unsigned long (*count_objects)(struct shrinker * , struct shrink_control * ) ; unsigned long (*scan_objects)(struct shrinker * , struct shrink_control * ) ; int seeks ; long batch ; unsigned long flags ; struct list_head list ; atomic_long_t *nr_deferred ; }; struct file_ra_state; struct writeback_control; struct bdi_writeback; struct vm_fault { unsigned int flags ; unsigned long pgoff ; void *virtual_address ; struct page *cow_page ; struct page *page ; unsigned long max_pgoff ; pte_t *pte ; }; struct vm_operations_struct { void (*open)(struct vm_area_struct * ) ; void (*close)(struct vm_area_struct * ) ; int (*fault)(struct vm_area_struct * , struct vm_fault * ) ; void (*map_pages)(struct vm_area_struct * , struct vm_fault * ) ; int (*page_mkwrite)(struct vm_area_struct * , struct vm_fault * ) ; int (*pfn_mkwrite)(struct vm_area_struct * , struct vm_fault * ) ; int (*access)(struct vm_area_struct * , unsigned long , void * , int , int ) ; char const *(*name)(struct vm_area_struct * ) ; int (*set_policy)(struct vm_area_struct * , struct mempolicy * ) ; struct mempolicy *(*get_policy)(struct vm_area_struct * , unsigned long ) ; struct page *(*find_special_page)(struct vm_area_struct * , unsigned long ) ; }; struct scatterlist { unsigned long sg_magic ; unsigned long page_link ; unsigned int offset ; unsigned int length ; dma_addr_t dma_address ; unsigned int dma_length ; }; struct sg_table { struct scatterlist *sgl ; unsigned int nents ; unsigned int orig_nents ; }; struct dma_map_ops { void *(*alloc)(struct device * , size_t , dma_addr_t * , gfp_t , struct dma_attrs * ) ; void (*free)(struct device * , size_t , void * , dma_addr_t , struct dma_attrs * ) ; int (*mmap)(struct device * , struct vm_area_struct * , void * , dma_addr_t , size_t , struct dma_attrs * ) ; int (*get_sgtable)(struct device * , struct sg_table * , void * , dma_addr_t , size_t , struct dma_attrs * ) ; dma_addr_t (*map_page)(struct device * , struct page * , unsigned long , size_t , enum dma_data_direction , struct dma_attrs * ) ; void (*unmap_page)(struct device * , dma_addr_t , size_t , enum dma_data_direction , struct dma_attrs * ) ; int (*map_sg)(struct device * , struct scatterlist * , int , enum dma_data_direction , struct dma_attrs * ) ; void (*unmap_sg)(struct device * , struct scatterlist * , int , enum dma_data_direction , struct dma_attrs * ) ; void (*sync_single_for_cpu)(struct device * , dma_addr_t , size_t , enum dma_data_direction ) ; void (*sync_single_for_device)(struct device * , dma_addr_t , size_t , enum dma_data_direction ) ; void (*sync_sg_for_cpu)(struct device * , struct scatterlist * , int , enum dma_data_direction ) ; void (*sync_sg_for_device)(struct device * , struct scatterlist * , int , enum dma_data_direction ) ; int (*mapping_error)(struct device * , dma_addr_t ) ; int (*dma_supported)(struct device * , u64 ) ; int (*set_dma_mask)(struct device * , u64 ) ; int is_phys ; }; typedef u64 netdev_features_t; union __anonunion_in6_u_218 { __u8 u6_addr8[16U] ; __be16 u6_addr16[8U] ; __be32 u6_addr32[4U] ; }; struct in6_addr { union __anonunion_in6_u_218 in6_u ; }; struct ethhdr { unsigned char h_dest[6U] ; unsigned char h_source[6U] ; __be16 h_proto ; }; struct pipe_buf_operations; struct pipe_buffer { struct page *page ; unsigned int offset ; unsigned int len ; struct pipe_buf_operations const *ops ; unsigned int flags ; unsigned long private ; }; struct pipe_inode_info { struct mutex mutex ; wait_queue_head_t wait ; unsigned int nrbufs ; unsigned int curbuf ; unsigned int buffers ; unsigned int readers ; unsigned int writers ; unsigned int files ; unsigned int waiting_writers ; unsigned int r_counter ; unsigned int w_counter ; struct page *tmp_page ; struct fasync_struct *fasync_readers ; struct fasync_struct *fasync_writers ; struct pipe_buffer *bufs ; }; struct pipe_buf_operations { int can_merge ; int (*confirm)(struct pipe_inode_info * , struct pipe_buffer * ) ; void (*release)(struct pipe_inode_info * , struct pipe_buffer * ) ; int (*steal)(struct pipe_inode_info * , struct pipe_buffer * ) ; void (*get)(struct pipe_inode_info * , struct pipe_buffer * ) ; }; struct napi_struct; struct nf_conntrack { atomic_t use ; }; union __anonunion____missing_field_name_223 { struct net_device *physoutdev ; char neigh_header[8U] ; }; union __anonunion____missing_field_name_224 { __be32 ipv4_daddr ; struct in6_addr ipv6_daddr ; }; struct nf_bridge_info { atomic_t use ; unsigned char orig_proto ; bool pkt_otherhost ; __u16 frag_max_size ; unsigned int mask ; struct net_device *physindev ; union __anonunion____missing_field_name_223 __annonCompField62 ; union __anonunion____missing_field_name_224 __annonCompField63 ; }; struct sk_buff_head { struct sk_buff *next ; struct sk_buff *prev ; __u32 qlen ; spinlock_t lock ; }; typedef unsigned int sk_buff_data_t; struct __anonstruct____missing_field_name_227 { u32 stamp_us ; u32 stamp_jiffies ; }; union __anonunion____missing_field_name_226 { u64 v64 ; struct __anonstruct____missing_field_name_227 __annonCompField64 ; }; struct skb_mstamp { union __anonunion____missing_field_name_226 __annonCompField65 ; }; union __anonunion____missing_field_name_230 { ktime_t tstamp ; struct skb_mstamp skb_mstamp ; }; struct __anonstruct____missing_field_name_229 { struct sk_buff *next ; struct sk_buff *prev ; union __anonunion____missing_field_name_230 __annonCompField66 ; }; union __anonunion____missing_field_name_228 { struct __anonstruct____missing_field_name_229 __annonCompField67 ; struct rb_node rbnode ; }; struct sec_path; struct __anonstruct____missing_field_name_232 { __u16 csum_start ; __u16 csum_offset ; }; union __anonunion____missing_field_name_231 { __wsum csum ; struct __anonstruct____missing_field_name_232 __annonCompField69 ; }; union __anonunion____missing_field_name_233 { unsigned int napi_id ; unsigned int sender_cpu ; }; union __anonunion____missing_field_name_234 { __u32 mark ; __u32 reserved_tailroom ; }; union __anonunion____missing_field_name_235 { __be16 inner_protocol ; __u8 inner_ipproto ; }; struct sk_buff { union __anonunion____missing_field_name_228 __annonCompField68 ; struct sock *sk ; struct net_device *dev ; char cb[48U] ; unsigned long _skb_refdst ; void (*destructor)(struct sk_buff * ) ; struct sec_path *sp ; struct nf_conntrack *nfct ; struct nf_bridge_info *nf_bridge ; unsigned int len ; unsigned int data_len ; __u16 mac_len ; __u16 hdr_len ; __u16 queue_mapping ; unsigned char cloned : 1 ; unsigned char nohdr : 1 ; unsigned char fclone : 2 ; unsigned char peeked : 1 ; unsigned char head_frag : 1 ; unsigned char xmit_more : 1 ; __u32 headers_start[0U] ; __u8 __pkt_type_offset[0U] ; unsigned char pkt_type : 3 ; unsigned char pfmemalloc : 1 ; unsigned char ignore_df : 1 ; unsigned char nfctinfo : 3 ; unsigned char nf_trace : 1 ; unsigned char ip_summed : 2 ; unsigned char ooo_okay : 1 ; unsigned char l4_hash : 1 ; unsigned char sw_hash : 1 ; unsigned char wifi_acked_valid : 1 ; unsigned char wifi_acked : 1 ; unsigned char no_fcs : 1 ; unsigned char encapsulation : 1 ; unsigned char encap_hdr_csum : 1 ; unsigned char csum_valid : 1 ; unsigned char csum_complete_sw : 1 ; unsigned char csum_level : 2 ; unsigned char csum_bad : 1 ; unsigned char ndisc_nodetype : 2 ; unsigned char ipvs_property : 1 ; unsigned char inner_protocol_type : 1 ; unsigned char remcsum_offload : 1 ; __u16 tc_index ; __u16 tc_verd ; union __anonunion____missing_field_name_231 __annonCompField70 ; __u32 priority ; int skb_iif ; __u32 hash ; __be16 vlan_proto ; __u16 vlan_tci ; union __anonunion____missing_field_name_233 __annonCompField71 ; __u32 secmark ; union __anonunion____missing_field_name_234 __annonCompField72 ; union __anonunion____missing_field_name_235 __annonCompField73 ; __u16 inner_transport_header ; __u16 inner_network_header ; __u16 inner_mac_header ; __be16 protocol ; __u16 transport_header ; __u16 network_header ; __u16 mac_header ; __u32 headers_end[0U] ; sk_buff_data_t tail ; sk_buff_data_t end ; unsigned char *head ; unsigned char *data ; unsigned int truesize ; atomic_t users ; }; struct dst_entry; struct dql { unsigned int num_queued ; unsigned int adj_limit ; unsigned int last_obj_cnt ; unsigned int limit ; unsigned int num_completed ; unsigned int prev_ovlimit ; unsigned int prev_num_queued ; unsigned int prev_last_obj_cnt ; unsigned int lowest_slack ; unsigned long slack_start_time ; unsigned int max_limit ; unsigned int min_limit ; unsigned int slack_hold_time ; }; struct __anonstruct_sync_serial_settings_237 { unsigned int clock_rate ; unsigned int clock_type ; unsigned short loopback ; }; typedef struct __anonstruct_sync_serial_settings_237 sync_serial_settings; struct __anonstruct_te1_settings_238 { unsigned int clock_rate ; unsigned int clock_type ; unsigned short loopback ; unsigned int slot_map ; }; typedef struct __anonstruct_te1_settings_238 te1_settings; struct __anonstruct_raw_hdlc_proto_239 { unsigned short encoding ; unsigned short parity ; }; typedef struct __anonstruct_raw_hdlc_proto_239 raw_hdlc_proto; struct __anonstruct_fr_proto_240 { unsigned int t391 ; unsigned int t392 ; unsigned int n391 ; unsigned int n392 ; unsigned int n393 ; unsigned short lmi ; unsigned short dce ; }; typedef struct __anonstruct_fr_proto_240 fr_proto; struct __anonstruct_fr_proto_pvc_241 { unsigned int dlci ; }; typedef struct __anonstruct_fr_proto_pvc_241 fr_proto_pvc; struct __anonstruct_fr_proto_pvc_info_242 { unsigned int dlci ; char master[16U] ; }; typedef struct __anonstruct_fr_proto_pvc_info_242 fr_proto_pvc_info; struct __anonstruct_cisco_proto_243 { unsigned int interval ; unsigned int timeout ; }; typedef struct __anonstruct_cisco_proto_243 cisco_proto; struct ifmap { unsigned long mem_start ; unsigned long mem_end ; unsigned short base_addr ; unsigned char irq ; unsigned char dma ; unsigned char port ; }; union __anonunion_ifs_ifsu_244 { raw_hdlc_proto *raw_hdlc ; cisco_proto *cisco ; fr_proto *fr ; fr_proto_pvc *fr_pvc ; fr_proto_pvc_info *fr_pvc_info ; sync_serial_settings *sync ; te1_settings *te1 ; }; struct if_settings { unsigned int type ; unsigned int size ; union __anonunion_ifs_ifsu_244 ifs_ifsu ; }; union __anonunion_ifr_ifrn_245 { char ifrn_name[16U] ; }; union __anonunion_ifr_ifru_246 { struct sockaddr ifru_addr ; struct sockaddr ifru_dstaddr ; struct sockaddr ifru_broadaddr ; struct sockaddr ifru_netmask ; struct sockaddr ifru_hwaddr ; short ifru_flags ; int ifru_ivalue ; int ifru_mtu ; struct ifmap ifru_map ; char ifru_slave[16U] ; char ifru_newname[16U] ; void *ifru_data ; struct if_settings ifru_settings ; }; struct ifreq { union __anonunion_ifr_ifrn_245 ifr_ifrn ; union __anonunion_ifr_ifru_246 ifr_ifru ; }; struct hlist_bl_node; struct hlist_bl_head { struct hlist_bl_node *first ; }; struct hlist_bl_node { struct hlist_bl_node *next ; struct hlist_bl_node **pprev ; }; struct __anonstruct____missing_field_name_251 { spinlock_t lock ; int count ; }; union __anonunion____missing_field_name_250 { struct __anonstruct____missing_field_name_251 __annonCompField74 ; }; struct lockref { union __anonunion____missing_field_name_250 __annonCompField75 ; }; struct vfsmount; struct __anonstruct____missing_field_name_253 { u32 hash ; u32 len ; }; union __anonunion____missing_field_name_252 { struct __anonstruct____missing_field_name_253 __annonCompField76 ; u64 hash_len ; }; struct qstr { union __anonunion____missing_field_name_252 __annonCompField77 ; unsigned char const *name ; }; struct dentry_operations; union __anonunion_d_u_254 { struct hlist_node d_alias ; struct callback_head d_rcu ; }; struct dentry { unsigned int d_flags ; seqcount_t d_seq ; struct hlist_bl_node d_hash ; struct dentry *d_parent ; struct qstr d_name ; struct inode *d_inode ; unsigned char d_iname[32U] ; struct lockref d_lockref ; struct dentry_operations const *d_op ; struct super_block *d_sb ; unsigned long d_time ; void *d_fsdata ; struct list_head d_lru ; struct list_head d_child ; struct list_head d_subdirs ; union __anonunion_d_u_254 d_u ; }; struct dentry_operations { int (*d_revalidate)(struct dentry * , unsigned int ) ; int (*d_weak_revalidate)(struct dentry * , unsigned int ) ; int (*d_hash)(struct dentry const * , struct qstr * ) ; int (*d_compare)(struct dentry const * , struct dentry const * , unsigned int , char const * , struct qstr const * ) ; int (*d_delete)(struct dentry const * ) ; void (*d_release)(struct dentry * ) ; void (*d_prune)(struct dentry * ) ; void (*d_iput)(struct dentry * , struct inode * ) ; char *(*d_dname)(struct dentry * , char * , int ) ; struct vfsmount *(*d_automount)(struct path * ) ; int (*d_manage)(struct dentry * , bool ) ; struct inode *(*d_select_inode)(struct dentry * , unsigned int ) ; }; struct path { struct vfsmount *mnt ; struct dentry *dentry ; }; struct list_lru_one { struct list_head list ; long nr_items ; }; struct list_lru_memcg { struct list_lru_one *lru[0U] ; }; struct list_lru_node { spinlock_t lock ; struct list_lru_one lru ; struct list_lru_memcg *memcg_lrus ; }; struct list_lru { struct list_lru_node *node ; struct list_head list ; }; struct __anonstruct____missing_field_name_258 { struct radix_tree_node *parent ; void *private_data ; }; union __anonunion____missing_field_name_257 { struct __anonstruct____missing_field_name_258 __annonCompField78 ; struct callback_head callback_head ; }; struct radix_tree_node { unsigned int path ; unsigned int count ; union __anonunion____missing_field_name_257 __annonCompField79 ; struct list_head private_list ; void *slots[64U] ; unsigned long tags[3U][1U] ; }; struct radix_tree_root { unsigned int height ; gfp_t gfp_mask ; struct radix_tree_node *rnode ; }; struct fiemap_extent { __u64 fe_logical ; __u64 fe_physical ; __u64 fe_length ; __u64 fe_reserved64[2U] ; __u32 fe_flags ; __u32 fe_reserved[3U] ; }; enum migrate_mode { MIGRATE_ASYNC = 0, MIGRATE_SYNC_LIGHT = 1, MIGRATE_SYNC = 2 } ; struct block_device; struct bio_vec { struct page *bv_page ; unsigned int bv_len ; unsigned int bv_offset ; }; struct export_operations; struct kstatfs; struct swap_info_struct; struct iattr { unsigned int ia_valid ; umode_t ia_mode ; kuid_t ia_uid ; kgid_t ia_gid ; loff_t ia_size ; struct timespec ia_atime ; struct timespec ia_mtime ; struct timespec ia_ctime ; struct file *ia_file ; }; struct dquot; typedef __kernel_uid32_t projid_t; struct __anonstruct_kprojid_t_262 { projid_t val ; }; typedef struct __anonstruct_kprojid_t_262 kprojid_t; enum quota_type { USRQUOTA = 0, GRPQUOTA = 1, PRJQUOTA = 2 } ; typedef long long qsize_t; union __anonunion____missing_field_name_263 { kuid_t uid ; kgid_t gid ; kprojid_t projid ; }; struct kqid { union __anonunion____missing_field_name_263 __annonCompField81 ; enum quota_type type ; }; struct mem_dqblk { qsize_t dqb_bhardlimit ; qsize_t dqb_bsoftlimit ; qsize_t dqb_curspace ; qsize_t dqb_rsvspace ; qsize_t dqb_ihardlimit ; qsize_t dqb_isoftlimit ; qsize_t dqb_curinodes ; time_t dqb_btime ; time_t dqb_itime ; }; struct quota_format_type; struct mem_dqinfo { struct quota_format_type *dqi_format ; int dqi_fmt_id ; struct list_head dqi_dirty_list ; unsigned long dqi_flags ; unsigned int dqi_bgrace ; unsigned int dqi_igrace ; qsize_t dqi_max_spc_limit ; qsize_t dqi_max_ino_limit ; void *dqi_priv ; }; struct dquot { struct hlist_node dq_hash ; struct list_head dq_inuse ; struct list_head dq_free ; struct list_head dq_dirty ; struct mutex dq_lock ; atomic_t dq_count ; wait_queue_head_t dq_wait_unused ; struct super_block *dq_sb ; struct kqid dq_id ; loff_t dq_off ; unsigned long dq_flags ; struct mem_dqblk dq_dqb ; }; struct quota_format_ops { int (*check_quota_file)(struct super_block * , int ) ; int (*read_file_info)(struct super_block * , int ) ; int (*write_file_info)(struct super_block * , int ) ; int (*free_file_info)(struct super_block * , int ) ; int (*read_dqblk)(struct dquot * ) ; int (*commit_dqblk)(struct dquot * ) ; int (*release_dqblk)(struct dquot * ) ; }; struct dquot_operations { int (*write_dquot)(struct dquot * ) ; struct dquot *(*alloc_dquot)(struct super_block * , int ) ; void (*destroy_dquot)(struct dquot * ) ; int (*acquire_dquot)(struct dquot * ) ; int (*release_dquot)(struct dquot * ) ; int (*mark_dirty)(struct dquot * ) ; int (*write_info)(struct super_block * , int ) ; qsize_t *(*get_reserved_space)(struct inode * ) ; int (*get_projid)(struct inode * , kprojid_t * ) ; }; struct qc_dqblk { int d_fieldmask ; u64 d_spc_hardlimit ; u64 d_spc_softlimit ; u64 d_ino_hardlimit ; u64 d_ino_softlimit ; u64 d_space ; u64 d_ino_count ; s64 d_ino_timer ; s64 d_spc_timer ; int d_ino_warns ; int d_spc_warns ; u64 d_rt_spc_hardlimit ; u64 d_rt_spc_softlimit ; u64 d_rt_space ; s64 d_rt_spc_timer ; int d_rt_spc_warns ; }; struct qc_type_state { unsigned int flags ; unsigned int spc_timelimit ; unsigned int ino_timelimit ; unsigned int rt_spc_timelimit ; unsigned int spc_warnlimit ; unsigned int ino_warnlimit ; unsigned int rt_spc_warnlimit ; unsigned long long ino ; blkcnt_t blocks ; blkcnt_t nextents ; }; struct qc_state { unsigned int s_incoredqs ; struct qc_type_state s_state[3U] ; }; struct qc_info { int i_fieldmask ; unsigned int i_flags ; unsigned int i_spc_timelimit ; unsigned int i_ino_timelimit ; unsigned int i_rt_spc_timelimit ; unsigned int i_spc_warnlimit ; unsigned int i_ino_warnlimit ; unsigned int i_rt_spc_warnlimit ; }; struct quotactl_ops { int (*quota_on)(struct super_block * , int , int , struct path * ) ; int (*quota_off)(struct super_block * , int ) ; int (*quota_enable)(struct super_block * , unsigned int ) ; int (*quota_disable)(struct super_block * , unsigned int ) ; int (*quota_sync)(struct super_block * , int ) ; int (*set_info)(struct super_block * , int , struct qc_info * ) ; int (*get_dqblk)(struct super_block * , struct kqid , struct qc_dqblk * ) ; int (*set_dqblk)(struct super_block * , struct kqid , struct qc_dqblk * ) ; int (*get_state)(struct super_block * , struct qc_state * ) ; int (*rm_xquota)(struct super_block * , unsigned int ) ; }; struct quota_format_type { int qf_fmt_id ; struct quota_format_ops const *qf_ops ; struct module *qf_owner ; struct quota_format_type *qf_next ; }; struct quota_info { unsigned int flags ; struct mutex dqio_mutex ; struct mutex dqonoff_mutex ; struct inode *files[3U] ; struct mem_dqinfo info[3U] ; struct quota_format_ops const *ops[3U] ; }; struct kiocb { struct file *ki_filp ; loff_t ki_pos ; void (*ki_complete)(struct kiocb * , long , long ) ; void *private ; int ki_flags ; }; struct address_space_operations { int (*writepage)(struct page * , struct writeback_control * ) ; int (*readpage)(struct file * , struct page * ) ; int (*writepages)(struct address_space * , struct writeback_control * ) ; int (*set_page_dirty)(struct page * ) ; int (*readpages)(struct file * , struct address_space * , struct list_head * , unsigned int ) ; int (*write_begin)(struct file * , struct address_space * , loff_t , unsigned int , unsigned int , struct page ** , void ** ) ; int (*write_end)(struct file * , struct address_space * , loff_t , unsigned int , unsigned int , struct page * , void * ) ; sector_t (*bmap)(struct address_space * , sector_t ) ; void (*invalidatepage)(struct page * , unsigned int , unsigned int ) ; int (*releasepage)(struct page * , gfp_t ) ; void (*freepage)(struct page * ) ; ssize_t (*direct_IO)(struct kiocb * , struct iov_iter * , loff_t ) ; int (*migratepage)(struct address_space * , struct page * , struct page * , enum migrate_mode ) ; int (*launder_page)(struct page * ) ; int (*is_partially_uptodate)(struct page * , unsigned long , unsigned long ) ; void (*is_dirty_writeback)(struct page * , bool * , bool * ) ; int (*error_remove_page)(struct address_space * , struct page * ) ; int (*swap_activate)(struct swap_info_struct * , struct file * , sector_t * ) ; void (*swap_deactivate)(struct file * ) ; }; struct address_space { struct inode *host ; struct radix_tree_root page_tree ; spinlock_t tree_lock ; atomic_t i_mmap_writable ; struct rb_root i_mmap ; struct rw_semaphore i_mmap_rwsem ; unsigned long nrpages ; unsigned long nrshadows ; unsigned long writeback_index ; struct address_space_operations const *a_ops ; unsigned long flags ; spinlock_t private_lock ; struct list_head private_list ; void *private_data ; }; struct request_queue; struct hd_struct; struct gendisk; struct block_device { dev_t bd_dev ; int bd_openers ; struct inode *bd_inode ; struct super_block *bd_super ; struct mutex bd_mutex ; struct list_head bd_inodes ; void *bd_claiming ; void *bd_holder ; int bd_holders ; bool bd_write_holder ; struct list_head bd_holder_disks ; struct block_device *bd_contains ; unsigned int bd_block_size ; struct hd_struct *bd_part ; unsigned int bd_part_count ; int bd_invalidated ; struct gendisk *bd_disk ; struct request_queue *bd_queue ; struct list_head bd_list ; unsigned long bd_private ; int bd_fsfreeze_count ; struct mutex bd_fsfreeze_mutex ; }; struct posix_acl; struct inode_operations; union __anonunion____missing_field_name_266 { unsigned int const i_nlink ; unsigned int __i_nlink ; }; union __anonunion____missing_field_name_267 { struct hlist_head i_dentry ; struct callback_head i_rcu ; }; struct file_lock_context; struct cdev; union __anonunion____missing_field_name_268 { struct pipe_inode_info *i_pipe ; struct block_device *i_bdev ; struct cdev *i_cdev ; char *i_link ; }; struct inode { umode_t i_mode ; unsigned short i_opflags ; kuid_t i_uid ; kgid_t i_gid ; unsigned int i_flags ; struct posix_acl *i_acl ; struct posix_acl *i_default_acl ; struct inode_operations const *i_op ; struct super_block *i_sb ; struct address_space *i_mapping ; void *i_security ; unsigned long i_ino ; union __anonunion____missing_field_name_266 __annonCompField82 ; dev_t i_rdev ; loff_t i_size ; struct timespec i_atime ; struct timespec i_mtime ; struct timespec i_ctime ; spinlock_t i_lock ; unsigned short i_bytes ; unsigned int i_blkbits ; blkcnt_t i_blocks ; unsigned long i_state ; struct mutex i_mutex ; unsigned long dirtied_when ; unsigned long dirtied_time_when ; struct hlist_node i_hash ; struct list_head i_wb_list ; struct bdi_writeback *i_wb ; int i_wb_frn_winner ; u16 i_wb_frn_avg_time ; u16 i_wb_frn_history ; struct list_head i_lru ; struct list_head i_sb_list ; union __anonunion____missing_field_name_267 __annonCompField83 ; u64 i_version ; atomic_t i_count ; atomic_t i_dio_count ; atomic_t i_writecount ; atomic_t i_readcount ; struct file_operations const *i_fop ; struct file_lock_context *i_flctx ; struct address_space i_data ; struct list_head i_devices ; union __anonunion____missing_field_name_268 __annonCompField84 ; __u32 i_generation ; __u32 i_fsnotify_mask ; struct hlist_head i_fsnotify_marks ; void *i_private ; }; struct fown_struct { rwlock_t lock ; struct pid *pid ; enum pid_type pid_type ; kuid_t uid ; kuid_t euid ; int signum ; }; struct file_ra_state { unsigned long start ; unsigned int size ; unsigned int async_size ; unsigned int ra_pages ; unsigned int mmap_miss ; loff_t prev_pos ; }; union __anonunion_f_u_269 { struct llist_node fu_llist ; struct callback_head fu_rcuhead ; }; struct file { union __anonunion_f_u_269 f_u ; struct path f_path ; struct inode *f_inode ; struct file_operations const *f_op ; spinlock_t f_lock ; atomic_long_t f_count ; unsigned int f_flags ; fmode_t f_mode ; struct mutex f_pos_lock ; loff_t f_pos ; struct fown_struct f_owner ; struct cred const *f_cred ; struct file_ra_state f_ra ; u64 f_version ; void *f_security ; void *private_data ; struct list_head f_ep_links ; struct list_head f_tfile_llink ; struct address_space *f_mapping ; }; typedef void *fl_owner_t; struct file_lock; struct file_lock_operations { void (*fl_copy_lock)(struct file_lock * , struct file_lock * ) ; void (*fl_release_private)(struct file_lock * ) ; }; struct lock_manager_operations { int (*lm_compare_owner)(struct file_lock * , struct file_lock * ) ; unsigned long (*lm_owner_key)(struct file_lock * ) ; fl_owner_t (*lm_get_owner)(fl_owner_t ) ; void (*lm_put_owner)(fl_owner_t ) ; void (*lm_notify)(struct file_lock * ) ; int (*lm_grant)(struct file_lock * , int ) ; bool (*lm_break)(struct file_lock * ) ; int (*lm_change)(struct file_lock * , int , struct list_head * ) ; void (*lm_setup)(struct file_lock * , void ** ) ; }; struct nlm_lockowner; struct nfs_lock_info { u32 state ; struct nlm_lockowner *owner ; struct list_head list ; }; struct nfs4_lock_state; struct nfs4_lock_info { struct nfs4_lock_state *owner ; }; struct __anonstruct_afs_271 { struct list_head link ; int state ; }; union __anonunion_fl_u_270 { struct nfs_lock_info nfs_fl ; struct nfs4_lock_info nfs4_fl ; struct __anonstruct_afs_271 afs ; }; struct file_lock { struct file_lock *fl_next ; struct list_head fl_list ; struct hlist_node fl_link ; struct list_head fl_block ; fl_owner_t fl_owner ; unsigned int fl_flags ; unsigned char fl_type ; unsigned int fl_pid ; int fl_link_cpu ; struct pid *fl_nspid ; wait_queue_head_t fl_wait ; struct file *fl_file ; loff_t fl_start ; loff_t fl_end ; struct fasync_struct *fl_fasync ; unsigned long fl_break_time ; unsigned long fl_downgrade_time ; struct file_lock_operations const *fl_ops ; struct lock_manager_operations const *fl_lmops ; union __anonunion_fl_u_270 fl_u ; }; struct file_lock_context { spinlock_t flc_lock ; struct list_head flc_flock ; struct list_head flc_posix ; struct list_head flc_lease ; }; struct fasync_struct { spinlock_t fa_lock ; int magic ; int fa_fd ; struct fasync_struct *fa_next ; struct file *fa_file ; struct callback_head fa_rcu ; }; struct sb_writers { struct percpu_counter counter[3U] ; wait_queue_head_t wait ; int frozen ; wait_queue_head_t wait_unfrozen ; struct lockdep_map lock_map[3U] ; }; struct super_operations; struct xattr_handler; struct mtd_info; struct super_block { struct list_head s_list ; dev_t s_dev ; unsigned char s_blocksize_bits ; unsigned long s_blocksize ; loff_t s_maxbytes ; struct file_system_type *s_type ; struct super_operations const *s_op ; struct dquot_operations const *dq_op ; struct quotactl_ops const *s_qcop ; struct export_operations const *s_export_op ; unsigned long s_flags ; unsigned long s_iflags ; unsigned long s_magic ; struct dentry *s_root ; struct rw_semaphore s_umount ; int s_count ; atomic_t s_active ; void *s_security ; struct xattr_handler const **s_xattr ; struct list_head s_inodes ; struct hlist_bl_head s_anon ; struct list_head s_mounts ; struct block_device *s_bdev ; struct backing_dev_info *s_bdi ; struct mtd_info *s_mtd ; struct hlist_node s_instances ; unsigned int s_quota_types ; struct quota_info s_dquot ; struct sb_writers s_writers ; char s_id[32U] ; u8 s_uuid[16U] ; void *s_fs_info ; unsigned int s_max_links ; fmode_t s_mode ; u32 s_time_gran ; struct mutex s_vfs_rename_mutex ; char *s_subtype ; char *s_options ; struct dentry_operations const *s_d_op ; int cleancache_poolid ; struct shrinker s_shrink ; atomic_long_t s_remove_count ; int s_readonly_remount ; struct workqueue_struct *s_dio_done_wq ; struct hlist_head s_pins ; struct list_lru s_dentry_lru ; struct list_lru s_inode_lru ; struct callback_head rcu ; int s_stack_depth ; }; struct fiemap_extent_info { unsigned int fi_flags ; unsigned int fi_extents_mapped ; unsigned int fi_extents_max ; struct fiemap_extent *fi_extents_start ; }; struct dir_context; struct dir_context { int (*actor)(struct dir_context * , char const * , int , loff_t , u64 , unsigned int ) ; loff_t pos ; }; struct file_operations { struct module *owner ; loff_t (*llseek)(struct file * , loff_t , int ) ; ssize_t (*read)(struct file * , char * , size_t , loff_t * ) ; ssize_t (*write)(struct file * , char const * , size_t , loff_t * ) ; ssize_t (*read_iter)(struct kiocb * , struct iov_iter * ) ; ssize_t (*write_iter)(struct kiocb * , struct iov_iter * ) ; int (*iterate)(struct file * , struct dir_context * ) ; unsigned int (*poll)(struct file * , struct poll_table_struct * ) ; long (*unlocked_ioctl)(struct file * , unsigned int , unsigned long ) ; long (*compat_ioctl)(struct file * , unsigned int , unsigned long ) ; int (*mmap)(struct file * , struct vm_area_struct * ) ; int (*mremap)(struct file * , struct vm_area_struct * ) ; int (*open)(struct inode * , struct file * ) ; int (*flush)(struct file * , fl_owner_t ) ; int (*release)(struct inode * , struct file * ) ; int (*fsync)(struct file * , loff_t , loff_t , int ) ; int (*aio_fsync)(struct kiocb * , int ) ; int (*fasync)(int , struct file * , int ) ; int (*lock)(struct file * , int , struct file_lock * ) ; ssize_t (*sendpage)(struct file * , struct page * , int , size_t , loff_t * , int ) ; unsigned long (*get_unmapped_area)(struct file * , unsigned long , unsigned long , unsigned long , unsigned long ) ; int (*check_flags)(int ) ; int (*flock)(struct file * , int , struct file_lock * ) ; ssize_t (*splice_write)(struct pipe_inode_info * , struct file * , loff_t * , size_t , unsigned int ) ; ssize_t (*splice_read)(struct file * , loff_t * , struct pipe_inode_info * , size_t , unsigned int ) ; int (*setlease)(struct file * , long , struct file_lock ** , void ** ) ; long (*fallocate)(struct file * , int , loff_t , loff_t ) ; void (*show_fdinfo)(struct seq_file * , struct file * ) ; }; struct inode_operations { struct dentry *(*lookup)(struct inode * , struct dentry * , unsigned int ) ; char const *(*follow_link)(struct dentry * , void ** ) ; int (*permission)(struct inode * , int ) ; struct posix_acl *(*get_acl)(struct inode * , int ) ; int (*readlink)(struct dentry * , char * , int ) ; void (*put_link)(struct inode * , void * ) ; int (*create)(struct inode * , struct dentry * , umode_t , bool ) ; int (*link)(struct dentry * , struct inode * , struct dentry * ) ; int (*unlink)(struct inode * , struct dentry * ) ; int (*symlink)(struct inode * , struct dentry * , char const * ) ; int (*mkdir)(struct inode * , struct dentry * , umode_t ) ; int (*rmdir)(struct inode * , struct dentry * ) ; int (*mknod)(struct inode * , struct dentry * , umode_t , dev_t ) ; int (*rename)(struct inode * , struct dentry * , struct inode * , struct dentry * ) ; int (*rename2)(struct inode * , struct dentry * , struct inode * , struct dentry * , unsigned int ) ; int (*setattr)(struct dentry * , struct iattr * ) ; int (*getattr)(struct vfsmount * , struct dentry * , struct kstat * ) ; int (*setxattr)(struct dentry * , char const * , void const * , size_t , int ) ; ssize_t (*getxattr)(struct dentry * , char const * , void * , size_t ) ; ssize_t (*listxattr)(struct dentry * , char * , size_t ) ; int (*removexattr)(struct dentry * , char const * ) ; int (*fiemap)(struct inode * , struct fiemap_extent_info * , u64 , u64 ) ; int (*update_time)(struct inode * , struct timespec * , int ) ; int (*atomic_open)(struct inode * , struct dentry * , struct file * , unsigned int , umode_t , int * ) ; int (*tmpfile)(struct inode * , struct dentry * , umode_t ) ; int (*set_acl)(struct inode * , struct posix_acl * , int ) ; }; struct super_operations { struct inode *(*alloc_inode)(struct super_block * ) ; void (*destroy_inode)(struct inode * ) ; void (*dirty_inode)(struct inode * , int ) ; int (*write_inode)(struct inode * , struct writeback_control * ) ; int (*drop_inode)(struct inode * ) ; void (*evict_inode)(struct inode * ) ; void (*put_super)(struct super_block * ) ; int (*sync_fs)(struct super_block * , int ) ; int (*freeze_super)(struct super_block * ) ; int (*freeze_fs)(struct super_block * ) ; int (*thaw_super)(struct super_block * ) ; int (*unfreeze_fs)(struct super_block * ) ; int (*statfs)(struct dentry * , struct kstatfs * ) ; int (*remount_fs)(struct super_block * , int * , char * ) ; void (*umount_begin)(struct super_block * ) ; int (*show_options)(struct seq_file * , struct dentry * ) ; int (*show_devname)(struct seq_file * , struct dentry * ) ; int (*show_path)(struct seq_file * , struct dentry * ) ; int (*show_stats)(struct seq_file * , struct dentry * ) ; ssize_t (*quota_read)(struct super_block * , int , char * , size_t , loff_t ) ; ssize_t (*quota_write)(struct super_block * , int , char const * , size_t , loff_t ) ; struct dquot **(*get_dquots)(struct inode * ) ; int (*bdev_try_to_free_page)(struct super_block * , struct page * , gfp_t ) ; long (*nr_cached_objects)(struct super_block * , struct shrink_control * ) ; long (*free_cached_objects)(struct super_block * , struct shrink_control * ) ; }; struct file_system_type { char const *name ; int fs_flags ; struct dentry *(*mount)(struct file_system_type * , int , char const * , void * ) ; void (*kill_sb)(struct super_block * ) ; struct module *owner ; struct file_system_type *next ; struct hlist_head fs_supers ; struct lock_class_key s_lock_key ; struct lock_class_key s_umount_key ; struct lock_class_key s_vfs_rename_key ; struct lock_class_key s_writers_key[3U] ; struct lock_class_key i_lock_key ; struct lock_class_key i_mutex_key ; struct lock_class_key i_mutex_dir_key ; }; typedef s32 compat_time_t; typedef s32 compat_long_t; typedef u32 compat_uptr_t; struct compat_timespec { compat_time_t tv_sec ; s32 tv_nsec ; }; struct compat_robust_list { compat_uptr_t next ; }; struct compat_robust_list_head { struct compat_robust_list list ; compat_long_t futex_offset ; compat_uptr_t list_op_pending ; }; struct ethtool_cmd { __u32 cmd ; __u32 supported ; __u32 advertising ; __u16 speed ; __u8 duplex ; __u8 port ; __u8 phy_address ; __u8 transceiver ; __u8 autoneg ; __u8 mdio_support ; __u32 maxtxpkt ; __u32 maxrxpkt ; __u16 speed_hi ; __u8 eth_tp_mdix ; __u8 eth_tp_mdix_ctrl ; __u32 lp_advertising ; __u32 reserved[2U] ; }; struct ethtool_drvinfo { __u32 cmd ; char driver[32U] ; char version[32U] ; char fw_version[32U] ; char bus_info[32U] ; char erom_version[32U] ; char reserved2[12U] ; __u32 n_priv_flags ; __u32 n_stats ; __u32 testinfo_len ; __u32 eedump_len ; __u32 regdump_len ; }; struct ethtool_wolinfo { __u32 cmd ; __u32 supported ; __u32 wolopts ; __u8 sopass[6U] ; }; struct ethtool_tunable { __u32 cmd ; __u32 id ; __u32 type_id ; __u32 len ; void *data[0U] ; }; struct ethtool_regs { __u32 cmd ; __u32 version ; __u32 len ; __u8 data[0U] ; }; struct ethtool_eeprom { __u32 cmd ; __u32 magic ; __u32 offset ; __u32 len ; __u8 data[0U] ; }; struct ethtool_eee { __u32 cmd ; __u32 supported ; __u32 advertised ; __u32 lp_advertised ; __u32 eee_active ; __u32 eee_enabled ; __u32 tx_lpi_enabled ; __u32 tx_lpi_timer ; __u32 reserved[2U] ; }; struct ethtool_modinfo { __u32 cmd ; __u32 type ; __u32 eeprom_len ; __u32 reserved[8U] ; }; struct ethtool_coalesce { __u32 cmd ; __u32 rx_coalesce_usecs ; __u32 rx_max_coalesced_frames ; __u32 rx_coalesce_usecs_irq ; __u32 rx_max_coalesced_frames_irq ; __u32 tx_coalesce_usecs ; __u32 tx_max_coalesced_frames ; __u32 tx_coalesce_usecs_irq ; __u32 tx_max_coalesced_frames_irq ; __u32 stats_block_coalesce_usecs ; __u32 use_adaptive_rx_coalesce ; __u32 use_adaptive_tx_coalesce ; __u32 pkt_rate_low ; __u32 rx_coalesce_usecs_low ; __u32 rx_max_coalesced_frames_low ; __u32 tx_coalesce_usecs_low ; __u32 tx_max_coalesced_frames_low ; __u32 pkt_rate_high ; __u32 rx_coalesce_usecs_high ; __u32 rx_max_coalesced_frames_high ; __u32 tx_coalesce_usecs_high ; __u32 tx_max_coalesced_frames_high ; __u32 rate_sample_interval ; }; struct ethtool_ringparam { __u32 cmd ; __u32 rx_max_pending ; __u32 rx_mini_max_pending ; __u32 rx_jumbo_max_pending ; __u32 tx_max_pending ; __u32 rx_pending ; __u32 rx_mini_pending ; __u32 rx_jumbo_pending ; __u32 tx_pending ; }; struct ethtool_channels { __u32 cmd ; __u32 max_rx ; __u32 max_tx ; __u32 max_other ; __u32 max_combined ; __u32 rx_count ; __u32 tx_count ; __u32 other_count ; __u32 combined_count ; }; struct ethtool_pauseparam { __u32 cmd ; __u32 autoneg ; __u32 rx_pause ; __u32 tx_pause ; }; struct ethtool_test { __u32 cmd ; __u32 flags ; __u32 reserved ; __u32 len ; __u64 data[0U] ; }; struct ethtool_stats { __u32 cmd ; __u32 n_stats ; __u64 data[0U] ; }; struct ethtool_tcpip4_spec { __be32 ip4src ; __be32 ip4dst ; __be16 psrc ; __be16 pdst ; __u8 tos ; }; struct ethtool_ah_espip4_spec { __be32 ip4src ; __be32 ip4dst ; __be32 spi ; __u8 tos ; }; struct ethtool_usrip4_spec { __be32 ip4src ; __be32 ip4dst ; __be32 l4_4_bytes ; __u8 tos ; __u8 ip_ver ; __u8 proto ; }; union ethtool_flow_union { struct ethtool_tcpip4_spec tcp_ip4_spec ; struct ethtool_tcpip4_spec udp_ip4_spec ; struct ethtool_tcpip4_spec sctp_ip4_spec ; struct ethtool_ah_espip4_spec ah_ip4_spec ; struct ethtool_ah_espip4_spec esp_ip4_spec ; struct ethtool_usrip4_spec usr_ip4_spec ; struct ethhdr ether_spec ; __u8 hdata[52U] ; }; struct ethtool_flow_ext { __u8 padding[2U] ; unsigned char h_dest[6U] ; __be16 vlan_etype ; __be16 vlan_tci ; __be32 data[2U] ; }; struct ethtool_rx_flow_spec { __u32 flow_type ; union ethtool_flow_union h_u ; struct ethtool_flow_ext h_ext ; union ethtool_flow_union m_u ; struct ethtool_flow_ext m_ext ; __u64 ring_cookie ; __u32 location ; }; struct ethtool_rxnfc { __u32 cmd ; __u32 flow_type ; __u64 data ; struct ethtool_rx_flow_spec fs ; __u32 rule_cnt ; __u32 rule_locs[0U] ; }; struct ethtool_flash { __u32 cmd ; __u32 region ; char data[128U] ; }; struct ethtool_dump { __u32 cmd ; __u32 version ; __u32 flag ; __u32 len ; __u8 data[0U] ; }; struct ethtool_ts_info { __u32 cmd ; __u32 so_timestamping ; __s32 phc_index ; __u32 tx_types ; __u32 tx_reserved[3U] ; __u32 rx_filters ; __u32 rx_reserved[3U] ; }; enum ethtool_phys_id_state { ETHTOOL_ID_INACTIVE = 0, ETHTOOL_ID_ACTIVE = 1, ETHTOOL_ID_ON = 2, ETHTOOL_ID_OFF = 3 } ; struct ethtool_ops { int (*get_settings)(struct net_device * , struct ethtool_cmd * ) ; int (*set_settings)(struct net_device * , struct ethtool_cmd * ) ; void (*get_drvinfo)(struct net_device * , struct ethtool_drvinfo * ) ; int (*get_regs_len)(struct net_device * ) ; void (*get_regs)(struct net_device * , struct ethtool_regs * , void * ) ; void (*get_wol)(struct net_device * , struct ethtool_wolinfo * ) ; int (*set_wol)(struct net_device * , struct ethtool_wolinfo * ) ; u32 (*get_msglevel)(struct net_device * ) ; void (*set_msglevel)(struct net_device * , u32 ) ; int (*nway_reset)(struct net_device * ) ; u32 (*get_link)(struct net_device * ) ; int (*get_eeprom_len)(struct net_device * ) ; int (*get_eeprom)(struct net_device * , struct ethtool_eeprom * , u8 * ) ; int (*set_eeprom)(struct net_device * , struct ethtool_eeprom * , u8 * ) ; int (*get_coalesce)(struct net_device * , struct ethtool_coalesce * ) ; int (*set_coalesce)(struct net_device * , struct ethtool_coalesce * ) ; void (*get_ringparam)(struct net_device * , struct ethtool_ringparam * ) ; int (*set_ringparam)(struct net_device * , struct ethtool_ringparam * ) ; void (*get_pauseparam)(struct net_device * , struct ethtool_pauseparam * ) ; int (*set_pauseparam)(struct net_device * , struct ethtool_pauseparam * ) ; void (*self_test)(struct net_device * , struct ethtool_test * , u64 * ) ; void (*get_strings)(struct net_device * , u32 , u8 * ) ; int (*set_phys_id)(struct net_device * , enum ethtool_phys_id_state ) ; void (*get_ethtool_stats)(struct net_device * , struct ethtool_stats * , u64 * ) ; int (*begin)(struct net_device * ) ; void (*complete)(struct net_device * ) ; u32 (*get_priv_flags)(struct net_device * ) ; int (*set_priv_flags)(struct net_device * , u32 ) ; int (*get_sset_count)(struct net_device * , int ) ; int (*get_rxnfc)(struct net_device * , struct ethtool_rxnfc * , u32 * ) ; int (*set_rxnfc)(struct net_device * , struct ethtool_rxnfc * ) ; int (*flash_device)(struct net_device * , struct ethtool_flash * ) ; int (*reset)(struct net_device * , u32 * ) ; u32 (*get_rxfh_key_size)(struct net_device * ) ; u32 (*get_rxfh_indir_size)(struct net_device * ) ; int (*get_rxfh)(struct net_device * , u32 * , u8 * , u8 * ) ; int (*set_rxfh)(struct net_device * , u32 const * , u8 const * , u8 const ) ; void (*get_channels)(struct net_device * , struct ethtool_channels * ) ; int (*set_channels)(struct net_device * , struct ethtool_channels * ) ; int (*get_dump_flag)(struct net_device * , struct ethtool_dump * ) ; int (*get_dump_data)(struct net_device * , struct ethtool_dump * , void * ) ; int (*set_dump)(struct net_device * , struct ethtool_dump * ) ; int (*get_ts_info)(struct net_device * , struct ethtool_ts_info * ) ; int (*get_module_info)(struct net_device * , struct ethtool_modinfo * ) ; int (*get_module_eeprom)(struct net_device * , struct ethtool_eeprom * , u8 * ) ; int (*get_eee)(struct net_device * , struct ethtool_eee * ) ; int (*set_eee)(struct net_device * , struct ethtool_eee * ) ; int (*get_tunable)(struct net_device * , struct ethtool_tunable const * , void * ) ; int (*set_tunable)(struct net_device * , struct ethtool_tunable const * , void const * ) ; }; struct prot_inuse; struct netns_core { struct ctl_table_header *sysctl_hdr ; int sysctl_somaxconn ; struct prot_inuse *inuse ; }; struct u64_stats_sync { }; struct ipstats_mib { u64 mibs[36U] ; struct u64_stats_sync syncp ; }; struct icmp_mib { unsigned long mibs[28U] ; }; struct icmpmsg_mib { atomic_long_t mibs[512U] ; }; struct icmpv6_mib { unsigned long mibs[6U] ; }; struct icmpv6msg_mib { atomic_long_t mibs[512U] ; }; struct tcp_mib { unsigned long mibs[16U] ; }; struct udp_mib { unsigned long mibs[9U] ; }; struct linux_mib { unsigned long mibs[115U] ; }; struct linux_xfrm_mib { unsigned long mibs[29U] ; }; struct proc_dir_entry; struct netns_mib { struct tcp_mib *tcp_statistics ; struct ipstats_mib *ip_statistics ; struct linux_mib *net_statistics ; struct udp_mib *udp_statistics ; struct udp_mib *udplite_statistics ; struct icmp_mib *icmp_statistics ; struct icmpmsg_mib *icmpmsg_statistics ; struct proc_dir_entry *proc_net_devsnmp6 ; struct udp_mib *udp_stats_in6 ; struct udp_mib *udplite_stats_in6 ; struct ipstats_mib *ipv6_statistics ; struct icmpv6_mib *icmpv6_statistics ; struct icmpv6msg_mib *icmpv6msg_statistics ; struct linux_xfrm_mib *xfrm_statistics ; }; struct netns_unix { int sysctl_max_dgram_qlen ; struct ctl_table_header *ctl ; }; struct netns_packet { struct mutex sklist_lock ; struct hlist_head sklist ; }; struct netns_frags { struct percpu_counter mem ; int timeout ; int high_thresh ; int low_thresh ; }; struct ipv4_devconf; struct fib_rules_ops; struct fib_table; struct local_ports { seqlock_t lock ; int range[2U] ; bool warned ; }; struct ping_group_range { seqlock_t lock ; kgid_t range[2U] ; }; struct inet_peer_base; struct xt_table; struct netns_ipv4 { struct ctl_table_header *forw_hdr ; struct ctl_table_header *frags_hdr ; struct ctl_table_header *ipv4_hdr ; struct ctl_table_header *route_hdr ; struct ctl_table_header *xfrm4_hdr ; struct ipv4_devconf *devconf_all ; struct ipv4_devconf *devconf_dflt ; struct fib_rules_ops *rules_ops ; bool fib_has_custom_rules ; struct fib_table *fib_local ; struct fib_table *fib_main ; struct fib_table *fib_default ; int fib_num_tclassid_users ; struct hlist_head *fib_table_hash ; bool fib_offload_disabled ; struct sock *fibnl ; struct sock **icmp_sk ; struct sock *mc_autojoin_sk ; struct inet_peer_base *peers ; struct sock **tcp_sk ; struct netns_frags frags ; struct xt_table *iptable_filter ; struct xt_table *iptable_mangle ; struct xt_table *iptable_raw ; struct xt_table *arptable_filter ; struct xt_table *iptable_security ; struct xt_table *nat_table ; int sysctl_icmp_echo_ignore_all ; int sysctl_icmp_echo_ignore_broadcasts ; int sysctl_icmp_ignore_bogus_error_responses ; int sysctl_icmp_ratelimit ; int sysctl_icmp_ratemask ; int sysctl_icmp_errors_use_inbound_ifaddr ; struct local_ports ip_local_ports ; int sysctl_tcp_ecn ; int sysctl_tcp_ecn_fallback ; int sysctl_ip_no_pmtu_disc ; int sysctl_ip_fwd_use_pmtu ; int sysctl_ip_nonlocal_bind ; int sysctl_fwmark_reflect ; int sysctl_tcp_fwmark_accept ; int sysctl_tcp_mtu_probing ; int sysctl_tcp_base_mss ; int sysctl_tcp_probe_threshold ; u32 sysctl_tcp_probe_interval ; struct ping_group_range ping_group_range ; atomic_t dev_addr_genid ; unsigned long *sysctl_local_reserved_ports ; struct list_head mr_tables ; struct fib_rules_ops *mr_rules_ops ; atomic_t rt_genid ; }; struct neighbour; struct dst_ops { unsigned short family ; unsigned int gc_thresh ; int (*gc)(struct dst_ops * ) ; struct dst_entry *(*check)(struct dst_entry * , __u32 ) ; unsigned int (*default_advmss)(struct dst_entry const * ) ; unsigned int (*mtu)(struct dst_entry const * ) ; u32 *(*cow_metrics)(struct dst_entry * , unsigned long ) ; void (*destroy)(struct dst_entry * ) ; void (*ifdown)(struct dst_entry * , struct net_device * , int ) ; struct dst_entry *(*negative_advice)(struct dst_entry * ) ; void (*link_failure)(struct sk_buff * ) ; void (*update_pmtu)(struct dst_entry * , struct sock * , struct sk_buff * , u32 ) ; void (*redirect)(struct dst_entry * , struct sock * , struct sk_buff * ) ; int (*local_out)(struct sk_buff * ) ; struct neighbour *(*neigh_lookup)(struct dst_entry const * , struct sk_buff * , void const * ) ; struct kmem_cache *kmem_cachep ; struct percpu_counter pcpuc_entries ; }; struct netns_sysctl_ipv6 { struct ctl_table_header *hdr ; struct ctl_table_header *route_hdr ; struct ctl_table_header *icmp_hdr ; struct ctl_table_header *frags_hdr ; struct ctl_table_header *xfrm6_hdr ; int bindv6only ; int flush_delay ; int ip6_rt_max_size ; int ip6_rt_gc_min_interval ; int ip6_rt_gc_timeout ; int ip6_rt_gc_interval ; int ip6_rt_gc_elasticity ; int ip6_rt_mtu_expires ; int ip6_rt_min_advmss ; int flowlabel_consistency ; int auto_flowlabels ; int icmpv6_time ; int anycast_src_echo_reply ; int fwmark_reflect ; int idgen_retries ; int idgen_delay ; int flowlabel_state_ranges ; }; struct ipv6_devconf; struct rt6_info; struct rt6_statistics; struct fib6_table; struct netns_ipv6 { struct netns_sysctl_ipv6 sysctl ; struct ipv6_devconf *devconf_all ; struct ipv6_devconf *devconf_dflt ; struct inet_peer_base *peers ; struct netns_frags frags ; struct xt_table *ip6table_filter ; struct xt_table *ip6table_mangle ; struct xt_table *ip6table_raw ; struct xt_table *ip6table_security ; struct xt_table *ip6table_nat ; struct rt6_info *ip6_null_entry ; struct rt6_statistics *rt6_stats ; struct timer_list ip6_fib_timer ; struct hlist_head *fib_table_hash ; struct fib6_table *fib6_main_tbl ; struct dst_ops ip6_dst_ops ; unsigned int ip6_rt_gc_expire ; unsigned long ip6_rt_last_gc ; struct rt6_info *ip6_prohibit_entry ; struct rt6_info *ip6_blk_hole_entry ; struct fib6_table *fib6_local_tbl ; struct fib_rules_ops *fib6_rules_ops ; struct sock **icmp_sk ; struct sock *ndisc_sk ; struct sock *tcp_sk ; struct sock *igmp_sk ; struct sock *mc_autojoin_sk ; struct list_head mr6_tables ; struct fib_rules_ops *mr6_rules_ops ; atomic_t dev_addr_genid ; atomic_t fib6_sernum ; }; struct netns_nf_frag { struct netns_sysctl_ipv6 sysctl ; struct netns_frags frags ; }; struct netns_sysctl_lowpan { struct ctl_table_header *frags_hdr ; }; struct netns_ieee802154_lowpan { struct netns_sysctl_lowpan sysctl ; struct netns_frags frags ; }; struct sctp_mib; struct netns_sctp { struct sctp_mib *sctp_statistics ; struct proc_dir_entry *proc_net_sctp ; struct ctl_table_header *sysctl_header ; struct sock *ctl_sock ; struct list_head local_addr_list ; struct list_head addr_waitq ; struct timer_list addr_wq_timer ; struct list_head auto_asconf_splist ; spinlock_t addr_wq_lock ; spinlock_t local_addr_lock ; unsigned int rto_initial ; unsigned int rto_min ; unsigned int rto_max ; int rto_alpha ; int rto_beta ; int max_burst ; int cookie_preserve_enable ; char *sctp_hmac_alg ; unsigned int valid_cookie_life ; unsigned int sack_timeout ; unsigned int hb_interval ; int max_retrans_association ; int max_retrans_path ; int max_retrans_init ; int pf_retrans ; int sndbuf_policy ; int rcvbuf_policy ; int default_auto_asconf ; int addip_enable ; int addip_noauth ; int prsctp_enable ; int auth_enable ; int scope_policy ; int rwnd_upd_shift ; unsigned long max_autoclose ; }; struct netns_dccp { struct sock *v4_ctl_sk ; struct sock *v6_ctl_sk ; }; struct nf_logger; struct netns_nf { struct proc_dir_entry *proc_netfilter ; struct nf_logger const *nf_loggers[13U] ; struct ctl_table_header *nf_log_dir_header ; }; struct ebt_table; struct netns_xt { struct list_head tables[13U] ; bool notrack_deprecated_warning ; bool clusterip_deprecated_warning ; struct ebt_table *broute_table ; struct ebt_table *frame_filter ; struct ebt_table *frame_nat ; }; struct hlist_nulls_node; struct hlist_nulls_head { struct hlist_nulls_node *first ; }; struct hlist_nulls_node { struct hlist_nulls_node *next ; struct hlist_nulls_node **pprev ; }; struct nf_proto_net { struct ctl_table_header *ctl_table_header ; struct ctl_table *ctl_table ; struct ctl_table_header *ctl_compat_header ; struct ctl_table *ctl_compat_table ; unsigned int users ; }; struct nf_generic_net { struct nf_proto_net pn ; unsigned int timeout ; }; struct nf_tcp_net { struct nf_proto_net pn ; unsigned int timeouts[14U] ; unsigned int tcp_loose ; unsigned int tcp_be_liberal ; unsigned int tcp_max_retrans ; }; struct nf_udp_net { struct nf_proto_net pn ; unsigned int timeouts[2U] ; }; struct nf_icmp_net { struct nf_proto_net pn ; unsigned int timeout ; }; struct nf_ip_net { struct nf_generic_net generic ; struct nf_tcp_net tcp ; struct nf_udp_net udp ; struct nf_icmp_net icmp ; struct nf_icmp_net icmpv6 ; struct ctl_table_header *ctl_table_header ; struct ctl_table *ctl_table ; }; struct ct_pcpu { spinlock_t lock ; struct hlist_nulls_head unconfirmed ; struct hlist_nulls_head dying ; struct hlist_nulls_head tmpl ; }; struct ip_conntrack_stat; struct nf_ct_event_notifier; struct nf_exp_event_notifier; struct netns_ct { atomic_t count ; unsigned int expect_count ; struct delayed_work ecache_dwork ; bool ecache_dwork_pending ; struct ctl_table_header *sysctl_header ; struct ctl_table_header *acct_sysctl_header ; struct ctl_table_header *tstamp_sysctl_header ; struct ctl_table_header *event_sysctl_header ; struct ctl_table_header *helper_sysctl_header ; char *slabname ; unsigned int sysctl_log_invalid ; int sysctl_events ; int sysctl_acct ; int sysctl_auto_assign_helper ; bool auto_assign_helper_warned ; int sysctl_tstamp ; int sysctl_checksum ; unsigned int htable_size ; seqcount_t generation ; struct kmem_cache *nf_conntrack_cachep ; struct hlist_nulls_head *hash ; struct hlist_head *expect_hash ; struct ct_pcpu *pcpu_lists ; struct ip_conntrack_stat *stat ; struct nf_ct_event_notifier *nf_conntrack_event_cb ; struct nf_exp_event_notifier *nf_expect_event_cb ; struct nf_ip_net nf_ct_proto ; unsigned int labels_used ; u8 label_words ; struct hlist_head *nat_bysource ; unsigned int nat_htable_size ; }; struct nft_af_info; struct netns_nftables { struct list_head af_info ; struct list_head commit_list ; struct nft_af_info *ipv4 ; struct nft_af_info *ipv6 ; struct nft_af_info *inet ; struct nft_af_info *arp ; struct nft_af_info *bridge ; struct nft_af_info *netdev ; unsigned int base_seq ; u8 gencursor ; }; struct irq_data; struct msi_msg; enum irqchip_irq_state; enum irqchip_irq_state; struct msi_desc; struct irq_domain; struct irq_common_data { unsigned int state_use_accessors ; }; struct irq_chip; struct irq_data { u32 mask ; unsigned int irq ; unsigned long hwirq ; unsigned int node ; struct irq_common_data *common ; struct irq_chip *chip ; struct irq_domain *domain ; struct irq_data *parent_data ; void *handler_data ; void *chip_data ; struct msi_desc *msi_desc ; cpumask_var_t affinity ; }; struct irq_chip { char const *name ; unsigned int (*irq_startup)(struct irq_data * ) ; void (*irq_shutdown)(struct irq_data * ) ; void (*irq_enable)(struct irq_data * ) ; void (*irq_disable)(struct irq_data * ) ; void (*irq_ack)(struct irq_data * ) ; void (*irq_mask)(struct irq_data * ) ; void (*irq_mask_ack)(struct irq_data * ) ; void (*irq_unmask)(struct irq_data * ) ; void (*irq_eoi)(struct irq_data * ) ; int (*irq_set_affinity)(struct irq_data * , struct cpumask const * , bool ) ; int (*irq_retrigger)(struct irq_data * ) ; int (*irq_set_type)(struct irq_data * , unsigned int ) ; int (*irq_set_wake)(struct irq_data * , unsigned int ) ; void (*irq_bus_lock)(struct irq_data * ) ; void (*irq_bus_sync_unlock)(struct irq_data * ) ; void (*irq_cpu_online)(struct irq_data * ) ; void (*irq_cpu_offline)(struct irq_data * ) ; void (*irq_suspend)(struct irq_data * ) ; void (*irq_resume)(struct irq_data * ) ; void (*irq_pm_shutdown)(struct irq_data * ) ; void (*irq_calc_mask)(struct irq_data * ) ; void (*irq_print_chip)(struct irq_data * , struct seq_file * ) ; int (*irq_request_resources)(struct irq_data * ) ; void (*irq_release_resources)(struct irq_data * ) ; void (*irq_compose_msi_msg)(struct irq_data * , struct msi_msg * ) ; void (*irq_write_msi_msg)(struct irq_data * , struct msi_msg * ) ; int (*irq_get_irqchip_state)(struct irq_data * , int , bool * ) ; int (*irq_set_irqchip_state)(struct irq_data * , int , bool ) ; int (*irq_set_vcpu_affinity)(struct irq_data * , void * ) ; unsigned long flags ; }; struct irq_affinity_notify; struct irqaction; struct irq_desc { struct irq_common_data irq_common_data ; struct irq_data irq_data ; unsigned int *kstat_irqs ; void (*handle_irq)(unsigned int , struct irq_desc * ) ; struct irqaction *action ; unsigned int status_use_accessors ; unsigned int core_internal_state__do_not_mess_with_it ; unsigned int depth ; unsigned int wake_depth ; unsigned int irq_count ; unsigned long last_unhandled ; unsigned int irqs_unhandled ; atomic_t threads_handled ; int threads_handled_last ; raw_spinlock_t lock ; struct cpumask *percpu_enabled ; struct cpumask const *affinity_hint ; struct irq_affinity_notify *affinity_notify ; cpumask_var_t pending_mask ; unsigned long threads_oneshot ; atomic_t threads_active ; wait_queue_head_t wait_for_threads ; unsigned int nr_actions ; unsigned int no_suspend_depth ; unsigned int cond_suspend_depth ; unsigned int force_resume_depth ; struct proc_dir_entry *dir ; int parent_irq ; struct module *owner ; char const *name ; }; struct irq_chip_regs { unsigned long enable ; unsigned long disable ; unsigned long mask ; unsigned long ack ; unsigned long eoi ; unsigned long type ; unsigned long polarity ; }; struct irq_chip_type { struct irq_chip chip ; struct irq_chip_regs regs ; void (*handler)(unsigned int , struct irq_desc * ) ; u32 type ; u32 mask_cache_priv ; u32 *mask_cache ; }; struct irq_chip_generic { raw_spinlock_t lock ; void *reg_base ; u32 (*reg_readl)(void * ) ; void (*reg_writel)(u32 , void * ) ; unsigned int irq_base ; unsigned int irq_cnt ; u32 mask_cache ; u32 type_cache ; u32 polarity_cache ; u32 wake_enabled ; u32 wake_active ; unsigned int num_ct ; void *private ; unsigned long installed ; unsigned long unused ; struct irq_domain *domain ; struct list_head list ; struct irq_chip_type chip_types[0U] ; }; enum irq_gc_flags { IRQ_GC_INIT_MASK_CACHE = 1, IRQ_GC_INIT_NESTED_LOCK = 2, IRQ_GC_MASK_CACHE_PER_TYPE = 4, IRQ_GC_NO_MASK = 8, IRQ_GC_BE_IO = 16 } ; struct irq_domain_chip_generic { unsigned int irqs_per_chip ; unsigned int num_chips ; unsigned int irq_flags_to_clear ; unsigned int irq_flags_to_set ; enum irq_gc_flags gc_flags ; struct irq_chip_generic *gc[0U] ; }; struct irqaction { irqreturn_t (*handler)(int , void * ) ; void *dev_id ; void *percpu_dev_id ; struct irqaction *next ; irqreturn_t (*thread_fn)(int , void * ) ; struct task_struct *thread ; unsigned int irq ; unsigned int flags ; unsigned long thread_flags ; unsigned long thread_mask ; char const *name ; struct proc_dir_entry *dir ; }; struct irq_affinity_notify { unsigned int irq ; struct kref kref ; struct work_struct work ; void (*notify)(struct irq_affinity_notify * , cpumask_t const * ) ; void (*release)(struct kref * ) ; }; struct tasklet_struct { struct tasklet_struct *next ; unsigned long state ; atomic_t count ; void (*func)(unsigned long ) ; unsigned long data ; }; struct flow_cache_percpu { struct hlist_head *hash_table ; int hash_count ; u32 hash_rnd ; int hash_rnd_recalc ; struct tasklet_struct flush_tasklet ; }; struct flow_cache { u32 hash_shift ; struct flow_cache_percpu *percpu ; struct notifier_block hotcpu_notifier ; int low_watermark ; int high_watermark ; struct timer_list rnd_timer ; }; struct xfrm_policy_hash { struct hlist_head *table ; unsigned int hmask ; u8 dbits4 ; u8 sbits4 ; u8 dbits6 ; u8 sbits6 ; }; struct xfrm_policy_hthresh { struct work_struct work ; seqlock_t lock ; u8 lbits4 ; u8 rbits4 ; u8 lbits6 ; u8 rbits6 ; }; struct netns_xfrm { struct list_head state_all ; struct hlist_head *state_bydst ; struct hlist_head *state_bysrc ; struct hlist_head *state_byspi ; unsigned int state_hmask ; unsigned int state_num ; struct work_struct state_hash_work ; struct hlist_head state_gc_list ; struct work_struct state_gc_work ; struct list_head policy_all ; struct hlist_head *policy_byidx ; unsigned int policy_idx_hmask ; struct hlist_head policy_inexact[3U] ; struct xfrm_policy_hash policy_bydst[3U] ; unsigned int policy_count[6U] ; struct work_struct policy_hash_work ; struct xfrm_policy_hthresh policy_hthresh ; struct sock *nlsk ; struct sock *nlsk_stash ; u32 sysctl_aevent_etime ; u32 sysctl_aevent_rseqth ; int sysctl_larval_drop ; u32 sysctl_acq_expires ; struct ctl_table_header *sysctl_hdr ; struct dst_ops xfrm4_dst_ops ; struct dst_ops xfrm6_dst_ops ; spinlock_t xfrm_state_lock ; rwlock_t xfrm_policy_lock ; struct mutex xfrm_cfg_mutex ; struct flow_cache flow_cache_global ; atomic_t flow_cache_genid ; struct list_head flow_cache_gc_list ; spinlock_t flow_cache_gc_lock ; struct work_struct flow_cache_gc_work ; struct work_struct flow_cache_flush_work ; struct mutex flow_flush_sem ; }; struct mpls_route; struct netns_mpls { size_t platform_labels ; struct mpls_route **platform_label ; struct ctl_table_header *ctl ; }; struct proc_ns_operations; struct ns_common { atomic_long_t stashed ; struct proc_ns_operations const *ops ; unsigned int inum ; }; struct net_generic; struct netns_ipvs; struct net { atomic_t passive ; atomic_t count ; spinlock_t rules_mod_lock ; atomic64_t cookie_gen ; struct list_head list ; struct list_head cleanup_list ; struct list_head exit_list ; struct user_namespace *user_ns ; spinlock_t nsid_lock ; struct idr netns_ids ; struct ns_common ns ; struct proc_dir_entry *proc_net ; struct proc_dir_entry *proc_net_stat ; struct ctl_table_set sysctls ; struct sock *rtnl ; struct sock *genl_sock ; struct list_head dev_base_head ; struct hlist_head *dev_name_head ; struct hlist_head *dev_index_head ; unsigned int dev_base_seq ; int ifindex ; unsigned int dev_unreg_count ; struct list_head rules_ops ; struct net_device *loopback_dev ; struct netns_core core ; struct netns_mib mib ; struct netns_packet packet ; struct netns_unix unx ; struct netns_ipv4 ipv4 ; struct netns_ipv6 ipv6 ; struct netns_ieee802154_lowpan ieee802154_lowpan ; struct netns_sctp sctp ; struct netns_dccp dccp ; struct netns_nf nf ; struct netns_xt xt ; struct netns_ct ct ; struct netns_nftables nft ; struct netns_nf_frag nf_frag ; struct sock *nfnl ; struct sock *nfnl_stash ; struct sk_buff_head wext_nlevents ; struct net_generic *gen ; struct netns_xfrm xfrm ; struct netns_ipvs *ipvs ; struct netns_mpls mpls ; struct sock *diag_nlsk ; atomic_t fnhe_genid ; }; struct __anonstruct_possible_net_t_302 { struct net *net ; }; typedef struct __anonstruct_possible_net_t_302 possible_net_t; typedef unsigned long kernel_ulong_t; struct pci_device_id { __u32 vendor ; __u32 device ; __u32 subvendor ; __u32 subdevice ; __u32 class ; __u32 class_mask ; kernel_ulong_t driver_data ; }; struct acpi_device_id { __u8 id[9U] ; kernel_ulong_t driver_data ; }; struct of_device_id { char name[32U] ; char type[32U] ; char compatible[128U] ; void const *data ; }; struct bcma_device_id { __u16 manuf ; __u16 id ; __u8 rev ; __u8 class ; }; struct platform_device_id { char name[20U] ; kernel_ulong_t driver_data ; }; enum fwnode_type { FWNODE_INVALID = 0, FWNODE_OF = 1, FWNODE_ACPI = 2, FWNODE_PDATA = 3 } ; struct fwnode_handle { enum fwnode_type type ; struct fwnode_handle *secondary ; }; typedef u32 phandle; struct property { char *name ; int length ; void *value ; struct property *next ; unsigned long _flags ; unsigned int unique_id ; struct bin_attribute attr ; }; struct device_node { char const *name ; char const *type ; phandle phandle ; char const *full_name ; struct fwnode_handle fwnode ; struct property *properties ; struct property *deadprops ; struct device_node *parent ; struct device_node *child ; struct device_node *sibling ; struct kobject kobj ; unsigned long _flags ; void *data ; }; struct of_phandle_args { struct device_node *np ; int args_count ; uint32_t args[16U] ; }; enum ldv_27762 { PHY_INTERFACE_MODE_NA = 0, PHY_INTERFACE_MODE_MII = 1, PHY_INTERFACE_MODE_GMII = 2, PHY_INTERFACE_MODE_SGMII = 3, PHY_INTERFACE_MODE_TBI = 4, PHY_INTERFACE_MODE_REVMII = 5, PHY_INTERFACE_MODE_RMII = 6, PHY_INTERFACE_MODE_RGMII = 7, PHY_INTERFACE_MODE_RGMII_ID = 8, PHY_INTERFACE_MODE_RGMII_RXID = 9, PHY_INTERFACE_MODE_RGMII_TXID = 10, PHY_INTERFACE_MODE_RTBI = 11, PHY_INTERFACE_MODE_SMII = 12, PHY_INTERFACE_MODE_XGMII = 13, PHY_INTERFACE_MODE_MOCA = 14, PHY_INTERFACE_MODE_QSGMII = 15, PHY_INTERFACE_MODE_MAX = 16 } ; typedef enum ldv_27762 phy_interface_t; enum ldv_27816 { MDIOBUS_ALLOCATED = 1, MDIOBUS_REGISTERED = 2, MDIOBUS_UNREGISTERED = 3, MDIOBUS_RELEASED = 4 } ; struct phy_device; struct mii_bus { char const *name ; char id[17U] ; void *priv ; int (*read)(struct mii_bus * , int , int ) ; int (*write)(struct mii_bus * , int , int , u16 ) ; int (*reset)(struct mii_bus * ) ; struct mutex mdio_lock ; struct device *parent ; enum ldv_27816 state ; struct device dev ; struct phy_device *phy_map[32U] ; u32 phy_mask ; u32 phy_ignore_ta_mask ; int *irq ; }; enum phy_state { PHY_DOWN = 0, PHY_STARTING = 1, PHY_READY = 2, PHY_PENDING = 3, PHY_UP = 4, PHY_AN = 5, PHY_RUNNING = 6, PHY_NOLINK = 7, PHY_FORCING = 8, PHY_CHANGELINK = 9, PHY_HALTED = 10, PHY_RESUMING = 11 } ; struct phy_c45_device_ids { u32 devices_in_package ; u32 device_ids[8U] ; }; struct phy_driver; struct phy_device { struct phy_driver *drv ; struct mii_bus *bus ; struct device dev ; u32 phy_id ; struct phy_c45_device_ids c45_ids ; bool is_c45 ; bool is_internal ; bool has_fixups ; bool suspended ; enum phy_state state ; u32 dev_flags ; phy_interface_t interface ; int addr ; int speed ; int duplex ; int pause ; int asym_pause ; int link ; u32 interrupts ; u32 supported ; u32 advertising ; u32 lp_advertising ; int autoneg ; int link_timeout ; int irq ; void *priv ; struct work_struct phy_queue ; struct delayed_work state_queue ; atomic_t irq_disable ; struct mutex lock ; struct net_device *attached_dev ; void (*adjust_link)(struct net_device * ) ; }; struct phy_driver { u32 phy_id ; char *name ; unsigned int phy_id_mask ; u32 features ; u32 flags ; void const *driver_data ; int (*soft_reset)(struct phy_device * ) ; int (*config_init)(struct phy_device * ) ; int (*probe)(struct phy_device * ) ; int (*suspend)(struct phy_device * ) ; int (*resume)(struct phy_device * ) ; int (*config_aneg)(struct phy_device * ) ; int (*aneg_done)(struct phy_device * ) ; int (*read_status)(struct phy_device * ) ; int (*ack_interrupt)(struct phy_device * ) ; int (*config_intr)(struct phy_device * ) ; int (*did_interrupt)(struct phy_device * ) ; void (*remove)(struct phy_device * ) ; int (*match_phy_device)(struct phy_device * ) ; int (*ts_info)(struct phy_device * , struct ethtool_ts_info * ) ; int (*hwtstamp)(struct phy_device * , struct ifreq * ) ; bool (*rxtstamp)(struct phy_device * , struct sk_buff * , int ) ; void (*txtstamp)(struct phy_device * , struct sk_buff * , int ) ; int (*set_wol)(struct phy_device * , struct ethtool_wolinfo * ) ; void (*get_wol)(struct phy_device * , struct ethtool_wolinfo * ) ; void (*link_change_notify)(struct phy_device * ) ; int (*read_mmd_indirect)(struct phy_device * , int , int , int ) ; void (*write_mmd_indirect)(struct phy_device * , int , int , int , u32 ) ; int (*module_info)(struct phy_device * , struct ethtool_modinfo * ) ; int (*module_eeprom)(struct phy_device * , struct ethtool_eeprom * , u8 * ) ; struct device_driver driver ; }; struct fixed_phy_status { int link ; int speed ; int duplex ; int pause ; int asym_pause ; }; enum dsa_tag_protocol { DSA_TAG_PROTO_NONE = 0, DSA_TAG_PROTO_DSA = 1, DSA_TAG_PROTO_TRAILER = 2, DSA_TAG_PROTO_EDSA = 3, DSA_TAG_PROTO_BRCM = 4 } ; struct dsa_chip_data { struct device *host_dev ; int sw_addr ; int eeprom_len ; struct device_node *of_node ; char *port_names[12U] ; struct device_node *port_dn[12U] ; s8 *rtable ; }; struct dsa_platform_data { struct device *netdev ; struct net_device *of_netdev ; int nr_chips ; struct dsa_chip_data *chip ; }; struct packet_type; struct dsa_switch; struct dsa_switch_tree { struct dsa_platform_data *pd ; struct net_device *master_netdev ; int (*rcv)(struct sk_buff * , struct net_device * , struct packet_type * , struct net_device * ) ; enum dsa_tag_protocol tag_protocol ; s8 cpu_switch ; s8 cpu_port ; int link_poll_needed ; struct work_struct link_poll_work ; struct timer_list link_poll_timer ; struct dsa_switch *ds[4U] ; }; struct dsa_switch_driver; struct dsa_switch { struct dsa_switch_tree *dst ; int index ; enum dsa_tag_protocol tag_protocol ; struct dsa_chip_data *pd ; struct dsa_switch_driver *drv ; struct device *master_dev ; char hwmon_name[24U] ; struct device *hwmon_dev ; u32 dsa_port_mask ; u32 phys_port_mask ; u32 phys_mii_mask ; struct mii_bus *slave_mii_bus ; struct net_device *ports[12U] ; }; struct dsa_switch_driver { struct list_head list ; enum dsa_tag_protocol tag_protocol ; int priv_size ; char *(*probe)(struct device * , int ) ; int (*setup)(struct dsa_switch * ) ; int (*set_addr)(struct dsa_switch * , u8 * ) ; u32 (*get_phy_flags)(struct dsa_switch * , int ) ; int (*phy_read)(struct dsa_switch * , int , int ) ; int (*phy_write)(struct dsa_switch * , int , int , u16 ) ; void (*poll_link)(struct dsa_switch * ) ; void (*adjust_link)(struct dsa_switch * , int , struct phy_device * ) ; void (*fixed_link_update)(struct dsa_switch * , int , struct fixed_phy_status * ) ; void (*get_strings)(struct dsa_switch * , int , uint8_t * ) ; void (*get_ethtool_stats)(struct dsa_switch * , int , uint64_t * ) ; int (*get_sset_count)(struct dsa_switch * ) ; void (*get_wol)(struct dsa_switch * , int , struct ethtool_wolinfo * ) ; int (*set_wol)(struct dsa_switch * , int , struct ethtool_wolinfo * ) ; int (*suspend)(struct dsa_switch * ) ; int (*resume)(struct dsa_switch * ) ; int (*port_enable)(struct dsa_switch * , int , struct phy_device * ) ; void (*port_disable)(struct dsa_switch * , int , struct phy_device * ) ; int (*set_eee)(struct dsa_switch * , int , struct phy_device * , struct ethtool_eee * ) ; int (*get_eee)(struct dsa_switch * , int , struct ethtool_eee * ) ; int (*get_temp)(struct dsa_switch * , int * ) ; int (*get_temp_limit)(struct dsa_switch * , int * ) ; int (*set_temp_limit)(struct dsa_switch * , int ) ; int (*get_temp_alarm)(struct dsa_switch * , bool * ) ; int (*get_eeprom_len)(struct dsa_switch * ) ; int (*get_eeprom)(struct dsa_switch * , struct ethtool_eeprom * , u8 * ) ; int (*set_eeprom)(struct dsa_switch * , struct ethtool_eeprom * , u8 * ) ; int (*get_regs_len)(struct dsa_switch * , int ) ; void (*get_regs)(struct dsa_switch * , int , struct ethtool_regs * , void * ) ; int (*port_join_bridge)(struct dsa_switch * , int , u32 ) ; int (*port_leave_bridge)(struct dsa_switch * , int , u32 ) ; int (*port_stp_update)(struct dsa_switch * , int , u8 ) ; int (*fdb_add)(struct dsa_switch * , int , unsigned char const * , u16 ) ; int (*fdb_del)(struct dsa_switch * , int , unsigned char const * , u16 ) ; int (*fdb_getnext)(struct dsa_switch * , int , unsigned char * , bool * ) ; }; struct ieee_ets { __u8 willing ; __u8 ets_cap ; __u8 cbs ; __u8 tc_tx_bw[8U] ; __u8 tc_rx_bw[8U] ; __u8 tc_tsa[8U] ; __u8 prio_tc[8U] ; __u8 tc_reco_bw[8U] ; __u8 tc_reco_tsa[8U] ; __u8 reco_prio_tc[8U] ; }; struct ieee_maxrate { __u64 tc_maxrate[8U] ; }; struct ieee_qcn { __u8 rpg_enable[8U] ; __u32 rppp_max_rps[8U] ; __u32 rpg_time_reset[8U] ; __u32 rpg_byte_reset[8U] ; __u32 rpg_threshold[8U] ; __u32 rpg_max_rate[8U] ; __u32 rpg_ai_rate[8U] ; __u32 rpg_hai_rate[8U] ; __u32 rpg_gd[8U] ; __u32 rpg_min_dec_fac[8U] ; __u32 rpg_min_rate[8U] ; __u32 cndd_state_machine[8U] ; }; struct ieee_qcn_stats { __u64 rppp_rp_centiseconds[8U] ; __u32 rppp_created_rps[8U] ; }; struct ieee_pfc { __u8 pfc_cap ; __u8 pfc_en ; __u8 mbc ; __u16 delay ; __u64 requests[8U] ; __u64 indications[8U] ; }; struct cee_pg { __u8 willing ; __u8 error ; __u8 pg_en ; __u8 tcs_supported ; __u8 pg_bw[8U] ; __u8 prio_pg[8U] ; }; struct cee_pfc { __u8 willing ; __u8 error ; __u8 pfc_en ; __u8 tcs_supported ; }; struct dcb_app { __u8 selector ; __u8 priority ; __u16 protocol ; }; struct dcb_peer_app_info { __u8 willing ; __u8 error ; }; struct dcbnl_rtnl_ops { int (*ieee_getets)(struct net_device * , struct ieee_ets * ) ; int (*ieee_setets)(struct net_device * , struct ieee_ets * ) ; int (*ieee_getmaxrate)(struct net_device * , struct ieee_maxrate * ) ; int (*ieee_setmaxrate)(struct net_device * , struct ieee_maxrate * ) ; int (*ieee_getqcn)(struct net_device * , struct ieee_qcn * ) ; int (*ieee_setqcn)(struct net_device * , struct ieee_qcn * ) ; int (*ieee_getqcnstats)(struct net_device * , struct ieee_qcn_stats * ) ; int (*ieee_getpfc)(struct net_device * , struct ieee_pfc * ) ; int (*ieee_setpfc)(struct net_device * , struct ieee_pfc * ) ; int (*ieee_getapp)(struct net_device * , struct dcb_app * ) ; int (*ieee_setapp)(struct net_device * , struct dcb_app * ) ; int (*ieee_delapp)(struct net_device * , struct dcb_app * ) ; int (*ieee_peer_getets)(struct net_device * , struct ieee_ets * ) ; int (*ieee_peer_getpfc)(struct net_device * , struct ieee_pfc * ) ; u8 (*getstate)(struct net_device * ) ; u8 (*setstate)(struct net_device * , u8 ) ; void (*getpermhwaddr)(struct net_device * , u8 * ) ; void (*setpgtccfgtx)(struct net_device * , int , u8 , u8 , u8 , u8 ) ; void (*setpgbwgcfgtx)(struct net_device * , int , u8 ) ; void (*setpgtccfgrx)(struct net_device * , int , u8 , u8 , u8 , u8 ) ; void (*setpgbwgcfgrx)(struct net_device * , int , u8 ) ; void (*getpgtccfgtx)(struct net_device * , int , u8 * , u8 * , u8 * , u8 * ) ; void (*getpgbwgcfgtx)(struct net_device * , int , u8 * ) ; void (*getpgtccfgrx)(struct net_device * , int , u8 * , u8 * , u8 * , u8 * ) ; void (*getpgbwgcfgrx)(struct net_device * , int , u8 * ) ; void (*setpfccfg)(struct net_device * , int , u8 ) ; void (*getpfccfg)(struct net_device * , int , u8 * ) ; u8 (*setall)(struct net_device * ) ; u8 (*getcap)(struct net_device * , int , u8 * ) ; int (*getnumtcs)(struct net_device * , int , u8 * ) ; int (*setnumtcs)(struct net_device * , int , u8 ) ; u8 (*getpfcstate)(struct net_device * ) ; void (*setpfcstate)(struct net_device * , u8 ) ; void (*getbcncfg)(struct net_device * , int , u32 * ) ; void (*setbcncfg)(struct net_device * , int , u32 ) ; void (*getbcnrp)(struct net_device * , int , u8 * ) ; void (*setbcnrp)(struct net_device * , int , u8 ) ; int (*setapp)(struct net_device * , u8 , u16 , u8 ) ; int (*getapp)(struct net_device * , u8 , u16 ) ; u8 (*getfeatcfg)(struct net_device * , int , u8 * ) ; u8 (*setfeatcfg)(struct net_device * , int , u8 ) ; u8 (*getdcbx)(struct net_device * ) ; u8 (*setdcbx)(struct net_device * , u8 ) ; int (*peer_getappinfo)(struct net_device * , struct dcb_peer_app_info * , u16 * ) ; int (*peer_getapptable)(struct net_device * , struct dcb_app * ) ; int (*cee_peer_getpg)(struct net_device * , struct cee_pg * ) ; int (*cee_peer_getpfc)(struct net_device * , struct cee_pfc * ) ; }; struct taskstats { __u16 version ; __u32 ac_exitcode ; __u8 ac_flag ; __u8 ac_nice ; __u64 cpu_count ; __u64 cpu_delay_total ; __u64 blkio_count ; __u64 blkio_delay_total ; __u64 swapin_count ; __u64 swapin_delay_total ; __u64 cpu_run_real_total ; __u64 cpu_run_virtual_total ; char ac_comm[32U] ; __u8 ac_sched ; __u8 ac_pad[3U] ; __u32 ac_uid ; __u32 ac_gid ; __u32 ac_pid ; __u32 ac_ppid ; __u32 ac_btime ; __u64 ac_etime ; __u64 ac_utime ; __u64 ac_stime ; __u64 ac_minflt ; __u64 ac_majflt ; __u64 coremem ; __u64 virtmem ; __u64 hiwater_rss ; __u64 hiwater_vm ; __u64 read_char ; __u64 write_char ; __u64 read_syscalls ; __u64 write_syscalls ; __u64 read_bytes ; __u64 write_bytes ; __u64 cancelled_write_bytes ; __u64 nvcsw ; __u64 nivcsw ; __u64 ac_utimescaled ; __u64 ac_stimescaled ; __u64 cpu_scaled_run_real_total ; __u64 freepages_count ; __u64 freepages_delay_total ; }; struct netprio_map { struct callback_head rcu ; u32 priomap_len ; u32 priomap[] ; }; struct mnt_namespace; struct ipc_namespace; struct nsproxy { atomic_t count ; struct uts_namespace *uts_ns ; struct ipc_namespace *ipc_ns ; struct mnt_namespace *mnt_ns ; struct pid_namespace *pid_ns_for_children ; struct net *net_ns ; }; struct nlmsghdr { __u32 nlmsg_len ; __u16 nlmsg_type ; __u16 nlmsg_flags ; __u32 nlmsg_seq ; __u32 nlmsg_pid ; }; struct nlattr { __u16 nla_len ; __u16 nla_type ; }; struct netlink_callback { struct sk_buff *skb ; struct nlmsghdr const *nlh ; int (*dump)(struct sk_buff * , struct netlink_callback * ) ; int (*done)(struct netlink_callback * ) ; void *data ; struct module *module ; u16 family ; u16 min_dump_alloc ; unsigned int prev_seq ; unsigned int seq ; long args[6U] ; }; struct ndmsg { __u8 ndm_family ; __u8 ndm_pad1 ; __u16 ndm_pad2 ; __s32 ndm_ifindex ; __u16 ndm_state ; __u8 ndm_flags ; __u8 ndm_type ; }; struct rtnl_link_stats64 { __u64 rx_packets ; __u64 tx_packets ; __u64 rx_bytes ; __u64 tx_bytes ; __u64 rx_errors ; __u64 tx_errors ; __u64 rx_dropped ; __u64 tx_dropped ; __u64 multicast ; __u64 collisions ; __u64 rx_length_errors ; __u64 rx_over_errors ; __u64 rx_crc_errors ; __u64 rx_frame_errors ; __u64 rx_fifo_errors ; __u64 rx_missed_errors ; __u64 tx_aborted_errors ; __u64 tx_carrier_errors ; __u64 tx_fifo_errors ; __u64 tx_heartbeat_errors ; __u64 tx_window_errors ; __u64 rx_compressed ; __u64 tx_compressed ; }; struct ifla_vf_stats { __u64 rx_packets ; __u64 tx_packets ; __u64 rx_bytes ; __u64 tx_bytes ; __u64 broadcast ; __u64 multicast ; }; struct ifla_vf_info { __u32 vf ; __u8 mac[32U] ; __u32 vlan ; __u32 qos ; __u32 spoofchk ; __u32 linkstate ; __u32 min_tx_rate ; __u32 max_tx_rate ; __u32 rss_query_en ; }; struct netpoll_info; struct wireless_dev; struct wpan_dev; struct mpls_dev; enum netdev_tx { __NETDEV_TX_MIN = (-0x7FFFFFFF-1), NETDEV_TX_OK = 0, NETDEV_TX_BUSY = 16, NETDEV_TX_LOCKED = 32 } ; typedef enum netdev_tx netdev_tx_t; struct net_device_stats { unsigned long rx_packets ; unsigned long tx_packets ; unsigned long rx_bytes ; unsigned long tx_bytes ; unsigned long rx_errors ; unsigned long tx_errors ; unsigned long rx_dropped ; unsigned long tx_dropped ; unsigned long multicast ; unsigned long collisions ; unsigned long rx_length_errors ; unsigned long rx_over_errors ; unsigned long rx_crc_errors ; unsigned long rx_frame_errors ; unsigned long rx_fifo_errors ; unsigned long rx_missed_errors ; unsigned long tx_aborted_errors ; unsigned long tx_carrier_errors ; unsigned long tx_fifo_errors ; unsigned long tx_heartbeat_errors ; unsigned long tx_window_errors ; unsigned long rx_compressed ; unsigned long tx_compressed ; }; struct neigh_parms; struct netdev_hw_addr_list { struct list_head list ; int count ; }; struct hh_cache { u16 hh_len ; u16 __pad ; seqlock_t hh_lock ; unsigned long hh_data[16U] ; }; struct header_ops { int (*create)(struct sk_buff * , struct net_device * , unsigned short , void const * , void const * , unsigned int ) ; int (*parse)(struct sk_buff const * , unsigned char * ) ; int (*cache)(struct neighbour const * , struct hh_cache * , __be16 ) ; void (*cache_update)(struct hh_cache * , struct net_device const * , unsigned char const * ) ; }; struct napi_struct { struct list_head poll_list ; unsigned long state ; int weight ; unsigned int gro_count ; int (*poll)(struct napi_struct * , int ) ; spinlock_t poll_lock ; int poll_owner ; struct net_device *dev ; struct sk_buff *gro_list ; struct sk_buff *skb ; struct hrtimer timer ; struct list_head dev_list ; struct hlist_node napi_hash_node ; unsigned int napi_id ; }; enum rx_handler_result { RX_HANDLER_CONSUMED = 0, RX_HANDLER_ANOTHER = 1, RX_HANDLER_EXACT = 2, RX_HANDLER_PASS = 3 } ; typedef enum rx_handler_result rx_handler_result_t; typedef rx_handler_result_t rx_handler_func_t(struct sk_buff ** ); struct Qdisc; struct netdev_queue { struct net_device *dev ; struct Qdisc *qdisc ; struct Qdisc *qdisc_sleeping ; struct kobject kobj ; int numa_node ; spinlock_t _xmit_lock ; int xmit_lock_owner ; unsigned long trans_start ; unsigned long trans_timeout ; unsigned long state ; struct dql dql ; unsigned long tx_maxrate ; }; struct rps_map { unsigned int len ; struct callback_head rcu ; u16 cpus[0U] ; }; struct rps_dev_flow { u16 cpu ; u16 filter ; unsigned int last_qtail ; }; struct rps_dev_flow_table { unsigned int mask ; struct callback_head rcu ; struct rps_dev_flow flows[0U] ; }; struct netdev_rx_queue { struct rps_map *rps_map ; struct rps_dev_flow_table *rps_flow_table ; struct kobject kobj ; struct net_device *dev ; }; struct xps_map { unsigned int len ; unsigned int alloc_len ; struct callback_head rcu ; u16 queues[0U] ; }; struct xps_dev_maps { struct callback_head rcu ; struct xps_map *cpu_map[0U] ; }; struct netdev_tc_txq { u16 count ; u16 offset ; }; struct netdev_fcoe_hbainfo { char manufacturer[64U] ; char serial_number[64U] ; char hardware_version[64U] ; char driver_version[64U] ; char optionrom_version[64U] ; char firmware_version[64U] ; char model[256U] ; char model_description[256U] ; }; struct netdev_phys_item_id { unsigned char id[32U] ; unsigned char id_len ; }; struct net_device_ops { int (*ndo_init)(struct net_device * ) ; void (*ndo_uninit)(struct net_device * ) ; int (*ndo_open)(struct net_device * ) ; int (*ndo_stop)(struct net_device * ) ; netdev_tx_t (*ndo_start_xmit)(struct sk_buff * , struct net_device * ) ; u16 (*ndo_select_queue)(struct net_device * , struct sk_buff * , void * , u16 (*)(struct net_device * , struct sk_buff * ) ) ; void (*ndo_change_rx_flags)(struct net_device * , int ) ; void (*ndo_set_rx_mode)(struct net_device * ) ; int (*ndo_set_mac_address)(struct net_device * , void * ) ; int (*ndo_validate_addr)(struct net_device * ) ; int (*ndo_do_ioctl)(struct net_device * , struct ifreq * , int ) ; int (*ndo_set_config)(struct net_device * , struct ifmap * ) ; int (*ndo_change_mtu)(struct net_device * , int ) ; int (*ndo_neigh_setup)(struct net_device * , struct neigh_parms * ) ; void (*ndo_tx_timeout)(struct net_device * ) ; struct rtnl_link_stats64 *(*ndo_get_stats64)(struct net_device * , struct rtnl_link_stats64 * ) ; struct net_device_stats *(*ndo_get_stats)(struct net_device * ) ; int (*ndo_vlan_rx_add_vid)(struct net_device * , __be16 , u16 ) ; int (*ndo_vlan_rx_kill_vid)(struct net_device * , __be16 , u16 ) ; void (*ndo_poll_controller)(struct net_device * ) ; int (*ndo_netpoll_setup)(struct net_device * , struct netpoll_info * ) ; void (*ndo_netpoll_cleanup)(struct net_device * ) ; int (*ndo_busy_poll)(struct napi_struct * ) ; int (*ndo_set_vf_mac)(struct net_device * , int , u8 * ) ; int (*ndo_set_vf_vlan)(struct net_device * , int , u16 , u8 ) ; int (*ndo_set_vf_rate)(struct net_device * , int , int , int ) ; int (*ndo_set_vf_spoofchk)(struct net_device * , int , bool ) ; int (*ndo_get_vf_config)(struct net_device * , int , struct ifla_vf_info * ) ; int (*ndo_set_vf_link_state)(struct net_device * , int , int ) ; int (*ndo_get_vf_stats)(struct net_device * , int , struct ifla_vf_stats * ) ; int (*ndo_set_vf_port)(struct net_device * , int , struct nlattr ** ) ; int (*ndo_get_vf_port)(struct net_device * , int , struct sk_buff * ) ; int (*ndo_set_vf_rss_query_en)(struct net_device * , int , bool ) ; int (*ndo_setup_tc)(struct net_device * , u8 ) ; int (*ndo_fcoe_enable)(struct net_device * ) ; int (*ndo_fcoe_disable)(struct net_device * ) ; int (*ndo_fcoe_ddp_setup)(struct net_device * , u16 , struct scatterlist * , unsigned int ) ; int (*ndo_fcoe_ddp_done)(struct net_device * , u16 ) ; int (*ndo_fcoe_ddp_target)(struct net_device * , u16 , struct scatterlist * , unsigned int ) ; int (*ndo_fcoe_get_hbainfo)(struct net_device * , struct netdev_fcoe_hbainfo * ) ; int (*ndo_fcoe_get_wwn)(struct net_device * , u64 * , int ) ; int (*ndo_rx_flow_steer)(struct net_device * , struct sk_buff const * , u16 , u32 ) ; int (*ndo_add_slave)(struct net_device * , struct net_device * ) ; int (*ndo_del_slave)(struct net_device * , struct net_device * ) ; netdev_features_t (*ndo_fix_features)(struct net_device * , netdev_features_t ) ; int (*ndo_set_features)(struct net_device * , netdev_features_t ) ; int (*ndo_neigh_construct)(struct neighbour * ) ; void (*ndo_neigh_destroy)(struct neighbour * ) ; int (*ndo_fdb_add)(struct ndmsg * , struct nlattr ** , struct net_device * , unsigned char const * , u16 , u16 ) ; int (*ndo_fdb_del)(struct ndmsg * , struct nlattr ** , struct net_device * , unsigned char const * , u16 ) ; int (*ndo_fdb_dump)(struct sk_buff * , struct netlink_callback * , struct net_device * , struct net_device * , int ) ; int (*ndo_bridge_setlink)(struct net_device * , struct nlmsghdr * , u16 ) ; int (*ndo_bridge_getlink)(struct sk_buff * , u32 , u32 , struct net_device * , u32 , int ) ; int (*ndo_bridge_dellink)(struct net_device * , struct nlmsghdr * , u16 ) ; int (*ndo_change_carrier)(struct net_device * , bool ) ; int (*ndo_get_phys_port_id)(struct net_device * , struct netdev_phys_item_id * ) ; int (*ndo_get_phys_port_name)(struct net_device * , char * , size_t ) ; void (*ndo_add_vxlan_port)(struct net_device * , sa_family_t , __be16 ) ; void (*ndo_del_vxlan_port)(struct net_device * , sa_family_t , __be16 ) ; void *(*ndo_dfwd_add_station)(struct net_device * , struct net_device * ) ; void (*ndo_dfwd_del_station)(struct net_device * , void * ) ; netdev_tx_t (*ndo_dfwd_start_xmit)(struct sk_buff * , struct net_device * , void * ) ; int (*ndo_get_lock_subclass)(struct net_device * ) ; netdev_features_t (*ndo_features_check)(struct sk_buff * , struct net_device * , netdev_features_t ) ; int (*ndo_set_tx_maxrate)(struct net_device * , int , u32 ) ; int (*ndo_get_iflink)(struct net_device const * ) ; }; struct __anonstruct_adj_list_315 { struct list_head upper ; struct list_head lower ; }; struct __anonstruct_all_adj_list_316 { struct list_head upper ; struct list_head lower ; }; struct iw_handler_def; struct iw_public_data; struct switchdev_ops; struct vlan_info; struct tipc_bearer; struct in_device; struct dn_dev; struct inet6_dev; struct tcf_proto; struct cpu_rmap; struct pcpu_lstats; struct pcpu_sw_netstats; struct pcpu_dstats; struct pcpu_vstats; union __anonunion____missing_field_name_317 { void *ml_priv ; struct pcpu_lstats *lstats ; struct pcpu_sw_netstats *tstats ; struct pcpu_dstats *dstats ; struct pcpu_vstats *vstats ; }; struct garp_port; struct mrp_port; struct rtnl_link_ops; struct net_device { char name[16U] ; struct hlist_node name_hlist ; char *ifalias ; unsigned long mem_end ; unsigned long mem_start ; unsigned long base_addr ; int irq ; atomic_t carrier_changes ; unsigned long state ; struct list_head dev_list ; struct list_head napi_list ; struct list_head unreg_list ; struct list_head close_list ; struct list_head ptype_all ; struct list_head ptype_specific ; struct __anonstruct_adj_list_315 adj_list ; struct __anonstruct_all_adj_list_316 all_adj_list ; netdev_features_t features ; netdev_features_t hw_features ; netdev_features_t wanted_features ; netdev_features_t vlan_features ; netdev_features_t hw_enc_features ; netdev_features_t mpls_features ; int ifindex ; int group ; struct net_device_stats stats ; atomic_long_t rx_dropped ; atomic_long_t tx_dropped ; struct iw_handler_def const *wireless_handlers ; struct iw_public_data *wireless_data ; struct net_device_ops const *netdev_ops ; struct ethtool_ops const *ethtool_ops ; struct switchdev_ops const *switchdev_ops ; struct header_ops const *header_ops ; unsigned int flags ; unsigned int priv_flags ; unsigned short gflags ; unsigned short padded ; unsigned char operstate ; unsigned char link_mode ; unsigned char if_port ; unsigned char dma ; unsigned int mtu ; unsigned short type ; unsigned short hard_header_len ; unsigned short needed_headroom ; unsigned short needed_tailroom ; unsigned char perm_addr[32U] ; unsigned char addr_assign_type ; unsigned char addr_len ; unsigned short neigh_priv_len ; unsigned short dev_id ; unsigned short dev_port ; spinlock_t addr_list_lock ; unsigned char name_assign_type ; bool uc_promisc ; struct netdev_hw_addr_list uc ; struct netdev_hw_addr_list mc ; struct netdev_hw_addr_list dev_addrs ; struct kset *queues_kset ; unsigned int promiscuity ; unsigned int allmulti ; struct vlan_info *vlan_info ; struct dsa_switch_tree *dsa_ptr ; struct tipc_bearer *tipc_ptr ; void *atalk_ptr ; struct in_device *ip_ptr ; struct dn_dev *dn_ptr ; struct inet6_dev *ip6_ptr ; void *ax25_ptr ; struct wireless_dev *ieee80211_ptr ; struct wpan_dev *ieee802154_ptr ; struct mpls_dev *mpls_ptr ; unsigned long last_rx ; unsigned char *dev_addr ; struct netdev_rx_queue *_rx ; unsigned int num_rx_queues ; unsigned int real_num_rx_queues ; unsigned long gro_flush_timeout ; rx_handler_func_t *rx_handler ; void *rx_handler_data ; struct tcf_proto *ingress_cl_list ; struct netdev_queue *ingress_queue ; struct list_head nf_hooks_ingress ; unsigned char broadcast[32U] ; struct cpu_rmap *rx_cpu_rmap ; struct hlist_node index_hlist ; struct netdev_queue *_tx ; unsigned int num_tx_queues ; unsigned int real_num_tx_queues ; struct Qdisc *qdisc ; unsigned long tx_queue_len ; spinlock_t tx_global_lock ; int watchdog_timeo ; struct xps_dev_maps *xps_maps ; unsigned long trans_start ; struct timer_list watchdog_timer ; int *pcpu_refcnt ; struct list_head todo_list ; struct list_head link_watch_list ; unsigned char reg_state ; bool dismantle ; unsigned short rtnl_link_state ; void (*destructor)(struct net_device * ) ; struct netpoll_info *npinfo ; possible_net_t nd_net ; union __anonunion____missing_field_name_317 __annonCompField94 ; struct garp_port *garp_port ; struct mrp_port *mrp_port ; struct device dev ; struct attribute_group const *sysfs_groups[4U] ; struct attribute_group const *sysfs_rx_queue_group ; struct rtnl_link_ops const *rtnl_link_ops ; unsigned int gso_max_size ; u16 gso_max_segs ; u16 gso_min_segs ; struct dcbnl_rtnl_ops const *dcbnl_ops ; u8 num_tc ; struct netdev_tc_txq tc_to_txq[16U] ; u8 prio_tc_map[16U] ; unsigned int fcoe_ddp_xid ; struct netprio_map *priomap ; struct phy_device *phydev ; struct lock_class_key *qdisc_tx_busylock ; }; struct packet_type { __be16 type ; struct net_device *dev ; int (*func)(struct sk_buff * , struct net_device * , struct packet_type * , struct net_device * ) ; bool (*id_match)(struct packet_type * , struct sock * ) ; void *af_packet_priv ; struct list_head list ; }; struct pcpu_sw_netstats { u64 rx_packets ; u64 rx_bytes ; u64 tx_packets ; u64 tx_bytes ; struct u64_stats_sync syncp ; }; struct firmware { size_t size ; u8 const *data ; struct page **pages ; void *priv ; }; struct hotplug_slot; struct pci_slot { struct pci_bus *bus ; struct list_head list ; struct hotplug_slot *hotplug ; unsigned char number ; struct kobject kobj ; }; typedef int pci_power_t; typedef unsigned int pci_channel_state_t; enum pci_channel_state { pci_channel_io_normal = 1, pci_channel_io_frozen = 2, pci_channel_io_perm_failure = 3 } ; typedef unsigned short pci_dev_flags_t; typedef unsigned short pci_bus_flags_t; struct pcie_link_state; struct pci_vpd; struct pci_sriov; struct pci_ats; struct pci_driver; union __anonunion____missing_field_name_326 { struct pci_sriov *sriov ; struct pci_dev *physfn ; }; struct pci_dev { struct list_head bus_list ; struct pci_bus *bus ; struct pci_bus *subordinate ; void *sysdata ; struct proc_dir_entry *procent ; struct pci_slot *slot ; unsigned int devfn ; unsigned short vendor ; unsigned short device ; unsigned short subsystem_vendor ; unsigned short subsystem_device ; unsigned int class ; u8 revision ; u8 hdr_type ; u8 pcie_cap ; u8 msi_cap ; u8 msix_cap ; unsigned char pcie_mpss : 3 ; u8 rom_base_reg ; u8 pin ; u16 pcie_flags_reg ; u8 dma_alias_devfn ; struct pci_driver *driver ; u64 dma_mask ; struct device_dma_parameters dma_parms ; pci_power_t current_state ; u8 pm_cap ; unsigned char pme_support : 5 ; unsigned char pme_interrupt : 1 ; unsigned char pme_poll : 1 ; unsigned char d1_support : 1 ; unsigned char d2_support : 1 ; unsigned char no_d1d2 : 1 ; unsigned char no_d3cold : 1 ; unsigned char d3cold_allowed : 1 ; unsigned char mmio_always_on : 1 ; unsigned char wakeup_prepared : 1 ; unsigned char runtime_d3cold : 1 ; unsigned char ignore_hotplug : 1 ; unsigned int d3_delay ; unsigned int d3cold_delay ; struct pcie_link_state *link_state ; pci_channel_state_t error_state ; struct device dev ; int cfg_size ; unsigned int irq ; struct resource resource[17U] ; bool match_driver ; unsigned char transparent : 1 ; unsigned char multifunction : 1 ; unsigned char is_added : 1 ; unsigned char is_busmaster : 1 ; unsigned char no_msi : 1 ; unsigned char no_64bit_msi : 1 ; unsigned char block_cfg_access : 1 ; unsigned char broken_parity_status : 1 ; unsigned char irq_reroute_variant : 2 ; unsigned char msi_enabled : 1 ; unsigned char msix_enabled : 1 ; unsigned char ari_enabled : 1 ; unsigned char is_managed : 1 ; unsigned char needs_freset : 1 ; unsigned char state_saved : 1 ; unsigned char is_physfn : 1 ; unsigned char is_virtfn : 1 ; unsigned char reset_fn : 1 ; unsigned char is_hotplug_bridge : 1 ; unsigned char __aer_firmware_first_valid : 1 ; unsigned char __aer_firmware_first : 1 ; unsigned char broken_intx_masking : 1 ; unsigned char io_window_1k : 1 ; unsigned char irq_managed : 1 ; unsigned char has_secondary_link : 1 ; pci_dev_flags_t dev_flags ; atomic_t enable_cnt ; u32 saved_config_space[16U] ; struct hlist_head saved_cap_space ; struct bin_attribute *rom_attr ; int rom_attr_enabled ; struct bin_attribute *res_attr[17U] ; struct bin_attribute *res_attr_wc[17U] ; struct list_head msi_list ; struct attribute_group const **msi_irq_groups ; struct pci_vpd *vpd ; union __anonunion____missing_field_name_326 __annonCompField95 ; struct pci_ats *ats ; phys_addr_t rom ; size_t romlen ; char *driver_override ; }; struct pci_ops; struct msi_controller; struct pci_bus { struct list_head node ; struct pci_bus *parent ; struct list_head children ; struct list_head devices ; struct pci_dev *self ; struct list_head slots ; struct resource *resource[4U] ; struct list_head resources ; struct resource busn_res ; struct pci_ops *ops ; struct msi_controller *msi ; void *sysdata ; struct proc_dir_entry *procdir ; unsigned char number ; unsigned char primary ; unsigned char max_bus_speed ; unsigned char cur_bus_speed ; char name[48U] ; unsigned short bridge_ctl ; pci_bus_flags_t bus_flags ; struct device *bridge ; struct device dev ; struct bin_attribute *legacy_io ; struct bin_attribute *legacy_mem ; unsigned char is_added : 1 ; }; struct pci_ops { void *(*map_bus)(struct pci_bus * , unsigned int , int ) ; int (*read)(struct pci_bus * , unsigned int , int , int , u32 * ) ; int (*write)(struct pci_bus * , unsigned int , int , int , u32 ) ; }; struct pci_dynids { spinlock_t lock ; struct list_head list ; }; typedef unsigned int pci_ers_result_t; struct pci_error_handlers { pci_ers_result_t (*error_detected)(struct pci_dev * , enum pci_channel_state ) ; pci_ers_result_t (*mmio_enabled)(struct pci_dev * ) ; pci_ers_result_t (*link_reset)(struct pci_dev * ) ; pci_ers_result_t (*slot_reset)(struct pci_dev * ) ; void (*reset_notify)(struct pci_dev * , bool ) ; void (*resume)(struct pci_dev * ) ; }; struct pci_driver { struct list_head node ; char const *name ; struct pci_device_id const *id_table ; int (*probe)(struct pci_dev * , struct pci_device_id const * ) ; void (*remove)(struct pci_dev * ) ; int (*suspend)(struct pci_dev * , pm_message_t ) ; int (*suspend_late)(struct pci_dev * , pm_message_t ) ; int (*resume_early)(struct pci_dev * ) ; int (*resume)(struct pci_dev * ) ; void (*shutdown)(struct pci_dev * ) ; int (*sriov_configure)(struct pci_dev * , int ) ; struct pci_error_handlers const *err_handler ; struct device_driver driver ; struct pci_dynids dynids ; }; struct mfd_cell; struct platform_device { char const *name ; int id ; bool id_auto ; struct device dev ; u32 num_resources ; struct resource *resource ; struct platform_device_id const *id_entry ; char *driver_override ; struct mfd_cell *mfd_cell ; struct pdev_archdata archdata ; }; struct irq_domain_ops { int (*match)(struct irq_domain * , struct device_node * ) ; int (*map)(struct irq_domain * , unsigned int , irq_hw_number_t ) ; void (*unmap)(struct irq_domain * , unsigned int ) ; int (*xlate)(struct irq_domain * , struct device_node * , u32 const * , unsigned int , unsigned long * , unsigned int * ) ; int (*alloc)(struct irq_domain * , unsigned int , unsigned int , void * ) ; void (*free)(struct irq_domain * , unsigned int , unsigned int ) ; void (*activate)(struct irq_domain * , struct irq_data * ) ; void (*deactivate)(struct irq_domain * , struct irq_data * ) ; }; struct irq_domain { struct list_head link ; char const *name ; struct irq_domain_ops const *ops ; void *host_data ; unsigned int flags ; struct device_node *of_node ; struct irq_domain_chip_generic *gc ; struct irq_domain *parent ; irq_hw_number_t hwirq_max ; unsigned int revmap_direct_max_irq ; unsigned int revmap_size ; struct radix_tree_root revmap_tree ; unsigned int linear_revmap[] ; }; struct gpio_chip; struct gpio_desc; struct gpio_chip { char const *label ; struct device *dev ; struct device *cdev ; struct module *owner ; struct list_head list ; int (*request)(struct gpio_chip * , unsigned int ) ; void (*free)(struct gpio_chip * , unsigned int ) ; int (*get_direction)(struct gpio_chip * , unsigned int ) ; int (*direction_input)(struct gpio_chip * , unsigned int ) ; int (*direction_output)(struct gpio_chip * , unsigned int , int ) ; int (*get)(struct gpio_chip * , unsigned int ) ; void (*set)(struct gpio_chip * , unsigned int , int ) ; void (*set_multiple)(struct gpio_chip * , unsigned long * , unsigned long * ) ; int (*set_debounce)(struct gpio_chip * , unsigned int , unsigned int ) ; int (*to_irq)(struct gpio_chip * , unsigned int ) ; void (*dbg_show)(struct seq_file * , struct gpio_chip * ) ; int base ; u16 ngpio ; struct gpio_desc *desc ; char const * const *names ; bool can_sleep ; bool irq_not_threaded ; struct irq_chip *irqchip ; struct irq_domain *irqdomain ; unsigned int irq_base ; void (*irq_handler)(unsigned int , struct irq_desc * ) ; unsigned int irq_default_type ; int irq_parent ; struct device_node *of_node ; int of_gpio_n_cells ; int (*of_xlate)(struct gpio_chip * , struct of_phandle_args const * , u32 * ) ; struct list_head pin_ranges ; }; struct bcma_chipcommon_pmu { u8 rev ; u32 crystalfreq ; }; struct bcma_drv_cc { struct bcma_device *core ; u32 status ; u32 capabilities ; u32 capabilities_ext ; unsigned char setup_done : 1 ; unsigned char early_setup_done : 1 ; u16 fast_pwrup_delay ; struct bcma_chipcommon_pmu pmu ; u32 ticks_per_ms ; struct platform_device *watchdog ; spinlock_t gpio_lock ; struct gpio_chip gpio ; struct irq_domain *irq_domain ; }; struct bcma_drv_cc_b { struct bcma_device *core ; unsigned char setup_done : 1 ; void *mii ; }; struct bcma_drv_pci; struct bcma_bus; struct bcma_drv_pci { struct bcma_device *core ; unsigned char early_setup_done : 1 ; unsigned char setup_done : 1 ; unsigned char hostmode : 1 ; }; struct bcma_drv_pcie2 { struct bcma_device *core ; u16 reqsize ; }; struct bcma_drv_mips { struct bcma_device *core ; unsigned char setup_done : 1 ; unsigned char early_setup_done : 1 ; }; struct bcma_drv_gmac_cmn { struct bcma_device *core ; struct mutex phy_mutex ; }; struct ssb_sprom_core_pwr_info { u8 itssi_2g ; u8 itssi_5g ; u8 maxpwr_2g ; u8 maxpwr_5gl ; u8 maxpwr_5g ; u8 maxpwr_5gh ; u16 pa_2g[4U] ; u16 pa_5gl[4U] ; u16 pa_5g[4U] ; u16 pa_5gh[4U] ; }; struct __anonstruct_antenna_gain_327 { s8 a0 ; s8 a1 ; s8 a2 ; s8 a3 ; }; struct __anonstruct_ghz2_329 { u8 tssipos ; u8 extpa_gain ; u8 pdet_range ; u8 tr_iso ; u8 antswlut ; }; struct __anonstruct_ghz5_330 { u8 tssipos ; u8 extpa_gain ; u8 pdet_range ; u8 tr_iso ; u8 antswlut ; }; struct __anonstruct_fem_328 { struct __anonstruct_ghz2_329 ghz2 ; struct __anonstruct_ghz5_330 ghz5 ; }; struct ssb_sprom { u8 revision ; u8 il0mac[6U] ; u8 et0mac[6U] ; u8 et1mac[6U] ; u8 et2mac[6U] ; u8 et0phyaddr ; u8 et1phyaddr ; u8 et2phyaddr ; u8 et0mdcport ; u8 et1mdcport ; u8 et2mdcport ; u16 dev_id ; u16 board_rev ; u16 board_num ; u16 board_type ; u8 country_code ; char alpha2[2U] ; u8 leddc_on_time ; u8 leddc_off_time ; u8 ant_available_a ; u8 ant_available_bg ; u16 pa0b0 ; u16 pa0b1 ; u16 pa0b2 ; u16 pa1b0 ; u16 pa1b1 ; u16 pa1b2 ; u16 pa1lob0 ; u16 pa1lob1 ; u16 pa1lob2 ; u16 pa1hib0 ; u16 pa1hib1 ; u16 pa1hib2 ; u8 gpio0 ; u8 gpio1 ; u8 gpio2 ; u8 gpio3 ; u8 maxpwr_bg ; u8 maxpwr_al ; u8 maxpwr_a ; u8 maxpwr_ah ; u8 itssi_a ; u8 itssi_bg ; u8 tri2g ; u8 tri5gl ; u8 tri5g ; u8 tri5gh ; u8 txpid2g[4U] ; u8 txpid5gl[4U] ; u8 txpid5g[4U] ; u8 txpid5gh[4U] ; s8 rxpo2g ; s8 rxpo5g ; u8 rssisav2g ; u8 rssismc2g ; u8 rssismf2g ; u8 bxa2g ; u8 rssisav5g ; u8 rssismc5g ; u8 rssismf5g ; u8 bxa5g ; u16 cck2gpo ; u32 ofdm2gpo ; u32 ofdm5glpo ; u32 ofdm5gpo ; u32 ofdm5ghpo ; u32 boardflags ; u32 boardflags2 ; u32 boardflags3 ; u16 boardflags_lo ; u16 boardflags_hi ; u16 boardflags2_lo ; u16 boardflags2_hi ; struct ssb_sprom_core_pwr_info core_pwr_info[4U] ; struct __anonstruct_antenna_gain_327 antenna_gain ; struct __anonstruct_fem_328 fem ; u16 mcs2gpo[8U] ; u16 mcs5gpo[8U] ; u16 mcs5glpo[8U] ; u16 mcs5ghpo[8U] ; u8 opo ; u8 rxgainerr2ga[3U] ; u8 rxgainerr5gla[3U] ; u8 rxgainerr5gma[3U] ; u8 rxgainerr5gha[3U] ; u8 rxgainerr5gua[3U] ; u8 noiselvl2ga[3U] ; u8 noiselvl5gla[3U] ; u8 noiselvl5gma[3U] ; u8 noiselvl5gha[3U] ; u8 noiselvl5gua[3U] ; u8 regrev ; u8 txchain ; u8 rxchain ; u8 antswitch ; u16 cddpo ; u16 stbcpo ; u16 bw40po ; u16 bwduppo ; u8 tempthresh ; u8 tempoffset ; u16 rawtempsense ; u8 measpower ; u8 tempsense_slope ; u8 tempcorrx ; u8 tempsense_option ; u8 freqoffset_corr ; u8 iqcal_swp_dis ; u8 hw_iqcal_en ; u8 elna2g ; u8 elna5g ; u8 phycal_tempdelta ; u8 temps_period ; u8 temps_hysteresis ; u8 measpower1 ; u8 measpower2 ; u8 pcieingress_war ; u16 cckbw202gpo ; u16 cckbw20ul2gpo ; u32 legofdmbw202gpo ; u32 legofdmbw20ul2gpo ; u32 legofdmbw205glpo ; u32 legofdmbw20ul5glpo ; u32 legofdmbw205gmpo ; u32 legofdmbw20ul5gmpo ; u32 legofdmbw205ghpo ; u32 legofdmbw20ul5ghpo ; u32 mcsbw202gpo ; u32 mcsbw20ul2gpo ; u32 mcsbw402gpo ; u32 mcsbw205glpo ; u32 mcsbw20ul5glpo ; u32 mcsbw405glpo ; u32 mcsbw205gmpo ; u32 mcsbw20ul5gmpo ; u32 mcsbw405gmpo ; u32 mcsbw205ghpo ; u32 mcsbw20ul5ghpo ; u32 mcsbw405ghpo ; u16 mcs32po ; u16 legofdm40duppo ; u8 sar2g ; u8 sar5g ; }; struct sdio_func; enum bcma_hosttype { BCMA_HOSTTYPE_PCI = 0, BCMA_HOSTTYPE_SDIO = 1, BCMA_HOSTTYPE_SOC = 2 } ; struct bcma_chipinfo { u16 id ; u8 rev ; u8 pkg ; }; struct bcma_boardinfo { u16 vendor ; u16 type ; }; struct bcma_host_ops { u8 (*read8)(struct bcma_device * , u16 ) ; u16 (*read16)(struct bcma_device * , u16 ) ; u32 (*read32)(struct bcma_device * , u16 ) ; void (*write8)(struct bcma_device * , u16 , u8 ) ; void (*write16)(struct bcma_device * , u16 , u16 ) ; void (*write32)(struct bcma_device * , u16 , u32 ) ; void (*block_read)(struct bcma_device * , void * , size_t , u16 , u8 ) ; void (*block_write)(struct bcma_device * , void const * , size_t , u16 , u8 ) ; u32 (*aread32)(struct bcma_device * , u16 ) ; void (*awrite32)(struct bcma_device * , u16 , u32 ) ; }; struct bcma_device { struct bcma_bus *bus ; struct bcma_device_id id ; struct device dev ; struct device *dma_dev ; unsigned int irq ; bool dev_registered ; u8 core_index ; u8 core_unit ; u32 addr ; u32 addr_s[8U] ; u32 wrap ; void *io_addr ; void *io_wrap ; void *drvdata ; struct list_head list ; }; struct bcma_driver { char const *name ; struct bcma_device_id const *id_table ; int (*probe)(struct bcma_device * ) ; void (*remove)(struct bcma_device * ) ; int (*suspend)(struct bcma_device * ) ; int (*resume)(struct bcma_device * ) ; void (*shutdown)(struct bcma_device * ) ; struct device_driver drv ; }; union __anonunion____missing_field_name_333 { struct pci_dev *host_pci ; struct sdio_func *host_sdio ; struct platform_device *host_pdev ; }; struct bcma_bus { void *mmio ; struct bcma_host_ops const *ops ; enum bcma_hosttype hosttype ; bool host_is_pcie2 ; union __anonunion____missing_field_name_333 __annonCompField98 ; struct bcma_chipinfo chipinfo ; struct bcma_boardinfo boardinfo ; struct bcma_device *mapped_core ; struct list_head cores ; u8 nr_cores ; u8 num ; struct bcma_drv_cc drv_cc ; struct bcma_drv_cc_b drv_cc_b ; struct bcma_drv_pci drv_pci[2U] ; struct bcma_drv_pcie2 drv_pcie2 ; struct bcma_drv_mips drv_mips ; struct bcma_drv_gmac_cmn drv_gmac_cmn ; struct ssb_sprom sprom ; }; struct ieee80211_p2p_noa_desc { u8 count ; __le32 duration ; __le32 interval ; __le32 start_time ; }; struct ieee80211_p2p_noa_attr { u8 index ; u8 oppps_ctwindow ; struct ieee80211_p2p_noa_desc desc[4U] ; }; struct ieee80211_mcs_info { u8 rx_mask[10U] ; __le16 rx_highest ; u8 tx_params ; u8 reserved[3U] ; }; struct ieee80211_ht_cap { __le16 cap_info ; u8 ampdu_params_info ; struct ieee80211_mcs_info mcs ; __le16 extended_ht_cap_info ; __le32 tx_BF_cap_info ; u8 antenna_selection_info ; }; struct ieee80211_vht_mcs_info { __le16 rx_mcs_map ; __le16 rx_highest ; __le16 tx_mcs_map ; __le16 tx_highest ; }; struct ieee80211_vht_cap { __le32 vht_cap_info ; struct ieee80211_vht_mcs_info supp_mcs ; }; enum nl80211_iftype { NL80211_IFTYPE_UNSPECIFIED = 0, NL80211_IFTYPE_ADHOC = 1, NL80211_IFTYPE_STATION = 2, NL80211_IFTYPE_AP = 3, NL80211_IFTYPE_AP_VLAN = 4, NL80211_IFTYPE_WDS = 5, NL80211_IFTYPE_MONITOR = 6, NL80211_IFTYPE_MESH_POINT = 7, NL80211_IFTYPE_P2P_CLIENT = 8, NL80211_IFTYPE_P2P_GO = 9, NL80211_IFTYPE_P2P_DEVICE = 10, NL80211_IFTYPE_OCB = 11, NUM_NL80211_IFTYPES = 12, NL80211_IFTYPE_MAX = 11 } ; struct nl80211_sta_flag_update { __u32 mask ; __u32 set ; }; enum nl80211_reg_initiator { NL80211_REGDOM_SET_BY_CORE = 0, NL80211_REGDOM_SET_BY_USER = 1, NL80211_REGDOM_SET_BY_DRIVER = 2, NL80211_REGDOM_SET_BY_COUNTRY_IE = 3 } ; enum nl80211_dfs_regions { NL80211_DFS_UNSET = 0, NL80211_DFS_FCC = 1, NL80211_DFS_ETSI = 2, NL80211_DFS_JP = 3 } ; enum nl80211_user_reg_hint_type { NL80211_USER_REG_HINT_USER = 0, NL80211_USER_REG_HINT_CELL_BASE = 1, NL80211_USER_REG_HINT_INDOOR = 2 } ; enum nl80211_mesh_power_mode { NL80211_MESH_POWER_UNKNOWN = 0, NL80211_MESH_POWER_ACTIVE = 1, NL80211_MESH_POWER_LIGHT_SLEEP = 2, NL80211_MESH_POWER_DEEP_SLEEP = 3, __NL80211_MESH_POWER_AFTER_LAST = 4, NL80211_MESH_POWER_MAX = 3 } ; enum nl80211_chan_width { NL80211_CHAN_WIDTH_20_NOHT = 0, NL80211_CHAN_WIDTH_20 = 1, NL80211_CHAN_WIDTH_40 = 2, NL80211_CHAN_WIDTH_80 = 3, NL80211_CHAN_WIDTH_80P80 = 4, NL80211_CHAN_WIDTH_160 = 5, NL80211_CHAN_WIDTH_5 = 6, NL80211_CHAN_WIDTH_10 = 7 } ; enum nl80211_bss_scan_width { NL80211_BSS_CHAN_WIDTH_20 = 0, NL80211_BSS_CHAN_WIDTH_10 = 1, NL80211_BSS_CHAN_WIDTH_5 = 2 } ; enum nl80211_auth_type { NL80211_AUTHTYPE_OPEN_SYSTEM = 0, NL80211_AUTHTYPE_SHARED_KEY = 1, NL80211_AUTHTYPE_FT = 2, NL80211_AUTHTYPE_NETWORK_EAP = 3, NL80211_AUTHTYPE_SAE = 4, __NL80211_AUTHTYPE_NUM = 5, NL80211_AUTHTYPE_MAX = 4, NL80211_AUTHTYPE_AUTOMATIC = 5 } ; enum nl80211_mfp { NL80211_MFP_NO = 0, NL80211_MFP_REQUIRED = 1 } ; enum nl80211_txrate_gi { NL80211_TXRATE_DEFAULT_GI = 0, NL80211_TXRATE_FORCE_SGI = 1, NL80211_TXRATE_FORCE_LGI = 2 } ; enum nl80211_tx_power_setting { NL80211_TX_POWER_AUTOMATIC = 0, NL80211_TX_POWER_LIMITED = 1, NL80211_TX_POWER_FIXED = 2 } ; struct nl80211_wowlan_tcp_data_seq { __u32 start ; __u32 offset ; __u32 len ; }; struct nl80211_wowlan_tcp_data_token { __u32 offset ; __u32 len ; __u8 token_stream[] ; }; struct nl80211_wowlan_tcp_data_token_feature { __u32 min_len ; __u32 max_len ; __u32 bufsize ; }; enum nl80211_dfs_state { NL80211_DFS_USABLE = 0, NL80211_DFS_UNAVAILABLE = 1, NL80211_DFS_AVAILABLE = 2 } ; struct nl80211_vendor_cmd_info { __u32 vendor_id ; __u32 subcmd ; }; enum environment_cap { ENVIRON_ANY = 0, ENVIRON_INDOOR = 1, ENVIRON_OUTDOOR = 2 } ; struct regulatory_request { struct callback_head callback_head ; int wiphy_idx ; enum nl80211_reg_initiator initiator ; enum nl80211_user_reg_hint_type user_reg_hint_type ; char alpha2[2U] ; enum nl80211_dfs_regions dfs_region ; bool intersect ; bool processed ; enum environment_cap country_ie_env ; struct list_head list ; }; struct ieee80211_freq_range { u32 start_freq_khz ; u32 end_freq_khz ; u32 max_bandwidth_khz ; }; struct ieee80211_power_rule { u32 max_antenna_gain ; u32 max_eirp ; }; struct ieee80211_reg_rule { struct ieee80211_freq_range freq_range ; struct ieee80211_power_rule power_rule ; u32 flags ; u32 dfs_cac_ms ; }; struct ieee80211_regdomain { struct callback_head callback_head ; u32 n_reg_rules ; char alpha2[3U] ; enum nl80211_dfs_regions dfs_region ; struct ieee80211_reg_rule reg_rules[6] ; }; struct wiphy; enum ieee80211_band { IEEE80211_BAND_2GHZ = 0, IEEE80211_BAND_5GHZ = 1, IEEE80211_BAND_60GHZ = 2, IEEE80211_NUM_BANDS = 3 } ; struct ieee80211_channel { enum ieee80211_band band ; u16 center_freq ; u16 hw_value ; u32 flags ; int max_antenna_gain ; int max_power ; int max_reg_power ; bool beacon_found ; u32 orig_flags ; int orig_mag ; int orig_mpwr ; enum nl80211_dfs_state dfs_state ; unsigned long dfs_state_entered ; unsigned int dfs_cac_ms ; }; struct ieee80211_rate { u32 flags ; u16 bitrate ; u16 hw_value ; u16 hw_value_short ; }; struct ieee80211_sta_ht_cap { u16 cap ; bool ht_supported ; u8 ampdu_factor ; u8 ampdu_density ; struct ieee80211_mcs_info mcs ; }; struct ieee80211_sta_vht_cap { bool vht_supported ; u32 cap ; struct ieee80211_vht_mcs_info vht_mcs ; }; struct ieee80211_supported_band { struct ieee80211_channel *channels ; struct ieee80211_rate *bitrates ; enum ieee80211_band band ; int n_channels ; int n_bitrates ; struct ieee80211_sta_ht_cap ht_cap ; struct ieee80211_sta_vht_cap vht_cap ; }; struct cfg80211_chan_def { struct ieee80211_channel *chan ; enum nl80211_chan_width width ; u32 center_freq1 ; u32 center_freq2 ; }; struct survey_info { struct ieee80211_channel *channel ; u64 time ; u64 time_busy ; u64 time_ext_busy ; u64 time_rx ; u64 time_tx ; u64 time_scan ; u32 filled ; s8 noise ; }; struct cfg80211_crypto_settings { u32 wpa_versions ; u32 cipher_group ; int n_ciphers_pairwise ; u32 ciphers_pairwise[5U] ; int n_akm_suites ; u32 akm_suites[2U] ; bool control_port ; __be16 control_port_ethertype ; bool control_port_no_encrypt ; }; struct mac_address { u8 addr[6U] ; }; struct rate_info { u8 flags ; u8 mcs ; u16 legacy ; u8 nss ; u8 bw ; }; struct sta_bss_parameters { u8 flags ; u8 dtim_period ; u16 beacon_interval ; }; struct cfg80211_tid_stats { u32 filled ; u64 rx_msdu ; u64 tx_msdu ; u64 tx_msdu_retries ; u64 tx_msdu_failed ; }; struct station_info { u32 filled ; u32 connected_time ; u32 inactive_time ; u64 rx_bytes ; u64 tx_bytes ; u16 llid ; u16 plid ; u8 plink_state ; s8 signal ; s8 signal_avg ; u8 chains ; s8 chain_signal[4U] ; s8 chain_signal_avg[4U] ; struct rate_info txrate ; struct rate_info rxrate ; u32 rx_packets ; u32 tx_packets ; u32 tx_retries ; u32 tx_failed ; u32 rx_dropped_misc ; struct sta_bss_parameters bss_param ; struct nl80211_sta_flag_update sta_flags ; int generation ; u8 const *assoc_req_ies ; size_t assoc_req_ies_len ; u32 beacon_loss_count ; s64 t_offset ; enum nl80211_mesh_power_mode local_pm ; enum nl80211_mesh_power_mode peer_pm ; enum nl80211_mesh_power_mode nonpeer_pm ; u32 expected_throughput ; u64 rx_beacon ; u8 rx_beacon_signal_avg ; struct cfg80211_tid_stats pertid[17U] ; }; struct cfg80211_ssid { u8 ssid[32U] ; u8 ssid_len ; }; struct cfg80211_scan_request { struct cfg80211_ssid *ssids ; int n_ssids ; u32 n_channels ; enum nl80211_bss_scan_width scan_width ; u8 const *ie ; size_t ie_len ; u32 flags ; u32 rates[3U] ; struct wireless_dev *wdev ; u8 mac_addr[6U] ; u8 mac_addr_mask[6U] ; struct wiphy *wiphy ; unsigned long scan_start ; bool aborted ; bool notified ; bool no_cck ; struct ieee80211_channel *channels[0U] ; }; struct cfg80211_match_set { struct cfg80211_ssid ssid ; s32 rssi_thold ; }; struct cfg80211_sched_scan_request { struct cfg80211_ssid *ssids ; int n_ssids ; u32 n_channels ; enum nl80211_bss_scan_width scan_width ; u32 interval ; u8 const *ie ; size_t ie_len ; u32 flags ; struct cfg80211_match_set *match_sets ; int n_match_sets ; s32 min_rssi_thold ; u32 delay ; u8 mac_addr[6U] ; u8 mac_addr_mask[6U] ; struct wiphy *wiphy ; struct net_device *dev ; unsigned long scan_start ; struct callback_head callback_head ; u32 owner_nlportid ; struct ieee80211_channel *channels[0U] ; }; enum cfg80211_signal_type { CFG80211_SIGNAL_TYPE_NONE = 0, CFG80211_SIGNAL_TYPE_MBM = 1, CFG80211_SIGNAL_TYPE_UNSPEC = 2 } ; struct cfg80211_ibss_params { u8 const *ssid ; u8 const *bssid ; struct cfg80211_chan_def chandef ; u8 const *ie ; u8 ssid_len ; u8 ie_len ; u16 beacon_interval ; u32 basic_rates ; bool channel_fixed ; bool privacy ; bool control_port ; bool userspace_handles_dfs ; int mcast_rate[3U] ; struct ieee80211_ht_cap ht_capa ; struct ieee80211_ht_cap ht_capa_mask ; }; struct cfg80211_connect_params { struct ieee80211_channel *channel ; struct ieee80211_channel *channel_hint ; u8 const *bssid ; u8 const *bssid_hint ; u8 const *ssid ; size_t ssid_len ; enum nl80211_auth_type auth_type ; u8 const *ie ; size_t ie_len ; bool privacy ; enum nl80211_mfp mfp ; struct cfg80211_crypto_settings crypto ; u8 const *key ; u8 key_len ; u8 key_idx ; u32 flags ; int bg_scan_period ; struct ieee80211_ht_cap ht_capa ; struct ieee80211_ht_cap ht_capa_mask ; struct ieee80211_vht_cap vht_capa ; struct ieee80211_vht_cap vht_capa_mask ; }; struct __anonstruct_control_373 { u32 legacy ; u8 ht_mcs[10U] ; u16 vht_mcs[8U] ; enum nl80211_txrate_gi gi ; }; struct cfg80211_bitrate_mask { struct __anonstruct_control_373 control[3U] ; }; struct cfg80211_pkt_pattern { u8 const *mask ; u8 const *pattern ; int pattern_len ; int pkt_offset ; }; struct cfg80211_wowlan_tcp { struct socket *sock ; __be32 src ; __be32 dst ; u16 src_port ; u16 dst_port ; u8 dst_mac[6U] ; int payload_len ; u8 const *payload ; struct nl80211_wowlan_tcp_data_seq payload_seq ; u32 data_interval ; u32 wake_len ; u8 const *wake_data ; u8 const *wake_mask ; u32 tokens_size ; struct nl80211_wowlan_tcp_data_token payload_tok ; }; struct cfg80211_wowlan { bool any ; bool disconnect ; bool magic_pkt ; bool gtk_rekey_failure ; bool eap_identity_req ; bool four_way_handshake ; bool rfkill_release ; struct cfg80211_pkt_pattern *patterns ; struct cfg80211_wowlan_tcp *tcp ; int n_patterns ; struct cfg80211_sched_scan_request *nd_config ; }; struct cfg80211_gtk_rekey_data { u8 const *kek ; u8 const *kck ; u8 const *replay_ctr ; }; struct ieee80211_iface_limit { u16 max ; u16 types ; }; struct ieee80211_iface_combination { struct ieee80211_iface_limit const *limits ; u32 num_different_channels ; u16 max_interfaces ; u8 n_limits ; bool beacon_int_infra_match ; u8 radar_detect_widths ; u8 radar_detect_regions ; }; struct ieee80211_txrx_stypes { u16 tx ; u16 rx ; }; struct wiphy_wowlan_tcp_support { struct nl80211_wowlan_tcp_data_token_feature const *tok ; u32 data_payload_max ; u32 data_interval_max ; u32 wake_payload_max ; bool seq ; }; struct wiphy_wowlan_support { u32 flags ; int n_patterns ; int pattern_max_len ; int pattern_min_len ; int max_pkt_offset ; int max_nd_match_sets ; struct wiphy_wowlan_tcp_support const *tcp ; }; struct wiphy_coalesce_support { int n_rules ; int max_delay ; int n_patterns ; int pattern_max_len ; int pattern_min_len ; int max_pkt_offset ; }; struct wiphy_vendor_command { struct nl80211_vendor_cmd_info info ; u32 flags ; int (*doit)(struct wiphy * , struct wireless_dev * , void const * , int ) ; }; struct wiphy { u8 perm_addr[6U] ; u8 addr_mask[6U] ; struct mac_address *addresses ; struct ieee80211_txrx_stypes const *mgmt_stypes ; struct ieee80211_iface_combination const *iface_combinations ; int n_iface_combinations ; u16 software_iftypes ; u16 n_addresses ; u16 interface_modes ; u16 max_acl_mac_addrs ; u32 flags ; u32 regulatory_flags ; u32 features ; u8 ext_features[1U] ; u32 ap_sme_capa ; enum cfg80211_signal_type signal_type ; int bss_priv_size ; u8 max_scan_ssids ; u8 max_sched_scan_ssids ; u8 max_match_sets ; u16 max_scan_ie_len ; u16 max_sched_scan_ie_len ; int n_cipher_suites ; u32 const *cipher_suites ; u8 retry_short ; u8 retry_long ; u32 frag_threshold ; u32 rts_threshold ; u8 coverage_class ; char fw_version[32U] ; u32 hw_version ; struct wiphy_wowlan_support const *wowlan ; struct cfg80211_wowlan *wowlan_config ; u16 max_remain_on_channel_duration ; u8 max_num_pmkids ; u32 available_antennas_tx ; u32 available_antennas_rx ; u32 probe_resp_offload ; u8 const *extended_capabilities ; u8 const *extended_capabilities_mask ; u8 extended_capabilities_len ; void const *privid ; struct ieee80211_supported_band *bands[3U] ; void (*reg_notifier)(struct wiphy * , struct regulatory_request * ) ; struct ieee80211_regdomain const *regd ; struct device dev ; bool registered ; struct dentry *debugfsdir ; struct ieee80211_ht_cap const *ht_capa_mod_mask ; struct ieee80211_vht_cap const *vht_capa_mod_mask ; possible_net_t _net ; struct iw_handler_def const *wext ; struct wiphy_coalesce_support const *coalesce ; struct wiphy_vendor_command const *vendor_commands ; struct nl80211_vendor_cmd_info const *vendor_events ; int n_vendor_commands ; int n_vendor_events ; u16 max_ap_assoc_sta ; u8 max_num_csa_counters ; u8 max_adj_channel_rssi_comp ; char priv[0U] ; }; struct cfg80211_conn; struct cfg80211_internal_bss; struct cfg80211_cached_keys; struct __anonstruct_wext_374 { struct cfg80211_ibss_params ibss ; struct cfg80211_connect_params connect ; struct cfg80211_cached_keys *keys ; u8 const *ie ; size_t ie_len ; u8 bssid[6U] ; u8 prev_bssid[6U] ; u8 ssid[32U] ; s8 default_key ; s8 default_mgmt_key ; bool prev_bssid_valid ; }; struct wireless_dev { struct wiphy *wiphy ; enum nl80211_iftype iftype ; struct list_head list ; struct net_device *netdev ; u32 identifier ; struct list_head mgmt_registrations ; spinlock_t mgmt_registrations_lock ; struct mutex mtx ; bool use_4addr ; bool p2p_started ; u8 address[6U] ; u8 ssid[32U] ; u8 ssid_len ; u8 mesh_id_len ; u8 mesh_id_up_len ; struct cfg80211_conn *conn ; struct cfg80211_cached_keys *connect_keys ; struct list_head event_list ; spinlock_t event_lock ; struct cfg80211_internal_bss *current_bss ; struct cfg80211_chan_def preset_chandef ; struct cfg80211_chan_def chandef ; bool ibss_fixed ; bool ibss_dfs_possible ; bool ps ; int ps_timeout ; int beacon_interval ; u32 ap_unexpected_nlportid ; bool cac_started ; unsigned long cac_start_time ; unsigned int cac_time_ms ; u32 owner_nlportid ; struct __anonstruct_wext_374 wext ; }; struct ieee80211_tx_queue_params { u16 txop ; u16 cw_min ; u16 cw_max ; u8 aifs ; bool acm ; bool uapsd ; }; struct ieee80211_low_level_stats { unsigned int dot11ACKFailureCount ; unsigned int dot11RTSFailureCount ; unsigned int dot11FCSErrorCount ; unsigned int dot11RTSSuccessCount ; }; struct ieee80211_chanctx_conf { struct cfg80211_chan_def def ; struct cfg80211_chan_def min_def ; u8 rx_chains_static ; u8 rx_chains_dynamic ; bool radar_enabled ; u8 drv_priv[0U] ; }; enum ieee80211_chanctx_switch_mode { CHANCTX_SWMODE_REASSIGN_VIF = 0, CHANCTX_SWMODE_SWAP_CONTEXTS = 1 } ; struct ieee80211_vif; struct ieee80211_vif_chanctx_switch { struct ieee80211_vif *vif ; struct ieee80211_chanctx_conf *old_ctx ; struct ieee80211_chanctx_conf *new_ctx ; }; enum ieee80211_event_type { RSSI_EVENT = 0, MLME_EVENT = 1, BAR_RX_EVENT = 2, BA_FRAME_TIMEOUT = 3 } ; enum ieee80211_rssi_event_data { RSSI_EVENT_HIGH = 0, RSSI_EVENT_LOW = 1 } ; struct ieee80211_rssi_event { enum ieee80211_rssi_event_data data ; }; enum ieee80211_mlme_event_data { AUTH_EVENT = 0, ASSOC_EVENT = 1, DEAUTH_RX_EVENT = 2, DEAUTH_TX_EVENT = 3 } ; enum ieee80211_mlme_event_status { MLME_SUCCESS = 0, MLME_DENIED = 1, MLME_TIMEOUT = 2 } ; struct ieee80211_mlme_event { enum ieee80211_mlme_event_data data ; enum ieee80211_mlme_event_status status ; u16 reason ; }; struct ieee80211_sta; struct ieee80211_ba_event { struct ieee80211_sta *sta ; u16 tid ; u16 ssn ; }; union __anonunion_u_375 { struct ieee80211_rssi_event rssi ; struct ieee80211_mlme_event mlme ; struct ieee80211_ba_event ba ; }; struct ieee80211_event { enum ieee80211_event_type type ; union __anonunion_u_375 u ; }; struct ieee80211_bss_conf { u8 const *bssid ; bool assoc ; bool ibss_joined ; bool ibss_creator ; u16 aid ; bool use_cts_prot ; bool use_short_preamble ; bool use_short_slot ; bool enable_beacon ; u8 dtim_period ; u16 beacon_int ; u16 assoc_capability ; u64 sync_tsf ; u32 sync_device_ts ; u8 sync_dtim_count ; u32 basic_rates ; struct ieee80211_rate *beacon_rate ; int mcast_rate[3U] ; u16 ht_operation_mode ; s32 cqm_rssi_thold ; u32 cqm_rssi_hyst ; struct cfg80211_chan_def chandef ; __be32 arp_addr_list[4U] ; int arp_addr_cnt ; bool qos ; bool idle ; bool ps ; u8 ssid[32U] ; size_t ssid_len ; bool hidden_ssid ; int txpower ; enum nl80211_tx_power_setting txpower_type ; struct ieee80211_p2p_noa_attr p2p_noa_attr ; }; struct ieee80211_tx_rate { s8 idx ; unsigned char count : 5 ; unsigned short flags : 11 ; }; struct __anonstruct____missing_field_name_379 { struct ieee80211_tx_rate rates[4U] ; s8 rts_cts_rate_idx ; unsigned char use_rts : 1 ; unsigned char use_cts_prot : 1 ; unsigned char short_preamble : 1 ; unsigned char skip_table : 1 ; }; union __anonunion____missing_field_name_378 { struct __anonstruct____missing_field_name_379 __annonCompField100 ; unsigned long jiffies ; }; struct ieee80211_key_conf; struct __anonstruct_control_377 { union __anonunion____missing_field_name_378 __annonCompField101 ; struct ieee80211_vif *vif ; struct ieee80211_key_conf *hw_key ; u32 flags ; }; struct __anonstruct_ack_380 { u64 cookie ; }; struct __anonstruct_status_381 { struct ieee80211_tx_rate rates[4U] ; s32 ack_signal ; u8 ampdu_ack_len ; u8 ampdu_len ; u8 antenna ; u16 tx_time ; void *status_driver_data[2U] ; }; struct __anonstruct____missing_field_name_382 { struct ieee80211_tx_rate driver_rates[4U] ; u8 pad[4U] ; void *rate_driver_data[3U] ; }; union __anonunion____missing_field_name_376 { struct __anonstruct_control_377 control ; struct __anonstruct_ack_380 ack ; struct __anonstruct_status_381 status ; struct __anonstruct____missing_field_name_382 __annonCompField102 ; void *driver_data[5U] ; }; struct ieee80211_tx_info { u32 flags ; u8 band ; u8 hw_queue ; u16 ack_frame_id ; union __anonunion____missing_field_name_376 __annonCompField103 ; }; struct ieee80211_scan_ies { u8 const *ies[3U] ; size_t len[3U] ; u8 const *common_ies ; size_t common_ie_len ; }; enum ieee80211_smps_mode { IEEE80211_SMPS_AUTOMATIC = 0, IEEE80211_SMPS_OFF = 1, IEEE80211_SMPS_STATIC = 2, IEEE80211_SMPS_DYNAMIC = 3, IEEE80211_SMPS_NUM_MODES = 4 } ; struct ieee80211_conf { u32 flags ; int power_level ; int dynamic_ps_timeout ; int max_sleep_period ; u16 listen_interval ; u8 ps_dtim_period ; u8 long_frame_max_tx_count ; u8 short_frame_max_tx_count ; struct cfg80211_chan_def chandef ; bool radar_enabled ; enum ieee80211_smps_mode smps_mode ; }; struct ieee80211_channel_switch { u64 timestamp ; u32 device_timestamp ; bool block_tx ; struct cfg80211_chan_def chandef ; u8 count ; }; struct ieee80211_txq; struct ieee80211_vif { enum nl80211_iftype type ; struct ieee80211_bss_conf bss_conf ; u8 addr[6U] ; bool p2p ; bool csa_active ; u8 cab_queue ; u8 hw_queue[4U] ; struct ieee80211_txq *txq ; struct ieee80211_chanctx_conf *chanctx_conf ; u32 driver_flags ; struct dentry *debugfs_dir ; u8 drv_priv[0U] ; }; struct ieee80211_key_conf { atomic64_t tx_pn ; u32 cipher ; u8 icv_len ; u8 iv_len ; u8 hw_key_idx ; u8 flags ; s8 keyidx ; u8 keylen ; u8 key[0U] ; }; struct __anonstruct_tkip_384 { u32 iv32 ; u16 iv16 ; }; struct __anonstruct_ccmp_385 { u8 pn[6U] ; }; struct __anonstruct_aes_cmac_386 { u8 pn[6U] ; }; struct __anonstruct_aes_gmac_387 { u8 pn[6U] ; }; struct __anonstruct_gcmp_388 { u8 pn[6U] ; }; struct __anonstruct_hw_389 { u8 seq[16U] ; u8 seq_len ; }; union __anonunion____missing_field_name_383 { struct __anonstruct_tkip_384 tkip ; struct __anonstruct_ccmp_385 ccmp ; struct __anonstruct_aes_cmac_386 aes_cmac ; struct __anonstruct_aes_gmac_387 aes_gmac ; struct __anonstruct_gcmp_388 gcmp ; struct __anonstruct_hw_389 hw ; }; struct ieee80211_key_seq { union __anonunion____missing_field_name_383 __annonCompField104 ; }; struct ieee80211_cipher_scheme { u32 cipher ; u16 iftype ; u8 hdr_len ; u8 pn_len ; u8 pn_off ; u8 key_idx_off ; u8 key_idx_mask ; u8 key_idx_shift ; u8 mic_len ; }; enum set_key_cmd { SET_KEY = 0, DISABLE_KEY = 1 } ; enum ieee80211_sta_state { IEEE80211_STA_NOTEXIST = 0, IEEE80211_STA_NONE = 1, IEEE80211_STA_AUTH = 2, IEEE80211_STA_ASSOC = 3, IEEE80211_STA_AUTHORIZED = 4 } ; enum ieee80211_sta_rx_bandwidth { IEEE80211_STA_RX_BW_20 = 0, IEEE80211_STA_RX_BW_40 = 1, IEEE80211_STA_RX_BW_80 = 2, IEEE80211_STA_RX_BW_160 = 3 } ; struct __anonstruct_rate_390 { s8 idx ; u8 count ; u8 count_cts ; u8 count_rts ; u16 flags ; }; struct ieee80211_sta_rates { struct callback_head callback_head ; struct __anonstruct_rate_390 rate[4U] ; }; struct ieee80211_sta { u32 supp_rates[3U] ; u8 addr[6U] ; u16 aid ; struct ieee80211_sta_ht_cap ht_cap ; struct ieee80211_sta_vht_cap vht_cap ; bool wme ; u8 uapsd_queues ; u8 max_sp ; u8 rx_nss ; enum ieee80211_sta_rx_bandwidth bandwidth ; enum ieee80211_smps_mode smps_mode ; struct ieee80211_sta_rates *rates ; bool tdls ; bool tdls_initiator ; bool mfp ; struct ieee80211_txq *txq[16U] ; u8 drv_priv[0U] ; }; enum sta_notify_cmd { STA_NOTIFY_SLEEP = 0, STA_NOTIFY_AWAKE = 1 } ; struct ieee80211_tx_control { struct ieee80211_sta *sta ; }; struct ieee80211_txq { struct ieee80211_vif *vif ; struct ieee80211_sta *sta ; u8 tid ; u8 ac ; u8 drv_priv[0U] ; }; enum ieee80211_hw_flags { IEEE80211_HW_HAS_RATE_CONTROL = 0, IEEE80211_HW_RX_INCLUDES_FCS = 1, IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING = 2, IEEE80211_HW_SIGNAL_UNSPEC = 3, IEEE80211_HW_SIGNAL_DBM = 4, IEEE80211_HW_NEED_DTIM_BEFORE_ASSOC = 5, IEEE80211_HW_SPECTRUM_MGMT = 6, IEEE80211_HW_AMPDU_AGGREGATION = 7, IEEE80211_HW_SUPPORTS_PS = 8, IEEE80211_HW_PS_NULLFUNC_STACK = 9, IEEE80211_HW_SUPPORTS_DYNAMIC_PS = 10, IEEE80211_HW_MFP_CAPABLE = 11, IEEE80211_HW_WANT_MONITOR_VIF = 12, IEEE80211_HW_NO_AUTO_VIF = 13, IEEE80211_HW_SW_CRYPTO_CONTROL = 14, IEEE80211_HW_SUPPORT_FAST_XMIT = 15, IEEE80211_HW_REPORTS_TX_ACK_STATUS = 16, IEEE80211_HW_CONNECTION_MONITOR = 17, IEEE80211_HW_QUEUE_CONTROL = 18, IEEE80211_HW_SUPPORTS_PER_STA_GTK = 19, IEEE80211_HW_AP_LINK_PS = 20, IEEE80211_HW_TX_AMPDU_SETUP_IN_HW = 21, IEEE80211_HW_SUPPORTS_RC_TABLE = 22, IEEE80211_HW_P2P_DEV_ADDR_FOR_INTF = 23, IEEE80211_HW_TIMING_BEACON_ONLY = 24, IEEE80211_HW_SUPPORTS_HT_CCK_RATES = 25, IEEE80211_HW_CHANCTX_STA_CSA = 26, IEEE80211_HW_SUPPORTS_CLONED_SKBS = 27, IEEE80211_HW_SINGLE_SCAN_ON_ALL_BANDS = 28, NUM_IEEE80211_HW_FLAGS = 29 } ; struct ieee80211_hw { struct ieee80211_conf conf ; struct wiphy *wiphy ; char const *rate_control_algorithm ; void *priv ; unsigned long flags[1U] ; unsigned int extra_tx_headroom ; unsigned int extra_beacon_tailroom ; int vif_data_size ; int sta_data_size ; int chanctx_data_size ; int txq_data_size ; u16 queues ; u16 max_listen_interval ; s8 max_signal ; u8 max_rates ; u8 max_report_rates ; u8 max_rate_tries ; u8 max_rx_aggregation_subframes ; u8 max_tx_aggregation_subframes ; u8 offchannel_tx_hw_queue ; u8 radiotap_mcs_details ; u16 radiotap_vht_details ; netdev_features_t netdev_features ; u8 uapsd_queues ; u8 uapsd_max_sp_len ; u8 n_cipher_schemes ; struct ieee80211_cipher_scheme const *cipher_schemes ; int txq_ac_max_pending ; }; struct ieee80211_scan_request { struct ieee80211_scan_ies ies ; struct cfg80211_scan_request req ; }; struct ieee80211_tdls_ch_sw_params { struct ieee80211_sta *sta ; struct cfg80211_chan_def *chandef ; u8 action_code ; u32 status ; u32 timestamp ; u16 switch_time ; u16 switch_timeout ; struct sk_buff *tmpl_skb ; u32 ch_sw_tm_ie ; }; enum ieee80211_ampdu_mlme_action { IEEE80211_AMPDU_RX_START = 0, IEEE80211_AMPDU_RX_STOP = 1, IEEE80211_AMPDU_TX_START = 2, IEEE80211_AMPDU_TX_STOP_CONT = 3, IEEE80211_AMPDU_TX_STOP_FLUSH = 4, IEEE80211_AMPDU_TX_STOP_FLUSH_CONT = 5, IEEE80211_AMPDU_TX_OPERATIONAL = 6 } ; enum ieee80211_frame_release_type { IEEE80211_FRAME_RELEASE_PSPOLL = 0, IEEE80211_FRAME_RELEASE_UAPSD = 1 } ; enum ieee80211_roc_type { IEEE80211_ROC_TYPE_NORMAL = 0, IEEE80211_ROC_TYPE_MGMT_TX = 1 } ; enum ieee80211_reconfig_type { IEEE80211_RECONFIG_TYPE_RESTART = 0, IEEE80211_RECONFIG_TYPE_SUSPEND = 1 } ; struct ieee80211_ops { void (*tx)(struct ieee80211_hw * , struct ieee80211_tx_control * , struct sk_buff * ) ; int (*start)(struct ieee80211_hw * ) ; void (*stop)(struct ieee80211_hw * ) ; int (*suspend)(struct ieee80211_hw * , struct cfg80211_wowlan * ) ; int (*resume)(struct ieee80211_hw * ) ; void (*set_wakeup)(struct ieee80211_hw * , bool ) ; int (*add_interface)(struct ieee80211_hw * , struct ieee80211_vif * ) ; int (*change_interface)(struct ieee80211_hw * , struct ieee80211_vif * , enum nl80211_iftype , bool ) ; void (*remove_interface)(struct ieee80211_hw * , struct ieee80211_vif * ) ; int (*config)(struct ieee80211_hw * , u32 ) ; void (*bss_info_changed)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_bss_conf * , u32 ) ; int (*start_ap)(struct ieee80211_hw * , struct ieee80211_vif * ) ; void (*stop_ap)(struct ieee80211_hw * , struct ieee80211_vif * ) ; u64 (*prepare_multicast)(struct ieee80211_hw * , struct netdev_hw_addr_list * ) ; void (*configure_filter)(struct ieee80211_hw * , unsigned int , unsigned int * , u64 ) ; int (*set_tim)(struct ieee80211_hw * , struct ieee80211_sta * , bool ) ; int (*set_key)(struct ieee80211_hw * , enum set_key_cmd , struct ieee80211_vif * , struct ieee80211_sta * , struct ieee80211_key_conf * ) ; void (*update_tkip_key)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_key_conf * , struct ieee80211_sta * , u32 , u16 * ) ; void (*set_rekey_data)(struct ieee80211_hw * , struct ieee80211_vif * , struct cfg80211_gtk_rekey_data * ) ; void (*set_default_unicast_key)(struct ieee80211_hw * , struct ieee80211_vif * , int ) ; int (*hw_scan)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_scan_request * ) ; void (*cancel_hw_scan)(struct ieee80211_hw * , struct ieee80211_vif * ) ; int (*sched_scan_start)(struct ieee80211_hw * , struct ieee80211_vif * , struct cfg80211_sched_scan_request * , struct ieee80211_scan_ies * ) ; int (*sched_scan_stop)(struct ieee80211_hw * , struct ieee80211_vif * ) ; void (*sw_scan_start)(struct ieee80211_hw * , struct ieee80211_vif * , u8 const * ) ; void (*sw_scan_complete)(struct ieee80211_hw * , struct ieee80211_vif * ) ; int (*get_stats)(struct ieee80211_hw * , struct ieee80211_low_level_stats * ) ; void (*get_key_seq)(struct ieee80211_hw * , struct ieee80211_key_conf * , struct ieee80211_key_seq * ) ; int (*set_frag_threshold)(struct ieee80211_hw * , u32 ) ; int (*set_rts_threshold)(struct ieee80211_hw * , u32 ) ; int (*sta_add)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * ) ; int (*sta_remove)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * ) ; void (*sta_add_debugfs)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * , struct dentry * ) ; void (*sta_remove_debugfs)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * , struct dentry * ) ; void (*sta_notify)(struct ieee80211_hw * , struct ieee80211_vif * , enum sta_notify_cmd , struct ieee80211_sta * ) ; int (*sta_state)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * , enum ieee80211_sta_state , enum ieee80211_sta_state ) ; void (*sta_pre_rcu_remove)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * ) ; void (*sta_rc_update)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * , u32 ) ; void (*sta_rate_tbl_update)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * ) ; void (*sta_statistics)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * , struct station_info * ) ; int (*conf_tx)(struct ieee80211_hw * , struct ieee80211_vif * , u16 , struct ieee80211_tx_queue_params const * ) ; u64 (*get_tsf)(struct ieee80211_hw * , struct ieee80211_vif * ) ; void (*set_tsf)(struct ieee80211_hw * , struct ieee80211_vif * , u64 ) ; void (*reset_tsf)(struct ieee80211_hw * , struct ieee80211_vif * ) ; int (*tx_last_beacon)(struct ieee80211_hw * ) ; int (*ampdu_action)(struct ieee80211_hw * , struct ieee80211_vif * , enum ieee80211_ampdu_mlme_action , struct ieee80211_sta * , u16 , u16 * , u8 ) ; int (*get_survey)(struct ieee80211_hw * , int , struct survey_info * ) ; void (*rfkill_poll)(struct ieee80211_hw * ) ; void (*set_coverage_class)(struct ieee80211_hw * , s16 ) ; int (*testmode_cmd)(struct ieee80211_hw * , struct ieee80211_vif * , void * , int ) ; int (*testmode_dump)(struct ieee80211_hw * , struct sk_buff * , struct netlink_callback * , void * , int ) ; void (*flush)(struct ieee80211_hw * , struct ieee80211_vif * , u32 , bool ) ; void (*channel_switch)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_channel_switch * ) ; int (*set_antenna)(struct ieee80211_hw * , u32 , u32 ) ; int (*get_antenna)(struct ieee80211_hw * , u32 * , u32 * ) ; int (*remain_on_channel)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_channel * , int , enum ieee80211_roc_type ) ; int (*cancel_remain_on_channel)(struct ieee80211_hw * ) ; int (*set_ringparam)(struct ieee80211_hw * , u32 , u32 ) ; void (*get_ringparam)(struct ieee80211_hw * , u32 * , u32 * , u32 * , u32 * ) ; bool (*tx_frames_pending)(struct ieee80211_hw * ) ; int (*set_bitrate_mask)(struct ieee80211_hw * , struct ieee80211_vif * , struct cfg80211_bitrate_mask const * ) ; void (*event_callback)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_event const * ) ; void (*allow_buffered_frames)(struct ieee80211_hw * , struct ieee80211_sta * , u16 , int , enum ieee80211_frame_release_type , bool ) ; void (*release_buffered_frames)(struct ieee80211_hw * , struct ieee80211_sta * , u16 , int , enum ieee80211_frame_release_type , bool ) ; int (*get_et_sset_count)(struct ieee80211_hw * , struct ieee80211_vif * , int ) ; void (*get_et_stats)(struct ieee80211_hw * , struct ieee80211_vif * , struct ethtool_stats * , u64 * ) ; void (*get_et_strings)(struct ieee80211_hw * , struct ieee80211_vif * , u32 , u8 * ) ; void (*mgd_prepare_tx)(struct ieee80211_hw * , struct ieee80211_vif * ) ; void (*mgd_protect_tdls_discover)(struct ieee80211_hw * , struct ieee80211_vif * ) ; int (*add_chanctx)(struct ieee80211_hw * , struct ieee80211_chanctx_conf * ) ; void (*remove_chanctx)(struct ieee80211_hw * , struct ieee80211_chanctx_conf * ) ; void (*change_chanctx)(struct ieee80211_hw * , struct ieee80211_chanctx_conf * , u32 ) ; int (*assign_vif_chanctx)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_chanctx_conf * ) ; void (*unassign_vif_chanctx)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_chanctx_conf * ) ; int (*switch_vif_chanctx)(struct ieee80211_hw * , struct ieee80211_vif_chanctx_switch * , int , enum ieee80211_chanctx_switch_mode ) ; void (*reconfig_complete)(struct ieee80211_hw * , enum ieee80211_reconfig_type ) ; void (*ipv6_addr_change)(struct ieee80211_hw * , struct ieee80211_vif * , struct inet6_dev * ) ; void (*channel_switch_beacon)(struct ieee80211_hw * , struct ieee80211_vif * , struct cfg80211_chan_def * ) ; int (*pre_channel_switch)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_channel_switch * ) ; int (*post_channel_switch)(struct ieee80211_hw * , struct ieee80211_vif * ) ; int (*join_ibss)(struct ieee80211_hw * , struct ieee80211_vif * ) ; void (*leave_ibss)(struct ieee80211_hw * , struct ieee80211_vif * ) ; u32 (*get_expected_throughput)(struct ieee80211_sta * ) ; int (*get_txpower)(struct ieee80211_hw * , struct ieee80211_vif * , int * ) ; int (*tdls_channel_switch)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * , u8 , struct cfg80211_chan_def * , struct sk_buff * , u32 ) ; void (*tdls_cancel_channel_switch)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_sta * ) ; void (*tdls_recv_channel_switch)(struct ieee80211_hw * , struct ieee80211_vif * , struct ieee80211_tdls_ch_sw_params * ) ; void (*wake_tx_queue)(struct ieee80211_hw * , struct ieee80211_txq * ) ; }; struct brcms_info; struct brcms_c_info; struct brcms_hardware; struct brcms_band; struct dma_pub; struct si_pub; struct phy_shim_info; struct brcms_phy_srom_fem { u8 tssipos ; u8 extpagain ; u8 pdetrange ; u8 triso ; u8 antswctrllut ; }; struct lo_complex_abgphy_info { s8 i ; s8 q ; }; struct nphy_iq_comp { s16 a0 ; s16 b0 ; s16 a1 ; s16 b1 ; }; struct nphy_txpwrindex { s8 index ; s8 index_internal ; s8 index_internal_save ; u16 AfectrlOverride ; u16 AfeCtrlDacGain ; u16 rad_gain ; u8 bbmult ; u16 iqcomp_a ; u16 iqcomp_b ; u16 locomp ; }; struct txiqcal_cache { u16 txcal_coeffs_2G[8U] ; u16 txcal_radio_regs_2G[8U] ; struct nphy_iq_comp rxcal_coeffs_2G ; u16 txcal_coeffs_5G[8U] ; u16 txcal_radio_regs_5G[8U] ; struct nphy_iq_comp rxcal_coeffs_5G ; }; struct nphy_pwrctrl { s8 max_pwr_2g ; s8 idle_targ_2g ; s16 pwrdet_2g_a1 ; s16 pwrdet_2g_b0 ; s16 pwrdet_2g_b1 ; s8 max_pwr_5gm ; s8 idle_targ_5gm ; s8 max_pwr_5gh ; s8 max_pwr_5gl ; s16 pwrdet_5gm_a1 ; s16 pwrdet_5gm_b0 ; s16 pwrdet_5gm_b1 ; s16 pwrdet_5gl_a1 ; s16 pwrdet_5gl_b0 ; s16 pwrdet_5gl_b1 ; s16 pwrdet_5gh_a1 ; s16 pwrdet_5gh_b0 ; s16 pwrdet_5gh_b1 ; s8 idle_targ_5gl ; s8 idle_targ_5gh ; s8 idle_tssi_2g ; s8 idle_tssi_5g ; s8 idle_tssi ; s16 a1 ; s16 b0 ; s16 b1 ; }; struct nphy_txgains { u16 txlpf[2U] ; u16 txgm[2U] ; u16 pga[2U] ; u16 pad[2U] ; u16 ipa[2U] ; }; struct nphy_noisevar_buf { int bufcount ; int tone_id[10U] ; u32 noise_vars[10U] ; u32 min_noise_vars[10U] ; }; struct rssical_cache { u16 rssical_radio_regs_2G[2U] ; u16 rssical_phyregs_2G[12U] ; u16 rssical_radio_regs_5G[2U] ; u16 rssical_phyregs_5G[12U] ; }; struct brcms_phy; struct shared_phy { struct brcms_phy *phy_head ; uint unit ; struct phy_shim_info *physhim ; uint corerev ; u32 machwcap ; bool up ; bool clk ; uint now ; u16 vid ; u16 did ; uint chip ; uint chiprev ; uint chippkg ; uint sromrev ; uint boardtype ; uint boardrev ; u32 boardflags ; u32 boardflags2 ; uint fast_timer ; uint slow_timer ; uint glacial_timer ; u8 rx_antdiv ; s8 phy_noise_window[8U] ; uint phy_noise_index ; u8 hw_phytxchain ; u8 hw_phyrxchain ; u8 phytxchain ; u8 phyrxchain ; u8 rssi_mode ; bool _rifs_phy ; }; struct brcms_phy_pub { uint phy_type ; uint phy_rev ; u8 phy_corenum ; u16 radioid ; u8 radiorev ; u8 radiover ; uint coreflags ; uint ana_rev ; bool abgphy_encore ; }; struct phy_func_ptr { void (*init)(struct brcms_phy * ) ; void (*calinit)(struct brcms_phy * ) ; void (*chanset)(struct brcms_phy * , u16 ) ; void (*txpwrrecalc)(struct brcms_phy * ) ; int (*longtrn)(struct brcms_phy * , int ) ; void (*txiqccget)(struct brcms_phy * , u16 * , u16 * ) ; void (*txiqccset)(struct brcms_phy * , u16 , u16 ) ; u16 (*txloccget)(struct brcms_phy * ) ; void (*radioloftget)(struct brcms_phy * , u8 * , u8 * , u8 * , u8 * ) ; void (*carrsuppr)(struct brcms_phy * ) ; s32 (*rxsigpwr)(struct brcms_phy * , s32 ) ; void (*detach)(struct brcms_phy * ) ; }; struct brcms_phy_lcnphy; union __anonunion_u_392 { struct brcms_phy_lcnphy *pi_lcnphy ; }; struct wlapi_timer; struct brcms_phy { struct brcms_phy_pub pubpi_ro ; struct shared_phy *sh ; struct phy_func_ptr pi_fptr ; union __anonunion_u_392 u ; bool user_txpwr_at_rfport ; struct bcma_device *d11core ; struct brcms_phy *next ; struct brcms_phy_pub pubpi ; bool do_initcal ; bool phytest_on ; bool ofdm_rateset_war ; bool bf_preempt_4306 ; u16 radio_chanspec ; u8 antsel_type ; u16 bw ; u8 txpwr_percent ; bool phy_init_por ; bool init_in_progress ; bool initialized ; bool sbtml_gm ; uint refcnt ; bool watchdog_override ; u8 phynoise_state ; uint phynoise_now ; int phynoise_chan_watchdog ; bool phynoise_polling ; bool disable_percal ; u32 measure_hold ; s16 txpa_2g[3U] ; s16 txpa_2g_low_temp[3U] ; s16 txpa_2g_high_temp[3U] ; s16 txpa_5g_low[3U] ; s16 txpa_5g_mid[3U] ; s16 txpa_5g_hi[3U] ; u8 tx_srom_max_2g ; u8 tx_srom_max_5g_low ; u8 tx_srom_max_5g_mid ; u8 tx_srom_max_5g_hi ; u8 tx_srom_max_rate_2g[101U] ; u8 tx_srom_max_rate_5g_low[101U] ; u8 tx_srom_max_rate_5g_mid[101U] ; u8 tx_srom_max_rate_5g_hi[101U] ; u8 tx_user_target[101U] ; s8 tx_power_offset[101U] ; u8 tx_power_target[101U] ; struct brcms_phy_srom_fem srom_fem2g ; struct brcms_phy_srom_fem srom_fem5g ; u8 tx_power_max ; u8 tx_power_max_rate_ind ; bool hwpwrctrl ; u8 nphy_txpwrctrl ; s8 nphy_txrx_chain ; bool phy_5g_pwrgain ; u16 phy_wreg ; u16 phy_wreg_limit ; s8 n_preamble_override ; u8 antswitch ; u8 aa2g ; u8 aa5g ; s8 idle_tssi[3U] ; s8 target_idle_tssi ; s8 txpwr_est_Pout ; u8 tx_power_min ; u8 txpwr_limit[101U] ; u8 txpwr_env_limit[101U] ; u8 adj_pwr_tbl_nphy[84U] ; bool channel_14_wide_filter ; bool txpwroverride ; bool txpwridx_override_aphy ; s16 radiopwr_override ; u16 hwpwr_txcur ; u8 saved_txpwr_idx ; bool edcrs_threshold_lock ; u32 tr_R_gain_val ; u32 tr_T_gain_val ; s16 ofdm_analog_filt_bw_override ; s16 cck_analog_filt_bw_override ; s16 ofdm_rccal_override ; s16 cck_rccal_override ; u16 extlna_type ; uint interference_mode_crs_time ; u16 crsglitch_prev ; bool interference_mode_crs ; u32 phy_tx_tone_freq ; uint phy_lastcal ; bool phy_forcecal ; bool phy_fixed_noise ; u32 xtalfreq ; u8 pdiv ; s8 carrier_suppr_disable ; bool phy_bphy_evm ; bool phy_bphy_rfcs ; s8 phy_scraminit ; u8 phy_gpiosel ; s16 phy_txcore_disable_temp ; s16 phy_txcore_enable_temp ; s8 phy_tempsense_offset ; bool phy_txcore_heatedup ; u16 radiopwr ; u16 bb_atten ; u16 txctl1 ; u16 mintxbias ; u16 mintxmag ; struct lo_complex_abgphy_info gphy_locomp_iq[32U][9U] ; s8 stats_11b_txpower[32U][9U] ; u16 gain_table[64U] ; bool loopback_gain ; s16 max_lpback_gain_hdB ; s16 trsw_rx_gain_hdB ; u8 power_vec[8U] ; u16 rc_cal ; int nrssi_table_delta ; int nrssi_slope_scale ; int nrssi_slope_offset ; int min_rssi ; int max_rssi ; s8 txpwridx ; u8 min_txpower ; u8 a_band_high_disable ; u16 tx_vos ; u16 global_tx_bb_dc_bias_loft ; int rf_max ; int bb_max ; int rf_list_size ; int bb_list_size ; u16 *rf_attn_list ; u16 *bb_attn_list ; u16 padmix_mask ; u16 padmix_reg ; u16 *txmag_list ; uint txmag_len ; bool txmag_enable ; s8 *a_tssi_to_dbm ; s8 *m_tssi_to_dbm ; s8 *l_tssi_to_dbm ; s8 *h_tssi_to_dbm ; u8 *hwtxpwr ; u16 freqtrack_saved_regs[2U] ; int cur_interference_mode ; bool hwpwrctrl_capable ; bool temppwrctrl_capable ; uint phycal_nslope ; uint phycal_noffset ; uint phycal_mlo ; uint phycal_txpower ; u8 phy_aa2g ; bool nphy_tableloaded ; s8 nphy_rssisel ; u32 nphy_bb_mult_save ; u16 nphy_txiqlocal_bestc[11U] ; bool nphy_txiqlocal_coeffsvalid ; struct nphy_txpwrindex nphy_txpwrindex[2U] ; struct nphy_pwrctrl nphy_pwrctrl_info[2U] ; u16 cck2gpo ; u32 ofdm2gpo ; u32 ofdm5gpo ; u32 ofdm5glpo ; u32 ofdm5ghpo ; u8 bw402gpo ; u8 bw405gpo ; u8 bw405glpo ; u8 bw405ghpo ; u8 cdd2gpo ; u8 cdd5gpo ; u8 cdd5glpo ; u8 cdd5ghpo ; u8 stbc2gpo ; u8 stbc5gpo ; u8 stbc5glpo ; u8 stbc5ghpo ; u8 bwdup2gpo ; u8 bwdup5gpo ; u8 bwdup5glpo ; u8 bwdup5ghpo ; u16 mcs2gpo[8U] ; u16 mcs5gpo[8U] ; u16 mcs5glpo[8U] ; u16 mcs5ghpo[8U] ; u32 nphy_rxcalparams ; u8 phy_spuravoid ; bool phy_isspuravoid ; u8 phy_pabias ; u8 nphy_papd_skip ; u8 nphy_tssi_slope ; s16 nphy_noise_win[4U][16U] ; u8 nphy_noise_index ; bool nphy_gain_boost ; bool nphy_elna_gain_config ; u16 old_bphy_test ; u16 old_bphy_testcontrol ; bool phyhang_avoid ; bool rssical_nphy ; u8 nphy_perical ; uint nphy_perical_last ; u8 cal_type_override ; u8 mphase_cal_phase_id ; u8 mphase_txcal_cmdidx ; u8 mphase_txcal_numcmds ; u16 mphase_txcal_bestcoeffs[11U] ; u16 nphy_txiqlocal_chanspec ; u16 nphy_iqcal_chanspec_2G ; u16 nphy_iqcal_chanspec_5G ; u16 nphy_rssical_chanspec_2G ; u16 nphy_rssical_chanspec_5G ; struct wlapi_timer *phycal_timer ; bool use_int_tx_iqlo_cal_nphy ; bool internal_tx_iqlo_cal_tapoff_intpa_nphy ; s16 nphy_lastcal_temp ; struct txiqcal_cache calibration_cache ; struct rssical_cache rssical_cache ; u8 nphy_txpwr_idx[2U] ; u8 nphy_papd_cal_type ; uint nphy_papd_last_cal ; u16 nphy_papd_tx_gain_at_last_cal[2U] ; u8 nphy_papd_cal_gain_index[2U] ; s16 nphy_papd_epsilon_offset[2U] ; bool nphy_papd_recal_enable ; u32 nphy_papd_recal_counter ; bool nphy_force_papd_cal ; bool nphy_papdcomp ; bool ipa2g_on ; bool ipa5g_on ; u16 classifier_state ; u16 clip_state[2U] ; uint nphy_deaf_count ; u8 rxiq_samps ; u8 rxiq_antsel ; u16 rfctrlIntc1_save ; u16 rfctrlIntc2_save ; bool first_cal_after_assoc ; u16 tx_rx_cal_radio_saveregs[22U] ; u16 tx_rx_cal_phy_saveregs[15U] ; u8 nphy_cal_orig_pwr_idx[2U] ; u8 nphy_txcal_pwr_idx[2U] ; u8 nphy_rxcal_pwr_idx[2U] ; u16 nphy_cal_orig_tx_gain[2U] ; struct nphy_txgains nphy_cal_target_gain ; u16 nphy_txcal_bbmult ; u16 nphy_gmval ; u16 nphy_saved_bbconf ; bool nphy_gband_spurwar_en ; bool nphy_gband_spurwar2_en ; bool nphy_aband_spurwar_en ; u16 nphy_rccal_value ; u16 nphy_crsminpwr[3U] ; struct nphy_noisevar_buf nphy_saved_noisevars ; bool nphy_anarxlpf_adjusted ; bool nphy_crsminpwr_adjusted ; bool nphy_noisevars_adjusted ; bool nphy_rxcal_active ; u16 radar_percal_mask ; bool dfs_lp_buffer_nphy ; u16 nphy_fineclockgatecontrol ; s8 rx2tx_biasentry ; u16 crsminpwr0 ; u16 crsminpwrl0 ; u16 crsminpwru0 ; s16 noise_crsminpwr_index ; u16 init_gain_core1 ; u16 init_gain_core2 ; u16 init_gainb_core1 ; u16 init_gainb_core2 ; u8 aci_noise_curr_channel ; u16 init_gain_rfseq[4U] ; bool radio_is_on ; bool nphy_sample_play_lpf_bw_ctl_ovr ; u16 tbl_data_hi ; u16 tbl_data_lo ; u16 tbl_addr ; uint tbl_save_id ; uint tbl_save_offset ; u8 txpwrctrl ; s8 txpwrindex[4U] ; u8 phycal_tempdelta ; u32 mcs20_po ; u32 mcs40_po ; struct wiphy *wiphy ; }; struct brcm_rateset { u32 count ; u8 rates[16U] ; }; struct brcms_c_rateset { uint count ; u8 rates[16U] ; u8 htphy_membership ; u8 mcs[16U] ; }; struct brcms_bss_info { u8 BSSID[6U] ; u16 flags ; u8 SSID_len ; u8 SSID[32U] ; s16 RSSI ; s16 SNR ; u16 beacon_period ; u16 chanspec ; struct brcms_c_rateset rateset ; }; struct scb_ampdu; struct wl_cnt; struct brcms_pub { struct brcms_c_info *wlc ; struct ieee80211_hw *ieee_hw ; struct scb_ampdu *global_ampdu ; uint mac80211_state ; uint unit ; uint corerev ; struct si_pub *sih ; bool up ; bool hw_off ; bool hw_up ; bool _piomode ; uint _nbands ; uint now ; bool delayed_down ; bool associated ; bool _ampdu ; u8 _n_enab ; u8 cur_etheraddr[6U] ; u32 radio_disabled ; u16 boardrev ; u8 sromrev ; char srom_ccode[4U] ; u32 boardflags ; u32 boardflags2 ; bool phy_11ncapable ; struct wl_cnt *_cnt ; struct dentry *dbgfs_dir ; }; struct brcms_antselcfg { u8 ant_config[4U] ; u8 num_antcfg ; }; struct dma_pub { uint txavail ; uint dmactrlflags ; uint rxgiants ; uint rxnobuf ; uint txnobuf ; }; struct macstat { u16 txallfrm ; u16 txrtsfrm ; u16 txctsfrm ; u16 txackfrm ; u16 txdnlfrm ; u16 txbcnfrm ; u16 txfunfl[8U] ; u16 txtplunfl ; u16 txphyerr ; u16 pktengrxducast ; u16 pktengrxdmcast ; u16 rxfrmtoolong ; u16 rxfrmtooshrt ; u16 rxinvmachdr ; u16 rxbadfcs ; u16 rxbadplcp ; u16 rxcrsglitch ; u16 rxstrt ; u16 rxdfrmucastmbss ; u16 rxmfrmucastmbss ; u16 rxcfrmucast ; u16 rxrtsucast ; u16 rxctsucast ; u16 rxackucast ; u16 rxdfrmocast ; u16 rxmfrmocast ; u16 rxcfrmocast ; u16 rxrtsocast ; u16 rxctsocast ; u16 rxdfrmmcast ; u16 rxmfrmmcast ; u16 rxcfrmmcast ; u16 rxbeaconmbss ; u16 rxdfrmucastobss ; u16 rxbeaconobss ; u16 rxrsptmout ; u16 bcntxcancl ; u16 pad1715 ; u16 rxf0ovfl ; u16 rxf1ovfl ; u16 rxf2ovfl ; u16 txsfovfl ; u16 pmqovfl ; u16 rxcgprqfrm ; u16 rxcgprsqovfl ; u16 txcgprsfail ; u16 txcgprssuc ; u16 prs_timeout ; u16 rxnack ; u16 frmscons ; u16 txnack ; u16 txglitch_nack ; u16 txburst ; u16 bphy_rxcrsglitch ; u16 phywatchdog ; u16 pad1733 ; u16 bphy_badplcp ; }; struct brcms_cm_info; struct scb; struct scb_ampdu_tid_ini { u8 tid ; u8 txretry[64U] ; struct scb *scb ; u8 ba_wsize ; }; struct scb_ampdu { struct scb *scb ; u8 mpdu_density ; u8 max_pdu ; u8 release ; u16 min_len ; u32 max_rx_ampdu_bytes ; struct scb_ampdu_tid_ini ini[8U] ; }; struct scb { u32 magic ; u32 flags ; u32 flags2 ; u8 state ; u8 ea[6U] ; uint fragresid[8U] ; u16 seqctl[8U] ; u16 seqctl_nonqos ; u16 seqnum[8U] ; struct scb_ampdu scb_ampdu ; }; struct d11init; struct brcms_ucode { struct d11init *d11lcn0bsinitvals24 ; struct d11init *d11lcn0initvals24 ; struct d11init *d11lcn1bsinitvals24 ; struct d11init *d11lcn1initvals24 ; struct d11init *d11lcn2bsinitvals24 ; struct d11init *d11lcn2initvals24 ; struct d11init *d11n0absinitvals16 ; struct d11init *d11n0bsinitvals16 ; struct d11init *d11n0initvals16 ; __le32 *bcm43xx_16_mimo ; size_t bcm43xx_16_mimosz ; __le32 *bcm43xx_24_lcn ; size_t bcm43xx_24_lcnsz ; u32 *bcm43xx_bommajor ; u32 *bcm43xx_bomminor ; }; enum led_brightness { LED_OFF = 0, LED_HALF = 127, LED_FULL = 255 } ; struct led_trigger; struct led_classdev { char const *name ; enum led_brightness brightness ; enum led_brightness max_brightness ; int flags ; void (*brightness_set)(struct led_classdev * , enum led_brightness ) ; int (*brightness_set_sync)(struct led_classdev * , enum led_brightness ) ; enum led_brightness (*brightness_get)(struct led_classdev * ) ; int (*blink_set)(struct led_classdev * , unsigned long * , unsigned long * ) ; struct device *dev ; struct attribute_group const **groups ; struct list_head node ; char const *default_trigger ; unsigned long blink_delay_on ; unsigned long blink_delay_off ; struct timer_list blink_timer ; int blink_brightness ; void (*flash_resume)(struct led_classdev * ) ; struct work_struct set_brightness_work ; int delayed_set_value ; struct rw_semaphore trigger_lock ; struct led_trigger *trigger ; struct list_head trig_list ; void *trigger_data ; bool activated ; struct mutex led_access ; }; struct led_trigger { char const *name ; void (*activate)(struct led_classdev * ) ; void (*deactivate)(struct led_classdev * ) ; rwlock_t leddev_list_lock ; struct list_head led_cdevs ; struct list_head next_trig ; }; struct brcms_led { char name[32U] ; unsigned int gpio ; bool active_low ; }; struct brcms_timer { struct delayed_work dly_wrk ; struct brcms_info *wl ; void (*fn)(void * ) ; void *arg ; uint ms ; bool periodic ; bool set ; struct brcms_timer *next ; }; struct brcms_if { uint subunit ; struct pci_dev *pci_dev ; }; struct brcms_firmware { u32 fw_cnt ; struct firmware const *fw_bin[4U] ; struct firmware const *fw_hdr[4U] ; u32 hdr_num_entries[4U] ; }; struct brcms_info { struct brcms_pub *pub ; struct brcms_c_info *wlc ; u32 magic ; int irq ; spinlock_t lock ; spinlock_t isr_lock ; wait_queue_head_t tx_flush_wq ; atomic_t callbacks ; struct brcms_timer *timers ; struct tasklet_struct tasklet ; bool resched ; struct brcms_firmware fw ; struct wiphy *wiphy ; struct brcms_ucode ucode ; bool mute_tx ; struct brcms_led radio_led ; struct led_classdev led_dev ; }; struct brcms_protection { bool _g ; s8 g_override ; u8 gmode_user ; s8 overlap ; s8 nmode_user ; s8 n_cfg ; s8 n_cfg_override ; bool nongf ; s8 nongf_override ; s8 n_pam_override ; bool n_obss ; }; struct brcms_stf { u8 hw_txchain ; u8 txchain ; u8 txstreams ; u8 hw_rxchain ; u8 rxchain ; u8 rxstreams ; u8 ant_rx_ovr ; s8 txant ; u16 phytxant ; u8 ss_opmode ; bool ss_algosel_auto ; u16 ss_algo_channel ; u8 rxchain_restore_delay ; s8 ldpc ; u8 txcore[5U] ; s8 spatial_policy ; }; struct brcms_core { uint coreidx ; uint *txavail[6U] ; struct macstat *macstat_snapshot ; }; struct brcms_band { int bandtype ; uint bandunit ; u16 phytype ; u16 phyrev ; u16 radioid ; u16 radiorev ; struct brcms_phy_pub *pi ; bool abgphy_encore ; u8 gmode ; struct scb *hwrs_scb ; struct brcms_c_rateset defrateset ; u8 band_stf_ss_mode ; s8 band_stf_stbc_tx ; struct brcms_c_rateset hw_rateset ; u8 basic_rate[109U] ; bool mimo_cap_40 ; s8 antgain ; u16 CWmin ; u16 CWmax ; struct ieee80211_supported_band band ; }; struct modulecb { char name[32U] ; struct brcms_info *hdl ; int (*down_fn)(void * ) ; }; struct brcms_hw_band { int bandtype ; uint bandunit ; u16 mhfs[5U] ; u8 bandhw_stf_ss_mode ; u16 CWmin ; u16 CWmax ; u32 core_flags ; u16 phytype ; u16 phyrev ; u16 radioid ; u16 radiorev ; struct brcms_phy_pub *pi ; bool abgphy_encore ; }; struct brcms_hardware { bool _piomode ; struct brcms_c_info *wlc ; struct dma_pub *di[6U] ; uint unit ; u16 vendorid ; u16 deviceid ; uint corerev ; u8 sromrev ; u16 boardrev ; u32 boardflags ; u32 boardflags2 ; u32 machwcap ; u32 machwcap_backup ; struct si_pub *sih ; struct bcma_device *d11core ; struct phy_shim_info *physhim ; struct shared_phy *phy_sh ; struct brcms_hw_band *band ; struct brcms_hw_band *bandstate[2U] ; u16 bmac_phytxant ; bool shortslot ; u16 SRL ; u16 LRL ; u16 SFBL ; u16 LFBL ; bool up ; uint now ; uint _nbands ; u16 chanspec ; uint *txavail[6U] ; u16 const *xmtfifo_sz ; u32 pllreq ; u8 suspended_fifos ; u32 maccontrol ; uint mac_suspend_depth ; u32 wake_override ; u32 mute_override ; u8 etheraddr[6U] ; bool noreset ; bool forcefastclk ; bool clk ; bool sbclk ; bool phyclk ; bool ucode_loaded ; u8 hw_stf_ss_opmode ; u8 antsel_type ; u32 antsel_avail ; }; struct ampdu_info; struct antsel_info; struct brcms_bss_cfg; struct brcms_c_info { struct brcms_pub *pub ; struct brcms_info *wl ; struct brcms_hardware *hw ; u16 fastpwrup_dly ; u32 macintstatus ; u32 macintmask ; u32 defmacintmask ; bool clk ; struct brcms_core *core ; struct brcms_band *band ; struct brcms_core *corestate ; struct brcms_band *bandstate[2U] ; uint qvalid ; struct ampdu_info *ampdu ; struct antsel_info *asi ; struct brcms_cm_info *cmi ; u16 vendorid ; u16 deviceid ; uint ucode_rev ; u8 perm_etheraddr[6U] ; bool bandlocked ; bool bandinit_pending ; bool radio_monitor ; bool going_down ; bool beacon_template_virgin ; struct brcms_timer *wdtimer ; struct brcms_timer *radio_timer ; uint filter_flags ; bool _rifs ; u8 bcn_li_bcn ; u8 bcn_li_dtim ; bool WDarmed ; u32 WDlast ; u16 edcf_txop[4U] ; u16 wme_retries[4U] ; struct brcms_bss_cfg *bsscfg ; struct modulecb *modulecb ; u8 mimoft ; s8 cck_40txbw ; s8 ofdm_40txbw ; s8 mimo_40txbw ; struct brcms_bss_info *default_bss ; u16 mc_fid_counter ; char country_default[4U] ; char autocountry_default[4U] ; u16 prb_resp_timeout ; u16 home_chanspec ; u16 chanspec ; u16 usr_fragthresh ; u16 fragthresh[6U] ; u16 RTSThresh ; u16 SRL ; u16 LRL ; u16 SFBL ; u16 LFBL ; bool shortslot ; s8 shortslot_override ; bool include_legacy_erp ; struct brcms_protection *protection ; s8 PLCPHdr_override ; struct brcms_stf *stf ; u32 bcn_rspec ; uint tempsense_lasttime ; u16 tx_duty_cycle_ofdm ; u16 tx_duty_cycle_cck ; struct wiphy *wiphy ; struct scb pri_scb ; struct sk_buff *beacon ; u16 beacon_tim_offset ; u16 beacon_dtim_period ; struct sk_buff *probe_resp ; }; struct antsel_info { struct brcms_c_info *wlc ; struct brcms_pub *pub ; u8 antsel_type ; u8 antsel_antswitch ; bool antsel_avail ; struct brcms_antselcfg antcfg_11n ; struct brcms_antselcfg antcfg_cur ; }; enum brcms_bss_type { BRCMS_TYPE_STATION = 0, BRCMS_TYPE_AP = 1, BRCMS_TYPE_ADHOC = 2 } ; struct brcms_bss_cfg { struct brcms_c_info *wlc ; enum brcms_bss_type type ; u8 SSID_len ; u8 SSID[32U] ; u8 BSSID[6U] ; struct brcms_bss_info *current_bss ; }; struct firmware_hdr { __le32 offset ; __le32 len ; __le32 idx ; }; typedef bool ldv_func_ret_type; typedef bool ldv_func_ret_type___0; typedef bool ldv_func_ret_type___1; typedef bool ldv_func_ret_type___2; typedef int ldv_func_ret_type___3; typedef struct ieee80211_hw *ldv_func_ret_type___4; typedef bool ldv_func_ret_type___5; typedef bool ldv_func_ret_type___6; struct paravirt_callee_save { void *func ; }; struct pv_irq_ops { struct paravirt_callee_save save_fl ; struct paravirt_callee_save restore_fl ; struct paravirt_callee_save irq_disable ; struct paravirt_callee_save irq_enable ; void (*safe_halt)(void) ; void (*halt)(void) ; void (*adjust_exception_frame)(void) ; }; struct static_key; typedef int pao_T__; typedef int pao_T_____0; struct static_key { atomic_t enabled ; }; enum hrtimer_restart; struct ieee80211_hdr { __le16 frame_control ; __le16 duration_id ; u8 addr1[6U] ; u8 addr2[6U] ; u8 addr3[6U] ; __le16 seq_ctrl ; u8 addr4[6U] ; }; struct ieee80211_rts { __le16 frame_control ; __le16 duration ; u8 ra[6U] ; u8 ta[6U] ; }; enum irqchip_irq_state; enum irqchip_irq_state; struct tx_status; enum txd_range { DMA_RANGE_ALL = 1, DMA_RANGE_TRANSMITTED = 2, DMA_RANGE_TRANSFERED = 3 } ; struct d11txh { __le16 MacTxControlLow ; __le16 MacTxControlHigh ; __le16 MacFrameControl ; __le16 TxFesTimeNormal ; __le16 PhyTxControlWord ; __le16 PhyTxControlWord_1 ; __le16 PhyTxControlWord_1_Fbr ; __le16 PhyTxControlWord_1_Rts ; __le16 PhyTxControlWord_1_FbrRts ; __le16 MainRates ; __le16 XtraFrameTypes ; u8 IV[16U] ; u8 TxFrameRA[6U] ; __le16 TxFesTimeFallback ; u8 RTSPLCPFallback[6U] ; __le16 RTSDurFallback ; u8 FragPLCPFallback[6U] ; __le16 FragDurFallback ; __le16 MModeLen ; __le16 MModeFbrLen ; __le16 TstampLow ; __le16 TstampHigh ; __le16 ABI_MimoAntSel ; __le16 PreloadSize ; __le16 AmpduSeqCtl ; __le16 TxFrameID ; __le16 TxStatus ; __le16 MaxNMpdus ; __le16 MaxABytes_MRT ; __le16 MaxABytes_FBR ; __le16 MinMBytes ; u8 RTSPhyHeader[6U] ; struct ieee80211_rts rts_frame ; u16 pad785 ; }; struct tx_status { u16 framelen ; u16 pad906 ; u16 frameid ; u16 status ; u16 lasttxtime ; u16 sequence ; u16 phyerr ; u16 ackphyrxsh ; }; struct brcms_mcs_info { u32 phy_rate_20 ; u32 phy_rate_40 ; u32 phy_rate_20_sgi ; u32 phy_rate_40_sgi ; u8 tx_phy_ctl3 ; u8 leg_ofdm ; }; struct brcms_ampdu_session { struct brcms_c_info *wlc ; struct sk_buff_head skb_list ; unsigned int max_ampdu_len ; u16 max_ampdu_frames ; u16 ampdu_len ; u16 dma_len ; }; struct tracepoint_func { void *func ; void *data ; }; struct tracepoint { char const *name ; struct static_key key ; void (*regfunc)(void) ; void (*unregfunc)(void) ; struct tracepoint_func *funcs ; }; struct trace_enum_map { char const *system ; char const *enum_string ; unsigned long enum_value ; }; union __anonunion___u_406 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_408 { struct tracepoint_func *__val ; char __c[1U] ; }; struct brcms_fifo_info { u16 ampdu_pld_size ; u8 mcs2ampdu_table[24U] ; u16 prev_txfunfl ; u32 accum_txfunfl ; u32 accum_txampdu ; u32 prev_txampdu ; u32 dmaxferrate ; }; struct ampdu_info { struct brcms_c_info *wlc ; int scb_handle ; u8 ini_enable[8U] ; u8 ba_tx_wsize ; u8 ba_rx_wsize ; u8 retry_limit ; u8 rr_retry_limit ; u8 retry_limit_tid[8U] ; u8 rr_retry_limit_tid[8U] ; u8 mpdu_density ; s8 max_pdu ; u8 dur ; u8 rx_factor ; u32 ffpld_rsvd ; u32 max_txlen[33U][2U][2U] ; bool mfbr ; u32 tx_max_funl ; struct brcms_fifo_info fifo_tb[4U] ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; struct txpwr_limits; struct txpwr_limits { u8 cck[4U] ; u8 ofdm[8U] ; u8 ofdm_cdd[8U] ; u8 ofdm_40_siso[8U] ; u8 ofdm_40_cdd[8U] ; u8 mcs_20_siso[8U] ; u8 mcs_20_cdd[8U] ; u8 mcs_20_stbc[8U] ; u8 mcs_20_mimo[8U] ; u8 mcs_40_siso[8U] ; u8 mcs_40_cdd[8U] ; u8 mcs_40_stbc[8U] ; u8 mcs_40_mimo[8U] ; u8 mcs32 ; }; struct brcms_chanvec { u8 vec[28U] ; }; struct locale_mimo_info { s8 maxpwr20[14U] ; s8 maxpwr40[14U] ; }; struct country_info { u8 const locale_mimo_2G ; u8 const locale_mimo_5G ; }; struct brcms_regd { struct country_info country ; struct ieee80211_regdomain const *regdomain ; }; struct brcms_cm_info { struct brcms_pub *pub ; struct brcms_c_info *wlc ; struct brcms_regd const *world_regd ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; enum skb_free_reason { SKB_REASON_CONSUMED = 0, SKB_REASON_DROPPED = 1 } ; struct ieee80211_rx_status; struct ieee80211_rx_status { u64 mactime ; u32 device_timestamp ; u32 ampdu_reference ; u32 flag ; u16 freq ; u8 vht_flag ; u8 rate_idx ; u8 vht_nss ; u8 rx_flags ; u8 band ; u8 antenna ; s8 signal ; u8 chains ; s8 chain_signal[4U] ; u8 ampdu_delimiter_crc ; }; enum bcma_clkmode { BCMA_CLKMODE_FAST = 0, BCMA_CLKMODE_DYNAMIC = 1 } ; struct d11rxhdr; struct si_pub { int ccrev ; u32 cccaps ; int pmurev ; u32 pmucaps ; uint boardtype ; uint boardvendor ; uint chip ; uint chiprev ; uint chippkg ; }; struct ofdm_phy_hdr { u8 rlpt[3U] ; u16 service ; u8 pad ; }; struct shm_acparams { u16 txop ; u16 cwmin ; u16 cwmax ; u16 cwcur ; u16 aifs ; u16 bslots ; u16 reggap ; u16 status ; u16 rsvd[8U] ; }; struct d11rxhdr_le { __le16 RxFrameSize ; u16 pad1388 ; __le16 PhyRxStatus_0 ; __le16 PhyRxStatus_1 ; __le16 PhyRxStatus_2 ; __le16 PhyRxStatus_3 ; __le16 PhyRxStatus_4 ; __le16 PhyRxStatus_5 ; __le16 RxStatus1 ; __le16 RxStatus2 ; __le16 RxTSFTime ; __le16 RxChan ; }; struct d11rxhdr { u16 RxFrameSize ; u16 pad1403 ; u16 PhyRxStatus_0 ; u16 PhyRxStatus_1 ; u16 PhyRxStatus_2 ; u16 PhyRxStatus_3 ; u16 PhyRxStatus_4 ; u16 PhyRxStatus_5 ; u16 RxStatus1 ; u16 RxStatus2 ; u16 RxTSFTime ; u16 RxChan ; }; struct shared_phy_params { struct si_pub *sih ; struct phy_shim_info *physhim ; uint unit ; uint corerev ; u16 vid ; u16 did ; uint chip ; uint chiprev ; uint chippkg ; uint sromrev ; uint boardtype ; uint boardrev ; u32 boardflags ; u32 boardflags2 ; }; union __anonunion___u_402 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_404 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_406___0 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_408___0 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_410 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_412 { struct tracepoint_func *__val ; char __c[1U] ; }; struct d11init { __le16 addr ; __le16 size ; __le32 value ; }; struct edcf_acparam { u8 ACI ; u8 ECW ; u16 TXOP ; }; struct plcp_signal_rate_lookup { u8 rate ; u8 signal_rate ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; struct phy_shim_info { struct brcms_hardware *wlc_hw ; struct brcms_c_info *wlc ; struct brcms_info *wl ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; struct si_info { struct si_pub pub ; struct bcma_bus *icbus ; struct pci_dev *pcibus ; u32 chipst ; }; struct cck_phy_hdr { u8 signal ; u8 service ; u16 length ; u16 crc ; }; struct legacy_phycfg { u32 rate_ofdm ; u8 tx_phy_ctl3 ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; struct tx_power { u32 flags ; u16 chanspec ; u16 local_chanspec ; u8 local_max ; u8 local_constraint ; s8 antgain[2U] ; u8 rf_cores ; u8 est_Pout[4U] ; u8 est_Pout_act[4U] ; u8 est_Pout_cck ; u8 tx_power_max[4U] ; u8 tx_power_max_rate_ind[4U] ; u8 user_limit[101U] ; u8 reg_limit[101U] ; u8 board_limit[101U] ; u8 target[101U] ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; struct phytbl_info { void const *tbl_ptr ; u32 tbl_len ; u32 tbl_id ; u32 tbl_offset ; u32 tbl_width ; }; struct lcnphy_cal_results { u16 txiqlocal_a ; u16 txiqlocal_b ; u16 txiqlocal_didq ; u8 txiqlocal_ei0 ; u8 txiqlocal_eq0 ; u8 txiqlocal_fi0 ; u8 txiqlocal_fq0 ; u16 txiqlocal_bestcoeffs[11U] ; u16 txiqlocal_bestcoeffs_valid ; u32 papd_eps_tbl[64U] ; u16 analog_gain_ref ; u16 lut_begin ; u16 lut_end ; u16 lut_step ; u16 rxcompdbm ; u16 papdctrl ; u16 sslpnCalibClkEnCtrl ; u16 rxiqcal_coeff_a0 ; u16 rxiqcal_coeff_b0 ; }; struct radio_regs { u16 address ; u32 init_a ; u32 init_g ; u8 do_init_a ; u8 do_init_g ; }; struct radio_20xx_regs { u16 address ; u8 init ; u8 do_init ; }; struct phy_iq_est { s32 iq_prod ; u32 i_pwr ; u32 q_pwr ; }; struct brcms_phy_lcnphy { int lcnphy_txrf_sp_9_override ; u8 lcnphy_full_cal_channel ; u8 lcnphy_cal_counter ; u16 lcnphy_cal_temper ; bool lcnphy_recal ; u8 lcnphy_rc_cap ; u32 lcnphy_mcs20_po ; u8 lcnphy_tr_isolation_mid ; u8 lcnphy_tr_isolation_low ; u8 lcnphy_tr_isolation_hi ; u8 lcnphy_bx_arch ; u8 lcnphy_rx_power_offset ; u8 lcnphy_rssi_vf ; u8 lcnphy_rssi_vc ; u8 lcnphy_rssi_gs ; u8 lcnphy_tssi_val ; u8 lcnphy_rssi_vf_lowtemp ; u8 lcnphy_rssi_vc_lowtemp ; u8 lcnphy_rssi_gs_lowtemp ; u8 lcnphy_rssi_vf_hightemp ; u8 lcnphy_rssi_vc_hightemp ; u8 lcnphy_rssi_gs_hightemp ; s16 lcnphy_pa0b0 ; s16 lcnphy_pa0b1 ; s16 lcnphy_pa0b2 ; u16 lcnphy_rawtempsense ; u8 lcnphy_measPower ; u8 lcnphy_tempsense_slope ; u8 lcnphy_freqoffset_corr ; u8 lcnphy_tempsense_option ; u8 lcnphy_tempcorrx ; bool lcnphy_iqcal_swp_dis ; bool lcnphy_hw_iqcal_en ; uint lcnphy_bandedge_corr ; bool lcnphy_spurmod ; u16 lcnphy_tssi_tx_cnt ; u16 lcnphy_tssi_idx ; u16 lcnphy_tssi_npt ; u16 lcnphy_target_tx_freq ; s8 lcnphy_tx_power_idx_override ; u16 lcnphy_noise_samples ; u32 lcnphy_papdRxGnIdx ; u32 lcnphy_papd_rxGnCtrl_init ; u32 lcnphy_gain_idx_14_lowword ; u32 lcnphy_gain_idx_14_hiword ; u32 lcnphy_gain_idx_27_lowword ; u32 lcnphy_gain_idx_27_hiword ; s16 lcnphy_ofdmgainidxtableoffset ; s16 lcnphy_dsssgainidxtableoffset ; u32 lcnphy_tr_R_gain_val ; u32 lcnphy_tr_T_gain_val ; s8 lcnphy_input_pwr_offset_db ; u16 lcnphy_Med_Low_Gain_db ; u16 lcnphy_Very_Low_Gain_db ; s8 lcnphy_lastsensed_temperature ; s8 lcnphy_pkteng_rssi_slope ; u8 lcnphy_saved_tx_user_target[101U] ; u8 lcnphy_volt_winner ; u8 lcnphy_volt_low ; u8 lcnphy_54_48_36_24mbps_backoff ; u8 lcnphy_11n_backoff ; u8 lcnphy_lowerofdm ; u8 lcnphy_cck ; u8 lcnphy_psat_2pt3_detected ; s32 lcnphy_lowest_Re_div_Im ; s8 lcnphy_final_papd_cal_idx ; u16 lcnphy_extstxctrl4 ; u16 lcnphy_extstxctrl0 ; u16 lcnphy_extstxctrl1 ; s16 lcnphy_cck_dig_filt_type ; s16 lcnphy_ofdm_dig_filt_type ; struct lcnphy_cal_results lcnphy_cal_results ; u8 lcnphy_psat_pwr ; u8 lcnphy_psat_indx ; s32 lcnphy_min_phase ; u8 lcnphy_final_idx ; u8 lcnphy_start_idx ; u8 lcnphy_current_index ; u16 lcnphy_logen_buf_1 ; u16 lcnphy_local_ovr_2 ; u16 lcnphy_local_oval_6 ; u16 lcnphy_local_oval_5 ; u16 lcnphy_logen_mixer_1 ; u8 lcnphy_aci_stat ; uint lcnphy_aci_start_time ; s8 lcnphy_tx_power_offset[101U] ; }; struct chan_info_basic { u16 chan ; u16 freq ; }; enum hrtimer_restart; struct cordic_iq { s32 i ; s32 q ; }; enum irqchip_irq_state; enum irqchip_irq_state; struct lcnphy_radio_regs { u16 address ; u8 init_a ; u8 init_g ; u8 do_init_a ; u8 do_init_g ; }; struct lcnphy_tx_gain_tbl_entry { unsigned char gm ; unsigned char pga ; unsigned char pad ; unsigned char dac ; unsigned char bb_mult ; }; struct lcnphy_txgains { u16 gm_gain ; u16 pga_gain ; u16 pad_gain ; u16 dac_gain ; }; enum lcnphy_cal_mode { LCNPHY_CAL_FULL = 0, LCNPHY_CAL_RECAL = 1, LCNPHY_CAL_CURRECAL = 2, LCNPHY_CAL_DIGCAL = 3, LCNPHY_CAL_GCTRL = 4 } ; struct lcnphy_rx_iqcomp { u8 chan ; s16 a ; s16 b ; }; struct lcnphy_spb_tone { s16 re ; s16 im ; }; struct lcnphy_unsign16_struct { u16 re ; u16 im ; }; struct lcnphy_iq_est { u32 iq_prod ; u32 i_pwr ; u32 q_pwr ; }; struct lcnphy_sfo_cfg { u16 ptcentreTs20 ; u16 ptcentreFactor ; }; typedef u16 iqcal_gain_params_lcnphy[9U]; struct chan_info_2064_lcnphy { uint chan ; uint freq ; u8 logen_buftune ; u8 logen_rccr_tx ; u8 txrf_mix_tune_ctrl ; u8 pa_input_tune_g ; u8 logen_rccr_rx ; u8 pa_rxrf_lna1_freq_tune ; u8 pa_rxrf_lna2_freq_tune ; u8 rxrf_rxrf_spare1 ; }; enum lcnphy_tssi_mode { LCNPHY_TSSI_PRE_PA = 0, LCNPHY_TSSI_POST_PA = 1, LCNPHY_TSSI_EXT = 2 } ; struct _ddebug { char const *modname ; char const *function ; char const *filename ; char const *format ; unsigned int lineno : 18 ; unsigned char flags ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; enum phy_cal_mode { CAL_FULL = 0, CAL_RECAL = 1, CAL_CURRECAL = 2, CAL_DIGCAL = 3, CAL_GCTRL = 4, CAL_SOFT = 5, CAL_DIGLO = 6 } ; struct nphy_iqcal_params { u16 txlpf ; u16 txgm ; u16 pga ; u16 pad ; u16 ipa ; u16 cal_gain ; u16 ncorr[5U] ; }; struct nphy_txiqcal_ladder { u8 percent ; u8 g_env ; }; struct nphy_ipa_txcalgains { struct nphy_txgains gains ; bool useindex ; u8 index ; }; struct nphy_papd_restore_state { u16 fbmix[2U] ; u16 vga_master[2U] ; u16 intpa_master[2U] ; u16 afectrl[2U] ; u16 afeoverride[2U] ; u16 pwrup[2U] ; u16 atten[2U] ; u16 mm ; }; struct nphy_ipa_txrxgain { u16 hpvga ; u16 lpf_biq1 ; u16 lpf_biq0 ; u16 lna2 ; u16 lna1 ; s8 txpwrindex ; }; struct chan_info_nphy_2055 { u16 chan ; u16 freq ; uint unknown ; u8 RF_pll_ref ; u8 RF_rf_pll_mod1 ; u8 RF_rf_pll_mod0 ; u8 RF_vco_cap_tail ; u8 RF_vco_cal1 ; u8 RF_vco_cal2 ; u8 RF_pll_lf_c1 ; u8 RF_pll_lf_r1 ; u8 RF_pll_lf_c2 ; u8 RF_lgbuf_cen_buf ; u8 RF_lgen_tune1 ; u8 RF_lgen_tune2 ; u8 RF_core1_lgbuf_a_tune ; u8 RF_core1_lgbuf_g_tune ; u8 RF_core1_rxrf_reg1 ; u8 RF_core1_tx_pga_pad_tn ; u8 RF_core1_tx_mx_bgtrim ; u8 RF_core2_lgbuf_a_tune ; u8 RF_core2_lgbuf_g_tune ; u8 RF_core2_rxrf_reg1 ; u8 RF_core2_tx_pga_pad_tn ; u8 RF_core2_tx_mx_bgtrim ; u16 PHY_BW1a ; u16 PHY_BW2 ; u16 PHY_BW3 ; u16 PHY_BW4 ; u16 PHY_BW5 ; u16 PHY_BW6 ; }; struct chan_info_nphy_radio205x { u16 chan ; u16 freq ; u8 RF_SYN_pll_vcocal1 ; u8 RF_SYN_pll_vcocal2 ; u8 RF_SYN_pll_refdiv ; u8 RF_SYN_pll_mmd2 ; u8 RF_SYN_pll_mmd1 ; u8 RF_SYN_pll_loopfilter1 ; u8 RF_SYN_pll_loopfilter2 ; u8 RF_SYN_pll_loopfilter3 ; u8 RF_SYN_pll_loopfilter4 ; u8 RF_SYN_pll_loopfilter5 ; u8 RF_SYN_reserved_addr27 ; u8 RF_SYN_reserved_addr28 ; u8 RF_SYN_reserved_addr29 ; u8 RF_SYN_logen_VCOBUF1 ; u8 RF_SYN_logen_MIXER2 ; u8 RF_SYN_logen_BUF3 ; u8 RF_SYN_logen_BUF4 ; u8 RF_RX0_lnaa_tune ; u8 RF_RX0_lnag_tune ; u8 RF_TX0_intpaa_boost_tune ; u8 RF_TX0_intpag_boost_tune ; u8 RF_TX0_pada_boost_tune ; u8 RF_TX0_padg_boost_tune ; u8 RF_TX0_pgaa_boost_tune ; u8 RF_TX0_pgag_boost_tune ; u8 RF_TX0_mixa_boost_tune ; u8 RF_TX0_mixg_boost_tune ; u8 RF_RX1_lnaa_tune ; u8 RF_RX1_lnag_tune ; u8 RF_TX1_intpaa_boost_tune ; u8 RF_TX1_intpag_boost_tune ; u8 RF_TX1_pada_boost_tune ; u8 RF_TX1_padg_boost_tune ; u8 RF_TX1_pgaa_boost_tune ; u8 RF_TX1_pgag_boost_tune ; u8 RF_TX1_mixa_boost_tune ; u8 RF_TX1_mixg_boost_tune ; u16 PHY_BW1a ; u16 PHY_BW2 ; u16 PHY_BW3 ; u16 PHY_BW4 ; u16 PHY_BW5 ; u16 PHY_BW6 ; }; struct chan_info_nphy_radio2057 { u16 chan ; u16 freq ; u8 RF_vcocal_countval0 ; u8 RF_vcocal_countval1 ; u8 RF_rfpll_refmaster_sparextalsize ; u8 RF_rfpll_loopfilter_r1 ; u8 RF_rfpll_loopfilter_c2 ; u8 RF_rfpll_loopfilter_c1 ; u8 RF_cp_kpd_idac ; u8 RF_rfpll_mmd0 ; u8 RF_rfpll_mmd1 ; u8 RF_vcobuf_tune ; u8 RF_logen_mx2g_tune ; u8 RF_logen_mx5g_tune ; u8 RF_logen_indbuf2g_tune ; u8 RF_logen_indbuf5g_tune ; u8 RF_txmix2g_tune_boost_pu_core0 ; u8 RF_pad2g_tune_pus_core0 ; u8 RF_pga_boost_tune_core0 ; u8 RF_txmix5g_boost_tune_core0 ; u8 RF_pad5g_tune_misc_pus_core0 ; u8 RF_lna2g_tune_core0 ; u8 RF_lna5g_tune_core0 ; u8 RF_txmix2g_tune_boost_pu_core1 ; u8 RF_pad2g_tune_pus_core1 ; u8 RF_pga_boost_tune_core1 ; u8 RF_txmix5g_boost_tune_core1 ; u8 RF_pad5g_tune_misc_pus_core1 ; u8 RF_lna2g_tune_core1 ; u8 RF_lna5g_tune_core1 ; u16 PHY_BW1a ; u16 PHY_BW2 ; u16 PHY_BW3 ; u16 PHY_BW4 ; u16 PHY_BW5 ; u16 PHY_BW6 ; }; struct chan_info_nphy_radio2057_rev5 { u16 chan ; u16 freq ; u8 RF_vcocal_countval0 ; u8 RF_vcocal_countval1 ; u8 RF_rfpll_refmaster_sparextalsize ; u8 RF_rfpll_loopfilter_r1 ; u8 RF_rfpll_loopfilter_c2 ; u8 RF_rfpll_loopfilter_c1 ; u8 RF_cp_kpd_idac ; u8 RF_rfpll_mmd0 ; u8 RF_rfpll_mmd1 ; u8 RF_vcobuf_tune ; u8 RF_logen_mx2g_tune ; u8 RF_logen_indbuf2g_tune ; u8 RF_txmix2g_tune_boost_pu_core0 ; u8 RF_pad2g_tune_pus_core0 ; u8 RF_lna2g_tune_core0 ; u8 RF_txmix2g_tune_boost_pu_core1 ; u8 RF_pad2g_tune_pus_core1 ; u8 RF_lna2g_tune_core1 ; u16 PHY_BW1a ; u16 PHY_BW2 ; u16 PHY_BW3 ; u16 PHY_BW4 ; u16 PHY_BW5 ; u16 PHY_BW6 ; }; struct nphy_sfo_cfg { u16 PHY_BW1a ; u16 PHY_BW2 ; u16 PHY_BW3 ; u16 PHY_BW4 ; u16 PHY_BW5 ; u16 PHY_BW6 ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; union __anonunion___u_414 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_416 { struct tracepoint_func *__val ; char __c[1U] ; }; struct dma64desc { __le32 ctrl1 ; __le32 ctrl2 ; __le32 addrlow ; __le32 addrhigh ; }; struct dma_info { struct dma_pub dma ; char name[8U] ; struct bcma_device *core ; struct device *dmadev ; struct brcms_ampdu_session ampdu_session ; bool dma64 ; bool addrext ; uint d64txregbase ; uint d64rxregbase ; struct dma64desc *txd64 ; struct dma64desc *rxd64 ; u16 dmadesc_align ; u16 ntxd ; u16 txin ; u16 txout ; struct sk_buff **txp ; dma_addr_t txdpa ; dma_addr_t txdpaorig ; u16 txdalign ; u32 txdalloc ; u32 xmtptrbase ; u16 nrxd ; u16 rxin ; u16 rxout ; struct sk_buff **rxp ; dma_addr_t rxdpa ; dma_addr_t rxdpaorig ; u16 rxdalign ; u32 rxdalloc ; u32 rcvptrbase ; unsigned int rxbufsize ; uint rxextrahdrroom ; uint nrxpost ; unsigned int rxoffset ; uint ddoffsetlow ; uint ddoffsethigh ; uint dataoffsetlow ; uint dataoffsethigh ; bool aligndesc_4k ; }; enum hrtimer_restart; struct pollfd { int fd ; short events ; short revents ; }; struct poll_table_struct { void (*_qproc)(struct file * , wait_queue_head_t * , struct poll_table_struct * ) ; unsigned long _key ; }; struct ring_buffer; struct ring_buffer_iter; struct trace_seq; struct seq_buf { char *buffer ; size_t size ; size_t len ; loff_t readpos ; }; struct trace_seq { unsigned char buffer[4096U] ; struct seq_buf seq ; int full ; }; union __anonunion____missing_field_name_262 { __u64 sample_period ; __u64 sample_freq ; }; union __anonunion____missing_field_name_263___0 { __u32 wakeup_events ; __u32 wakeup_watermark ; }; union __anonunion____missing_field_name_264 { __u64 bp_addr ; __u64 config1 ; }; union __anonunion____missing_field_name_265 { __u64 bp_len ; __u64 config2 ; }; struct perf_event_attr { __u32 type ; __u32 size ; __u64 config ; union __anonunion____missing_field_name_262 __annonCompField76 ; __u64 sample_type ; __u64 read_format ; unsigned char disabled : 1 ; unsigned char inherit : 1 ; unsigned char pinned : 1 ; unsigned char exclusive : 1 ; unsigned char exclude_user : 1 ; unsigned char exclude_kernel : 1 ; unsigned char exclude_hv : 1 ; unsigned char exclude_idle : 1 ; unsigned char mmap : 1 ; unsigned char comm : 1 ; unsigned char freq : 1 ; unsigned char inherit_stat : 1 ; unsigned char enable_on_exec : 1 ; unsigned char task : 1 ; unsigned char watermark : 1 ; unsigned char precise_ip : 2 ; unsigned char mmap_data : 1 ; unsigned char sample_id_all : 1 ; unsigned char exclude_host : 1 ; unsigned char exclude_guest : 1 ; unsigned char exclude_callchain_kernel : 1 ; unsigned char exclude_callchain_user : 1 ; unsigned char mmap2 : 1 ; unsigned char comm_exec : 1 ; unsigned char use_clockid : 1 ; unsigned long __reserved_1 : 38 ; union __anonunion____missing_field_name_263___0 __annonCompField77 ; __u32 bp_type ; union __anonunion____missing_field_name_264 __annonCompField78 ; union __anonunion____missing_field_name_265 __annonCompField79 ; __u64 branch_sample_type ; __u64 sample_regs_user ; __u32 sample_stack_user ; __s32 clockid ; __u64 sample_regs_intr ; __u32 aux_watermark ; __u32 __reserved_2 ; }; struct __anonstruct____missing_field_name_268 { unsigned char mem_op : 5 ; unsigned short mem_lvl : 14 ; unsigned char mem_snoop : 5 ; unsigned char mem_lock : 2 ; unsigned char mem_dtlb : 7 ; unsigned int mem_rsvd : 31 ; }; union perf_mem_data_src { __u64 val ; struct __anonstruct____missing_field_name_268 __annonCompField82 ; }; struct perf_branch_entry { __u64 from ; __u64 to ; unsigned char mispred : 1 ; unsigned char predicted : 1 ; unsigned char in_tx : 1 ; unsigned char abort : 1 ; unsigned long reserved : 60 ; }; struct pidmap { atomic_t nr_free ; void *page ; }; struct fs_pin; struct pid_namespace { struct kref kref ; struct pidmap pidmap[128U] ; struct callback_head rcu ; int last_pid ; unsigned int nr_hashed ; struct task_struct *child_reaper ; struct kmem_cache *pid_cachep ; unsigned int level ; struct pid_namespace *parent ; struct vfsmount *proc_mnt ; struct dentry *proc_self ; struct dentry *proc_thread_self ; struct fs_pin *bacct ; struct user_namespace *user_ns ; struct work_struct proc_work ; kgid_t pid_gid ; int hide_pid ; int reboot ; struct ns_common ns ; }; struct __anonstruct_local_t_276 { atomic_long_t a ; }; typedef struct __anonstruct_local_t_276 local_t; struct __anonstruct_local64_t_277 { local_t a ; }; typedef struct __anonstruct_local64_t_277 local64_t; struct arch_hw_breakpoint { unsigned long address ; unsigned long mask ; u8 len ; u8 type ; }; struct pmu; struct ftrace_hash; struct ftrace_ops; struct ftrace_ops_hash { struct ftrace_hash *notrace_hash ; struct ftrace_hash *filter_hash ; struct mutex regex_lock ; }; struct ftrace_ops { void (*func)(unsigned long , unsigned long , struct ftrace_ops * , struct pt_regs * ) ; struct ftrace_ops *next ; unsigned long flags ; void *private ; int *disabled ; int nr_trampolines ; struct ftrace_ops_hash local_hash ; struct ftrace_ops_hash *func_hash ; struct ftrace_ops_hash old_hash ; unsigned long trampoline ; unsigned long trampoline_size ; }; struct ftrace_ret_stack { unsigned long ret ; unsigned long func ; unsigned long long calltime ; unsigned long long subtime ; unsigned long fp ; }; struct irq_work { unsigned long flags ; struct llist_node llnode ; void (*func)(struct irq_work * ) ; }; struct perf_regs { __u64 abi ; struct pt_regs *regs ; }; struct perf_callchain_entry { __u64 nr ; __u64 ip[127U] ; }; struct perf_raw_record { u32 size ; void *data ; }; struct perf_branch_stack { __u64 nr ; struct perf_branch_entry entries[0U] ; }; struct hw_perf_event_extra { u64 config ; unsigned int reg ; int alloc ; int idx ; }; struct __anonstruct____missing_field_name_294 { u64 config ; u64 last_tag ; unsigned long config_base ; unsigned long event_base ; int event_base_rdpmc ; int idx ; int last_cpu ; int flags ; struct hw_perf_event_extra extra_reg ; struct hw_perf_event_extra branch_reg ; }; struct __anonstruct____missing_field_name_295 { struct hrtimer hrtimer ; }; struct __anonstruct____missing_field_name_296 { struct list_head tp_list ; }; struct __anonstruct____missing_field_name_297 { int cqm_state ; u32 cqm_rmid ; struct list_head cqm_events_entry ; struct list_head cqm_groups_entry ; struct list_head cqm_group_entry ; }; struct __anonstruct____missing_field_name_298 { int itrace_started ; }; struct __anonstruct____missing_field_name_299 { struct arch_hw_breakpoint info ; struct list_head bp_list ; }; union __anonunion____missing_field_name_293 { struct __anonstruct____missing_field_name_294 __annonCompField83 ; struct __anonstruct____missing_field_name_295 __annonCompField84 ; struct __anonstruct____missing_field_name_296 __annonCompField85 ; struct __anonstruct____missing_field_name_297 __annonCompField86 ; struct __anonstruct____missing_field_name_298 __annonCompField87 ; struct __anonstruct____missing_field_name_299 __annonCompField88 ; }; struct hw_perf_event { union __anonunion____missing_field_name_293 __annonCompField89 ; struct task_struct *target ; int state ; local64_t prev_count ; u64 sample_period ; u64 last_period ; local64_t period_left ; u64 interrupts_seq ; u64 interrupts ; u64 freq_time_stamp ; u64 freq_count_stamp ; }; struct perf_cpu_context; struct pmu { struct list_head entry ; struct module *module ; struct device *dev ; struct attribute_group const **attr_groups ; char const *name ; int type ; int capabilities ; int *pmu_disable_count ; struct perf_cpu_context *pmu_cpu_context ; atomic_t exclusive_cnt ; int task_ctx_nr ; int hrtimer_interval_ms ; void (*pmu_enable)(struct pmu * ) ; void (*pmu_disable)(struct pmu * ) ; int (*event_init)(struct perf_event * ) ; void (*event_mapped)(struct perf_event * ) ; void (*event_unmapped)(struct perf_event * ) ; int (*add)(struct perf_event * , int ) ; void (*del)(struct perf_event * , int ) ; void (*start)(struct perf_event * , int ) ; void (*stop)(struct perf_event * , int ) ; void (*read)(struct perf_event * ) ; void (*start_txn)(struct pmu * ) ; int (*commit_txn)(struct pmu * ) ; void (*cancel_txn)(struct pmu * ) ; int (*event_idx)(struct perf_event * ) ; void (*sched_task)(struct perf_event_context * , bool ) ; size_t task_ctx_size ; u64 (*count)(struct perf_event * ) ; void *(*setup_aux)(int , void ** , int , bool ) ; void (*free_aux)(void * ) ; int (*filter_match)(struct perf_event * ) ; }; enum perf_event_active_state { PERF_EVENT_STATE_EXIT = -3, PERF_EVENT_STATE_ERROR = -2, PERF_EVENT_STATE_OFF = -1, PERF_EVENT_STATE_INACTIVE = 0, PERF_EVENT_STATE_ACTIVE = 1 } ; struct perf_sample_data; struct perf_cgroup; struct event_filter; struct perf_event { struct list_head event_entry ; struct list_head group_entry ; struct list_head sibling_list ; struct list_head migrate_entry ; struct hlist_node hlist_entry ; struct list_head active_entry ; int nr_siblings ; int group_flags ; struct perf_event *group_leader ; struct pmu *pmu ; enum perf_event_active_state state ; unsigned int attach_state ; local64_t count ; atomic64_t child_count ; u64 total_time_enabled ; u64 total_time_running ; u64 tstamp_enabled ; u64 tstamp_running ; u64 tstamp_stopped ; u64 shadow_ctx_time ; struct perf_event_attr attr ; u16 header_size ; u16 id_header_size ; u16 read_size ; struct hw_perf_event hw ; struct perf_event_context *ctx ; atomic_long_t refcount ; atomic64_t child_total_time_enabled ; atomic64_t child_total_time_running ; struct mutex child_mutex ; struct list_head child_list ; struct perf_event *parent ; int oncpu ; int cpu ; struct list_head owner_entry ; struct task_struct *owner ; struct mutex mmap_mutex ; atomic_t mmap_count ; struct ring_buffer *rb ; struct list_head rb_entry ; unsigned long rcu_batches ; int rcu_pending ; wait_queue_head_t waitq ; struct fasync_struct *fasync ; int pending_wakeup ; int pending_kill ; int pending_disable ; struct irq_work pending ; atomic_t event_limit ; void (*destroy)(struct perf_event * ) ; struct callback_head callback_head ; struct pid_namespace *ns ; u64 id ; u64 (*clock)(void) ; void (*overflow_handler)(struct perf_event * , struct perf_sample_data * , struct pt_regs * ) ; void *overflow_handler_context ; struct trace_event_call *tp_event ; struct event_filter *filter ; struct ftrace_ops ftrace_ops ; struct perf_cgroup *cgrp ; int cgrp_defer_enabled ; }; struct perf_event_context { struct pmu *pmu ; raw_spinlock_t lock ; struct mutex mutex ; struct list_head active_ctx_list ; struct list_head pinned_groups ; struct list_head flexible_groups ; struct list_head event_list ; int nr_events ; int nr_active ; int is_active ; int nr_stat ; int nr_freq ; int rotate_disable ; atomic_t refcount ; struct task_struct *task ; u64 time ; u64 timestamp ; struct perf_event_context *parent_ctx ; u64 parent_gen ; u64 generation ; int pin_count ; int nr_cgroups ; void *task_ctx_data ; struct callback_head callback_head ; struct delayed_work orphans_remove ; bool orphans_remove_sched ; }; struct perf_cpu_context { struct perf_event_context ctx ; struct perf_event_context *task_ctx ; int active_oncpu ; int exclusive ; raw_spinlock_t hrtimer_lock ; struct hrtimer hrtimer ; ktime_t hrtimer_interval ; unsigned int hrtimer_active ; struct pmu *unique_pmu ; struct perf_cgroup *cgrp ; }; struct perf_cgroup_info { u64 time ; u64 timestamp ; }; struct perf_cgroup { struct cgroup_subsys_state css ; struct perf_cgroup_info *info ; }; struct __anonstruct_tid_entry_301 { u32 pid ; u32 tid ; }; struct __anonstruct_cpu_entry_302 { u32 cpu ; u32 reserved ; }; struct perf_sample_data { u64 addr ; struct perf_raw_record *raw ; struct perf_branch_stack *br_stack ; u64 period ; u64 weight ; u64 txn ; union perf_mem_data_src data_src ; u64 type ; u64 ip ; struct __anonstruct_tid_entry_301 tid_entry ; u64 time ; u64 id ; u64 stream_id ; struct __anonstruct_cpu_entry_302 cpu_entry ; struct perf_callchain_entry *callchain ; struct perf_regs regs_user ; struct pt_regs regs_user_copy ; struct perf_regs regs_intr ; u64 stack_user_size ; }; struct trace_array; struct trace_buffer; struct tracer; struct bpf_prog; struct trace_iterator; struct trace_event; struct trace_entry { unsigned short type ; unsigned char flags ; unsigned char preempt_count ; int pid ; }; struct trace_iterator { struct trace_array *tr ; struct tracer *trace ; struct trace_buffer *trace_buffer ; void *private ; int cpu_file ; struct mutex mutex ; struct ring_buffer_iter **buffer_iter ; unsigned long iter_flags ; struct trace_seq tmp_seq ; cpumask_var_t started ; bool snapshot ; struct trace_seq seq ; struct trace_entry *ent ; unsigned long lost_events ; int leftover ; int ent_size ; int cpu ; u64 ts ; loff_t pos ; long idx ; }; enum print_line_t; struct trace_event_functions { enum print_line_t (*trace)(struct trace_iterator * , int , struct trace_event * ) ; enum print_line_t (*raw)(struct trace_iterator * , int , struct trace_event * ) ; enum print_line_t (*hex)(struct trace_iterator * , int , struct trace_event * ) ; enum print_line_t (*binary)(struct trace_iterator * , int , struct trace_event * ) ; }; struct trace_event { struct hlist_node node ; struct list_head list ; int type ; struct trace_event_functions *funcs ; }; enum print_line_t { TRACE_TYPE_PARTIAL_LINE = 0, TRACE_TYPE_HANDLED = 1, TRACE_TYPE_UNHANDLED = 2, TRACE_TYPE_NO_CONSUME = 3 } ; enum trace_reg { TRACE_REG_REGISTER = 0, TRACE_REG_UNREGISTER = 1, TRACE_REG_PERF_REGISTER = 2, TRACE_REG_PERF_UNREGISTER = 3, TRACE_REG_PERF_OPEN = 4, TRACE_REG_PERF_CLOSE = 5, TRACE_REG_PERF_ADD = 6, TRACE_REG_PERF_DEL = 7 } ; struct trace_event_class { char const *system ; void *probe ; void *perf_probe ; int (*reg)(struct trace_event_call * , enum trace_reg , void * ) ; int (*define_fields)(struct trace_event_call * ) ; struct list_head *(*get_fields)(struct trace_event_call * ) ; struct list_head fields ; int (*raw_init)(struct trace_event_call * ) ; }; union __anonunion____missing_field_name_303 { char *name ; struct tracepoint *tp ; }; struct trace_event_call { struct list_head list ; struct trace_event_class *class ; union __anonunion____missing_field_name_303 __annonCompField91 ; struct trace_event event ; char *print_fmt ; struct event_filter *filter ; void *mod ; void *data ; int flags ; int perf_refcount ; struct hlist_head *perf_events ; struct bpf_prog *prog ; int (*perf_perm)(struct trace_event_call * , struct perf_event * ) ; }; struct trace_event_raw_brcms_timer { struct trace_entry ent ; uint ms ; uint set ; uint periodic ; char __data[0U] ; }; struct trace_event_raw_brcms_dpc { struct trace_entry ent ; unsigned long data ; char __data[0U] ; }; struct trace_event_raw_brcms_macintstatus { struct trace_entry ent ; u32 __data_loc_dev ; int in_isr ; u32 macintstatus ; u32 mask ; char __data[0U] ; }; struct trace_event_raw_brcms_txdesc { struct trace_entry ent ; u32 __data_loc_dev ; u32 __data_loc_txh ; char __data[0U] ; }; struct trace_event_raw_brcms_txstatus { struct trace_entry ent ; u32 __data_loc_dev ; u16 framelen ; u16 frameid ; u16 status ; u16 lasttxtime ; u16 sequence ; u16 phyerr ; u16 ackphyrxsh ; char __data[0U] ; }; struct trace_event_raw_brcms_ampdu_session { struct trace_entry ent ; u32 __data_loc_dev ; unsigned int max_ampdu_len ; u16 max_ampdu_frames ; u16 ampdu_len ; u16 ampdu_frames ; u16 dma_len ; char __data[0U] ; }; struct trace_event_raw_brcms_msg_event { struct trace_entry ent ; u32 __data_loc_msg ; char __data[0U] ; }; struct trace_event_raw_brcms_dbg { struct trace_entry ent ; u32 level ; u32 __data_loc_func ; u32 __data_loc_msg ; char __data[0U] ; }; struct va_list; typedef __builtin_va_list __gnuc_va_list; typedef __gnuc_va_list va_list; struct va_format { char const *fmt ; va_list *va ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; union __anonunion___u_418 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_420 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_422 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_424 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_426 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_428 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_430 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_432 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_434 { struct tracepoint_func *__val ; char __c[1U] ; }; union __anonunion___u_436 { struct tracepoint_func *__val ; char __c[1U] ; }; struct brcms_debugfs_entry { int (*read)(struct seq_file * , void * ) ; struct brcms_pub *drvr ; }; enum hrtimer_restart; enum irqchip_irq_state; enum irqchip_irq_state; __inline static long ldv__builtin_expect(long exp , long c ) ; extern struct module __this_module ; __inline static int test_and_set_bit(long nr , unsigned long volatile *addr ) { char c ; { __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; bts %2, %0; setc %1": "+m" (*addr), "=qm" (c): "Ir" (nr): "memory"); return ((int )((signed char )c) != 0); } } __inline static int no_printk(char const *fmt , ...) { { return (0); } } extern int printk(char const * , ...) ; extern void __might_sleep(char const * , int , int ) ; extern int sprintf(char * , char const * , ...) ; __inline static void INIT_LIST_HEAD(struct list_head *list ) { { list->next = list; list->prev = list; return; } } extern void warn_slowpath_null(char const * , int const ) ; extern void *memcpy(void * , void const * , size_t ) ; extern void *memset(void * , int , size_t ) ; extern void *kmemdup(void const * , size_t , gfp_t ) ; __inline static int atomic_read(atomic_t const *v ) { int __var ; { __var = 0; return ((int )*((int const volatile *)(& v->counter))); } } __inline static void atomic_set(atomic_t *v , int i ) { { v->counter = i; return; } } __inline static void atomic_inc(atomic_t *v ) { { __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; incl %0": "+m" (v->counter)); return; } } __inline static void atomic_dec(atomic_t *v ) { { __asm__ volatile (".pushsection .smp_locks,\"a\"\n.balign 4\n.long 671f - .\n.popsection\n671:\n\tlock; decl %0": "+m" (v->counter)); return; } } extern void lockdep_init_map(struct lockdep_map * , char const * , struct lock_class_key * , int ) ; extern void __raw_spin_lock_init(raw_spinlock_t * , char const * , struct lock_class_key * ) ; extern void _raw_spin_lock(raw_spinlock_t * ) ; extern void _raw_spin_lock_bh(raw_spinlock_t * ) ; extern unsigned long _raw_spin_lock_irqsave(raw_spinlock_t * ) ; extern void _raw_spin_unlock(raw_spinlock_t * ) ; extern void _raw_spin_unlock_bh(raw_spinlock_t * ) ; extern void _raw_spin_unlock_irqrestore(raw_spinlock_t * , unsigned long ) ; __inline static raw_spinlock_t *spinlock_check(spinlock_t *lock ) { { return (& lock->__annonCompField18.rlock); } } __inline static void spin_lock(spinlock_t *lock ) { { _raw_spin_lock(& lock->__annonCompField18.rlock); return; } } __inline static void spin_lock_bh(spinlock_t *lock ) { { _raw_spin_lock_bh(& lock->__annonCompField18.rlock); return; } } __inline static void spin_unlock(spinlock_t *lock ) { { _raw_spin_unlock(& lock->__annonCompField18.rlock); return; } } __inline static void spin_unlock_bh(spinlock_t *lock ) { { _raw_spin_unlock_bh(& lock->__annonCompField18.rlock); return; } } __inline static void spin_unlock_irqrestore(spinlock_t *lock , unsigned long flags ) { { _raw_spin_unlock_irqrestore(& lock->__annonCompField18.rlock, flags); return; } } extern void __init_waitqueue_head(wait_queue_head_t * , char const * , struct lock_class_key * ) ; extern void __wake_up(wait_queue_head_t * , unsigned int , int , void * ) ; extern long prepare_to_wait_event(wait_queue_head_t * , wait_queue_t * , int ) ; extern void finish_wait(wait_queue_head_t * , wait_queue_t * ) ; extern unsigned int jiffies_to_msecs(unsigned long const ) ; extern unsigned long __msecs_to_jiffies(unsigned int const ) ; __inline static unsigned long msecs_to_jiffies(unsigned int const m ) { unsigned long tmp___0 ; { tmp___0 = __msecs_to_jiffies(m); return (tmp___0); } } extern void init_timer_key(struct timer_list * , unsigned int , char const * , struct lock_class_key * ) ; extern void delayed_work_timer_fn(unsigned long ) ; extern void __init_work(struct work_struct * , int ) ; extern struct workqueue_struct *system_wq ; extern bool queue_work_on(int , struct workqueue_struct * , struct work_struct * ) ; bool ldv_queue_work_on_5(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_7(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; extern bool queue_delayed_work_on(int , struct workqueue_struct * , struct delayed_work * , unsigned long ) ; bool ldv_queue_delayed_work_on_6(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_9(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; extern void flush_workqueue(struct workqueue_struct * ) ; void ldv_flush_workqueue_8(struct workqueue_struct *ldv_func_arg1 ) ; extern bool cancel_work_sync(struct work_struct * ) ; bool ldv_cancel_work_sync_14(struct work_struct *ldv_func_arg1 ) ; extern bool cancel_delayed_work(struct delayed_work * ) ; bool ldv_cancel_delayed_work_15(struct delayed_work *ldv_func_arg1 ) ; __inline static bool queue_work(struct workqueue_struct *wq , struct work_struct *work ) { bool tmp ; { tmp = ldv_queue_work_on_5(8192, wq, work); return (tmp); } } __inline static bool schedule_work(struct work_struct *work ) { bool tmp ; { tmp = queue_work(system_wq, work); return (tmp); } } extern long schedule_timeout(long ) ; extern void schedule(void) ; extern void kfree(void const * ) ; extern void *__kmalloc(size_t , gfp_t ) ; __inline static void *kmalloc(size_t size , gfp_t flags ) { void *tmp___2 ; { tmp___2 = __kmalloc(size, flags); return (tmp___2); } } __inline static void *kzalloc(size_t size , gfp_t flags ) { void *tmp ; { tmp = kmalloc(size, flags | 32768U); return (tmp); } } extern void *malloc(size_t ) ; extern void *calloc(size_t , size_t ) ; extern int __VERIFIER_nondet_int(void) ; extern unsigned long __VERIFIER_nondet_ulong(void) ; extern void *__VERIFIER_nondet_pointer(void) ; extern void __VERIFIER_assume(int ) ; void *ldv_malloc(size_t size ) { void *p ; void *tmp ; int tmp___0 ; { tmp___0 = __VERIFIER_nondet_int(); if (tmp___0 != 0) { return ((void *)0); } else { tmp = malloc(size); p = tmp; __VERIFIER_assume((unsigned long )p != (unsigned long )((void *)0)); return (p); } } } void *ldv_zalloc(size_t size ) { void *p ; void *tmp ; int tmp___0 ; { tmp___0 = __VERIFIER_nondet_int(); if (tmp___0 != 0) { return ((void *)0); } else { tmp = calloc(1UL, size); p = tmp; __VERIFIER_assume((unsigned long )p != (unsigned long )((void *)0)); return (p); } } } void *ldv_init_zalloc(size_t size ) { void *p ; void *tmp ; { tmp = calloc(1UL, size); p = tmp; __VERIFIER_assume((unsigned long )p != (unsigned long )((void *)0)); return (p); } } void *ldv_memset(void *s , int c , size_t n ) { void *tmp ; { tmp = memset(s, c, n); return (tmp); } } int ldv_undef_int(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); return (tmp); } } void *ldv_undef_ptr(void) { void *tmp ; { tmp = __VERIFIER_nondet_pointer(); return (tmp); } } unsigned long ldv_undef_ulong(void) { unsigned long tmp ; { tmp = __VERIFIER_nondet_ulong(); return (tmp); } } __inline static void ldv_stop(void) { { LDV_STOP: ; goto LDV_STOP; } } __inline static long ldv__builtin_expect(long exp , long c ) { { return (exp); } } int ldv_state_variable_8 ; int ldv_state_variable_15 ; int ldv_state_variable_20 ; struct work_struct *ldv_work_struct_3_1 ; struct trace_event_call *event_class_brcms_ampdu_session_group0 ; struct trace_event_call *event_class_brcms_dbg_group0 ; struct trace_event_call *event_class_brcms_macintstatus_group0 ; int ldv_state_variable_0 ; int ldv_state_variable_21 ; int ldv_state_variable_5 ; int ldv_state_variable_13 ; int ldv_state_variable_12 ; int ldv_work_3_2 ; int ldv_state_variable_22 ; int ldv_state_variable_14 ; int ldv_work_3_0 ; int ldv_state_variable_17 ; struct work_struct *ldv_work_struct_2_3 ; struct work_struct *ldv_work_struct_2_0 ; int ldv_state_variable_19 ; int ldv_state_variable_9 ; struct work_struct *ldv_work_struct_2_2 ; int ref_cnt ; int ldv_irq_line_1_1 ; int ldv_work_3_3 ; int ldv_state_variable_1 ; int ldv_state_variable_7 ; struct trace_event_call *event_class_brcms_txdesc_group0 ; int ldv_irq_line_1_2 ; int ldv_state_variable_23 ; struct work_struct *ldv_work_struct_3_3 ; struct ieee80211_hw *brcms_ops_group0 ; struct bcma_device *brcms_bcma_driver_group0 ; int ldv_irq_1_3 = 0; void *ldv_irq_data_1_1 ; int ldv_state_variable_10 ; struct trace_event_call *event_class_brcms_msg_event_group0 ; int ldv_irq_1_0 = 0; struct work_struct *ldv_work_struct_2_1 ; struct work_struct *ldv_work_struct_3_2 ; void *ldv_irq_data_1_0 ; int ldv_state_variable_6 ; struct trace_event_call *event_class_brcms_txstatus_group0 ; int ldv_state_variable_16 ; int ldv_work_3_1 ; void *ldv_irq_data_1_3 ; int ldv_state_variable_2 ; int ldv_work_2_0 ; void *ldv_irq_data_1_2 ; struct work_struct *ldv_work_struct_3_0 ; int ldv_state_variable_11 ; int ldv_irq_1_2 = 0; int LDV_IN_INTERRUPT = 1; int ldv_irq_1_1 = 0; int ldv_state_variable_18 ; struct trace_event_call *event_class_brcms_timer_group0 ; struct trace_event_call *event_class_brcms_dpc_group0 ; int ldv_irq_line_1_3 ; int ldv_work_2_2 ; int ldv_state_variable_3 ; int ldv_irq_line_1_0 ; int ldv_work_2_3 ; int ldv_state_variable_4 ; struct file *brcms_debugfs_def_ops_group2 ; int ldv_work_2_1 ; struct inode *brcms_debugfs_def_ops_group1 ; void work_init_3(void) ; void ldv_initialize_trace_event_class_15(void) ; void ldv_initialize_trace_event_class_6(void) ; void work_init_2(void) ; void call_and_disable_all_2(int state ) ; int reg_check_1(irqreturn_t (*handler)(int , void * ) ) ; void activate_work_2(struct work_struct *work , int state ) ; void activate_work_3(struct work_struct *work , int state ) ; void ldv_initialize_bcma_driver_22(void) ; void ldv_initialize_trace_event_class_16(void) ; void ldv_initialize_trace_event_class_17(void) ; void ldv_initialize_trace_event_class_11(void) ; void ldv_initialize_trace_event_class_10(void) ; void choose_interrupt_1(void) ; void call_and_disable_work_3(struct work_struct *work ) ; void ldv_initialize_ieee80211_ops_23(void) ; void disable_work_3(struct work_struct *work ) ; void disable_work_2(struct work_struct *work ) ; void invoke_work_3(void) ; void disable_suitable_irq_1(int line , void *data ) ; int ldv_irq_1(int state , int line , void *data ) ; void activate_suitable_irq_1(int line , void *data ) ; void ldv_initialize_trace_event_class_9(void) ; void call_and_disable_all_3(int state ) ; void ldv_initialize_trace_event_class_5(void) ; void call_and_disable_work_2(struct work_struct *work ) ; void invoke_work_2(void) ; void ldv_file_operations_4(void) ; extern void dev_err(struct device const * , char const * , ...) ; extern void _dev_info(struct device const * , char const * , ...) ; extern void kfree_skb(struct sk_buff * ) ; extern void __const_udelay(unsigned long ) ; extern int request_threaded_irq(unsigned int , irqreturn_t (*)(int , void * ) , irqreturn_t (*)(int , void * ) , unsigned long , char const * , void * ) ; __inline static int request_irq(unsigned int irq , irqreturn_t (*handler)(int , void * ) , unsigned long flags , char const *name , void *dev ) { int tmp ; { tmp = request_threaded_irq(irq, handler, (irqreturn_t (*)(int , void * ))0, flags, name, dev); return (tmp); } } __inline static int ldv_request_irq_12(unsigned int irq , irqreturn_t (*handler)(int , void * ) , unsigned long flags , char const *name , void *dev ) ; extern void free_irq(unsigned int , void * ) ; void ldv_free_irq_10(unsigned int ldv_func_arg1 , void *ldv_func_arg2 ) ; extern void __tasklet_schedule(struct tasklet_struct * ) ; __inline static void tasklet_schedule(struct tasklet_struct *t ) { int tmp ; { tmp = test_and_set_bit(0L, (unsigned long volatile *)(& t->state)); if (tmp == 0) { __tasklet_schedule(t); } else { } return; } } extern void tasklet_kill(struct tasklet_struct * ) ; extern void tasklet_init(struct tasklet_struct * , void (*)(unsigned long ) , unsigned long ) ; __inline static bool is_zero_ether_addr(u8 const *addr ) { { return (((unsigned int )*((u32 const *)addr) | (unsigned int )*((u16 const *)addr + 4U)) == 0U); } } __inline static bool is_multicast_ether_addr(u8 const *addr ) { u32 a ; { a = *((u32 const *)addr); return ((a & 1U) != 0U); } } __inline static bool is_valid_ether_addr(u8 const *addr ) { bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; int tmp___3 ; { tmp = is_multicast_ether_addr(addr); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { tmp___1 = is_zero_ether_addr(addr); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { tmp___3 = 1; } else { tmp___3 = 0; } } else { tmp___3 = 0; } return ((bool )tmp___3); } } extern int request_firmware(struct firmware const ** , char const * , struct device * ) ; extern void release_firmware(struct firmware const * ) ; extern void bcma_core_pci_power_save(struct bcma_bus * , bool ) ; __inline static void *bcma_get_drvdata(struct bcma_device *core ) { { return (core->drvdata); } } __inline static void bcma_set_drvdata(struct bcma_device *core , void *drvdata ) { { core->drvdata = drvdata; return; } } extern int __bcma_driver_register(struct bcma_driver * , struct module * ) ; extern void bcma_driver_unregister(struct bcma_driver * ) ; __inline static void set_wiphy_dev(struct wiphy *wiphy , struct device *dev ) { { wiphy->dev.parent = dev; return; } } extern int regulatory_hint(struct wiphy * , char const * ) ; extern void wiphy_rfkill_set_hw_state(struct wiphy * , bool ) ; extern void wiphy_rfkill_start_polling(struct wiphy * ) ; extern void wiphy_rfkill_stop_polling(struct wiphy * ) ; __inline static struct ieee80211_tx_info *IEEE80211_SKB_CB(struct sk_buff *skb ) { { return ((struct ieee80211_tx_info *)(& skb->cb)); } } __inline static void _ieee80211_hw_set(struct ieee80211_hw *hw , enum ieee80211_hw_flags flg ) { { return; } } __inline static void SET_IEEE80211_DEV(struct ieee80211_hw *hw , struct device *dev ) { { set_wiphy_dev(hw->wiphy, dev); return; } } __inline static void SET_IEEE80211_PERM_ADDR(struct ieee80211_hw *hw , u8 *addr ) { { memcpy((void *)(& (hw->wiphy)->perm_addr), (void const *)addr, 6UL); return; } } extern struct ieee80211_hw *ieee80211_alloc_hw_nm(size_t , struct ieee80211_ops const * , char const * ) ; __inline static struct ieee80211_hw *ieee80211_alloc_hw(size_t priv_data_len , struct ieee80211_ops const *ops ) { struct ieee80211_hw *tmp ; { tmp = ieee80211_alloc_hw_nm(priv_data_len, ops, (char const *)0); return (tmp); } } __inline static struct ieee80211_hw *ldv_ieee80211_alloc_hw_13(size_t priv_data_len , struct ieee80211_ops const *ops ) ; extern int ieee80211_register_hw(struct ieee80211_hw * ) ; extern void ieee80211_unregister_hw(struct ieee80211_hw * ) ; extern void ieee80211_free_hw(struct ieee80211_hw * ) ; void ldv_ieee80211_free_hw_11(struct ieee80211_hw *ldv_func_arg1 ) ; extern void ieee80211_restart_hw(struct ieee80211_hw * ) ; extern struct sk_buff *ieee80211_beacon_get_tim(struct ieee80211_hw * , struct ieee80211_vif * , u16 * , u16 * ) ; extern struct sk_buff *ieee80211_proberesp_get(struct ieee80211_hw * , struct ieee80211_vif * ) ; extern void ieee80211_stop_queues(struct ieee80211_hw * ) ; extern void ieee80211_wake_queues(struct ieee80211_hw * ) ; extern void ieee80211_queue_delayed_work(struct ieee80211_hw * , struct delayed_work * , unsigned long ) ; extern void ieee80211_start_tx_ba_cb_irqsafe(struct ieee80211_vif * , u8 const * , u16 ) ; extern void ieee80211_stop_tx_ba_cb_irqsafe(struct ieee80211_vif * , u8 const * , u16 ) ; struct brcms_c_info *brcms_c_attach(struct brcms_info *wl , struct bcma_device *core , uint unit , bool piomode , uint *perr ) ; uint brcms_c_detach(struct brcms_c_info *wlc ) ; int brcms_c_up(struct brcms_c_info *wlc ) ; uint brcms_c_down(struct brcms_c_info *wlc ) ; bool brcms_c_chipmatch(struct bcma_device *core ) ; void brcms_c_init(struct brcms_c_info *wlc , bool mute_tx ) ; void brcms_c_reset(struct brcms_c_info *wlc ) ; void brcms_c_intrson(struct brcms_c_info *wlc ) ; u32 brcms_c_intrsoff(struct brcms_c_info *wlc ) ; void brcms_c_intrsrestore(struct brcms_c_info *wlc , u32 macintmask ) ; bool brcms_c_intrsupd(struct brcms_c_info *wlc ) ; bool brcms_c_isr(struct brcms_c_info *wlc ) ; bool brcms_c_dpc(struct brcms_c_info *wlc , bool bounded ) ; bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc , struct sk_buff *sdu , struct ieee80211_hw *hw ) ; bool brcms_c_aggregatable(struct brcms_c_info *wlc , u8 tid ) ; void brcms_c_protection_upd(struct brcms_c_info *wlc , uint idx , int val ) ; int brcms_c_get_header_len(void) ; void brcms_c_set_addrmatch(struct brcms_c_info *wlc , int match_reg_offset , u8 const *addr ) ; void brcms_c_wme_setparams(struct brcms_c_info *wlc , u16 aci , struct ieee80211_tx_queue_params const *params , bool suspend ) ; struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc ) ; void brcms_c_ampdu_flush(struct brcms_c_info *wlc , struct ieee80211_sta *sta , u16 tid ) ; void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc , u8 tid , u8 ba_wsize , uint max_rx_ampdu_bytes ) ; int brcms_c_module_register(struct brcms_pub *pub , char const *name , struct brcms_info *hdl , int (*d_fn)(void * ) ) ; int brcms_c_module_unregister(struct brcms_pub *pub , char const *name , struct brcms_info *hdl ) ; void brcms_c_associate_upd(struct brcms_c_info *wlc , bool state ) ; void brcms_c_scan_start(struct brcms_c_info *wlc ) ; void brcms_c_scan_stop(struct brcms_c_info *wlc ) ; int brcms_c_get_curband(struct brcms_c_info *wlc ) ; int brcms_c_set_channel(struct brcms_c_info *wlc , u16 channel ) ; int brcms_c_set_rate_limit(struct brcms_c_info *wlc , u16 srl , u16 lrl ) ; void brcms_c_get_current_rateset(struct brcms_c_info *wlc , struct brcm_rateset *currs ) ; int brcms_c_set_rateset(struct brcms_c_info *wlc , struct brcm_rateset *rs ) ; int brcms_c_set_beacon_period(struct brcms_c_info *wlc , u16 period ) ; u16 brcms_c_get_phy_type(struct brcms_c_info *wlc , int phyidx ) ; void brcms_c_set_shortslot_override(struct brcms_c_info *wlc , s8 sslot_override ) ; void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc , u8 interval ) ; u64 brcms_c_tsf_get(struct brcms_c_info *wlc ) ; void brcms_c_tsf_set(struct brcms_c_info *wlc , u64 tsf ) ; int brcms_c_set_tx_power(struct brcms_c_info *wlc , int txpwr ) ; int brcms_c_get_tx_power(struct brcms_c_info *wlc ) ; bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc ) ; void brcms_c_mute(struct brcms_c_info *wlc , bool mute_tx ) ; bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc ) ; void brcms_c_start_station(struct brcms_c_info *wlc , u8 *addr ) ; void brcms_c_start_ap(struct brcms_c_info *wlc , u8 *addr , u8 const *bssid , u8 *ssid , size_t ssid_len ) ; void brcms_c_start_adhoc(struct brcms_c_info *wlc , u8 *addr ) ; void brcms_c_set_new_beacon(struct brcms_c_info *wlc , struct sk_buff *beacon , u16 tim_offset , u16 dtim_period ) ; void brcms_c_set_new_probe_resp(struct brcms_c_info *wlc , struct sk_buff *probe_resp ) ; void brcms_c_enable_probe_resp(struct brcms_c_info *wlc , bool enable ) ; void brcms_c_set_ssid(struct brcms_c_info *wlc , u8 *ssid , size_t ssid_len ) ; void brcms_c_regd_init(struct brcms_c_info *wlc ) ; int brcms_ucode_data_init(struct brcms_info *wl , struct brcms_ucode *ucode ) ; void brcms_ucode_data_free(struct brcms_ucode *ucode ) ; int brcms_ucode_init_buf(struct brcms_info *wl , void **pbuf , unsigned int idx ) ; int brcms_ucode_init_uint(struct brcms_info *wl , size_t *n_bytes , unsigned int idx ) ; void brcms_ucode_free_buf(void *p ) ; int brcms_check_firmwares(struct brcms_info *wl ) ; void brcms_led_unregister(struct brcms_info *wl ) ; int brcms_led_register(struct brcms_info *wl ) ; void brcms_init(struct brcms_info *wl ) ; uint brcms_reset(struct brcms_info *wl ) ; void brcms_intrson(struct brcms_info *wl ) ; u32 brcms_intrsoff(struct brcms_info *wl ) ; void brcms_intrsrestore(struct brcms_info *wl , u32 macintmask ) ; int brcms_up(struct brcms_info *wl ) ; void brcms_down(struct brcms_info *wl ) ; void brcms_txflowcontrol(struct brcms_info *wl , struct brcms_if *wlif , bool state , int prio ) ; bool brcms_rfkill_set_hw_state(struct brcms_info *wl ) ; struct brcms_timer *brcms_init_timer(struct brcms_info *wl , void (*fn)(void * ) , void *arg , char const *name ) ; void brcms_free_timer(struct brcms_timer *t ) ; void brcms_add_timer(struct brcms_timer *t , uint ms , int periodic ) ; bool brcms_del_timer(struct brcms_timer *t ) ; void brcms_dpc(unsigned long data ) ; void brcms_fatal_error(struct brcms_info *wl ) ; void brcms_c_mac_promisc(struct brcms_c_info *wlc , uint filter_flags ) ; void brcms_c_init_scb(struct scb *scb ) ; void __brcms_err(struct device *dev , char const *fmt , ...) ; void __brcms_dbg(struct device *dev , u32 level , char const *func , char const *fmt , ...) ; void brcms_debugfs_init(void) ; void brcms_debugfs_exit(void) ; int brcms_debugfs_attach(struct brcms_pub *drvr ) ; void brcms_debugfs_detach(struct brcms_pub *drvr ) ; void brcms_debugfs_create_files(struct brcms_pub *drvr ) ; static char const * const brcms_firmwares[4U] = { "brcm/bcm43xx", (char const *)0}; static int n_adapters_found ; static struct bcma_device_id brcms_coreid_table[4U] = { {1215U, 2066U, 17U, 255U}, {1215U, 2066U, 23U, 255U}, {1215U, 2066U, 24U, 255U}}; struct bcma_device_id const __mod_bcma__brcms_coreid_table_device_table[4U] ; static struct ieee80211_channel brcms_2ghz_chantable[14U] = { {0, 2412U, 1U, 32U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2417U, 2U, 32U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2422U, 3U, 32U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2427U, 4U, 32U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2432U, 5U, 0U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2437U, 6U, 0U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2442U, 7U, 0U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2447U, 8U, 16U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2452U, 9U, 16U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2457U, 10U, 16U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2462U, 11U, 16U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2467U, 12U, 18U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2472U, 13U, 18U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {0, 2484U, 14U, 114U, 0, 19, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}}; static struct ieee80211_channel brcms_5ghz_nphy_chantable[24U] = { {1, 5180U, 36U, 32U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5200U, 40U, 16U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5220U, 44U, 32U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5240U, 48U, 16U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5260U, 52U, 42U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5280U, 56U, 26U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5300U, 60U, 42U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5320U, 64U, 26U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5500U, 100U, 42U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5520U, 104U, 26U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5540U, 108U, 42U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5560U, 112U, 26U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5580U, 116U, 42U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5600U, 120U, 26U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5620U, 124U, 42U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5640U, 128U, 26U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5660U, 132U, 42U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5680U, 136U, 26U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5700U, 140U, 58U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5745U, 149U, 32U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5765U, 153U, 16U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5785U, 157U, 32U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5805U, 161U, 16U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}, {1, 5825U, 165U, 48U, 0, 21, 0, (_Bool)0, 0U, 0, 0, 0, 0UL, 0U}}; static struct ieee80211_rate legacy_ratetable[12U] = { {0U, 10U, 2U, (unsigned short)0}, {1U, 20U, 4U, (unsigned short)0}, {1U, 55U, 11U, (unsigned short)0}, {1U, 110U, 22U, (unsigned short)0}, {0U, 60U, 12U, (unsigned short)0}, {0U, 90U, 18U, (unsigned short)0}, {0U, 120U, 24U, (unsigned short)0}, {0U, 180U, 36U, (unsigned short)0}, {0U, 240U, 48U, (unsigned short)0}, {0U, 360U, 72U, (unsigned short)0}, {0U, 480U, 96U, (unsigned short)0}, {0U, 540U, 108U, (unsigned short)0}}; static struct ieee80211_supported_band const brcms_band_2GHz_nphy_template = {(struct ieee80211_channel *)(& brcms_2ghz_chantable), (struct ieee80211_rate *)(& legacy_ratetable), 0, 14, 12, {112U, 1, 3U, 6U, {{255U, 255U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, 500U, 1U, {(unsigned char)0, (unsigned char)0, (unsigned char)0}}}, {(_Bool)0, 0U, {(unsigned short)0, (unsigned short)0, (unsigned short)0, (unsigned short)0}}}; static struct ieee80211_supported_band const brcms_band_5GHz_nphy_template = {(struct ieee80211_channel *)(& brcms_5ghz_nphy_chantable), (struct ieee80211_rate *)(& legacy_ratetable) + 4UL, 1, 24, 8, {112U, 1, 3U, 6U, {{255U, 255U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}, 500U, 1U, {(unsigned char)0, (unsigned char)0, (unsigned char)0}}}, {(_Bool)0, 0U, {(unsigned short)0, (unsigned short)0, (unsigned short)0, (unsigned short)0}}}; static void brcms_set_basic_rate(struct brcm_rateset *rs , u16 rate , bool is_br ) { u32 i ; { i = 0U; goto ldv_55622; ldv_55621: ; if ((int )rate != ((int )rs->rates[i] & 127)) { goto ldv_55620; } else { } if ((int )is_br) { rs->rates[i] = (u8 )((unsigned int )rs->rates[i] | 128U); } else { rs->rates[i] = (unsigned int )rs->rates[i] & 127U; } return; ldv_55620: i = i + 1U; ldv_55622: ; if (rs->count > i) { goto ldv_55621; } else { } return; } } static void brcms_free(struct brcms_info *wl ) { struct brcms_timer *t ; struct brcms_timer *next ; int tmp ; { if (wl->fw.fw_cnt != 0U) { brcms_ucode_data_free(& wl->ucode); } else { } if (wl->irq != 0) { ldv_free_irq_10((unsigned int )wl->irq, (void *)wl); } else { } tasklet_kill(& wl->tasklet); if ((unsigned long )wl->pub != (unsigned long )((struct brcms_pub *)0)) { brcms_debugfs_detach(wl->pub); brcms_c_module_unregister(wl->pub, "linux", wl); } else { } if ((unsigned long )wl->wlc != (unsigned long )((struct brcms_c_info *)0)) { brcms_c_detach(wl->wlc); wl->wlc = (struct brcms_c_info *)0; wl->pub = (struct brcms_pub *)0; } else { } goto ldv_55630; ldv_55629: schedule(); ldv_55630: tmp = atomic_read((atomic_t const *)(& wl->callbacks)); if (tmp > 0) { goto ldv_55629; } else { } t = wl->timers; goto ldv_55633; ldv_55632: next = t->next; kfree((void const *)t); t = next; ldv_55633: ; if ((unsigned long )t != (unsigned long )((struct brcms_timer *)0)) { goto ldv_55632; } else { } return; } } static void brcms_remove(struct bcma_device *pdev ) { struct ieee80211_hw *hw ; void *tmp ; struct brcms_info *wl ; { tmp = bcma_get_drvdata(pdev); hw = (struct ieee80211_hw *)tmp; wl = (struct brcms_info *)hw->priv; if ((unsigned long )wl->wlc != (unsigned long )((struct brcms_c_info *)0)) { brcms_led_unregister(wl); wiphy_rfkill_set_hw_state(((wl->pub)->ieee_hw)->wiphy, 0); wiphy_rfkill_stop_polling(((wl->pub)->ieee_hw)->wiphy); ieee80211_unregister_hw(hw); } else { } brcms_free(wl); bcma_set_drvdata(pdev, (void *)0); ldv_ieee80211_free_hw_11(hw); return; } } static void brcms_release_fw(struct brcms_info *wl ) { int i ; { i = 0; goto ldv_55645; ldv_55644: release_firmware(wl->fw.fw_bin[i]); release_firmware(wl->fw.fw_hdr[i]); i = i + 1; ldv_55645: ; if (i <= 3) { goto ldv_55644; } else { } return; } } static int brcms_request_fw(struct brcms_info *wl , struct bcma_device *pdev ) { int status ; struct device *device ; char fw_name[100U] ; int i ; { device = & pdev->dev; memset((void *)(& wl->fw), 0, 88UL); i = 0; goto ldv_55657; ldv_55656: ; if ((unsigned long )brcms_firmwares[i] == (unsigned long )((char const */* const */)0)) { goto ldv_55655; } else { } sprintf((char *)(& fw_name), "%s-%d.fw", brcms_firmwares[i], 0); status = request_firmware((struct firmware const **)(& wl->fw.fw_bin) + (unsigned long )i, (char const *)(& fw_name), device); if (status != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: fail to load firmware %s\n", (char *)"brcmsmac", (char *)(& fw_name)); return (status); } else { } sprintf((char *)(& fw_name), "%s_hdr-%d.fw", brcms_firmwares[i], 0); status = request_firmware((struct firmware const **)(& wl->fw.fw_hdr) + (unsigned long )i, (char const *)(& fw_name), device); if (status != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: fail to load firmware %s\n", (char *)"brcmsmac", (char *)(& fw_name)); return (status); } else { } wl->fw.hdr_num_entries[i] = (u32 )((unsigned long )(wl->fw.fw_hdr[i])->size / 12UL); i = i + 1; ldv_55657: ; if (i <= 3) { goto ldv_55656; } else { } ldv_55655: wl->fw.fw_cnt = (u32 )i; status = brcms_ucode_data_init(wl, & wl->ucode); brcms_release_fw(wl); return (status); } } static void brcms_ops_tx(struct ieee80211_hw *hw , struct ieee80211_tx_control *control , struct sk_buff *skb ) { struct brcms_info *wl ; struct ieee80211_tx_info *tx_info ; struct ieee80211_tx_info *tmp ; bool tmp___0 ; { wl = (struct brcms_info *)hw->priv; tmp = IEEE80211_SKB_CB(skb); tx_info = tmp; spin_lock_bh(& wl->lock); if (! (wl->pub)->up) { __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "ops->tx called while down\n"); kfree_skb(skb); goto done; } else { } tmp___0 = brcms_c_sendpkt_mac80211(wl->wlc, skb, hw); if ((int )tmp___0) { tx_info->__annonCompField103.__annonCompField102.rate_driver_data[0] = (void *)control->sta; } else { } done: spin_unlock_bh(& wl->lock); return; } } static int brcms_ops_start(struct ieee80211_hw *hw ) { struct brcms_info *wl ; bool blocked ; int err ; { wl = (struct brcms_info *)hw->priv; if ((unsigned long )wl->ucode.bcm43xx_bomminor == (unsigned long )((u32 *)0U)) { err = brcms_request_fw(wl, ((wl->wlc)->hw)->d11core); if (err != 0) { return (-2); } else { } } else { } ieee80211_wake_queues(hw); spin_lock_bh(& wl->lock); blocked = brcms_rfkill_set_hw_state(wl); spin_unlock_bh(& wl->lock); if (! blocked) { wiphy_rfkill_stop_polling(((wl->pub)->ieee_hw)->wiphy); } else { } spin_lock_bh(& wl->lock); wl->mute_tx = 1; if (! (wl->pub)->up) { if (! blocked) { err = brcms_up(wl); } else { err = -132; } } else { err = -19; } spin_unlock_bh(& wl->lock); if (err != 0) { __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "%s: brcms_up() returned %d\n", "brcms_ops_start", err); } else { } bcma_core_pci_power_save((((wl->wlc)->hw)->d11core)->bus, 1); return (err); } } static void brcms_ops_stop(struct ieee80211_hw *hw ) { struct brcms_info *wl ; int status ; bool tmp ; { wl = (struct brcms_info *)hw->priv; ieee80211_stop_queues(hw); if ((unsigned long )wl->wlc == (unsigned long )((struct brcms_c_info *)0)) { return; } else { } spin_lock_bh(& wl->lock); tmp = brcms_c_chipmatch(((wl->wlc)->hw)->d11core); status = (int )tmp; spin_unlock_bh(& wl->lock); if (status == 0) { __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "wl: brcms_ops_stop: chipmatch failed\n"); return; } else { } bcma_core_pci_power_save((((wl->wlc)->hw)->d11core)->bus, 0); spin_lock_bh(& wl->lock); brcms_down(wl); spin_unlock_bh(& wl->lock); return; } } static int brcms_ops_add_interface(struct ieee80211_hw *hw , struct ieee80211_vif *vif ) { struct brcms_info *wl ; { wl = (struct brcms_info *)hw->priv; if (((unsigned int )vif->type != 2U && (unsigned int )vif->type != 3U) && (unsigned int )vif->type != 1U) { __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "%s: Attempt to add type %d, only STA, AP and AdHoc for now\n", "brcms_ops_add_interface", (unsigned int )vif->type); return (-95); } else { } spin_lock_bh(& wl->lock); wl->mute_tx = 0; brcms_c_mute(wl->wlc, 0); if ((unsigned int )vif->type == 2U) { brcms_c_start_station(wl->wlc, (u8 *)(& vif->addr)); } else if ((unsigned int )vif->type == 3U) { brcms_c_start_ap(wl->wlc, (u8 *)(& vif->addr), vif->bss_conf.bssid, (u8 *)(& vif->bss_conf.ssid), vif->bss_conf.ssid_len); } else if ((unsigned int )vif->type == 1U) { brcms_c_start_adhoc(wl->wlc, (u8 *)(& vif->addr)); } else { } spin_unlock_bh(& wl->lock); return (0); } } static void brcms_ops_remove_interface(struct ieee80211_hw *hw , struct ieee80211_vif *vif ) { { return; } } static int brcms_ops_config(struct ieee80211_hw *hw , u32 changed ) { struct ieee80211_conf *conf ; struct brcms_info *wl ; struct bcma_device *core ; int err ; int new_int ; { conf = & hw->conf; wl = (struct brcms_info *)hw->priv; core = ((wl->wlc)->hw)->d11core; err = 0; spin_lock_bh(& wl->lock); if ((changed & 4U) != 0U) { brcms_c_set_beacon_listen_interval(wl->wlc, (int )((u8 )conf->listen_interval)); } else { } if ((changed & 8U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_ops_config", "%s: change monitor mode: %s\n", "brcms_ops_config", (int )conf->flags & 1 ? (char *)"true" : (char *)"false"); } else { } if ((changed & 16U) != 0U) { __brcms_err(& core->dev, "%s: change power-save mode: %s (implement)\n", "brcms_ops_config", (conf->flags & 2U) != 0U ? (char *)"true" : (char *)"false"); } else { } if ((changed & 32U) != 0U) { err = brcms_c_set_tx_power(wl->wlc, conf->power_level); if (err < 0) { __brcms_err(& core->dev, "%s: Error setting power_level\n", "brcms_ops_config"); goto config_out; } else { } new_int = brcms_c_get_tx_power(wl->wlc); if (conf->power_level != new_int) { __brcms_err(& core->dev, "%s: Power level req != actual, %d %d\n", "brcms_ops_config", conf->power_level, new_int); } else { } } else { } if ((changed & 64U) != 0U) { if ((unsigned int )conf->chandef.width == 1U || (unsigned int )conf->chandef.width == 0U) { err = brcms_c_set_channel(wl->wlc, (int )(conf->chandef.chan)->hw_value); } else { err = -524; } } else { } if ((changed & 128U) != 0U) { err = brcms_c_set_rate_limit(wl->wlc, (int )conf->short_frame_max_tx_count, (int )conf->long_frame_max_tx_count); } else { } config_out: spin_unlock_bh(& wl->lock); return (err); } } static void brcms_ops_bss_info_changed(struct ieee80211_hw *hw , struct ieee80211_vif *vif , struct ieee80211_bss_conf *info , u32 changed ) { struct brcms_info *wl ; struct bcma_device *core ; s8 val ; u16 mode ; struct ieee80211_supported_band *bi ; u32 br_mask ; u32 i ; u16 rate ; struct brcm_rateset rs ; int error ; int tmp ; struct sk_buff *beacon ; u16 tim_offset ; struct sk_buff *probe_resp ; { wl = (struct brcms_info *)hw->priv; core = ((wl->wlc)->hw)->d11core; if ((int )changed & 1) { __brcms_err(& core->dev, "%s: %s: %sassociated\n", (char *)"brcmsmac", "brcms_ops_bss_info_changed", (int )info->assoc ? (char *)"" : (char *)"dis"); spin_lock_bh(& wl->lock); brcms_c_associate_upd(wl->wlc, (int )info->assoc); spin_unlock_bh(& wl->lock); } else { } if ((changed & 8U) != 0U) { if ((int )info->use_short_slot) { val = 1; } else { val = 0; } spin_lock_bh(& wl->lock); brcms_c_set_shortslot_override(wl->wlc, (int )val); spin_unlock_bh(& wl->lock); } else { } if ((changed & 16U) != 0U) { mode = info->ht_operation_mode; spin_lock_bh(& wl->lock); brcms_c_protection_upd(wl->wlc, 11U, (int )mode & 3); brcms_c_protection_upd(wl->wlc, 13U, (int )mode & 4); brcms_c_protection_upd(wl->wlc, 16U, (int )mode & 16); spin_unlock_bh(& wl->lock); } else { } if ((changed & 32U) != 0U) { spin_lock_bh(& wl->lock); brcms_c_get_current_rateset(wl->wlc, & rs); spin_unlock_bh(& wl->lock); br_mask = info->basic_rates; tmp = brcms_c_get_curband(wl->wlc); bi = (hw->wiphy)->bands[tmp]; i = 0U; goto ldv_55717; ldv_55716: rate = (u16 )(((int )(bi->bitrates + (unsigned long )i)->bitrate << 1) / 10); brcms_set_basic_rate(& rs, (int )rate, (int )br_mask & 1); br_mask = br_mask >> 1; i = i + 1U; ldv_55717: ; if ((u32 )bi->n_bitrates > i) { goto ldv_55716; } else { } spin_lock_bh(& wl->lock); error = brcms_c_set_rateset(wl->wlc, & rs); spin_unlock_bh(& wl->lock); if (error != 0) { __brcms_err(& core->dev, "changing basic rates failed: %d\n", error); } else { } } else { } if ((changed & 64U) != 0U) { spin_lock_bh(& wl->lock); brcms_c_set_beacon_period(wl->wlc, (int )info->beacon_int); spin_unlock_bh(& wl->lock); } else { } if ((changed & 128U) != 0U) { spin_lock_bh(& wl->lock); brcms_c_set_addrmatch(wl->wlc, 3, info->bssid); spin_unlock_bh(& wl->lock); } else { } if ((changed & 32768U) != 0U) { spin_lock_bh(& wl->lock); brcms_c_set_ssid(wl->wlc, (u8 *)(& info->ssid), info->ssid_len); spin_unlock_bh(& wl->lock); } else { } if ((changed & 256U) != 0U) { tim_offset = 0U; spin_lock_bh(& wl->lock); beacon = ieee80211_beacon_get_tim(hw, vif, & tim_offset, (u16 *)0U); brcms_c_set_new_beacon(wl->wlc, beacon, (int )tim_offset, (int )info->dtim_period); spin_unlock_bh(& wl->lock); } else { } if ((changed & 65536U) != 0U) { spin_lock_bh(& wl->lock); probe_resp = ieee80211_proberesp_get(hw, vif); brcms_c_set_new_probe_resp(wl->wlc, probe_resp); spin_unlock_bh(& wl->lock); } else { } if ((changed & 512U) != 0U) { __brcms_err(& core->dev, "%s: Beacon enabled: %s\n", "brcms_ops_bss_info_changed", (int )info->enable_beacon ? (char *)"true" : (char *)"false"); if ((int )info->enable_beacon && ((hw->wiphy)->flags & 524288U) != 0U) { brcms_c_enable_probe_resp(wl->wlc, 1); } else { brcms_c_enable_probe_resp(wl->wlc, 0); } } else { } if ((changed & 1024U) != 0U) { __brcms_err(& core->dev, "%s: cqm change: threshold %d, hys %d (implement)\n", "brcms_ops_bss_info_changed", info->cqm_rssi_thold, info->cqm_rssi_hyst); } else { } if ((changed & 2048U) != 0U) { __brcms_err(& core->dev, "%s: IBSS joined: %s (implement)\n", "brcms_ops_bss_info_changed", (int )info->ibss_joined ? (char *)"true" : (char *)"false"); } else { } if ((changed & 4096U) != 0U) { __brcms_err(& core->dev, "%s: arp filtering: %d addresses (implement)\n", "brcms_ops_bss_info_changed", info->arp_addr_cnt); } else { } if ((changed & 8192U) != 0U) { __brcms_err(& core->dev, "%s: qos enabled: %s (implement)\n", "brcms_ops_bss_info_changed", (int )info->qos ? (char *)"true" : (char *)"false"); } else { } return; } } static void brcms_ops_configure_filter(struct ieee80211_hw *hw , unsigned int changed_flags , unsigned int *total_flags , u64 multicast ) { struct brcms_info *wl ; struct bcma_device *core ; { wl = (struct brcms_info *)hw->priv; core = ((wl->wlc)->hw)->d11core; changed_flags = changed_flags & 246U; *total_flags = *total_flags & 246U; if ((changed_flags & 2U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_ops_configure_filter", "FIF_ALLMULTI\n"); } else { } if ((changed_flags & 4U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_ops_configure_filter", "FIF_FCSFAIL\n"); } else { } if ((changed_flags & 32U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_ops_configure_filter", "FIF_CONTROL\n"); } else { } if ((changed_flags & 64U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_ops_configure_filter", "FIF_OTHER_BSS\n"); } else { } if ((changed_flags & 128U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_ops_configure_filter", "FIF_PSPOLL\n"); } else { } if ((changed_flags & 16U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_ops_configure_filter", "FIF_BCN_PRBRESP_PROMISC\n"); } else { } spin_lock_bh(& wl->lock); brcms_c_mac_promisc(wl->wlc, *total_flags); spin_unlock_bh(& wl->lock); return; } } static void brcms_ops_sw_scan_start(struct ieee80211_hw *hw , struct ieee80211_vif *vif , u8 const *mac_addr ) { struct brcms_info *wl ; { wl = (struct brcms_info *)hw->priv; spin_lock_bh(& wl->lock); brcms_c_scan_start(wl->wlc); spin_unlock_bh(& wl->lock); return; } } static void brcms_ops_sw_scan_complete(struct ieee80211_hw *hw , struct ieee80211_vif *vif ) { struct brcms_info *wl ; { wl = (struct brcms_info *)hw->priv; spin_lock_bh(& wl->lock); brcms_c_scan_stop(wl->wlc); spin_unlock_bh(& wl->lock); return; } } static int brcms_ops_conf_tx(struct ieee80211_hw *hw , struct ieee80211_vif *vif , u16 queue , struct ieee80211_tx_queue_params const *params ) { struct brcms_info *wl ; { wl = (struct brcms_info *)hw->priv; spin_lock_bh(& wl->lock); brcms_c_wme_setparams(wl->wlc, (int )queue, params, 1); spin_unlock_bh(& wl->lock); return (0); } } static int brcms_ops_sta_add(struct ieee80211_hw *hw , struct ieee80211_vif *vif , struct ieee80211_sta *sta ) { struct brcms_info *wl ; struct scb *scb ; { wl = (struct brcms_info *)hw->priv; scb = & (wl->wlc)->pri_scb; brcms_c_init_scb(scb); (wl->pub)->global_ampdu = & scb->scb_ampdu; ((wl->pub)->global_ampdu)->scb = scb; ((wl->pub)->global_ampdu)->max_pdu = 16U; return (0); } } static int brcms_ops_ampdu_action(struct ieee80211_hw *hw , struct ieee80211_vif *vif , enum ieee80211_ampdu_mlme_action action , struct ieee80211_sta *sta , u16 tid , u16 *ssn , u8 buf_size ) { struct brcms_info *wl ; struct scb *scb ; int status ; int __ret_warn_on ; long tmp ; long tmp___0 ; bool tmp___1 ; { wl = (struct brcms_info *)hw->priv; scb = & (wl->wlc)->pri_scb; __ret_warn_on = scb->magic != 3203386110U; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c", 829); } else { } tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { return (-43); } else { } switch ((unsigned int )action) { case 0U: ; goto ldv_55771; case 1U: ; goto ldv_55771; case 2U: spin_lock_bh(& wl->lock); tmp___1 = brcms_c_aggregatable(wl->wlc, (int )((u8 )tid)); status = (int )tmp___1; spin_unlock_bh(& wl->lock); if (status == 0) { __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "START: tid %d is not agg\'able\n", (int )tid); return (-22); } else { } ieee80211_start_tx_ba_cb_irqsafe(vif, (u8 const *)(& sta->addr), (int )tid); goto ldv_55771; case 3U: ; case 4U: ; case 5U: spin_lock_bh(& wl->lock); brcms_c_ampdu_flush(wl->wlc, sta, (int )tid); spin_unlock_bh(& wl->lock); ieee80211_stop_tx_ba_cb_irqsafe(vif, (u8 const *)(& sta->addr), (int )tid); goto ldv_55771; case 6U: spin_lock_bh(& wl->lock); brcms_c_ampdu_tx_operational(wl->wlc, (int )((u8 )tid), (int )buf_size, (uint )((1 << ((int )sta->ht_cap.ampdu_factor + 13)) + -1)); spin_unlock_bh(& wl->lock); goto ldv_55771; default: __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "%s: Invalid command, ignoring\n", "brcms_ops_ampdu_action"); } ldv_55771: ; return (0); } } static void brcms_ops_rfkill_poll(struct ieee80211_hw *hw ) { struct brcms_info *wl ; bool blocked ; { wl = (struct brcms_info *)hw->priv; spin_lock_bh(& wl->lock); blocked = brcms_c_check_radio_disabled(wl->wlc); spin_unlock_bh(& wl->lock); wiphy_rfkill_set_hw_state(((wl->pub)->ieee_hw)->wiphy, (int )blocked); return; } } static bool brcms_tx_flush_completed(struct brcms_info *wl ) { bool result ; { spin_lock_bh(& wl->lock); result = brcms_c_tx_flush_completed(wl->wlc); spin_unlock_bh(& wl->lock); return (result); } } static void brcms_ops_flush(struct ieee80211_hw *hw , struct ieee80211_vif *vif , u32 queues , bool drop ) { struct brcms_info *wl ; int ret ; long __ret ; unsigned long tmp ; wait_queue_t __wait ; long __ret___0 ; unsigned long tmp___0 ; long __int ; long tmp___1 ; bool __cond ; bool tmp___2 ; bool __cond___0 ; bool tmp___3 ; unsigned int tmp___4 ; { wl = (struct brcms_info *)hw->priv; no_printk("%s: drop = %s\n", "brcms_ops_flush", (int )drop ? (char *)"true" : (char *)"false"); tmp = msecs_to_jiffies(500U); __ret = (long )tmp; __might_sleep("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c", 910, 0); tmp___3 = brcms_tx_flush_completed(wl); __cond___0 = tmp___3; if ((int )__cond___0 && __ret == 0L) { __ret = 1L; } else { } if (((int )__cond___0 || __ret == 0L) == 0) { tmp___0 = msecs_to_jiffies(500U); __ret___0 = (long )tmp___0; INIT_LIST_HEAD(& __wait.task_list); __wait.flags = 0U; ldv_55808: tmp___1 = prepare_to_wait_event(& wl->tx_flush_wq, & __wait, 2); __int = tmp___1; tmp___2 = brcms_tx_flush_completed(wl); __cond = tmp___2; if ((int )__cond && __ret___0 == 0L) { __ret___0 = 1L; } else { } if (((int )__cond || __ret___0 == 0L) != 0) { goto ldv_55807; } else { } __ret___0 = schedule_timeout(__ret___0); goto ldv_55808; ldv_55807: finish_wait(& wl->tx_flush_wq, & __wait); __ret = __ret___0; } else { } ret = (int )__ret; tmp___4 = jiffies_to_msecs((unsigned long const )ret); __brcms_dbg(& (((wl->wlc)->hw)->d11core)->dev, 2U, "brcms_ops_flush", "ret=%d\n", tmp___4); return; } } static u64 brcms_ops_get_tsf(struct ieee80211_hw *hw , struct ieee80211_vif *vif ) { struct brcms_info *wl ; u64 tsf ; { wl = (struct brcms_info *)hw->priv; spin_lock_bh(& wl->lock); tsf = brcms_c_tsf_get(wl->wlc); spin_unlock_bh(& wl->lock); return (tsf); } } static void brcms_ops_set_tsf(struct ieee80211_hw *hw , struct ieee80211_vif *vif , u64 tsf ) { struct brcms_info *wl ; { wl = (struct brcms_info *)hw->priv; spin_lock_bh(& wl->lock); brcms_c_tsf_set(wl->wlc, tsf); spin_unlock_bh(& wl->lock); return; } } static struct ieee80211_ops const brcms_ops = {& brcms_ops_tx, & brcms_ops_start, & brcms_ops_stop, 0, 0, 0, & brcms_ops_add_interface, 0, & brcms_ops_remove_interface, & brcms_ops_config, & brcms_ops_bss_info_changed, 0, 0, 0, & brcms_ops_configure_filter, 0, 0, 0, 0, 0, 0, 0, 0, 0, & brcms_ops_sw_scan_start, & brcms_ops_sw_scan_complete, 0, 0, 0, 0, & brcms_ops_sta_add, 0, 0, 0, 0, 0, 0, 0, 0, 0, & brcms_ops_conf_tx, & brcms_ops_get_tsf, & brcms_ops_set_tsf, 0, 0, & brcms_ops_ampdu_action, 0, & brcms_ops_rfkill_poll, 0, 0, 0, & brcms_ops_flush, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; void brcms_dpc(unsigned long data ) { struct brcms_info *wl ; unsigned long flags ; raw_spinlock_t *tmp ; { wl = (struct brcms_info *)data; spin_lock_bh(& wl->lock); if ((int )(wl->pub)->up) { if ((int )wl->resched) { tmp = spinlock_check(& wl->isr_lock); flags = _raw_spin_lock_irqsave(tmp); brcms_c_intrsupd(wl->wlc); spin_unlock_irqrestore(& wl->isr_lock, flags); } else { } wl->resched = brcms_c_dpc(wl->wlc, 1); } else { } if (! (wl->pub)->up) { goto done; } else { } if ((int )wl->resched) { tasklet_schedule(& wl->tasklet); } else { brcms_intrson(wl); } done: spin_unlock_bh(& wl->lock); __wake_up(& wl->tx_flush_wq, 3U, 1, (void *)0); return; } } static irqreturn_t brcms_isr(int irq , void *dev_id ) { struct brcms_info *wl ; irqreturn_t ret ; bool tmp ; { ret = 0; wl = (struct brcms_info *)dev_id; spin_lock(& wl->isr_lock); tmp = brcms_c_isr(wl->wlc); if ((int )tmp) { tasklet_schedule(& wl->tasklet); ret = 1; } else { } spin_unlock(& wl->isr_lock); return (ret); } } static int ieee_hw_rate_init(struct ieee80211_hw *hw ) { struct brcms_info *wl ; struct brcms_c_info *wlc ; struct ieee80211_supported_band *band ; int has_5g ; u16 phy_type ; { wl = (struct brcms_info *)hw->priv; wlc = wl->wlc; has_5g = 0; (hw->wiphy)->bands[0] = (struct ieee80211_supported_band *)0; (hw->wiphy)->bands[1] = (struct ieee80211_supported_band *)0; phy_type = brcms_c_get_phy_type(wl->wlc, 0); if ((unsigned int )phy_type == 4U || (unsigned int )phy_type == 8U) { band = & (wlc->bandstate[0])->band; *band = brcms_band_2GHz_nphy_template; if ((unsigned int )phy_type == 8U) { band->ht_cap.mcs.rx_mask[1] = 0U; band->ht_cap.mcs.rx_highest = 72U; } else { } (hw->wiphy)->bands[0] = band; } else { return (-1); } if ((wl->pub)->_nbands > 1U) { has_5g = has_5g + 1; if ((unsigned int )phy_type == 4U || (unsigned int )phy_type == 8U) { band = & (wlc->bandstate[1])->band; *band = brcms_band_5GHz_nphy_template; (hw->wiphy)->bands[1] = band; } else { return (-1); } } else { } return (0); } } static int ieee_hw_init(struct ieee80211_hw *hw ) { int tmp ; int tmp___0 ; { _ieee80211_hw_set(hw, 7); _ieee80211_hw_set(hw, 4); _ieee80211_hw_set(hw, 16); tmp = brcms_c_get_header_len(); hw->extra_tx_headroom = (unsigned int )tmp; hw->queues = 4U; hw->max_rates = 2U; (hw->wiphy)->interface_modes = 14U; hw->rate_control_algorithm = "minstrel_ht"; hw->sta_data_size = 0; tmp___0 = ieee_hw_rate_init(hw); return (tmp___0); } } static struct brcms_info *brcms_attach(struct bcma_device *pdev ) { struct brcms_info *wl ; int unit ; int err ; struct ieee80211_hw *hw ; u8 perm[6U] ; void *tmp ; int __ret_warn_on ; long tmp___0 ; long tmp___1 ; int __ret_warn_on___0 ; long tmp___2 ; long tmp___3 ; struct lock_class_key __key ; struct lock_class_key __key___0 ; struct lock_class_key __key___1 ; int tmp___4 ; int tmp___5 ; int __ret_warn_on___1 ; bool tmp___6 ; int tmp___7 ; long tmp___8 ; long tmp___9 ; int tmp___10 ; { wl = (struct brcms_info *)0; unit = n_adapters_found; err = 0; if (unit < 0) { return ((struct brcms_info *)0); } else { } tmp = bcma_get_drvdata(pdev); hw = (struct ieee80211_hw *)tmp; if ((unsigned long )hw != (unsigned long )((struct ieee80211_hw *)0)) { wl = (struct brcms_info *)hw->priv; } else { } __ret_warn_on = (unsigned long )hw == (unsigned long )((struct ieee80211_hw *)0); tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c", 1114); } else { } tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { return ((struct brcms_info *)0); } else { __ret_warn_on___0 = (unsigned long )wl == (unsigned long )((struct brcms_info *)0); tmp___2 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___2 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c", 1114); } else { } tmp___3 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___3 != 0L) { return ((struct brcms_info *)0); } else { } } wl->wiphy = hw->wiphy; atomic_set(& wl->callbacks, 0); __init_waitqueue_head(& wl->tx_flush_wq, "&wl->tx_flush_wq", & __key); tasklet_init(& wl->tasklet, & brcms_dpc, (unsigned long )wl); spinlock_check(& wl->lock); __raw_spin_lock_init(& wl->lock.__annonCompField18.rlock, "&(&wl->lock)->rlock", & __key___0); spinlock_check(& wl->isr_lock); __raw_spin_lock_init(& wl->isr_lock.__annonCompField18.rlock, "&(&wl->isr_lock)->rlock", & __key___1); wl->wlc = brcms_c_attach(wl, pdev, (uint )unit, 0, (uint *)(& err)); if ((unsigned long )wl->wlc == (unsigned long )((struct brcms_c_info *)0)) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: attach() failed with code %d\n", (char *)"brcmsmac", err); goto fail; } else { } wl->pub = brcms_c_pub(wl->wlc); (wl->pub)->ieee_hw = hw; tmp___4 = ldv_request_irq_12(pdev->irq, & brcms_isr, 128UL, "brcmsmac", (void *)wl); if (tmp___4 != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "wl%d: request_irq() failed\n", unit); goto fail; } else { } wl->irq = (int )pdev->irq; brcms_c_module_register(wl->pub, "linux", wl, (int (*)(void * ))0); tmp___5 = ieee_hw_init(hw); if (tmp___5 != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "wl%d: %s: ieee_hw_init failed!\n", unit, "brcms_attach"); goto fail; } else { } brcms_c_regd_init(wl->wlc); memcpy((void *)(& perm), (void const *)(& (wl->pub)->cur_etheraddr), 6UL); tmp___6 = is_valid_ether_addr((u8 const *)(& perm)); if (tmp___6) { tmp___7 = 0; } else { tmp___7 = 1; } __ret_warn_on___1 = tmp___7; tmp___8 = ldv__builtin_expect(__ret_warn_on___1 != 0, 0L); if (tmp___8 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c", 1159); } else { } tmp___9 = ldv__builtin_expect(__ret_warn_on___1 != 0, 0L); if (tmp___9 != 0L) { goto fail; } else { } SET_IEEE80211_PERM_ADDR(hw, (u8 *)(& perm)); err = ieee80211_register_hw(hw); if (err != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: ieee80211_register_hw failed, status%d\n", "brcms_attach", err); } else { } if ((int )((signed char )(wl->pub)->srom_ccode[0]) != 0) { tmp___10 = regulatory_hint(wl->wiphy, (char const *)(& (wl->pub)->srom_ccode)); if (tmp___10 != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: regulatory hint failed\n", "brcms_attach"); } else { } } else { } brcms_debugfs_attach(wl->pub); brcms_debugfs_create_files(wl->pub); n_adapters_found = n_adapters_found + 1; return (wl); fail: brcms_free(wl); return ((struct brcms_info *)0); } } static int brcms_bcma_probe(struct bcma_device *pdev ) { struct brcms_info *wl ; struct ieee80211_hw *hw ; { _dev_info((struct device const *)(& pdev->dev), "mfg %x core %x rev %d class %d irq %d\n", (int )pdev->id.manuf, (int )pdev->id.id, (int )pdev->id.rev, (int )pdev->id.class, pdev->irq); if ((unsigned int )pdev->id.manuf != 1215U || (unsigned int )pdev->id.id != 2066U) { return (-19); } else { } hw = ldv_ieee80211_alloc_hw_13(1288UL, & brcms_ops); if ((unsigned long )hw == (unsigned long )((struct ieee80211_hw *)0)) { printk("\vbrcmsmac: %s: ieee80211_alloc_hw failed\n", "brcms_bcma_probe"); return (-12); } else { } SET_IEEE80211_DEV(hw, & pdev->dev); bcma_set_drvdata(pdev, (void *)hw); memset(hw->priv, 0, 1288UL); wl = brcms_attach(pdev); if ((unsigned long )wl == (unsigned long )((struct brcms_info *)0)) { printk("\vbrcmsmac: %s: brcms_attach failed!\n", "brcms_bcma_probe"); return (-19); } else { } brcms_led_register(wl); return (0); } } static int brcms_suspend(struct bcma_device *pdev ) { struct brcms_info *wl ; struct ieee80211_hw *hw ; void *tmp ; { tmp = bcma_get_drvdata(pdev); hw = (struct ieee80211_hw *)tmp; wl = (struct brcms_info *)hw->priv; if ((unsigned long )wl == (unsigned long )((struct brcms_info *)0)) { printk("\vbrcmsmac: %s: %s: no driver private struct!\n", (char *)"brcmsmac", "brcms_suspend"); return (-19); } else { } spin_lock_bh(& wl->lock); (wl->pub)->hw_up = 0; spin_unlock_bh(& wl->lock); __brcms_dbg(& (((wl->wlc)->hw)->d11core)->dev, 1U, "brcms_suspend", "brcms_suspend ok\n"); return (0); } } static int brcms_resume(struct bcma_device *pdev ) { { return (0); } } static struct bcma_driver brcms_bcma_driver = {"brcmsmac", (struct bcma_device_id const *)(& brcms_coreid_table), & brcms_bcma_probe, & brcms_remove, & brcms_suspend, & brcms_resume, 0, {0, 0, 0, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}; static void brcms_driver_init(struct work_struct *work ) { int error ; { error = __bcma_driver_register(& brcms_bcma_driver, & __this_module); if (error != 0) { printk("\vbrcmsmac: %s: register returned %d\n", "brcms_driver_init", error); } else { } return; } } static struct work_struct brcms_driver_work = {{137438953424L}, {& brcms_driver_work.entry, & brcms_driver_work.entry}, & brcms_driver_init, {(struct lock_class_key *)(& brcms_driver_work), {0, 0}, "brcms_driver_work", 0, 0UL}}; static int brcms_module_init(void) { bool tmp ; int tmp___0 ; { brcms_debugfs_init(); tmp = schedule_work(& brcms_driver_work); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (-16); } else { } return (0); } } static void brcms_module_exit(void) { { ldv_cancel_work_sync_14(& brcms_driver_work); bcma_driver_unregister(& brcms_bcma_driver); brcms_debugfs_exit(); return; } } void brcms_txflowcontrol(struct brcms_info *wl , struct brcms_if *wlif , bool state , int prio ) { { __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "Shouldn\'t be here %s\n", "brcms_txflowcontrol"); return; } } void brcms_init(struct brcms_info *wl ) { { __brcms_dbg(& (((wl->wlc)->hw)->d11core)->dev, 1U, "brcms_init", "Initializing wl%d\n", (wl->pub)->unit); brcms_reset(wl); brcms_c_init(wl->wlc, (int )wl->mute_tx); return; } } uint brcms_reset(struct brcms_info *wl ) { { __brcms_dbg(& (((wl->wlc)->hw)->d11core)->dev, 1U, "brcms_reset", "Resetting wl%d\n", (wl->pub)->unit); brcms_c_reset(wl->wlc); wl->resched = 0; (wl->pub)->up = 0; return (0U); } } void brcms_fatal_error(struct brcms_info *wl ) { { __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "wl%d: fatal error, reinitializing\n", ((wl->wlc)->pub)->unit); brcms_reset(wl); ieee80211_restart_hw((wl->pub)->ieee_hw); return; } } void brcms_intrson(struct brcms_info *wl ) { unsigned long flags ; raw_spinlock_t *tmp ; { tmp = spinlock_check(& wl->isr_lock); flags = _raw_spin_lock_irqsave(tmp); brcms_c_intrson(wl->wlc); spin_unlock_irqrestore(& wl->isr_lock, flags); return; } } u32 brcms_intrsoff(struct brcms_info *wl ) { unsigned long flags ; u32 status ; raw_spinlock_t *tmp ; { tmp = spinlock_check(& wl->isr_lock); flags = _raw_spin_lock_irqsave(tmp); status = brcms_c_intrsoff(wl->wlc); spin_unlock_irqrestore(& wl->isr_lock, flags); return (status); } } void brcms_intrsrestore(struct brcms_info *wl , u32 macintmask ) { unsigned long flags ; raw_spinlock_t *tmp ; { tmp = spinlock_check(& wl->isr_lock); flags = _raw_spin_lock_irqsave(tmp); brcms_c_intrsrestore(wl->wlc, macintmask); spin_unlock_irqrestore(& wl->isr_lock, flags); return; } } int brcms_up(struct brcms_info *wl ) { int error ; { error = 0; if ((int )(wl->pub)->up) { return (0); } else { } error = brcms_c_up(wl->wlc); return (error); } } void brcms_down(struct brcms_info *wl ) { uint callbacks ; uint ret_val ; int tmp ; uint countdown ; int tmp___0 ; { ret_val = 0U; ret_val = brcms_c_down(wl->wlc); tmp = atomic_read((atomic_t const *)(& wl->callbacks)); callbacks = (uint )tmp - ret_val; spin_unlock_bh(& wl->lock); countdown = 100009U; goto ldv_55959; ldv_55958: __const_udelay(42950UL); countdown = countdown - 10U; ldv_55959: tmp___0 = atomic_read((atomic_t const *)(& wl->callbacks)); if ((uint )tmp___0 > callbacks && countdown > 9U) { goto ldv_55958; } else { } spin_lock_bh(& wl->lock); return; } } static void _brcms_timer(struct work_struct *work ) { struct brcms_timer *t ; struct work_struct const *__mptr ; unsigned long tmp ; { __mptr = (struct work_struct const *)work; t = (struct brcms_timer *)__mptr; spin_lock_bh(& (t->wl)->lock); if ((int )t->set) { if ((int )t->periodic) { atomic_inc(& (t->wl)->callbacks); tmp = msecs_to_jiffies(t->ms); ieee80211_queue_delayed_work(((t->wl)->pub)->ieee_hw, & t->dly_wrk, tmp); } else { t->set = 0; } (*(t->fn))(t->arg); } else { } atomic_dec(& (t->wl)->callbacks); spin_unlock_bh(& (t->wl)->lock); return; } } struct brcms_timer *brcms_init_timer(struct brcms_info *wl , void (*fn)(void * ) , void *arg , char const *name ) { struct brcms_timer *t ; void *tmp ; struct lock_class_key __key ; atomic_long_t __constr_expr_0 ; struct lock_class_key __key___0 ; { tmp = kzalloc(264UL, 32U); t = (struct brcms_timer *)tmp; if ((unsigned long )t == (unsigned long )((struct brcms_timer *)0)) { return ((struct brcms_timer *)0); } else { } __init_work(& t->dly_wrk.work, 0); __constr_expr_0.counter = 137438953408L; t->dly_wrk.work.data = __constr_expr_0; lockdep_init_map(& t->dly_wrk.work.lockdep_map, "(&(&t->dly_wrk)->work)", & __key, 0); INIT_LIST_HEAD(& t->dly_wrk.work.entry); t->dly_wrk.work.func = & _brcms_timer; init_timer_key(& t->dly_wrk.timer, 2097152U, "(&(&t->dly_wrk)->timer)", & __key___0); t->dly_wrk.timer.function = & delayed_work_timer_fn; t->dly_wrk.timer.data = (unsigned long )(& t->dly_wrk); t->wl = wl; t->fn = fn; t->arg = arg; t->next = wl->timers; wl->timers = t; return (t); } } void brcms_add_timer(struct brcms_timer *t , uint ms , int periodic ) { struct ieee80211_hw *hw ; unsigned long tmp ; { hw = ((t->wl)->pub)->ieee_hw; t->ms = ms; t->periodic = periodic != 0; if (! t->set) { t->set = 1; atomic_inc(& (t->wl)->callbacks); } else { } tmp = msecs_to_jiffies(ms); ieee80211_queue_delayed_work(hw, & t->dly_wrk, tmp); return; } } bool brcms_del_timer(struct brcms_timer *t ) { bool tmp ; int tmp___0 ; { if ((int )t->set) { t->set = 0; tmp = ldv_cancel_delayed_work_15(& t->dly_wrk); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } atomic_dec(& (t->wl)->callbacks); } else { } return (1); } } void brcms_free_timer(struct brcms_timer *t ) { struct brcms_info *wl ; struct brcms_timer *tmp ; { wl = t->wl; brcms_del_timer(t); if ((unsigned long )wl->timers == (unsigned long )t) { wl->timers = (wl->timers)->next; kfree((void const *)t); return; } else { } tmp = wl->timers; goto ldv_55993; ldv_55992: ; if ((unsigned long )tmp->next == (unsigned long )t) { tmp->next = t->next; kfree((void const *)t); return; } else { } tmp = tmp->next; ldv_55993: ; if ((unsigned long )tmp != (unsigned long )((struct brcms_timer *)0)) { goto ldv_55992; } else { } return; } } int brcms_ucode_init_buf(struct brcms_info *wl , void **pbuf , unsigned int idx ) { int i ; int entry ; u8 const *pdata ; struct firmware_hdr *hdr ; u32 len ; { i = 0; goto ldv_56010; ldv_56009: hdr = (struct firmware_hdr *)(wl->fw.fw_hdr[i])->data; entry = 0; goto ldv_56007; ldv_56006: len = hdr->len; if (hdr->idx == idx) { pdata = (wl->fw.fw_bin[i])->data + (unsigned long )hdr->offset; *pbuf = kmemdup((void const *)pdata, (size_t )len, 32U); if ((unsigned long )*pbuf == (unsigned long )((void *)0)) { goto fail; } else { } return (0); } else { } entry = entry + 1; hdr = hdr + 1; ldv_56007: ; if ((u32 )entry < wl->fw.hdr_num_entries[i]) { goto ldv_56006; } else { } i = i + 1; ldv_56010: ; if ((u32 )i < wl->fw.fw_cnt) { goto ldv_56009; } else { } __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "OLD_ERROR: ucode buf tag:%d can not be found!\n", idx); *pbuf = (void *)0; fail: ; return (-61); } } int brcms_ucode_init_uint(struct brcms_info *wl , size_t *n_bytes , unsigned int idx ) { int i ; int entry ; u8 const *pdata ; struct firmware_hdr *hdr ; { i = 0; goto ldv_56025; ldv_56024: hdr = (struct firmware_hdr *)(wl->fw.fw_hdr[i])->data; entry = 0; goto ldv_56022; ldv_56021: ; if (hdr->idx == idx) { pdata = (wl->fw.fw_bin[i])->data + (unsigned long )hdr->offset; if (hdr->len != 4U) { __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "OLD_ERROR: fw hdr len\n"); return (-42); } else { } *n_bytes = (size_t )*((__le32 *)pdata); return (0); } else { } entry = entry + 1; hdr = hdr + 1; ldv_56022: ; if ((u32 )entry < wl->fw.hdr_num_entries[i]) { goto ldv_56021; } else { } i = i + 1; ldv_56025: ; if ((u32 )i < wl->fw.fw_cnt) { goto ldv_56024; } else { } __brcms_err(& (((wl->wlc)->hw)->d11core)->dev, "OLD_ERROR: ucode tag:%d can not be found!\n", idx); return (-42); } } void brcms_ucode_free_buf(void *p ) { { kfree((void const *)p); return; } } int brcms_check_firmwares(struct brcms_info *wl ) { int i ; int entry ; int rc ; struct firmware const *fw ; struct firmware const *fw_hdr ; struct firmware_hdr *ucode_hdr ; { rc = 0; i = 0; goto ldv_56045; ldv_56044: fw = wl->fw.fw_bin[i]; fw_hdr = wl->fw.fw_hdr[i]; if ((unsigned long )fw == (unsigned long )((struct firmware const *)0) && (unsigned long )fw_hdr == (unsigned long )((struct firmware const *)0)) { goto ldv_56039; } else if ((unsigned long )fw == (unsigned long )((struct firmware const *)0) || (unsigned long )fw_hdr == (unsigned long )((struct firmware const *)0)) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: invalid bin/hdr fw\n", "brcms_check_firmwares"); rc = -9; } else if ((unsigned long )fw_hdr->size % 12UL != 0UL) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: non integral fw hdr file size %zu/%zu\n", "brcms_check_firmwares", fw_hdr->size, 12UL); rc = -9; } else if ((unsigned long )fw->size <= 39999UL || (unsigned long )fw->size > 150000UL) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: out of bounds fw file size %zu\n", "brcms_check_firmwares", fw->size); rc = -9; } else { ucode_hdr = (struct firmware_hdr *)fw_hdr->data; entry = 0; goto ldv_56042; ldv_56041: ; if ((unsigned long )(ucode_hdr->offset + ucode_hdr->len) > (unsigned long )fw->size) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: conflicting bin/hdr\n", "brcms_check_firmwares"); rc = -9; } else { } entry = entry + 1; ucode_hdr = ucode_hdr + 1; ldv_56042: ; if ((u32 )entry < wl->fw.hdr_num_entries[i] && rc == 0) { goto ldv_56041; } else { } } i = i + 1; ldv_56045: ; if (i <= 3 && rc == 0) { goto ldv_56044; } else { } ldv_56039: ; if (rc == 0 && wl->fw.fw_cnt != (u32 )i) { dev_err((struct device const *)(& (wl->wiphy)->dev), "%s: invalid fw_cnt=%d\n", "brcms_check_firmwares", wl->fw.fw_cnt); rc = -9; } else { } return (rc); } } bool brcms_rfkill_set_hw_state(struct brcms_info *wl ) { bool blocked ; bool tmp ; { tmp = brcms_c_check_radio_disabled(wl->wlc); blocked = tmp; spin_unlock_bh(& wl->lock); wiphy_rfkill_set_hw_state(((wl->pub)->ieee_hw)->wiphy, (int )blocked); if ((int )blocked) { wiphy_rfkill_start_polling(((wl->pub)->ieee_hw)->wiphy); } else { } spin_lock_bh(& wl->lock); return (blocked); } } int ldv_retval_0 ; int ldv_retval_4 ; int ldv_retval_1 ; extern void ldv_initialize(void) ; void ldv_check_final_state(void) ; int ldv_retval_3 ; int ldv_retval_2 ; void work_init_3(void) { { ldv_work_3_0 = 0; ldv_work_3_1 = 0; ldv_work_3_2 = 0; ldv_work_3_3 = 0; return; } } void work_init_2(void) { { ldv_work_2_0 = 0; ldv_work_2_1 = 0; ldv_work_2_2 = 0; ldv_work_2_3 = 0; return; } } void call_and_disable_all_2(int state ) { { if (ldv_work_2_0 == state) { call_and_disable_work_2(ldv_work_struct_2_0); } else { } if (ldv_work_2_1 == state) { call_and_disable_work_2(ldv_work_struct_2_1); } else { } if (ldv_work_2_2 == state) { call_and_disable_work_2(ldv_work_struct_2_2); } else { } if (ldv_work_2_3 == state) { call_and_disable_work_2(ldv_work_struct_2_3); } else { } return; } } int reg_check_1(irqreturn_t (*handler)(int , void * ) ) { { if ((unsigned long )handler == (unsigned long )(& brcms_isr)) { return (1); } else { } return (0); } } void activate_work_2(struct work_struct *work , int state ) { { if (ldv_work_2_0 == 0) { ldv_work_struct_2_0 = work; ldv_work_2_0 = state; return; } else { } if (ldv_work_2_1 == 0) { ldv_work_struct_2_1 = work; ldv_work_2_1 = state; return; } else { } if (ldv_work_2_2 == 0) { ldv_work_struct_2_2 = work; ldv_work_2_2 = state; return; } else { } if (ldv_work_2_3 == 0) { ldv_work_struct_2_3 = work; ldv_work_2_3 = state; return; } else { } return; } } void activate_work_3(struct work_struct *work , int state ) { { if (ldv_work_3_0 == 0) { ldv_work_struct_3_0 = work; ldv_work_3_0 = state; return; } else { } if (ldv_work_3_1 == 0) { ldv_work_struct_3_1 = work; ldv_work_3_1 = state; return; } else { } if (ldv_work_3_2 == 0) { ldv_work_struct_3_2 = work; ldv_work_3_2 = state; return; } else { } if (ldv_work_3_3 == 0) { ldv_work_struct_3_3 = work; ldv_work_3_3 = state; return; } else { } return; } } void ldv_initialize_bcma_driver_22(void) { void *tmp ; { tmp = ldv_init_zalloc(1528UL); brcms_bcma_driver_group0 = (struct bcma_device *)tmp; return; } } void choose_interrupt_1(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ldv_irq_1_0 = ldv_irq_1(ldv_irq_1_0, ldv_irq_line_1_0, ldv_irq_data_1_0); goto ldv_56088; case 1: ldv_irq_1_0 = ldv_irq_1(ldv_irq_1_1, ldv_irq_line_1_1, ldv_irq_data_1_1); goto ldv_56088; case 2: ldv_irq_1_0 = ldv_irq_1(ldv_irq_1_2, ldv_irq_line_1_2, ldv_irq_data_1_2); goto ldv_56088; case 3: ldv_irq_1_0 = ldv_irq_1(ldv_irq_1_3, ldv_irq_line_1_3, ldv_irq_data_1_3); goto ldv_56088; default: ldv_stop(); } ldv_56088: ; return; } } void call_and_disable_work_3(struct work_struct *work ) { { if ((ldv_work_3_0 == 2 || ldv_work_3_0 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_3_0) { brcms_driver_init(work); ldv_work_3_0 = 1; return; } else { } if ((ldv_work_3_1 == 2 || ldv_work_3_1 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_3_1) { brcms_driver_init(work); ldv_work_3_1 = 1; return; } else { } if ((ldv_work_3_2 == 2 || ldv_work_3_2 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_3_2) { brcms_driver_init(work); ldv_work_3_2 = 1; return; } else { } if ((ldv_work_3_3 == 2 || ldv_work_3_3 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_3_3) { brcms_driver_init(work); ldv_work_3_3 = 1; return; } else { } return; } } void ldv_initialize_ieee80211_ops_23(void) { void *tmp ; { tmp = ldv_init_zalloc(160UL); brcms_ops_group0 = (struct ieee80211_hw *)tmp; return; } } void disable_work_3(struct work_struct *work ) { { if ((ldv_work_3_0 == 3 || ldv_work_3_0 == 2) && (unsigned long )ldv_work_struct_3_0 == (unsigned long )work) { ldv_work_3_0 = 1; } else { } if ((ldv_work_3_1 == 3 || ldv_work_3_1 == 2) && (unsigned long )ldv_work_struct_3_1 == (unsigned long )work) { ldv_work_3_1 = 1; } else { } if ((ldv_work_3_2 == 3 || ldv_work_3_2 == 2) && (unsigned long )ldv_work_struct_3_2 == (unsigned long )work) { ldv_work_3_2 = 1; } else { } if ((ldv_work_3_3 == 3 || ldv_work_3_3 == 2) && (unsigned long )ldv_work_struct_3_3 == (unsigned long )work) { ldv_work_3_3 = 1; } else { } return; } } void disable_work_2(struct work_struct *work ) { { if ((ldv_work_2_0 == 3 || ldv_work_2_0 == 2) && (unsigned long )ldv_work_struct_2_0 == (unsigned long )work) { ldv_work_2_0 = 1; } else { } if ((ldv_work_2_1 == 3 || ldv_work_2_1 == 2) && (unsigned long )ldv_work_struct_2_1 == (unsigned long )work) { ldv_work_2_1 = 1; } else { } if ((ldv_work_2_2 == 3 || ldv_work_2_2 == 2) && (unsigned long )ldv_work_struct_2_2 == (unsigned long )work) { ldv_work_2_2 = 1; } else { } if ((ldv_work_2_3 == 3 || ldv_work_2_3 == 2) && (unsigned long )ldv_work_struct_2_3 == (unsigned long )work) { ldv_work_2_3 = 1; } else { } return; } } void invoke_work_3(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ; if (ldv_work_3_0 == 2 || ldv_work_3_0 == 3) { ldv_work_3_0 = 4; brcms_driver_init(ldv_work_struct_3_0); ldv_work_3_0 = 1; } else { } goto ldv_56113; case 1: ; if (ldv_work_3_1 == 2 || ldv_work_3_1 == 3) { ldv_work_3_1 = 4; brcms_driver_init(ldv_work_struct_3_0); ldv_work_3_1 = 1; } else { } goto ldv_56113; case 2: ; if (ldv_work_3_2 == 2 || ldv_work_3_2 == 3) { ldv_work_3_2 = 4; brcms_driver_init(ldv_work_struct_3_0); ldv_work_3_2 = 1; } else { } goto ldv_56113; case 3: ; if (ldv_work_3_3 == 2 || ldv_work_3_3 == 3) { ldv_work_3_3 = 4; brcms_driver_init(ldv_work_struct_3_0); ldv_work_3_3 = 1; } else { } goto ldv_56113; default: ldv_stop(); } ldv_56113: ; return; } } void disable_suitable_irq_1(int line , void *data ) { { if (ldv_irq_1_0 != 0 && line == ldv_irq_line_1_0) { ldv_irq_1_0 = 0; return; } else { } if (ldv_irq_1_1 != 0 && line == ldv_irq_line_1_1) { ldv_irq_1_1 = 0; return; } else { } if (ldv_irq_1_2 != 0 && line == ldv_irq_line_1_2) { ldv_irq_1_2 = 0; return; } else { } if (ldv_irq_1_3 != 0 && line == ldv_irq_line_1_3) { ldv_irq_1_3 = 0; return; } else { } return; } } int ldv_irq_1(int state , int line , void *data ) { irqreturn_t irq_retval ; int tmp ; int tmp___0 ; { tmp = __VERIFIER_nondet_int(); irq_retval = (irqreturn_t )tmp; if (state != 0) { tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (state == 1) { LDV_IN_INTERRUPT = 2; irq_retval = brcms_isr(line, data); LDV_IN_INTERRUPT = 1; return (state); } else { } goto ldv_56129; default: ldv_stop(); } ldv_56129: ; } else { } return (state); } } void activate_suitable_irq_1(int line , void *data ) { { if (ldv_irq_1_0 == 0) { ldv_irq_line_1_0 = line; ldv_irq_data_1_0 = data; ldv_irq_1_0 = 1; return; } else { } if (ldv_irq_1_1 == 0) { ldv_irq_line_1_1 = line; ldv_irq_data_1_1 = data; ldv_irq_1_1 = 1; return; } else { } if (ldv_irq_1_2 == 0) { ldv_irq_line_1_2 = line; ldv_irq_data_1_2 = data; ldv_irq_1_2 = 1; return; } else { } if (ldv_irq_1_3 == 0) { ldv_irq_line_1_3 = line; ldv_irq_data_1_3 = data; ldv_irq_1_3 = 1; return; } else { } return; } } void call_and_disable_all_3(int state ) { { if (ldv_work_3_0 == state) { call_and_disable_work_3(ldv_work_struct_3_0); } else { } if (ldv_work_3_1 == state) { call_and_disable_work_3(ldv_work_struct_3_1); } else { } if (ldv_work_3_2 == state) { call_and_disable_work_3(ldv_work_struct_3_2); } else { } if (ldv_work_3_3 == state) { call_and_disable_work_3(ldv_work_struct_3_3); } else { } return; } } void call_and_disable_work_2(struct work_struct *work ) { { if ((ldv_work_2_0 == 2 || ldv_work_2_0 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_2_0) { _brcms_timer(work); ldv_work_2_0 = 1; return; } else { } if ((ldv_work_2_1 == 2 || ldv_work_2_1 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_2_1) { _brcms_timer(work); ldv_work_2_1 = 1; return; } else { } if ((ldv_work_2_2 == 2 || ldv_work_2_2 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_2_2) { _brcms_timer(work); ldv_work_2_2 = 1; return; } else { } if ((ldv_work_2_3 == 2 || ldv_work_2_3 == 3) && (unsigned long )work == (unsigned long )ldv_work_struct_2_3) { _brcms_timer(work); ldv_work_2_3 = 1; return; } else { } return; } } void invoke_work_2(void) { int tmp ; { tmp = __VERIFIER_nondet_int(); switch (tmp) { case 0: ; if (ldv_work_2_0 == 2 || ldv_work_2_0 == 3) { ldv_work_2_0 = 4; _brcms_timer(ldv_work_struct_2_0); ldv_work_2_0 = 1; } else { } goto ldv_56151; case 1: ; if (ldv_work_2_1 == 2 || ldv_work_2_1 == 3) { ldv_work_2_1 = 4; _brcms_timer(ldv_work_struct_2_0); ldv_work_2_1 = 1; } else { } goto ldv_56151; case 2: ; if (ldv_work_2_2 == 2 || ldv_work_2_2 == 3) { ldv_work_2_2 = 4; _brcms_timer(ldv_work_struct_2_0); ldv_work_2_2 = 1; } else { } goto ldv_56151; case 3: ; if (ldv_work_2_3 == 2 || ldv_work_2_3 == 3) { ldv_work_2_3 = 4; _brcms_timer(ldv_work_struct_2_0); ldv_work_2_3 = 1; } else { } goto ldv_56151; default: ldv_stop(); } ldv_56151: ; return; } } void ldv_main_exported_11(void) ; void ldv_main_exported_7(void) ; void ldv_main_exported_17(void) ; void ldv_main_exported_18(void) ; void ldv_main_exported_16(void) ; void ldv_main_exported_13(void) ; void ldv_main_exported_6(void) ; void ldv_main_exported_9(void) ; void ldv_main_exported_12(void) ; void ldv_main_exported_14(void) ; void ldv_main_exported_15(void) ; void ldv_main_exported_20(void) ; void ldv_main_exported_8(void) ; void ldv_main_exported_10(void) ; void ldv_main_exported_19(void) ; void ldv_main_exported_5(void) ; void ldv_main_exported_4(void) ; int main(void) { struct work_struct *ldvarg2 ; void *tmp ; struct ieee80211_vif *ldvarg39 ; void *tmp___0 ; u16 *ldvarg18 ; void *tmp___1 ; struct ieee80211_vif *ldvarg11 ; void *tmp___2 ; u16 ldvarg32 ; struct ieee80211_tx_queue_params *ldvarg31 ; void *tmp___3 ; enum ieee80211_ampdu_mlme_action ldvarg20 ; u32 ldvarg41 ; u16 ldvarg23 ; struct ieee80211_vif *ldvarg12 ; void *tmp___4 ; bool ldvarg37 ; u8 *ldvarg13 ; void *tmp___5 ; struct ieee80211_vif *ldvarg36 ; void *tmp___6 ; struct ieee80211_vif *ldvarg29 ; void *tmp___7 ; struct ieee80211_vif *ldvarg40 ; void *tmp___8 ; struct sk_buff *ldvarg24 ; void *tmp___9 ; struct ieee80211_vif *ldvarg27 ; void *tmp___10 ; u64 ldvarg26 ; struct ieee80211_bss_conf *ldvarg35 ; void *tmp___11 ; u32 ldvarg38 ; struct ieee80211_vif *ldvarg33 ; void *tmp___12 ; struct ieee80211_vif *ldvarg30 ; void *tmp___13 ; u64 ldvarg15 ; unsigned int *ldvarg16 ; void *tmp___14 ; u8 ldvarg21 ; unsigned int ldvarg17 ; struct ieee80211_vif *ldvarg14 ; void *tmp___15 ; struct ieee80211_tx_control *ldvarg25 ; void *tmp___16 ; struct ieee80211_vif *ldvarg22 ; void *tmp___17 ; struct ieee80211_sta *ldvarg19 ; void *tmp___18 ; u32 ldvarg34 ; struct ieee80211_sta *ldvarg28 ; void *tmp___19 ; int tmp___20 ; int tmp___21 ; int tmp___22 ; int tmp___23 ; int tmp___24 ; { tmp = ldv_init_zalloc(80UL); ldvarg2 = (struct work_struct *)tmp; tmp___0 = ldv_init_zalloc(296UL); ldvarg39 = (struct ieee80211_vif *)tmp___0; tmp___1 = ldv_init_zalloc(2UL); ldvarg18 = (u16 *)tmp___1; tmp___2 = ldv_init_zalloc(296UL); ldvarg11 = (struct ieee80211_vif *)tmp___2; tmp___3 = ldv_init_zalloc(10UL); ldvarg31 = (struct ieee80211_tx_queue_params *)tmp___3; tmp___4 = ldv_init_zalloc(296UL); ldvarg12 = (struct ieee80211_vif *)tmp___4; tmp___5 = ldv_init_zalloc(1UL); ldvarg13 = (u8 *)tmp___5; tmp___6 = ldv_init_zalloc(296UL); ldvarg36 = (struct ieee80211_vif *)tmp___6; tmp___7 = ldv_init_zalloc(296UL); ldvarg29 = (struct ieee80211_vif *)tmp___7; tmp___8 = ldv_init_zalloc(296UL); ldvarg40 = (struct ieee80211_vif *)tmp___8; tmp___9 = ldv_init_zalloc(232UL); ldvarg24 = (struct sk_buff *)tmp___9; tmp___10 = ldv_init_zalloc(296UL); ldvarg27 = (struct ieee80211_vif *)tmp___10; tmp___11 = ldv_init_zalloc(240UL); ldvarg35 = (struct ieee80211_bss_conf *)tmp___11; tmp___12 = ldv_init_zalloc(296UL); ldvarg33 = (struct ieee80211_vif *)tmp___12; tmp___13 = ldv_init_zalloc(296UL); ldvarg30 = (struct ieee80211_vif *)tmp___13; tmp___14 = ldv_init_zalloc(4UL); ldvarg16 = (unsigned int *)tmp___14; tmp___15 = ldv_init_zalloc(296UL); ldvarg14 = (struct ieee80211_vif *)tmp___15; tmp___16 = ldv_init_zalloc(8UL); ldvarg25 = (struct ieee80211_tx_control *)tmp___16; tmp___17 = ldv_init_zalloc(296UL); ldvarg22 = (struct ieee80211_vif *)tmp___17; tmp___18 = ldv_init_zalloc(216UL); ldvarg19 = (struct ieee80211_sta *)tmp___18; tmp___19 = ldv_init_zalloc(216UL); ldvarg28 = (struct ieee80211_sta *)tmp___19; ldv_initialize(); ldv_memset((void *)(& ldvarg32), 0, 2UL); ldv_memset((void *)(& ldvarg20), 0, 4UL); ldv_memset((void *)(& ldvarg41), 0, 4UL); ldv_memset((void *)(& ldvarg23), 0, 2UL); ldv_memset((void *)(& ldvarg37), 0, 1UL); ldv_memset((void *)(& ldvarg26), 0, 8UL); ldv_memset((void *)(& ldvarg38), 0, 4UL); ldv_memset((void *)(& ldvarg15), 0, 8UL); ldv_memset((void *)(& ldvarg21), 0, 1UL); ldv_memset((void *)(& ldvarg17), 0, 4UL); ldv_memset((void *)(& ldvarg34), 0, 4UL); ldv_state_variable_11 = 0; ldv_state_variable_21 = 0; ldv_state_variable_7 = 0; ldv_state_variable_17 = 0; work_init_2(); ldv_state_variable_2 = 1; ldv_state_variable_22 = 0; ldv_state_variable_1 = 1; ldv_state_variable_18 = 0; ref_cnt = 0; ldv_state_variable_0 = 1; ldv_state_variable_23 = 0; ldv_state_variable_16 = 0; ldv_state_variable_13 = 0; ldv_state_variable_6 = 0; work_init_3(); ldv_state_variable_3 = 1; ldv_state_variable_9 = 0; ldv_state_variable_12 = 0; ldv_state_variable_20 = 0; ldv_state_variable_14 = 0; ldv_state_variable_15 = 0; ldv_state_variable_8 = 0; ldv_state_variable_4 = 0; ldv_state_variable_19 = 0; ldv_state_variable_10 = 0; ldv_state_variable_5 = 0; ldv_56292: tmp___20 = __VERIFIER_nondet_int(); switch (tmp___20) { case 0: ; if (ldv_state_variable_11 != 0) { ldv_main_exported_11(); } else { } goto ldv_56234; case 1: ; if (ldv_state_variable_21 != 0) { tmp___21 = __VERIFIER_nondet_int(); switch (tmp___21) { case 0: ; if (ldv_state_variable_21 == 1) { brcms_driver_init(ldvarg2); ldv_state_variable_21 = 1; } else { } goto ldv_56237; default: ldv_stop(); } ldv_56237: ; } else { } goto ldv_56234; case 2: ; if (ldv_state_variable_7 != 0) { ldv_main_exported_7(); } else { } goto ldv_56234; case 3: ; if (ldv_state_variable_17 != 0) { ldv_main_exported_17(); } else { } goto ldv_56234; case 4: ; if (ldv_state_variable_2 != 0) { invoke_work_2(); } else { } goto ldv_56234; case 5: ; if (ldv_state_variable_22 != 0) { tmp___22 = __VERIFIER_nondet_int(); switch (tmp___22) { case 0: ; if (ldv_state_variable_22 == 1) { ldv_retval_2 = brcms_bcma_probe(brcms_bcma_driver_group0); if (ldv_retval_2 == 0) { ldv_state_variable_22 = 2; ref_cnt = ref_cnt + 1; } else { } } else { } goto ldv_56244; case 1: ; if (ldv_state_variable_22 == 2) { ldv_retval_1 = brcms_suspend(brcms_bcma_driver_group0); if (ldv_retval_1 == 0) { ldv_state_variable_22 = 3; } else { } } else { } goto ldv_56244; case 2: ; if (ldv_state_variable_22 == 3) { ldv_retval_0 = brcms_resume(brcms_bcma_driver_group0); if (ldv_retval_0 == 0) { ldv_state_variable_22 = 2; } else { } } else { } goto ldv_56244; case 3: ; if (ldv_state_variable_22 == 3) { brcms_remove(brcms_bcma_driver_group0); ldv_state_variable_22 = 1; ref_cnt = ref_cnt - 1; } else { } if (ldv_state_variable_22 == 2) { brcms_remove(brcms_bcma_driver_group0); ldv_state_variable_22 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_56244; default: ldv_stop(); } ldv_56244: ; } else { } goto ldv_56234; case 6: ; if (ldv_state_variable_1 != 0) { choose_interrupt_1(); } else { } goto ldv_56234; case 7: ; if (ldv_state_variable_18 != 0) { ldv_main_exported_18(); } else { } goto ldv_56234; case 8: ; if (ldv_state_variable_0 != 0) { tmp___23 = __VERIFIER_nondet_int(); switch (tmp___23) { case 0: ; if (ldv_state_variable_0 == 3 && ref_cnt == 0) { brcms_module_exit(); ldv_state_variable_0 = 2; goto ldv_final; } else { } goto ldv_56254; case 1: ; if (ldv_state_variable_0 == 1) { ldv_retval_3 = brcms_module_init(); if (ldv_retval_3 == 0) { ldv_state_variable_0 = 3; ldv_state_variable_5 = 1; ldv_initialize_trace_event_class_5(); ldv_state_variable_19 = 1; ldv_state_variable_10 = 1; ldv_initialize_trace_event_class_10(); ldv_state_variable_4 = 1; ldv_file_operations_4(); ldv_state_variable_8 = 1; ldv_state_variable_15 = 1; ldv_initialize_trace_event_class_15(); ldv_state_variable_14 = 1; ldv_state_variable_20 = 1; ldv_state_variable_12 = 1; ldv_state_variable_9 = 1; ldv_initialize_trace_event_class_9(); ldv_state_variable_6 = 1; ldv_initialize_trace_event_class_6(); ldv_state_variable_13 = 1; ldv_state_variable_16 = 1; ldv_initialize_trace_event_class_16(); ldv_state_variable_18 = 1; ldv_state_variable_22 = 1; ldv_initialize_bcma_driver_22(); ldv_state_variable_17 = 1; ldv_initialize_trace_event_class_17(); ldv_state_variable_7 = 1; ldv_state_variable_21 = 1; ldv_state_variable_11 = 1; ldv_initialize_trace_event_class_11(); } else { } if (ldv_retval_3 != 0) { ldv_state_variable_0 = 2; goto ldv_final; } else { } } else { } goto ldv_56254; default: ldv_stop(); } ldv_56254: ; } else { } goto ldv_56234; case 9: ; if (ldv_state_variable_23 != 0) { tmp___24 = __VERIFIER_nondet_int(); switch (tmp___24) { case 0: ; if (ldv_state_variable_23 == 1) { ldv_retval_4 = brcms_ops_start(brcms_ops_group0); if (ldv_retval_4 == 0) { ldv_state_variable_23 = 2; ref_cnt = ref_cnt + 1; } else { } } else { } goto ldv_56259; case 1: ; if (ldv_state_variable_23 == 1) { brcms_ops_config(brcms_ops_group0, ldvarg41); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_config(brcms_ops_group0, ldvarg41); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 2: ; if (ldv_state_variable_23 == 1) { brcms_ops_get_tsf(brcms_ops_group0, ldvarg40); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_get_tsf(brcms_ops_group0, ldvarg40); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 3: ; if (ldv_state_variable_23 == 1) { brcms_ops_flush(brcms_ops_group0, ldvarg39, ldvarg38, (int )ldvarg37); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_flush(brcms_ops_group0, ldvarg39, ldvarg38, (int )ldvarg37); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 4: ; if (ldv_state_variable_23 == 1) { brcms_ops_bss_info_changed(brcms_ops_group0, ldvarg36, ldvarg35, ldvarg34); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_bss_info_changed(brcms_ops_group0, ldvarg36, ldvarg35, ldvarg34); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 5: ; if (ldv_state_variable_23 == 1) { brcms_ops_conf_tx(brcms_ops_group0, ldvarg33, (int )ldvarg32, (struct ieee80211_tx_queue_params const *)ldvarg31); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_conf_tx(brcms_ops_group0, ldvarg33, (int )ldvarg32, (struct ieee80211_tx_queue_params const *)ldvarg31); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 6: ; if (ldv_state_variable_23 == 1) { brcms_ops_sw_scan_complete(brcms_ops_group0, ldvarg30); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_sw_scan_complete(brcms_ops_group0, ldvarg30); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 7: ; if (ldv_state_variable_23 == 1) { brcms_ops_sta_add(brcms_ops_group0, ldvarg29, ldvarg28); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_sta_add(brcms_ops_group0, ldvarg29, ldvarg28); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 8: ; if (ldv_state_variable_23 == 2) { brcms_ops_stop(brcms_ops_group0); ldv_state_variable_23 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_56259; case 9: ; if (ldv_state_variable_23 == 1) { brcms_ops_set_tsf(brcms_ops_group0, ldvarg27, ldvarg26); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_set_tsf(brcms_ops_group0, ldvarg27, ldvarg26); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 10: ; if (ldv_state_variable_23 == 1) { brcms_ops_tx(brcms_ops_group0, ldvarg25, ldvarg24); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_tx(brcms_ops_group0, ldvarg25, ldvarg24); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 11: ; if (ldv_state_variable_23 == 1) { brcms_ops_ampdu_action(brcms_ops_group0, ldvarg22, ldvarg20, ldvarg19, (int )ldvarg23, ldvarg18, (int )ldvarg21); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_ampdu_action(brcms_ops_group0, ldvarg22, ldvarg20, ldvarg19, (int )ldvarg23, ldvarg18, (int )ldvarg21); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 12: ; if (ldv_state_variable_23 == 1) { brcms_ops_configure_filter(brcms_ops_group0, ldvarg17, ldvarg16, ldvarg15); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_configure_filter(brcms_ops_group0, ldvarg17, ldvarg16, ldvarg15); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 13: ; if (ldv_state_variable_23 == 1) { brcms_ops_rfkill_poll(brcms_ops_group0); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_rfkill_poll(brcms_ops_group0); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 14: ; if (ldv_state_variable_23 == 1) { brcms_ops_sw_scan_start(brcms_ops_group0, ldvarg14, (u8 const *)ldvarg13); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_sw_scan_start(brcms_ops_group0, ldvarg14, (u8 const *)ldvarg13); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 15: ; if (ldv_state_variable_23 == 1) { brcms_ops_add_interface(brcms_ops_group0, ldvarg12); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_add_interface(brcms_ops_group0, ldvarg12); ldv_state_variable_23 = 2; } else { } goto ldv_56259; case 16: ; if (ldv_state_variable_23 == 1) { brcms_ops_remove_interface(brcms_ops_group0, ldvarg11); ldv_state_variable_23 = 1; } else { } if (ldv_state_variable_23 == 2) { brcms_ops_remove_interface(brcms_ops_group0, ldvarg11); ldv_state_variable_23 = 2; } else { } goto ldv_56259; default: ldv_stop(); } ldv_56259: ; } else { } goto ldv_56234; case 10: ; if (ldv_state_variable_16 != 0) { ldv_main_exported_16(); } else { } goto ldv_56234; case 11: ; if (ldv_state_variable_13 != 0) { ldv_main_exported_13(); } else { } goto ldv_56234; case 12: ; if (ldv_state_variable_6 != 0) { ldv_main_exported_6(); } else { } goto ldv_56234; case 13: ; if (ldv_state_variable_3 != 0) { invoke_work_3(); } else { } goto ldv_56234; case 14: ; if (ldv_state_variable_9 != 0) { ldv_main_exported_9(); } else { } goto ldv_56234; case 15: ; if (ldv_state_variable_12 != 0) { ldv_main_exported_12(); } else { } goto ldv_56234; case 16: ; if (ldv_state_variable_20 != 0) { ldv_main_exported_20(); } else { } goto ldv_56234; case 17: ; if (ldv_state_variable_14 != 0) { ldv_main_exported_14(); } else { } goto ldv_56234; case 18: ; if (ldv_state_variable_15 != 0) { ldv_main_exported_15(); } else { } goto ldv_56234; case 19: ; if (ldv_state_variable_8 != 0) { ldv_main_exported_8(); } else { } goto ldv_56234; case 20: ; if (ldv_state_variable_4 != 0) { ldv_main_exported_4(); } else { } goto ldv_56234; case 21: ; if (ldv_state_variable_19 != 0) { ldv_main_exported_19(); } else { } goto ldv_56234; case 22: ; if (ldv_state_variable_10 != 0) { ldv_main_exported_10(); } else { } goto ldv_56234; case 23: ; if (ldv_state_variable_5 != 0) { ldv_main_exported_5(); } else { } goto ldv_56234; default: ldv_stop(); } ldv_56234: ; goto ldv_56292; ldv_final: ldv_check_final_state(); return 0; } } bool ldv_queue_work_on_5(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_6(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_7(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_8(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_9(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } void ldv_free_irq_10(unsigned int ldv_func_arg1 , void *ldv_func_arg2 ) { { free_irq(ldv_func_arg1, ldv_func_arg2); disable_suitable_irq_1((int )ldv_func_arg1, ldv_func_arg2); return; } } void ldv_ieee80211_free_hw_11(struct ieee80211_hw *ldv_func_arg1 ) { { ieee80211_free_hw(ldv_func_arg1); if ((unsigned long )brcms_ops_group0 == (unsigned long )ldv_func_arg1) { ldv_state_variable_23 = 0; } else { } return; } } __inline static int ldv_request_irq_12(unsigned int irq , irqreturn_t (*handler)(int , void * ) , unsigned long flags , char const *name , void *dev ) { ldv_func_ret_type___3 ldv_func_res ; int tmp ; int tmp___0 ; { tmp = request_irq(irq, handler, flags, name, dev); ldv_func_res = tmp; tmp___0 = reg_check_1(handler); if (tmp___0 != 0 && ldv_func_res == 0) { activate_suitable_irq_1((int )irq, dev); } else { } return (ldv_func_res); } } __inline static struct ieee80211_hw *ldv_ieee80211_alloc_hw_13(size_t priv_data_len , struct ieee80211_ops const *ops ) { ldv_func_ret_type___4 ldv_func_res ; struct ieee80211_hw *tmp ; { tmp = ieee80211_alloc_hw(priv_data_len, ops); ldv_func_res = tmp; if ((unsigned long )ldv_func_res != (unsigned long )((ldv_func_ret_type___4 )0)) { ldv_state_variable_23 = 1; ldv_initialize_ieee80211_ops_23(); brcms_ops_group0 = ldv_func_res; } else { } return (ldv_func_res); } } bool ldv_cancel_work_sync_14(struct work_struct *ldv_func_arg1 ) { ldv_func_ret_type___5 ldv_func_res ; bool tmp ; { tmp = cancel_work_sync(ldv_func_arg1); ldv_func_res = tmp; disable_work_2(ldv_func_arg1); return (ldv_func_res); } } bool ldv_cancel_delayed_work_15(struct delayed_work *ldv_func_arg1 ) { ldv_func_ret_type___6 ldv_func_res ; bool tmp ; { tmp = cancel_delayed_work(ldv_func_arg1); ldv_func_res = tmp; disable_work_2(& ldv_func_arg1->work); return (ldv_func_res); } } bool ldv_queue_work_on_31(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_33(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_32(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_35(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_34(struct workqueue_struct *ldv_func_arg1 ) ; int brcms_ucode_data_init(struct brcms_info *wl , struct brcms_ucode *ucode ) { int rc ; int tmp ; int tmp___0 ; int tmp___1 ; int tmp___2 ; int tmp___3 ; int tmp___4 ; int tmp___5 ; int tmp___6 ; int tmp___7 ; int tmp___8 ; int tmp___9 ; int tmp___10 ; int tmp___11 ; int tmp___12 ; int tmp___13 ; { rc = brcms_check_firmwares(wl); if (rc >= 0) { tmp = brcms_ucode_init_buf(wl, (void **)(& ucode->d11lcn0bsinitvals24), 1U); rc = tmp; } else { rc = rc; } if (rc >= 0) { tmp___0 = brcms_ucode_init_buf(wl, (void **)(& ucode->d11lcn0initvals24), 2U); rc = tmp___0; } else { rc = rc; } if (rc >= 0) { tmp___1 = brcms_ucode_init_buf(wl, (void **)(& ucode->d11lcn1bsinitvals24), 3U); rc = tmp___1; } else { rc = rc; } if (rc >= 0) { tmp___2 = brcms_ucode_init_buf(wl, (void **)(& ucode->d11lcn1initvals24), 4U); rc = tmp___2; } else { rc = rc; } if (rc >= 0) { tmp___3 = brcms_ucode_init_buf(wl, (void **)(& ucode->d11lcn2bsinitvals24), 5U); rc = tmp___3; } else { rc = rc; } if (rc >= 0) { tmp___4 = brcms_ucode_init_buf(wl, (void **)(& ucode->d11lcn2initvals24), 6U); rc = tmp___4; } else { rc = rc; } if (rc >= 0) { tmp___5 = brcms_ucode_init_buf(wl, (void **)(& ucode->d11n0absinitvals16), 7U); rc = tmp___5; } else { rc = rc; } if (rc >= 0) { tmp___6 = brcms_ucode_init_buf(wl, (void **)(& ucode->d11n0bsinitvals16), 8U); rc = tmp___6; } else { rc = rc; } if (rc >= 0) { tmp___7 = brcms_ucode_init_buf(wl, (void **)(& ucode->d11n0initvals16), 9U); rc = tmp___7; } else { rc = rc; } if (rc >= 0) { tmp___8 = brcms_ucode_init_buf(wl, (void **)(& ucode->bcm43xx_16_mimo), 10U); rc = tmp___8; } else { rc = rc; } if (rc >= 0) { tmp___9 = brcms_ucode_init_uint(wl, & ucode->bcm43xx_16_mimosz, 11U); rc = tmp___9; } else { rc = rc; } if (rc >= 0) { tmp___10 = brcms_ucode_init_buf(wl, (void **)(& ucode->bcm43xx_24_lcn), 12U); rc = tmp___10; } else { rc = rc; } if (rc >= 0) { tmp___11 = brcms_ucode_init_uint(wl, & ucode->bcm43xx_24_lcnsz, 13U); rc = tmp___11; } else { rc = rc; } if (rc >= 0) { tmp___12 = brcms_ucode_init_buf(wl, (void **)(& ucode->bcm43xx_bommajor), 14U); rc = tmp___12; } else { rc = rc; } if (rc >= 0) { tmp___13 = brcms_ucode_init_buf(wl, (void **)(& ucode->bcm43xx_bomminor), 15U); rc = tmp___13; } else { rc = rc; } return (rc); } } void brcms_ucode_data_free(struct brcms_ucode *ucode ) { { brcms_ucode_free_buf((void *)ucode->d11lcn0bsinitvals24); brcms_ucode_free_buf((void *)ucode->d11lcn0initvals24); brcms_ucode_free_buf((void *)ucode->d11lcn1bsinitvals24); brcms_ucode_free_buf((void *)ucode->d11lcn1initvals24); brcms_ucode_free_buf((void *)ucode->d11lcn2bsinitvals24); brcms_ucode_free_buf((void *)ucode->d11lcn2initvals24); brcms_ucode_free_buf((void *)ucode->d11n0absinitvals16); brcms_ucode_free_buf((void *)ucode->d11n0bsinitvals16); brcms_ucode_free_buf((void *)ucode->d11n0initvals16); brcms_ucode_free_buf((void *)ucode->bcm43xx_16_mimo); brcms_ucode_free_buf((void *)ucode->bcm43xx_24_lcn); brcms_ucode_free_buf((void *)ucode->bcm43xx_bommajor); brcms_ucode_free_buf((void *)ucode->bcm43xx_bomminor); return; } } bool ldv_queue_work_on_31(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_32(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_33(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_34(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_35(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static void __read_once_size(void const volatile *p , void *res , int size ) { { switch (size) { case 1: *((__u8 *)res) = *((__u8 volatile *)p); goto ldv_880; case 2: *((__u16 *)res) = *((__u16 volatile *)p); goto ldv_880; case 4: *((__u32 *)res) = *((__u32 volatile *)p); goto ldv_880; case 8: *((__u64 *)res) = *((__u64 volatile *)p); goto ldv_880; default: __asm__ volatile ("": : : "memory"); __builtin_memcpy(res, (void const *)p, (unsigned long )size); __asm__ volatile ("": : : "memory"); } ldv_880: ; return; } } extern struct pv_irq_ops pv_irq_ops ; extern void __bad_percpu_size(void) ; extern void warn_slowpath_fmt(char const * , int const , char const * , ...) ; __inline static unsigned long arch_local_save_flags(void) { unsigned long __ret ; unsigned long __edi ; unsigned long __esi ; unsigned long __edx ; unsigned long __ecx ; unsigned long __eax ; long tmp ; { __edi = __edi; __esi = __esi; __edx = __edx; __ecx = __ecx; __eax = __eax; tmp = ldv__builtin_expect((unsigned long )pv_irq_ops.save_fl.func == (unsigned long )((void *)0), 0L); if (tmp != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"./arch/x86/include/asm/paravirt.h"), "i" (831), "i" (12UL)); ldv_4860: ; goto ldv_4860; } else { } __asm__ volatile ("771:\n\tcall *%c2;\n772:\n.pushsection .parainstructions,\"a\"\n .balign 8 \n .quad 771b\n .byte %c1\n .byte 772b-771b\n .short %c3\n.popsection\n": "=a" (__eax): [paravirt_typenum] "i" (43UL), [paravirt_opptr] "i" (& pv_irq_ops.save_fl.func), [paravirt_clobber] "i" (1): "memory", "cc"); __ret = __eax; return (__ret); } } __inline static int arch_irqs_disabled_flags(unsigned long flags ) { { return ((flags & 512UL) == 0UL); } } extern int __preempt_count ; __inline static int preempt_count(void) { int pfo_ret__ ; { switch (4UL) { case 1UL: __asm__ ("movb %%gs:%1,%0": "=q" (pfo_ret__): "m" (__preempt_count)); goto ldv_6002; case 2UL: __asm__ ("movw %%gs:%1,%0": "=r" (pfo_ret__): "m" (__preempt_count)); goto ldv_6002; case 4UL: __asm__ ("movl %%gs:%1,%0": "=r" (pfo_ret__): "m" (__preempt_count)); goto ldv_6002; case 8UL: __asm__ ("movq %%gs:%1,%0": "=r" (pfo_ret__): "m" (__preempt_count)); goto ldv_6002; default: __bad_percpu_size(); } ldv_6002: ; return (pfo_ret__ & 2147483647); } } __inline static void __preempt_count_add(int val ) { int pao_ID__ ; { pao_ID__ = 0; switch (4UL) { case 1UL: ; if (pao_ID__ == 1) { __asm__ ("incb %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decb %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addb %1, %%gs:%0": "+m" (__preempt_count): "qi" (val)); } goto ldv_6059; case 2UL: ; if (pao_ID__ == 1) { __asm__ ("incw %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decw %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addw %1, %%gs:%0": "+m" (__preempt_count): "ri" (val)); } goto ldv_6059; case 4UL: ; if (pao_ID__ == 1) { __asm__ ("incl %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decl %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addl %1, %%gs:%0": "+m" (__preempt_count): "ri" (val)); } goto ldv_6059; case 8UL: ; if (pao_ID__ == 1) { __asm__ ("incq %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decq %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addq %1, %%gs:%0": "+m" (__preempt_count): "re" (val)); } goto ldv_6059; default: __bad_percpu_size(); } ldv_6059: ; return; } } __inline static void __preempt_count_sub(int val ) { int pao_ID__ ; { pao_ID__ = 0; switch (4UL) { case 1UL: ; if (pao_ID__ == 1) { __asm__ ("incb %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decb %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addb %1, %%gs:%0": "+m" (__preempt_count): "qi" (- val)); } goto ldv_6071; case 2UL: ; if (pao_ID__ == 1) { __asm__ ("incw %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decw %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addw %1, %%gs:%0": "+m" (__preempt_count): "ri" (- val)); } goto ldv_6071; case 4UL: ; if (pao_ID__ == 1) { __asm__ ("incl %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decl %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addl %1, %%gs:%0": "+m" (__preempt_count): "ri" (- val)); } goto ldv_6071; case 8UL: ; if (pao_ID__ == 1) { __asm__ ("incq %%gs:%0": "+m" (__preempt_count)); } else if (pao_ID__ == -1) { __asm__ ("decq %%gs:%0": "+m" (__preempt_count)); } else { __asm__ ("addq %1, %%gs:%0": "+m" (__preempt_count): "re" (- val)); } goto ldv_6071; default: __bad_percpu_size(); } ldv_6071: ; return; } } extern int debug_locks ; extern int lock_is_held(struct lockdep_map * ) ; extern void lockdep_rcu_suspicious(char const * , int const , char const * ) ; __inline static int static_key_count(struct static_key *key ) { int tmp ; { tmp = atomic_read((atomic_t const *)(& key->enabled)); return (tmp); } } __inline static bool static_key_false(struct static_key *key ) { int tmp ; long tmp___0 ; { tmp = static_key_count(key); tmp___0 = ldv__builtin_expect(tmp > 0, 0L); if (tmp___0 != 0L) { return (1); } else { } return (0); } } extern bool rcu_is_watching(void) ; extern bool rcu_lockdep_current_cpu_online(void) ; extern struct lockdep_map rcu_sched_lock_map ; extern int debug_lockdep_rcu_enabled(void) ; __inline static int rcu_read_lock_sched_held(void) { int lockdep_opinion ; int tmp ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; int tmp___4 ; unsigned long _flags ; int tmp___5 ; int tmp___6 ; { lockdep_opinion = 0; tmp = debug_lockdep_rcu_enabled(); if (tmp == 0) { return (1); } else { } tmp___0 = rcu_is_watching(); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return (0); } else { } tmp___2 = rcu_lockdep_current_cpu_online(); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { return (0); } else { } if (debug_locks != 0) { lockdep_opinion = lock_is_held(& rcu_sched_lock_map); } else { } if (lockdep_opinion != 0) { tmp___6 = 1; } else { tmp___4 = preempt_count(); if (tmp___4 != 0) { tmp___6 = 1; } else { _flags = arch_local_save_flags(); tmp___5 = arch_irqs_disabled_flags(_flags); if (tmp___5 != 0) { tmp___6 = 1; } else { tmp___6 = 0; } } } return (tmp___6); } } __inline static void rcu_read_lock_sched_notrace(void) { { __preempt_count_add(1); __asm__ volatile ("": : : "memory"); return; } } __inline static void rcu_read_unlock_sched_notrace(void) { { __asm__ volatile ("": : : "memory"); __preempt_count_sub(1); return; } } bool ldv_queue_work_on_45(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_47(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_46(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_49(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_48(struct workqueue_struct *ldv_func_arg1 ) ; __inline static int skb_queue_empty(struct sk_buff_head const *list ) { { return ((unsigned long )((struct sk_buff const *)list->next) == (unsigned long )((struct sk_buff const *)list)); } } __inline static struct sk_buff *skb_peek(struct sk_buff_head const *list_ ) { struct sk_buff *skb ; { skb = list_->next; if ((unsigned long )skb == (unsigned long )((struct sk_buff *)list_)) { skb = (struct sk_buff *)0; } else { } return (skb); } } __inline static struct sk_buff *skb_peek_tail(struct sk_buff_head const *list_ ) { struct sk_buff *skb ; { skb = list_->prev; if ((unsigned long )skb == (unsigned long )((struct sk_buff *)list_)) { skb = (struct sk_buff *)0; } else { } return (skb); } } __inline static __u32 skb_queue_len(struct sk_buff_head const *list_ ) { { return ((__u32 )list_->qlen); } } __inline static void __skb_queue_head_init(struct sk_buff_head *list ) { struct sk_buff *tmp ; { tmp = (struct sk_buff *)list; list->next = tmp; list->prev = tmp; list->qlen = 0U; return; } } __inline static void skb_queue_head_init(struct sk_buff_head *list ) { struct lock_class_key __key ; { spinlock_check(& list->lock); __raw_spin_lock_init(& list->lock.__annonCompField18.rlock, "&(&list->lock)->rlock", & __key); __skb_queue_head_init(list); return; } } extern void skb_queue_tail(struct sk_buff_head * , struct sk_buff * ) ; extern unsigned char *skb_pull(struct sk_buff * , unsigned int ) ; __inline static int ieee80211_is_rts(__le16 fc ) { { return (((int )fc & 252) == 180); } } __inline static int ieee80211_is_cts(__le16 fc ) { { return (((int )fc & 252) == 196); } } __inline static void ieee80211_tx_info_clear_status(struct ieee80211_tx_info *info ) { int i ; { i = 0; goto ldv_47948; ldv_47947: info->__annonCompField103.status.rates[i].count = 0U; i = i + 1; ldv_47948: ; if (i <= 3) { goto ldv_47947; } else { } memset((void *)(& info->__annonCompField103.status.ampdu_ack_len), 0, 24UL); return; } } extern void ieee80211_tx_status_irqsafe(struct ieee80211_hw * , struct sk_buff * ) ; __inline static u32 bcma_read32(struct bcma_device *core , u16 offset ) { u32 tmp ; { tmp = (*(((core->bus)->ops)->read32))(core, (int )offset); return (tmp); } } struct sk_buff *dma_getnexttxp(struct dma_pub *pub , enum txd_range range ) ; extern void brcmu_pkt_buf_free_skb(struct sk_buff * ) ; u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi ) ; struct brcms_mcs_info const mcs_table[33U] ; __inline static uint mcs_2_rate(u8 mcs , bool is40 , bool sgi ) { { if ((int )sgi) { if ((int )is40) { return ((uint )mcs_table[(int )mcs].phy_rate_40_sgi); } else { } return ((uint )mcs_table[(int )mcs].phy_rate_20_sgi); } else { } if ((int )is40) { return ((uint )mcs_table[(int )mcs].phy_rate_40); } else { } return ((uint )mcs_table[(int )mcs].phy_rate_20); } } __inline static bool plcp3_issgi(u8 plcp ) { { return ((int )((signed char )plcp) < 0); } } __inline static u8 cck_rspec(u8 cck ) { { return ((unsigned int )cck & 127U); } } __inline static u8 cck_phy2mac_rate(u8 signal ) { { return ((u8 )((unsigned int )signal / 5U)); } } u8 brcms_c_antsel_antsel2id(struct antsel_info *asi , u16 antsel ) ; int brcms_c_txfifo(struct brcms_c_info *wlc , uint fifo , struct sk_buff *p ) ; int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw , uint fifo , uint *blocks ) ; u16 brcms_c_calc_lsig_len(struct brcms_c_info *wlc , u32 ratespec , uint mac_len ) ; u32 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc , u32 rspec , bool use_rspec , u16 mimo_ctlchbw ) ; u16 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc , bool cts_only , u32 rts_rate , u32 frame_rate , u8 rts_preamble_type , u8 frame_preamble_type , uint frame_len , bool ba ) ; void brcms_c_inval_dma_pkts(struct brcms_hardware *hw , struct ieee80211_sta *sta , void *dma_callback_fn ) ; void brcms_b_write_shm(struct brcms_hardware *wlc_hw , uint offset , u16 v ) ; u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw , uint offset ) ; void brcms_b_write_template_ram(struct brcms_hardware *wlc_hw , int offset , int len , void *buf ) ; void brcms_c_ampdu_reset_session(struct brcms_ampdu_session *session , struct brcms_c_info *wlc ) ; int brcms_c_ampdu_add_frame(struct brcms_ampdu_session *session , struct sk_buff *p ) ; void brcms_c_ampdu_finalize(struct brcms_ampdu_session *session ) ; struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc ) ; void brcms_c_ampdu_detach(struct ampdu_info *ampdu ) ; void brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu , struct scb *scb , struct sk_buff *p , struct tx_status *txs ) ; void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc ) ; void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu ) ; struct tracepoint __tracepoint_brcms_txdesc ; __inline static void trace_brcms_txdesc(struct device const *dev , void *txh , size_t txh_len ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_406 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_408 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false(& __tracepoint_brcms_txdesc.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_txdesc.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_tx.h", 38, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_55245: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct device const * , void * , size_t ))it_func))(__data, dev, txh, txh_len); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_55245; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_txdesc.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_tx.h", 38, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } static void brcms_c_scb_ampdu_update_max_txlen(struct ampdu_info *ampdu , u8 dur ) { u32 rate ; u32 mcs ; { mcs = 0U; goto ldv_55746; ldv_55745: rate = mcs_2_rate((int )((u8 )mcs), 0, 0); ampdu->max_txlen[mcs][0][0] = (u32 )dur * rate >> 3; rate = mcs_2_rate((int )((u8 )mcs), 1, 0); ampdu->max_txlen[mcs][1][0] = (u32 )dur * rate >> 3; rate = mcs_2_rate((int )((u8 )mcs), 0, 1); ampdu->max_txlen[mcs][0][1] = (u32 )dur * rate >> 3; rate = mcs_2_rate((int )((u8 )mcs), 1, 1); ampdu->max_txlen[mcs][1][1] = (u32 )dur * rate >> 3; mcs = mcs + 1U; ldv_55746: ; if (mcs <= 32U) { goto ldv_55745; } else { } return; } } static bool brcms_c_ampdu_cap(struct ampdu_info *ampdu ) { { if (((unsigned int )((ampdu->wlc)->band)->phytype == 4U || (unsigned int )((ampdu->wlc)->band)->phytype == 8U) || (unsigned int )((ampdu->wlc)->band)->phytype == 6U) { return (1); } else { return (0); } } } static int brcms_c_ampdu_set(struct ampdu_info *ampdu , bool on ) { struct brcms_c_info *wlc ; struct bcma_device *core ; bool tmp ; int tmp___0 ; { wlc = ampdu->wlc; core = (wlc->hw)->d11core; (wlc->pub)->_ampdu = 0; if ((int )on) { if (((int )(wlc->pub)->_n_enab & 3) == 0) { __brcms_err(& core->dev, "wl%d: driver not nmode enabled\n", (wlc->pub)->unit); return (-524); } else { } tmp = brcms_c_ampdu_cap(ampdu); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { __brcms_err(& core->dev, "wl%d: device not ampdu capable\n", (wlc->pub)->unit); return (-524); } else { } (wlc->pub)->_ampdu = on; } else { } return (0); } } static void brcms_c_ffpld_init(struct ampdu_info *ampdu ) { int i ; int j ; struct brcms_fifo_info *fifo ; { j = 0; goto ldv_55767; ldv_55766: fifo = (struct brcms_fifo_info *)(& ampdu->fifo_tb) + (unsigned long )j; fifo->ampdu_pld_size = 0U; i = 0; goto ldv_55764; ldv_55763: fifo->mcs2ampdu_table[i] = 255U; i = i + 1; ldv_55764: ; if (i <= 23) { goto ldv_55763; } else { } fifo->dmaxferrate = 0U; fifo->accum_txampdu = 0U; fifo->prev_txfunfl = 0U; fifo->accum_txfunfl = 0U; j = j + 1; ldv_55767: ; if (j <= 3) { goto ldv_55766; } else { } return; } } struct ampdu_info *brcms_c_ampdu_attach(struct brcms_c_info *wlc ) { struct ampdu_info *ampdu ; int i ; void *tmp ; { tmp = kzalloc(760UL, 32U); ampdu = (struct ampdu_info *)tmp; if ((unsigned long )ampdu == (unsigned long )((struct ampdu_info *)0)) { return ((struct ampdu_info *)0); } else { } ampdu->wlc = wlc; i = 0; goto ldv_55775; ldv_55774: ampdu->ini_enable[i] = 1U; i = i + 1; ldv_55775: ; if (i <= 7) { goto ldv_55774; } else { } ampdu->ini_enable[6] = 0U; ampdu->ini_enable[7] = 0U; ampdu->ini_enable[2] = 0U; ampdu->ini_enable[1] = 0U; ampdu->ba_tx_wsize = 64U; ampdu->ba_rx_wsize = 64U; ampdu->mpdu_density = 6U; ampdu->max_pdu = -1; ampdu->dur = 5U; ampdu->ffpld_rsvd = 2048U; if ((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->band)->phyrev <= 1U) { ampdu->rx_factor = 2U; } else { ampdu->rx_factor = 3U; } ampdu->retry_limit = 5U; ampdu->rr_retry_limit = 2U; i = 0; goto ldv_55778; ldv_55777: ampdu->retry_limit_tid[i] = ampdu->retry_limit; ampdu->rr_retry_limit_tid[i] = ampdu->rr_retry_limit; i = i + 1; ldv_55778: ; if (i <= 7) { goto ldv_55777; } else { } brcms_c_scb_ampdu_update_max_txlen(ampdu, (int )ampdu->dur); ampdu->mfbr = 0; brcms_c_ampdu_set(ampdu, (int )(wlc->pub)->_ampdu); ampdu->tx_max_funl = 200U; brcms_c_ffpld_init(ampdu); return (ampdu); } } void brcms_c_ampdu_detach(struct ampdu_info *ampdu ) { { kfree((void const *)ampdu); return; } } static void brcms_c_scb_ampdu_update_config(struct ampdu_info *ampdu , struct scb *scb ) { struct scb_ampdu *scb_ampdu ; int i ; u8 __min1 ; u8 __min2 ; u8 __min1___0 ; u8 __min2___0 ; u8 _min1 ; u8 _min2 ; { scb_ampdu = & scb->scb_ampdu; scb_ampdu->max_pdu = 16U; i = 0; goto ldv_55790; ldv_55789: ; if ((unsigned int )ampdu->fifo_tb[i].ampdu_pld_size > 1000U) { scb_ampdu->max_pdu = 16U; } else { } i = i + 1; ldv_55790: ; if (i <= 3) { goto ldv_55789; } else { } if ((int )ampdu->max_pdu != -1) { scb_ampdu->max_pdu = (unsigned char )ampdu->max_pdu; } else { } __min1 = scb_ampdu->max_pdu; __min2 = 20U; scb_ampdu->release = (u8 )((int )__min1 < (int )__min2 ? __min1 : __min2); if (scb_ampdu->max_rx_ampdu_bytes != 0U) { __min1___0 = scb_ampdu->release; __min2___0 = (u8 )(scb_ampdu->max_rx_ampdu_bytes / 1600U); scb_ampdu->release = (u8 )((int )__min1___0 < (int )__min2___0 ? __min1___0 : __min2___0); } else { } _min1 = scb_ampdu->release; _min2 = ampdu->fifo_tb[1].mcs2ampdu_table[23]; scb_ampdu->release = (u8 )((int )_min1 < (int )_min2 ? _min1 : _min2); return; } } static void brcms_c_scb_ampdu_update_config_all(struct ampdu_info *ampdu ) { { brcms_c_scb_ampdu_update_config(ampdu, & (ampdu->wlc)->pri_scb); return; } } static void brcms_c_ffpld_calc_mcs2ampdu_table(struct ampdu_info *ampdu , int f ) { int i ; u32 phy_rate ; u32 dma_rate ; u32 tmp ; u8 max_mpdu ; struct brcms_fifo_info *fifo ; u8 __min1 ; u8 __min2 ; uint tmp___0 ; u32 __min1___0 ; u32 __min2___0 ; { fifo = (struct brcms_fifo_info *)(& ampdu->fifo_tb) + (unsigned long )f; __min1 = fifo->mcs2ampdu_table[23]; __min2 = 16U; max_mpdu = (u8 )((int )__min1 < (int )__min2 ? __min1 : __min2); phy_rate = mcs_2_rate(23, 1, 0); dma_rate = (((phy_rate / 100U) * (u32 )((int )max_mpdu * 1800 - (int )fifo->ampdu_pld_size)) / (u32 )((int )max_mpdu * 1800)) * 100U; fifo->dmaxferrate = dma_rate; dma_rate = dma_rate >> 7; i = 0; goto ldv_55821; ldv_55820: tmp___0 = mcs_2_rate((int )((u8 )i), 1, 0); phy_rate = tmp___0 >> 7; if (phy_rate > dma_rate) { tmp = ((u32 )fifo->ampdu_pld_size * phy_rate) / ((phy_rate - dma_rate) * 1800U) + 1U; __min1___0 = tmp; __min2___0 = 255U; tmp = __min1___0 < __min2___0 ? __min1___0 : __min2___0; fifo->mcs2ampdu_table[i] = (unsigned char )tmp; } else { } i = i + 1; ldv_55821: ; if (i <= 22) { goto ldv_55820; } else { } return; } } static int brcms_c_ffpld_check_txfunfl(struct brcms_c_info *wlc , int fid ) { struct ampdu_info *ampdu ; u32 phy_rate ; uint tmp ; u32 txunfl_ratio ; u8 max_mpdu ; u32 current_ampdu_cnt ; u16 max_pld_size ; u32 new_txunfl ; struct brcms_fifo_info *fifo ; uint xmtfifo_sz___0 ; u16 cur_txunfl ; int tmp___0 ; u8 __min1 ; u8 __min2 ; { ampdu = wlc->ampdu; tmp = mcs_2_rate(23, 1, 0); phy_rate = tmp; current_ampdu_cnt = 0U; fifo = (struct brcms_fifo_info *)(& ampdu->fifo_tb) + (unsigned long )fid; cur_txunfl = brcms_b_read_shm(wlc->hw, (uint )((unsigned long )fid + 118UL) * 2U); new_txunfl = (u32 )((int )cur_txunfl - (int )fifo->prev_txfunfl); if (new_txunfl == 0U) { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_ffpld_check_txfunfl", "TX status FRAG set but no tx underflows\n"); return (-1); } else { } fifo->prev_txfunfl = cur_txunfl; if (ampdu->tx_max_funl == 0U) { return (1); } else { } tmp___0 = brcms_b_xmtfifo_sz_get(wlc->hw, (uint )fid, & xmtfifo_sz___0); if (tmp___0 != 0) { return (-1); } else { } if (xmtfifo_sz___0 * 256U <= ampdu->ffpld_rsvd) { return (1); } else { } max_pld_size = (unsigned int )((u16 )xmtfifo_sz___0) * 256U - (unsigned int )((u16 )ampdu->ffpld_rsvd); fifo->accum_txfunfl = fifo->accum_txfunfl + new_txunfl; if (fifo->accum_txfunfl <= 9U) { return (0); } else { } __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_ffpld_check_txfunfl", "ampdu_count %d tx_underflows %d\n", current_ampdu_cnt, fifo->accum_txfunfl); txunfl_ratio = current_ampdu_cnt / fifo->accum_txfunfl; if (ampdu->tx_max_funl < txunfl_ratio) { if (current_ampdu_cnt > 4999U) { fifo->accum_txfunfl = 0U; } else { } return (0); } else { } __min1 = fifo->mcs2ampdu_table[23]; __min2 = 16U; max_mpdu = (u8 )((int )__min1 < (int )__min2 ? __min1 : __min2); if ((int )fifo->ampdu_pld_size >= (int )max_mpdu * 1800) { fifo->accum_txfunfl = 0U; return (0); } else { } if ((int )fifo->ampdu_pld_size < (int )max_pld_size) { fifo->ampdu_pld_size = (unsigned int )fifo->ampdu_pld_size + 1000U; if ((int )fifo->ampdu_pld_size > (int )max_pld_size) { fifo->ampdu_pld_size = max_pld_size; } else { } brcms_c_scb_ampdu_update_config_all(ampdu); fifo->dmaxferrate = (((phy_rate / 100U) * (u32 )((int )max_mpdu * 1800 - (int )fifo->ampdu_pld_size)) / (u32 )((int )max_mpdu * 1800)) * 100U; __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_ffpld_check_txfunfl", "DMA estimated transfer rate %d; pre-load size %d\n", fifo->dmaxferrate, (int )fifo->ampdu_pld_size); } else if ((unsigned int )fifo->mcs2ampdu_table[23] > 1U) { if ((unsigned int )fifo->mcs2ampdu_table[23] == 255U) { fifo->mcs2ampdu_table[23] = 15U; } else { fifo->mcs2ampdu_table[23] = (unsigned int )fifo->mcs2ampdu_table[23] + 255U; } brcms_c_ffpld_calc_mcs2ampdu_table(ampdu, fid); brcms_c_scb_ampdu_update_config_all(ampdu); } else { } fifo->accum_txfunfl = 0U; return (0); } } void brcms_c_ampdu_tx_operational(struct brcms_c_info *wlc , u8 tid , u8 ba_wsize , uint max_rx_ampdu_bytes ) { struct scb_ampdu *scb_ampdu ; struct scb_ampdu_tid_ini *ini ; struct ampdu_info *ampdu ; struct scb *scb ; { ampdu = wlc->ampdu; scb = & wlc->pri_scb; scb_ampdu = & scb->scb_ampdu; if ((unsigned int )ampdu->ini_enable[(int )tid] == 0U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "%s: Rejecting tid %d\n", "brcms_c_ampdu_tx_operational", (int )tid); return; } else { } ini = (struct scb_ampdu_tid_ini *)(& scb_ampdu->ini) + (unsigned long )tid; ini->tid = tid; ini->scb = scb_ampdu->scb; ini->ba_wsize = ba_wsize; scb_ampdu->max_rx_ampdu_bytes = max_rx_ampdu_bytes; return; } } void brcms_c_ampdu_reset_session(struct brcms_ampdu_session *session , struct brcms_c_info *wlc ) { { session->wlc = wlc; skb_queue_head_init(& session->skb_list); session->max_ampdu_len = 0U; session->max_ampdu_frames = 0U; session->ampdu_len = 0U; session->dma_len = 0U; return; } } int brcms_c_ampdu_add_frame(struct brcms_ampdu_session *session , struct sk_buff *p ) { struct brcms_c_info *wlc ; struct ampdu_info *ampdu ; struct scb *scb ; struct scb_ampdu *scb_ampdu ; struct ieee80211_tx_info *tx_info ; struct ieee80211_tx_info *tmp ; struct ieee80211_tx_rate *txrate ; struct d11txh *txh ; unsigned int ampdu_frames ; u8 ndelim ; u8 tid ; u8 *plcp ; uint len ; u16 mcl ; bool fbr_iscck ; bool rr ; int __y ; struct sk_buff *first ; u8 plcp0 ; u8 plcp3 ; u8 is40 ; u8 sgi ; u8 mcs ; uint fifo ; struct brcms_fifo_info *f ; bool tmp___0 ; u32 _min1 ; u32 _min2 ; u16 __min1 ; u16 __min2 ; uint tmp___1 ; { wlc = session->wlc; ampdu = wlc->ampdu; scb = & wlc->pri_scb; scb_ampdu = & scb->scb_ampdu; tmp = IEEE80211_SKB_CB(p); tx_info = tmp; txrate = (struct ieee80211_tx_rate *)(& tx_info->__annonCompField103.status.rates); txh = (struct d11txh *)p->data; ndelim = txh->RTSPLCPFallback[5]; plcp = (u8 *)txh + 1U; fbr_iscck = ((int )txh->XtraFrameTypes & 3) == 0; len = (uint )((int )fbr_iscck ? (int )txh->FragPLCPFallback[4] + ((int )txh->FragPLCPFallback[5] << 8) : (int )txh->FragPLCPFallback[1] + ((int )txh->FragPLCPFallback[2] << 8)); __y = 4; len = ((((uint )__y + len) + 4294967295U) / (uint )__y) * (uint )__y + (uint )(((int )ndelim + 1) * 4); ampdu_frames = skb_queue_len((struct sk_buff_head const *)(& session->skb_list)); if (ampdu_frames != 0U) { if (ampdu_frames + 1U > (unsigned int )session->max_ampdu_frames || (uint )session->ampdu_len + len > session->max_ampdu_len) { return (-28); } else { } first = skb_peek((struct sk_buff_head const *)(& session->skb_list)); if (p->priority != first->priority) { return (-28); } else { } } else { } session->ampdu_len = (int )session->ampdu_len + (int )((u16 )len); session->dma_len = (int )session->dma_len + (int )((u16 )p->len); tid = (unsigned char )p->priority; if ((int )txrate->count <= (int )ampdu->rr_retry_limit_tid[(int )tid]) { txrate->count = (unsigned char )((int )txrate->count + 1); rr = 1; } else { (txrate + 1UL)->count = (unsigned char )((int )(txrate + 1UL)->count + 1); rr = 0; } if (ampdu_frames == 0U) { fifo = (uint )txh->TxFrameID & 7U; f = (struct brcms_fifo_info *)(& ampdu->fifo_tb) + (unsigned long )fifo; if ((int )rr) { plcp0 = *plcp; plcp3 = *(plcp + 3UL); } else { plcp0 = txh->FragPLCPFallback[0]; plcp3 = txh->FragPLCPFallback[3]; } is40 = (int )((signed char )plcp0) < 0; tmp___0 = plcp3_issgi((int )plcp3); sgi = (u8 )tmp___0; mcs = (unsigned int )plcp0 & 127U; _min1 = scb_ampdu->max_rx_ampdu_bytes; _min2 = ampdu->max_txlen[(int )mcs][(int )is40][(int )sgi]; session->max_ampdu_len = _min1 < _min2 ? _min1 : _min2; session->max_ampdu_frames = (u16 )scb_ampdu->max_pdu; tmp___1 = mcs_2_rate((int )mcs, 1, 0); if (tmp___1 >= f->dmaxferrate) { __min1 = (u16 )f->mcs2ampdu_table[(int )mcs]; __min2 = session->max_ampdu_frames; session->max_ampdu_frames = (u16 )((int )__min1 < (int )__min2 ? __min1 : __min2); } else { } } else { } mcl = txh->MacTxControlLow; mcl = (unsigned int )mcl & 63999U; mcl = (u16 )((unsigned int )mcl | 1024U); mcl = (unsigned int )mcl & 63475U; txh->MacTxControlLow = mcl; txh->PreloadSize = 0U; skb_queue_tail(& session->skb_list, p); return (0); } } void brcms_c_ampdu_finalize(struct brcms_ampdu_session *session ) { struct brcms_c_info *wlc ; struct ampdu_info *ampdu ; struct sk_buff *first ; struct sk_buff *last ; struct d11txh *txh ; struct ieee80211_tx_info *tx_info ; struct ieee80211_tx_rate *txrate ; u8 ndelim ; u8 *plcp ; uint len ; uint fifo ; struct brcms_fifo_info *f ; u16 mcl ; bool fbr ; bool fbr_iscck ; struct ieee80211_rts *rts ; bool use_rts ; bool use_cts ; u16 dma_len ; u16 mimo_ctlchbw ; u32 rspec ; u32 rspec_fallback ; u32 rts_rspec ; u32 rts_rspec_fallback ; u8 plcp0 ; u8 plcp3 ; u8 is40 ; u8 sgi ; u8 mcs ; u16 mch ; u8 preamble_type ; u8 fbr_preamble_type ; u8 rts_preamble_type ; u8 rts_fbr_preamble_type ; int tmp ; int __y ; int tmp___0 ; int tmp___1 ; bool tmp___2 ; u16 tmp___3 ; u8 tmp___4 ; u8 tmp___5 ; u16 mmodelen ; u16 tmp___6 ; u16 mmfbrlen ; u16 tmp___7 ; u16 _min1 ; u16 _min2 ; uint tmp___8 ; u16 durid ; __u32 tmp___9 ; { wlc = session->wlc; ampdu = wlc->ampdu; use_rts = 0; use_cts = 0; dma_len = session->dma_len; mimo_ctlchbw = 2U; rspec = 0U; rspec_fallback = 0U; rts_rspec = 0U; rts_rspec_fallback = 0U; preamble_type = 2U; fbr_preamble_type = 2U; rts_preamble_type = 0U; rts_fbr_preamble_type = 0U; tmp = skb_queue_empty((struct sk_buff_head const *)(& session->skb_list)); if (tmp != 0) { return; } else { } first = skb_peek((struct sk_buff_head const *)(& session->skb_list)); last = skb_peek_tail((struct sk_buff_head const *)(& session->skb_list)); txh = (struct d11txh *)last->data; fifo = (uint )txh->TxFrameID & 7U; f = (struct brcms_fifo_info *)(& ampdu->fifo_tb) + (unsigned long )fifo; mcl = txh->MacTxControlLow; mcl = (unsigned int )mcl & 63999U; mcl = (u16 )((unsigned int )mcl | 1536U); txh->MacTxControlLow = mcl; ndelim = txh->RTSPLCPFallback[5]; txh->RTSPLCPFallback[5] = 0U; session->ampdu_len = (unsigned int )session->ampdu_len + (unsigned int )((u16 )ndelim) * 65532U; fbr_iscck = ((int )txh->XtraFrameTypes & 3) == 0; len = (uint )((int )fbr_iscck ? (int )txh->FragPLCPFallback[4] + ((int )txh->FragPLCPFallback[5] << 8) : (int )txh->FragPLCPFallback[1] + ((int )txh->FragPLCPFallback[2] << 8)); __y = 4; session->ampdu_len = (int )session->ampdu_len + ((int )((u16 )len) - (int )((u16 )(((((uint )__y + len) + 4294967295U) / (uint )__y) * (uint )__y))); tx_info = IEEE80211_SKB_CB(first); txrate = (struct ieee80211_tx_rate *)(& tx_info->__annonCompField103.status.rates); txh = (struct d11txh *)first->data; plcp = (u8 *)txh + 1U; rts = & txh->rts_frame; mcl = txh->MacTxControlLow; if ((unsigned long )first != (unsigned long )last) { mcl = (unsigned int )mcl & 63999U; mcl = (u16 )((unsigned int )mcl | 512U); } else { } mcl = (u16 )((unsigned int )mcl | 8U); tmp___0 = ieee80211_is_rts((int )rts->frame_control); if (tmp___0 != 0) { mcl = (u16 )((unsigned int )mcl | 4U); use_rts = 1; } else { } tmp___1 = ieee80211_is_cts((int )rts->frame_control); if (tmp___1 != 0) { mcl = (u16 )((unsigned int )mcl | 2048U); use_cts = 1; } else { } txh->MacTxControlLow = mcl; fbr = (int )(txrate + 1UL)->count > 0; if (! fbr) { plcp0 = *plcp; plcp3 = *(plcp + 3UL); } else { plcp0 = txh->FragPLCPFallback[0]; plcp3 = txh->FragPLCPFallback[3]; } is40 = (int )((signed char )plcp0) < 0; tmp___2 = plcp3_issgi((int )plcp3); sgi = (u8 )tmp___2; mcs = (unsigned int )plcp0 & 127U; if ((unsigned int )is40 != 0U) { tmp___3 = wlc_phy_chanspec_get((wlc->band)->pi); if (((int )tmp___3 & 768) == 512) { mimo_ctlchbw = 3U; } else { mimo_ctlchbw = 2U; } } else { } rspec = 134217728U; rspec = ((u32 )*plcp & 4294967167U) | rspec; if ((int )((signed char )*plcp) < 0) { rspec = rspec | 1024U; } else { } fbr_iscck = ((int )txh->XtraFrameTypes & 3) == 0; if ((int )fbr_iscck) { tmp___4 = cck_phy2mac_rate((int )txh->FragPLCPFallback[0]); tmp___5 = cck_rspec((int )tmp___4); rspec_fallback = (u32 )tmp___5; } else { rspec_fallback = 134217728U; rspec_fallback = ((u32 )txh->FragPLCPFallback[0] & 4294967167U) | rspec_fallback; if ((int )((signed char )txh->FragPLCPFallback[0]) < 0) { rspec_fallback = rspec_fallback | 1024U; } else { } } if ((int )use_rts || (int )use_cts) { rts_rspec = brcms_c_rspec_to_rts_rspec(wlc, rspec, 0, (int )mimo_ctlchbw); rts_rspec_fallback = brcms_c_rspec_to_rts_rspec(wlc, rspec_fallback, 0, (int )mimo_ctlchbw); } else { } *(plcp + 1UL) = (u8 )session->ampdu_len; *(plcp + 2UL) = (u8 )((int )session->ampdu_len >> 8); *(plcp + 3UL) = (u8 )((unsigned int )*(plcp + 3UL) | 8U); if ((unsigned int )txh->MModeLen != 0U) { tmp___6 = brcms_c_calc_lsig_len(wlc, rspec, (uint )session->ampdu_len); mmodelen = tmp___6; txh->MModeLen = mmodelen; preamble_type = 4U; } else { } if ((unsigned int )txh->MModeFbrLen != 0U) { tmp___7 = brcms_c_calc_lsig_len(wlc, rspec_fallback, (uint )session->ampdu_len); mmfbrlen = tmp___7; txh->MModeFbrLen = mmfbrlen; fbr_preamble_type = 4U; } else { } tmp___8 = mcs_2_rate((int )mcs, 1, 0); if (tmp___8 >= f->dmaxferrate) { _min1 = dma_len; _min2 = f->ampdu_pld_size; dma_len = (u16 )((int )_min1 < (int )_min2 ? _min1 : _min2); txh->PreloadSize = dma_len; } else { txh->PreloadSize = 0U; } mch = txh->MacTxControlHigh; if ((int )use_rts || (int )use_cts) { if (((int )mch & 16384) != 0) { rts_preamble_type = 1U; } else { } if ((int )((short )mch) < 0) { rts_fbr_preamble_type = 1U; } else { } durid = brcms_c_compute_rtscts_dur(wlc, (int )use_cts, rts_rspec, rspec, (int )rts_preamble_type, (int )preamble_type, (uint )session->ampdu_len, 1); rts->duration = durid; durid = brcms_c_compute_rtscts_dur(wlc, (int )use_cts, rts_rspec_fallback, rspec_fallback, (int )rts_fbr_preamble_type, (int )fbr_preamble_type, (uint )session->ampdu_len, 1); txh->RTSDurFallback = durid; txh->TxFesTimeNormal = rts->duration; txh->TxFesTimeFallback = txh->RTSDurFallback; } else { } if ((int )fbr) { mch = (u16 )((unsigned int )mch | 4096U); txh->MacTxControlHigh = mch; *(plcp + 3UL) = (u8 )((unsigned int )*(plcp + 3UL) | 8U); txh->FragPLCPFallback[3] = (u8 )((unsigned int )txh->FragPLCPFallback[3] | 8U); } else { } tmp___9 = skb_queue_len((struct sk_buff_head const *)(& session->skb_list)); __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_ampdu_finalize", "wl%d: count %d ampdu_len %d\n", (wlc->pub)->unit, tmp___9, (int )session->ampdu_len); return; } } static void brcms_c_ampdu_rate_status(struct brcms_c_info *wlc , struct ieee80211_tx_info *tx_info , struct tx_status *txs , u8 mcs ) { struct ieee80211_tx_rate *txrate ; int i ; { txrate = (struct ieee80211_tx_rate *)(& tx_info->__annonCompField103.status.rates); i = 2; goto ldv_55946; ldv_55945: (txrate + (unsigned long )i)->idx = -1; (txrate + (unsigned long )i)->count = 0U; i = i + 1; ldv_55946: ; if (i <= 3) { goto ldv_55945; } else { } return; } } static void brcms_c_ampdu_dotxstatus_complete(struct ampdu_info *ampdu , struct scb *scb , struct sk_buff *p , struct tx_status *txs , u32 s1 , u32 s2 ) { struct scb_ampdu *scb_ampdu ; struct brcms_c_info *wlc ; struct scb_ampdu_tid_ini *ini ; u8 bitmap[8U] ; u8 queue ; u8 tid ; struct d11txh *txh ; u8 *plcp ; struct ieee80211_hdr *h ; u16 seq ; u16 start_seq ; u16 bindex ; u16 index ; u16 mcl ; u8 mcs ; bool ba_recd ; bool ack_recd ; u8 suc_mpdu ; u8 tot_mpdu ; uint supr_status ; bool update_rate ; bool retry ; bool tx_error ; u16 mimoantsel ; u8 antselid ; u8 retry_limit ; u8 rr_retry_limit ; struct ieee80211_tx_info *tx_info ; struct ieee80211_tx_info *tmp ; int __ret_warn_on ; long tmp___0 ; int __ret_warn_on___0 ; long tmp___1 ; int __ret_warn_on___1 ; long tmp___2 ; int tmp___3 ; u8 tmp___4 ; int ret ; bool __warned ; int __ret_warn_once ; int __ret_warn_on___2 ; long tmp___5 ; long tmp___6 ; long tmp___7 ; { wlc = ampdu->wlc; start_seq = 0U; mcs = 0U; ba_recd = 0; ack_recd = 0; suc_mpdu = 0U; tot_mpdu = 0U; update_rate = 1; retry = 1; tx_error = 0; mimoantsel = 0U; antselid = 0U; tmp = IEEE80211_SKB_CB(p); tx_info = tmp; scb_ampdu = & scb->scb_ampdu; tid = (unsigned char )p->priority; ini = (struct scb_ampdu_tid_ini *)(& scb_ampdu->ini) + (unsigned long )tid; retry_limit = ampdu->retry_limit_tid[(int )tid]; rr_retry_limit = ampdu->rr_retry_limit_tid[(int )tid]; memset((void *)(& bitmap), 0, 8UL); queue = (unsigned int )((u8 )txs->frameid) & 7U; supr_status = (uint )txs->status & 28U; if (((int )txs->status & 2) != 0) { if (supr_status == 24U) { update_rate = 0; } else { } __ret_warn_on = ((int )txs->status & 64) == 0; tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c", 878); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); start_seq = (u16 )((int )txs->sequence >> 4); bitmap[0] = (u8 )((int )txs->status >> 12); __ret_warn_on___0 = (s1 & 64U) != 0U; tmp___1 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c", 883); } else { } ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); __ret_warn_on___1 = (s1 & 32U) == 0U; tmp___2 = ldv__builtin_expect(__ret_warn_on___1 != 0, 0L); if (tmp___2 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c", 884); } else { } ldv__builtin_expect(__ret_warn_on___1 != 0, 0L); bitmap[0] = (unsigned int )bitmap[0] | (((unsigned int )((u8 )s1) & 30U) << 3U); bitmap[1] = (u8 )(s1 >> 8); bitmap[2] = (u8 )(s1 >> 16); bitmap[3] = (u8 )(s1 >> 24); bitmap[4] = (u8 )s2; bitmap[5] = (u8 )(s2 >> 8); bitmap[6] = (u8 )(s2 >> 16); bitmap[7] = (u8 )(s2 >> 24); ba_recd = 1; } else if (supr_status != 0U) { update_rate = 0; if (supr_status == 16U) { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_ampdu_dotxstatus_complete", "%s: Pkt tx suppressed, illegal channel possibly %d\n", "brcms_c_ampdu_dotxstatus_complete", (int )((unsigned char )(wlc->default_bss)->chanspec)); } else if (supr_status != 12U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "%s: supr_status 0x%x\n", "brcms_c_ampdu_dotxstatus_complete", supr_status); } else { } if (supr_status == 16U || supr_status == 20U) { retry = 0; } else if (supr_status == 20U) { } else if (supr_status == 12U) { tmp___3 = brcms_c_ffpld_check_txfunfl(wlc, (int )queue); if (tmp___3 > 0) { tx_error = 1; } else { } } else { } } else if ((unsigned int )txs->phyerr != 0U) { update_rate = 0; __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_ampdu_dotxstatus_complete", "%s: ampdu tx phy error (0x%x)\n", "brcms_c_ampdu_dotxstatus_complete", (int )txs->phyerr); } else { } goto ldv_55999; ldv_55998: tx_info = IEEE80211_SKB_CB(p); txh = (struct d11txh *)p->data; mcl = txh->MacTxControlLow; plcp = (u8 *)txh + 1U; h = (struct ieee80211_hdr *)plcp + 6U; seq = (u16 )((int )h->seq_ctrl >> 4); trace_brcms_txdesc((struct device const *)(& ((wlc->hw)->d11core)->dev), (void *)txh, 112UL); if ((unsigned int )tot_mpdu == 0U) { mcs = (unsigned int )*plcp & 127U; mimoantsel = txh->ABI_MimoAntSel; } else { } index = (unsigned int )seq & 63U; ack_recd = 0; if ((int )ba_recd) { bindex = (unsigned int )((u16 )((int )seq - (int )start_seq)) & 4095U; __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_ampdu_dotxstatus_complete", "tid %d seq %d, start_seq %d, bindex %d set %d, index %d\n", (int )tid, (int )seq, (int )start_seq, (int )bindex, (int )*((u8 const *)(& bitmap) + (unsigned long )((unsigned int )bindex / 8U)) & (1 << ((int )bindex & 7)), (int )index); if ((unsigned int )bindex <= 63U && ((int )*((u8 const *)(& bitmap) + (unsigned long )((unsigned int )bindex / 8U)) >> ((int )bindex & 7)) & 1) { ini->txretry[(int )index] = 0U; brcms_c_ampdu_rate_status(wlc, tx_info, txs, (int )mcs); tx_info->flags = tx_info->flags | 512U; tx_info->flags = tx_info->flags | 1024U; tmp___4 = 1U; tx_info->__annonCompField103.status.ampdu_len = tmp___4; tx_info->__annonCompField103.status.ampdu_ack_len = tmp___4; skb_pull(p, 6U); skb_pull(p, 112U); ieee80211_tx_status_irqsafe((wlc->pub)->ieee_hw, p); ack_recd = 1; suc_mpdu = (u8 )((int )suc_mpdu + 1); } else { } } else { } if (! ack_recd) { if ((int )retry && (int )ini->txretry[(int )index] < (int )retry_limit) { ini->txretry[(int )index] = (u8 )((int )ini->txretry[(int )index] + 1); ret = brcms_c_txfifo(wlc, (uint )queue, p); __ret_warn_once = ret != 0; tmp___7 = ldv__builtin_expect(__ret_warn_once != 0, 0L); if (tmp___7 != 0L) { __ret_warn_on___2 = ! __warned; tmp___5 = ldv__builtin_expect(__ret_warn_on___2 != 0, 0L); if (tmp___5 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/ampdu.c", 998, "queue %d out of txds\n", (int )queue); } else { } tmp___6 = ldv__builtin_expect(__ret_warn_on___2 != 0, 0L); if (tmp___6 != 0L) { __warned = 1; } else { } } else { } ldv__builtin_expect(__ret_warn_once != 0, 0L); } else { ieee80211_tx_info_clear_status(tx_info); tx_info->__annonCompField103.status.ampdu_ack_len = 0U; tx_info->__annonCompField103.status.ampdu_len = 1U; tx_info->flags = tx_info->flags | 2048U; skb_pull(p, 6U); skb_pull(p, 112U); __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_ampdu_dotxstatus_complete", "BA Timeout, seq %d\n", (int )seq); ieee80211_tx_status_irqsafe((wlc->pub)->ieee_hw, p); } } else { } tot_mpdu = (u8 )((int )tot_mpdu + 1); if (((int )mcl & 1536) >> 9 == 3) { goto ldv_55997; } else { } p = dma_getnexttxp((wlc->hw)->di[(int )queue], 2); ldv_55999: ; if ((unsigned long )p != (unsigned long )((struct sk_buff *)0)) { goto ldv_55998; } else { } ldv_55997: antselid = brcms_c_antsel_antsel2id(wlc->asi, (int )mimoantsel); return; } } void brcms_c_ampdu_dotxstatus(struct ampdu_info *ampdu , struct scb *scb , struct sk_buff *p , struct tx_status *txs ) { struct scb_ampdu *scb_ampdu ; struct brcms_c_info *wlc ; struct scb_ampdu_tid_ini *ini ; u32 s1 ; u32 s2 ; struct ieee80211_tx_info *tx_info ; u8 status_delay ; u8 queue ; struct d11txh *txh ; u16 mcl ; { wlc = ampdu->wlc; s1 = 0U; s2 = 0U; tx_info = IEEE80211_SKB_CB(p); if (((int )txs->status & 2) != 0) { status_delay = 0U; s1 = bcma_read32((wlc->hw)->d11core, 368); goto ldv_56014; ldv_56013: __const_udelay(4295UL); status_delay = (u8 )((int )status_delay + 1); if ((unsigned int )status_delay > 10U) { return; } else { } s1 = bcma_read32((wlc->hw)->d11core, 368); ldv_56014: ; if ((s1 & 1U) == 0U) { goto ldv_56013; } else { } s2 = bcma_read32((wlc->hw)->d11core, 372); } else { } if ((unsigned long )scb != (unsigned long )((struct scb *)0)) { scb_ampdu = & scb->scb_ampdu; ini = (struct scb_ampdu_tid_ini *)(& scb_ampdu->ini) + (unsigned long )p->priority; brcms_c_ampdu_dotxstatus_complete(ampdu, scb, p, txs, s1, s2); } else { queue = (unsigned int )((u8 )txs->frameid) & 7U; goto ldv_56021; ldv_56020: tx_info = IEEE80211_SKB_CB(p); txh = (struct d11txh *)p->data; trace_brcms_txdesc((struct device const *)(& ((wlc->hw)->d11core)->dev), (void *)txh, 112UL); mcl = txh->MacTxControlLow; brcmu_pkt_buf_free_skb(p); if (((int )mcl & 1536) >> 9 == 3) { goto ldv_56019; } else { } p = dma_getnexttxp((wlc->hw)->di[(int )queue], 2); ldv_56021: ; if ((unsigned long )p != (unsigned long )((struct sk_buff *)0)) { goto ldv_56020; } else { } ldv_56019: ; } return; } } void brcms_c_ampdu_macaddr_upd(struct brcms_c_info *wlc ) { char template[8U] ; { memset((void *)(& template), 0, 8UL); memcpy((void *)(& template), (void const *)(& (wlc->pub)->cur_etheraddr), 6UL); brcms_b_write_template_ram(wlc->hw, 72, 8, (void *)(& template)); return; } } bool brcms_c_aggregatable(struct brcms_c_info *wlc , u8 tid ) { { return ((unsigned int )(wlc->ampdu)->ini_enable[(int )tid] != 0U); } } void brcms_c_ampdu_shm_upd(struct ampdu_info *ampdu ) { struct brcms_c_info *wlc ; { wlc = ampdu->wlc; if (((int )ampdu->rx_factor & 3) == 3) { brcms_b_write_shm(wlc->hw, 186U, 65535); brcms_b_write_shm(wlc->hw, 60U, 10); } else { brcms_b_write_shm(wlc->hw, 186U, 32768); brcms_b_write_shm(wlc->hw, 60U, 5); } return; } } static void dma_cb_fn_ampdu(void *txi , void *arg_a ) { struct ieee80211_sta *sta ; struct ieee80211_tx_info *tx_info ; { sta = (struct ieee80211_sta *)arg_a; tx_info = (struct ieee80211_tx_info *)txi; if ((tx_info->flags & 64U) != 0U && ((unsigned long )tx_info->__annonCompField103.__annonCompField102.rate_driver_data[0] == (unsigned long )((void *)sta) || (unsigned long )sta == (unsigned long )((struct ieee80211_sta *)0))) { tx_info->__annonCompField103.__annonCompField102.rate_driver_data[0] = (void *)0; } else { } return; } } void brcms_c_ampdu_flush(struct brcms_c_info *wlc , struct ieee80211_sta *sta , u16 tid ) { { brcms_c_inval_dma_pkts(wlc->hw, sta, (void *)(& dma_cb_fn_ampdu)); return; } } bool ldv_queue_work_on_45(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_46(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_47(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_48(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_49(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_59(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_61(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_60(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_63(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_62(struct workqueue_struct *ldv_func_arg1 ) ; void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw , u8 antsel_type ) ; struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc ) ; void brcms_c_antsel_detach(struct antsel_info *asi ) ; void brcms_c_antsel_init(struct antsel_info *asi ) ; void brcms_c_antsel_antcfg_get(struct antsel_info *asi , bool usedef , bool sel , u8 antselid , u8 fbantselid , u8 *antcfg , u8 *fbantcfg ) ; static u16 const mimo_2x4_div_antselpat_tbl[16U] = { 0U, 0U, 9U, 10U, 0U, 0U, 5U, 6U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u8 const mimo_2x4_div_antselid_tbl[16U] = { 0U, 0U, 0U, 0U, 0U, 2U, 3U, 0U, 0U, 0U, 1U, 0U, 0U, 0U, 0U, 0U}; static u16 const mimo_2x3_div_antselpat_tbl[16U] = { 16U, 0U, 1U, 16U, 16U, 16U, 16U, 16U, 16U, 2U, 16U, 16U, 16U, 16U, 16U, 16U}; static u8 const mimo_2x3_div_antselid_tbl[16U] = { 0U, 1U, 2U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static void brcms_c_antsel_init_cfg(struct antsel_info *asi , struct brcms_antselcfg *antsel , bool auto_sel ) { u8 antcfg_def ; { if ((unsigned int )asi->antsel_type == 2U) { antcfg_def = (int )asi->antsel_avail && (int )auto_sel ? 129U : 1U; antsel->ant_config[2] = antcfg_def; antsel->ant_config[0] = antcfg_def; antsel->ant_config[3] = antcfg_def; antsel->ant_config[1] = antcfg_def; antsel->num_antcfg = 3U; } else if ((unsigned int )asi->antsel_type == 1U) { antsel->ant_config[2] = 2U; antsel->ant_config[0] = 2U; antsel->ant_config[3] = 2U; antsel->ant_config[1] = 2U; antsel->num_antcfg = 4U; } else { antsel->ant_config[2] = 1U; antsel->ant_config[0] = 1U; antsel->ant_config[3] = 1U; antsel->ant_config[1] = 1U; antsel->num_antcfg = 0U; } return; } } struct antsel_info *brcms_c_antsel_attach(struct brcms_c_info *wlc ) { struct antsel_info *asi ; struct ssb_sprom *sprom ; void *tmp ; { sprom = & (((wlc->hw)->d11core)->bus)->sprom; tmp = kzalloc(32UL, 32U); asi = (struct antsel_info *)tmp; if ((unsigned long )asi == (unsigned long )((struct antsel_info *)0)) { return ((struct antsel_info *)0); } else { } asi->wlc = wlc; asi->pub = wlc->pub; asi->antsel_type = 0U; asi->antsel_avail = 0; asi->antsel_antswitch = sprom->antswitch; if ((unsigned int )(asi->pub)->sromrev > 3U && (unsigned int )asi->antsel_antswitch != 0U) { switch ((int )asi->antsel_antswitch) { case 1: ; case 2: ; case 3: asi->antsel_type = 2U; if ((unsigned int )sprom->ant_available_bg == 7U || (unsigned int )sprom->ant_available_a == 7U) { asi->antsel_avail = 1; } else if ((unsigned int )sprom->ant_available_bg == 3U || (unsigned int )sprom->ant_available_a == 3U) { asi->antsel_avail = 0; } else { asi->antsel_avail = 0; __brcms_err(& ((wlc->hw)->d11core)->dev, "antsel_attach: 2o3 board cfg invalid\n"); } goto ldv_54624; default: ; goto ldv_54624; } ldv_54624: ; } else if (((unsigned int )(asi->pub)->sromrev == 4U && (unsigned int )sprom->ant_available_bg == 7U) && (unsigned int )sprom->ant_available_a == 0U) { asi->antsel_type = 2U; asi->antsel_avail = 1; } else if (((asi->pub)->boardflags2 & 8U) != 0U) { asi->antsel_type = 1U; asi->antsel_avail = 1; } else { } brcms_b_antsel_type_set(wlc->hw, (int )asi->antsel_type); brcms_c_antsel_init_cfg(asi, & asi->antcfg_11n, 1); brcms_c_antsel_init_cfg(asi, & asi->antcfg_cur, 1); return (asi); } } void brcms_c_antsel_detach(struct antsel_info *asi ) { { kfree((void const *)asi); return; } } static u16 brcms_c_antsel_antcfg2antsel(struct antsel_info *asi , u8 ant_cfg ) { u8 idx ; u16 mimo_antsel ; { idx = (((unsigned int )((u8 )(((int )ant_cfg & 51) >> 4)) & 15U) << 2U) + ((unsigned int )ant_cfg & 3U); mimo_antsel = 0U; if ((unsigned int )asi->antsel_type == 1U) { mimo_antsel = (unsigned int )((u16 )mimo_2x4_div_antselpat_tbl[(int )idx]) & 15U; return (mimo_antsel); } else if ((unsigned int )asi->antsel_type == 2U) { mimo_antsel = (unsigned int )((u16 )mimo_2x3_div_antselpat_tbl[(int )idx]) & 15U; return (mimo_antsel); } else { } return (mimo_antsel); } } static int brcms_c_antsel_cfgupd(struct antsel_info *asi , struct brcms_antselcfg *antsel ) { struct brcms_c_info *wlc ; u8 ant_cfg ; u16 mimo_antsel ; { wlc = asi->wlc; ant_cfg = antsel->ant_config[2]; mimo_antsel = brcms_c_antsel_antcfg2antsel(asi, (int )ant_cfg); brcms_b_write_shm(wlc->hw, 200U, (int )mimo_antsel); asi->antcfg_cur.ant_config[2] = ant_cfg; ant_cfg = antsel->ant_config[3]; mimo_antsel = brcms_c_antsel_antcfg2antsel(asi, (int )ant_cfg); brcms_b_write_shm(wlc->hw, 198U, (int )mimo_antsel); asi->antcfg_cur.ant_config[3] = ant_cfg; return (0); } } void brcms_c_antsel_init(struct antsel_info *asi ) { { if ((unsigned int )asi->antsel_type == 2U || (unsigned int )asi->antsel_type == 1U) { brcms_c_antsel_cfgupd(asi, & asi->antcfg_11n); } else { } return; } } static u8 brcms_c_antsel_id2antcfg(struct antsel_info *asi , u8 id ) { u8 antcfg ; { antcfg = 1U; if ((unsigned int )asi->antsel_type == 1U) { antcfg = (u8 )((int )((signed char )(((int )id & 2) << 3)) | (int )((signed char )(((unsigned int )id & 1U) + 2U))); return (antcfg); } else if ((unsigned int )asi->antsel_type == 2U) { antcfg = (u8 )((int )((signed char )(((int )id & 2) << 4)) | (int )((signed char )(((unsigned int )id & 1U) + 1U))); return (antcfg); } else { } return (antcfg); } } void brcms_c_antsel_antcfg_get(struct antsel_info *asi , bool usedef , bool sel , u8 antselid , u8 fbantselid , u8 *antcfg , u8 *fbantcfg ) { u8 ant ; { if ((int )usedef) { *antcfg = asi->antcfg_11n.ant_config[2]; *fbantcfg = *antcfg; return; } else { } if (! sel) { *antcfg = asi->antcfg_11n.ant_config[0]; *fbantcfg = *antcfg; } else { ant = asi->antcfg_11n.ant_config[0]; if ((int )((signed char )ant) < 0) { *antcfg = brcms_c_antsel_id2antcfg(asi, (int )antselid); *fbantcfg = brcms_c_antsel_id2antcfg(asi, (int )fbantselid); } else { *antcfg = asi->antcfg_11n.ant_config[0]; *fbantcfg = *antcfg; } } return; } } u8 brcms_c_antsel_antsel2id(struct antsel_info *asi , u16 antsel ) { u8 antselid ; { antselid = 0U; if ((unsigned int )asi->antsel_type == 1U) { antselid = mimo_2x4_div_antselid_tbl[(int )antsel & 15]; return (antselid); } else if ((unsigned int )asi->antsel_type == 2U) { antselid = mimo_2x3_div_antselid_tbl[(int )antsel & 15]; return (antselid); } else { } return (antselid); } } bool ldv_queue_work_on_59(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_60(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_61(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_62(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_63(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; bool ldv_is_err(void const *ptr ) ; extern int strcmp(char const * , char const * ) ; extern char *strncpy(char * , char const * , __kernel_size_t ) ; extern int strncmp(char const * , char const * , __kernel_size_t ) ; __inline static bool IS_ERR(void const *ptr ) ; bool ldv_queue_work_on_73(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_75(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_74(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_77(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_76(struct workqueue_struct *ldv_func_arg1 ) ; extern void wiphy_apply_custom_regulatory(struct wiphy * , struct ieee80211_regdomain const * ) ; extern struct ieee80211_reg_rule const *freq_reg_info(struct wiphy * , u32 ) ; extern struct ieee80211_hw *wiphy_to_ieee80211_hw(struct wiphy * ) ; __inline static int chspec_bandunit(u16 chspec ) { { return (((int )chspec & 61440) == 4096); } } void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi , bool wide_filter ) ; void wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi , uint band , struct brcms_chanvec *channels ) ; int brcms_c_set_gmode(struct brcms_c_info *wlc , u8 gmode , bool config ) ; int brcms_c_set_nmode(struct brcms_c_info *wlc ) ; void brcms_b_set_chanspec(struct brcms_hardware *wlc_hw , u16 chanspec , bool mute_tx , struct txpwr_limits *txpwr ) ; int brcms_c_stf_ss_update(struct brcms_c_info *wlc , struct brcms_band *band ) ; struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc ) ; void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm ) ; bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm , u16 chspec ) ; void brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm , u16 chanspec , struct txpwr_limits *txpwr ) ; void brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm , u16 chanspec , u8 local_constraint_qdbm ) ; static struct ieee80211_regdomain const brcms_regdom_x2 = {{0, 0}, 6U, {'X', '2', '\000'}, 0, {{{2402000U, 2472000U, 40000U}, {0U, 1900U}, 0U, 0U}, {{2457000U, 2482000U, 20000U}, {0U, 1900U}, 128U, 0U}, {{5170000U, 5250000U, 40000U}, {0U, 2100U}, 128U, 0U}, {{5250000U, 5330000U, 40000U}, {0U, 2100U}, 144U, 0U}, {{5490000U, 5710000U, 40000U}, {0U, 2100U}, 144U, 0U}, {{5735000U, 5835000U, 40000U}, {0U, 2100U}, 128U, 0U}}}; static struct locale_mimo_info const locale_bn = {{52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52, 52}, {0, 0, 52, 52, 52, 52, 52, 52, 52, 52, 52, 0, 0}}; static struct locale_mimo_info const *g_mimo_2g_table[1U] = { & locale_bn}; static struct locale_mimo_info const locale_11n = {{50, 50, 50, 60, 60}, {56, 60, 60, 60, 60}}; static struct locale_mimo_info const *g_mimo_5g_table[1U] = { & locale_11n}; static struct brcms_regd const cntry_locales[1U] = { {{0U, 0U}, & brcms_regdom_x2}}; static struct locale_mimo_info const *brcms_c_get_mimo_2g(u8 locale_idx ) { { if ((unsigned int )locale_idx != 0U) { return ((struct locale_mimo_info const *)0); } else { } return (g_mimo_2g_table[(int )locale_idx]); } } static struct locale_mimo_info const *brcms_c_get_mimo_5g(u8 locale_idx ) { { if ((unsigned int )locale_idx != 0U) { return ((struct locale_mimo_info const *)0); } else { } return (g_mimo_5g_table[(int )locale_idx]); } } static bool brcms_c_country_valid(char const *ccode ) { int tmp ; int tmp___0 ; int tmp___1 ; { if ((((((int const )*ccode < 0 || (int )((signed char )*ccode) <= 64) || (int )((signed char )*ccode) > 90) || (int const )*(ccode + 1UL) < 0) || (int )((signed char )*(ccode + 1UL)) <= 64) || (int )((signed char )*(ccode + 1UL)) > 90) { return (0); } else { } tmp = strcmp("AA", ccode); if (tmp == 0) { return (0); } else { tmp___0 = strcmp("ZZ", ccode); if (tmp___0 == 0) { return (0); } else if ((int )((signed char )*ccode) == 88) { return (0); } else if ((int )((signed char )*ccode) == 81 && ((int )((signed char )*(ccode + 1UL)) > 76 && (int )((signed char )*(ccode + 1UL)) <= 90)) { return (0); } else { } } tmp___1 = strcmp("NA", ccode); if (tmp___1 == 0) { return (0); } else { } return (1); } } static struct brcms_regd const *brcms_world_regd(char const *regdom , int len ) { struct brcms_regd const *regd ; int i ; int tmp ; { regd = (struct brcms_regd const *)0; i = 0; goto ldv_54939; ldv_54938: tmp = strncmp(regdom, (char const *)(& (cntry_locales[i].regdomain)->alpha2), (__kernel_size_t )len); if (tmp == 0) { regd = (struct brcms_regd const *)(& cntry_locales) + (unsigned long )i; goto ldv_54937; } else { } i = i + 1; ldv_54939: ; if (i == 0) { goto ldv_54938; } else { } ldv_54937: ; return (regd); } } static struct brcms_regd const *brcms_default_world_regd(void) { { return ((struct brcms_regd const *)(& cntry_locales)); } } static bool brcms_c_japan_ccode(char const *ccode ) { { return ((bool )((int )((signed char )*ccode) == 74 && ((int )((signed char )*(ccode + 1UL)) == 80 || ((int )((signed char )*(ccode + 1UL)) > 48 && (int )((signed char )*(ccode + 1UL)) <= 57)))); } } static void brcms_c_channel_min_txpower_limits_with_local_constraint(struct brcms_cm_info *wlc_cm , struct txpwr_limits *txpwr , u8 local_constraint_qdbm ) { int j ; u8 _min1 ; u8 _min2 ; u8 _min1___0 ; u8 _min2___0 ; u8 _min1___1 ; u8 _min2___1 ; u8 _min1___2 ; u8 _min2___2 ; u8 _min1___3 ; u8 _min2___3 ; u8 _min1___4 ; u8 _min2___4 ; u8 _min1___5 ; u8 _min2___5 ; u8 _min1___6 ; u8 _min2___6 ; u8 _min1___7 ; u8 _min2___7 ; u8 _min1___8 ; u8 _min2___8 ; u8 _min1___9 ; u8 _min2___9 ; u8 _min1___10 ; u8 _min2___10 ; u8 _min1___11 ; u8 _min2___11 ; u8 _min1___12 ; u8 _min2___12 ; { j = 0; goto ldv_54956; ldv_54955: _min1 = txpwr->cck[j]; _min2 = local_constraint_qdbm; txpwr->cck[j] = (u8 )((int )_min1 < (int )_min2 ? _min1 : _min2); j = j + 1; ldv_54956: ; if (j <= 3) { goto ldv_54955; } else { } j = 0; goto ldv_54962; ldv_54961: _min1___0 = txpwr->ofdm[j]; _min2___0 = local_constraint_qdbm; txpwr->ofdm[j] = (u8 )((int )_min1___0 < (int )_min2___0 ? _min1___0 : _min2___0); j = j + 1; ldv_54962: ; if (j <= 7) { goto ldv_54961; } else { } j = 0; goto ldv_54968; ldv_54967: _min1___1 = txpwr->ofdm_cdd[j]; _min2___1 = local_constraint_qdbm; txpwr->ofdm_cdd[j] = (u8 )((int )_min1___1 < (int )_min2___1 ? _min1___1 : _min2___1); j = j + 1; ldv_54968: ; if (j <= 7) { goto ldv_54967; } else { } j = 0; goto ldv_54974; ldv_54973: _min1___2 = txpwr->ofdm_40_siso[j]; _min2___2 = local_constraint_qdbm; txpwr->ofdm_40_siso[j] = (u8 )((int )_min1___2 < (int )_min2___2 ? _min1___2 : _min2___2); j = j + 1; ldv_54974: ; if (j <= 7) { goto ldv_54973; } else { } j = 0; goto ldv_54980; ldv_54979: _min1___3 = txpwr->ofdm_40_cdd[j]; _min2___3 = local_constraint_qdbm; txpwr->ofdm_40_cdd[j] = (u8 )((int )_min1___3 < (int )_min2___3 ? _min1___3 : _min2___3); j = j + 1; ldv_54980: ; if (j <= 7) { goto ldv_54979; } else { } j = 0; goto ldv_54986; ldv_54985: _min1___4 = txpwr->mcs_20_siso[j]; _min2___4 = local_constraint_qdbm; txpwr->mcs_20_siso[j] = (u8 )((int )_min1___4 < (int )_min2___4 ? _min1___4 : _min2___4); j = j + 1; ldv_54986: ; if (j <= 7) { goto ldv_54985; } else { } j = 0; goto ldv_54992; ldv_54991: _min1___5 = txpwr->mcs_20_cdd[j]; _min2___5 = local_constraint_qdbm; txpwr->mcs_20_cdd[j] = (u8 )((int )_min1___5 < (int )_min2___5 ? _min1___5 : _min2___5); j = j + 1; ldv_54992: ; if (j <= 7) { goto ldv_54991; } else { } j = 0; goto ldv_54998; ldv_54997: _min1___6 = txpwr->mcs_20_stbc[j]; _min2___6 = local_constraint_qdbm; txpwr->mcs_20_stbc[j] = (u8 )((int )_min1___6 < (int )_min2___6 ? _min1___6 : _min2___6); j = j + 1; ldv_54998: ; if (j <= 7) { goto ldv_54997; } else { } j = 0; goto ldv_55004; ldv_55003: _min1___7 = txpwr->mcs_20_mimo[j]; _min2___7 = local_constraint_qdbm; txpwr->mcs_20_mimo[j] = (u8 )((int )_min1___7 < (int )_min2___7 ? _min1___7 : _min2___7); j = j + 1; ldv_55004: ; if (j <= 7) { goto ldv_55003; } else { } j = 0; goto ldv_55010; ldv_55009: _min1___8 = txpwr->mcs_40_siso[j]; _min2___8 = local_constraint_qdbm; txpwr->mcs_40_siso[j] = (u8 )((int )_min1___8 < (int )_min2___8 ? _min1___8 : _min2___8); j = j + 1; ldv_55010: ; if (j <= 7) { goto ldv_55009; } else { } j = 0; goto ldv_55016; ldv_55015: _min1___9 = txpwr->mcs_40_cdd[j]; _min2___9 = local_constraint_qdbm; txpwr->mcs_40_cdd[j] = (u8 )((int )_min1___9 < (int )_min2___9 ? _min1___9 : _min2___9); j = j + 1; ldv_55016: ; if (j <= 7) { goto ldv_55015; } else { } j = 0; goto ldv_55022; ldv_55021: _min1___10 = txpwr->mcs_40_stbc[j]; _min2___10 = local_constraint_qdbm; txpwr->mcs_40_stbc[j] = (u8 )((int )_min1___10 < (int )_min2___10 ? _min1___10 : _min2___10); j = j + 1; ldv_55022: ; if (j <= 7) { goto ldv_55021; } else { } j = 0; goto ldv_55028; ldv_55027: _min1___11 = txpwr->mcs_40_mimo[j]; _min2___11 = local_constraint_qdbm; txpwr->mcs_40_mimo[j] = (u8 )((int )_min1___11 < (int )_min2___11 ? _min1___11 : _min2___11); j = j + 1; ldv_55028: ; if (j <= 7) { goto ldv_55027; } else { } _min1___12 = txpwr->mcs32; _min2___12 = local_constraint_qdbm; txpwr->mcs32 = (u8 )((int )_min1___12 < (int )_min2___12 ? _min1___12 : _min2___12); return; } } static void brcms_c_set_country(struct brcms_cm_info *wlc_cm , struct brcms_regd const *regd ) { struct brcms_c_info *wlc ; { wlc = wlc_cm->wlc; if (((int )(wlc->pub)->_n_enab & 3) != (int )(wlc->protection)->nmode_user) { brcms_c_set_nmode(wlc); } else { } brcms_c_stf_ss_update(wlc, wlc->bandstate[0]); brcms_c_stf_ss_update(wlc, wlc->bandstate[1]); brcms_c_set_gmode(wlc, (int )(wlc->protection)->gmode_user, 0); return; } } struct brcms_cm_info *brcms_c_channel_mgr_attach(struct brcms_c_info *wlc ) { struct brcms_cm_info *wlc_cm ; struct brcms_pub *pub ; struct ssb_sprom *sprom ; char const *ccode ; int ccode_len ; void *tmp ; bool tmp___0 ; { pub = wlc->pub; sprom = & (((wlc->hw)->d11core)->bus)->sprom; ccode = (char const *)(& sprom->alpha2); ccode_len = 2; tmp = kzalloc(24UL, 32U); wlc_cm = (struct brcms_cm_info *)tmp; if ((unsigned long )wlc_cm == (unsigned long )((struct brcms_cm_info *)0)) { return ((struct brcms_cm_info *)0); } else { } wlc_cm->pub = pub; wlc_cm->wlc = wlc; wlc->cmi = wlc_cm; wlc_cm->world_regd = brcms_world_regd(ccode, ccode_len); tmp___0 = brcms_c_country_valid(ccode); if ((int )tmp___0) { strncpy((char *)(& (wlc->pub)->srom_ccode), ccode, (__kernel_size_t )ccode_len); } else { } if ((unsigned long )wlc_cm->world_regd == (unsigned long )((struct brcms_regd const *)0)) { wlc_cm->world_regd = brcms_default_world_regd(); ccode = (char const *)(& ((wlc_cm->world_regd)->regdomain)->alpha2); ccode_len = 3; } else { } strncpy((char *)(& wlc->country_default), ccode, (__kernel_size_t )ccode_len); strncpy((char *)(& wlc->autocountry_default), ccode, (__kernel_size_t )ccode_len); brcms_c_set_country(wlc_cm, wlc_cm->world_regd); return (wlc_cm); } } void brcms_c_channel_mgr_detach(struct brcms_cm_info *wlc_cm ) { { kfree((void const *)wlc_cm); return; } } void brcms_c_channel_set_chanspec(struct brcms_cm_info *wlc_cm , u16 chanspec , u8 local_constraint_qdbm ) { struct brcms_c_info *wlc ; struct ieee80211_channel *ch ; struct txpwr_limits txpwr ; { wlc = wlc_cm->wlc; ch = ((wlc->pub)->ieee_hw)->conf.chandef.chan; brcms_c_channel_reg_limits(wlc_cm, (int )chanspec, & txpwr); brcms_c_channel_min_txpower_limits_with_local_constraint(wlc_cm, & txpwr, (int )local_constraint_qdbm); if ((ch->flags & 64U) != 0U) { brcms_c_set_gmode(wlc, 0, 0); } else { brcms_c_set_gmode(wlc, (int )(wlc->protection)->gmode_user, 0); } brcms_b_set_chanspec(wlc->hw, (int )chanspec, (ch->flags & 2U) != 0U, & txpwr); return; } } void brcms_c_channel_reg_limits(struct brcms_cm_info *wlc_cm , u16 chanspec , struct txpwr_limits *txpwr ) { struct brcms_c_info *wlc ; struct ieee80211_channel *ch ; uint i ; uint chan ; int maxpwr ; int delta ; struct country_info const *country ; struct brcms_band *band ; int conducted_max ; struct locale_mimo_info const *li_mimo ; int maxpwr20 ; int maxpwr40 ; int maxpwr_idx ; uint j ; int __ret_warn_on ; long tmp ; long tmp___0 ; int tmp___1 ; struct locale_mimo_info const *tmp___2 ; struct locale_mimo_info const *tmp___3 ; int _max1 ; int _max2 ; int _min1 ; int _min2 ; int _max1___0 ; int _max2___0 ; int _max1___1 ; int _max2___1 ; { wlc = wlc_cm->wlc; ch = ((wlc->pub)->ieee_hw)->conf.chandef.chan; conducted_max = 127; memset((void *)txpwr, 0, 101UL); __ret_warn_on = (unsigned long )ch == (unsigned long )((struct ieee80211_channel *)0); tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/channel.c", 417); } else { } tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { return; } else { } country = & (wlc_cm->world_regd)->country; chan = (uint )((unsigned char )chanspec); tmp___1 = chspec_bandunit((int )chanspec); band = wlc->bandstate[tmp___1]; if (band->bandtype == 1) { tmp___2 = brcms_c_get_mimo_5g((int )country->locale_mimo_5G); li_mimo = tmp___2; } else { tmp___3 = brcms_c_get_mimo_2g((int )country->locale_mimo_2G); li_mimo = tmp___3; } delta = (int )band->antgain; if (band->bandtype == 2) { conducted_max = 88; } else { } maxpwr = ch->max_power * 4 - delta; _max1 = maxpwr; _max2 = 0; maxpwr = _max1 > _max2 ? _max1 : _max2; _min1 = maxpwr; _min2 = conducted_max; maxpwr = _min1 < _min2 ? _min1 : _min2; if (band->bandtype == 2) { i = 0U; goto ldv_55085; ldv_55084: txpwr->cck[i] = (unsigned char )maxpwr; i = i + 1U; ldv_55085: ; if (i <= 3U) { goto ldv_55084; } else { } } else { } i = 0U; goto ldv_55088; ldv_55087: txpwr->ofdm[i] = (unsigned char )maxpwr; txpwr->ofdm_40_siso[i] = 0U; txpwr->ofdm_cdd[i] = (unsigned char )maxpwr; txpwr->ofdm_40_cdd[i] = 0U; i = i + 1U; ldv_55088: ; if (i <= 7U) { goto ldv_55087; } else { } delta = 0; if ((int )band->antgain > 24) { delta = (int )band->antgain + -24; } else { } if (band->bandtype == 2) { maxpwr_idx = (int )(chan - 1U); } else { maxpwr_idx = chan > 51U ? (chan > 61U ? (chan > 99U ? (chan <= 148U ? 3 : 4) : 2) : 1) : 0; } maxpwr20 = (int )li_mimo->maxpwr20[maxpwr_idx]; maxpwr40 = (int )li_mimo->maxpwr40[maxpwr_idx]; maxpwr20 = maxpwr20 - delta; _max1___0 = maxpwr20; _max2___0 = 0; maxpwr20 = _max1___0 > _max2___0 ? _max1___0 : _max2___0; maxpwr40 = maxpwr40 - delta; _max1___1 = maxpwr40; _max2___1 = 0; maxpwr40 = _max1___1 > _max2___1 ? _max1___1 : _max2___1; i = 0U; goto ldv_55097; ldv_55096: txpwr->mcs_20_siso[i] = txpwr->ofdm[i]; txpwr->mcs_40_siso[i] = 0U; i = i + 1U; ldv_55097: ; if (i <= 7U) { goto ldv_55096; } else { } i = 0U; goto ldv_55100; ldv_55099: txpwr->mcs_20_cdd[i] = (unsigned char )maxpwr20; txpwr->mcs_40_cdd[i] = (unsigned char )maxpwr40; i = i + 1U; ldv_55100: ; if (i <= 7U) { goto ldv_55099; } else { } if ((unsigned long )li_mimo == (unsigned long )(& locale_bn)) { if ((unsigned long )li_mimo == (unsigned long )(& locale_bn)) { maxpwr20 = 64; maxpwr40 = 0; if (chan > 2U && chan <= 11U) { maxpwr40 = 64; } else { } } else { } i = 0U; goto ldv_55103; ldv_55102: txpwr->mcs_20_siso[i] = (unsigned char )maxpwr20; txpwr->mcs_40_siso[i] = (unsigned char )maxpwr40; i = i + 1U; ldv_55103: ; if (i <= 7U) { goto ldv_55102; } else { } } else { } i = 0U; goto ldv_55106; ldv_55105: txpwr->mcs_20_stbc[i] = 0U; txpwr->mcs_40_stbc[i] = 0U; i = i + 1U; ldv_55106: ; if (i <= 7U) { goto ldv_55105; } else { } i = 0U; goto ldv_55109; ldv_55108: txpwr->mcs_20_mimo[i] = (unsigned char )maxpwr20; txpwr->mcs_40_mimo[i] = (unsigned char )maxpwr40; i = i + 1U; ldv_55109: ; if (i <= 7U) { goto ldv_55108; } else { } txpwr->mcs32 = (unsigned char )maxpwr40; i = 0U; j = 0U; goto ldv_55112; ldv_55111: ; if ((unsigned int )txpwr->ofdm_40_cdd[i] == 0U) { txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j]; } else { } if (i == 0U) { i = i + 1U; if ((unsigned int )txpwr->ofdm_40_cdd[i] == 0U) { txpwr->ofdm_40_cdd[i] = txpwr->mcs_40_cdd[j]; } else { } } else { } i = i + 1U; j = j + 1U; ldv_55112: ; if (i <= 7U) { goto ldv_55111; } else { } i = 0U; goto ldv_55115; ldv_55114: ; if ((unsigned int )txpwr->mcs_40_siso[i] == 0U) { txpwr->mcs_40_siso[i] = txpwr->mcs_40_cdd[i]; } else { } i = i + 1U; ldv_55115: ; if (i <= 7U) { goto ldv_55114; } else { } i = 0U; j = 0U; goto ldv_55118; ldv_55117: ; if ((unsigned int )txpwr->ofdm_40_siso[i] == 0U) { txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j]; } else { } if (i == 0U) { i = i + 1U; if ((unsigned int )txpwr->ofdm_40_siso[i] == 0U) { txpwr->ofdm_40_siso[i] = txpwr->mcs_40_siso[j]; } else { } } else { } i = i + 1U; j = j + 1U; ldv_55118: ; if (i <= 7U) { goto ldv_55117; } else { } i = 0U; goto ldv_55121; ldv_55120: ; if ((unsigned int )txpwr->mcs_20_stbc[i] == 0U) { txpwr->mcs_20_stbc[i] = txpwr->mcs_20_cdd[i]; } else { } if ((unsigned int )txpwr->mcs_40_stbc[i] == 0U) { txpwr->mcs_40_stbc[i] = txpwr->mcs_40_cdd[i]; } else { } i = i + 1U; ldv_55121: ; if (i <= 7U) { goto ldv_55120; } else { } return; } } static bool brcms_c_chspec_malformed(u16 chanspec ) { { if (((int )chanspec & 61440) != 4096 && ((int )chanspec & 61440) != 8192) { return (1); } else { } if (((int )chanspec & 3072) != 3072 && ((int )chanspec & 3072) != 2048) { return (1); } else { } if (((int )chanspec & 3072) == 2048) { if (((int )chanspec & 768) != 768) { return (1); } else { } } else if (((int )chanspec & 768) != 512 && ((int )chanspec & 768) != 256) { return (1); } else { } return (0); } } static bool brcms_c_valid_chanspec_ext(struct brcms_cm_info *wlc_cm , u16 chspec ) { struct brcms_c_info *wlc ; u8 channel ; bool tmp ; int tmp___0 ; { wlc = wlc_cm->wlc; channel = (unsigned char )chspec; tmp = brcms_c_chspec_malformed((int )chspec); if ((int )tmp) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: malformed chanspec 0x%x\n", (wlc->pub)->unit, (int )chspec); return (0); } else { } tmp___0 = chspec_bandunit((int )chspec); if (((unsigned int )channel > 14U) != tmp___0) { return (0); } else { } return (1); } } bool brcms_c_valid_chanspec_db(struct brcms_cm_info *wlc_cm , u16 chspec ) { bool tmp ; { tmp = brcms_c_valid_chanspec_ext(wlc_cm, (int )chspec); return (tmp); } } static bool brcms_is_radar_freq(u16 center_freq ) { { return ((bool )((unsigned int )center_freq > 5259U && (unsigned int )center_freq <= 5700U)); } } static void brcms_reg_apply_radar_flags(struct wiphy *wiphy ) { struct ieee80211_supported_band *sband ; struct ieee80211_channel *ch ; int i ; bool tmp ; int tmp___0 ; { sband = wiphy->bands[1]; if ((unsigned long )sband == (unsigned long )((struct ieee80211_supported_band *)0)) { return; } else { } i = 0; goto ldv_55147; ldv_55146: ch = sband->channels + (unsigned long )i; tmp = brcms_is_radar_freq((int )ch->center_freq); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { goto ldv_55145; } else { } if ((ch->flags & 1U) == 0U) { ch->flags = ch->flags | 10U; } else { } ldv_55145: i = i + 1; ldv_55147: ; if (sband->n_channels > i) { goto ldv_55146; } else { } return; } } static void brcms_reg_apply_beaconing_flags(struct wiphy *wiphy , enum nl80211_reg_initiator initiator ) { struct ieee80211_supported_band *sband ; struct ieee80211_channel *ch ; struct ieee80211_reg_rule const *rule ; int band ; int i ; bool tmp ; { band = 0; goto ldv_55164; ldv_55163: sband = wiphy->bands[band]; if ((unsigned long )sband == (unsigned long )((struct ieee80211_supported_band *)0)) { goto ldv_55158; } else { } i = 0; goto ldv_55161; ldv_55160: ch = sband->channels + (unsigned long )i; if ((ch->flags & 9U) != 0U) { goto ldv_55159; } else { } if ((unsigned int )initiator == 3U) { rule = freq_reg_info(wiphy, (u32 )((int )ch->center_freq * 1000)); tmp = IS_ERR((void const *)rule); if ((int )tmp) { goto ldv_55159; } else { } if (((unsigned int )rule->flags & 128U) == 0U) { ch->flags = ch->flags & 4294967293U; } else { } } else if ((int )ch->beacon_found) { ch->flags = ch->flags & 4294967293U; } else { } ldv_55159: i = i + 1; ldv_55161: ; if (sband->n_channels > i) { goto ldv_55160; } else { } ldv_55158: band = band + 1; ldv_55164: ; if (band <= 2) { goto ldv_55163; } else { } return; } } static void brcms_reg_notifier(struct wiphy *wiphy , struct regulatory_request *request ) { struct ieee80211_hw *hw ; struct ieee80211_hw *tmp ; struct brcms_info *wl ; struct brcms_c_info *wlc ; struct ieee80211_supported_band *sband ; struct ieee80211_channel *ch ; int band ; int i ; bool ch_found ; bool tmp___0 ; { tmp = wiphy_to_ieee80211_hw(wiphy); hw = tmp; wl = (struct brcms_info *)hw->priv; wlc = wl->wlc; ch_found = 0; brcms_reg_apply_radar_flags(wiphy); if ((unsigned int )request->initiator == 3U) { brcms_reg_apply_beaconing_flags(wiphy, request->initiator); } else { } band = 0; goto ldv_55183; ldv_55182: sband = wiphy->bands[band]; if ((unsigned long )sband == (unsigned long )((struct ieee80211_supported_band *)0)) { goto ldv_55178; } else { } i = 0; goto ldv_55180; ldv_55179: ch = sband->channels + (unsigned long )i; if ((ch->flags & 1U) == 0U) { ch_found = 1; } else { } i = i + 1; ldv_55180: ; if (! ch_found && sband->n_channels > i) { goto ldv_55179; } else { } ldv_55178: band = band + 1; ldv_55183: ; if (! ch_found && band <= 2) { goto ldv_55182; } else { } if ((int )ch_found) { (wlc->pub)->radio_disabled = (wlc->pub)->radio_disabled & 4294967287U; } else { (wlc->pub)->radio_disabled = (wlc->pub)->radio_disabled | 8U; __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s: no valid channel for \"%s\"\n", (wlc->pub)->unit, "brcms_reg_notifier", (char *)(& request->alpha2)); } if ((wlc->pub)->_nbands > 1U || (wlc->band)->bandtype == 2) { tmp___0 = brcms_c_japan_ccode((char const *)(& request->alpha2)); wlc_phy_chanspec_ch14_widefilter_set((wlc->band)->pi, (int )tmp___0); } else { } return; } } void brcms_c_regd_init(struct brcms_c_info *wlc ) { struct wiphy *wiphy ; struct brcms_regd const *regd ; struct ieee80211_supported_band *sband ; struct ieee80211_channel *ch ; struct brcms_chanvec sup_chan ; struct brcms_band *band ; int band_idx ; int i ; { wiphy = wlc->wiphy; regd = (wlc->cmi)->world_regd; band_idx = 0; goto ldv_55201; ldv_55200: band = wlc->bandstate[band_idx]; wlc_phy_chanspec_band_validch(band->pi, (uint )band->bandtype, & sup_chan); if (band_idx == 0) { sband = wiphy->bands[0]; } else { sband = wiphy->bands[1]; } i = 0; goto ldv_55198; ldv_55197: ch = sband->channels + (unsigned long )i; if ((((int )*((u8 const *)(& sup_chan.vec) + (unsigned long )((unsigned int )ch->hw_value / 8U)) >> ((int )ch->hw_value & 7)) & 1) == 0) { ch->flags = ch->flags | 1U; } else { } i = i + 1; ldv_55198: ; if (sband->n_channels > i) { goto ldv_55197; } else { } band_idx = band_idx + 1; ldv_55201: ; if ((uint )band_idx < (wlc->pub)->_nbands) { goto ldv_55200; } else { } (wlc->wiphy)->reg_notifier = & brcms_reg_notifier; (wlc->wiphy)->regulatory_flags = (wlc->wiphy)->regulatory_flags | 3U; wiphy_apply_custom_regulatory(wlc->wiphy, regd->regdomain); brcms_reg_apply_beaconing_flags(wiphy, 2); return; } } __inline static bool IS_ERR(void const *ptr ) { bool tmp ; { tmp = ldv_is_err(ptr); return (tmp); } } bool ldv_queue_work_on_73(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_74(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_75(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_76(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_77(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static __u32 __arch_swab32(__u32 val ) { { __asm__ ("bswapl %0": "=r" (val): "0" (val)); return (val); } } __inline static __u32 __fswab32(__u32 val ) { __u32 tmp ; { tmp = __arch_swab32(val); return (tmp); } } extern int snprintf(char * , size_t , char const * , ...) ; __inline static unsigned long arch_local_save_flags___0(void) { unsigned long __ret ; unsigned long __edi ; unsigned long __esi ; unsigned long __edx ; unsigned long __ecx ; unsigned long __eax ; long tmp ; { __edi = __edi; __esi = __esi; __edx = __edx; __ecx = __ecx; __eax = __eax; tmp = ldv__builtin_expect((unsigned long )pv_irq_ops.save_fl.func == (unsigned long )((void *)0), 0L); if (tmp != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"./arch/x86/include/asm/paravirt.h"), "i" (831), "i" (12UL)); ldv_4860: ; goto ldv_4860; } else { } __asm__ volatile ("771:\n\tcall *%c2;\n772:\n.pushsection .parainstructions,\"a\"\n .balign 8 \n .quad 771b\n .byte %c1\n .byte 772b-771b\n .short %c3\n.popsection\n": "=a" (__eax): [paravirt_typenum] "i" (43UL), [paravirt_opptr] "i" (& pv_irq_ops.save_fl.func), [paravirt_clobber] "i" (1): "memory", "cc"); __ret = __eax; return (__ret); } } __inline static bool static_key_false___0(struct static_key *key ) { int tmp ; long tmp___0 ; { tmp = static_key_count(key); tmp___0 = ldv__builtin_expect(tmp > 0, 0L); if (tmp___0 != 0L) { return (1); } else { } return (0); } } __inline static int rcu_read_lock_sched_held___0(void) { int lockdep_opinion ; int tmp ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; int tmp___4 ; unsigned long _flags ; int tmp___5 ; int tmp___6 ; { lockdep_opinion = 0; tmp = debug_lockdep_rcu_enabled(); if (tmp == 0) { return (1); } else { } tmp___0 = rcu_is_watching(); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return (0); } else { } tmp___2 = rcu_lockdep_current_cpu_online(); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { return (0); } else { } if (debug_locks != 0) { lockdep_opinion = lock_is_held(& rcu_sched_lock_map); } else { } if (lockdep_opinion != 0) { tmp___6 = 1; } else { tmp___4 = preempt_count(); if (tmp___4 != 0) { tmp___6 = 1; } else { _flags = arch_local_save_flags___0(); tmp___5 = arch_irqs_disabled_flags(_flags); if (tmp___5 != 0) { tmp___6 = 1; } else { tmp___6 = 0; } } } return (tmp___6); } } bool ldv_queue_work_on_87(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_89(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_88(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_91(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_90(struct workqueue_struct *ldv_func_arg1 ) ; extern void skb_unlink(struct sk_buff * , struct sk_buff_head * ) ; __inline static bool skb_is_nonlinear(struct sk_buff const *skb ) { { return ((unsigned int )skb->data_len != 0U); } } __inline static void skb_reset_tail_pointer(struct sk_buff *skb ) { { skb->tail = (sk_buff_data_t )((long )skb->data) - (sk_buff_data_t )((long )skb->head); return; } } __inline static void skb_set_tail_pointer(struct sk_buff *skb , int const offset ) { { skb_reset_tail_pointer(skb); skb->tail = skb->tail + (sk_buff_data_t )offset; return; } } extern unsigned char *skb_push(struct sk_buff * , unsigned int ) ; __inline static void __skb_trim(struct sk_buff *skb , unsigned int len ) { int __ret_warn_on ; long tmp ; bool tmp___0 ; long tmp___1 ; { tmp___0 = skb_is_nonlinear((struct sk_buff const *)skb); tmp___1 = ldv__builtin_expect((long )tmp___0, 0L); if (tmp___1 != 0L) { __ret_warn_on = 1; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("include/linux/skbuff.h", 2054); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return; } else { } skb->len = len; skb_set_tail_pointer(skb, (int const )len); return; } } __inline static u16 skb_get_queue_mapping(struct sk_buff const *skb ) { { return ((u16 )skb->queue_mapping); } } extern void __dev_kfree_skb_any(struct sk_buff * , enum skb_free_reason ) ; __inline static void dev_kfree_skb_any(struct sk_buff *skb ) { { __dev_kfree_skb_any(skb, 1); return; } } __inline static int ieee80211_has_morefrags(__le16 fc ) { { return (((int )fc & 1024) != 0); } } __inline static int ieee80211_is_mgmt(__le16 fc ) { { return (((int )fc & 12) == 0); } } __inline static int ieee80211_is_data(__le16 fc ) { { return (((int )fc & 12) == 8); } } __inline static int ieee80211_is_data_qos(__le16 fc ) { { return (((int )fc & 140) == 136); } } __inline static int ieee80211_is_beacon(__le16 fc ) { { return (((int )fc & 252) == 128); } } __inline static int ieee80211_is_pspoll(__le16 fc ) { { return (((int )fc & 252) == 164); } } extern int ieee80211_channel_to_frequency(int , enum ieee80211_band ) ; __inline static struct ieee80211_rx_status *IEEE80211_SKB_RXCB(struct sk_buff *skb ) { { return ((struct ieee80211_rx_status *)(& skb->cb)); } } __inline static struct ieee80211_rate *ieee80211_get_tx_rate(struct ieee80211_hw const *hw , struct ieee80211_tx_info const *c ) { bool __warned ; int __ret_warn_once ; int __ret_warn_on ; long tmp ; long tmp___0 ; long tmp___1 ; long tmp___2 ; { __ret_warn_once = (int )((signed char )c->__annonCompField103.control.__annonCompField101.__annonCompField100.rates[0].idx) < 0; tmp___1 = ldv__builtin_expect(__ret_warn_once != 0, 0L); if (tmp___1 != 0L) { __ret_warn_on = ! __warned; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("include/net/mac80211.h", 2151); } else { } tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { __warned = 1; } else { } } else { } tmp___2 = ldv__builtin_expect(__ret_warn_once != 0, 0L); if (tmp___2 != 0L) { return ((struct ieee80211_rate *)0); } else { } return (((hw->wiphy)->bands[(int )c->band])->bitrates + (unsigned long )c->__annonCompField103.control.__annonCompField101.__annonCompField100.rates[0].idx); } } extern void ieee80211_rx_irqsafe(struct ieee80211_hw * , struct sk_buff * ) ; extern void ieee80211_wake_queue(struct ieee80211_hw * , int ) ; extern void ieee80211_stop_queue(struct ieee80211_hw * , int ) ; extern int ieee80211_queue_stopped(struct ieee80211_hw * , int ) ; extern u32 bcma_chipco_gpio_control(struct bcma_drv_cc * , u32 , u32 ) ; __inline static u32 bcma_read16(struct bcma_device *core , u16 offset ) { u16 tmp ; { tmp = (*(((core->bus)->ops)->read16))(core, (int )offset); return ((u32 )tmp); } } __inline static void bcma_write16(struct bcma_device *core , u16 offset , u32 value ) { { (*(((core->bus)->ops)->write16))(core, (int )offset, (int )((u16 )value)); return; } } __inline static void bcma_write32(struct bcma_device *core , u16 offset , u32 value ) { { (*(((core->bus)->ops)->write32))(core, (int )offset, value); return; } } __inline static u32 bcma_aread32(struct bcma_device *core , u16 offset ) { u32 tmp ; { tmp = (*(((core->bus)->ops)->aread32))(core, (int )offset); return (tmp); } } __inline static void bcma_awrite32(struct bcma_device *core , u16 offset , u32 value ) { { (*(((core->bus)->ops)->awrite32))(core, (int )offset, value); return; } } __inline static void bcma_mask32(struct bcma_device *cc , u16 offset , u32 mask ) { u32 tmp ; { tmp = bcma_read32(cc, (int )offset); bcma_write32(cc, (int )offset, tmp & mask); return; } } __inline static void bcma_set32(struct bcma_device *cc , u16 offset , u32 set ) { u32 tmp ; { tmp = bcma_read32(cc, (int )offset); bcma_write32(cc, (int )offset, tmp | set); return; } } __inline static void bcma_mask16(struct bcma_device *cc , u16 offset , u16 mask ) { u32 tmp ; { tmp = bcma_read16(cc, (int )offset); bcma_write16(cc, (int )offset, tmp & (u32 )mask); return; } } __inline static void bcma_set16(struct bcma_device *cc , u16 offset , u16 set ) { u32 tmp ; { tmp = bcma_read16(cc, (int )offset); bcma_write16(cc, (int )offset, tmp | (u32 )set); return; } } extern void bcma_host_pci_up(struct bcma_bus * ) ; extern void bcma_host_pci_down(struct bcma_bus * ) ; extern int bcma_host_pci_irq_ctl(struct bcma_bus * , struct bcma_device * , bool ) ; extern bool bcma_core_is_enabled(struct bcma_device * ) ; extern void bcma_core_disable(struct bcma_device * , u32 ) ; extern int bcma_core_enable(struct bcma_device * , u32 ) ; u32 brcm_msg_level ; struct si_pub *ai_attach(struct bcma_bus *pbus ) ; void ai_detach(struct si_pub *sih ) ; uint ai_cc_reg(struct si_pub *sih , uint regoff , u32 mask , u32 val ) ; void ai_clkctl_init(struct si_pub *sih ) ; u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih ) ; bool ai_clkctl_cc(struct si_pub *sih , enum bcma_clkmode mode ) ; bool ai_deviceremoved(struct si_pub *sih ) ; void ai_epa_4313war(struct si_pub *sih ) ; __inline static u32 ai_get_cccaps(struct si_pub *sih ) { { return (sih->cccaps); } } __inline static int ai_get_pmurev(struct si_pub *sih ) { { return (sih->pmurev); } } __inline static uint ai_get_boardtype(struct si_pub *sih ) { { return (sih->boardtype); } } __inline static uint ai_get_boardvendor(struct si_pub *sih ) { { return (sih->boardvendor); } } __inline static uint ai_get_chip_id(struct si_pub *sih ) { { return (sih->chip); } } __inline static uint ai_get_chiprev(struct si_pub *sih ) { { return (sih->chiprev); } } __inline static uint ai_get_chippkg(struct si_pub *sih ) { { return (sih->chippkg); } } __inline static u16 ch20mhz_chspec(int channel ) { u16 rc ; { rc = channel <= 14 ? 8192U : 4096U; return ((u16 )((unsigned int )((int )((unsigned short )channel) | (int )rc) | 2816U)); } } void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc ) ; void brcms_c_enable_mac(struct brcms_c_info *wlc ) ; void brcms_c_update_beacon(struct brcms_c_info *wlc ) ; struct dma_pub *dma_attach(char *name , struct brcms_c_info *wlc , uint txregbase , uint rxregbase , uint ntxd , uint nrxd , uint rxbufsize , int rxextheadroom , uint nrxpost , uint rxoffset ) ; void dma_rxinit(struct dma_pub *pub ) ; int dma_rx(struct dma_pub *pub , struct sk_buff_head *skb_list ) ; bool dma_rxfill(struct dma_pub *pub ) ; bool dma_rxreset(struct dma_pub *pub ) ; bool dma_txreset(struct dma_pub *pub ) ; void dma_txinit(struct dma_pub *pub ) ; int dma_txfast(struct brcms_c_info *wlc , struct dma_pub *pub , struct sk_buff *p ) ; int dma_txpending(struct dma_pub *pub ) ; void dma_kick_tx(struct dma_pub *pub ) ; void dma_txsuspend(struct dma_pub *pub ) ; void dma_txresume(struct dma_pub *pub ) ; void dma_txreclaim(struct dma_pub *pub , enum txd_range range ) ; void dma_rxreclaim(struct dma_pub *pub ) ; void dma_detach(struct dma_pub *pub ) ; unsigned long dma_getvar(struct dma_pub *pub , char const *name ) ; void dma_counterreset(struct dma_pub *pub ) ; void dma_walk_packets(struct dma_pub *dmah , void (*callback_fnc)(void * , void * ) , void *arg_a ) ; struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw , struct brcms_info *wl , struct brcms_c_info *wlc ) ; void wlc_phy_shim_detach(struct phy_shim_info *physhim ) ; struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp ) ; struct brcms_phy_pub *wlc_phy_attach(struct shared_phy *sh , struct bcma_device *d11core , int bandtype , struct wiphy *wiphy ) ; void wlc_phy_detach(struct brcms_phy_pub *pih ) ; bool wlc_phy_get_phyversion(struct brcms_phy_pub *pih , u16 *phytype , u16 *phyrev , u16 *radioid , u16 *radiover ) ; bool wlc_phy_get_encore(struct brcms_phy_pub *pih ) ; u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih ) ; void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *pih , bool newstate ) ; void wlc_phy_hw_state_upd(struct brcms_phy_pub *pih , bool newstate ) ; void wlc_phy_init(struct brcms_phy_pub *pih , u16 chanspec ) ; void wlc_phy_watchdog(struct brcms_phy_pub *pih ) ; int wlc_phy_down(struct brcms_phy_pub *pih ) ; u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih ) ; void wlc_phy_cal_init(struct brcms_phy_pub *pih ) ; void wlc_phy_antsel_init(struct brcms_phy_pub *ppi , bool lut_init ) ; void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi , u16 chanspec ) ; void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi , u16 newch ) ; void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi , u16 bw ) ; int wlc_phy_rssi_compute(struct brcms_phy_pub *pih , struct d11rxhdr *rxh ) ; void wlc_phy_por_inform(struct brcms_phy_pub *ppi ) ; void wlc_phy_noise_sample_intr(struct brcms_phy_pub *pih ) ; void wlc_phy_switch_radio(struct brcms_phy_pub *pih , bool on ) ; void wlc_phy_anacore(struct brcms_phy_pub *pih , bool on ) ; void wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi , struct txpwr_limits *txpwr , u16 chanspec ) ; int wlc_phy_txpower_get(struct brcms_phy_pub *ppi , uint *qdbm , bool *override ) ; int wlc_phy_txpower_set(struct brcms_phy_pub *ppi , uint qdbm , bool override ) ; void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih , u8 txchain , u8 rxchain ) ; void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi , bool ldpc ) ; void wlc_phy_hold_upd(struct brcms_phy_pub *pih , u32 id , bool set ) ; void wlc_phy_mute_upd(struct brcms_phy_pub *pih , bool mute , u32 flags ) ; void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi , u8 antsel_type ) ; void wlc_phy_initcal_enable(struct brcms_phy_pub *pih , bool initcal ) ; void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih , bool war ) ; void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi , u32 machwcap ) ; u8 const rate_info[109U] ; struct brcms_c_rateset const cck_ofdm_mimo_rates ; struct brcms_c_rateset const ofdm_mimo_rates ; struct brcms_c_rateset const cck_ofdm_rates ; struct brcms_c_rateset const cck_rates ; struct brcms_c_rateset const gphy_legacy_rates ; __inline static u8 mcs_2_txstreams(u8 mcs ) { { return ((u8 )((int const )mcs_table[(int )mcs].tx_phy_ctl3 >> 6)); } } __inline static bool rspec_active(u32 rspec ) { { return ((rspec & 134217855U) != 0U); } } __inline static u8 rspec_phytxbyte2(u32 rspec ) { { return ((u8 )((rspec & 65280U) >> 8)); } } __inline static u32 rspec_get_bw(u32 rspec ) { { return ((rspec & 1792U) >> 8); } } __inline static bool rspec_issgi(u32 rspec ) { { return ((rspec & 8388608U) != 0U); } } __inline static bool rspec_is40mhz(u32 rspec ) { u32 bw ; u32 tmp ; { tmp = rspec_get_bw(rspec); bw = tmp; return ((bool )(bw == 4U || bw == 5U)); } } __inline static uint rspec2rate(u32 rspec ) { bool tmp ; bool tmp___0 ; uint tmp___1 ; { if ((rspec & 134217728U) != 0U) { tmp = rspec_issgi(rspec); tmp___0 = rspec_is40mhz(rspec); tmp___1 = mcs_2_rate((int )((u8 )rspec) & 127, (int )tmp___0, (int )tmp); return (tmp___1); } else { } return (rspec & 127U); } } __inline static u8 rspec_mimoplcp3(u32 rspec ) { { return ((u8 )((rspec & 15728640U) >> 16)); } } __inline static uint rspec_stc(u32 rspec ) { { return ((rspec & 3145728U) >> 20); } } __inline static uint rspec_stf(u32 rspec ) { { return ((rspec & 14336U) >> 11); } } __inline static bool is_mcs_rate(u32 ratespec ) { { return ((ratespec & 134217728U) != 0U); } } __inline static bool is_ofdm_rate(u32 ratespec ) { bool tmp ; int tmp___0 ; { tmp = is_mcs_rate(ratespec); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } return ((bool )(tmp___0 && (int )((signed char )rate_info[ratespec & 127U]) < 0)); } } __inline static bool is_cck_rate(u32 ratespec ) { u32 rate ; bool tmp ; int tmp___0 ; { rate = ratespec & 127U; tmp = is_mcs_rate(ratespec); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } return ((bool )(tmp___0 && (((rate == 2U || rate == 4U) || rate == 11U) || rate == 22U))); } } __inline static bool is_single_stream(u8 mcs ) { { return ((bool )((unsigned int )mcs <= 7U || (unsigned int )mcs == 32U)); } } bool brcms_c_rate_hwrs_filter_sort_validate(struct brcms_c_rateset *rs , struct brcms_c_rateset const *hw_rs , bool check_brate , u8 txstreams ) ; void brcms_c_rateset_copy(struct brcms_c_rateset const *src , struct brcms_c_rateset *dst ) ; u32 brcms_c_compute_rspec(struct d11rxhdr *rxh , u8 *plcp ) ; void brcms_c_rateset_filter(struct brcms_c_rateset *src , struct brcms_c_rateset *dst , bool basic_only , u8 rates , uint xmask , bool mcsallow ) ; void brcms_c_rateset_default(struct brcms_c_rateset *rs_tgt , struct brcms_c_rateset const *rs_hw , uint phy_type , int bandtype , bool cck_only , uint rate_mask , bool mcsallow , u8 bw , u8 txstreams ) ; s16 brcms_c_rate_legacy_phyctl(uint rate ) ; void brcms_c_rateset_mcs_upd(struct brcms_c_rateset *rs , u8 txstreams ) ; void brcms_c_rateset_mcs_build(struct brcms_c_rateset *rateset , u8 txstreams ) ; void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset , u8 bw ) ; int brcms_c_stf_attach(struct brcms_c_info *wlc ) ; void brcms_c_stf_detach(struct brcms_c_info *wlc ) ; void brcms_c_tempsense_upd(struct brcms_c_info *wlc ) ; void brcms_c_stf_ss_algo_channel_get(struct brcms_c_info *wlc , u16 *ss_algo_channel , u16 chanspec ) ; void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc ) ; void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc ) ; u16 brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc , u32 rspec ) ; u16 brcms_c_stf_d11hdrs_phyctl_txant(struct brcms_c_info *wlc , u32 rspec ) ; __inline static bool is_broadcast_ether_addr(u8 const *addr ) { { return ((unsigned int )(((int )((unsigned short )*((u16 const *)addr)) & (int )((unsigned short )*((u16 const *)addr + 2U))) & (int )((unsigned short )*((u16 const *)addr + 4U))) == 65535U); } } void brcms_c_update_probe_resp(struct brcms_c_info *wlc , bool suspend ) ; void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc , u32 bcn_rspec ) ; void brcms_b_mhf(struct brcms_hardware *wlc_hw , u8 idx , u16 mask , u16 val , int bands ) ; void brcms_b_corereset(struct brcms_hardware *wlc_hw , u32 flags ) ; void brcms_b_mctrl(struct brcms_hardware *wlc_hw , u32 mask , u32 val ) ; void brcms_b_phy_reset(struct brcms_hardware *wlc_hw ) ; void brcms_b_bw_set(struct brcms_hardware *wlc_hw , u16 bw ) ; void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw ) ; void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw , u32 override_bit ) ; void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw , u32 override_bit ) ; u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw , u8 rate ) ; void brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw , uint offset , void const *buf , int len , u32 sel ) ; void brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw , uint offset , void *buf , int len , u32 sel ) ; void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw , u8 spurmode ) ; u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw ) ; void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw , bool clk ) ; void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw , bool clk ) ; void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw , bool on ) ; void brcms_b_txant_set(struct brcms_hardware *wlc_hw , u16 phytxant ) ; void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw , u8 stf_mode ) ; void __brcms_warn(struct device *dev , char const *fmt , ...) ; struct tracepoint __tracepoint_brcms_macintstatus ; __inline static void trace_brcms_macintstatus(struct device const *dev , int in_isr , u32 macintstatus , u32 mask ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_402 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_404 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___0(& __tracepoint_brcms_macintstatus.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_macintstatus.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___0(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac.h", 91, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_55457: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct device const * , int , u32 , u32 ))it_func))(__data, dev, in_isr, macintstatus, mask); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_55457; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_macintstatus.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___0(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac.h", 91, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } __inline static void trace_brcms_txdesc___0(struct device const *dev , void *txh , size_t txh_len ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_406___0 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_408___0 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___0(& __tracepoint_brcms_txdesc.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_txdesc.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___0(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_tx.h", 38, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_55521: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct device const * , void * , size_t ))it_func))(__data, dev, txh, txh_len); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_55521; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_txdesc.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___0(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_tx.h", 38, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } struct tracepoint __tracepoint_brcms_txstatus ; __inline static void trace_brcms_txstatus(struct device const *dev , u16 framelen , u16 frameid , u16 status , u16 lasttxtime , u16 sequence , u16 phyerr , u16 ackphyrxsh ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_410 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_412 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___0(& __tracepoint_brcms_txstatus.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_txstatus.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___0(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_tx.h", 71, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_55592: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct device const * , u16 , u16 , u16 , u16 , u16 , u16 , u16 ))it_func))(__data, dev, (int )framelen, (int )frameid, (int )status, (int )lasttxtime, (int )sequence, (int )phyerr, (int )ackphyrxsh); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_55592; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_txstatus.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___0(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_tx.h", 71, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } static u8 const wme_fifo2ac[6U] = { 3U, 2U, 1U, 0U, 2U, 2U}; static u8 const wme_ac2fifo[4U] = { 3U, 2U, 1U, 0U}; static u16 const xmtfifo_sz[12U][6U] = { { 20U, 192U, 192U, 21U, 17U, 5U}, { 0U, 0U, 0U, 0U, 0U, 0U}, { 0U, 0U, 0U, 0U, 0U, 0U}, { 20U, 192U, 192U, 21U, 17U, 5U}, { 9U, 58U, 22U, 14U, 14U, 5U}, { 20U, 192U, 192U, 21U, 17U, 5U}, { 20U, 192U, 192U, 21U, 17U, 5U}, { 9U, 58U, 22U, 14U, 14U, 5U}, { 0U, 0U, 0U, 0U, 0U, 0U}, { 0U, 0U, 0U, 0U, 0U, 0U}, { 0U, 0U, 0U, 0U, 0U, 0U}, { 9U, 58U, 22U, 14U, 14U, 5U}}; static char const fifo_names[6U][1U] ; static u8 const ac_to_fifo_mapping[4U] = { 3U, 2U, 1U, 0U}; static u8 const fifo_to_ac_mapping[4U] = { 3U, 2U, 1U, 0U}; static u8 brcms_ac_to_fifo(u8 ac ) { { if ((unsigned int )ac > 3U) { return (1U); } else { } return ((u8 )ac_to_fifo_mapping[(int )ac]); } } static u8 brcms_fifo_to_ac(u8 fifo ) { { if ((unsigned int )fifo > 3U) { return (2U); } else { } return ((u8 )fifo_to_ac_mapping[(int )fifo]); } } static u8 brcms_basic_rate(struct brcms_c_info *wlc , u32 rspec ) { bool tmp ; { tmp = is_mcs_rate(rspec); if ((int )tmp) { return ((wlc->band)->basic_rate[(int )mcs_table[rspec & 127U].leg_ofdm]); } else { } return ((wlc->band)->basic_rate[rspec & 127U]); } } static u16 frametype(u32 rspec , u8 mimoframe ) { bool tmp ; bool tmp___0 ; { tmp = is_mcs_rate(rspec); if ((int )tmp) { return ((u16 )mimoframe); } else { } tmp___0 = is_cck_rate(rspec); return ((int )tmp___0 ? 0U : 1U); } } static u16 get_sifs(struct brcms_band *band ) { { return (band->bandtype == 1 ? 16U : 10U); } } static bool brcms_deviceremoved(struct brcms_c_info *wlc ) { u32 macctrl ; bool tmp ; { if (! (wlc->hw)->clk) { tmp = ai_deviceremoved((wlc->hw)->sih); return (tmp); } else { } macctrl = bcma_read32((wlc->hw)->d11core, 288); return ((macctrl & 1028U) != 1024U); } } static int brcms_txpktpendtot(struct brcms_c_info *wlc ) { int i ; int pending ; int tmp ; { pending = 0; i = 0; goto ldv_56036; ldv_56035: ; if ((unsigned long )(wlc->hw)->di[i] != (unsigned long )((struct dma_pub *)0)) { tmp = dma_txpending((wlc->hw)->di[i]); pending = tmp + pending; } else { } i = i + 1; ldv_56036: ; if ((unsigned int )i <= 5U) { goto ldv_56035; } else { } return (pending); } } static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc ) { { return ((bool )((wlc->pub)->_nbands > 1U && ! wlc->bandlocked)); } } static int brcms_chspec_bw(u16 chanspec ) { { if (((int )chanspec & 3072) == 3072) { return (40); } else { } if (((int )chanspec & 3072) == 2048) { return (20); } else { } return (10); } } static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg ) { { if ((unsigned long )cfg == (unsigned long )((struct brcms_bss_cfg *)0)) { return; } else { } kfree((void const *)cfg->current_bss); kfree((void const *)cfg); return; } } static void brcms_c_detach_mfree(struct brcms_c_info *wlc ) { { if ((unsigned long )wlc == (unsigned long )((struct brcms_c_info *)0)) { return; } else { } brcms_c_bsscfg_mfree(wlc->bsscfg); kfree((void const *)wlc->pub); kfree((void const *)wlc->modulecb); kfree((void const *)wlc->default_bss); kfree((void const *)wlc->protection); kfree((void const *)wlc->stf); kfree((void const *)wlc->bandstate[0]); if ((unsigned long )wlc->corestate != (unsigned long )((struct brcms_core *)0)) { kfree((void const *)(wlc->corestate)->macstat_snapshot); } else { } kfree((void const *)wlc->corestate); if ((unsigned long )wlc->hw != (unsigned long )((struct brcms_hardware *)0)) { kfree((void const *)(wlc->hw)->bandstate[0]); } else { } kfree((void const *)wlc->hw); if ((unsigned long )wlc->beacon != (unsigned long )((struct sk_buff *)0)) { dev_kfree_skb_any(wlc->beacon); } else { } if ((unsigned long )wlc->probe_resp != (unsigned long )((struct sk_buff *)0)) { dev_kfree_skb_any(wlc->probe_resp); } else { } kfree((void const *)wlc); return; } } static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit ) { struct brcms_bss_cfg *cfg ; void *tmp ; void *tmp___0 ; { tmp = kzalloc(64UL, 32U); cfg = (struct brcms_bss_cfg *)tmp; if ((unsigned long )cfg == (unsigned long )((struct brcms_bss_cfg *)0)) { goto fail; } else { } tmp___0 = kzalloc(92UL, 32U); cfg->current_bss = (struct brcms_bss_info *)tmp___0; if ((unsigned long )cfg->current_bss == (unsigned long )((struct brcms_bss_info *)0)) { goto fail; } else { } return (cfg); fail: brcms_c_bsscfg_mfree(cfg); return ((struct brcms_bss_cfg *)0); } } static struct brcms_c_info *brcms_c_attach_malloc(uint unit , uint *err , uint devid ) { struct brcms_c_info *wlc ; void *tmp ; void *tmp___0 ; void *tmp___1 ; void *tmp___2 ; int i ; void *tmp___3 ; void *tmp___4 ; void *tmp___5 ; void *tmp___6 ; void *tmp___7 ; int i___0 ; void *tmp___8 ; void *tmp___9 ; { tmp = kzalloc(1160UL, 32U); wlc = (struct brcms_c_info *)tmp; if ((unsigned long )wlc == (unsigned long )((struct brcms_c_info *)0)) { *err = 1002U; goto fail; } else { } tmp___0 = kzalloc(112UL, 32U); wlc->pub = (struct brcms_pub *)tmp___0; if ((unsigned long )wlc->pub == (unsigned long )((struct brcms_pub *)0)) { *err = 1003U; goto fail; } else { } (wlc->pub)->wlc = wlc; tmp___1 = kzalloc(288UL, 32U); wlc->hw = (struct brcms_hardware *)tmp___1; if ((unsigned long )wlc->hw == (unsigned long )((struct brcms_hardware *)0)) { *err = 1005U; goto fail; } else { } (wlc->hw)->wlc = wlc; tmp___2 = kzalloc(112UL, 32U); (wlc->hw)->bandstate[0] = (struct brcms_hw_band *)tmp___2; if ((unsigned long )(wlc->hw)->bandstate[0] == (unsigned long )((struct brcms_hw_band *)0)) { *err = 1006U; goto fail; } else { i = 1; goto ldv_56064; ldv_56063: (wlc->hw)->bandstate[i] = (struct brcms_hw_band *)((unsigned long )(wlc->hw)->bandstate[0] + (unsigned long )i * 56UL); i = i + 1; ldv_56064: ; if (i <= 1) { goto ldv_56063; } else { } } tmp___3 = kzalloc(1056UL, 32U); wlc->modulecb = (struct modulecb *)tmp___3; if ((unsigned long )wlc->modulecb == (unsigned long )((struct modulecb *)0)) { *err = 1009U; goto fail; } else { } tmp___4 = kzalloc(92UL, 32U); wlc->default_bss = (struct brcms_bss_info *)tmp___4; if ((unsigned long )wlc->default_bss == (unsigned long )((struct brcms_bss_info *)0)) { *err = 1010U; goto fail; } else { } wlc->bsscfg = brcms_c_bsscfg_malloc(unit); if ((unsigned long )wlc->bsscfg == (unsigned long )((struct brcms_bss_cfg *)0)) { *err = 1011U; goto fail; } else { } tmp___5 = kzalloc(11UL, 32U); wlc->protection = (struct brcms_protection *)tmp___5; if ((unsigned long )wlc->protection == (unsigned long )((struct brcms_protection *)0)) { *err = 1016U; goto fail; } else { } tmp___6 = kzalloc(22UL, 32U); wlc->stf = (struct brcms_stf *)tmp___6; if ((unsigned long )wlc->stf == (unsigned long )((struct brcms_stf *)0)) { *err = 1017U; goto fail; } else { } tmp___7 = kzalloc(624UL, 32U); wlc->bandstate[0] = (struct brcms_band *)tmp___7; if ((unsigned long )wlc->bandstate[0] == (unsigned long )((struct brcms_band *)0)) { *err = 1025U; goto fail; } else { i___0 = 1; goto ldv_56068; ldv_56067: wlc->bandstate[i___0] = (struct brcms_band *)((unsigned long )wlc->bandstate[0] + (unsigned long )i___0 * 312UL); i___0 = i___0 + 1; ldv_56068: ; if (i___0 <= 1) { goto ldv_56067; } else { } } tmp___8 = kzalloc(64UL, 32U); wlc->corestate = (struct brcms_core *)tmp___8; if ((unsigned long )wlc->corestate == (unsigned long )((struct brcms_core *)0)) { *err = 1026U; goto fail; } else { } tmp___9 = kzalloc(128UL, 32U); (wlc->corestate)->macstat_snapshot = (struct macstat *)tmp___9; if ((unsigned long )(wlc->corestate)->macstat_snapshot == (unsigned long )((struct macstat *)0)) { *err = 1027U; goto fail; } else { } return (wlc); fail: brcms_c_detach_mfree(wlc); return ((struct brcms_c_info *)0); } } static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw , bool shortslot ) { struct bcma_device *core ; { core = wlc_hw->d11core; if ((int )shortslot) { bcma_write16(core, 1668, 519U); brcms_b_write_shm(wlc_hw, 16U, 9); } else { bcma_write16(core, 1668, 530U); brcms_b_write_shm(wlc_hw, 16U, 20); } return; } } static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc , u32 ratespec , u8 preamble_type , uint mac_len ) { uint nsyms ; uint dur ; uint Ndps ; uint kNdps ; uint rate ; uint tmp ; uint mcs ; int tot_streams ; u8 tmp___0 ; uint tmp___1 ; bool tmp___2 ; bool tmp___3 ; uint tmp___4 ; uint tmp___5 ; bool tmp___6 ; bool tmp___7 ; { dur = 0U; tmp = rspec2rate(ratespec); rate = tmp; if (rate == 0U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: WAR: using rate of 1 mbps\n", (wlc->pub)->unit); rate = 2U; } else { } tmp___7 = is_mcs_rate(ratespec); if ((int )tmp___7) { mcs = ratespec & 127U; tmp___0 = mcs_2_txstreams((int )((u8 )mcs)); tmp___1 = rspec_stc(ratespec); tot_streams = (int )((uint )tmp___0 + tmp___1); dur = (uint )((tot_streams + 6) * 4); if ((unsigned int )preamble_type == 4U) { dur = dur + 12U; } else { } tmp___2 = rspec_issgi(ratespec); tmp___3 = rspec_is40mhz(ratespec); tmp___4 = mcs_2_rate((int )((u8 )mcs), (int )tmp___3, (int )tmp___2); kNdps = tmp___4 * 4U; tmp___5 = rspec_stc(ratespec); if (tmp___5 == 0U) { nsyms = ((mac_len * 8000U + kNdps) + 21999U) / kNdps; } else { nsyms = (((mac_len * 4000U + kNdps) * 2U + 21999U) / (kNdps * 2U)) * 2U; } dur = nsyms * 4U + dur; if ((wlc->band)->bandtype == 2) { dur = dur + 6U; } else { } } else { tmp___6 = is_ofdm_rate(rate); if ((int )tmp___6) { dur = 16U; dur = dur + 4U; Ndps = rate * 2U; nsyms = (((mac_len + 2U) * 8U + Ndps) + 5U) / Ndps; dur = nsyms * 4U + dur; if ((wlc->band)->bandtype == 2) { dur = dur + 6U; } else { } } else { mac_len = mac_len * 16U; dur = ((mac_len + rate) - 1U) / rate; if ((int )preamble_type & 1) { dur = dur + 96U; } else { dur = dur + 192U; } } } return (dur); } } static void brcms_c_write_inits(struct brcms_hardware *wlc_hw , struct d11init const *inits ) { struct bcma_device *core ; int i ; uint offset ; u16 size ; u32 value ; { core = wlc_hw->d11core; __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_c_write_inits", "wl%d\n", wlc_hw->unit); i = 0; goto ldv_56100; ldv_56099: size = (inits + (unsigned long )i)->size; offset = (uint )(inits + (unsigned long )i)->addr; value = (inits + (unsigned long )i)->value; if ((unsigned int )size == 2U) { bcma_write16(core, (int )((u16 )offset), value); } else if ((unsigned int )size == 4U) { bcma_write32(core, (int )((u16 )offset), value); } else { goto ldv_56098; } i = i + 1; ldv_56100: ; if ((unsigned int )((unsigned short )(inits + (unsigned long )i)->addr) != 65535U) { goto ldv_56099; } else { } ldv_56098: ; return; } } static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw , u16 *mhfs ) { u8 idx ; u16 addr[5U] ; { addr[0] = 94U; addr[1] = 96U; addr[2] = 98U; addr[3] = 120U; addr[4] = 212U; idx = 0U; goto ldv_56108; ldv_56107: brcms_b_write_shm(wlc_hw, (uint )addr[(int )idx], (int )*(mhfs + (unsigned long )idx)); idx = (u8 )((int )idx + 1); ldv_56108: ; if ((unsigned int )idx <= 4U) { goto ldv_56107; } else { } return; } } static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw ) { struct brcms_ucode *ucode ; { ucode = & ((wlc_hw->wlc)->wl)->ucode; brcms_c_write_mhf(wlc_hw, (u16 *)(& (wlc_hw->band)->mhfs)); if (wlc_hw->corerev == 17U || wlc_hw->corerev == 23U) { if ((unsigned int )(wlc_hw->band)->phytype == 4U) { brcms_c_write_inits(wlc_hw, (struct d11init const *)ucode->d11n0bsinitvals16); } else { __brcms_err(& (wlc_hw->d11core)->dev, "%s: wl%d: unsupported phy in corerev %d\n", "brcms_c_ucode_bsinit", wlc_hw->unit, wlc_hw->corerev); } } else if (wlc_hw->corerev == 24U) { if ((unsigned int )(wlc_hw->band)->phytype == 8U) { brcms_c_write_inits(wlc_hw, (struct d11init const *)ucode->d11lcn0bsinitvals24); } else { __brcms_err(& (wlc_hw->d11core)->dev, "%s: wl%d: unsupported phy in core rev %d\n", "brcms_c_ucode_bsinit", wlc_hw->unit, wlc_hw->corerev); } } else { __brcms_err(& (wlc_hw->d11core)->dev, "%s: wl%d: unsupported corerev %d\n", "brcms_c_ucode_bsinit", wlc_hw->unit, wlc_hw->corerev); } return; } } static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw , u32 m , u32 v ) { struct bcma_device *core ; u32 ioctl ; u32 tmp ; { core = wlc_hw->d11core; tmp = bcma_aread32(core, 1032); ioctl = tmp & ~ m; bcma_awrite32(core, 1032, ioctl | v); return; } } static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw , bool clk ) { { __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_b_core_phy_clk", "wl%d: clk %d\n", wlc_hw->unit, (int )clk); wlc_hw->phyclk = clk; if (! clk) { brcms_b_core_ioctl(wlc_hw, 8202U, 10U); __const_udelay(4295UL); brcms_b_core_ioctl(wlc_hw, 10U, 8U); __const_udelay(4295UL); } else { brcms_b_core_ioctl(wlc_hw, 10U, 2U); __const_udelay(4295UL); brcms_b_core_ioctl(wlc_hw, 2U, 0U); __const_udelay(4295UL); } return; } } static void brcms_c_setxband(struct brcms_hardware *wlc_hw , uint bandunit ) { u32 gmode ; { __brcms_dbg(& (wlc_hw->d11core)->dev, 2U, "brcms_c_setxband", "wl%d: bandunit %d\n", wlc_hw->unit, bandunit); wlc_hw->band = wlc_hw->bandstate[bandunit]; (wlc_hw->wlc)->band = (wlc_hw->wlc)->bandstate[bandunit]; if ((int )wlc_hw->sbclk && ! wlc_hw->noreset) { gmode = 0U; if (bandunit == 0U) { gmode = 8192U; } else { } brcms_b_core_ioctl(wlc_hw, 8192U, gmode); } else { } return; } } static u32 brcms_c_setband_inact(struct brcms_c_info *wlc , uint bandunit ) { struct brcms_hardware *wlc_hw ; u32 macintmask ; u32 macctrl ; int __ret_warn_on ; long tmp ; { wlc_hw = wlc->hw; __brcms_dbg(& (wlc_hw->d11core)->dev, 2U, "brcms_c_setband_inact", "wl%d\n", wlc_hw->unit); macctrl = bcma_read32(wlc_hw->d11core, 288); __ret_warn_on = (int )macctrl & 1; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 816); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); macintmask = brcms_intrsoff(wlc->wl); wlc_phy_switch_radio((wlc_hw->band)->pi, 0); brcms_b_core_phy_clk(wlc_hw, 0); brcms_c_setxband(wlc_hw, bandunit); return (macintmask); } } static bool brcms_c_dotxstatus(struct brcms_c_info *wlc , struct tx_status *txs ) { struct sk_buff *p ; uint queue ; struct dma_pub *dma ; struct d11txh *txh ; struct scb *scb ; bool free_pdu ; int tx_rts ; int tx_frame_count ; int tx_rts_count ; uint totlen ; uint supr_status ; bool lastframe ; struct ieee80211_hdr *h ; u16 mcl ; struct ieee80211_tx_info *tx_info ; struct ieee80211_tx_rate *txrate ; int i ; bool fatal ; unsigned int xfts ; int tmp ; u16 sfbl ; u16 lfbl ; u16 fbl ; u16 ac_queue ; u8 tmp___0 ; int tmp___1 ; { p = (struct sk_buff *)0; queue = 6U; dma = (struct dma_pub *)0; txh = (struct d11txh *)0; scb = (struct scb *)0; fatal = 1; trace_brcms_txstatus((struct device const *)(& ((wlc->hw)->d11core)->dev), (int )txs->framelen, (int )txs->frameid, (int )txs->status, (int )txs->lasttxtime, (int )txs->sequence, (int )txs->phyerr, (int )txs->ackphyrxsh); if (((int )txs->status & 32) == 0 && ((int )txs->status & 64) != 0) { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 8U, "brcms_c_dotxstatus", "INTERMEDIATE but not AMPDU\n"); fatal = 0; goto out; } else { } queue = (uint )txs->frameid & 7U; if (queue > 5U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "queue %u >= NFIFO\n", queue); goto out; } else { } dma = (wlc->hw)->di[queue]; p = dma_getnexttxp((wlc->hw)->di[queue], 2); if ((unsigned long )p == (unsigned long )((struct sk_buff *)0)) { __brcms_err(& ((wlc->hw)->d11core)->dev, "dma_getnexttxp returned null!\n"); goto out; } else { } txh = (struct d11txh *)p->data; mcl = txh->MacTxControlLow; if ((unsigned int )txs->phyerr != 0U) { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 8U, "brcms_c_dotxstatus", "phyerr 0x%x, rate 0x%x\n", (int )txs->phyerr, (int )txh->MainRates); } else { } if ((int )txs->frameid != (int )txh->TxFrameID) { __brcms_err(& ((wlc->hw)->d11core)->dev, "frameid != txh->TxFrameID\n"); goto out; } else { } tx_info = IEEE80211_SKB_CB(p); h = (struct ieee80211_hdr *)txh + 7U; if ((unsigned long )tx_info->__annonCompField103.__annonCompField102.rate_driver_data[0] != (unsigned long )((void *)0)) { scb = & wlc->pri_scb; } else { } if ((tx_info->flags & 64U) != 0U) { brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs); fatal = 0; goto out; } else { } trace_brcms_txdesc___0((struct device const *)(& ((wlc->hw)->d11core)->dev), (void *)txh, 112UL); supr_status = (uint )txs->status & 28U; if (supr_status == 16U) { xfts = (unsigned int )txh->XtraFrameTypes; __brcms_dbg(& ((wlc->hw)->d11core)->dev, 8U, "brcms_c_dotxstatus", "Pkt tx suppressed, dest chan %u, current %d\n", (xfts >> 8) & 255U, (int )((unsigned char )(wlc->default_bss)->chanspec)); } else { } tx_rts = (int )txh->MacTxControlLow & 4; tx_frame_count = (int )txs->status >> 12; tx_rts_count = ((int )txs->status & 3840) >> 8; tmp = ieee80211_has_morefrags((int )h->frame_control); lastframe = tmp == 0; if (! lastframe) { __brcms_err(& ((wlc->hw)->d11core)->dev, "Not last frame!\n"); } else { if (queue <= 3U) { sfbl = (unsigned int )((u16 )((int )wlc->wme_retries[(int )wme_fifo2ac[queue]] >> 4)) & 15U; lfbl = (u16 )((int )wlc->wme_retries[(int )wme_fifo2ac[queue]] >> 12); } else { sfbl = wlc->SFBL; lfbl = wlc->LFBL; } txrate = (struct ieee80211_tx_rate *)(& tx_info->__annonCompField103.status.rates); if ((int )txrate->flags & 1) { fbl = lfbl; } else { fbl = sfbl; } ieee80211_tx_info_clear_status(tx_info); if ((int )fbl < tx_frame_count && (int )(txrate + 1UL)->idx >= 0) { txrate->count = (unsigned char )fbl; (txrate + 1UL)->count = (unsigned char )((int )((unsigned char )tx_frame_count) - (int )((unsigned char )fbl)); } else { txrate->count = (unsigned char )tx_frame_count; (txrate + 1UL)->idx = -1; (txrate + 1UL)->count = 0U; } i = 2; goto ldv_56172; ldv_56171: (txrate + (unsigned long )i)->idx = -1; (txrate + (unsigned long )i)->count = 0U; i = i + 1; ldv_56172: ; if (i <= 3) { goto ldv_56171; } else { } if (((int )txs->status & 2) != 0) { tx_info->flags = tx_info->flags | 512U; } else { } } totlen = p->len; free_pdu = 1; if ((int )lastframe) { skb_pull(p, 6U); skb_pull(p, 112U); ieee80211_tx_status_irqsafe((wlc->pub)->ieee_hw, p); } else { __brcms_err(& ((wlc->hw)->d11core)->dev, "%s: Not last frame => not calling tx_status\n", "brcms_c_dotxstatus"); } fatal = 0; out: ; if ((int )fatal) { if ((unsigned long )txh != (unsigned long )((struct d11txh *)0)) { trace_brcms_txdesc___0((struct device const *)(& ((wlc->hw)->d11core)->dev), (void *)txh, 112UL); } else { } brcmu_pkt_buf_free_skb(p); } else { } if ((unsigned long )dma != (unsigned long )((struct dma_pub *)0) && queue <= 5U) { tmp___0 = brcms_fifo_to_ac((int )((u8 )queue)); ac_queue = (u16 )tmp___0; if (dma->txavail > 4U && queue <= 3U) { tmp___1 = ieee80211_queue_stopped((wlc->pub)->ieee_hw, (int )ac_queue); if (tmp___1 != 0) { ieee80211_wake_queue((wlc->pub)->ieee_hw, (int )ac_queue); } else { } } else { } dma_kick_tx(dma); } else { } return (fatal); } } static bool brcms_b_txstatus(struct brcms_hardware *wlc_hw , bool bound , bool *fatal ) { struct bcma_device *core ; struct tx_status txstatus ; struct tx_status *txs ; u32 s1 ; u32 s2 ; uint n ; uint max_tx_num ; { n = 0U; max_tx_num = (int )bound ? 8U : 4294967295U; txs = & txstatus; core = wlc_hw->d11core; *fatal = 0; goto ldv_56190; ldv_56189: s1 = bcma_read32(core, 368); if (s1 == 4294967295U) { __brcms_err(& core->dev, "wl%d: %s: dead chip\n", wlc_hw->unit, "brcms_b_txstatus"); *fatal = 1; return (0); } else { } if ((s1 & 1U) == 0U) { goto ldv_56188; } else { } s2 = bcma_read32(core, 372); txs->status = (u16 )s1; txs->frameid = (u16 )(s1 >> 16); txs->sequence = (u16 )s2; txs->phyerr = (u16 )((s2 & 16711680U) >> 16); txs->lasttxtime = 0U; *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs); if ((int )*fatal) { return (0); } else { } n = n + 1U; ldv_56190: ; if (n < max_tx_num) { goto ldv_56189; } else { } ldv_56188: ; return (n >= max_tx_num); } } static void brcms_c_tbtt(struct brcms_c_info *wlc ) { { if ((unsigned int )(wlc->bsscfg)->type == 2U) { wlc->qvalid = wlc->qvalid | 4U; } else { } return; } } static void brcms_c_mhfdef(struct brcms_c_info *wlc , u16 *mhfs , u16 mhf2_init ) { struct brcms_hardware *wlc_hw ; { wlc_hw = wlc->hw; memset((void *)mhfs, 0, 10UL); *(mhfs + 1UL) = (u16 )((int )*(mhfs + 1UL) | (int )mhf2_init); if ((wlc_hw->boardflags & 32U) != 0U) { *mhfs = (u16 )((unsigned int )*mhfs | 1024U); } else { } if ((unsigned int )(wlc_hw->band)->phytype == 4U && (unsigned int )(wlc_hw->band)->phyrev <= 1U) { *(mhfs + 1UL) = (u16 )((unsigned int )*(mhfs + 1UL) | 2048U); *mhfs = (u16 )((unsigned int )*mhfs | 512U); } else { } return; } } static uint dmareg(uint direction , uint fifonum ) { { if (direction == 1U) { return ((uint )((unsigned long )fifonum + 8UL) * 64U); } else { } return ((uint )((unsigned long )fifonum + 8UL) * 64U + 32U); } } static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc , uint j , bool wme ) { uint i ; char name[8U] ; u16 pio_mhf2 ; struct brcms_hardware *wlc_hw ; uint unit ; int dma_attach_err ; uint tmp ; uint tmp___0 ; uint tmp___1 ; uint tmp___2 ; uint tmp___3 ; uint tmp___4 ; unsigned long tmp___5 ; { pio_mhf2 = 0U; wlc_hw = wlc->hw; unit = wlc_hw->unit; snprintf((char *)(& name), 8UL, "wl%d", unit); if ((unsigned long )wlc_hw->di[0] == (unsigned long )((struct dma_pub *)0)) { dma_attach_err = 0; tmp = dmareg(2U, 0U); if ((int )wme) { tmp___0 = dmareg(1U, 0U); tmp___1 = tmp___0; } else { tmp___1 = 0U; } wlc_hw->di[0] = dma_attach((char *)(& name), wlc, tmp___1, tmp, (int )wme ? 64U : 0U, 256U, 2048U, -1, 32U, 38U); dma_attach_err = ((unsigned long )wlc_hw->di[0] == (unsigned long )((struct dma_pub *)0)) | dma_attach_err; tmp___2 = dmareg(1U, 1U); wlc_hw->di[1] = dma_attach((char *)(& name), wlc, tmp___2, 0U, 64U, 0U, 0U, -1, 0U, 0U); dma_attach_err = ((unsigned long )wlc_hw->di[1] == (unsigned long )((struct dma_pub *)0)) | dma_attach_err; tmp___3 = dmareg(1U, 2U); wlc_hw->di[2] = dma_attach((char *)(& name), wlc, tmp___3, 0U, 64U, 0U, 0U, -1, 0U, 0U); dma_attach_err = ((unsigned long )wlc_hw->di[2] == (unsigned long )((struct dma_pub *)0)) | dma_attach_err; tmp___4 = dmareg(1U, 3U); wlc_hw->di[3] = dma_attach((char *)(& name), wlc, tmp___4, 0U, 64U, 0U, 0U, -1, 0U, 0U); dma_attach_err = ((unsigned long )wlc_hw->di[3] == (unsigned long )((struct dma_pub *)0)) | dma_attach_err; if (dma_attach_err != 0) { __brcms_err(& (wlc_hw->d11core)->dev, "wl%d: wlc_attach: dma_attach failed\n", unit); return (0); } else { } i = 0U; goto ldv_56216; ldv_56215: ; if ((unsigned long )wlc_hw->di[i] != (unsigned long )((struct dma_pub *)0)) { tmp___5 = dma_getvar(wlc_hw->di[i], "&txavail"); wlc_hw->txavail[i] = (uint *)tmp___5; } else { } i = i + 1U; ldv_56216: ; if (i <= 5U) { goto ldv_56215; } else { } } else { } brcms_c_mhfdef(wlc, (u16 *)(& (wlc_hw->band)->mhfs), (int )pio_mhf2); return (1); } } static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw ) { uint j ; { j = 0U; goto ldv_56223; ldv_56222: ; if ((unsigned long )wlc_hw->di[j] != (unsigned long )((struct dma_pub *)0)) { dma_detach(wlc_hw->di[j]); wlc_hw->di[j] = (struct dma_pub *)0; } else { } j = j + 1U; ldv_56223: ; if (j <= 5U) { goto ldv_56222; } else { } return; } } static void brcms_b_info_init(struct brcms_hardware *wlc_hw ) { struct brcms_c_info *wlc ; { wlc = wlc_hw->wlc; wlc->defmacintmask = 2955389028U; wlc_hw->shortslot = 0; wlc_hw->SFBL = 3U; wlc_hw->LFBL = 2U; wlc_hw->SRL = 7U; wlc_hw->LRL = 4U; wlc_hw->chanspec = ch20mhz_chspec(1); return; } } static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw ) { uint countdown ; u16 tmp ; { __const_udelay(171800UL); countdown = (uint )((int )(wlc_hw->wlc)->fastpwrup_dly + 9); goto ldv_56234; ldv_56233: __const_udelay(42950UL); countdown = countdown - 10U; ldv_56234: tmp = brcms_b_read_shm(wlc_hw, 64U); if ((unsigned int )tmp == 4U && countdown > 9U) { goto ldv_56233; } else { } return; } } static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw , enum bcma_clkmode mode ) { uint countdown ; u32 tmp ; int __ret_warn_on ; u32 tmp___0 ; long tmp___1 ; uint countdown___0 ; u32 tmp___2 ; int tmp___3 ; u32 tmp___4 ; int __ret_warn_on___0 ; u32 tmp___5 ; long tmp___6 ; u32 tmp___7 ; { tmp___7 = ai_get_cccaps(wlc_hw->sih); if ((tmp___7 & 268435456U) != 0U) { if ((int )wlc_hw->clk) { if ((unsigned int )mode == 0U) { bcma_set32(wlc_hw->d11core, 480, 2U); __const_udelay(274880UL); countdown = 15009U; goto ldv_56242; ldv_56241: __const_udelay(42950UL); countdown = countdown - 10U; ldv_56242: tmp = bcma_read32(wlc_hw->d11core, 480); if ((tmp & 131072U) == 0U && countdown > 9U) { goto ldv_56241; } else { } tmp___0 = bcma_read32(wlc_hw->d11core, 480); __ret_warn_on = (tmp___0 & 131072U) == 0U; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 1266); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); } else { tmp___3 = ai_get_pmurev(wlc_hw->sih); if (tmp___3 == 0) { tmp___4 = bcma_read32(wlc_hw->d11core, 480); if ((tmp___4 & 18U) != 0U) { countdown___0 = 15009U; goto ldv_56248; ldv_56247: __const_udelay(42950UL); countdown___0 = countdown___0 - 10U; ldv_56248: tmp___2 = bcma_read32(wlc_hw->d11core, 480); if ((tmp___2 & 131072U) == 0U && countdown___0 > 9U) { goto ldv_56247; } else { } } else { } } else { } bcma_mask32(wlc_hw->d11core, 480, 4294967293U); } } else { } wlc_hw->forcefastclk = (unsigned int )mode == 0U; } else { wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode); if ((int )wlc_hw->forcefastclk && (int )wlc_hw->clk) { tmp___5 = bcma_aread32(wlc_hw->d11core, 1280); __ret_warn_on___0 = (tmp___5 & 4U) == 0U; tmp___6 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___6 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 1295); } else { } ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); } else { } if ((int )wlc_hw->forcefastclk) { wlc_hw->wake_override = wlc_hw->wake_override | 16U; } else { wlc_hw->wake_override = wlc_hw->wake_override & 4294967279U; } } return; } } void brcms_b_mhf(struct brcms_hardware *wlc_hw , u8 idx , u16 mask , u16 val , int bands ) { u16 save ; u16 addr[5U] ; struct brcms_hw_band *band ; { addr[0] = 94U; addr[1] = 96U; addr[2] = 98U; addr[3] = 120U; addr[4] = 212U; if (((int )val & ~ ((int )mask)) != 0 || (unsigned int )idx > 4U) { return; } else { } switch (bands) { case 0: ; case 3: band = wlc_hw->band; goto ldv_56264; case 1: band = wlc_hw->bandstate[1]; goto ldv_56264; case 2: band = wlc_hw->bandstate[0]; goto ldv_56264; default: band = (struct brcms_hw_band *)0; } ldv_56264: ; if ((unsigned long )band != (unsigned long )((struct brcms_hw_band *)0)) { save = band->mhfs[(int )idx]; band->mhfs[(int )idx] = (u16 )(((int )((short )band->mhfs[(int )idx]) & ~ ((int )((short )mask))) | (int )((short )val)); if (((int )wlc_hw->clk && (int )band->mhfs[(int )idx] != (int )save) && (unsigned long )wlc_hw->band == (unsigned long )band) { brcms_b_write_shm(wlc_hw, (uint )addr[(int )idx], (int )band->mhfs[(int )idx]); } else { } } else { } if (bands == 3) { (wlc_hw->bandstate[0])->mhfs[(int )idx] = (u16 )(((int )((short )(wlc_hw->bandstate[0])->mhfs[(int )idx]) & ~ ((int )((short )mask))) | (int )((short )val)); (wlc_hw->bandstate[1])->mhfs[(int )idx] = (u16 )(((int )((short )(wlc_hw->bandstate[1])->mhfs[(int )idx]) & ~ ((int )((short )mask))) | (int )((short )val)); } else { } return; } } static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw ) { { wlc_hw->maccontrol = 0U; wlc_hw->suspended_fifos = 0U; wlc_hw->wake_override = 0U; wlc_hw->mute_override = 0U; brcms_b_mctrl(wlc_hw, 4294967295U, 67109888U); return; } } static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw ) { u32 maccontrol ; { maccontrol = wlc_hw->maccontrol; if (wlc_hw->wake_override != 0U) { maccontrol = maccontrol | 67108864U; } else { } if (wlc_hw->mute_override != 0U) { maccontrol = maccontrol & 4294705151U; maccontrol = maccontrol | 131072U; } else { } bcma_write32(wlc_hw->d11core, 288, maccontrol); return; } } void brcms_b_mctrl(struct brcms_hardware *wlc_hw , u32 mask , u32 val ) { u32 maccontrol ; u32 new_maccontrol ; { if ((~ mask & val) != 0U) { return; } else { } maccontrol = wlc_hw->maccontrol; new_maccontrol = (~ mask & maccontrol) | val; if (new_maccontrol == maccontrol) { return; } else { } wlc_hw->maccontrol = new_maccontrol; brcms_c_mctrl_write(wlc_hw); return; } } void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw , u32 override_bit ) { { if (wlc_hw->wake_override != 0U || (wlc_hw->maccontrol & 67108864U) != 0U) { wlc_hw->wake_override = wlc_hw->wake_override | override_bit; return; } else { } wlc_hw->wake_override = wlc_hw->wake_override | override_bit; brcms_c_mctrl_write(wlc_hw); brcms_b_wait_for_wake(wlc_hw); return; } } void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw , u32 override_bit ) { { wlc_hw->wake_override = wlc_hw->wake_override & ~ override_bit; if (wlc_hw->wake_override != 0U || (wlc_hw->maccontrol & 67108864U) != 0U) { return; } else { } brcms_c_mctrl_write(wlc_hw); return; } } static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw ) { { wlc_hw->mute_override = 1U; if ((wlc_hw->maccontrol & 393216U) == 131072U) { return; } else { } brcms_c_mctrl_write(wlc_hw); return; } } static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw ) { { if (wlc_hw->mute_override == 0U) { return; } else { } wlc_hw->mute_override = 0U; if ((wlc_hw->maccontrol & 393216U) == 131072U) { return; } else { } brcms_c_mctrl_write(wlc_hw); return; } } static void brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw , int match_reg_offset , u8 const *addr ) { struct bcma_device *core ; u16 mac_l ; u16 mac_m ; u16 mac_h ; { core = wlc_hw->d11core; __brcms_dbg(& core->dev, 4U, "brcms_b_set_addrmatch", "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit); mac_l = (u16 )((int )((short )*addr) | (int )((short )((int )*(addr + 1UL) << 8))); mac_m = (u16 )((int )((short )*(addr + 2UL)) | (int )((short )((int )*(addr + 3UL) << 8))); mac_h = (u16 )((int )((short )*(addr + 4UL)) | (int )((short )((int )*(addr + 5UL) << 8))); bcma_write16(core, 1056, (u32 )(match_reg_offset | 32)); bcma_write16(core, 1058, (u32 )mac_l); bcma_write16(core, 1058, (u32 )mac_m); bcma_write16(core, 1058, (u32 )mac_h); return; } } void brcms_b_write_template_ram(struct brcms_hardware *wlc_hw , int offset , int len , void *buf ) { struct bcma_device *core ; u32 word ; __le32 word_le ; __be32 word_be ; bool be_bit ; u32 tmp ; __u32 tmp___0 ; { core = wlc_hw->d11core; __brcms_dbg(& core->dev, 1U, "brcms_b_write_template_ram", "wl%d\n", wlc_hw->unit); bcma_write32(core, 304, (u32 )offset); tmp = bcma_read32(core, 288); be_bit = (tmp & 65536U) != 0U; goto ldv_56319; ldv_56318: memcpy((void *)(& word), (void const *)buf, 4UL); if ((int )be_bit) { tmp___0 = __fswab32(word); word_be = tmp___0; word = word_be; } else { word_le = word; word = word_le; } bcma_write32(core, 308, word); buf = buf + 4U; len = (int )((unsigned int )len - 4U); ldv_56319: ; if (len > 0) { goto ldv_56318; } else { } return; } } static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw , u16 newmin ) { { (wlc_hw->band)->CWmin = newmin; bcma_write32(wlc_hw->d11core, 352, 131075U); bcma_read32(wlc_hw->d11core, 352); bcma_write32(wlc_hw->d11core, 356, (u32 )newmin); return; } } static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw , u16 newmax ) { { (wlc_hw->band)->CWmax = newmax; bcma_write32(wlc_hw->d11core, 352, 131076U); bcma_read32(wlc_hw->d11core, 352); bcma_write32(wlc_hw->d11core, 356, (u32 )newmax); return; } } void brcms_b_bw_set(struct brcms_hardware *wlc_hw , u16 bw ) { bool fastclk ; u16 tmp ; { fastclk = wlc_hw->forcefastclk; if (! fastclk) { brcms_b_clkctl_clk(wlc_hw, 0); } else { } wlc_phy_bw_state_set((wlc_hw->band)->pi, (int )bw); brcms_b_phy_reset(wlc_hw); tmp = wlc_phy_chanspec_get((wlc_hw->band)->pi); wlc_phy_init((wlc_hw->band)->pi, (int )tmp); if (! fastclk) { brcms_b_clkctl_clk(wlc_hw, 1); } else { } return; } } static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw ) { u16 v ; struct brcms_c_info *wlc ; { wlc = wlc_hw->wlc; if ((unsigned int )(wlc->band)->phytype == 8U) { v = 300U; } else if ((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->band)->phyrev > 2U) { v = 2048U; } else { v = 1050U; } brcms_b_write_shm(wlc_hw, 148U, (int )v); return; } } static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw ) { u16 phyctl ; u16 phytxant ; u16 mask ; { phytxant = wlc_hw->bmac_phytxant; mask = 960U; phyctl = brcms_b_read_shm(wlc_hw, 392U); phyctl = (u16 )((~ ((int )((short )mask)) & (int )((short )phyctl)) | (int )((short )phytxant)); brcms_b_write_shm(wlc_hw, 392U, (int )phyctl); phyctl = brcms_b_read_shm(wlc_hw, 34U); phyctl = (u16 )((~ ((int )((short )mask)) & (int )((short )phyctl)) | (int )((short )phytxant)); brcms_b_write_shm(wlc_hw, 34U, (int )phyctl); return; } } static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw , u8 rate ) { uint i ; u8 plcp_rate ; struct plcp_signal_rate_lookup rate_lookup[8U] ; u16 tmp ; { plcp_rate = 0U; rate_lookup[0].rate = 12U; rate_lookup[0].signal_rate = 11U; rate_lookup[1].rate = 18U; rate_lookup[1].signal_rate = 15U; rate_lookup[2].rate = 24U; rate_lookup[2].signal_rate = 10U; rate_lookup[3].rate = 36U; rate_lookup[3].signal_rate = 14U; rate_lookup[4].rate = 48U; rate_lookup[4].signal_rate = 9U; rate_lookup[5].rate = 72U; rate_lookup[5].signal_rate = 13U; rate_lookup[6].rate = 96U; rate_lookup[6].signal_rate = 8U; rate_lookup[7].rate = 108U; rate_lookup[7].signal_rate = 12U; i = 0U; goto ldv_56359; ldv_56358: ; if ((int )rate_lookup[i].rate == (int )rate) { plcp_rate = rate_lookup[i].signal_rate; goto ldv_56357; } else { } i = i + 1U; ldv_56359: ; if (i <= 7U) { goto ldv_56358; } else { } ldv_56357: tmp = brcms_b_read_shm(wlc_hw, (uint )(((int )plcp_rate + 224) * 2)); return ((unsigned int )tmp * 2U); } } static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw ) { u8 rate ; u8 rates[8U] ; u16 entry_ptr ; u16 pctl1 ; uint i ; { rates[0] = 12U; rates[1] = 18U; rates[2] = 24U; rates[3] = 36U; rates[4] = 48U; rates[5] = 72U; rates[6] = 96U; rates[7] = 108U; if (((unsigned int )(wlc_hw->band)->phytype != 4U && (unsigned int )(wlc_hw->band)->phytype != 8U) && (unsigned int )(wlc_hw->band)->phytype != 6U) { return; } else { } i = 0U; goto ldv_56371; ldv_56370: rate = rates[i]; entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, (int )rate); pctl1 = brcms_b_read_shm(wlc_hw, (uint )((int )entry_ptr + 18)); pctl1 = (unsigned int )pctl1 & 65479U; pctl1 = (u16 )((int )((short )((int )wlc_hw->hw_stf_ss_opmode << 3)) | (int )((short )pctl1)); brcms_b_write_shm(wlc_hw, (uint )((int )entry_ptr + 18), (int )pctl1); i = i + 1U; ldv_56371: ; if (i <= 7U) { goto ldv_56370; } else { } return; } } static void brcms_b_bsinit(struct brcms_c_info *wlc , u16 chanspec ) { struct brcms_hardware *wlc_hw ; { wlc_hw = wlc->hw; __brcms_dbg(& (wlc_hw->d11core)->dev, 2U, "brcms_b_bsinit", "wl%d: bandunit %d\n", wlc_hw->unit, (wlc_hw->band)->bandunit); brcms_c_ucode_bsinit(wlc_hw); wlc_phy_init((wlc_hw->band)->pi, (int )chanspec); brcms_c_ucode_txant_set(wlc_hw); brcms_b_set_cwmin(wlc_hw, (int )(wlc_hw->band)->CWmin); brcms_b_set_cwmax(wlc_hw, (int )(wlc_hw->band)->CWmax); brcms_b_update_slot_timing(wlc_hw, (wlc_hw->band)->bandtype == 1 || (int )wlc_hw->shortslot != 0); brcms_b_write_shm(wlc_hw, 82U, (int )(wlc_hw->band)->phytype); brcms_b_write_shm(wlc_hw, 80U, (int )(wlc_hw->band)->phyrev); brcms_upd_ofdm_pctl1_table(wlc_hw); brcms_b_upd_synthpu(wlc_hw); return; } } void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw ) { { ai_cc_reg(wlc_hw->sih, 1616U, 4294967295U, 0U); __const_udelay(4295UL); ai_cc_reg(wlc_hw->sih, 1620U, 4U, 0U); __const_udelay(4295UL); ai_cc_reg(wlc_hw->sih, 1620U, 4U, 4U); __const_udelay(4295UL); ai_cc_reg(wlc_hw->sih, 1620U, 4U, 0U); __const_udelay(4295UL); return; } } void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw , bool clk ) { { if ((unsigned int )(wlc_hw->band)->phytype != 4U) { return; } else { } if ((int )clk) { brcms_b_core_ioctl(wlc_hw, 2U, 2U); } else { brcms_b_core_ioctl(wlc_hw, 2U, 0U); } return; } } void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw , bool clk ) { { if ((int )clk) { brcms_b_core_ioctl(wlc_hw, 16U, 16U); } else { brcms_b_core_ioctl(wlc_hw, 16U, 0U); } return; } } void brcms_b_phy_reset(struct brcms_hardware *wlc_hw ) { struct brcms_phy_pub *pih ; u32 phy_bw_clkbits ; bool phy_in_reset ; { pih = (wlc_hw->band)->pi; phy_in_reset = 0; __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_b_phy_reset", "wl%d: reset phy\n", wlc_hw->unit); if ((unsigned long )pih == (unsigned long )((struct brcms_phy_pub *)0)) { return; } else { } phy_bw_clkbits = wlc_phy_clk_bwbits((wlc_hw->band)->pi); if (((unsigned int )(wlc_hw->band)->phytype == 4U && (unsigned int )(wlc_hw->band)->phyrev > 2U) && (unsigned int )(wlc_hw->band)->phyrev <= 4U) { brcms_b_core_ioctl(wlc_hw, 192U, phy_bw_clkbits); __const_udelay(4295UL); brcms_b_core_phypll_reset(wlc_hw); brcms_b_core_ioctl(wlc_hw, 12U, 12U); phy_in_reset = 1; } else { brcms_b_core_ioctl(wlc_hw, 204U, phy_bw_clkbits | 12U); } __const_udelay(8590UL); brcms_b_core_phy_clk(wlc_hw, 1); if ((unsigned long )pih != (unsigned long )((struct brcms_phy_pub *)0)) { wlc_phy_anacore(pih, 1); } else { } return; } } static void brcms_b_setband(struct brcms_hardware *wlc_hw , uint bandunit , u16 chanspec ) { struct brcms_c_info *wlc ; u32 macintmask ; bool tmp ; int tmp___0 ; int __ret_warn_on ; u32 tmp___1 ; long tmp___2 ; { wlc = wlc_hw->wlc; tmp = bcma_core_is_enabled(wlc_hw->d11core); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { bcma_core_enable(wlc_hw->d11core, 0U); brcms_c_mctrl_reset(wlc_hw); } else { } macintmask = brcms_c_setband_inact(wlc, bandunit); if (! wlc_hw->up) { return; } else { } brcms_b_core_phy_clk(wlc_hw, 1); brcms_b_bsinit(wlc, (int )chanspec); if (wlc->macintstatus != 0U) { wlc->macintstatus = 32768U; } else { } brcms_intrsrestore(wlc->wl, macintmask); tmp___1 = bcma_read32(wlc_hw->d11core, 288); __ret_warn_on = (int )tmp___1 & 1; tmp___2 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___2 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 1857); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return; } } static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw ) { { if (((268435376 >> (int )wlc_hw->corerev) & 1) == 0) { dev_err((struct device const *)(& ((wlc_hw->wlc)->wiphy)->dev), "unsupported core rev %d\n", wlc_hw->corerev); return (0); } else { } return (1); } } static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw ) { uint boardrev ; uint brt ; uint b0 ; uint b1 ; uint b2 ; uint tmp ; { boardrev = (uint )wlc_hw->boardrev; brt = (boardrev & 61440U) >> 12; b0 = (boardrev & 3840U) >> 8; b1 = (boardrev & 240U) >> 4; b2 = boardrev & 15U; tmp = ai_get_boardvendor(wlc_hw->sih); if (tmp != 5348U) { return (1); } else { } if (boardrev == 0U) { return (0); } else { } if (boardrev <= 255U) { return (1); } else { } if (((((brt > 2U || brt == 0U) || b0 > 9U) || b0 == 0U) || b1 > 9U) || b2 > 9U) { return (0); } else { } return (1); } } static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw , u8 *etheraddr ) { struct ssb_sprom *sprom ; bool tmp ; int tmp___0 ; { sprom = & ((wlc_hw->d11core)->bus)->sprom; tmp = is_zero_ether_addr((u8 const *)(& sprom->il0mac)); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { memcpy((void *)etheraddr, (void const *)(& sprom->il0mac), 6UL); return; } else { } if (wlc_hw->_nbands > 1U) { memcpy((void *)etheraddr, (void const *)(& sprom->et1mac), 6UL); } else { memcpy((void *)etheraddr, (void const *)(& sprom->il0mac), 6UL); } return; } } static void brcms_b_xtal(struct brcms_hardware *wlc_hw , bool want ) { { __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_b_xtal", "wl%d: want %d\n", wlc_hw->unit, (int )want); if (! want && wlc_hw->pllreq != 0U) { return; } else { } wlc_hw->sbclk = want; if (! wlc_hw->sbclk) { wlc_hw->clk = 0; if ((unsigned long )wlc_hw->band != (unsigned long )((struct brcms_hw_band *)0) && (unsigned long )(wlc_hw->band)->pi != (unsigned long )((struct brcms_phy_pub *)0)) { wlc_phy_hw_clk_state_upd((wlc_hw->band)->pi, 0); } else { } } else { } return; } } static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw ) { bool v ; bool clk ; bool xtal ; u32 flags ; u32 tmp ; { flags = 0U; xtal = wlc_hw->sbclk; if (! xtal) { brcms_b_xtal(wlc_hw, 1); } else { } clk = wlc_hw->clk; if (! clk) { if (wlc_hw->corerev > 17U) { flags = flags | 4U; } else { } bcma_core_enable(wlc_hw->d11core, flags); brcms_c_mctrl_reset(wlc_hw); } else { } tmp = bcma_read32(wlc_hw->d11core, 344); v = (tmp & 65536U) != 0U; if (! clk) { bcma_core_disable(wlc_hw->d11core, 0U); } else { } if (! xtal) { brcms_b_xtal(wlc_hw, 0); } else { } return (v); } } static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw , uint fifo ) { struct dma_pub *di ; bool tmp ; { di = wlc_hw->di[fifo]; tmp = dma_rxreset(di); return (tmp); } } void brcms_b_corereset(struct brcms_hardware *wlc_hw , u32 flags ) { uint i ; bool fastclk ; bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; bool tmp___3 ; u32 tmp___4 ; { if (flags == 4294967295U) { flags = (unsigned long )(wlc_hw->band)->pi != (unsigned long )((struct brcms_phy_pub *)0) ? (wlc_hw->band)->core_flags : 0U; } else { } __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_b_corereset", "wl%d: core reset\n", wlc_hw->unit); fastclk = wlc_hw->forcefastclk; if (! fastclk) { brcms_b_clkctl_clk(wlc_hw, 0); } else { } tmp___3 = bcma_core_is_enabled(wlc_hw->d11core); if ((int )tmp___3) { i = 0U; goto ldv_56447; ldv_56446: ; if ((unsigned long )wlc_hw->di[i] != (unsigned long )((struct dma_pub *)0)) { tmp = dma_txreset(wlc_hw->di[i]); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { __brcms_err(& (wlc_hw->d11core)->dev, "wl%d: %s: dma_txreset[%d]: cannot stop dma\n", wlc_hw->unit, "brcms_b_corereset", i); } else { } } else { } i = i + 1U; ldv_56447: ; if (i <= 5U) { goto ldv_56446; } else { } if ((unsigned long )wlc_hw->di[0] != (unsigned long )((struct dma_pub *)0)) { tmp___1 = wlc_dma_rxreset(wlc_hw, 0U); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { __brcms_err(& (wlc_hw->d11core)->dev, "wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, "brcms_b_corereset", 0); } else { } } else { } } else { } if ((int )wlc_hw->noreset) { (wlc_hw->wlc)->macintstatus = 0U; brcms_b_mctrl(wlc_hw, 3U, 0U); return; } else { } if (wlc_hw->corerev > 17U) { flags = flags | 4U; } else { } wlc_hw->clk = 0; bcma_core_enable(wlc_hw->d11core, flags); wlc_hw->clk = 1; if ((unsigned long )wlc_hw->band != (unsigned long )((struct brcms_hw_band *)0) && (unsigned long )(wlc_hw->band)->pi != (unsigned long )((struct brcms_phy_pub *)0)) { wlc_phy_hw_clk_state_upd((wlc_hw->band)->pi, 1); } else { } brcms_c_mctrl_reset(wlc_hw); tmp___4 = ai_get_cccaps(wlc_hw->sih); if ((tmp___4 & 268435456U) != 0U) { brcms_b_clkctl_clk(wlc_hw, 0); } else { } brcms_b_phy_reset(wlc_hw); brcms_b_core_phypll_ctl(wlc_hw, 1); (wlc_hw->wlc)->macintstatus = 0U; if (! fastclk) { brcms_b_clkctl_clk(wlc_hw, 1); } else { } return; } } static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw ) { struct bcma_device *core ; u16 fifo_nu ; u16 txfifo_startblk ; u16 txfifo_endblk ; u16 txfifo_def ; u16 txfifo_def1 ; u16 txfifo_cmd ; { core = wlc_hw->d11core; txfifo_startblk = 6U; txfifo_startblk = 6U; fifo_nu = 0U; goto ldv_56460; ldv_56459: txfifo_endblk = (int )((u16 )*(wlc_hw->xmtfifo_sz + (unsigned long )fifo_nu)) + (int )txfifo_startblk; txfifo_def = (u16 )(((int )((short )txfifo_startblk) & 255) | (int )((short )(((int )txfifo_endblk + -1) << 8))); txfifo_def1 = (u16 )(((int )((short )((int )txfifo_startblk >> 8)) & 1) | ((int )((short )((unsigned int )txfifo_endblk + 65535U)) & 256)); txfifo_cmd = (u16 )((int )((short )((int )fifo_nu << 8)) | -32768); bcma_write16(core, 1344, (u32 )txfifo_cmd); bcma_write16(core, 1312, (u32 )txfifo_def); bcma_write16(core, 1324, (u32 )txfifo_def1); bcma_write16(core, 1344, (u32 )txfifo_cmd); txfifo_startblk = (int )((u16 )*(wlc_hw->xmtfifo_sz + (unsigned long )fifo_nu)) + (int )txfifo_startblk; fifo_nu = (u16 )((int )fifo_nu + 1); ldv_56460: ; if ((unsigned int )fifo_nu <= 5U) { goto ldv_56459; } else { } brcms_b_write_shm(wlc_hw, 152U, (int )*(wlc_hw->xmtfifo_sz + 1UL)); brcms_b_write_shm(wlc_hw, 154U, (int )*(wlc_hw->xmtfifo_sz + 2UL)); brcms_b_write_shm(wlc_hw, 156U, (int )((u16 )((int )((short )((int )*(wlc_hw->xmtfifo_sz + 3UL) << 8)) | (int )((short )*(wlc_hw->xmtfifo_sz))))); brcms_b_write_shm(wlc_hw, 158U, (int )((u16 )((int )((short )((int )*(wlc_hw->xmtfifo_sz + 5UL) << 8)) | (int )((short )*(wlc_hw->xmtfifo_sz + 4UL))))); return; } } void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw , u8 spurmode ) { struct bcma_device *core ; uint tmp ; uint tmp___0 ; { core = wlc_hw->d11core; tmp = ai_get_chip_id(wlc_hw->sih); if (tmp == 43224U) { goto _L; } else { tmp___0 = ai_get_chip_id(wlc_hw->sih); if (tmp___0 == 43225U) { _L: /* CIL Label */ if ((unsigned int )spurmode == 2U) { bcma_write16(core, 1582, 8322U); bcma_write16(core, 1584, 8U); } else if ((unsigned int )spurmode == 1U) { bcma_write16(core, 1582, 21313U); bcma_write16(core, 1584, 8U); } else { bcma_write16(core, 1582, 34953U); bcma_write16(core, 1584, 8U); } } else if ((unsigned int )(wlc_hw->band)->phytype == 8U) { if ((unsigned int )spurmode == 1U) { bcma_write16(core, 1582, 31968U); bcma_write16(core, 1584, 12U); } else { bcma_write16(core, 1582, 52429U); bcma_write16(core, 1584, 12U); } } else { } } return; } } void brcms_c_start_station(struct brcms_c_info *wlc , u8 *addr ) { { memcpy((void *)(& (wlc->pub)->cur_etheraddr), (void const *)addr, 6UL); (wlc->bsscfg)->type = 0; return; } } void brcms_c_start_ap(struct brcms_c_info *wlc , u8 *addr , u8 const *bssid , u8 *ssid , size_t ssid_len ) { { brcms_c_set_ssid(wlc, ssid, ssid_len); memcpy((void *)(& (wlc->pub)->cur_etheraddr), (void const *)addr, 6UL); memcpy((void *)(& (wlc->bsscfg)->BSSID), (void const *)bssid, 6UL); (wlc->bsscfg)->type = 1; brcms_b_mctrl(wlc->hw, 393216U, 393216U); return; } } void brcms_c_start_adhoc(struct brcms_c_info *wlc , u8 *addr ) { { memcpy((void *)(& (wlc->pub)->cur_etheraddr), (void const *)addr, 6UL); (wlc->bsscfg)->type = 2; brcms_b_mctrl(wlc->hw, 393216U, 0U); return; } } static void brcms_c_gpio_init(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; u32 gc ; u32 gm ; { wlc_hw = wlc->hw; brcms_b_mctrl(wlc_hw, 49152U, 0U); gm = 0U; gc = gm; if ((unsigned int )wlc_hw->antsel_type == 2U) { brcms_b_mhf(wlc_hw, 2, 1, 1, 3); brcms_b_mhf(wlc_hw, 2, 2, 2, 3); wlc_phy_antsel_init((wlc_hw->band)->pi, 0); } else if ((unsigned int )wlc_hw->antsel_type == 1U) { gc = gc | 12288U; gm = gc | gm; bcma_set16(wlc_hw->d11core, 1182, 12288); bcma_set16(wlc_hw->d11core, 1180, 12288); brcms_b_mhf(wlc_hw, 2, 1, 1, 3); brcms_b_mhf(wlc_hw, 2, 2, 0, 3); brcms_b_write_shm(wlc_hw, 194U, 6); } else { } if ((wlc_hw->boardflags & 2U) != 0U) { gc = gc | 512U; gm = gc | gm; } else { } bcma_chipco_gpio_control(& ((wlc_hw->d11core)->bus)->drv_cc, gm, gc); return; } } static void brcms_ucode_write(struct brcms_hardware *wlc_hw , __le32 const *ucode , size_t const nbytes ) { struct bcma_device *core ; uint i ; uint count ; { core = wlc_hw->d11core; __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_ucode_write", "wl%d\n", wlc_hw->unit); count = (uint )((unsigned long )nbytes / 4UL); bcma_write32(core, 352, 50331648U); bcma_read32(core, 352); i = 0U; goto ldv_56498; ldv_56497: bcma_write32(core, 356, *(ucode + (unsigned long )i)); i = i + 1U; ldv_56498: ; if (i < count) { goto ldv_56497; } else { } return; } } static void brcms_ucode_download(struct brcms_hardware *wlc_hw ) { struct brcms_c_info *wlc ; struct brcms_ucode *ucode ; { ucode = & ((wlc_hw->wlc)->wl)->ucode; wlc = wlc_hw->wlc; if ((int )wlc_hw->ucode_loaded) { return; } else { } if (wlc_hw->corerev == 17U || wlc_hw->corerev == 23U) { if ((unsigned int )(wlc_hw->band)->phytype == 4U) { brcms_ucode_write(wlc_hw, (__le32 const *)ucode->bcm43xx_16_mimo, ucode->bcm43xx_16_mimosz); wlc_hw->ucode_loaded = 1; } else { __brcms_err(& (wlc_hw->d11core)->dev, "%s: wl%d: unsupported phy in corerev %d\n", "brcms_ucode_download", wlc_hw->unit, wlc_hw->corerev); } } else if (wlc_hw->corerev == 24U) { if ((unsigned int )(wlc_hw->band)->phytype == 8U) { brcms_ucode_write(wlc_hw, (__le32 const *)ucode->bcm43xx_24_lcn, ucode->bcm43xx_24_lcnsz); wlc_hw->ucode_loaded = 1; } else { __brcms_err(& (wlc_hw->d11core)->dev, "%s: wl%d: unsupported phy in corerev %d\n", "brcms_ucode_download", wlc_hw->unit, wlc_hw->corerev); } } else { } return; } } void brcms_b_txant_set(struct brcms_hardware *wlc_hw , u16 phytxant ) { { wlc_hw->bmac_phytxant = phytxant; if (! wlc_hw->up) { return; } else { } brcms_c_ucode_txant_set(wlc_hw); return; } } u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw ) { { return ((unsigned short )((wlc_hw->wlc)->stf)->txant); } } void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw , u8 antsel_type ) { { wlc_hw->antsel_type = antsel_type; wlc_phy_antsel_type_set((wlc_hw->band)->pi, (int )antsel_type); return; } } static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw ) { bool fatal ; uint unit ; uint intstatus ; uint idx ; struct bcma_device *core ; u32 tmp ; { fatal = 0; core = wlc_hw->d11core; unit = wlc_hw->unit; idx = 0U; goto ldv_56529; ldv_56528: tmp = bcma_read32(core, (int )((unsigned int )((u16 )((unsigned long )idx + 4UL)) * 8U)); intstatus = tmp & 56320U; if (intstatus == 0U) { goto ldv_56525; } else { } __brcms_dbg(& core->dev, 16U, "brcms_b_fifoerrors", "wl%d: intstatus%d 0x%x\n", unit, idx, intstatus); if ((intstatus & 16384U) != 0U) { __brcms_err(& core->dev, "wl%d: fifo %d: receive fifo overflow\n", unit, idx); fatal = 1; } else { } if ((intstatus & 1024U) != 0U) { __brcms_err(& core->dev, "wl%d: fifo %d: descriptor error\n", unit, idx); fatal = 1; } else { } if ((intstatus & 2048U) != 0U) { __brcms_err(& core->dev, "wl%d: fifo %d: data error\n", unit, idx); fatal = 1; } else { } if ((intstatus & 4096U) != 0U) { __brcms_err(& core->dev, "wl%d: fifo %d: descriptor protocol error\n", unit, idx); fatal = 1; } else { } if ((intstatus & 8192U) != 0U) { __brcms_err(& core->dev, "wl%d: fifo %d: receive descriptor underflow\n", idx, unit); } else { } if ((intstatus & 32768U) != 0U) { __brcms_err(& core->dev, "wl%d: fifo %d: transmit fifo underflow\n", idx, unit); fatal = 1; } else { } if ((int )fatal) { brcms_fatal_error((wlc_hw->wlc)->wl); goto ldv_56527; } else { bcma_write32(core, (int )((unsigned int )((u16 )((unsigned long )idx + 4UL)) * 8U), intstatus); } ldv_56525: idx = idx + 1U; ldv_56529: ; if (idx <= 5U) { goto ldv_56528; } else { } ldv_56527: ; return; } } void brcms_c_intrson(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; { wlc_hw = wlc->hw; wlc->macintmask = wlc->defmacintmask; bcma_write32(wlc_hw->d11core, 300, wlc->macintmask); return; } } u32 brcms_c_intrsoff(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; u32 macintmask ; { wlc_hw = wlc->hw; if (! wlc_hw->clk) { return (0U); } else { } macintmask = wlc->macintmask; bcma_write32(wlc_hw->d11core, 300, 0U); bcma_read32(wlc_hw->d11core, 300); __const_udelay(4295UL); wlc->macintmask = 0U; return (wlc->macintstatus == 0U ? macintmask : 0U); } } void brcms_c_intrsrestore(struct brcms_c_info *wlc , u32 macintmask ) { struct brcms_hardware *wlc_hw ; { wlc_hw = wlc->hw; if (! wlc_hw->clk) { return; } else { } wlc->macintmask = macintmask; bcma_write32(wlc_hw->d11core, 300, wlc->macintmask); return; } } static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw , uint tx_fifo ) { u8 fifo ; { fifo = (u8 )(1 << (int )tx_fifo); if (((int )wlc_hw->suspended_fifos & (int )fifo) == (int )fifo) { return; } else { } if ((unsigned int )wlc_hw->suspended_fifos == 0U) { brcms_c_ucode_wake_override_set(wlc_hw, 8U); } else { } wlc_hw->suspended_fifos = (u8 )((int )wlc_hw->suspended_fifos | (int )fifo); if ((unsigned long )wlc_hw->di[tx_fifo] != (unsigned long )((struct dma_pub *)0)) { if (((unsigned int )(wlc_hw->band)->phytype == 4U || (unsigned int )(wlc_hw->band)->phytype == 8U) || (unsigned int )(wlc_hw->band)->phytype == 6U) { brcms_c_suspend_mac_and_wait(wlc_hw->wlc); } else { } dma_txsuspend(wlc_hw->di[tx_fifo]); if (((unsigned int )(wlc_hw->band)->phytype == 4U || (unsigned int )(wlc_hw->band)->phytype == 8U) || (unsigned int )(wlc_hw->band)->phytype == 6U) { brcms_c_enable_mac(wlc_hw->wlc); } else { } } else { } return; } } static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw , uint tx_fifo ) { { if ((unsigned long )wlc_hw->di[tx_fifo] != (unsigned long )((struct dma_pub *)0)) { dma_txresume(wlc_hw->di[tx_fifo]); } else { } if ((unsigned int )wlc_hw->suspended_fifos == 0U) { return; } else { wlc_hw->suspended_fifos = (u8 )((int )((signed char )wlc_hw->suspended_fifos) & ~ ((int )((signed char )(1 << (int )tx_fifo)))); if ((unsigned int )wlc_hw->suspended_fifos == 0U) { brcms_c_ucode_wake_override_clear(wlc_hw, 8U); } else { } } return; } } static void brcms_b_mute(struct brcms_hardware *wlc_hw , bool mute_tx ) { u8 null_ether_addr[6U] ; u8 *ethaddr ; { null_ether_addr[0] = 0U; null_ether_addr[1] = 0U; null_ether_addr[2] = 0U; null_ether_addr[3] = 0U; null_ether_addr[4] = 0U; null_ether_addr[5] = 0U; ethaddr = (u8 *)(& ((wlc_hw->wlc)->pub)->cur_etheraddr); if ((int )mute_tx) { brcms_b_tx_fifo_suspend(wlc_hw, 1U); brcms_b_tx_fifo_suspend(wlc_hw, 3U); brcms_b_tx_fifo_suspend(wlc_hw, 0U); brcms_b_tx_fifo_suspend(wlc_hw, 2U); brcms_b_set_addrmatch(wlc_hw, 0, (u8 const *)(& null_ether_addr)); } else { brcms_b_tx_fifo_resume(wlc_hw, 1U); brcms_b_tx_fifo_resume(wlc_hw, 3U); brcms_b_tx_fifo_resume(wlc_hw, 0U); brcms_b_tx_fifo_resume(wlc_hw, 2U); brcms_b_set_addrmatch(wlc_hw, 0, (u8 const *)ethaddr); } wlc_phy_mute_upd((wlc_hw->band)->pi, (int )mute_tx, 0U); if ((int )mute_tx) { brcms_c_ucode_mute_override_set(wlc_hw); } else { brcms_c_ucode_mute_override_clear(wlc_hw); } return; } } void brcms_c_mute(struct brcms_c_info *wlc , bool mute_tx ) { { brcms_b_mute(wlc->hw, (int )mute_tx); return; } } __inline static u32 wlc_intstatus(struct brcms_c_info *wlc , bool in_isr ) { struct brcms_hardware *wlc_hw ; struct bcma_device *core ; u32 macintstatus ; u32 mask ; bool tmp ; { wlc_hw = wlc->hw; core = wlc_hw->d11core; macintstatus = bcma_read32(core, 296); mask = (int )in_isr ? wlc->macintmask : wlc->defmacintmask; trace_brcms_macintstatus((struct device const *)(& core->dev), (int )in_isr, macintstatus, mask); tmp = brcms_deviceremoved(wlc); if ((int )tmp) { return (4294967295U); } else { } if (macintstatus == 4294967295U) { return (0U); } else { } macintstatus = macintstatus & mask; if (macintstatus == 0U) { return (0U); } else { } bcma_write32(core, 300, 0U); bcma_read32(core, 300); wlc->macintmask = 0U; bcma_write32(core, 296, macintstatus); if ((macintstatus & 32768U) != 0U) { bcma_write32(core, 32, 65536U); } else { } return (macintstatus); } } bool brcms_c_intrsupd(struct brcms_c_info *wlc ) { u32 macintstatus ; { macintstatus = wlc_intstatus(wlc, 0); if (macintstatus == 4294967295U) { return (0); } else { } wlc->macintstatus = wlc->macintstatus | macintstatus; return (1); } } bool brcms_c_isr(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; u32 macintstatus ; { wlc_hw = wlc->hw; if (! wlc_hw->up || wlc->macintmask == 0U) { return (0); } else { } macintstatus = wlc_intstatus(wlc, 1); if (macintstatus == 4294967295U) { __brcms_err(& (wlc_hw->d11core)->dev, "DEVICEREMOVED detected in the ISR code path\n"); return (0); } else { } if (macintstatus == 0U) { return (0); } else { } wlc->macintstatus = macintstatus; return (1); } } void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; struct bcma_device *core ; u32 mc ; u32 mi ; int __ret_warn_on ; long tmp ; int __ret_warn_on___0 ; long tmp___0 ; int __ret_warn_on___1 ; long tmp___1 ; int __ret_warn_on___2 ; long tmp___2 ; uint countdown ; u32 tmp___3 ; u32 tmp___4 ; u32 tmp___5 ; u32 tmp___6 ; u32 tmp___7 ; int __ret_warn_on___3 ; long tmp___8 ; int __ret_warn_on___4 ; long tmp___9 ; int __ret_warn_on___5 ; long tmp___10 ; { wlc_hw = wlc->hw; core = wlc_hw->d11core; __brcms_dbg(& core->dev, 2U, "brcms_c_suspend_mac_and_wait", "wl%d: bandunit %d\n", wlc_hw->unit, (wlc_hw->band)->bandunit); wlc_hw->mac_suspend_depth = wlc_hw->mac_suspend_depth + 1U; if (wlc_hw->mac_suspend_depth > 1U) { return; } else { } brcms_c_ucode_wake_override_set(wlc_hw, 4U); mc = bcma_read32(core, 288); if (mc == 4294967295U) { __brcms_err(& core->dev, "wl%d: %s: dead chip\n", wlc_hw->unit, "brcms_c_suspend_mac_and_wait"); brcms_down(wlc->wl); return; } else { } __ret_warn_on = (mc & 4U) != 0U; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2671); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); __ret_warn_on___0 = (mc & 2U) == 0U; tmp___0 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2672); } else { } ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); __ret_warn_on___1 = (mc & 1U) == 0U; tmp___1 = ldv__builtin_expect(__ret_warn_on___1 != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2673); } else { } ldv__builtin_expect(__ret_warn_on___1 != 0, 0L); mi = bcma_read32(core, 296); if (mi == 4294967295U) { __brcms_err(& core->dev, "wl%d: %s: dead chip\n", wlc_hw->unit, "brcms_c_suspend_mac_and_wait"); brcms_down(wlc->wl); return; } else { } __ret_warn_on___2 = (int )mi & 1; tmp___2 = ldv__builtin_expect(__ret_warn_on___2 != 0, 0L); if (tmp___2 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2682); } else { } ldv__builtin_expect(__ret_warn_on___2 != 0, 0L); brcms_b_mctrl(wlc_hw, 1U, 0U); countdown = 83009U; goto ldv_56598; ldv_56597: __const_udelay(42950UL); countdown = countdown - 10U; ldv_56598: tmp___3 = bcma_read32(core, 296); if ((tmp___3 & 1U) == 0U && countdown > 9U) { goto ldv_56597; } else { } tmp___7 = bcma_read32(core, 296); if ((tmp___7 & 1U) == 0U) { __brcms_err(& core->dev, "wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n", wlc_hw->unit, 83000); tmp___4 = bcma_read16(core, 1168); tmp___5 = bcma_read32(core, 344); tmp___6 = bcma_read32(core, 340); __brcms_err(& core->dev, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n", wlc_hw->unit, tmp___6, tmp___5, tmp___4); } else { } mc = bcma_read32(core, 288); if (mc == 4294967295U) { __brcms_err(& core->dev, "wl%d: %s: dead chip\n", wlc_hw->unit, "brcms_c_suspend_mac_and_wait"); brcms_down(wlc->wl); return; } else { } __ret_warn_on___3 = (mc & 4U) != 0U; tmp___8 = ldv__builtin_expect(__ret_warn_on___3 != 0, 0L); if (tmp___8 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2707); } else { } ldv__builtin_expect(__ret_warn_on___3 != 0, 0L); __ret_warn_on___4 = (mc & 2U) == 0U; tmp___9 = ldv__builtin_expect(__ret_warn_on___4 != 0, 0L); if (tmp___9 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2708); } else { } ldv__builtin_expect(__ret_warn_on___4 != 0, 0L); __ret_warn_on___5 = (int )mc & 1; tmp___10 = ldv__builtin_expect(__ret_warn_on___5 != 0, 0L); if (tmp___10 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2709); } else { } ldv__builtin_expect(__ret_warn_on___5 != 0, 0L); return; } } void brcms_c_enable_mac(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; struct bcma_device *core ; u32 mc ; u32 mi ; int __ret_warn_on ; long tmp ; int __ret_warn_on___0 ; long tmp___0 ; int __ret_warn_on___1 ; long tmp___1 ; int __ret_warn_on___2 ; long tmp___2 ; int __ret_warn_on___3 ; long tmp___3 ; int __ret_warn_on___4 ; long tmp___4 ; int __ret_warn_on___5 ; long tmp___5 ; { wlc_hw = wlc->hw; core = wlc_hw->d11core; __brcms_dbg(& core->dev, 2U, "brcms_c_enable_mac", "wl%d: bandunit %d\n", wlc_hw->unit, (wlc->band)->bandunit); wlc_hw->mac_suspend_depth = wlc_hw->mac_suspend_depth - 1U; if (wlc_hw->mac_suspend_depth != 0U) { return; } else { } mc = bcma_read32(core, 288); __ret_warn_on = (mc & 4U) != 0U; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2729); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); __ret_warn_on___0 = (int )mc & 1; tmp___0 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2730); } else { } ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); __ret_warn_on___1 = (mc & 2U) == 0U; tmp___1 = ldv__builtin_expect(__ret_warn_on___1 != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2731); } else { } ldv__builtin_expect(__ret_warn_on___1 != 0, 0L); brcms_b_mctrl(wlc_hw, 1U, 1U); bcma_write32(core, 296, 1U); mc = bcma_read32(core, 288); __ret_warn_on___2 = (mc & 4U) != 0U; tmp___2 = ldv__builtin_expect(__ret_warn_on___2 != 0, 0L); if (tmp___2 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2737); } else { } ldv__builtin_expect(__ret_warn_on___2 != 0, 0L); __ret_warn_on___3 = (mc & 1U) == 0U; tmp___3 = ldv__builtin_expect(__ret_warn_on___3 != 0, 0L); if (tmp___3 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2738); } else { } ldv__builtin_expect(__ret_warn_on___3 != 0, 0L); __ret_warn_on___4 = (mc & 2U) == 0U; tmp___4 = ldv__builtin_expect(__ret_warn_on___4 != 0, 0L); if (tmp___4 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2739); } else { } ldv__builtin_expect(__ret_warn_on___4 != 0, 0L); mi = bcma_read32(core, 296); __ret_warn_on___5 = (int )mi & 1; tmp___5 = ldv__builtin_expect(__ret_warn_on___5 != 0, 0L); if (tmp___5 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 2742); } else { } ldv__builtin_expect(__ret_warn_on___5 != 0, 0L); brcms_c_ucode_wake_override_clear(wlc_hw, 4U); return; } } void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw , u8 stf_mode ) { { wlc_hw->hw_stf_ss_opmode = stf_mode; if ((int )wlc_hw->clk) { brcms_upd_ofdm_pctl1_table(wlc_hw); } else { } return; } } static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw ) { struct bcma_device *core ; u32 w ; u32 val ; struct wiphy *wiphy ; { core = wlc_hw->d11core; wiphy = (wlc_hw->wlc)->wiphy; bcma_write32(core, 352, 65536U); bcma_read32(core, 352); w = bcma_read32(core, 356); bcma_write32(core, 352, 65536U); bcma_read32(core, 352); bcma_write32(core, 356, 2857719210U); bcma_write32(core, 352, 65536U); bcma_read32(core, 352); val = bcma_read32(core, 356); if (val != 2857719210U) { dev_err((struct device const *)(& wiphy->dev), "wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val); return (0); } else { } bcma_write32(core, 352, 65536U); bcma_read32(core, 352); bcma_write32(core, 356, 1437248085U); bcma_write32(core, 352, 65536U); bcma_read32(core, 352); val = bcma_read32(core, 356); if (val != 1437248085U) { dev_err((struct device const *)(& wiphy->dev), "wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val); return (0); } else { } bcma_write32(core, 352, 65536U); bcma_read32(core, 352); bcma_write32(core, 356, w); bcma_write32(core, 396, 0U); w = bcma_read32(core, 288); if (w != 67109888U && w != 2214593536U) { dev_err((struct device const *)(& wiphy->dev), "wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, 67109888, 2214593536U); return (0); } else { } return (1); } } void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw , bool on ) { struct bcma_device *core ; u32 tmp ; uint countdown ; u32 tmp___0 ; uint countdown___0 ; u32 tmp___1 ; uint tmp___2 ; { core = wlc_hw->d11core; __brcms_dbg(& core->dev, 1U, "brcms_b_core_phypll_ctl", "wl%d\n", wlc_hw->unit); tmp = 0U; if ((int )on) { tmp___2 = ai_get_chip_id(wlc_hw->sih); if (tmp___2 == 17171U) { bcma_set32(core, 480, 784U); countdown = 100009U; goto ldv_56648; ldv_56647: __const_udelay(42950UL); countdown = countdown - 10U; ldv_56648: tmp___0 = bcma_read32(core, 480); if ((tmp___0 & 131072U) == 0U && countdown > 9U) { goto ldv_56647; } else { } tmp = bcma_read32(core, 480); if ((tmp & 131072U) == 0U) { __brcms_err(& core->dev, "%s: turn on PHY PLL failed\n", "brcms_b_core_phypll_ctl"); } else { } } else { bcma_set32(core, 480, tmp | 768U); countdown___0 = 100009U; goto ldv_56652; ldv_56651: __const_udelay(42950UL); countdown___0 = countdown___0 - 10U; ldv_56652: tmp___1 = bcma_read32(core, 480); if ((tmp___1 & 50331648U) != 50331648U && countdown___0 > 9U) { goto ldv_56651; } else { } tmp = bcma_read32(core, 480); if ((tmp & 50331648U) != 50331648U) { __brcms_err(& core->dev, "%s: turn on PHY PLL failed\n", "brcms_b_core_phypll_ctl"); } else { } } } else { bcma_mask32(core, 480, 4294966783U); bcma_read32(core, 480); } return; } } static void brcms_c_coredisable(struct brcms_hardware *wlc_hw ) { bool dev_gone ; { __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_c_coredisable", "wl%d: disable core\n", wlc_hw->unit); dev_gone = brcms_deviceremoved(wlc_hw->wlc); if ((int )dev_gone) { return; } else { } if ((int )wlc_hw->noreset) { return; } else { } wlc_phy_switch_radio((wlc_hw->band)->pi, 0); wlc_phy_anacore((wlc_hw->band)->pi, 0); brcms_b_core_phypll_ctl(wlc_hw, 0); wlc_hw->clk = 0; bcma_core_disable(wlc_hw->d11core, 0U); wlc_phy_hw_clk_state_upd((wlc_hw->band)->pi, 0); return; } } static void brcms_c_flushqueues(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; uint i ; u8 tmp ; { wlc_hw = wlc->hw; i = 0U; goto ldv_56665; ldv_56664: ; if ((unsigned long )wlc_hw->di[i] != (unsigned long )((struct dma_pub *)0)) { dma_txreclaim(wlc_hw->di[i], 1); if (i <= 3U) { tmp = brcms_fifo_to_ac((int )((u8 )i)); ieee80211_wake_queue((wlc->pub)->ieee_hw, (int )tmp); } else { } } else { } i = i + 1U; ldv_56665: ; if (i <= 5U) { goto ldv_56664; } else { } dma_rxreclaim(wlc_hw->di[0]); return; } } static u16 brcms_b_read_objmem(struct brcms_hardware *wlc_hw , uint offset , u32 sel ) { struct bcma_device *core ; u16 objoff ; u32 tmp ; { core = wlc_hw->d11core; objoff = 356U; bcma_write32(core, 352, (offset >> 2) | sel); bcma_read32(core, 352); if ((offset & 2U) != 0U) { objoff = (unsigned int )objoff + 2U; } else { } tmp = bcma_read16(core, (int )objoff); return ((u16 )tmp); } } static void brcms_b_write_objmem(struct brcms_hardware *wlc_hw , uint offset , u16 v , u32 sel ) { struct bcma_device *core ; u16 objoff ; { core = wlc_hw->d11core; objoff = 356U; bcma_write32(core, 352, (offset >> 2) | sel); bcma_read32(core, 352); if ((offset & 2U) != 0U) { objoff = (unsigned int )objoff + 2U; } else { } bcma_write16(core, (int )objoff, (u32 )v); return; } } u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw , uint offset ) { u16 tmp ; { tmp = brcms_b_read_objmem(wlc_hw, offset, 65536U); return (tmp); } } void brcms_b_write_shm(struct brcms_hardware *wlc_hw , uint offset , u16 v ) { { brcms_b_write_objmem(wlc_hw, offset, (int )v, 65536U); return; } } void brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw , uint offset , void const *buf , int len , u32 sel ) { u16 v ; u8 const *p ; int i ; { p = (u8 const *)buf; if ((len <= 0 || (int )offset & 1) || len & 1) { return; } else { } i = 0; goto ldv_56702; ldv_56701: v = (u16 )((int )((short )*(p + (unsigned long )i)) | (int )((short )((int )*(p + ((unsigned long )i + 1UL)) << 8))); brcms_b_write_objmem(wlc_hw, offset + (uint )i, (int )v, sel); i = i + 2; ldv_56702: ; if (i < len) { goto ldv_56701; } else { } return; } } void brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw , uint offset , void *buf , int len , u32 sel ) { u16 v ; u8 *p ; int i ; { p = (u8 *)buf; if ((len <= 0 || (int )offset & 1) || len & 1) { return; } else { } i = 0; goto ldv_56715; ldv_56714: v = brcms_b_read_objmem(wlc_hw, offset + (uint )i, sel); *(p + (unsigned long )i) = (u8 )v; *(p + ((unsigned long )i + 1UL)) = (u8 )((int )v >> 8); i = i + 2; ldv_56715: ; if (i < len) { goto ldv_56714; } else { } return; } } static void brcms_c_copyto_shm(struct brcms_c_info *wlc , uint offset , void const *buf , int len ) { { brcms_b_copyto_objmem(wlc->hw, offset, buf, len, 65536U); return; } } static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw , u16 SRL , u16 LRL ) { { wlc_hw->SRL = SRL; wlc_hw->LRL = LRL; if ((int )wlc_hw->up) { bcma_write32(wlc_hw->d11core, 352, 131078U); bcma_read32(wlc_hw->d11core, 352); bcma_write32(wlc_hw->d11core, 356, (u32 )wlc_hw->SRL); bcma_write32(wlc_hw->d11core, 352, 131079U); bcma_read32(wlc_hw->d11core, 352); bcma_write32(wlc_hw->d11core, 356, (u32 )wlc_hw->LRL); } else { } return; } } static void brcms_b_pllreq(struct brcms_hardware *wlc_hw , bool set , u32 req_bit ) { { if ((int )set) { if ((wlc_hw->pllreq & req_bit) != 0U) { return; } else { } wlc_hw->pllreq = wlc_hw->pllreq | req_bit; if ((wlc_hw->pllreq & 4U) != 0U) { if (! wlc_hw->sbclk) { brcms_b_xtal(wlc_hw, 1); } else { } } else { } } else { if ((wlc_hw->pllreq & req_bit) == 0U) { return; } else { } wlc_hw->pllreq = wlc_hw->pllreq & ~ req_bit; if ((wlc_hw->pllreq & 4U) != 0U) { if ((int )wlc_hw->sbclk) { brcms_b_xtal(wlc_hw, 0); } else { } } else { } } return; } } static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw , u32 antsel_avail ) { { wlc_hw->antsel_avail = antsel_avail; return; } } static bool brcms_c_ps_allowed(struct brcms_c_info *wlc ) { { return (0); } } static void brcms_c_statsupd(struct brcms_c_info *wlc ) { int i ; struct macstat *macstats ; { if (! (wlc->pub)->up) { return; } else { } macstats = (wlc->core)->macstat_snapshot; brcms_b_copyfrom_objmem(wlc->hw, 224U, (void *)macstats, 128, 65536U); i = 0; goto ldv_56746; ldv_56745: ; if ((unsigned long )(wlc->hw)->di[i] != (unsigned long )((struct dma_pub *)0)) { dma_counterreset((wlc->hw)->di[i]); } else { } i = i + 1; ldv_56746: ; if (i <= 5) { goto ldv_56745; } else { } return; } } static void brcms_b_reset(struct brcms_hardware *wlc_hw ) { bool tmp ; int tmp___0 ; { tmp = brcms_deviceremoved(wlc_hw->wlc); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { brcms_b_corereset(wlc_hw, 4294967295U); } else { } brcms_c_flushqueues(wlc_hw->wlc); return; } } void brcms_c_reset(struct brcms_c_info *wlc ) { { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 1U, "brcms_c_reset", "wl%d\n", (wlc->pub)->unit); brcms_c_statsupd(wlc); memset((void *)(wlc->core)->macstat_snapshot, 0, 128UL); brcms_b_reset(wlc->hw); return; } } void brcms_c_init_scb(struct scb *scb ) { int i ; { memset((void *)scb, 0, 816UL); scb->flags = 65600U; i = 0; goto ldv_56760; ldv_56759: scb->seqnum[i] = 0U; scb->seqctl[i] = 65535U; i = i + 1; ldv_56760: ; if (i <= 7) { goto ldv_56759; } else { } scb->seqctl_nonqos = 65535U; scb->magic = 3203386110U; return; } } static void brcms_b_coreinit(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; struct bcma_device *core ; u32 sflags ; u32 bcnint_us ; uint i ; bool fifosz_fixup ; int err ; u16 buf[6U] ; struct brcms_ucode *ucode ; uint countdown ; u32 tmp ; u32 tmp___0 ; int __ret_warn_on ; u32 tmp___1 ; long tmp___2 ; { wlc_hw = wlc->hw; core = wlc_hw->d11core; i = 0U; fifosz_fixup = 0; err = 0; ucode = & ((wlc_hw->wlc)->wl)->ucode; __brcms_dbg(& core->dev, 1U, "brcms_b_coreinit", "wl%d: core init\n", wlc_hw->unit); brcms_b_mctrl(wlc_hw, 4294967295U, 67109892U); brcms_ucode_download(wlc_hw); fifosz_fixup = 1; bcma_write32(core, 296, 4294967295U); brcms_b_mctrl(wlc_hw, 4294967295U, 67240962U); countdown = 1000009U; goto ldv_56777; ldv_56776: __const_udelay(42950UL); countdown = countdown - 10U; ldv_56777: tmp = bcma_read32(core, 296); if ((tmp & 1U) == 0U && countdown > 9U) { goto ldv_56776; } else { } tmp___0 = bcma_read32(core, 296); if ((tmp___0 & 1U) == 0U) { __brcms_err(& core->dev, "wl%d: wlc_coreinit: ucode did not self-suspend!\n", wlc_hw->unit); } else { } brcms_c_gpio_init(wlc); sflags = bcma_aread32(core, 1280); if (wlc_hw->corerev == 17U || wlc_hw->corerev == 23U) { if ((unsigned int )(wlc_hw->band)->phytype == 4U) { brcms_c_write_inits(wlc_hw, (struct d11init const *)ucode->d11n0initvals16); } else { __brcms_err(& core->dev, "%s: wl%d: unsupported phy in corerev %d\n", "brcms_b_coreinit", wlc_hw->unit, wlc_hw->corerev); } } else if (wlc_hw->corerev == 24U) { if ((unsigned int )(wlc_hw->band)->phytype == 8U) { brcms_c_write_inits(wlc_hw, (struct d11init const *)ucode->d11lcn0initvals24); } else { __brcms_err(& core->dev, "%s: wl%d: unsupported phy in corerev %d\n", "brcms_b_coreinit", wlc_hw->unit, wlc_hw->corerev); } } else { __brcms_err(& core->dev, "%s: wl%d: unsupported corerev %d\n", "brcms_b_coreinit", wlc_hw->unit, wlc_hw->corerev); } if ((int )fifosz_fixup) { brcms_b_corerev_fifofixup(wlc_hw); } else { } buf[1] = brcms_b_read_shm(wlc_hw, 152U); if ((int )buf[1] != (int )((unsigned short )*(wlc_hw->xmtfifo_sz + 1UL))) { i = 1U; err = -1; } else { } buf[2] = brcms_b_read_shm(wlc_hw, 154U); if ((int )buf[2] != (int )((unsigned short )*(wlc_hw->xmtfifo_sz + 2UL))) { i = 2U; err = -1; } else { } buf[0] = brcms_b_read_shm(wlc_hw, 156U); buf[3] = (u16 )((int )buf[0] >> 8); buf[0] = (unsigned int )buf[0] & 255U; if ((int )buf[0] != (int )((unsigned short )*(wlc_hw->xmtfifo_sz))) { i = 0U; err = -1; } else { } if ((int )buf[3] != (int )((unsigned short )*(wlc_hw->xmtfifo_sz + 3UL))) { i = 3U; err = -1; } else { } buf[4] = brcms_b_read_shm(wlc_hw, 158U); buf[5] = (u16 )((int )buf[4] >> 8); buf[4] = (unsigned int )buf[4] & 255U; if ((int )buf[4] != (int )((unsigned short )*(wlc_hw->xmtfifo_sz + 4UL))) { i = 4U; err = -1; } else { } if ((int )buf[5] != (int )((unsigned short )*(wlc_hw->xmtfifo_sz + 5UL))) { i = 5U; err = -1; } else { } if (err != 0) { __brcms_err(& core->dev, "wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n", (int )buf[i], (int )*(wlc_hw->xmtfifo_sz + (unsigned long )i), i); } else { } tmp___1 = bcma_read32(core, 288); __ret_warn_on = tmp___1 == 4294967295U; tmp___2 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___2 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 3280); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); brcms_b_write_shm(wlc_hw, 128U, 8); brcms_b_write_shm(wlc_hw, 92U, 10); bcma_write32(core, 256, 16777216U); brcms_b_mctrl(wlc_hw, 1074135040U, 1073872896U); bcnint_us = 33554432U; bcma_write32(core, 392, bcnint_us << 6); bcma_write32(core, 396, bcnint_us); bcma_write32(core, 296, 16384U); bcma_write32(core, 36, 65536U); brcms_b_macphyclk_set(wlc_hw, 1); wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih); bcma_write16(core, 1704, (u32 )wlc->fastpwrup_dly); brcms_b_write_shm(wlc_hw, 22U, (int )((unsigned short )wlc_hw->corerev)); brcms_b_write_shm(wlc_hw, 192U, (int )((unsigned short )wlc_hw->machwcap)); brcms_b_write_shm(wlc_hw, 194U, (int )((unsigned short )(wlc_hw->machwcap >> 16))); bcma_write32(core, 352, 131078U); bcma_read32(core, 352); bcma_write32(core, 356, (u32 )wlc_hw->SRL); bcma_write32(core, 352, 131079U); bcma_read32(core, 352); bcma_write32(core, 356, (u32 )wlc_hw->LRL); brcms_b_write_shm(wlc_hw, 68U, (int )wlc_hw->SFBL); brcms_b_write_shm(wlc_hw, 70U, (int )wlc_hw->LFBL); bcma_mask16(core, 1672, 4095); bcma_write16(core, 1692, 1U); i = 0U; goto ldv_56782; ldv_56781: ; if ((unsigned long )wlc_hw->di[i] != (unsigned long )((struct dma_pub *)0)) { dma_txinit(wlc_hw->di[i]); } else { } i = i + 1U; ldv_56782: ; if (i <= 5U) { goto ldv_56781; } else { } dma_rxinit(wlc_hw->di[0]); dma_rxfill(wlc_hw->di[0]); return; } } static void brcms_b_init(struct brcms_hardware *wlc_hw , u16 chanspec ) { u32 macintmask ; bool fastclk ; struct brcms_c_info *wlc ; int tmp ; { wlc = wlc_hw->wlc; fastclk = wlc_hw->forcefastclk; if (! fastclk) { brcms_b_clkctl_clk(wlc_hw, 0); } else { } macintmask = brcms_intrsoff(wlc->wl); tmp = chspec_bandunit((int )chanspec); brcms_c_setxband(wlc_hw, (uint )tmp); wlc_phy_chanspec_radio_set((wlc_hw->band)->pi, (int )chanspec); wlc_phy_cal_init((wlc_hw->band)->pi); brcms_b_coreinit(wlc); brcms_b_bsinit(wlc, (int )chanspec); brcms_intrsrestore(wlc->wl, macintmask); wlc_hw->wake_override = wlc_hw->wake_override | 4U; wlc_hw->mac_suspend_depth = 1U; if (! fastclk) { brcms_b_clkctl_clk(wlc_hw, 1); } else { } return; } } static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc , u16 chanspec ) { { wlc->chanspec = chanspec; brcms_c_channel_set_chanspec(wlc->cmi, (int )chanspec, 127); if ((int )(wlc->stf)->ss_algosel_auto) { brcms_c_stf_ss_algo_channel_get(wlc, & (wlc->stf)->ss_algo_channel, (int )chanspec); } else { } brcms_c_stf_ss_update(wlc, wlc->band); return; } } static void brcms_default_rateset(struct brcms_c_info *wlc , struct brcms_c_rateset *rs ) { int tmp ; { tmp = brcms_chspec_bw((int )(wlc->default_bss)->chanspec); brcms_c_rateset_default(rs, (struct brcms_c_rateset const *)0, (uint )(wlc->band)->phytype, (wlc->band)->bandtype, 0, 255U, ((int )(wlc->pub)->_n_enab & 3) != 0, (int )((u8 )tmp), (int )(wlc->stf)->txstreams); return; } } static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc , struct brcms_c_rateset *rateset ) { u8 rate ; u8 mandatory ; u8 cck_basic ; u8 ofdm_basic ; u8 *br ; uint i ; bool tmp ; bool tmp___0 ; bool tmp___1 ; { cck_basic = 0U; ofdm_basic = 0U; br = (u8 *)(& (wlc->band)->basic_rate); memset((void *)br, 0, 109UL); i = 0U; goto ldv_56811; ldv_56810: ; if ((int )((signed char )rateset->rates[i]) >= 0) { goto ldv_56809; } else { } rate = (unsigned int )rateset->rates[i] & 127U; if ((unsigned int )rate > 108U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "brcms_c_rate_lookup_init: invalid rate 0x%X in rate set\n", (int )rateset->rates[i]); goto ldv_56809; } else { } *(br + (unsigned long )rate) = rate; ldv_56809: i = i + 1U; ldv_56811: ; if (rateset->count > i) { goto ldv_56810; } else { } i = 0U; goto ldv_56815; ldv_56814: rate = (wlc->band)->hw_rateset.rates[i]; if ((unsigned int )*(br + (unsigned long )rate) != 0U) { tmp = is_ofdm_rate((u32 )rate); if ((int )tmp) { ofdm_basic = rate; } else { cck_basic = rate; } goto ldv_56813; } else { } tmp___0 = is_ofdm_rate((u32 )rate); *(br + (unsigned long )rate) = (int )tmp___0 ? ofdm_basic : cck_basic; if ((unsigned int )*(br + (unsigned long )rate) != 0U) { goto ldv_56813; } else { } tmp___1 = is_ofdm_rate((u32 )rate); if ((int )tmp___1) { if ((unsigned int )rate > 47U) { mandatory = 48U; } else if ((unsigned int )rate > 23U) { mandatory = 24U; } else { mandatory = 12U; } } else { mandatory = rate; } *(br + (unsigned long )rate) = mandatory; ldv_56813: i = i + 1U; ldv_56815: ; if ((wlc->band)->hw_rateset.count > i) { goto ldv_56814; } else { } return; } } static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc , u16 chanspec ) { struct brcms_c_rateset default_rateset ; uint parkband ; uint i ; uint band_order[2U] ; int tmp ; uint j ; { if ((int )wlc->bandlocked || (wlc->pub)->_nbands == 1U) { parkband = (wlc->band)->bandunit; band_order[1] = parkband; band_order[0] = band_order[1]; } else { tmp = chspec_bandunit((int )chanspec); parkband = (uint )tmp; band_order[0] = parkband ^ 1U; band_order[1] = parkband; } i = 0U; goto ldv_56827; ldv_56826: j = band_order[i]; wlc->band = wlc->bandstate[j]; brcms_default_rateset(wlc, & default_rateset); brcms_c_rateset_filter(& default_rateset, & (wlc->band)->hw_rateset, 0, 0, 127U, ((int )(wlc->pub)->_n_enab & 3) != 0); brcms_c_rate_lookup_init(wlc, & default_rateset); i = i + 1U; ldv_56827: ; if ((wlc->pub)->_nbands > i) { goto ldv_56826; } else { } brcms_c_set_phy_chanspec(wlc, (int )chanspec); return; } } void brcms_c_mac_promisc(struct brcms_c_info *wlc , uint filter_flags ) { u32 promisc_bits ; { promisc_bits = 0U; wlc->filter_flags = filter_flags; if ((filter_flags & 64U) != 0U) { promisc_bits = promisc_bits | 16777216U; } else { } if ((filter_flags & 16U) != 0U) { promisc_bits = promisc_bits | 1048576U; } else { } if ((filter_flags & 4U) != 0U) { promisc_bits = promisc_bits | 8388608U; } else { } if ((filter_flags & 160U) != 0U) { promisc_bits = promisc_bits | 4194304U; } else { } brcms_b_mctrl(wlc->hw, 30408704U, promisc_bits); return; } } static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc ) { u16 tmp ; { tmp = wlc_phy_chanspec_get((wlc->band)->pi); if ((int )wlc->home_chanspec == (int )tmp) { if ((int )(wlc->pub)->associated) { if (((unsigned int )(wlc->band)->phytype == 4U || (unsigned int )(wlc->band)->phytype == 8U) || (unsigned int )(wlc->band)->phytype == 6U) { brcms_b_write_shm(wlc->hw, 28U, 0); } else { } } else { } } else { } return; } } static void brcms_c_write_rate_shm(struct brcms_c_info *wlc , u8 rate , u8 basic_rate ) { u8 phy_rate ; u8 index ; u8 basic_phy_rate ; u8 basic_index ; u16 dir_table ; u16 basic_table ; u16 basic_ptr ; bool tmp ; bool tmp___0 ; { tmp = is_ofdm_rate((u32 )basic_rate); dir_table = (int )tmp ? 448U : 512U; tmp___0 = is_ofdm_rate((u32 )rate); basic_table = (int )tmp___0 ? 480U : 544U; phy_rate = (unsigned int )((u8 )rate_info[(int )rate]) & 127U; basic_phy_rate = (unsigned int )((u8 )rate_info[(int )basic_rate]) & 127U; index = (unsigned int )phy_rate & 15U; basic_index = (unsigned int )basic_phy_rate & 15U; basic_ptr = brcms_b_read_shm(wlc->hw, (uint )((int )dir_table + (int )basic_index * 2)); brcms_b_write_shm(wlc->hw, (uint )((int )basic_table + (int )index * 2), (int )basic_ptr); return; } } static struct brcms_c_rateset const *brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc ) { struct brcms_c_rateset const *rs_dflt ; { if (((unsigned int )(wlc->band)->phytype == 4U || (unsigned int )(wlc->band)->phytype == 8U) || (unsigned int )(wlc->band)->phytype == 6U) { if ((wlc->band)->bandtype == 1) { rs_dflt = & ofdm_mimo_rates; } else { rs_dflt = & cck_ofdm_mimo_rates; } } else if ((unsigned int )(wlc->band)->gmode != 0U) { rs_dflt = & cck_ofdm_rates; } else { rs_dflt = & cck_rates; } return (rs_dflt); } } static void brcms_c_set_ratetable(struct brcms_c_info *wlc ) { struct brcms_c_rateset const *rs_dflt ; struct brcms_c_rateset rs ; u8 rate ; u8 basic_rate ; uint i ; { rs_dflt = brcms_c_rateset_get_hwrs(wlc); brcms_c_rateset_copy(rs_dflt, & rs); brcms_c_rateset_mcs_upd(& rs, (int )(wlc->stf)->txstreams); i = 0U; goto ldv_56862; ldv_56861: rate = (unsigned int )rs.rates[i] & 127U; basic_rate = brcms_basic_rate(wlc, (u32 )rate); if ((unsigned int )basic_rate == 0U) { basic_rate = (unsigned int )rs.rates[0] & 127U; } else { } brcms_c_write_rate_shm(wlc, (int )rate, (int )basic_rate); i = i + 1U; ldv_56862: ; if (rs.count > i) { goto ldv_56861; } else { } return; } } static void brcms_c_bsinit(struct brcms_c_info *wlc ) { { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 1U, "brcms_c_bsinit", "wl%d: bandunit %d\n", (wlc->pub)->unit, (wlc->band)->bandunit); brcms_c_set_ratetable(wlc); brcms_c_ucode_mac_upd(wlc); brcms_c_antsel_init(wlc->asi); return; } } static int brcms_c_duty_cycle_set(struct brcms_c_info *wlc , int duty_cycle , bool isOFDM , bool writeToShm ) { int idle_busy_ratio_x_16 ; uint offset ; { idle_busy_ratio_x_16 = 0; offset = (int )isOFDM ? 180U : 164U; if (duty_cycle > 100 || duty_cycle < 0) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: duty cycle value off limit\n", (wlc->pub)->unit); return (-22); } else { } if (duty_cycle != 0) { idle_busy_ratio_x_16 = ((100 - duty_cycle) * 16) / duty_cycle; } else { } if ((int )writeToShm) { brcms_b_write_shm(wlc->hw, offset, (int )((unsigned short )idle_busy_ratio_x_16)); } else { } if ((int )isOFDM) { wlc->tx_duty_cycle_ofdm = (unsigned short )duty_cycle; } else { wlc->tx_duty_cycle_cck = (unsigned short )duty_cycle; } return (0); } } static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc ) { u32 v1 ; u32 v2 ; bool hps ; bool awake_before ; { hps = brcms_c_ps_allowed(wlc); __brcms_dbg(& ((wlc->hw)->d11core)->dev, 2U, "brcms_c_set_ps_ctrl", "wl%d: hps %d\n", (wlc->pub)->unit, (int )hps); v1 = bcma_read32((wlc->hw)->d11core, 288); v2 = 67108864U; if ((int )hps) { v2 = v2 | 33554432U; } else { } brcms_b_mctrl(wlc->hw, 100663296U, v2); awake_before = (bool )((v1 & 67108864U) != 0U || (v1 & 33554432U) == 0U); if (! awake_before) { brcms_b_wait_for_wake(wlc->hw); } else { } return; } } static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg ) { int err ; struct brcms_c_info *wlc ; { err = 0; wlc = bsscfg->wlc; brcms_c_set_addrmatch(wlc, 0, (u8 const *)(& (wlc->pub)->cur_etheraddr)); brcms_c_ampdu_macaddr_upd(wlc); return (err); } } static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg ) { { brcms_c_set_addrmatch(bsscfg->wlc, 3, (u8 const *)(& bsscfg->BSSID)); return; } } void brcms_c_set_ssid(struct brcms_c_info *wlc , u8 *ssid , size_t ssid_len ) { u8 len ; u8 __min1 ; u8 __min2 ; { __min1 = 32U; __min2 = (u8 )ssid_len; len = (u8 )((int )__min1 < (int )__min2 ? __min1 : __min2); memset((void *)(& (wlc->bsscfg)->SSID), 0, 32UL); memcpy((void *)(& (wlc->bsscfg)->SSID), (void const *)ssid, (size_t )len); (wlc->bsscfg)->SSID_len = len; return; } } static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw , bool shortslot ) { { wlc_hw->shortslot = shortslot; if ((wlc_hw->band)->bandtype == 2 && (int )wlc_hw->up) { brcms_c_suspend_mac_and_wait(wlc_hw->wlc); brcms_b_update_slot_timing(wlc_hw, (int )shortslot); brcms_c_enable_mac(wlc_hw->wlc); } else { } return; } } static void brcms_c_switch_shortslot(struct brcms_c_info *wlc , bool shortslot ) { { if ((int )wlc->shortslot_override != -1) { shortslot = (int )wlc->shortslot_override == 1; } else { } if ((int )wlc->shortslot == (int )shortslot) { return; } else { } wlc->shortslot = shortslot; brcms_b_set_shortslot(wlc->hw, (int )shortslot); return; } } static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc , u16 chanspec ) { { if ((int )wlc->home_chanspec != (int )chanspec) { wlc->home_chanspec = chanspec; if ((int )(wlc->pub)->associated) { ((wlc->bsscfg)->current_bss)->chanspec = chanspec; } else { } } else { } return; } } void brcms_b_set_chanspec(struct brcms_hardware *wlc_hw , u16 chanspec , bool mute_tx , struct txpwr_limits *txpwr ) { uint bandunit ; int tmp ; { __brcms_dbg(& (wlc_hw->d11core)->dev, 2U, "brcms_b_set_chanspec", "wl%d: 0x%x\n", wlc_hw->unit, (int )chanspec); wlc_hw->chanspec = chanspec; if (wlc_hw->_nbands > 1U) { tmp = chspec_bandunit((int )chanspec); bandunit = (uint )tmp; if ((wlc_hw->band)->bandunit != bandunit) { if ((int )wlc_hw->up) { wlc_phy_chanspec_radio_set((wlc_hw->bandstate[bandunit])->pi, (int )chanspec); brcms_b_setband(wlc_hw, bandunit, (int )chanspec); } else { brcms_c_setxband(wlc_hw, bandunit); } } else { } } else { } wlc_phy_initcal_enable((wlc_hw->band)->pi, (int )((bool )(! ((int )mute_tx != 0)))); if (! wlc_hw->up) { if ((int )wlc_hw->clk) { wlc_phy_txpower_limit_set((wlc_hw->band)->pi, txpwr, (int )chanspec); } else { } wlc_phy_chanspec_radio_set((wlc_hw->band)->pi, (int )chanspec); } else { wlc_phy_chanspec_set((wlc_hw->band)->pi, (int )chanspec); wlc_phy_txpower_limit_set((wlc_hw->band)->pi, txpwr, (int )chanspec); brcms_b_mute(wlc_hw, (int )mute_tx); } return; } } static void brcms_c_setband(struct brcms_c_info *wlc , uint bandunit ) { { wlc->band = wlc->bandstate[bandunit]; if (! (wlc->pub)->up) { return; } else { } brcms_c_set_ps_ctrl(wlc); brcms_c_bsinit(wlc); return; } } static void brcms_c_set_chanspec(struct brcms_c_info *wlc , u16 chanspec ) { uint bandunit ; bool switchband ; u16 old_chanspec ; bool tmp ; int tmp___0 ; int tmp___1 ; int tmp___2 ; int tmp___3 ; int tmp___4 ; int tmp___5 ; { switchband = 0; old_chanspec = wlc->chanspec; tmp = brcms_c_valid_chanspec_db(wlc->cmi, (int )chanspec); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s: Bad channel %d\n", (wlc->pub)->unit, "brcms_c_set_chanspec", (int )((unsigned char )chanspec)); return; } else { } if ((wlc->pub)->_nbands > 1U) { tmp___1 = chspec_bandunit((int )chanspec); bandunit = (uint )tmp___1; if ((wlc->band)->bandunit != bandunit || (int )wlc->bandinit_pending) { switchband = 1; if ((int )wlc->bandlocked) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s: chspec %d band is locked!\n", (wlc->pub)->unit, "brcms_c_set_chanspec", (int )((unsigned char )chanspec)); return; } else { } brcms_c_setband(wlc, bandunit); } else { } } else { } brcms_c_set_phy_chanspec(wlc, (int )chanspec); tmp___4 = brcms_chspec_bw((int )old_chanspec); tmp___5 = brcms_chspec_bw((int )chanspec); if (tmp___4 != tmp___5) { brcms_c_antsel_init(wlc->asi); if ((int )(wlc->band)->mimo_cap_40) { tmp___2 = brcms_chspec_bw((int )chanspec); tmp___3 = (int )((u8 )tmp___2); } else { tmp___3 = 0; } brcms_c_rateset_bw_mcs_filter(& (wlc->band)->hw_rateset, tmp___3); } else { } brcms_c_ucode_mac_upd(wlc); return; } } void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc , u32 bcn_rspec ) { u16 phyctl ; u16 phytxant ; u16 mask ; { phytxant = (wlc->stf)->phytxant; mask = 960U; if (((unsigned int )(wlc->band)->phytype == 4U || (unsigned int )(wlc->band)->phytype == 8U) || (unsigned int )(wlc->band)->phytype == 6U) { phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec); } else { } phyctl = brcms_b_read_shm(wlc->hw, 84U); phyctl = (u16 )((~ ((int )((short )mask)) & (int )((short )phyctl)) | (int )((short )phytxant)); brcms_b_write_shm(wlc->hw, 84U, (int )phyctl); return; } } void brcms_c_protection_upd(struct brcms_c_info *wlc , uint idx , int val ) { { if ((int )brcm_msg_level & 1) { dev_err((struct device const *)(& (wlc->wiphy)->dev), "%s: idx %d, val %d\n", "brcms_c_protection_upd", idx, val); } else { } switch (idx) { case 1U: (wlc->protection)->_g = val != 0; goto ldv_56947; case 2U: (wlc->protection)->g_override = (signed char )val; goto ldv_56947; case 3U: (wlc->protection)->gmode_user = (unsigned char )val; goto ldv_56947; case 4U: (wlc->protection)->overlap = (signed char )val; goto ldv_56947; case 10U: (wlc->protection)->nmode_user = (signed char )val; goto ldv_56947; case 11U: (wlc->protection)->n_cfg = (signed char )val; goto ldv_56947; case 12U: (wlc->protection)->n_cfg_override = (signed char )val; goto ldv_56947; case 13U: (wlc->protection)->nongf = val != 0; goto ldv_56947; case 14U: (wlc->protection)->nongf_override = (signed char )val; goto ldv_56947; case 15U: (wlc->protection)->n_pam_override = (signed char )val; goto ldv_56947; case 16U: (wlc->protection)->n_obss = val != 0; goto ldv_56947; default: ; goto ldv_56947; } ldv_56947: ; return; } } static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc , int val ) { { if ((int )(wlc->pub)->up) { brcms_c_update_beacon(wlc); brcms_c_update_probe_resp(wlc, 1); } else { } return; } } static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc , s8 val ) { { (wlc->stf)->ldpc = val; if ((int )(wlc->pub)->up) { brcms_c_update_beacon(wlc); brcms_c_update_probe_resp(wlc, 1); wlc_phy_ldpc_override_set((wlc->band)->pi, (int )val != 0); } else { } return; } } void brcms_c_wme_setparams(struct brcms_c_info *wlc , u16 aci , struct ieee80211_tx_queue_params const *params , bool suspend ) { int i ; struct shm_acparams acp_shm ; u16 *shm_entry ; u32 tmp ; u16 *tmp___0 ; { if (! wlc->clk) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s : no-clock\n", (wlc->pub)->unit, "brcms_c_wme_setparams"); return; } else { } memset((void *)(& acp_shm), 0, 32UL); acp_shm.txop = params->txop; acp_shm.txop = (int )acp_shm.txop << 5U; wlc->edcf_txop[(int )aci & 3] = acp_shm.txop; acp_shm.aifs = (unsigned int )((u16 )params->aifs) & 15U; if (((unsigned int )aci == 1U && (unsigned int )acp_shm.txop == 0U) && (unsigned int )acp_shm.aifs <= 14U) { acp_shm.aifs = (u16 )((int )acp_shm.aifs + 1); } else { } if ((unsigned int )acp_shm.aifs == 0U || (unsigned int )acp_shm.aifs > 15U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: edcf_setparams: bad aifs %d\n", (wlc->pub)->unit, (int )acp_shm.aifs); } else { acp_shm.cwmin = params->cw_min; acp_shm.cwmax = params->cw_max; acp_shm.cwcur = acp_shm.cwmin; tmp = bcma_read16((wlc->hw)->d11core, 1626); acp_shm.bslots = (int )((u16 )tmp) & (int )acp_shm.cwcur; acp_shm.reggap = (int )acp_shm.bslots + (int )acp_shm.aifs; acp_shm.status = brcms_b_read_shm(wlc->hw, (uint )(((int )wme_ac2fifo[(int )aci] + 18) * 32 + 14)); acp_shm.status = (u16 )((unsigned int )acp_shm.status | 256U); shm_entry = (u16 *)(& acp_shm); i = 0; goto ldv_56978; ldv_56977: tmp___0 = shm_entry; shm_entry = shm_entry + 1; brcms_b_write_shm(wlc->hw, (uint )(((int )wme_ac2fifo[(int )aci] + 18) * 32 + i), (int )*tmp___0); i = i + 2; ldv_56978: ; if (i <= 31) { goto ldv_56977; } else { } } if ((int )suspend) { brcms_c_suspend_mac_and_wait(wlc); } else { } brcms_c_update_beacon(wlc); brcms_c_update_probe_resp(wlc, 0); if ((int )suspend) { brcms_c_enable_mac(wlc); } else { } return; } } static void brcms_c_edcf_setparams(struct brcms_c_info *wlc , bool suspend ) { u16 aci ; int i_ac ; struct ieee80211_tx_queue_params txq_pars ; struct edcf_acparam default_edcf_acparams[4U] ; struct edcf_acparam const *edcf_acp ; { default_edcf_acparams[0].ACI = 3U; default_edcf_acparams[0].ECW = 164U; default_edcf_acparams[0].TXOP = 0U; default_edcf_acparams[1].ACI = 39U; default_edcf_acparams[1].ECW = 164U; default_edcf_acparams[1].TXOP = 0U; default_edcf_acparams[2].ACI = 66U; default_edcf_acparams[2].ECW = 67U; default_edcf_acparams[2].TXOP = 94U; default_edcf_acparams[3].ACI = 98U; default_edcf_acparams[3].ECW = 50U; default_edcf_acparams[3].TXOP = 47U; edcf_acp = (struct edcf_acparam const *)(& default_edcf_acparams); i_ac = 0; goto ldv_56990; ldv_56989: aci = (u16 )(((int )edcf_acp->ACI & 96) >> 5); txq_pars.txop = edcf_acp->TXOP; txq_pars.aifs = edcf_acp->ACI; txq_pars.cw_min = (unsigned int )((u16 )(1 << ((int )edcf_acp->ECW & 15))) + 65535U; txq_pars.cw_max = (unsigned int )((u16 )(1 << (int )((int const )edcf_acp->ECW >> 4))) + 65535U; brcms_c_wme_setparams(wlc, (int )aci, (struct ieee80211_tx_queue_params const *)(& txq_pars), (int )suspend); i_ac = i_ac + 1; edcf_acp = edcf_acp + 1; ldv_56990: ; if (i_ac <= 3) { goto ldv_56989; } else { } if ((int )suspend) { brcms_c_suspend_mac_and_wait(wlc); brcms_c_enable_mac(wlc); } else { } return; } } static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc ) { { if ((int )wlc->radio_monitor) { return; } else { } wlc->radio_monitor = 1; brcms_b_pllreq(wlc->hw, 1, 2U); brcms_add_timer(wlc->radio_timer, 800U, 1); return; } } static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc ) { bool tmp ; { if (! wlc->radio_monitor) { return (1); } else { } wlc->radio_monitor = 0; brcms_b_pllreq(wlc->hw, 0, 2U); tmp = brcms_del_timer(wlc->radio_timer); return (tmp); } } static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc ) { bool tmp ; { if ((int )(wlc->pub)->hw_off) { return; } else { } tmp = brcms_b_radio_read_hwdisabled(wlc->hw); if ((int )tmp) { (wlc->pub)->radio_disabled = (wlc->pub)->radio_disabled | 2U; } else { (wlc->pub)->radio_disabled = (wlc->pub)->radio_disabled & 4294967293U; } return; } } bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc ) { { brcms_c_radio_hwdisable_upd(wlc); return (((wlc->pub)->radio_disabled & 2U) != 0U); } } static void brcms_c_radio_timer(void *arg ) { struct brcms_c_info *wlc ; bool tmp ; { wlc = (struct brcms_c_info *)arg; tmp = brcms_deviceremoved(wlc); if ((int )tmp) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s: dead chip\n", (wlc->pub)->unit, "brcms_c_radio_timer"); brcms_down(wlc->wl); return; } else { } brcms_c_radio_hwdisable_upd(wlc); return; } } static void brcms_b_watchdog(struct brcms_c_info *wlc ) { struct brcms_hardware *wlc_hw ; { wlc_hw = wlc->hw; if (! wlc_hw->up) { return; } else { } wlc_hw->now = wlc_hw->now + 1U; brcms_b_fifoerrors(wlc_hw); dma_rxfill((wlc->hw)->di[0]); wlc_phy_watchdog((wlc_hw->band)->pi); return; } } static void brcms_c_watchdog(struct brcms_c_info *wlc ) { bool tmp ; { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 1U, "brcms_c_watchdog", "wl%d\n", (wlc->pub)->unit); if (! (wlc->pub)->up) { return; } else { } tmp = brcms_deviceremoved(wlc); if ((int )tmp) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s: dead chip\n", (wlc->pub)->unit, "brcms_c_watchdog"); brcms_down(wlc->wl); return; } else { } (wlc->pub)->now = (wlc->pub)->now + 1U; brcms_c_radio_hwdisable_upd(wlc); if ((wlc->pub)->radio_disabled != 0U) { return; } else { } brcms_b_watchdog(wlc); if ((wlc->pub)->now % 30U == 0U) { brcms_c_statsupd(wlc); } else { } if ((unsigned int )(wlc->band)->phytype == 4U && (wlc->pub)->now - wlc->tempsense_lasttime > 9U) { wlc->tempsense_lasttime = (wlc->pub)->now; brcms_c_tempsense_upd(wlc); } else { } return; } } static void brcms_c_watchdog_by_timer(void *arg ) { struct brcms_c_info *wlc ; { wlc = (struct brcms_c_info *)arg; brcms_c_watchdog(wlc); return; } } static bool brcms_c_timers_init(struct brcms_c_info *wlc , int unit ) { { wlc->wdtimer = brcms_init_timer(wlc->wl, & brcms_c_watchdog_by_timer, (void *)wlc, "watchdog"); if ((unsigned long )wlc->wdtimer == (unsigned long )((struct brcms_timer *)0)) { dev_err((struct device const *)(& (wlc->wiphy)->dev), "wl%d: wl_init_timer for wdtimer failed\n", unit); goto fail; } else { } wlc->radio_timer = brcms_init_timer(wlc->wl, & brcms_c_radio_timer, (void *)wlc, "radio"); if ((unsigned long )wlc->radio_timer == (unsigned long )((struct brcms_timer *)0)) { dev_err((struct device const *)(& (wlc->wiphy)->dev), "wl%d: wl_init_timer for radio_timer failed\n", unit); goto fail; } else { } return (1); fail: ; return (0); } } static void brcms_c_info_init(struct brcms_c_info *wlc , int unit ) { int i ; { wlc->chanspec = ch20mhz_chspec(1); wlc->shortslot = 0; wlc->shortslot_override = -1; brcms_c_protection_upd(wlc, 2U, -1); brcms_c_protection_upd(wlc, 1U, 0); brcms_c_protection_upd(wlc, 12U, -1); brcms_c_protection_upd(wlc, 11U, 0); brcms_c_protection_upd(wlc, 14U, -1); brcms_c_protection_upd(wlc, 13U, 0); brcms_c_protection_upd(wlc, 15U, -1); brcms_c_protection_upd(wlc, 4U, 2); wlc->include_legacy_erp = 1; (wlc->stf)->ant_rx_ovr = 3U; (wlc->stf)->txant = 3; wlc->prb_resp_timeout = 0U; wlc->usr_fragthresh = 2346U; i = 0; goto ldv_57032; ldv_57031: wlc->fragthresh[i] = 2346U; i = i + 1; ldv_57032: ; if (i <= 5) { goto ldv_57031; } else { } wlc->RTSThresh = 2347U; wlc->SFBL = 3U; wlc->LFBL = 2U; wlc->SRL = 7U; wlc->LRL = 4U; (wlc->pub)->_ampdu = 1; return; } } static uint brcms_c_attach_module(struct brcms_c_info *wlc ) { uint err ; uint unit ; int tmp ; { err = 0U; unit = (wlc->pub)->unit; wlc->asi = brcms_c_antsel_attach(wlc); if ((unsigned long )wlc->asi == (unsigned long )((struct antsel_info *)0)) { dev_err((struct device const *)(& (wlc->wiphy)->dev), "wl%d: attach: antsel_attach failed\n", unit); err = 44U; goto fail; } else { } wlc->ampdu = brcms_c_ampdu_attach(wlc); if ((unsigned long )wlc->ampdu == (unsigned long )((struct ampdu_info *)0)) { dev_err((struct device const *)(& (wlc->wiphy)->dev), "wl%d: attach: ampdu_attach failed\n", unit); err = 50U; goto fail; } else { } tmp = brcms_c_stf_attach(wlc); if (tmp != 0) { dev_err((struct device const *)(& (wlc->wiphy)->dev), "wl%d: attach: stf_attach failed\n", unit); err = 68U; goto fail; } else { } fail: ; return (err); } } struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc ) { { return (wlc->pub); } } static int brcms_b_attach(struct brcms_c_info *wlc , struct bcma_device *core , uint unit , bool piomode ) { struct brcms_hardware *wlc_hw ; uint err ; uint j ; bool wme ; struct shared_phy_params sha_params ; struct wiphy *wiphy ; struct pci_dev *pcidev ; struct ssb_sprom *sprom ; bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; bool tmp___3 ; int tmp___4 ; uint tmp___5 ; bool tmp___6 ; int tmp___7 ; uint tmp___8 ; int __ret_warn_on ; long tmp___9 ; int __ret_warn_on___0 ; long tmp___10 ; bool tmp___11 ; int tmp___12 ; bool tmp___13 ; bool tmp___14 ; uint tmp___15 ; { err = 0U; wme = 0; wiphy = wlc->wiphy; pcidev = (core->bus)->__annonCompField98.host_pci; sprom = & (core->bus)->sprom; if ((unsigned int )(core->bus)->hosttype == 0U) { __brcms_dbg(& core->dev, 1U, "brcms_b_attach", "wl%d: vendor 0x%x device 0x%x\n", unit, (int )pcidev->vendor, (int )pcidev->device); } else { __brcms_dbg(& core->dev, 1U, "brcms_b_attach", "wl%d: vendor 0x%x device 0x%x\n", unit, (int )(core->bus)->boardinfo.vendor, (int )(core->bus)->boardinfo.type); } wme = 1; wlc_hw = wlc->hw; wlc_hw->wlc = wlc; wlc_hw->unit = unit; wlc_hw->band = wlc_hw->bandstate[0]; wlc_hw->_piomode = piomode; brcms_b_info_init(wlc_hw); wlc_hw->sih = ai_attach(core->bus); if ((unsigned long )wlc_hw->sih == (unsigned long )((struct si_pub *)0)) { dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: si_attach failed\n", unit); err = 11U; goto fail; } else { } tmp = brcms_c_chipmatch(core); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: Unsupported device\n", unit); err = 12U; goto fail; } else { } if ((unsigned int )(core->bus)->hosttype == 0U) { wlc_hw->vendorid = pcidev->vendor; wlc_hw->deviceid = pcidev->device; } else { wlc_hw->vendorid = (core->bus)->boardinfo.vendor; wlc_hw->deviceid = (core->bus)->boardinfo.type; } wlc_hw->d11core = core; wlc_hw->corerev = (uint )core->id.rev; tmp___1 = brcms_c_isgoodchip(wlc_hw); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { err = 13U; goto fail; } else { } ai_clkctl_init(wlc_hw->sih); brcms_b_clkctl_clk(wlc_hw, 0); brcms_b_corereset(wlc_hw, 4294967295U); tmp___3 = brcms_b_validate_chip_access(wlc_hw); if (tmp___3) { tmp___4 = 0; } else { tmp___4 = 1; } if (tmp___4) { dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: validate_chip_access failed\n", unit); err = 14U; goto fail; } else { } j = (uint )sprom->board_rev; if (j == 255U) { j = 1U; } else { } wlc_hw->boardrev = (unsigned short )j; tmp___6 = brcms_c_validboardtype(wlc_hw); if (tmp___6) { tmp___7 = 0; } else { tmp___7 = 1; } if (tmp___7) { tmp___5 = ai_get_boardtype(wlc_hw->sih); dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: Unsupported Broadcom board type (0x%x) or revision level (0x%x)\n", unit, tmp___5, (int )wlc_hw->boardrev); err = 15U; goto fail; } else { } wlc_hw->sromrev = sprom->revision; wlc_hw->boardflags = (u32 )((int )sprom->boardflags_lo + ((int )sprom->boardflags_hi << 16)); wlc_hw->boardflags2 = (u32 )((int )sprom->boardflags2_lo + ((int )sprom->boardflags2_hi << 16)); if ((wlc_hw->boardflags & 32U) != 0U) { brcms_b_pllreq(wlc_hw, 1, 1U); } else { } if (((unsigned int )wlc_hw->deviceid == 17235U || (unsigned int )wlc_hw->deviceid == 1398U) || (unsigned int )wlc_hw->deviceid == 43224U) { wlc_hw->_nbands = 2U; } else { wlc_hw->_nbands = 1U; } tmp___8 = ai_get_chip_id(wlc_hw->sih); if (tmp___8 == 43225U) { wlc_hw->_nbands = 1U; } else { } wlc->vendorid = wlc_hw->vendorid; wlc->deviceid = wlc_hw->deviceid; (wlc->pub)->sih = wlc_hw->sih; (wlc->pub)->corerev = wlc_hw->corerev; (wlc->pub)->sromrev = wlc_hw->sromrev; (wlc->pub)->boardrev = wlc_hw->boardrev; (wlc->pub)->boardflags = wlc_hw->boardflags; (wlc->pub)->boardflags2 = wlc_hw->boardflags2; (wlc->pub)->_nbands = wlc_hw->_nbands; wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc); if ((unsigned long )wlc_hw->physhim == (unsigned long )((struct phy_shim_info *)0)) { dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: wlc_phy_shim_attach failed\n", unit); err = 25U; goto fail; } else { } sha_params.sih = wlc_hw->sih; sha_params.physhim = wlc_hw->physhim; sha_params.unit = unit; sha_params.corerev = wlc_hw->corerev; sha_params.vid = wlc_hw->vendorid; sha_params.did = wlc_hw->deviceid; sha_params.chip = ai_get_chip_id(wlc_hw->sih); sha_params.chiprev = ai_get_chiprev(wlc_hw->sih); sha_params.chippkg = ai_get_chippkg(wlc_hw->sih); sha_params.sromrev = (uint )wlc_hw->sromrev; sha_params.boardtype = ai_get_boardtype(wlc_hw->sih); sha_params.boardrev = (uint )wlc_hw->boardrev; sha_params.boardflags = wlc_hw->boardflags; sha_params.boardflags2 = wlc_hw->boardflags2; wlc_hw->phy_sh = wlc_phy_shared_attach(& sha_params); if ((unsigned long )wlc_hw->phy_sh == (unsigned long )((struct shared_phy *)0)) { err = 16U; goto fail; } else { } j = 0U; goto ldv_57068; ldv_57067: brcms_c_setxband(wlc_hw, j); (wlc_hw->band)->bandunit = j; (wlc_hw->band)->bandtype = j != 0U ? 1 : 2; (wlc->band)->bandunit = j; (wlc->band)->bandtype = j != 0U ? 1 : 2; (wlc->core)->coreidx = (uint )core->core_index; wlc_hw->machwcap = bcma_read32(core, 348); wlc_hw->machwcap_backup = wlc_hw->machwcap; __ret_warn_on = wlc_hw->corerev - 17U > 12U; tmp___9 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___9 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 4590); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); wlc_hw->xmtfifo_sz = (u16 const *)(& xmtfifo_sz) + (unsigned long )(wlc_hw->corerev - 17U); __ret_warn_on___0 = (unsigned int )((unsigned short )*(wlc_hw->xmtfifo_sz)) == 0U; tmp___10 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___10 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 4593); } else { } ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); (wlc_hw->band)->pi = wlc_phy_attach(wlc_hw->phy_sh, core, (wlc_hw->band)->bandtype, wlc->wiphy); if ((unsigned long )(wlc_hw->band)->pi == (unsigned long )((struct brcms_phy_pub *)0)) { dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: wlc_phy_attach failed\n", unit); err = 17U; goto fail; } else { } wlc_phy_machwcap_set((wlc_hw->band)->pi, wlc_hw->machwcap); wlc_phy_get_phyversion((wlc_hw->band)->pi, & (wlc_hw->band)->phytype, & (wlc_hw->band)->phyrev, & (wlc_hw->band)->radioid, & (wlc_hw->band)->radiorev); (wlc_hw->band)->abgphy_encore = wlc_phy_get_encore((wlc_hw->band)->pi); (wlc->band)->abgphy_encore = wlc_phy_get_encore((wlc_hw->band)->pi); (wlc_hw->band)->core_flags = wlc_phy_get_coreflags((wlc_hw->band)->pi); if ((unsigned int )(wlc_hw->band)->phytype == 4U) { if ((511 >> (int )(wlc_hw->band)->phyrev) & 1) { goto good_phy; } else { goto bad_phy; } } else if ((unsigned int )(wlc_hw->band)->phytype == 8U) { if ((7 >> (int )(wlc_hw->band)->phyrev) & 1) { goto good_phy; } else { goto bad_phy; } } else { bad_phy: dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: unsupported phy type/rev (%d/%d)\n", unit, (int )(wlc_hw->band)->phytype, (int )(wlc_hw->band)->phyrev); err = 18U; goto fail; } good_phy: (wlc->band)->pi = (wlc_hw->band)->pi; (wlc->band)->phytype = (wlc_hw->band)->phytype; (wlc->band)->phyrev = (wlc_hw->band)->phyrev; (wlc->band)->radioid = (wlc_hw->band)->radioid; (wlc->band)->radiorev = (wlc_hw->band)->radiorev; __brcms_dbg(& core->dev, 1U, "brcms_b_attach", "wl%d: phy %u/%u radio %x/%u\n", unit, (int )(wlc->band)->phytype, (int )(wlc->band)->phyrev, (int )(wlc->band)->radioid, (int )(wlc->band)->radiorev); (wlc_hw->band)->CWmin = 15U; (wlc_hw->band)->CWmax = 1023U; tmp___11 = brcms_b_attach_dmapio(wlc, j, (int )wme); if (tmp___11) { tmp___12 = 0; } else { tmp___12 = 1; } if (tmp___12) { err = 19U; goto fail; } else { } j = j + 1U; ldv_57068: ; if (wlc_hw->_nbands > j) { goto ldv_57067; } else { } brcms_c_coredisable(wlc_hw); bcma_host_pci_down((wlc_hw->d11core)->bus); brcms_b_xtal(wlc_hw, 0); brcms_c_get_macaddr(wlc_hw, (u8 *)(& wlc_hw->etheraddr)); tmp___13 = is_broadcast_ether_addr((u8 const *)(& wlc_hw->etheraddr)); if ((int )tmp___13) { dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: bad macaddr\n", unit); err = 22U; goto fail; } else { tmp___14 = is_zero_ether_addr((u8 const *)(& wlc_hw->etheraddr)); if ((int )tmp___14) { dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: bad macaddr\n", unit); err = 22U; goto fail; } else { } } tmp___15 = ai_get_boardtype(wlc_hw->sih); __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_b_attach", "deviceid 0x%x nbands %d board 0x%x\n", (int )wlc_hw->deviceid, wlc_hw->_nbands, tmp___15); return ((int )err); fail: dev_err((struct device const *)(& wiphy->dev), "wl%d: brcms_b_attach: failed with err %d\n", unit, err); return ((int )err); } } static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc ) { int aa ; uint unit ; int bandtype ; struct ssb_sprom *sprom ; { sprom = & (((wlc->hw)->d11core)->bus)->sprom; unit = (wlc->pub)->unit; bandtype = (wlc->band)->bandtype; if (bandtype == 1) { aa = (int )sprom->ant_available_a; } else { aa = (int )sprom->ant_available_bg; } if (aa <= 0 || aa > 15) { dev_err((struct device const *)(& (wlc->wiphy)->dev), "wl%d: %s: Invalid antennas available in srom (0x%x), using 3\n", unit, "brcms_c_attach_stf_ant_init", aa); aa = 3; } else { } if (aa == 1) { (wlc->stf)->ant_rx_ovr = 0U; (wlc->stf)->txant = 0; } else if (aa == 2) { (wlc->stf)->ant_rx_ovr = 1U; (wlc->stf)->txant = 1; } else { } if (bandtype == 1) { (wlc->band)->antgain = sprom->antenna_gain.a1; } else { (wlc->band)->antgain = sprom->antenna_gain.a0; } return (1); } } static void brcms_c_bss_default_init(struct brcms_c_info *wlc ) { u16 chanspec ; struct brcms_band *band ; struct brcms_bss_info *bi ; u16 tmp ; int tmp___0 ; int tmp___1 ; { bi = wlc->default_bss; memset((void *)bi, 0, 92UL); bi->beacon_period = 100U; chanspec = ch20mhz_chspec(1); tmp = chanspec; bi->chanspec = tmp; wlc->home_chanspec = tmp; band = wlc->band; if ((wlc->pub)->_nbands > 1U) { tmp___0 = chspec_bandunit((int )chanspec); if (band->bandunit != (uint )tmp___0) { band = wlc->bandstate[(wlc->band)->bandunit == 0U]; } else { } } else { } tmp___1 = brcms_chspec_bw((int )chanspec); brcms_c_rateset_default(& bi->rateset, (struct brcms_c_rateset const *)0, (uint )band->phytype, band->bandtype, 0, 255U, ((int )(wlc->pub)->_n_enab & 3) != 0, (int )((u8 )tmp___1), (int )(wlc->stf)->txstreams); if (((int )(wlc->pub)->_n_enab & 3) != 0) { bi->flags = (u16 )((unsigned int )bi->flags | 32U); } else { } return; } } static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc , u8 bwcap ) { uint i ; struct brcms_band *band ; { i = 0U; goto ldv_57091; ldv_57090: band = wlc->bandstate[i]; if (band->bandtype == 1) { if ((unsigned int )bwcap == 1U || (unsigned int )bwcap == 2U) { band->mimo_cap_40 = 1; } else { band->mimo_cap_40 = 0; } } else if ((unsigned int )bwcap == 1U) { band->mimo_cap_40 = 1; } else { band->mimo_cap_40 = 0; } i = i + 1U; ldv_57091: ; if ((wlc->pub)->_nbands > i) { goto ldv_57090; } else { } return; } } static void brcms_c_timers_deinit(struct brcms_c_info *wlc ) { { if ((unsigned long )wlc->wdtimer != (unsigned long )((struct brcms_timer *)0)) { brcms_free_timer(wlc->wdtimer); wlc->wdtimer = (struct brcms_timer *)0; } else { } if ((unsigned long )wlc->radio_timer != (unsigned long )((struct brcms_timer *)0)) { brcms_free_timer(wlc->radio_timer); wlc->radio_timer = (struct brcms_timer *)0; } else { } return; } } static void brcms_c_detach_module(struct brcms_c_info *wlc ) { { if ((unsigned long )wlc->asi != (unsigned long )((struct antsel_info *)0)) { brcms_c_antsel_detach(wlc->asi); wlc->asi = (struct antsel_info *)0; } else { } if ((unsigned long )wlc->ampdu != (unsigned long )((struct ampdu_info *)0)) { brcms_c_ampdu_detach(wlc->ampdu); wlc->ampdu = (struct ampdu_info *)0; } else { } brcms_c_stf_detach(wlc); return; } } static void brcms_b_detach(struct brcms_c_info *wlc ) { uint i ; struct brcms_hw_band *band ; struct brcms_hardware *wlc_hw ; { wlc_hw = wlc->hw; brcms_b_detach_dmapio(wlc_hw); band = wlc_hw->band; i = 0U; goto ldv_57106; ldv_57105: ; if ((unsigned long )band->pi != (unsigned long )((struct brcms_phy_pub *)0)) { wlc_phy_detach(band->pi); band->pi = (struct brcms_phy_pub *)0; } else { } band = wlc_hw->bandstate[(wlc->band)->bandunit == 0U]; i = i + 1U; ldv_57106: ; if (wlc_hw->_nbands > i) { goto ldv_57105; } else { } kfree((void const *)wlc_hw->phy_sh); wlc_phy_shim_detach(wlc_hw->physhim); if ((unsigned long )wlc_hw->sih != (unsigned long )((struct si_pub *)0)) { ai_detach(wlc_hw->sih); wlc_hw->sih = (struct si_pub *)0; } else { } return; } } uint brcms_c_detach(struct brcms_c_info *wlc ) { uint callbacks ; bool tmp ; int tmp___0 ; { if ((unsigned long )wlc == (unsigned long )((struct brcms_c_info *)0)) { return (0U); } else { } brcms_b_detach(wlc); callbacks = 0U; tmp = brcms_c_radio_monitor_stop(wlc); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { callbacks = callbacks + 1U; } else { } brcms_c_channel_mgr_detach(wlc->cmi); brcms_c_timers_deinit(wlc); brcms_c_detach_module(wlc); brcms_c_detach_mfree(wlc); return (callbacks); } } static void brcms_c_ap_upd(struct brcms_c_info *wlc ) { { wlc->PLCPHdr_override = 0; return; } } static void brcms_b_hw_up(struct brcms_hardware *wlc_hw ) { uint tmp ; { if ((int )((wlc_hw->wlc)->pub)->hw_up) { return; } else { } __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_b_hw_up", "wl%d\n", wlc_hw->unit); brcms_b_xtal(wlc_hw, 1); ai_clkctl_init(wlc_hw->sih); brcms_b_clkctl_clk(wlc_hw, 0); wlc_phy_por_inform((wlc_hw->band)->pi); wlc_hw->ucode_loaded = 0; ((wlc_hw->wlc)->pub)->hw_up = 1; if ((wlc_hw->boardflags & 2048U) != 0U) { tmp = ai_get_chip_id(wlc_hw->sih); if (tmp == 17171U) { if ((unsigned int )wlc_hw->boardrev <= 4687U || (wlc_hw->boardflags & 4194304U) == 0U) { ai_epa_4313war(wlc_hw->sih); } else { } } else { } } else { } return; } } static int brcms_b_up_prep(struct brcms_hardware *wlc_hw ) { bool tmp ; { __brcms_dbg(& (wlc_hw->d11core)->dev, 1U, "brcms_b_up_prep", "wl%d\n", wlc_hw->unit); brcms_b_xtal(wlc_hw, 1); ai_clkctl_init(wlc_hw->sih); brcms_b_clkctl_clk(wlc_hw, 0); bcma_host_pci_irq_ctl((wlc_hw->d11core)->bus, wlc_hw->d11core, 1); tmp = brcms_b_radio_read_hwdisabled(wlc_hw); if ((int )tmp) { bcma_host_pci_down((wlc_hw->d11core)->bus); brcms_b_xtal(wlc_hw, 0); return (-123); } else { } bcma_host_pci_up((wlc_hw->d11core)->bus); brcms_b_corereset(wlc_hw, 4294967295U); return (0); } } static int brcms_b_up_finish(struct brcms_hardware *wlc_hw ) { { wlc_hw->up = 1; wlc_phy_hw_state_upd((wlc_hw->band)->pi, 1); brcms_b_clkctl_clk(wlc_hw, 1); brcms_intrson((wlc_hw->wlc)->wl); return (0); } } static void brcms_c_wme_retries_write(struct brcms_c_info *wlc ) { int ac ; { if (! wlc->clk) { return; } else { } ac = 0; goto ldv_57131; ldv_57130: brcms_b_write_shm(wlc->hw, (uint )((ac + 384) * 2), (int )wlc->wme_retries[ac]); ac = ac + 1; ldv_57131: ; if (ac <= 3) { goto ldv_57130; } else { } return; } } int brcms_c_up(struct brcms_c_info *wlc ) { struct ieee80211_channel *ch ; bool tmp ; uint tmp___0 ; int status ; int tmp___1 ; struct brcms_bss_cfg *bsscfg ; u16 tmp___2 ; { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 1U, "brcms_c_up", "wl%d\n", (wlc->pub)->unit); if ((int )(wlc->pub)->hw_off) { return (-123); } else { tmp = brcms_deviceremoved(wlc); if ((int )tmp) { return (-123); } else { } } if (! (wlc->pub)->hw_up) { brcms_b_hw_up(wlc->hw); (wlc->pub)->hw_up = 1; } else { } if (((wlc->pub)->boardflags & 2048U) != 0U) { tmp___0 = ai_get_chip_id((wlc->hw)->sih); if (tmp___0 == 17171U) { if ((unsigned int )(wlc->pub)->boardrev > 4687U && ((wlc->pub)->boardflags & 4194304U) != 0U) { brcms_b_mhf(wlc->hw, 4, 1, 1, 3); } else { brcms_b_mhf(wlc->hw, 3, 16384, 16384, 3); } } else { } } else { } if ((wlc->pub)->radio_disabled == 0U) { tmp___1 = brcms_b_up_prep(wlc->hw); status = tmp___1; if (status == -123) { if (((wlc->pub)->radio_disabled & 2U) == 0U) { bsscfg = wlc->bsscfg; (wlc->pub)->radio_disabled = (wlc->pub)->radio_disabled | 2U; if ((unsigned int )bsscfg->type == 0U || (unsigned int )bsscfg->type == 2U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: up: rfdisable -> bsscfg_disable()\n", (wlc->pub)->unit); } else { } } else { } } else { } } else { } if ((wlc->pub)->radio_disabled != 0U) { brcms_c_radio_monitor_start(wlc); return (0); } else { } wlc->clk = 1; brcms_c_radio_monitor_stop(wlc); brcms_b_mhf(wlc->hw, 0, 256, 256, 3); brcms_init(wlc->wl); (wlc->pub)->up = 1; if ((int )wlc->bandinit_pending) { ch = ((wlc->pub)->ieee_hw)->conf.chandef.chan; brcms_c_suspend_mac_and_wait(wlc); tmp___2 = ch20mhz_chspec((int )ch->hw_value); brcms_c_set_chanspec(wlc, (int )tmp___2); wlc->bandinit_pending = 0; brcms_c_enable_mac(wlc); } else { } brcms_b_up_finish(wlc->hw); brcms_c_wme_retries_write(wlc); brcms_add_timer(wlc->wdtimer, 1000U, 1); wlc->WDarmed = 1; brcms_c_stf_phy_txant_upd(wlc); brcms_c_ht_update_ldpc(wlc, (int )(wlc->stf)->ldpc); return (0); } } static uint brcms_c_down_del_timer(struct brcms_c_info *wlc ) { uint callbacks ; { callbacks = 0U; return (callbacks); } } static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw ) { bool dev_gone ; uint callbacks ; int tmp ; { callbacks = 0U; if (! wlc_hw->up) { return ((int )callbacks); } else { } dev_gone = brcms_deviceremoved(wlc_hw->wlc); if ((int )dev_gone) { (wlc_hw->wlc)->macintmask = 0U; } else { brcms_intrsoff((wlc_hw->wlc)->wl); brcms_b_clkctl_clk(wlc_hw, 0); } tmp = wlc_phy_down((wlc_hw->band)->pi); callbacks = (uint )tmp + callbacks; return ((int )callbacks); } } static int brcms_b_down_finish(struct brcms_hardware *wlc_hw ) { uint callbacks ; bool dev_gone ; u32 tmp ; uint tmp___0 ; bool tmp___1 ; { callbacks = 0U; if (! wlc_hw->up) { return ((int )callbacks); } else { } wlc_hw->up = 0; wlc_phy_hw_state_upd((wlc_hw->band)->pi, 0); dev_gone = brcms_deviceremoved(wlc_hw->wlc); if ((int )dev_gone) { wlc_hw->sbclk = 0; wlc_hw->clk = 0; wlc_phy_hw_clk_state_upd((wlc_hw->band)->pi, 0); brcms_c_flushqueues(wlc_hw->wlc); } else { tmp___1 = bcma_core_is_enabled(wlc_hw->d11core); if ((int )tmp___1) { tmp = bcma_read32(wlc_hw->d11core, 288); if ((int )tmp & 1) { brcms_c_suspend_mac_and_wait(wlc_hw->wlc); } else { } tmp___0 = brcms_reset((wlc_hw->wlc)->wl); callbacks = tmp___0 + callbacks; brcms_c_coredisable(wlc_hw); } else { } if (! wlc_hw->noreset) { bcma_host_pci_down((wlc_hw->d11core)->bus); brcms_b_xtal(wlc_hw, 0); } else { } } return ((int )callbacks); } } uint brcms_c_down(struct brcms_c_info *wlc ) { uint callbacks ; int i ; bool dev_gone ; int tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; uint tmp___3 ; int tmp___4 ; { callbacks = 0U; dev_gone = 0; __brcms_dbg(& ((wlc->hw)->d11core)->dev, 1U, "brcms_c_down", "wl%d\n", (wlc->pub)->unit); if ((int )wlc->going_down) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s: Driver going down so return\n", (wlc->pub)->unit, "brcms_c_down"); return (0U); } else { } if (! (wlc->pub)->up) { return (callbacks); } else { } wlc->going_down = 1; tmp = brcms_b_bmac_down_prep(wlc->hw); callbacks = (uint )tmp + callbacks; dev_gone = brcms_deviceremoved(wlc); i = 0; goto ldv_57162; ldv_57161: ; if ((unsigned long )(wlc->modulecb + (unsigned long )i)->down_fn != (unsigned long )((int (*)(void * ))0)) { tmp___0 = (*((wlc->modulecb + (unsigned long )i)->down_fn))((void *)(wlc->modulecb + (unsigned long )i)->hdl); callbacks = (uint )tmp___0 + callbacks; } else { } i = i + 1; ldv_57162: ; if (i <= 21) { goto ldv_57161; } else { } if ((int )wlc->WDarmed) { tmp___1 = brcms_del_timer(wlc->wdtimer); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { callbacks = callbacks + 1U; } else { } wlc->WDarmed = 0; } else { } tmp___3 = brcms_c_down_del_timer(wlc); callbacks = tmp___3 + callbacks; (wlc->pub)->up = 0; wlc_phy_mute_upd((wlc->band)->pi, 0, 4294967295U); tmp___4 = brcms_b_down_finish(wlc->hw); callbacks = (uint )tmp___4 + callbacks; wlc->clk = 0; wlc->going_down = 0; return (callbacks); } } int brcms_c_set_gmode(struct brcms_c_info *wlc , u8 gmode , bool config ) { int ret ; uint i ; struct brcms_c_rateset rs ; s8 shortslot ; bool shortslot_restrict ; bool ofdm_basic ; int preamble ; bool preamble_restrict ; struct brcms_band *band ; { ret = 0; shortslot = -1; shortslot_restrict = 0; ofdm_basic = 0; preamble = 1; preamble_restrict = 0; if (((int )(wlc->pub)->_n_enab & 3) != 0 && (unsigned int )gmode == 0U) { return (-524); } else { } if ((wlc->band)->bandtype == 2) { band = wlc->band; } else if ((wlc->pub)->_nbands > 1U && (wlc->bandstate[(wlc->band)->bandunit == 0U])->bandtype == 2) { band = wlc->bandstate[(wlc->band)->bandunit == 0U]; } else { return (-22); } if ((int )config) { brcms_c_protection_upd(wlc, 3U, (int )gmode); } else { } memset((void *)(& rs), 0, 40UL); switch ((int )gmode) { case 0: shortslot = 0; brcms_c_rateset_copy(& gphy_legacy_rates, & rs); goto ldv_57179; case 5: ; goto ldv_57179; case 1: ; goto ldv_57179; case 2: ofdm_basic = 1; preamble = 0; preamble_restrict = 1; goto ldv_57179; case 4: shortslot = 1; shortslot_restrict = 1; ofdm_basic = 1; preamble = 0; preamble_restrict = 1; goto ldv_57179; default: __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s: invalid gmode %d\n", (wlc->pub)->unit, "brcms_c_set_gmode", (int )gmode); return (-524); } ldv_57179: band->gmode = gmode; wlc->shortslot_override = shortslot; if (rs.count == 0U) { brcms_c_rateset_copy(& cck_ofdm_rates, & rs); } else { } if ((int )ofdm_basic) { i = 0U; goto ldv_57187; ldv_57186: ; if (((unsigned int )rs.rates[i] == 12U || (unsigned int )rs.rates[i] == 24U) || (unsigned int )rs.rates[i] == 48U) { rs.rates[i] = (u8 )((unsigned int )rs.rates[i] | 128U); } else { } i = i + 1U; ldv_57187: ; if (rs.count > i) { goto ldv_57186; } else { } } else { } (wlc->default_bss)->rateset.count = rs.count; memcpy((void *)(& (wlc->default_bss)->rateset.rates), (void const *)(& rs.rates), 16UL); return (ret); } } int brcms_c_set_nmode(struct brcms_c_info *wlc ) { uint i ; s32 nmode ; { nmode = -1; if ((unsigned int )(wlc->stf)->txstreams == 3U) { nmode = 3; } else { nmode = 1; } brcms_c_set_gmode(wlc, 1, 1); if (nmode == 3) { (wlc->pub)->_n_enab = 7U; } else { (wlc->pub)->_n_enab = 3U; } (wlc->default_bss)->flags = (u16 )((unsigned int )(wlc->default_bss)->flags | 32U); brcms_c_rateset_mcs_build(& (wlc->default_bss)->rateset, (int )(wlc->stf)->txstreams); i = 0U; goto ldv_57195; ldv_57194: memcpy((void *)(& (wlc->bandstate[i])->hw_rateset.mcs), (void const *)(& (wlc->default_bss)->rateset.mcs), 16UL); i = i + 1U; ldv_57195: ; if ((wlc->pub)->_nbands > i) { goto ldv_57194; } else { } return (0); } } static int brcms_c_set_internal_rateset(struct brcms_c_info *wlc , struct brcms_c_rateset *rs_arg ) { struct brcms_c_rateset rs ; struct brcms_c_rateset new ; uint bandunit ; bool tmp ; bool tmp___0 ; bool tmp___1 ; { memcpy((void *)(& rs), (void const *)rs_arg, 40UL); if (rs.count == 0U || rs.count > 16U) { return (-22); } else { } bandunit = (wlc->band)->bandunit; memcpy((void *)(& new), (void const *)(& rs), 40UL); tmp = brcms_c_rate_hwrs_filter_sort_validate(& new, (struct brcms_c_rateset const *)(& (wlc->bandstate[bandunit])->hw_rateset), 1, (int )(wlc->stf)->txstreams); if ((int )tmp) { goto good; } else { } tmp___1 = brcms_is_mband_unlocked(wlc); if ((int )tmp___1) { bandunit = (wlc->band)->bandunit == 0U; memcpy((void *)(& new), (void const *)(& rs), 40UL); tmp___0 = brcms_c_rate_hwrs_filter_sort_validate(& new, (struct brcms_c_rateset const *)(& (wlc->bandstate[bandunit])->hw_rateset), 1, (int )(wlc->stf)->txstreams); if ((int )tmp___0) { goto good; } else { } } else { } return (-52); good: memcpy((void *)(& (wlc->default_bss)->rateset), (void const *)(& new), 40UL); memcpy((void *)(& (wlc->bandstate[bandunit])->defrateset), (void const *)(& new), 40UL); return (0); } } static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc ) { u8 r ; bool war ; { war = 0; if ((int )(wlc->pub)->associated) { r = ((wlc->bsscfg)->current_bss)->rateset.rates[0]; } else { r = (wlc->default_bss)->rateset.rates[0]; } wlc_phy_ofdm_rateset_war((wlc->band)->pi, (int )war); return; } } int brcms_c_set_channel(struct brcms_c_info *wlc , u16 channel ) { u16 chspec ; u16 tmp ; bool tmp___0 ; int tmp___1 ; int tmp___2 ; bool tmp___3 ; u16 tmp___4 ; { tmp = ch20mhz_chspec((int )channel); chspec = tmp; if ((unsigned int )channel > 224U) { return (-22); } else { } tmp___0 = brcms_c_valid_chanspec_db(wlc->cmi, (int )chspec); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return (-22); } else { } if (! (wlc->pub)->up) { tmp___3 = brcms_is_mband_unlocked(wlc); if ((int )tmp___3) { tmp___2 = chspec_bandunit((int )chspec); if ((wlc->band)->bandunit != (uint )tmp___2) { wlc->bandinit_pending = 1; } else { wlc->bandinit_pending = 0; } } else { } } else { } (wlc->default_bss)->chanspec = chspec; if ((int )(wlc->pub)->up) { tmp___4 = wlc_phy_chanspec_get((wlc->band)->pi); if ((int )tmp___4 != (int )chspec) { brcms_c_set_home_chanspec(wlc, (int )chspec); brcms_c_suspend_mac_and_wait(wlc); brcms_c_set_chanspec(wlc, (int )chspec); brcms_c_enable_mac(wlc); } else { } } else { } return (0); } } int brcms_c_set_rate_limit(struct brcms_c_info *wlc , u16 srl , u16 lrl ) { int ac ; { if ((((unsigned int )srl == 0U || (unsigned int )srl > 255U) || (unsigned int )lrl == 0U) || (unsigned int )lrl > 255U) { return (-22); } else { } wlc->SRL = srl; wlc->LRL = lrl; brcms_b_retrylimit_upd(wlc->hw, (int )wlc->SRL, (int )wlc->LRL); ac = 0; goto ldv_57222; ldv_57221: wlc->wme_retries[ac] = ((unsigned int )wlc->wme_retries[ac] & 65520U) | (unsigned int )wlc->SRL; wlc->wme_retries[ac] = ((unsigned int )wlc->wme_retries[ac] & 61695U) | (unsigned int )((int )wlc->LRL << 8U); ac = ac + 1; ldv_57222: ; if (ac <= 3) { goto ldv_57221; } else { } brcms_c_wme_retries_write(wlc); return (0); } } void brcms_c_get_current_rateset(struct brcms_c_info *wlc , struct brcm_rateset *currs ) { struct brcms_c_rateset *rs ; { if ((int )(wlc->pub)->associated) { rs = & ((wlc->bsscfg)->current_bss)->rateset; } else { rs = & (wlc->default_bss)->rateset; } currs->count = rs->count; memcpy((void *)(& currs->rates), (void const *)(& rs->rates), (size_t )rs->count); return; } } int brcms_c_set_rateset(struct brcms_c_info *wlc , struct brcm_rateset *rs ) { struct brcms_c_rateset internal_rs ; int bcmerror ; struct brcms_bss_info *mcsset_bss ; { if (rs->count > 16U) { return (-105); } else { } memset((void *)(& internal_rs), 0, 40UL); internal_rs.count = rs->count; memcpy((void *)(& internal_rs.rates), (void const *)(& rs->rates), (size_t )internal_rs.count); if (((int )(wlc->pub)->_n_enab & 3) != 0) { if ((int )(wlc->pub)->associated) { mcsset_bss = (wlc->bsscfg)->current_bss; } else { mcsset_bss = wlc->default_bss; } memcpy((void *)(& internal_rs.mcs), (void const *)(& mcsset_bss->rateset.mcs), 16UL); } else { } bcmerror = brcms_c_set_internal_rateset(wlc, & internal_rs); if (bcmerror == 0) { brcms_c_ofdm_rateset_war(wlc); } else { } return (bcmerror); } } static void brcms_c_time_lock(struct brcms_c_info *wlc ) { { bcma_set32((wlc->hw)->d11core, 288, 268435456U); bcma_read32((wlc->hw)->d11core, 288); return; } } static void brcms_c_time_unlock(struct brcms_c_info *wlc ) { { bcma_mask32((wlc->hw)->d11core, 288, 4026531839U); bcma_read32((wlc->hw)->d11core, 288); return; } } int brcms_c_set_beacon_period(struct brcms_c_info *wlc , u16 period ) { u32 bcnint_us ; { if ((unsigned int )period == 0U) { return (-22); } else { } (wlc->default_bss)->beacon_period = period; bcnint_us = (u32 )((int )period << 10); brcms_c_time_lock(wlc); bcma_write32((wlc->hw)->d11core, 392, bcnint_us << 6); bcma_write32((wlc->hw)->d11core, 396, bcnint_us); brcms_c_time_unlock(wlc); return (0); } } u16 brcms_c_get_phy_type(struct brcms_c_info *wlc , int phyidx ) { { return ((wlc->band)->phytype); } } void brcms_c_set_shortslot_override(struct brcms_c_info *wlc , s8 sslot_override ) { { wlc->shortslot_override = sslot_override; if ((wlc->band)->bandtype == 1) { return; } else { } if ((int )(wlc->pub)->up && (int )(wlc->pub)->associated) { } else if ((int )(wlc->pub)->up) { brcms_c_switch_shortslot(wlc, 0); } else if ((int )wlc->shortslot_override == -1) { wlc->shortslot = 0; } else { wlc->shortslot = (int )wlc->shortslot_override == 1; } return; } } int brcms_c_module_register(struct brcms_pub *pub , char const *name , struct brcms_info *hdl , int (*d_fn)(void * ) ) { struct brcms_c_info *wlc ; int i ; { wlc = pub->wlc; i = 0; goto ldv_57265; ldv_57264: ; if ((int )((signed char )(wlc->modulecb + (unsigned long )i)->name[0]) == 0) { strncpy((char *)(& (wlc->modulecb + (unsigned long )i)->name), name, 31UL); (wlc->modulecb + (unsigned long )i)->hdl = hdl; (wlc->modulecb + (unsigned long )i)->down_fn = d_fn; return (0); } else { } i = i + 1; ldv_57265: ; if (i <= 21) { goto ldv_57264; } else { } return (-63); } } int brcms_c_module_unregister(struct brcms_pub *pub , char const *name , struct brcms_info *hdl ) { struct brcms_c_info *wlc ; int i ; int tmp ; { wlc = pub->wlc; if ((unsigned long )wlc == (unsigned long )((struct brcms_c_info *)0)) { return (-61); } else { } i = 0; goto ldv_57275; ldv_57274: tmp = strcmp((char const *)(& (wlc->modulecb + (unsigned long )i)->name), name); if (tmp == 0 && (unsigned long )(wlc->modulecb + (unsigned long )i)->hdl == (unsigned long )hdl) { memset((void *)wlc->modulecb + (unsigned long )i, 0, 48UL); return (0); } else { } i = i + 1; ldv_57275: ; if (i <= 21) { goto ldv_57274; } else { } return (-61); } } static bool brcms_c_chipmatch_pci(struct bcma_device *core ) { struct pci_dev *pcidev ; u16 vendor ; u16 device ; { pcidev = (core->bus)->__annonCompField98.host_pci; vendor = pcidev->vendor; device = pcidev->device; if ((unsigned int )vendor != 5348U) { printk("\vbrcmsmac: unknown vendor id %04x\n", (int )vendor); return (0); } else { } if ((unsigned int )device == 1398U || (unsigned int )device == 43224U) { return (1); } else { } if ((unsigned int )device == 17235U || (unsigned int )device == 17239U) { return (1); } else { } if ((unsigned int )device == 18215U || (unsigned int )device == 17171U) { return (1); } else { } if ((unsigned int )device == 17222U || (unsigned int )device == 17223U) { return (1); } else { } printk("\vbrcmsmac: unknown device id %04x\n", (int )device); return (0); } } static bool brcms_c_chipmatch_soc(struct bcma_device *core ) { struct bcma_chipinfo *chipinfo ; { chipinfo = & (core->bus)->chipinfo; if ((unsigned int )chipinfo->id == 18198U) { return (1); } else { } printk("\vbrcmsmac: unknown chip id %04x\n", (int )chipinfo->id); return (0); } } bool brcms_c_chipmatch(struct bcma_device *core ) { bool tmp ; bool tmp___0 ; { switch ((unsigned int )(core->bus)->hosttype) { case 0U: tmp = brcms_c_chipmatch_pci(core); return (tmp); case 2U: tmp___0 = brcms_c_chipmatch_soc(core); return (tmp___0); default: printk("\vbrcmsmac: unknown host type: %i\n", (unsigned int )(core->bus)->hosttype); return (0); } } } u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw , u8 rate ) { u16 table_ptr ; u8 phy_rate ; u8 index ; bool tmp ; u16 tmp___0 ; { tmp = is_ofdm_rate((u32 )rate); if ((int )tmp) { table_ptr = 448U; } else { table_ptr = 512U; } phy_rate = (unsigned int )((u8 )rate_info[(int )rate]) & 127U; index = (unsigned int )phy_rate & 15U; tmp___0 = brcms_b_read_shm(wlc_hw, (uint )((int )table_ptr + (int )index * 2)); return ((unsigned int )tmp___0 * 2U); } } __inline static u16 bcmc_fid_generate(struct brcms_c_info *wlc , struct brcms_bss_cfg *bsscfg , struct d11txh *txh ) { u16 frameid ; u16 tmp ; { frameid = (unsigned int )txh->TxFrameID & 32792U; tmp = wlc->mc_fid_counter; wlc->mc_fid_counter = (u16 )((int )wlc->mc_fid_counter + 1); frameid = (u16 )((((int )((short )((int )tmp << 5)) & 32736) | 4) | (int )((short )frameid)); return (frameid); } } static uint brcms_c_calc_ack_time(struct brcms_c_info *wlc , u32 rspec , u8 preamble_type ) { uint dur ; u8 tmp ; { dur = 0U; tmp = brcms_basic_rate(wlc, rspec); rspec = (u32 )tmp; dur = brcms_c_calc_frame_time(wlc, rspec, (int )preamble_type, 14U); return (dur); } } static uint brcms_c_calc_cts_time(struct brcms_c_info *wlc , u32 rspec , u8 preamble_type ) { uint tmp ; { tmp = brcms_c_calc_ack_time(wlc, rspec, (int )preamble_type); return (tmp); } } static uint brcms_c_calc_ba_time(struct brcms_c_info *wlc , u32 rspec , u8 preamble_type ) { u8 tmp ; uint tmp___0 ; { tmp = brcms_basic_rate(wlc, rspec); rspec = (u32 )tmp; tmp___0 = brcms_c_calc_frame_time(wlc, rspec, (int )preamble_type, 136U); return (tmp___0); } } static u16 brcms_c_compute_frame_dur(struct brcms_c_info *wlc , u32 rate , u8 preamble_type , uint next_frag_len ) { u16 dur ; u16 sifs ; uint tmp ; uint tmp___0 ; { sifs = get_sifs(wlc->band); dur = sifs; tmp = brcms_c_calc_ack_time(wlc, rate, (int )preamble_type); dur = (int )((u16 )tmp) + (int )dur; if (next_frag_len != 0U) { dur = (unsigned int )dur * 2U; dur = (int )dur + (int )sifs; tmp___0 = brcms_c_calc_frame_time(wlc, rate, (int )preamble_type, next_frag_len); dur = (int )((u16 )tmp___0) + (int )dur; } else { } return (dur); } } static uint brcms_c_calc_frame_len(struct brcms_c_info *wlc , u32 ratespec , u8 preamble_type , uint dur ) { uint nsyms ; uint mac_len ; uint Ndps ; uint kNdps ; uint rate ; uint tmp ; uint mcs ; int tot_streams ; u8 tmp___0 ; uint tmp___1 ; bool tmp___2 ; bool tmp___3 ; uint tmp___4 ; bool tmp___5 ; bool tmp___6 ; { tmp = rspec2rate(ratespec); rate = tmp; tmp___6 = is_mcs_rate(ratespec); if ((int )tmp___6) { mcs = ratespec & 127U; tmp___0 = mcs_2_txstreams((int )((u8 )mcs)); tmp___1 = rspec_stc(ratespec); tot_streams = (int )((uint )tmp___0 + tmp___1); dur = (uint )((-6 - tot_streams) * 4) + dur; if ((wlc->band)->bandtype == 2) { dur = dur - 6U; } else { } tmp___2 = rspec_issgi(ratespec); tmp___3 = rspec_is40mhz(ratespec); tmp___4 = mcs_2_rate((int )((u8 )mcs), (int )tmp___3, (int )tmp___2); kNdps = tmp___4 * 4U; nsyms = dur / 4U; mac_len = (nsyms * kNdps - 22000U) / 8000U; } else { tmp___5 = is_ofdm_rate(ratespec); if ((int )tmp___5) { dur = dur - 16U; dur = dur - 4U; Ndps = rate * 2U; nsyms = dur / 4U; mac_len = (nsyms * Ndps - 22U) / 8U; } else { if ((int )preamble_type & 1) { dur = dur - 96U; } else { dur = dur - 192U; } mac_len = dur * rate; mac_len = mac_len / 16U; } } return (mac_len); } } static bool brcms_c_valid_rate(struct brcms_c_info *wlc , u32 rspec , int band , bool verbose ) { struct brcms_c_rateset *hw_rateset ; uint i ; bool tmp ; uint tmp___0 ; { if (band == 0 || (wlc->band)->bandtype == band) { hw_rateset = & (wlc->band)->hw_rateset; } else if ((wlc->pub)->_nbands > 1U) { hw_rateset = & (wlc->bandstate[(wlc->band)->bandunit == 0U])->hw_rateset; } else { return (0); } tmp = is_mcs_rate(rspec); if ((int )tmp) { if ((rspec & 127U) > 32U) { goto error; } else { } return (((int )*((u8 const *)(& hw_rateset->mcs) + (unsigned long )((rspec & 127U) / 8U)) & (1 << ((int )rspec & 7))) != 0); } else { } i = 0U; goto ldv_57353; ldv_57352: tmp___0 = rspec2rate(rspec); if ((uint )hw_rateset->rates[i] == tmp___0) { return (1); } else { } i = i + 1U; ldv_57353: ; if (hw_rateset->count > i) { goto ldv_57352; } else { } error: ; if ((int )verbose) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: valid_rate: rate spec 0x%x not in hw_rateset\n", (wlc->pub)->unit, rspec); } else { } return (0); } } static u32 mac80211_wlc_set_nrate(struct brcms_c_info *wlc , struct brcms_band *cur_band , u32 int_val ) { struct bcma_device *core ; u8 stf ; u8 rate ; u32 rspec ; bool ismcs ; bool issgi ; bool override_mcs_only ; int bcmerror ; bool tmp ; bool tmp___0 ; u8 stc ; bool tmp___1 ; int tmp___2 ; { core = (wlc->hw)->d11core; stf = (u8 )((int_val & 65280U) >> 8); rate = (unsigned int )((u8 )int_val) & 127U; ismcs = (int_val & 128U) != 0U; issgi = (int_val & 8388608U) >> 23 != 0U; override_mcs_only = (int_val & 1073741824U) != 0U; bcmerror = 0; if (! ismcs) { return ((u32 )rate); } else { } if (((int )(wlc->pub)->_n_enab & 3) != 0 && (int )ismcs) { if ((unsigned int )stf > 3U) { __brcms_err(& core->dev, "wl%d: %s: Invalid stf\n", (wlc->pub)->unit, "mac80211_wlc_set_nrate"); bcmerror = -22; goto done; } else { } if ((unsigned int )rate == 32U) { if (((int )wlc->home_chanspec & 3072) != 3072 || ((unsigned int )stf != 0U && (unsigned int )stf != 1U)) { __brcms_err(& core->dev, "wl%d: %s: Invalid mcs 32\n", (wlc->pub)->unit, "mac80211_wlc_set_nrate"); bcmerror = -22; goto done; } else { } } else if ((unsigned int )rate > 7U) { if ((unsigned int )stf != 3U) { __brcms_dbg(& core->dev, 2U, "mac80211_wlc_set_nrate", "wl%d: enabling SDM mode for mcs %d\n", (wlc->pub)->unit, (int )rate); stf = 3U; } else { } } else if ((unsigned int )stf > 2U || (((unsigned int )(wlc->band)->phytype != 4U || (unsigned int )(wlc->band)->phyrev <= 2U) && (unsigned int )stf == 2U)) { __brcms_err(& core->dev, "wl%d: %s: Invalid STBC\n", (wlc->pub)->unit, "mac80211_wlc_set_nrate"); bcmerror = -22; goto done; } else { } } else { tmp___0 = is_ofdm_rate((u32 )rate); if ((int )tmp___0) { if ((unsigned int )stf != 1U && (unsigned int )stf != 0U) { __brcms_err(& core->dev, "wl%d: %s: Invalid OFDM\n", (wlc->pub)->unit, "mac80211_wlc_set_nrate"); bcmerror = -22; goto done; } else { } } else { tmp = is_cck_rate((u32 )rate); if ((int )tmp) { if (cur_band->bandtype != 2 || (unsigned int )stf != 0U) { __brcms_err(& core->dev, "wl%d: %s: Invalid CCK\n", (wlc->pub)->unit, "mac80211_wlc_set_nrate"); bcmerror = -22; goto done; } else { } } else { __brcms_err(& core->dev, "wl%d: %s: Unknown rate type\n", (wlc->pub)->unit, "mac80211_wlc_set_nrate"); bcmerror = -22; goto done; } } } if ((unsigned int )stf != 0U && (unsigned int )(wlc->stf)->txstreams == 1U) { __brcms_err(& core->dev, "wl%d: %s: SISO antenna but !SISO request\n", (wlc->pub)->unit, "mac80211_wlc_set_nrate"); bcmerror = -22; goto done; } else { } rspec = (u32 )rate; if ((int )ismcs) { rspec = rspec | 134217728U; if ((unsigned int )stf == 2U) { stc = 1U; rspec = (u32 )((int )stc << 20) | rspec; } else { } } else { } rspec = (u32 )((int )stf << 11) | rspec; if ((int )override_mcs_only) { rspec = rspec | 1073741824U; } else { } if ((int )issgi) { rspec = rspec | 8388608U; } else { } if ((unsigned int )rate != 0U) { tmp___1 = brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, 1); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return ((u32 )rate); } else { } } else { } return (rspec); done: ; return ((u32 )rate); } } static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc , int rate_500 , uint length , u8 *plcp ) { u16 usec ; u8 le ; { usec = 0U; le = 0U; switch (rate_500) { case 2: usec = (int )((u16 )length) << 3U; goto ldv_57380; case 4: usec = (int )((u16 )length) << 2U; goto ldv_57380; case 11: usec = (u16 )((length << 4) / 11U); if ((length << 4) + (uint )((int )usec * -11) != 0U) { usec = (u16 )((int )usec + 1); } else { } goto ldv_57380; case 22: usec = (u16 )((length << 3) / 11U); if ((length << 3) + (uint )((int )usec * -11) != 0U) { usec = (u16 )((int )usec + 1); if ((uint )((int )usec * 11) - (length << 3) > 7U) { le = 128U; } else { } } else { } goto ldv_57380; default: __brcms_err(& ((wlc->hw)->d11core)->dev, "brcms_c_cck_plcp_set: unsupported rate %d\n", rate_500); rate_500 = 2; usec = (int )((u16 )length) << 3U; goto ldv_57380; } ldv_57380: *plcp = (unsigned int )((u8 )rate_500) * 5U; *(plcp + 1UL) = (unsigned int )le | 4U; *(plcp + 2UL) = (u8 )usec; *(plcp + 3UL) = (u8 )((int )usec >> 8); *(plcp + 4UL) = 0U; *(plcp + 5UL) = 0U; return; } } static void brcms_c_compute_mimo_plcp(u32 rspec , uint length , u8 *plcp ) { u8 mcs ; bool tmp ; { mcs = (unsigned int )((unsigned char )rspec) & 127U; *plcp = mcs; tmp = rspec_is40mhz(rspec); if ((int )tmp || (unsigned int )mcs == 32U) { *plcp = (u8 )((unsigned int )*plcp | 128U); } else { } *(plcp + 1UL) = (u8 )length; *(plcp + 2UL) = (u8 )(length >> 8); *(plcp + 3UL) = rspec_mimoplcp3(rspec); *(plcp + 3UL) = (u8 )((unsigned int )*(plcp + 3UL) | 7U); *(plcp + 4UL) = 0U; *(plcp + 5UL) = 0U; return; } } static void brcms_c_compute_ofdm_plcp(u32 rspec , u32 length , u8 *plcp ) { u8 rate_signal ; u32 tmp ; int rate ; uint tmp___0 ; { tmp = 0U; tmp___0 = rspec2rate(rspec); rate = (int )tmp___0; rate_signal = (unsigned int )((u8 )rate_info[rate]) & 127U; memset((void *)plcp, 0, 6UL); ((struct ofdm_phy_hdr *)plcp)->rlpt[0] = (u8 )(((int )((signed char )((struct ofdm_phy_hdr *)plcp)->rlpt[0]) & -16) | ((int )((signed char )rate_signal) & 15)); tmp = (length & 4095U) << 5; *(plcp + 2UL) = (int )*(plcp + 2UL) | (int )((u8 )(tmp >> 16)); *(plcp + 1UL) = (int )*(plcp + 1UL) | (int )((u8 )(tmp >> 8)); *plcp = (int )*plcp | (int )((u8 )tmp); return; } } static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc , u32 rspec , uint length , u8 *plcp ) { int rate ; uint tmp ; { tmp = rspec2rate(rspec); rate = (int )tmp; brcms_c_cck_plcp_set(wlc, rate, length, plcp); return; } } static void brcms_c_compute_plcp(struct brcms_c_info *wlc , u32 rspec , uint length , u8 *plcp ) { bool tmp ; bool tmp___0 ; { tmp___0 = is_mcs_rate(rspec); if ((int )tmp___0) { brcms_c_compute_mimo_plcp(rspec, length, plcp); } else { tmp = is_ofdm_rate(rspec); if ((int )tmp) { brcms_c_compute_ofdm_plcp(rspec, length, plcp); } else { brcms_c_compute_cck_plcp(wlc, rspec, length, plcp); } } return; } } u16 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc , bool cts_only , u32 rts_rate , u32 frame_rate , u8 rts_preamble_type , u8 frame_preamble_type , uint frame_len , bool ba ) { u16 dur ; u16 sifs ; uint tmp ; uint tmp___0 ; uint tmp___1 ; uint tmp___2 ; { sifs = get_sifs(wlc->band); if (! cts_only) { dur = (unsigned int )sifs * 3U; tmp = brcms_c_calc_cts_time(wlc, rts_rate, (int )rts_preamble_type); dur = (int )((u16 )tmp) + (int )dur; } else { dur = (unsigned int )sifs * 2U; } tmp___0 = brcms_c_calc_frame_time(wlc, frame_rate, (int )frame_preamble_type, frame_len); dur = (int )((u16 )tmp___0) + (int )dur; if ((int )ba) { tmp___1 = brcms_c_calc_ba_time(wlc, frame_rate, 1); dur = (int )((u16 )tmp___1) + (int )dur; } else { tmp___2 = brcms_c_calc_ack_time(wlc, frame_rate, (int )frame_preamble_type); dur = (int )((u16 )tmp___2) + (int )dur; } return (dur); } } static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc , u32 rspec ) { u16 phyctl1 ; u16 bw ; u32 tmp ; uint mcs ; u8 tmp___0 ; uint tmp___1 ; s16 phycfg ; uint tmp___2 ; uint tmp___3 ; bool tmp___4 ; bool tmp___5 ; { phyctl1 = 0U; if ((unsigned int )(wlc->band)->phytype == 8U) { bw = 2U; } else { tmp = rspec_get_bw(rspec); bw = (u16 )tmp; if ((unsigned int )bw <= 1U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "phytxctl1_calc: bw %d is not supported yet, set to 20L\n", (int )bw); bw = 2U; } else { } } tmp___5 = is_mcs_rate(rspec); if ((int )tmp___5) { mcs = rspec & 127U; tmp___0 = rspec_phytxbyte2(rspec); phyctl1 = (u16 )tmp___0; phyctl1 = (u16 )((int )((short )((int )mcs_table[mcs].tx_phy_ctl3 << 8)) | (int )((short )phyctl1)); } else { tmp___4 = is_cck_rate(rspec); if (((int )tmp___4 && (unsigned int )(wlc->band)->phytype != 8U) && (unsigned int )(wlc->band)->phytype != 6U) { tmp___1 = rspec_stf(rspec); phyctl1 = ((int )((u16 )tmp___1) << 3U) | (int )bw; } else { tmp___2 = rspec2rate(rspec); phycfg = brcms_c_rate_legacy_phyctl(tmp___2); if ((int )phycfg == -1) { __brcms_err(& ((wlc->hw)->d11core)->dev, "phytxctl1_calc: wrong legacy OFDM/CCK rate\n"); phycfg = 0; } else { } tmp___3 = rspec_stf(rspec); phyctl1 = (int )((u16 )((int )((short )((int )phycfg << 8)) | (int )((short )bw))) | ((int )((u16 )tmp___3) << 3U); } } return (phyctl1); } } static u16 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc , struct ieee80211_hw *hw , struct sk_buff *p , struct scb *scb , uint frag , uint nfrags , uint queue , uint next_frag_len ) { struct ieee80211_hdr *h ; struct d11txh *txh ; u8 *plcp ; u8 plcp_fallback[6U] ; int len ; int phylen ; int rts_phylen ; u16 mch ; u16 phyctl ; u16 xfts ; u16 mainrates ; u16 seq ; u16 mcl ; u16 status ; u16 frameid ; u32 rspec[2U] ; u32 rts_rspec[2U] ; bool use_rts ; bool use_cts ; bool use_rifs ; bool short_preamble[2U] ; u8 preamble_type[2U] ; u8 rts_preamble_type[2U] ; u8 *rts_plcp ; u8 rts_plcp_fallback[6U] ; struct ieee80211_rts *rts ; bool qos ; uint ac ; bool hwtkmic ; u16 mimo_ctlchbw ; u8 antcfg ; u8 fbantcfg ; uint phyctl1_stf ; u16 durid ; struct ieee80211_tx_rate *txrate[2U] ; int k ; struct ieee80211_tx_info *tx_info ; bool is_mcs ; u16 mimo_txbw ; u8 mimo_preamble_type ; int tmp ; unsigned char *tmp___0 ; unsigned char *tmp___1 ; int tmp___2 ; bool tmp___3 ; int tmp___4 ; bool tmp___5 ; int tmp___6 ; u8 stc ; bool tmp___7 ; bool tmp___8 ; bool tmp___9 ; bool tmp___10 ; u16 tmp___11 ; bool tmp___12 ; bool tmp___13 ; int tmp___14 ; bool tmp___15 ; bool tmp___16 ; int tmp___17 ; bool tmp___18 ; bool tmp___19 ; bool tmp___20 ; int tmp___21 ; bool tmp___22 ; int tmp___23 ; int tmp___24 ; bool tmp___25 ; int tmp___26 ; bool tmp___27 ; bool tmp___28 ; uint tmp___29 ; int tmp___30 ; bool tmp___31 ; int tmp___32 ; bool tmp___33 ; int tmp___34 ; bool tmp___35 ; int tmp___36 ; u16 tmp___37 ; uint tmp___38 ; bool tmp___39 ; int tmp___40 ; uint tmp___41 ; bool tmp___42 ; int tmp___43 ; uint tmp___44 ; bool tmp___45 ; u16 tmp___46 ; u16 tmp___47 ; u16 tmp___48 ; uint tmp___49 ; u16 tmp___50 ; u16 phyctl1 ; u16 mmodelen ; u16 tmp___51 ; bool tmp___52 ; u16 mmodefbrlen ; u16 tmp___53 ; bool tmp___54 ; u16 tmp___55 ; uint frag_dur ; uint dur ; uint dur_fallback ; u16 tmp___56 ; u16 tmp___57 ; uint newfragthresh ; uint tmp___58 ; { seq = 0U; mcl = 0U; status = 0U; frameid = 0U; rspec[0] = 2U; rspec[1] = 2U; rts_rspec[0] = 2U; rts_rspec[1] = 2U; use_rts = 0; use_cts = 0; use_rifs = 0; short_preamble[0] = 0; short_preamble[1] = 0; preamble_type[0] = 0U; preamble_type[1] = 0U; rts_preamble_type[0] = 0U; rts_preamble_type[1] = 0U; rts = (struct ieee80211_rts *)0; hwtkmic = 0; mimo_ctlchbw = 2U; antcfg = 255U; fbantcfg = 255U; phyctl1_stf = 0U; durid = 0U; h = (struct ieee80211_hdr *)p->data; tmp = ieee80211_is_data_qos((int )h->frame_control); qos = tmp != 0; len = (int )p->len; phylen = len + 4; tx_info = IEEE80211_SKB_CB(p); tmp___0 = skb_push(p, 6U); plcp = tmp___0; tmp___1 = skb_push(p, 112U); txh = (struct d11txh *)tmp___1; memset((void *)txh, 0, 112UL); if ((tx_info->flags & 2U) != 0U) { if (queue == 4U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: %s: ASSERT queue == TX_BCMC!\n", (wlc->pub)->unit, "brcms_c_d11hdrs_mac80211"); frameid = bcmc_fid_generate(wlc, (struct brcms_bss_cfg *)0, txh); } else { if ((tx_info->flags & 16U) != 0U) { scb->seqnum[p->priority] = (u16 )((int )scb->seqnum[p->priority] + 1); } else { } seq = (unsigned int )h->seq_ctrl & 15U; seq = (u16 )((int )((short )((int )scb->seqnum[p->priority] << 4)) | (int )((short )seq)); h->seq_ctrl = seq; frameid = ((unsigned int )((int )seq << 5U) & 32736U) | ((unsigned int )((u16 )queue) & 7U); } } else { } frameid = ((unsigned int )((u16 )queue) & 7U) | (unsigned int )frameid; tmp___2 = ieee80211_is_beacon((int )h->frame_control); if (tmp___2 != 0) { mcl = (u16 )((unsigned int )mcl | 32U); } else { } txrate[0] = (struct ieee80211_tx_rate *)(& tx_info->__annonCompField103.control.__annonCompField101.__annonCompField100.rates); txrate[1] = txrate[0] + 1UL; if ((int )(txrate[1])->idx < 0) { txrate[1] = txrate[0]; } else { } k = 0; goto ldv_57484; ldv_57483: is_mcs = ((int )(txrate[k])->flags & 8) != 0; if (! is_mcs) { if ((int )(txrate[k])->idx >= 0 && (int )(txrate[k])->idx < ((hw->wiphy)->bands[(int )tx_info->band])->n_bitrates) { rspec[k] = (u32 )(((hw->wiphy)->bands[(int )tx_info->band])->bitrates + (unsigned long )(txrate[k])->idx)->hw_value; short_preamble[k] = ((int )(txrate[k])->flags & 4) != 0; } else { rspec[k] = 2U; } } else { rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band, (u32 )((int )(txrate[k])->idx | 128)); } use_rts = ((int )use_rts | ((int )(txrate[k])->flags & 1)) != 0; use_cts = ((int )use_cts | (((int )(txrate[k])->flags & 2) != 0)) != 0; tmp___5 = rspec_active(rspec[k]); if (tmp___5) { tmp___6 = 0; } else { tmp___6 = 1; } if (tmp___6) { rspec[k] = 2U; } else { tmp___3 = is_multicast_ether_addr((u8 const *)(& h->addr1)); if (tmp___3) { tmp___4 = 0; } else { tmp___4 = 1; } if (tmp___4) { brcms_c_antsel_antcfg_get(wlc->asi, 0, 0, 0, 0, & antcfg, & fbantcfg); } else { } } k = k + 1; ldv_57484: ; if ((int )hw->max_rates > k) { goto ldv_57483; } else { } phyctl1_stf = (uint )(wlc->stf)->ss_opmode; if (((int )(wlc->pub)->_n_enab & 3) != 0) { k = 0; goto ldv_57488; ldv_57487: tmp___8 = is_mcs_rate(rspec[k]); if ((int )tmp___8) { tmp___9 = is_single_stream((int )((u8 )rspec[k]) & 127); if ((int )tmp___9) { goto _L; } else { goto _L___0; } } else { _L___0: /* CIL Label */ tmp___10 = is_ofdm_rate(rspec[k]); if ((int )tmp___10) { _L: /* CIL Label */ if ((rspec[k] & 1073741824U) != 0U || (int )rspec[k] >= 0) { rspec[k] = rspec[k] & 4291807231U; tmp___7 = is_mcs_rate(rspec[k]); if ((int )tmp___7 && ((unsigned int )(wlc->stf)->txstreams > 1U && ((int )(wlc->band)->band_stf_stbc_tx == 1 || (((scb->flags & 1073741824U) != 0U && (int )(wlc->band)->band_stf_stbc_tx == -1) && ((int )*((u8 const *)(& (wlc->stf)->ss_algo_channel)) & 4) != 0)))) { stc = 1U; rspec[k] = (rspec[k] | (u32 )((int )stc << 20)) | 4096U; } else { rspec[k] = rspec[k] | (phyctl1_stf << 11); } } else { } } else { } } tmp___14 = brcms_chspec_bw((int )wlc->chanspec); if (tmp___14 == 40) { tmp___11 = wlc_phy_chanspec_get((wlc->band)->pi); mimo_txbw = ((int )tmp___11 & 768) == 512 ? 3U : 2U; mimo_ctlchbw = mimo_txbw; tmp___13 = is_mcs_rate(rspec[k]); if ((int )tmp___13) { if ((rspec[k] & 127U) == 32U) { mimo_txbw = 5U; } else if ((int )wlc->mimo_40txbw != -1) { mimo_txbw = (u16 )wlc->mimo_40txbw; } else if ((scb->flags & 524288U) != 0U) { mimo_txbw = 4U; } else { } } else { tmp___12 = is_ofdm_rate(rspec[k]); if ((int )tmp___12) { if ((int )wlc->ofdm_40txbw != -1) { mimo_txbw = (u16 )wlc->ofdm_40txbw; } else { } } else if ((int )wlc->cck_40txbw != -1) { mimo_txbw = (u16 )wlc->cck_40txbw; } else { } } } else { if ((rspec[k] & 127U) == 32U) { rspec[k] = 134217728U; } else { } mimo_txbw = 2U; } rspec[k] = rspec[k] & 4294965503U; if (k == 0) { rspec[k] = rspec[k] | (u32 )((int )mimo_txbw << 8); } else if (k > 0) { tmp___15 = is_mcs_rate(rspec[k]); if ((int )tmp___15) { rspec[k] = rspec[k] | (u32 )((int )mimo_txbw << 8); } else { rspec[k] = rspec[k] | (u32 )((int )mimo_ctlchbw << 8); } } else { rspec[k] = rspec[k] | (u32 )((int )mimo_ctlchbw << 8); } rspec[k] = rspec[k] & 4286578687U; mimo_preamble_type = 4U; if (((int )(txrate[k])->flags & 16) != 0) { mimo_preamble_type = 2U; } else { } if (((int )(txrate[k])->flags & 8) != 0) { tmp___16 = is_mcs_rate(rspec[k]); if (tmp___16) { tmp___17 = 0; } else { tmp___17 = 1; } if (tmp___17) { __brcms_warn(& ((wlc->hw)->d11core)->dev, "wl%d: %s: IEEE80211_TX_RC_MCS != is_mcs_rate(rspec)\n", (wlc->pub)->unit, "brcms_c_d11hdrs_mac80211"); } else { } } else { } tmp___19 = is_mcs_rate(rspec[k]); if ((int )tmp___19) { preamble_type[k] = mimo_preamble_type; if ((rspec[k] & 8388608U) != 0U) { tmp___18 = is_single_stream((int )((u8 )rspec[k]) & 127); if ((int )tmp___18) { preamble_type[k] = 4U; } else { } } else { } } else { } tmp___20 = is_mcs_rate(rspec[0]); if (tmp___20) { tmp___21 = 0; } else { tmp___21 = 1; } if (tmp___21 && ((int )tx_info->__annonCompField103.control.__annonCompField101.__annonCompField100.rates[0].flags & 4) != 0) { preamble_type[k] = 1U; } else { } k = k + 1; ldv_57488: ; if ((int )hw->max_rates > k) { goto ldv_57487; } else { } } else { k = 0; goto ldv_57491; ldv_57490: rspec[k] = rspec[k] & 4294965503U; rspec[k] = rspec[k] | 512U; if ((unsigned int )(wlc->band)->phytype == 4U) { tmp___22 = is_ofdm_rate(rspec[k]); if ((int )tmp___22) { rspec[k] = rspec[k] & 4294952959U; rspec[k] = rspec[k] | (phyctl1_stf << 11); } else { } } else { } k = k + 1; ldv_57491: ; if ((int )hw->max_rates > k) { goto ldv_57490; } else { } } (txrate[0])->count = 0U; (txrate[1])->count = 0U; tmp___23 = ieee80211_is_data((int )h->frame_control); if (tmp___23 != 0) { goto _L___1; } else { tmp___24 = ieee80211_is_mgmt((int )h->frame_control); if (tmp___24 != 0) { _L___1: /* CIL Label */ if ((int )wlc->RTSThresh < phylen) { tmp___25 = is_multicast_ether_addr((u8 const *)(& h->addr1)); if (tmp___25) { tmp___26 = 0; } else { tmp___26 = 1; } if (tmp___26) { use_rts = 1; } else { } } else { } } else { } } brcms_c_compute_plcp(wlc, rspec[0], (uint )phylen, plcp); brcms_c_compute_plcp(wlc, rspec[1], (uint )phylen, (u8 *)(& plcp_fallback)); memcpy((void *)(& txh->FragPLCPFallback), (void const *)(& plcp_fallback), 6UL); tmp___27 = is_cck_rate(rspec[1]); if ((int )tmp___27) { txh->FragPLCPFallback[4] = (u8 )phylen; txh->FragPLCPFallback[5] = (u8 )((phylen & 65280) >> 8); } else { } tmp___28 = is_ofdm_rate(rspec[0]); mainrates = (int )tmp___28 ? (unsigned int )((u16 )((struct ofdm_phy_hdr *)plcp)->rlpt[0]) & 15U : (u16 )*plcp; tmp___30 = ieee80211_is_pspoll((int )h->frame_control); if (tmp___30 == 0) { tmp___31 = is_multicast_ether_addr((u8 const *)(& h->addr1)); if (tmp___31) { tmp___32 = 0; } else { tmp___32 = 1; } if (tmp___32) { if (! use_rifs) { durid = brcms_c_compute_frame_dur(wlc, rspec[0], (int )preamble_type[0], next_frag_len); h->duration_id = durid; } else { goto _L___3; } } else { goto _L___3; } } else _L___3: /* CIL Label */ if ((int )use_rifs) { tmp___29 = brcms_c_calc_frame_time(wlc, rspec[0], (int )preamble_type[0], 2346U); durid = (unsigned short )tmp___29; durid = (unsigned int )durid + 2U; h->duration_id = durid; } else { } tmp___34 = ieee80211_is_pspoll((int )h->frame_control); if (tmp___34 != 0) { txh->FragDurFallback = h->duration_id; } else { tmp___33 = is_multicast_ether_addr((u8 const *)(& h->addr1)); if ((int )tmp___33 || (int )use_rifs) { txh->FragDurFallback = 0U; } else { durid = brcms_c_compute_frame_dur(wlc, rspec[1], (int )preamble_type[1], next_frag_len); txh->FragDurFallback = durid; } } if (frag == 0U) { mcl = (u16 )((unsigned int )mcl | 8U); } else { } tmp___35 = is_multicast_ether_addr((u8 const *)(& h->addr1)); if (tmp___35) { tmp___36 = 0; } else { tmp___36 = 1; } if (tmp___36) { mcl = (u16 )((unsigned int )mcl | 1U); } else { } if ((wlc->band)->bandtype == 1) { mcl = (u16 )((unsigned int )mcl | 128U); } else { } tmp___37 = wlc_phy_chanspec_get((wlc->band)->pi); if (((int )tmp___37 & 3072) == 3072) { mcl = (u16 )((unsigned int )mcl | 256U); } else { } if ((int )hwtkmic) { mcl = (u16 )((unsigned int )mcl | 32768U); } else { } txh->MacTxControlLow = mcl; mch = 0U; if ((unsigned int )preamble_type[1] == 1U || (unsigned int )preamble_type[1] == 2U) { tmp___38 = rspec2rate(rspec[1]); if (tmp___38 != 2U) { mch = (u16 )((unsigned int )mch | 8192U); } else { } } else { } memcpy((void *)(& txh->MacFrameControl), (void const *)(& h->frame_control), 2UL); txh->TxFesTimeNormal = 0U; txh->TxFesTimeFallback = 0U; memcpy((void *)(& txh->TxFrameRA), (void const *)(& h->addr1), 6UL); txh->TxFrameID = frameid; txh->TxStatus = status; txh->MaxNMpdus = 0U; txh->MaxABytes_MRT = 0U; txh->MaxABytes_FBR = 0U; txh->MinMBytes = 0U; if ((int )use_rts || (int )use_cts) { if ((int )use_rts && (int )use_cts) { use_cts = 0; } else { } k = 0; goto ldv_57494; ldv_57493: rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k], 0, (int )mimo_ctlchbw); k = k + 1; ldv_57494: ; if (k <= 1) { goto ldv_57493; } else { } tmp___39 = is_ofdm_rate(rts_rspec[0]); if (tmp___39) { tmp___40 = 0; } else { tmp___40 = 1; } if (tmp___40) { tmp___41 = rspec2rate(rts_rspec[0]); if (tmp___41 != 2U && (int )wlc->PLCPHdr_override != 1) { rts_preamble_type[0] = 1U; mch = (u16 )((unsigned int )mch | 16384U); } else { } } else { } tmp___42 = is_ofdm_rate(rts_rspec[1]); if (tmp___42) { tmp___43 = 0; } else { tmp___43 = 1; } if (tmp___43) { tmp___44 = rspec2rate(rts_rspec[1]); if (tmp___44 != 2U && (int )wlc->PLCPHdr_override != 1) { rts_preamble_type[1] = 1U; mch = (u16 )((unsigned int )mch | 32768U); } else { } } else { } if ((int )use_cts) { txh->MacTxControlLow = (__le16 )((unsigned int )txh->MacTxControlLow | 2048U); } else { txh->MacTxControlLow = (__le16 )((unsigned int )txh->MacTxControlLow | 4U); txh->MacTxControlLow = (__le16 )((unsigned int )txh->MacTxControlLow | 2U); } rts_plcp = (u8 *)(& txh->RTSPhyHeader); if ((int )use_cts) { rts_phylen = 14; } else { rts_phylen = 20; } brcms_c_compute_plcp(wlc, rts_rspec[0], (uint )rts_phylen, rts_plcp); brcms_c_compute_plcp(wlc, rts_rspec[1], (uint )rts_phylen, (u8 *)(& rts_plcp_fallback)); memcpy((void *)(& txh->RTSPLCPFallback), (void const *)(& rts_plcp_fallback), 6UL); rts = & txh->rts_frame; durid = brcms_c_compute_rtscts_dur(wlc, (int )use_cts, rts_rspec[0], rspec[0], (int )rts_preamble_type[0], (int )preamble_type[0], (uint )phylen, 0); rts->duration = durid; durid = brcms_c_compute_rtscts_dur(wlc, (int )use_cts, rts_rspec[1], rspec[1], (int )rts_preamble_type[1], (int )preamble_type[1], (uint )phylen, 0); txh->RTSDurFallback = durid; if ((int )use_cts) { rts->frame_control = 196U; memcpy((void *)(& rts->ra), (void const *)(& h->addr2), 6UL); } else { rts->frame_control = 180U; memcpy((void *)(& rts->ra), (void const *)(& h->addr1), 12UL); } tmp___45 = is_ofdm_rate(rts_rspec[0]); mainrates = (u16 )(((int )tmp___45 ? (short )(((int )((struct ofdm_phy_hdr *)rts_plcp)->rlpt[0] & 15) << 8) : (short )((int )*rts_plcp << 8)) | (int )((short )mainrates)); } else { memset((void *)(& txh->RTSPhyHeader), 0, 6UL); memset((void *)(& txh->rts_frame), 0, 16UL); memset((void *)(& txh->RTSPLCPFallback), 0, 6UL); txh->RTSDurFallback = 0U; } txh->MacTxControlHigh = mch; txh->MainRates = mainrates; xfts = frametype(rspec[1], (int )wlc->mimoft); tmp___46 = frametype(rts_rspec[0], (int )wlc->mimoft); xfts = (u16 )((int )((short )((int )tmp___46 << 2)) | (int )((short )xfts)); tmp___47 = frametype(rts_rspec[1], (int )wlc->mimoft); xfts = (u16 )((int )((short )((int )tmp___47 << 4)) | (int )((short )xfts)); tmp___48 = wlc_phy_chanspec_get((wlc->band)->pi); xfts = (u16 )((int )((short )((int )((unsigned char )tmp___48) << 8)) | (int )((short )xfts)); txh->XtraFrameTypes = xfts; phyctl = frametype(rspec[0], (int )wlc->mimoft); if ((unsigned int )preamble_type[0] == 1U || (unsigned int )preamble_type[0] == 2U) { tmp___49 = rspec2rate(rspec[0]); if (tmp___49 != 2U) { phyctl = (u16 )((unsigned int )phyctl | 16U); } else { } } else { } tmp___50 = brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]); phyctl = (u16 )((int )tmp___50 | (int )phyctl); txh->PhyTxControlWord = phyctl; if (((unsigned int )(wlc->band)->phytype == 4U || (unsigned int )(wlc->band)->phytype == 8U) || (unsigned int )(wlc->band)->phytype == 6U) { phyctl1 = 0U; phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]); txh->PhyTxControlWord_1 = phyctl1; phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]); txh->PhyTxControlWord_1_Fbr = phyctl1; if ((int )use_rts || (int )use_cts) { phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]); txh->PhyTxControlWord_1_Rts = phyctl1; phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]); txh->PhyTxControlWord_1_FbrRts = phyctl1; } else { } tmp___52 = is_mcs_rate(rspec[0]); if ((int )tmp___52 && (unsigned int )preamble_type[0] == 4U) { tmp___51 = brcms_c_calc_lsig_len(wlc, rspec[0], (uint )phylen); mmodelen = tmp___51; txh->MModeLen = mmodelen; } else { } tmp___54 = is_mcs_rate(rspec[1]); if ((int )tmp___54 && (unsigned int )preamble_type[1] == 4U) { tmp___53 = brcms_c_calc_lsig_len(wlc, rspec[1], (uint )phylen); mmodefbrlen = tmp___53; txh->MModeFbrLen = mmodefbrlen; } else { } } else { } tmp___55 = skb_get_queue_mapping((struct sk_buff const *)p); ac = (uint )tmp___55; if (((scb->flags & 64U) != 0U && (int )qos) && (unsigned int )wlc->edcf_txop[ac] != 0U) { if ((tx_info->flags & 64U) == 0U && frag == 0U) { frag_dur = brcms_c_calc_frame_time(wlc, rspec[0], (int )preamble_type[0], (uint )phylen); if ((unsigned long )rts != (unsigned long )((struct ieee80211_rts *)0)) { dur = brcms_c_calc_cts_time(wlc, rts_rspec[0], (int )rts_preamble_type[0]); dur_fallback = brcms_c_calc_cts_time(wlc, rts_rspec[1], (int )rts_preamble_type[1]); dur = (uint )rts->duration + dur; dur_fallback = (uint )txh->RTSDurFallback + dur_fallback; } else if ((int )use_rifs) { dur = frag_dur; dur_fallback = 0U; } else { dur = frag_dur; tmp___56 = brcms_c_compute_frame_dur(wlc, rspec[0], (int )preamble_type[0], 0U); dur = (uint )tmp___56 + dur; dur_fallback = brcms_c_calc_frame_time(wlc, rspec[1], (int )preamble_type[1], (uint )phylen); tmp___57 = brcms_c_compute_frame_dur(wlc, rspec[1], (int )preamble_type[1], 0U); dur_fallback = (uint )tmp___57 + dur_fallback; } txh->TxFesTimeNormal = (unsigned short )dur; txh->TxFesTimeFallback = (unsigned short )dur_fallback; if ((uint )wlc->edcf_txop[ac] >= dur - frag_dur) { newfragthresh = brcms_c_calc_frame_len(wlc, rspec[0], (int )preamble_type[0], (uint )wlc->edcf_txop[ac] + (frag_dur - dur)); if (newfragthresh <= 255U) { newfragthresh = 256U; } else if ((uint )wlc->usr_fragthresh < newfragthresh) { newfragthresh = (uint )wlc->usr_fragthresh; } else { } if ((int )wlc->fragthresh[queue] != (int )((unsigned short )newfragthresh)) { wlc->fragthresh[queue] = (unsigned short )newfragthresh; } else { } } else { tmp___58 = rspec2rate(rspec[0]); __brcms_warn(& ((wlc->hw)->d11core)->dev, "wl%d: %s txop invalid for rate %d\n", (wlc->pub)->unit, (char const *)(& fifo_names) + (unsigned long )queue, tmp___58); } if ((uint )wlc->edcf_txop[ac] < dur) { __brcms_warn(& ((wlc->hw)->d11core)->dev, "wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n", (wlc->pub)->unit, "brcms_c_d11hdrs_mac80211", (char const *)(& fifo_names) + (unsigned long )queue, phylen, (int )wlc->fragthresh[queue], dur, (int )wlc->edcf_txop[ac]); } else { } } else { } } else { } return (0U); } } static int brcms_c_tx(struct brcms_c_info *wlc , struct sk_buff *skb ) { struct dma_pub *dma ; int fifo ; int ret ; struct d11txh *txh ; u16 frameid ; u16 tmp ; u8 tmp___0 ; int __ret_warn_on ; u16 tmp___1 ; int tmp___2 ; long tmp___3 ; bool __warned ; int __ret_warn_once ; int __ret_warn_on___0 ; long tmp___4 ; long tmp___5 ; long tmp___6 ; { ret = -28; frameid = 65535U; tmp = skb_get_queue_mapping((struct sk_buff const *)skb); tmp___0 = brcms_ac_to_fifo((int )((u8 )tmp)); fifo = (int )tmp___0; dma = (wlc->hw)->di[fifo]; txh = (struct d11txh *)skb->data; if (dma->txavail == 0U) { __brcms_warn(& ((wlc->hw)->d11core)->dev, "Received frame for tx with no space in DMA ring\n"); tmp___1 = skb_get_queue_mapping((struct sk_buff const *)skb); tmp___2 = ieee80211_queue_stopped((wlc->pub)->ieee_hw, (int )tmp___1); __ret_warn_on = tmp___2 == 0; tmp___3 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___3 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 6886); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return (-28); } else { } if (fifo == 4) { frameid = txh->TxFrameID; } else { } if ((unsigned int )frameid != 65535U) { brcms_b_write_shm(wlc->hw, 168U, (int )frameid); } else { } ret = brcms_c_txfifo(wlc, (uint )fifo, skb); __ret_warn_once = ret != 0; tmp___6 = ldv__builtin_expect(__ret_warn_once != 0, 0L); if (tmp___6 != 0L) { __ret_warn_on___0 = ! __warned; tmp___4 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___4 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 6911); } else { } tmp___5 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___5 != 0L) { __warned = 1; } else { } } else { } ldv__builtin_expect(__ret_warn_once != 0, 0L); return (ret); } } bool brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc , struct sk_buff *sdu , struct ieee80211_hw *hw ) { uint fifo ; struct scb *scb ; u16 tmp ; u8 tmp___0 ; int tmp___1 ; { scb = & wlc->pri_scb; tmp = skb_get_queue_mapping((struct sk_buff const *)sdu); tmp___0 = brcms_ac_to_fifo((int )((u8 )tmp)); fifo = (uint )tmp___0; brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0U, 1U, fifo, 0U); tmp___1 = brcms_c_tx(wlc, sdu); if (tmp___1 == 0) { return (1); } else { } dev_kfree_skb_any(sdu); return (0); } } int brcms_c_txfifo(struct brcms_c_info *wlc , uint fifo , struct sk_buff *p ) { struct dma_pub *dma ; int ret ; u16 queue ; int tmp ; { dma = (wlc->hw)->di[fifo]; ret = dma_txfast(wlc, dma, p); if (ret < 0) { dev_err((struct device const *)(& (wlc->wiphy)->dev), "txfifo: fatal, toss frames !!!\n"); } else { } queue = skb_get_queue_mapping((struct sk_buff const *)p); if (dma->txavail <= 4U && fifo <= 3U) { tmp = ieee80211_queue_stopped((wlc->pub)->ieee_hw, (int )queue); if (tmp == 0) { ieee80211_stop_queue((wlc->pub)->ieee_hw, (int )queue); } else { } } else { } return (ret); } } u32 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc , u32 rspec , bool use_rspec , u16 mimo_ctlchbw ) { u32 rts_rspec ; u8 tmp ; u8 tmp___0 ; bool tmp___1 ; int tmp___2 ; bool tmp___3 ; bool tmp___4 ; int tmp___5 ; bool tmp___6 ; { rts_rspec = 0U; if ((int )use_rspec) { rts_rspec = rspec; } else if ((unsigned int )(wlc->band)->gmode != 0U && (int )(wlc->protection)->_g) { tmp___1 = is_cck_rate(rspec); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { tmp = brcms_basic_rate(wlc, 22U); rts_rspec = (u32 )tmp; } else { tmp___0 = brcms_basic_rate(wlc, rspec); rts_rspec = (u32 )tmp___0; } } else { tmp___0 = brcms_basic_rate(wlc, rspec); rts_rspec = (u32 )tmp___0; } if (((unsigned int )(wlc->band)->phytype == 4U || (unsigned int )(wlc->band)->phytype == 8U) || (unsigned int )(wlc->band)->phytype == 6U) { rts_rspec = rts_rspec & 4294965503U; tmp___3 = rspec_is40mhz(rspec); if ((int )tmp___3) { tmp___4 = is_cck_rate(rts_rspec); if (tmp___4) { tmp___5 = 0; } else { tmp___5 = 1; } if (tmp___5) { rts_rspec = rts_rspec | 1280U; } else { rts_rspec = (u32 )((int )mimo_ctlchbw << 8) | rts_rspec; } } else { rts_rspec = (u32 )((int )mimo_ctlchbw << 8) | rts_rspec; } tmp___6 = is_ofdm_rate(rts_rspec); if ((int )tmp___6) { rts_rspec = rts_rspec & 4294952959U; rts_rspec = (u32 )((int )(wlc->stf)->ss_opmode << 11) | rts_rspec; } else { } } else { } return (rts_rspec); } } static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc ) { { if ((unsigned int )wlc->bcn_li_dtim == 1U) { brcms_b_write_shm(wlc->hw, 182U, 0); } else { brcms_b_write_shm(wlc->hw, 182U, (int )((u16 )((int )((short )((int )wlc->bcn_li_dtim << 8)) | (int )((short )wlc->bcn_li_bcn)))); } return; } } static void brcms_b_read_tsf(struct brcms_hardware *wlc_hw , u32 *tsf_l_ptr , u32 *tsf_h_ptr ) { struct bcma_device *core ; { core = wlc_hw->d11core; *tsf_l_ptr = bcma_read32(core, 384); *tsf_h_ptr = bcma_read32(core, 388); return; } } static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc , struct d11rxhdr *rxh ) { u32 tsf_h ; u32 tsf_l ; u16 rx_tsf_0_15 ; u16 rx_tsf_16_31 ; { brcms_b_read_tsf(wlc->hw, & tsf_l, & tsf_h); rx_tsf_16_31 = (unsigned short )(tsf_l >> 16); rx_tsf_0_15 = rxh->RxTSFTime; if ((int )((unsigned short )tsf_l) < (int )rx_tsf_0_15) { rx_tsf_16_31 = (unsigned int )rx_tsf_16_31 + 65535U; if ((unsigned int )rx_tsf_16_31 == 65535U) { tsf_h = tsf_h - 1U; } else { } } else { } return (((unsigned long long )tsf_h << 32) | (unsigned long long )(((unsigned int )rx_tsf_16_31 << 16) + (unsigned int )rx_tsf_0_15)); } } static void prep_mac80211_status(struct brcms_c_info *wlc , struct d11rxhdr *rxh , struct sk_buff *p , struct ieee80211_rx_status *rx_status ) { int channel ; u32 rspec ; unsigned char *plcp ; int tmp ; int tmp___0 ; bool tmp___1 ; uint tmp___2 ; bool tmp___3 ; bool tmp___4 ; bool tmp___5 ; bool tmp___6 ; { rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh); rx_status->flag = rx_status->flag | 128U; channel = ((int )rxh->RxChan & 2040) >> 3; rx_status->band = channel > 14; tmp = ieee80211_channel_to_frequency(channel, (enum ieee80211_band )rx_status->band); rx_status->freq = (u16 )tmp; tmp___0 = wlc_phy_rssi_compute(((wlc->hw)->band)->pi, rxh); rx_status->signal = (s8 )tmp___0; rx_status->antenna = ((int )rxh->PhyRxStatus_0 & 32) != 0; plcp = p->data; rspec = brcms_c_compute_rspec(rxh, plcp); tmp___5 = is_mcs_rate(rspec); if ((int )tmp___5) { rx_status->rate_idx = (unsigned int )((u8 )rspec) & 127U; rx_status->flag = rx_status->flag | 512U; tmp___1 = rspec_is40mhz(rspec); if ((int )tmp___1) { rx_status->flag = rx_status->flag | 1024U; } else { } } else { tmp___2 = rspec2rate(rspec); switch (tmp___2) { case 2U: rx_status->rate_idx = 0U; goto ldv_57568; case 4U: rx_status->rate_idx = 1U; goto ldv_57568; case 11U: rx_status->rate_idx = 2U; goto ldv_57568; case 22U: rx_status->rate_idx = 3U; goto ldv_57568; case 12U: rx_status->rate_idx = 4U; goto ldv_57568; case 18U: rx_status->rate_idx = 5U; goto ldv_57568; case 24U: rx_status->rate_idx = 6U; goto ldv_57568; case 36U: rx_status->rate_idx = 7U; goto ldv_57568; case 48U: rx_status->rate_idx = 8U; goto ldv_57568; case 72U: rx_status->rate_idx = 9U; goto ldv_57568; case 96U: rx_status->rate_idx = 10U; goto ldv_57568; case 108U: rx_status->rate_idx = 11U; goto ldv_57568; default: __brcms_err(& ((wlc->hw)->d11core)->dev, "%s: Unknown rate\n", "prep_mac80211_status"); } ldv_57568: ; if ((unsigned int )rx_status->band == 1U) { rx_status->rate_idx = (unsigned int )rx_status->rate_idx + 252U; } else { } tmp___4 = is_cck_rate(rspec); if ((int )tmp___4) { if (((int )rxh->PhyRxStatus_0 & 128) != 0) { rx_status->flag = rx_status->flag | 256U; } else { } } else { tmp___3 = is_ofdm_rate(rspec); if ((int )tmp___3) { rx_status->flag = rx_status->flag | 256U; } else { __brcms_err(& ((wlc->hw)->d11core)->dev, "%s: Unknown modulation\n", "prep_mac80211_status"); } } } tmp___6 = plcp3_issgi((int )*(plcp + 3UL)); if ((int )tmp___6) { rx_status->flag = rx_status->flag | 2048U; } else { } if (((int )rxh->RxStatus1 & 16) != 0) { rx_status->flag = rx_status->flag | 64U; __brcms_err(& ((wlc->hw)->d11core)->dev, "%s: RX_FLAG_FAILED_PLCP_CRC\n", "prep_mac80211_status"); } else { } if ((int )rxh->RxStatus1 & 1) { rx_status->flag = rx_status->flag | 32U; __brcms_err(& ((wlc->hw)->d11core)->dev, "%s: RX_FLAG_FAILED_FCS_CRC\n", "prep_mac80211_status"); } else { } return; } } static void brcms_c_recvctl(struct brcms_c_info *wlc , struct d11rxhdr *rxh , struct sk_buff *p ) { int len_mpdu ; struct ieee80211_rx_status rx_status ; struct ieee80211_hdr *hdr ; int tmp ; struct ieee80211_rx_status *tmp___0 ; { memset((void *)(& rx_status), 0, 40UL); prep_mac80211_status(wlc, rxh, p, & rx_status); len_mpdu = (int )(p->len - 10U); skb_pull(p, 6U); __skb_trim(p, (unsigned int )len_mpdu); if ((unsigned int )(wlc->hw)->suspended_fifos != 0U) { hdr = (struct ieee80211_hdr *)p->data; tmp = ieee80211_is_beacon((int )hdr->frame_control); if (tmp != 0) { brcms_b_mute(wlc->hw, 0); } else { } } else { } tmp___0 = IEEE80211_SKB_RXCB(p); memcpy((void *)tmp___0, (void const *)(& rx_status), 40UL); ieee80211_rx_irqsafe((wlc->pub)->ieee_hw, p); return; } } u16 brcms_c_calc_lsig_len(struct brcms_c_info *wlc , u32 ratespec , uint mac_len ) { uint nsyms ; uint len ; uint kNdps ; uint mcs ; int tot_streams ; u8 tmp ; uint tmp___0 ; bool tmp___1 ; bool tmp___2 ; uint tmp___3 ; uint tmp___4 ; bool tmp___5 ; { len = 0U; tmp___5 = is_mcs_rate(ratespec); if ((int )tmp___5) { mcs = ratespec & 127U; tmp = mcs_2_txstreams((int )((u8 )mcs)); tmp___0 = rspec_stc(ratespec); tot_streams = (int )(((uint )tmp + tmp___0) + 1U); tmp___1 = rspec_issgi(ratespec); tmp___2 = rspec_is40mhz(ratespec); tmp___3 = mcs_2_rate((int )((u8 )mcs), (int )tmp___2, (int )tmp___1); kNdps = tmp___3 * 4U; tmp___4 = rspec_stc(ratespec); if (tmp___4 == 0U) { nsyms = ((mac_len * 8000U + kNdps) + 21999U) / kNdps; } else { nsyms = (((mac_len * 4000U + kNdps) * 2U + 21999U) / (kNdps * 2U)) * 2U; } nsyms = ((uint )tot_streams + nsyms) + 3U; len = nsyms * 3U + 4294967293U; } else { } return ((u16 )len); } } static void brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc , uint frame_len ) { struct brcms_c_rateset const *rs_dflt ; struct brcms_c_rateset rs ; u8 rate ; u16 entry_ptr ; u8 plcp[6U] ; u16 dur ; u16 sifs ; uint i ; uint tmp ; { sifs = get_sifs(wlc->band); rs_dflt = brcms_c_rateset_get_hwrs(wlc); brcms_c_rateset_copy(rs_dflt, & rs); brcms_c_rateset_mcs_upd(& rs, (int )(wlc->stf)->txstreams); i = 0U; goto ldv_57613; ldv_57612: rate = (unsigned int )rs.rates[i] & 127U; entry_ptr = brcms_b_rate_shm_offset(wlc->hw, (int )rate); brcms_c_compute_plcp(wlc, (u32 )rate, frame_len, (u8 *)(& plcp)); tmp = brcms_c_calc_frame_time(wlc, (u32 )rate, 0, frame_len); dur = (unsigned short )tmp; dur = (int )dur + (int )sifs; brcms_b_write_shm(wlc->hw, (uint )((int )entry_ptr + 10), (int )((unsigned short )plcp[0]) + ((int )((unsigned short )plcp[1]) << 8U)); brcms_b_write_shm(wlc->hw, (uint )((int )entry_ptr + 12), (int )((unsigned short )plcp[2]) + ((int )((unsigned short )plcp[3]) << 8U)); brcms_b_write_shm(wlc->hw, (uint )((int )entry_ptr + 16), (int )dur); i = i + 1U; ldv_57613: ; if (rs.count > i) { goto ldv_57612; } else { } return; } } int brcms_c_get_header_len(void) { { return (118); } } static void brcms_c_beacon_write(struct brcms_c_info *wlc , struct sk_buff *beacon , u16 tim_offset , u16 dtim_period , bool bcn0 , bool bcn1 ) { size_t len ; struct ieee80211_tx_info *tx_info ; struct brcms_hardware *wlc_hw ; struct ieee80211_hw *ieee_hw ; struct brcms_pub *tmp ; size_t __min1 ; size_t __min2 ; struct ieee80211_rate *tmp___0 ; { wlc_hw = wlc->hw; tmp = brcms_c_pub(wlc); ieee_hw = tmp->ieee_hw; tx_info = IEEE80211_SKB_CB(beacon); __min1 = (size_t )beacon->len; __min2 = 512UL; len = __min1 < __min2 ? __min1 : __min2; tmp___0 = ieee80211_get_tx_rate((struct ieee80211_hw const *)ieee_hw, (struct ieee80211_tx_info const *)tx_info); wlc->bcn_rspec = (u32 )tmp___0->hw_value; brcms_c_compute_plcp(wlc, wlc->bcn_rspec, (uint )len - 2U, beacon->data); brcms_c_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec); if ((int )bcn0) { brcms_b_write_template_ram(wlc_hw, 104, (int )((unsigned int )len + 3U) & -4, (void *)beacon->data); brcms_b_write_shm(wlc_hw, 24U, (int )((unsigned short )len)); } else { } if ((int )bcn1) { brcms_b_write_template_ram(wlc_hw, 1128, (int )((unsigned int )len + 3U) & -4, (void *)beacon->data); brcms_b_write_shm(wlc_hw, 26U, (int )((unsigned short )len)); } else { } if ((unsigned int )tim_offset != 0U) { brcms_b_write_shm(wlc_hw, 30U, (int )((unsigned int )tim_offset + 6U)); brcms_b_write_shm(wlc_hw, 18U, (int )dtim_period); } else { brcms_b_write_shm(wlc_hw, 30U, (int )((unsigned int )((u16 )len) + 6U)); brcms_b_write_shm(wlc_hw, 18U, 0); } return; } } static void brcms_c_update_beacon_hw(struct brcms_c_info *wlc , struct sk_buff *beacon , u16 tim_offset , u16 dtim_period ) { struct brcms_hardware *wlc_hw ; struct bcma_device *core ; u32 both_valid ; u32 tmp ; u32 tmp___0 ; u32 tmp___1 ; u32 tmp___2 ; { wlc_hw = wlc->hw; core = wlc_hw->d11core; both_valid = 3U; tmp = bcma_read32(core, 292); if ((tmp & both_valid) == both_valid) { bcma_write32(core, 296, 2U); } else { } if ((int )wlc->beacon_template_virgin) { wlc->beacon_template_virgin = 0; brcms_c_beacon_write(wlc, beacon, (int )tim_offset, (int )dtim_period, 1, 1); bcma_set32(core, 292, 1U); return; } else { } tmp___0 = bcma_read32(core, 292); if ((tmp___0 & both_valid) == both_valid) { wlc->defmacintmask = wlc->defmacintmask | 2U; return; } else { } tmp___1 = bcma_read32(core, 292); if ((tmp___1 & 1U) == 0U) { brcms_c_beacon_write(wlc, beacon, (int )tim_offset, (int )dtim_period, 1, 0); bcma_set32(core, 292, 1U); return; } else { } tmp___2 = bcma_read32(core, 292); if ((tmp___2 & 2U) == 0U) { brcms_c_beacon_write(wlc, beacon, (int )tim_offset, (int )dtim_period, 0, 1); bcma_set32(core, 292, 2U); return; } else { } return; } } void brcms_c_update_beacon(struct brcms_c_info *wlc ) { struct brcms_bss_cfg *bsscfg ; { bsscfg = wlc->bsscfg; if ((int )(wlc->pub)->up && ((unsigned int )bsscfg->type == 1U || (unsigned int )bsscfg->type == 2U)) { wlc->defmacintmask = wlc->defmacintmask & 4294967293U; if ((unsigned long )wlc->beacon == (unsigned long )((struct sk_buff *)0)) { return; } else { } brcms_c_update_beacon_hw(wlc, wlc->beacon, (int )wlc->beacon_tim_offset, (int )wlc->beacon_dtim_period); } else { } return; } } void brcms_c_set_new_beacon(struct brcms_c_info *wlc , struct sk_buff *beacon , u16 tim_offset , u16 dtim_period ) { { if ((unsigned long )beacon == (unsigned long )((struct sk_buff *)0)) { return; } else { } if ((unsigned long )wlc->beacon != (unsigned long )((struct sk_buff *)0)) { dev_kfree_skb_any(wlc->beacon); } else { } wlc->beacon = beacon; skb_push(wlc->beacon, 6U); wlc->beacon_tim_offset = tim_offset; wlc->beacon_dtim_period = dtim_period; brcms_c_update_beacon(wlc); return; } } void brcms_c_set_new_probe_resp(struct brcms_c_info *wlc , struct sk_buff *probe_resp ) { { if ((unsigned long )probe_resp == (unsigned long )((struct sk_buff *)0)) { return; } else { } if ((unsigned long )wlc->probe_resp != (unsigned long )((struct sk_buff *)0)) { dev_kfree_skb_any(wlc->probe_resp); } else { } wlc->probe_resp = probe_resp; skb_push(wlc->probe_resp, 6U); brcms_c_update_probe_resp(wlc, 0); return; } } void brcms_c_enable_probe_resp(struct brcms_c_info *wlc , bool enable ) { { wlc->prb_resp_timeout = (int )enable ? 0U : 1U; brcms_b_write_shm(wlc->hw, 116U, (int )wlc->prb_resp_timeout); return; } } static void brcms_c_shm_ssid_upd(struct brcms_c_info *wlc , struct brcms_bss_cfg *cfg ) { u8 *ssidptr ; u16 base ; u8 ssidbuf[32U] ; { ssidptr = (u8 *)(& cfg->SSID); base = 352U; memset((void *)(& ssidbuf), 0, 32UL); memcpy((void *)(& ssidbuf), (void const *)ssidptr, (size_t )cfg->SSID_len); brcms_c_copyto_shm(wlc, (uint )base, (void const *)(& ssidbuf), 32); brcms_b_write_shm(wlc->hw, 72U, (int )cfg->SSID_len); return; } } static void brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc , struct brcms_bss_cfg *cfg , struct sk_buff *probe_resp , bool suspend ) { int len ; size_t __min1 ; size_t __min2 ; { __min1 = (size_t )probe_resp->len; __min2 = 512UL; len = (int )(__min1 < __min2 ? __min1 : __min2); if ((int )suspend) { brcms_c_suspend_mac_and_wait(wlc); } else { } brcms_b_write_template_ram(wlc->hw, 616, (len + 3) & -4, (void *)probe_resp->data); brcms_b_write_shm(wlc->hw, 74U, (int )((unsigned short )len)); brcms_c_shm_ssid_upd(wlc, cfg); brcms_c_mod_prb_rsp_rate_table(wlc, (uint )((int )((unsigned short )len) + -2)); if ((int )suspend) { brcms_c_enable_mac(wlc); } else { } return; } } void brcms_c_update_probe_resp(struct brcms_c_info *wlc , bool suspend ) { struct brcms_bss_cfg *bsscfg ; { bsscfg = wlc->bsscfg; if ((int )(wlc->pub)->up && ((unsigned int )bsscfg->type == 1U || (unsigned int )bsscfg->type == 2U)) { if ((unsigned long )wlc->probe_resp == (unsigned long )((struct sk_buff *)0)) { return; } else { } brcms_c_bss_update_probe_resp(wlc, bsscfg, wlc->probe_resp, (int )suspend); } else { } return; } } int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw , uint fifo , uint *blocks ) { { if (fifo > 5U) { return (-22); } else { } *blocks = (uint )*(wlc_hw->xmtfifo_sz + (unsigned long )fifo); return (0); } } void brcms_c_set_addrmatch(struct brcms_c_info *wlc , int match_reg_offset , u8 const *addr ) { { brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr); if (match_reg_offset == 3) { memcpy((void *)(& (wlc->bsscfg)->BSSID), (void const *)addr, 6UL); } else { } return; } } void brcms_c_scan_start(struct brcms_c_info *wlc ) { { wlc_phy_hold_upd((wlc->band)->pi, 2U, 1); return; } } void brcms_c_scan_stop(struct brcms_c_info *wlc ) { { wlc_phy_hold_upd((wlc->band)->pi, 2U, 0); return; } } void brcms_c_associate_upd(struct brcms_c_info *wlc , bool state ) { { (wlc->pub)->associated = state; return; } } void brcms_c_inval_dma_pkts(struct brcms_hardware *hw , struct ieee80211_sta *sta , void *dma_callback_fn ) { struct dma_pub *dmah ; int i ; { i = 0; goto ldv_57710; ldv_57709: dmah = hw->di[i]; if ((unsigned long )dmah != (unsigned long )((struct dma_pub *)0)) { dma_walk_packets(dmah, (void (*)(void * , void * ))dma_callback_fn, (void *)sta); } else { } i = i + 1; ldv_57710: ; if (i <= 5) { goto ldv_57709; } else { } return; } } int brcms_c_get_curband(struct brcms_c_info *wlc ) { { return ((int )(wlc->band)->bandunit); } } bool brcms_c_tx_flush_completed(struct brcms_c_info *wlc ) { int i ; int tmp ; { i = 0; goto ldv_57722; ldv_57721: ; if ((unsigned long )(wlc->hw)->di[i] != (unsigned long )((struct dma_pub *)0)) { dma_kick_tx((wlc->hw)->di[i]); } else { } i = i + 1; ldv_57722: ; if ((unsigned int )i <= 5U) { goto ldv_57721; } else { } tmp = brcms_txpktpendtot(wlc); return (tmp == 0); } } void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc , u8 interval ) { { wlc->bcn_li_bcn = interval; if ((int )(wlc->pub)->up) { brcms_c_bcn_li_upd(wlc); } else { } return; } } u64 brcms_c_tsf_get(struct brcms_c_info *wlc ) { u32 tsf_h ; u32 tsf_l ; u64 tsf ; { brcms_b_read_tsf(wlc->hw, & tsf_l, & tsf_h); tsf = (u64 )tsf_h; tsf = tsf << 32; tsf = (u64 )tsf_l | tsf; return (tsf); } } void brcms_c_tsf_set(struct brcms_c_info *wlc , u64 tsf ) { u32 tsf_h ; u32 tsf_l ; { brcms_c_time_lock(wlc); tsf_l = (u32 )tsf; tsf_h = (u32 )(tsf >> 32); bcma_write32((wlc->hw)->d11core, 384, tsf_l); bcma_write32((wlc->hw)->d11core, 388, tsf_h); brcms_c_time_unlock(wlc); return; } } int brcms_c_set_tx_power(struct brcms_c_info *wlc , int txpwr ) { uint qdbm ; uint __min1 ; uint __min2 ; int tmp ; { __min1 = (uint )(txpwr * 4); __min2 = 255U; qdbm = __min1 < __min2 ? __min1 : __min2; tmp = wlc_phy_txpower_set((wlc->band)->pi, qdbm, 0); return (tmp); } } int brcms_c_get_tx_power(struct brcms_c_info *wlc ) { uint qdbm ; bool override ; { wlc_phy_txpower_get((wlc->band)->pi, & qdbm, & override); return ((int )(qdbm / 4U)); } } static void brcms_c_recv(struct brcms_c_info *wlc , struct sk_buff *p ) { struct d11rxhdr *rxh ; struct ieee80211_hdr *h ; uint len ; bool is_amsdu ; { rxh = (struct d11rxhdr *)p->data; skb_pull(p, 38U); if (((int )rxh->RxStatus1 & 4) != 0) { if (p->len <= 1U) { __brcms_err(& ((wlc->hw)->d11core)->dev, "wl%d: recv: rcvd runt of len %d\n", (wlc->pub)->unit, p->len); goto toss; } else { } skb_pull(p, 2U); } else { } h = (struct ieee80211_hdr *)p->data + 6U; len = p->len; if ((int )rxh->RxStatus1 & 1) { if ((wlc->filter_flags & 4U) == 0U) { goto toss; } else { } } else { } if (len <= 7U) { goto toss; } else { } is_amsdu = ((int )rxh->RxStatus2 & 1) != 0; if ((int )is_amsdu) { goto toss; } else { } brcms_c_recvctl(wlc, rxh, p); return; toss: brcmu_pkt_buf_free_skb(p); return; } } static bool brcms_b_recv(struct brcms_hardware *wlc_hw , uint fifo , bool bound ) { struct sk_buff *p ; struct sk_buff *next ; struct sk_buff_head recv_frames ; uint n ; uint bound_limit ; bool morepending ; int tmp ; struct d11rxhdr_le *rxh_le ; struct d11rxhdr *rxh ; { next = (struct sk_buff *)0; n = 0U; bound_limit = (int )bound ? 8U : 4294967295U; morepending = 0; skb_queue_head_init(& recv_frames); ldv_57774: ; if (n >= bound_limit) { goto ldv_57773; } else { } tmp = dma_rx(wlc_hw->di[fifo], & recv_frames); morepending = tmp != 0; n = n + 1U; if ((int )morepending) { goto ldv_57774; } else { } ldv_57773: dma_rxfill(wlc_hw->di[fifo]); p = recv_frames.next; next = p->__annonCompField68.__annonCompField67.next; goto ldv_57778; ldv_57777: skb_unlink(p, & recv_frames); rxh_le = (struct d11rxhdr_le *)p->data; rxh = (struct d11rxhdr *)p->data; rxh->RxFrameSize = rxh_le->RxFrameSize; rxh->PhyRxStatus_0 = rxh_le->PhyRxStatus_0; rxh->PhyRxStatus_1 = rxh_le->PhyRxStatus_1; rxh->PhyRxStatus_2 = rxh_le->PhyRxStatus_2; rxh->PhyRxStatus_3 = rxh_le->PhyRxStatus_3; rxh->PhyRxStatus_4 = rxh_le->PhyRxStatus_4; rxh->PhyRxStatus_5 = rxh_le->PhyRxStatus_5; rxh->RxStatus1 = rxh_le->RxStatus1; rxh->RxStatus2 = rxh_le->RxStatus2; rxh->RxTSFTime = rxh_le->RxTSFTime; rxh->RxChan = rxh_le->RxChan; brcms_c_recv(wlc_hw->wlc, p); p = next; next = p->__annonCompField68.__annonCompField67.next; ldv_57778: ; if ((unsigned long )((struct sk_buff *)(& recv_frames)) != (unsigned long )p) { goto ldv_57777; } else { } return (morepending); } } bool brcms_c_dpc(struct brcms_c_info *wlc , bool bounded ) { u32 macintstatus ; struct brcms_hardware *wlc_hw ; struct bcma_device *core ; bool tmp ; int __ret_warn_on ; long tmp___0 ; bool fatal ; bool tmp___1 ; bool tmp___2 ; bool __print_once ; uint tmp___3 ; uint tmp___4 ; { wlc_hw = wlc->hw; core = wlc_hw->d11core; tmp = brcms_deviceremoved(wlc); if ((int )tmp) { __brcms_err(& core->dev, "wl%d: %s: dead chip\n", wlc_hw->unit, "brcms_c_dpc"); brcms_down(wlc->wl); return (0); } else { } macintstatus = wlc->macintstatus; wlc->macintstatus = 0U; __brcms_dbg(& core->dev, 16U, "brcms_c_dpc", "wl%d: macintstatus 0x%x\n", wlc_hw->unit, macintstatus); __ret_warn_on = (macintstatus & 1048576U) != 0U; tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/main.c", 7796); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); if ((macintstatus & 536870912U) != 0U) { tmp___1 = brcms_b_txstatus(wlc->hw, (int )bounded, & fatal); if ((int )tmp___1) { wlc->macintstatus = wlc->macintstatus | 536870912U; } else { } if ((int )fatal) { __brcms_err(& core->dev, "MI_TFS: fatal\n"); goto fatal; } else { } } else { } if ((macintstatus & 524292U) != 0U) { brcms_c_tbtt(wlc); } else { } if ((macintstatus & 32U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_c_dpc", "end of ATIM window\n"); bcma_set32(core, 292, wlc->qvalid); wlc->qvalid = 0U; } else { } if ((macintstatus & 32768U) != 0U) { tmp___2 = brcms_b_recv(wlc_hw, 0U, (int )bounded); if ((int )tmp___2) { wlc->macintstatus = wlc->macintstatus | 32768U; } else { } } else { } if ((macintstatus & 262144U) != 0U) { wlc_phy_noise_sample_intr((wlc_hw->band)->pi); } else { } if ((macintstatus & 8192U) != 0U) { __brcms_err(& core->dev, "wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now); if (! __print_once) { __print_once = 1; tmp___3 = ai_get_chiprev(wlc_hw->sih); tmp___4 = ai_get_chip_id(wlc_hw->sih); printk("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n", "brcms_c_dpc", tmp___4, tmp___3); } else { } brcms_fatal_error((wlc_hw->wlc)->wl); } else { } if ((int )macintstatus < 0) { bcma_write32(core, 24, 0U); } else { } if ((macintstatus & 268435456U) != 0U) { __brcms_dbg(& core->dev, 1U, "brcms_c_dpc", "wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit); brcms_rfkill_set_hw_state(wlc->wl); } else { } if ((macintstatus & 2U) != 0U) { brcms_c_update_beacon(wlc); } else { } return (wlc->macintstatus != 0U); fatal: brcms_fatal_error((wlc_hw->wlc)->wl); return (wlc->macintstatus != 0U); } } void brcms_c_init(struct brcms_c_info *wlc , bool mute_tx ) { struct bcma_device *core ; struct ieee80211_channel *ch ; u16 chanspec ; u32 bi ; u16 rev ; u16 patch ; int ac ; { core = (wlc->hw)->d11core; ch = ((wlc->pub)->ieee_hw)->conf.chandef.chan; __brcms_dbg(& core->dev, 1U, "brcms_c_init", "wl%d\n", (wlc->pub)->unit); chanspec = ch20mhz_chspec((int )ch->hw_value); brcms_b_init(wlc->hw, (int )chanspec); brcms_c_bcn_li_upd(wlc); brcms_c_set_mac(wlc->bsscfg); brcms_c_set_bssid(wlc->bsscfg); if ((int )(wlc->pub)->associated && (int )(wlc->pub)->up) { bi = (u32 )((int )((wlc->bsscfg)->current_bss)->beacon_period << 10); bcma_write32(core, 392, bi << 6); brcms_c_set_ps_ctrl(wlc); } else { } brcms_c_bandinit_ordered(wlc, (int )chanspec); brcms_b_write_shm(wlc->hw, 116U, (int )wlc->prb_resp_timeout); brcms_b_write_shm(wlc->hw, 130U, (int )wlc->_rifs ? 1504 : 10000); brcms_c_duty_cycle_set(wlc, (int )wlc->tx_duty_cycle_ofdm, 1, 1); brcms_c_duty_cycle_set(wlc, (int )wlc->tx_duty_cycle_cck, 0, 1); brcms_c_ampdu_shm_upd(wlc->ampdu); brcms_c_bsinit(wlc); bcma_set16(core, 1672, 4); brcms_c_edcf_setparams(wlc, 0); if (wlc->ucode_rev == 0U) { rev = brcms_b_read_shm(wlc->hw, 0U); patch = brcms_b_read_shm(wlc->hw, 2U); wlc->ucode_rev = (uint )(((int )rev << 16) | (int )patch); snprintf((char *)(& (wlc->wiphy)->fw_version), 32UL, "%u.%u", (int )rev, (int )patch); } else { } brcms_c_enable_mac(wlc); if ((int )mute_tx) { brcms_b_mute(wlc->hw, 1); } else { } bcma_write32(core, 988, 10000000U); if (((unsigned int )wlc->wme_retries[0] & 15U) == 0U) { ac = 0; goto ldv_57806; ldv_57805: wlc->wme_retries[ac] = brcms_b_read_shm(wlc->hw, (uint )((ac + 384) * 2)); ac = ac + 1; ldv_57806: ; if (ac <= 3) { goto ldv_57805; } else { } } else { } return; } } struct brcms_c_info *brcms_c_attach(struct brcms_info *wl , struct bcma_device *core , uint unit , bool piomode , uint *perr ) { struct brcms_c_info *wlc ; uint err ; uint i ; uint j ; struct brcms_pub *pub ; int tmp ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; { err = 0U; wlc = brcms_c_attach_malloc(unit, & err, 0U); if ((unsigned long )wlc == (unsigned long )((struct brcms_c_info *)0)) { goto fail; } else { } wlc->wiphy = wl->wiphy; pub = wlc->pub; wlc->band = wlc->bandstate[0]; wlc->core = wlc->corestate; wlc->wl = wl; pub->unit = unit; pub->_piomode = piomode; wlc->bandinit_pending = 0; wlc->beacon_template_virgin = 1; brcms_c_info_init(wlc, (int )unit); brcms_c_ap_upd(wlc); tmp = brcms_b_attach(wlc, core, unit, (int )piomode); err = (uint )tmp; if (err != 0U) { goto fail; } else { } brcms_c_protection_upd(wlc, 15U, 0); pub->phy_11ncapable = (bool )(((unsigned int )(wlc->band)->phytype == 4U || (unsigned int )(wlc->band)->phytype == 8U) || (unsigned int )(wlc->band)->phytype == 6U); wlc->tx_duty_cycle_ofdm = 0U; wlc->tx_duty_cycle_cck = 0U; brcms_c_stf_phy_chain_calc(wlc); if ((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->stf)->txstreams == 1U) { (wlc->stf)->txant = (s8 )((unsigned int )(wlc->stf)->hw_txchain + 255U); } else { } wlc_phy_stf_chain_init((wlc->band)->pi, (int )(wlc->stf)->hw_txchain, (int )(wlc->stf)->hw_rxchain); i = 0U; goto ldv_57822; ldv_57821: (wlc->core)->txavail[i] = (wlc->hw)->txavail[i]; i = i + 1U; ldv_57822: ; if (i <= 5U) { goto ldv_57821; } else { } memcpy((void *)(& wlc->perm_etheraddr), (void const *)(& (wlc->hw)->etheraddr), 6UL); memcpy((void *)(& pub->cur_etheraddr), (void const *)(& (wlc->hw)->etheraddr), 6UL); j = 0U; goto ldv_57825; ldv_57824: wlc->band = wlc->bandstate[j]; tmp___0 = brcms_c_attach_stf_ant_init(wlc); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { err = 24U; goto fail; } else { } (wlc->band)->CWmin = 15U; (wlc->band)->CWmax = 1023U; if ((wlc->band)->bandtype == 2) { (wlc->band)->gmode = 1U; brcms_c_protection_upd(wlc, 3U, (int )(wlc->band)->gmode); } else { } if (((unsigned int )(wlc->band)->phytype == 4U || (unsigned int )(wlc->band)->phytype == 8U) || (unsigned int )(wlc->band)->phytype == 6U) { pub->_n_enab = 3U; brcms_c_protection_upd(wlc, 10U, (unsigned int )pub->_n_enab == 3U ? 1 : 3); } else { } brcms_default_rateset(wlc, & (wlc->band)->defrateset); brcms_c_rateset_filter(& (wlc->band)->defrateset, & (wlc->band)->hw_rateset, 0, 0, 127U, ((int )(wlc->pub)->_n_enab & 3) != 0); j = j + 1U; ldv_57825: ; if ((wlc->pub)->_nbands > j) { goto ldv_57824; } else { } brcms_c_stf_phy_txant_upd(wlc); err = brcms_c_attach_module(wlc); if (err != 0U) { goto fail; } else { } tmp___2 = brcms_c_timers_init(wlc, (int )unit); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { dev_err((struct device const *)(& (wl->wiphy)->dev), "wl%d: %s: init_timer failed\n", unit, "brcms_c_attach"); err = 32U; goto fail; } else { } wlc->cmi = brcms_c_channel_mgr_attach(wlc); if ((unsigned long )wlc->cmi == (unsigned long )((struct brcms_cm_info *)0)) { dev_err((struct device const *)(& (wl->wiphy)->dev), "wl%d: %s: channel_mgr_attach failed\n", unit, "brcms_c_attach"); err = 33U; goto fail; } else { } brcms_c_bss_default_init(wlc); (wlc->bsscfg)->wlc = wlc; wlc->mimoft = 2U; wlc->mimo_40txbw = -1; wlc->ofdm_40txbw = -1; wlc->cck_40txbw = -1; brcms_c_update_mimo_band_bwcap(wlc, 2); if (((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->band)->phyrev > 2U) || (unsigned int )(wlc->band)->phytype == 8U) { brcms_c_ht_update_sgi_rx(wlc, 3); } else if ((unsigned int )(wlc->band)->phytype == 6U) { brcms_c_ht_update_sgi_rx(wlc, 3); } else { brcms_c_ht_update_sgi_rx(wlc, 0); } brcms_b_antsel_set(wlc->hw, (u32 )(wlc->asi)->antsel_avail); if ((unsigned long )perr != (unsigned long )((uint *)0U)) { *perr = 0U; } else { } return (wlc); fail: dev_err((struct device const *)(& (wl->wiphy)->dev), "wl%d: %s: failed with err %d\n", unit, "brcms_c_attach", err); if ((unsigned long )wlc != (unsigned long )((struct brcms_c_info *)0)) { brcms_c_detach(wlc); } else { } if ((unsigned long )perr != (unsigned long )((uint *)0U)) { *perr = err; } else { } return ((struct brcms_c_info *)0); } } bool ldv_queue_work_on_87(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_88(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_89(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_90(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_91(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_101(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_103(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_102(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_105(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_104(struct workqueue_struct *ldv_func_arg1 ) ; struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim , void (*fn)(struct brcms_phy * ) , void *arg , char const *name ) ; void wlapi_free_timer(struct wlapi_timer *t ) ; void wlapi_add_timer(struct wlapi_timer *t , uint ms , int periodic ) ; bool wlapi_del_timer(struct wlapi_timer *t ) ; void wlapi_intrson(struct phy_shim_info *physhim ) ; u32 wlapi_intrsoff(struct phy_shim_info *physhim ) ; void wlapi_intrsrestore(struct phy_shim_info *physhim , u32 macintmask ) ; void wlapi_bmac_write_shm(struct phy_shim_info *physhim , uint offset , u16 v ) ; u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim , uint offset ) ; void wlapi_bmac_mhf(struct phy_shim_info *physhim , u8 idx , u16 mask , u16 val , int bands ) ; void wlapi_bmac_corereset(struct phy_shim_info *physhim , u32 flags ) ; void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim ) ; void wlapi_switch_macfreq(struct phy_shim_info *physhim , u8 spurmode ) ; void wlapi_enable_mac(struct phy_shim_info *physhim ) ; void wlapi_bmac_mctrl(struct phy_shim_info *physhim , u32 mask , u32 val ) ; void wlapi_bmac_phy_reset(struct phy_shim_info *physhim ) ; void wlapi_bmac_bw_set(struct phy_shim_info *physhim , u16 bw ) ; void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim , bool clk ) ; void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim , bool clk ) ; void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim , bool on ) ; void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim ) ; void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim ) ; void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim ) ; void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim , int offset , int len , void *buf ) ; u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim , u8 rate ) ; void wlapi_ucode_sample_init(struct phy_shim_info *physhim ) ; void wlapi_copyfrom_objmem(struct phy_shim_info *physhim , uint offset , void *buf , int len , u32 sel ) ; void wlapi_copyto_objmem(struct phy_shim_info *physhim , uint offset , void const *buf , int l , u32 sel ) ; u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim ) ; struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw , struct brcms_info *wl , struct brcms_c_info *wlc ) { struct phy_shim_info *physhim ; void *tmp ; { physhim = (struct phy_shim_info *)0; tmp = kzalloc(24UL, 32U); physhim = (struct phy_shim_info *)tmp; if ((unsigned long )physhim == (unsigned long )((struct phy_shim_info *)0)) { return ((struct phy_shim_info *)0); } else { } physhim->wlc_hw = wlc_hw; physhim->wlc = wlc; physhim->wl = wl; return (physhim); } } void wlc_phy_shim_detach(struct phy_shim_info *physhim ) { { kfree((void const *)physhim); return; } } struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim , void (*fn)(struct brcms_phy * ) , void *arg , char const *name ) { struct brcms_timer *tmp ; { tmp = brcms_init_timer(physhim->wl, (void (*)(void * ))fn, arg, name); return ((struct wlapi_timer *)tmp); } } void wlapi_free_timer(struct wlapi_timer *t ) { { brcms_free_timer((struct brcms_timer *)t); return; } } void wlapi_add_timer(struct wlapi_timer *t , uint ms , int periodic ) { { brcms_add_timer((struct brcms_timer *)t, ms, periodic); return; } } bool wlapi_del_timer(struct wlapi_timer *t ) { bool tmp ; { tmp = brcms_del_timer((struct brcms_timer *)t); return (tmp); } } void wlapi_intrson(struct phy_shim_info *physhim ) { { brcms_intrson(physhim->wl); return; } } u32 wlapi_intrsoff(struct phy_shim_info *physhim ) { u32 tmp ; { tmp = brcms_intrsoff(physhim->wl); return (tmp); } } void wlapi_intrsrestore(struct phy_shim_info *physhim , u32 macintmask ) { { brcms_intrsrestore(physhim->wl, macintmask); return; } } void wlapi_bmac_write_shm(struct phy_shim_info *physhim , uint offset , u16 v ) { { brcms_b_write_shm(physhim->wlc_hw, offset, (int )v); return; } } u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim , uint offset ) { u16 tmp ; { tmp = brcms_b_read_shm(physhim->wlc_hw, offset); return (tmp); } } void wlapi_bmac_mhf(struct phy_shim_info *physhim , u8 idx , u16 mask , u16 val , int bands ) { { brcms_b_mhf(physhim->wlc_hw, (int )idx, (int )mask, (int )val, bands); return; } } void wlapi_bmac_corereset(struct phy_shim_info *physhim , u32 flags ) { { brcms_b_corereset(physhim->wlc_hw, flags); return; } } void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim ) { { brcms_c_suspend_mac_and_wait(physhim->wlc); return; } } void wlapi_switch_macfreq(struct phy_shim_info *physhim , u8 spurmode ) { { brcms_b_switch_macfreq(physhim->wlc_hw, (int )spurmode); return; } } void wlapi_enable_mac(struct phy_shim_info *physhim ) { { brcms_c_enable_mac(physhim->wlc); return; } } void wlapi_bmac_mctrl(struct phy_shim_info *physhim , u32 mask , u32 val ) { { brcms_b_mctrl(physhim->wlc_hw, mask, val); return; } } void wlapi_bmac_phy_reset(struct phy_shim_info *physhim ) { { brcms_b_phy_reset(physhim->wlc_hw); return; } } void wlapi_bmac_bw_set(struct phy_shim_info *physhim , u16 bw ) { { brcms_b_bw_set(physhim->wlc_hw, (int )bw); return; } } u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim ) { u16 tmp ; { tmp = brcms_b_get_txant(physhim->wlc_hw); return (tmp); } } void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim , bool clk ) { { brcms_b_phyclk_fgc(physhim->wlc_hw, (int )clk); return; } } void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim , bool clk ) { { brcms_b_macphyclk_set(physhim->wlc_hw, (int )clk); return; } } void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim , bool on ) { { brcms_b_core_phypll_ctl(physhim->wlc_hw, (int )on); return; } } void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim ) { { brcms_b_core_phypll_reset(physhim->wlc_hw); return; } } void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim ) { { brcms_c_ucode_wake_override_set(physhim->wlc_hw, 2U); return; } } void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim ) { { brcms_c_ucode_wake_override_clear(physhim->wlc_hw, 2U); return; } } void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim , int offset , int len , void *buf ) { { brcms_b_write_template_ram(physhim->wlc_hw, offset, len, buf); return; } } u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim , u8 rate ) { u16 tmp ; { tmp = brcms_b_rate_shm_offset(physhim->wlc_hw, (int )rate); return (tmp); } } void wlapi_ucode_sample_init(struct phy_shim_info *physhim ) { { return; } } void wlapi_copyfrom_objmem(struct phy_shim_info *physhim , uint offset , void *buf , int len , u32 sel ) { { brcms_b_copyfrom_objmem(physhim->wlc_hw, offset, buf, len, sel); return; } } void wlapi_copyto_objmem(struct phy_shim_info *physhim , uint offset , void const *buf , int l , u32 sel ) { { brcms_b_copyto_objmem(physhim->wlc_hw, offset, buf, l, sel); return; } } bool ldv_queue_work_on_101(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_102(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_103(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_104(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_105(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_115(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_117(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_116(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_119(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_118(struct workqueue_struct *ldv_func_arg1 ) ; u16 si_pmu_fast_pwrup_delay(struct si_pub *sih ) ; u32 si_pmu_measure_alpclk(struct si_pub *sih ) ; u16 si_pmu_fast_pwrup_delay(struct si_pub *sih ) { uint delay ; uint tmp ; { delay = 15000U; tmp = ai_get_chip_id(sih); switch (tmp) { case 43224U: ; case 43225U: ; case 17171U: delay = 3700U; goto ldv_35246; default: ; goto ldv_35246; } ldv_35246: ; return ((u16 )delay); } } u32 si_pmu_measure_alpclk(struct si_pub *sih ) { struct si_info *sii ; struct si_pub const *__mptr ; struct bcma_device *core ; u32 alp_khz ; int tmp ; u32 ilp_ctr ; u32 alp_hz ; u32 tmp___0 ; u32 tmp___1 ; { __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; tmp = ai_get_pmurev(sih); if (tmp <= 9) { return (0U); } else { } core = (sii->icbus)->drv_cc.core; tmp___1 = bcma_read32(core, 1544); if ((tmp___1 & 256U) != 0U) { bcma_write32(core, 1644, 2147483648U); __const_udelay(4295000UL); tmp___0 = bcma_read32(core, 1644); ilp_ctr = tmp___0 & 8191U; bcma_write32(core, 1644, 0U); alp_hz = (ilp_ctr * 32768U) / 4U; alp_khz = ((alp_hz + 50000U) / 100000U) * 100U; } else { alp_khz = 0U; } return (alp_khz); } } bool ldv_queue_work_on_115(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_116(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_117(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_118(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_119(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_129(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_131(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_130(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_133(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_132(struct workqueue_struct *ldv_func_arg1 ) ; u8 const *wlc_phy_get_ofdm_rate_lookup(void) ; struct brcms_c_rateset const ofdm_rates ; __inline static u8 ofdm_phy2mac_rate(u8 rlpt ) { u8 const *tmp ; { tmp = wlc_phy_get_ofdm_rate_lookup(); return ((u8 )*(tmp + ((unsigned long )rlpt & 7UL))); } } void brcms_c_rateset_mcs_clear(struct brcms_c_rateset *rateset ) ; u8 const rate_info[109U] = { 0U, 0U, 10U, 0U, 20U, 0U, 0U, 0U, 0U, 0U, 0U, 55U, 139U, 0U, 0U, 0U, 0U, 0U, 143U, 0U, 0U, 0U, 110U, 0U, 138U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 142U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 137U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 141U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 136U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 140U}; struct brcms_mcs_info const mcs_table[33U] = { {6500U, 13500U, 7223U, 15000U, 0U, 12U}, {13000U, 27000U, 14445U, 30000U, 8U, 24U}, {19500U, 40500U, 21667U, 45000U, 10U, 36U}, {26000U, 54000U, 28889U, 60000U, 16U, 48U}, {39000U, 81000U, 43334U, 90000U, 18U, 72U}, {52000U, 108000U, 57778U, 120000U, 25U, 96U}, {58500U, 121500U, 65000U, 135000U, 26U, 108U}, {65000U, 135000U, 72223U, 150000U, 28U, 108U}, {13000U, 27000U, 14445U, 30000U, 64U, 12U}, {26000U, 54000U, 28889U, 60000U, 72U, 24U}, {39000U, 81000U, 43334U, 90000U, 74U, 36U}, {52000U, 108000U, 57778U, 120000U, 80U, 48U}, {78000U, 162000U, 86667U, 180000U, 82U, 72U}, {104000U, 216000U, 115556U, 240000U, 89U, 96U}, {117000U, 243000U, 130000U, 270000U, 90U, 108U}, {130000U, 270000U, 144445U, 300000U, 92U, 108U}, {19500U, 40500U, 21667U, 45000U, 128U, 12U}, {39000U, 81000U, 43334U, 90000U, 136U, 24U}, {58500U, 121500U, 65000U, 135000U, 138U, 36U}, {78000U, 162000U, 86667U, 180000U, 144U, 48U}, {117000U, 243000U, 130000U, 270000U, 146U, 72U}, {156000U, 324000U, 173334U, 360000U, 153U, 96U}, {175500U, 364500U, 195000U, 405000U, 154U, 108U}, {195000U, 405000U, 216667U, 450000U, 155U, 108U}, {26000U, 54000U, 28889U, 60000U, 192U, 12U}, {52000U, 108000U, 57778U, 120000U, 200U, 24U}, {78000U, 162000U, 86667U, 180000U, 202U, 36U}, {104000U, 216000U, 115556U, 240000U, 208U, 48U}, {156000U, 324000U, 173334U, 360000U, 210U, 72U}, {208000U, 432000U, 231112U, 480000U, 217U, 96U}, {234000U, 486000U, 260000U, 540000U, 218U, 108U}, {260000U, 540000U, 288889U, 600000U, 219U, 108U}, {0U, 6000U, 0U, 6667U, 0U, 12U}}; static struct legacy_phycfg const legacy_phycfg_table[12U] = { {2U, 0U}, {4U, 8U}, {11U, 16U}, {22U, 24U}, {12U, 0U}, {18U, 2U}, {24U, 8U}, {36U, 10U}, {48U, 16U}, {72U, 18U}, {96U, 25U}, {108U, 26U}}; struct brcms_c_rateset const cck_ofdm_mimo_rates = {12U, {130U, 132U, 139U, 12U, 18U, 150U, 24U, 36U, 48U, 72U, 96U, 108U}, 0U, {255U, 255U, 255U, 255U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}}; struct brcms_c_rateset const ofdm_mimo_rates = {8U, {140U, 18U, 152U, 36U, 176U, 72U, 96U, 108U}, 0U, {255U, 255U, 255U, 255U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}}; static struct brcms_c_rateset const cck_ofdm_40bw_mimo_rates = {12U, {130U, 132U, 139U, 12U, 18U, 150U, 24U, 36U, 48U, 72U, 96U, 108U}, 0U, {255U, 255U, 255U, 255U, 1U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}}; static struct brcms_c_rateset const ofdm_40bw_mimo_rates = {8U, {140U, 18U, 152U, 36U, 176U, 72U, 96U, 108U}, 0U, {255U, 255U, 255U, 255U, 1U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}}; struct brcms_c_rateset const cck_ofdm_rates = {12U, {130U, 132U, 139U, 12U, 18U, 150U, 24U, 36U, 48U, 72U, 96U, 108U}, 0U, {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}}; struct brcms_c_rateset const gphy_legacy_rates = {4U, {130U, 132U, 139U, 150U}, 0U, {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}}; struct brcms_c_rateset const ofdm_rates = {8U, {140U, 18U, 152U, 36U, 176U, 72U, 96U, 108U}, 0U, {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}}; struct brcms_c_rateset const cck_rates = {4U, {130U, 132U, 11U, 22U}, 0U, {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}}; static bool brcms_c_rateset_valid(struct brcms_c_rateset *rs , bool check_brate ) { uint idx ; { if (rs->count == 0U) { return (0); } else { } if (! check_brate) { return (1); } else { } idx = 0U; goto ldv_36098; ldv_36097: ; if ((int )((signed char )rs->rates[idx]) < 0) { return (1); } else { } idx = idx + 1U; ldv_36098: ; if (rs->count > idx) { goto ldv_36097; } else { } return (0); } } void brcms_c_rateset_mcs_upd(struct brcms_c_rateset *rs , u8 txstreams ) { int i ; { i = (int )txstreams; goto ldv_36106; ldv_36105: rs->mcs[i] = 0U; i = i + 1; ldv_36106: ; if (i <= 3) { goto ldv_36105; } else { } return; } } bool brcms_c_rate_hwrs_filter_sort_validate(struct brcms_c_rateset *rs , struct brcms_c_rateset const *hw_rs , bool check_brate , u8 txstreams ) { u8 rateset[109U] ; u8 r ; uint count ; uint i ; uint tmp ; bool tmp___0 ; { memset((void *)(& rateset), 0, 109UL); count = rs->count; i = 0U; goto ldv_36120; ldv_36119: r = (unsigned int )rs->rates[i] & 127U; if ((unsigned int )r > 108U || (unsigned int )((unsigned char )rate_info[(int )r]) == 0U) { goto ldv_36118; } else { } rateset[(int )r] = rs->rates[i]; ldv_36118: i = i + 1U; ldv_36120: ; if (i < count) { goto ldv_36119; } else { } count = 0U; i = 0U; goto ldv_36123; ldv_36122: r = (unsigned int )hw_rs->rates[i] & 127U; if ((unsigned int )rateset[(int )r] != 0U) { tmp = count; count = count + 1U; rs->rates[tmp] = rateset[(int )r]; } else { } i = i + 1U; ldv_36123: ; if ((uint )hw_rs->count > i) { goto ldv_36122; } else { } rs->count = count; i = 0U; goto ldv_36126; ldv_36125: rs->mcs[i] = (u8 )((int )rs->mcs[i] & (int )hw_rs->mcs[i]); i = i + 1U; ldv_36126: ; if (i <= 15U) { goto ldv_36125; } else { } tmp___0 = brcms_c_rateset_valid(rs, (int )check_brate); if ((int )tmp___0) { return (1); } else { return (0); } } } u32 brcms_c_compute_rspec(struct d11rxhdr *rxh , u8 *plcp ) { int phy_type ; u32 rspec ; u8 tmp ; u8 tmp___0 ; bool tmp___1 ; u8 tmp___2 ; u8 tmp___3 ; { rspec = 512U; phy_type = (int )rxh->RxChan & 7; if (((phy_type == 4 || phy_type == 6) || phy_type == 8) || phy_type == 7) { switch ((int )rxh->PhyRxStatus_0 & 3) { case 0: tmp = cck_phy2mac_rate((int )((struct cck_phy_hdr *)plcp)->signal); rspec = (u32 )tmp; goto ldv_36135; case 1: tmp___0 = ofdm_phy2mac_rate((int )((struct ofdm_phy_hdr *)plcp)->rlpt[0]); rspec = (u32 )tmp___0; goto ldv_36135; case 2: rspec = (u32 )(((int )*plcp & 127) | 134217728); if ((int )((signed char )*plcp) < 0) { rspec = rspec & 4294965503U; rspec = rspec | 1024U; } else { } goto ldv_36135; case 3: ; default: ; goto ldv_36135; } ldv_36135: tmp___1 = plcp3_issgi((int )*(plcp + 3UL)); if ((int )tmp___1) { rspec = rspec | 8388608U; } else { } } else if (phy_type == 0 || (int )rxh->PhyRxStatus_0 & 1) { tmp___2 = ofdm_phy2mac_rate((int )((struct ofdm_phy_hdr *)plcp)->rlpt[0]); rspec = (u32 )tmp___2; } else { tmp___3 = cck_phy2mac_rate((int )((struct cck_phy_hdr *)plcp)->signal); rspec = (u32 )tmp___3; } return (rspec); } } void brcms_c_rateset_copy(struct brcms_c_rateset const *src , struct brcms_c_rateset *dst ) { { memcpy((void *)dst, (void const *)src, 40UL); return; } } void brcms_c_rateset_filter(struct brcms_c_rateset *src , struct brcms_c_rateset *dst , bool basic_only , u8 rates , uint xmask , bool mcsallow ) { uint i ; uint r ; uint count ; bool tmp ; bool tmp___0 ; uint tmp___1 ; { count = 0U; i = 0U; goto ldv_36157; ldv_36156: r = (uint )src->rates[i]; if ((int )basic_only && (r & 128U) == 0U) { goto ldv_36155; } else { } if ((unsigned int )rates == 1U) { tmp = is_ofdm_rate(r & 127U); if ((int )tmp) { goto ldv_36155; } else { } } else { } if ((unsigned int )rates == 2U) { tmp___0 = is_cck_rate(r & 127U); if ((int )tmp___0) { goto ldv_36155; } else { } } else { } tmp___1 = count; count = count + 1U; dst->rates[tmp___1] = (int )((u8 )r) & (int )((u8 )xmask); ldv_36155: i = i + 1U; ldv_36157: ; if (src->count > i) { goto ldv_36156; } else { } dst->count = count; dst->htphy_membership = src->htphy_membership; if ((int )mcsallow && (unsigned int )rates != 1U) { memcpy((void *)(& dst->mcs), (void const *)(& src->mcs), 16UL); } else { brcms_c_rateset_mcs_clear(dst); } return; } } void brcms_c_rateset_default(struct brcms_c_rateset *rs_tgt , struct brcms_c_rateset const *rs_hw , uint phy_type , int bandtype , bool cck_only , uint rate_mask , bool mcsallow , u8 bw , u8 txstreams ) { struct brcms_c_rateset const *rs_dflt ; struct brcms_c_rateset rs_sel ; { if ((phy_type == 4U || phy_type == 8U) || phy_type == 6U) { if (bandtype == 1) { rs_dflt = (unsigned int )bw == 20U ? & ofdm_mimo_rates : & ofdm_40bw_mimo_rates; } else { rs_dflt = (unsigned int )bw == 20U ? & cck_ofdm_mimo_rates : & cck_ofdm_40bw_mimo_rates; } } else { rs_dflt = & cck_rates; } if ((unsigned long )rs_hw == (unsigned long )((struct brcms_c_rateset const *)0)) { rs_hw = rs_dflt; } else { } brcms_c_rateset_copy(rs_dflt, & rs_sel); brcms_c_rateset_mcs_upd(& rs_sel, (int )txstreams); brcms_c_rateset_filter(& rs_sel, rs_tgt, 0, (int )cck_only, rate_mask, (int )mcsallow); brcms_c_rate_hwrs_filter_sort_validate(rs_tgt, rs_hw, 0, (int )mcsallow ? (int )txstreams : 1); return; } } s16 brcms_c_rate_legacy_phyctl(uint rate ) { uint i ; { i = 0U; goto ldv_36177; ldv_36176: ; if ((uint )legacy_phycfg_table[i].rate_ofdm == rate) { return ((s16 )legacy_phycfg_table[i].tx_phy_ctl3); } else { } i = i + 1U; ldv_36177: ; if (i <= 11U) { goto ldv_36176; } else { } return (-1); } } void brcms_c_rateset_mcs_clear(struct brcms_c_rateset *rateset ) { uint i ; { i = 0U; goto ldv_36184; ldv_36183: rateset->mcs[i] = 0U; i = i + 1U; ldv_36184: ; if (i <= 15U) { goto ldv_36183; } else { } return; } } void brcms_c_rateset_mcs_build(struct brcms_c_rateset *rateset , u8 txstreams ) { { memcpy((void *)(& rateset->mcs), (void const *)(& cck_ofdm_mimo_rates.mcs), 16UL); brcms_c_rateset_mcs_upd(rateset, (int )txstreams); return; } } void brcms_c_rateset_bw_mcs_filter(struct brcms_c_rateset *rateset , u8 bw ) { { if ((unsigned int )bw == 40U) { *((u8 *)(& rateset->mcs) + 4UL) = (u8 )((unsigned int )*((u8 *)(& rateset->mcs) + 4UL) | 1U); } else { *((u8 *)(& rateset->mcs) + 4UL) = (unsigned int )*((u8 *)(& rateset->mcs) + 4UL) & 254U; } return; } } bool ldv_queue_work_on_129(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_130(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_131(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_132(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_133(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static unsigned int __arch_hweight32(unsigned int w ) { unsigned int res ; { res = 0U; __asm__ ("661:\n\tcall __sw_hweight32\n662:\n.skip -(((6651f-6641f)-(662b-661b)) > 0) * ((6651f-6641f)-(662b-661b)),0x90\n663:\n.pushsection .altinstructions,\"a\"\n .long 661b - .\n .long 6641f - .\n .word ( 4*32+23)\n .byte 663b-661b\n .byte 6651f-6641f\n .byte 663b-662b\n.popsection\n.pushsection .altinstr_replacement, \"ax\"\n6641:\n\t.byte 0xf3,0x40,0x0f,0xb8,0xc7\n6651:\n\t.popsection": "=a" (res): "D" (w)); return (res); } } __inline static unsigned int __arch_hweight8(unsigned int w ) { unsigned int tmp ; { tmp = __arch_hweight32(w & 255U); return (tmp); } } bool ldv_queue_work_on_143(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_145(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_144(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_147(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_146(struct workqueue_struct *ldv_func_arg1 ) ; bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi ) ; void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih , u8 txchain , u8 rxchain ) ; u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih ) ; void wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi , struct tx_power *power , uint channel ) ; int brcms_c_stf_txchain_set(struct brcms_c_info *wlc , s32 int_val , bool force ) ; bool brcms_c_stf_stbc_rx_set(struct brcms_c_info *wlc , s32 int_val ) ; static u8 const txcore_default[5U] = { 0U, 1U, 3U, 7U, 15U}; static void brcms_c_stf_stbc_rx_ht_update(struct brcms_c_info *wlc , int val ) { { if (((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->band)->phyrev > 3U) && (unsigned int )(wlc->band)->phyrev <= 6U) { if ((unsigned int )(wlc->stf)->rxstreams == 1U && val != 0) { return; } else { } } else { } if ((int )(wlc->pub)->up) { brcms_c_update_beacon(wlc); brcms_c_update_probe_resp(wlc, 1); } else { } return; } } void brcms_c_tempsense_upd(struct brcms_c_info *wlc ) { struct brcms_phy_pub *pi ; uint active_chains ; uint txchain ; u8 tmp ; { pi = (wlc->band)->pi; tmp = wlc_phy_stf_chain_active_get(pi); active_chains = (uint )tmp; txchain = active_chains & 15U; if ((int )(wlc->stf)->txchain == (int )(wlc->stf)->hw_txchain) { if (txchain != 0U && (uint )(wlc->stf)->hw_txchain > txchain) { brcms_c_stf_txchain_set(wlc, (s32 )txchain, 1); } else { } } else if ((int )(wlc->stf)->txchain < (int )(wlc->stf)->hw_txchain) { if ((uint )(wlc->stf)->hw_txchain == txchain) { brcms_c_stf_txchain_set(wlc, (s32 )txchain, 1); } else { } } else { } return; } } void brcms_c_stf_ss_algo_channel_get(struct brcms_c_info *wlc , u16 *ss_algo_channel , u16 chanspec ) { struct tx_power power ; u8 siso_mcs_id ; u8 cdd_mcs_id ; u8 stbc_mcs_id ; { *ss_algo_channel = 0U; if (! (wlc->pub)->up) { *ss_algo_channel = 65535U; return; } else { } wlc_phy_txpower_get_current((wlc->band)->pi, & power, (uint )((unsigned char )chanspec)); siso_mcs_id = ((int )chanspec & 3072) == 3072 ? 68U : 20U; cdd_mcs_id = ((int )chanspec & 3072) == 3072 ? 76U : 28U; stbc_mcs_id = ((int )chanspec & 3072) == 3072 ? 84U : 36U; if ((int )power.target[(int )siso_mcs_id] > (int )power.target[(int )cdd_mcs_id] + 12) { *((u8 *)ss_algo_channel) = (u8 )((unsigned int )*((u8 *)ss_algo_channel) | 1U); } else { *((u8 *)ss_algo_channel) = (u8 )((unsigned int )*((u8 *)ss_algo_channel) | 2U); } if ((int )power.target[(int )siso_mcs_id] <= (int )power.target[(int )stbc_mcs_id] + 12) { *((u8 *)ss_algo_channel) = (u8 )((unsigned int )*((u8 *)ss_algo_channel) | 4U); } else { } return; } } static bool brcms_c_stf_stbc_tx_set(struct brcms_c_info *wlc , s32 int_val ) { { if ((int_val != -1 && int_val != 0) && int_val != 1) { return (0); } else { } if (int_val == 1 && (unsigned int )(wlc->stf)->txstreams == 1U) { return (0); } else { } (wlc->bandstate[0])->band_stf_stbc_tx = (signed char )int_val; (wlc->bandstate[1])->band_stf_stbc_tx = (signed char )int_val; return (1); } } bool brcms_c_stf_stbc_rx_set(struct brcms_c_info *wlc , s32 int_val ) { { if (int_val != 0 && int_val != 1) { return (0); } else { } if (((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->band)->phyrev > 3U) && (unsigned int )(wlc->band)->phyrev <= 6U) { if (int_val != 0 && (unsigned int )(wlc->stf)->rxstreams == 1U) { return (0); } else { } } else { } brcms_c_stf_stbc_rx_ht_update(wlc, int_val); return (1); } } static int brcms_c_stf_txcore_set(struct brcms_c_info *wlc , u8 Nsts , u8 core_mask ) { unsigned int tmp ; unsigned int tmp___0 ; { __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_stf_txcore_set", "wl%d: Nsts %d core_mask %x\n", (wlc->pub)->unit, (int )Nsts, (int )core_mask); tmp = __arch_hweight8((unsigned int )core_mask); if (tmp > (unsigned int )(wlc->stf)->txstreams) { core_mask = 0U; } else { } tmp___0 = __arch_hweight8((unsigned int )core_mask); if (tmp___0 == (unsigned int )(wlc->stf)->txstreams && (((int )core_mask & ~ ((int )(wlc->stf)->txchain)) != 0 || (unsigned int )((int )(wlc->stf)->txchain & (int )core_mask) == 0U)) { core_mask = (wlc->stf)->txchain; } else { } (wlc->stf)->txcore[(int )Nsts] = core_mask; if ((unsigned int )Nsts == 1U) { (wlc->stf)->phytxant = (int )((u16 )core_mask) << 6U; brcms_b_txant_set(wlc->hw, (int )(wlc->stf)->phytxant); if ((int )wlc->clk) { brcms_c_suspend_mac_and_wait(wlc); brcms_c_beacon_phytxctl_txant_upd(wlc, wlc->bcn_rspec); brcms_c_enable_mac(wlc); } else { } } else { } return (0); } } static int brcms_c_stf_spatial_policy_set(struct brcms_c_info *wlc , int val ) { int i ; u8 core_mask ; { core_mask = 0U; __brcms_dbg(& ((wlc->hw)->d11core)->dev, 64U, "brcms_c_stf_spatial_policy_set", "wl%d: val %x\n", (wlc->pub)->unit, val); (wlc->stf)->spatial_policy = (signed char )val; i = 1; goto ldv_55058; ldv_55057: core_mask = val == 1 ? (wlc->stf)->txchain : (u8 )txcore_default[i]; brcms_c_stf_txcore_set(wlc, (int )((unsigned char )i), (int )core_mask); i = i + 1; ldv_55058: ; if (i <= 4) { goto ldv_55057; } else { } return (0); } } static void _brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc ) { s8 txant ; int __ret_warn_on ; long tmp ; { txant = (wlc->stf)->txant; if (((unsigned int )(wlc->band)->phytype == 4U || (unsigned int )(wlc->band)->phytype == 8U) || (unsigned int )(wlc->band)->phytype == 6U) { if ((int )txant == 0) { (wlc->stf)->phytxant = 64U; } else if ((int )txant == 1) { (wlc->stf)->phytxant = 128U; if (((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->band)->phyrev > 2U) && (unsigned int )(wlc->band)->phyrev <= 6U) { (wlc->stf)->phytxant = 256U; } else { } } else if ((unsigned int )(wlc->band)->phytype == 8U || (unsigned int )(wlc->band)->phytype == 6U) { (wlc->stf)->phytxant = 0U; } else { __ret_warn_on = (unsigned int )(wlc->stf)->txchain == 0U; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/stf.c", 247); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); (wlc->stf)->phytxant = (int )((u16 )(wlc->stf)->txchain) << 6U; } } else if ((int )txant == 0) { (wlc->stf)->phytxant = 0U; } else if ((int )txant == 1) { (wlc->stf)->phytxant = 256U; } else { (wlc->stf)->phytxant = 768U; } brcms_b_txant_set(wlc->hw, (int )(wlc->stf)->phytxant); return; } } int brcms_c_stf_txchain_set(struct brcms_c_info *wlc , s32 int_val , bool force ) { u8 txchain ; u8 txstreams ; uint i ; unsigned int tmp ; { txchain = (unsigned char )int_val; if ((int )(wlc->stf)->txchain == (int )txchain) { return (0); } else { } if (((int )txchain & ~ ((int )(wlc->stf)->hw_txchain)) != 0 || (unsigned int )((int )(wlc->stf)->hw_txchain & (int )txchain) == 0U) { return (-22); } else { } tmp = __arch_hweight8((unsigned int )txchain); txstreams = (unsigned char )tmp; if ((unsigned int )txstreams > 4U) { return (-22); } else { } (wlc->stf)->txchain = txchain; (wlc->stf)->txstreams = txstreams; brcms_c_stf_stbc_tx_set(wlc, (s32 )(wlc->band)->band_stf_stbc_tx); brcms_c_stf_ss_update(wlc, wlc->bandstate[0]); brcms_c_stf_ss_update(wlc, wlc->bandstate[1]); (wlc->stf)->txant = (unsigned int )(wlc->stf)->txstreams == 1U ? 0 : 3; _brcms_c_stf_phy_txant_upd(wlc); wlc_phy_stf_chain_set((wlc->band)->pi, (int )(wlc->stf)->txchain, (int )(wlc->stf)->rxchain); i = 1U; goto ldv_55075; ldv_55074: brcms_c_stf_txcore_set(wlc, (int )((unsigned char )i), (int )txcore_default[i]); i = i + 1U; ldv_55075: ; if (i <= 4U) { goto ldv_55074; } else { } return (0); } } int brcms_c_stf_ss_update(struct brcms_c_info *wlc , struct brcms_band *band ) { int ret_code ; u8 prev_stf_ss ; u8 upd_stf_ss ; { ret_code = 0; prev_stf_ss = (wlc->stf)->ss_opmode; if ((((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->band)->phyrev > 2U) && (int )(wlc->stf)->ss_algosel_auto) && (unsigned int )(wlc->stf)->ss_algo_channel != 65535U) { upd_stf_ss = (u8 )((unsigned int )(wlc->stf)->txstreams != 1U && ((int )*((u8 const *)(& (wlc->stf)->ss_algo_channel)) & 1) == 0); } else { if ((unsigned long )wlc->band != (unsigned long )band) { return (ret_code); } else { } upd_stf_ss = (unsigned int )(wlc->stf)->txstreams != 1U ? band->band_stf_ss_mode : 0U; } if ((int )prev_stf_ss != (int )upd_stf_ss) { (wlc->stf)->ss_opmode = upd_stf_ss; brcms_b_band_stf_ss_set(wlc->hw, (int )upd_stf_ss); } else { } return (ret_code); } } int brcms_c_stf_attach(struct brcms_c_info *wlc ) { bool tmp ; int tmp___0 ; { (wlc->bandstate[0])->band_stf_ss_mode = 0U; (wlc->bandstate[1])->band_stf_ss_mode = 1U; if ((unsigned int )(wlc->band)->phytype == 4U) { tmp = wlc_phy_txpower_hw_ctrl_get((wlc->band)->pi); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { (wlc->bandstate[0])->band_stf_ss_mode = 1U; } else { } } else { } brcms_c_stf_ss_update(wlc, wlc->bandstate[0]); brcms_c_stf_ss_update(wlc, wlc->bandstate[1]); brcms_c_stf_stbc_rx_ht_update(wlc, 0); (wlc->bandstate[0])->band_stf_stbc_tx = 0; (wlc->bandstate[1])->band_stf_stbc_tx = 0; if ((unsigned int )(wlc->band)->phytype == 4U && (unsigned int )(wlc->band)->phyrev > 2U) { (wlc->stf)->ss_algosel_auto = 1; (wlc->stf)->ss_algo_channel = 65535U; } else { } return (0); } } void brcms_c_stf_detach(struct brcms_c_info *wlc ) { { return; } } void brcms_c_stf_phy_txant_upd(struct brcms_c_info *wlc ) { { _brcms_c_stf_phy_txant_upd(wlc); return; } } void brcms_c_stf_phy_chain_calc(struct brcms_c_info *wlc ) { struct ssb_sprom *sprom ; unsigned int tmp ; unsigned int tmp___0 ; { sprom = & (((wlc->hw)->d11core)->bus)->sprom; (wlc->stf)->hw_txchain = sprom->txchain; (wlc->stf)->hw_rxchain = sprom->rxchain; if ((unsigned int )(wlc->stf)->hw_txchain == 0U || (unsigned int )(wlc->stf)->hw_txchain == 15U) { if ((unsigned int )(wlc->band)->phytype == 4U) { (wlc->stf)->hw_txchain = 3U; } else { (wlc->stf)->hw_txchain = 1U; } } else { } (wlc->stf)->txchain = (wlc->stf)->hw_txchain; tmp = __arch_hweight8((unsigned int )(wlc->stf)->hw_txchain); (wlc->stf)->txstreams = (unsigned char )tmp; if ((unsigned int )(wlc->stf)->hw_rxchain == 0U || (unsigned int )(wlc->stf)->hw_rxchain == 15U) { if ((unsigned int )(wlc->band)->phytype == 4U) { (wlc->stf)->hw_rxchain = 3U; } else { (wlc->stf)->hw_rxchain = 1U; } } else { } (wlc->stf)->rxchain = (wlc->stf)->hw_rxchain; tmp___0 = __arch_hweight8((unsigned int )(wlc->stf)->hw_rxchain); (wlc->stf)->rxstreams = (unsigned char )tmp___0; memcpy((void *)(& (wlc->stf)->txcore), (void const *)(& txcore_default), 5UL); (wlc->stf)->spatial_policy = 0; brcms_c_stf_spatial_policy_set(wlc, 0); return; } } static u16 _brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc , u32 rspec ) { u16 phytxant ; uint tmp ; { phytxant = (wlc->stf)->phytxant; tmp = rspec_stf(rspec); if (tmp != 0U) { phytxant = (int )((u16 )(wlc->stf)->txchain) << 6U; } else if ((int )(wlc->stf)->txant == 3) { phytxant = (int )((u16 )(wlc->stf)->txchain) << 6U; } else { } phytxant = (unsigned int )phytxant & 960U; return (phytxant); } } u16 brcms_c_stf_phytxchain_sel(struct brcms_c_info *wlc , u32 rspec ) { u16 tmp ; { tmp = _brcms_c_stf_phytxchain_sel(wlc, rspec); return (tmp); } } u16 brcms_c_stf_d11hdrs_phyctl_txant(struct brcms_c_info *wlc , u32 rspec ) { u16 phytxant ; u16 mask ; { phytxant = (wlc->stf)->phytxant; mask = 960U; if ((unsigned int )(wlc->band)->phytype == 4U) { phytxant = _brcms_c_stf_phytxchain_sel(wlc, rspec); mask = 16320U; } else { } phytxant = phytxant; return (phytxant); } } bool ldv_queue_work_on_143(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_144(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_145(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_146(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_147(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_157(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_159(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_158(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_161(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_160(struct workqueue_struct *ldv_func_arg1 ) ; extern int pci_bus_read_config_dword(struct pci_bus * , unsigned int , int , u32 * ) ; __inline static int pci_read_config_dword(struct pci_dev const *dev , int where , u32 *val ) { int tmp ; { tmp = pci_bus_read_config_dword(dev->bus, dev->devfn, where, val); return (tmp); } } __inline static void bcma_maskset32(struct bcma_device *cc , u16 offset , u32 mask , u32 set ) { u32 tmp ; { tmp = bcma_read32(cc, (int )offset); bcma_write32(cc, (int )offset, (tmp & mask) | set); return; } } extern void bcma_core_set_clockmode(struct bcma_device * , enum bcma_clkmode ) ; static bool ai_buscore_setup(struct si_info *sii , struct bcma_device *cc ) { u32 tmp ; { if ((unsigned int )(cc->bus)->nr_cores == 0U) { return (0); } else { } sii->pub.ccrev = (int )cc->id.rev; sii->chipst = bcma_read32(cc, 44); sii->pub.cccaps = bcma_read32(cc, 4); tmp = ai_get_cccaps(& sii->pub); if ((tmp & 268435456U) != 0U) { sii->pub.pmucaps = bcma_read32(cc, 1540); sii->pub.pmurev = (int )sii->pub.pmucaps & 255; } else { } return (1); } } static struct si_info *ai_doattach(struct si_info *sii , struct bcma_bus *pbus ) { struct si_pub *sih ; struct bcma_device *cc ; bool tmp ; int tmp___0 ; u32 tmp___1 ; { sih = & sii->pub; sii->icbus = pbus; sii->pcibus = pbus->__annonCompField98.host_pci; cc = pbus->drv_cc.core; sih->chip = (uint )pbus->chipinfo.id; sih->chiprev = (uint )pbus->chipinfo.rev; sih->chippkg = (uint )pbus->chipinfo.pkg; sih->boardvendor = (uint )pbus->boardinfo.vendor; sih->boardtype = (uint )pbus->boardinfo.type; tmp = ai_buscore_setup(sii, cc); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { goto exit; } else { } bcma_write32(cc, 88, 0U); bcma_write32(cc, 92, 0U); tmp___1 = ai_get_cccaps(sih); if ((tmp___1 & 268435456U) != 0U) { si_pmu_measure_alpclk(sih); } else { } return (sii); exit: ; return ((struct si_info *)0); } } struct si_pub *ai_attach(struct bcma_bus *pbus ) { struct si_info *sii ; void *tmp ; struct si_info *tmp___0 ; { tmp = kzalloc(64UL, 32U); sii = (struct si_info *)tmp; if ((unsigned long )sii == (unsigned long )((struct si_info *)0)) { return ((struct si_pub *)0); } else { } tmp___0 = ai_doattach(sii, pbus); if ((unsigned long )tmp___0 == (unsigned long )((struct si_info *)0)) { kfree((void const *)sii); return ((struct si_pub *)0); } else { } return ((struct si_pub *)sii); } } void ai_detach(struct si_pub *sih ) { struct si_info *sii ; struct si_pub const *__mptr ; { __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; if ((unsigned long )sii == (unsigned long )((struct si_info *)0)) { return; } else { } kfree((void const *)sii); return; } } uint ai_cc_reg(struct si_pub *sih , uint regoff , u32 mask , u32 val ) { struct bcma_device *cc ; u32 w ; struct si_info *sii ; struct si_pub const *__mptr ; { __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; cc = (sii->icbus)->drv_cc.core; if (mask != 0U || val != 0U) { bcma_maskset32(cc, (int )((u16 )regoff), ~ mask, val); } else { } w = bcma_read32(cc, (int )((u16 )regoff)); return (w); } } static uint ai_slowclk_src(struct si_pub *sih , struct bcma_device *cc ) { { return (1U); } } static uint ai_slowclk_freq(struct si_pub *sih , bool max_freq , struct bcma_device *cc ) { uint div ; { div = bcma_read32(cc, 192); div = ((div >> 16) + 1U) * 4U; return ((int )max_freq ? 20200000U : 19800000U / div); } } static void ai_clkctl_setdelay(struct si_pub *sih , struct bcma_device *cc ) { uint slowmaxfreq ; uint pll_delay ; uint slowclk ; uint pll_on_delay ; uint fref_sel_delay ; { pll_delay = 150U; slowclk = ai_slowclk_src(sih, cc); if (slowclk != 1U) { pll_delay = pll_delay + 1000U; } else { } slowmaxfreq = ai_slowclk_freq(sih, 0, cc); pll_on_delay = (slowmaxfreq * pll_delay + 999999U) / 1000000U; fref_sel_delay = (slowmaxfreq * 200U + 999999U) / 1000000U; bcma_write32(cc, 176, pll_on_delay); bcma_write32(cc, 180, fref_sel_delay); return; } } void ai_clkctl_init(struct si_pub *sih ) { struct si_info *sii ; struct si_pub const *__mptr ; struct bcma_device *cc ; u32 tmp ; { __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; tmp = ai_get_cccaps(sih); if ((tmp & 262144U) == 0U) { return; } else { } cc = (sii->icbus)->drv_cc.core; if ((unsigned long )cc == (unsigned long )((struct bcma_device *)0)) { return; } else { } bcma_maskset32(cc, 192, 4294901760U, 262144U); ai_clkctl_setdelay(sih, cc); return; } } u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih ) { struct si_info *sii ; struct bcma_device *cc ; uint slowminfreq ; u16 fpdelay ; struct si_pub const *__mptr ; u32 tmp ; u32 tmp___0 ; u32 tmp___1 ; { __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; tmp = ai_get_cccaps(sih); if ((tmp & 268435456U) != 0U) { fpdelay = si_pmu_fast_pwrup_delay(sih); return (fpdelay); } else { } tmp___0 = ai_get_cccaps(sih); if ((tmp___0 & 262144U) == 0U) { return (0U); } else { } fpdelay = 0U; cc = (sii->icbus)->drv_cc.core; if ((unsigned long )cc != (unsigned long )((struct bcma_device *)0)) { slowminfreq = ai_slowclk_freq(sih, 0, cc); tmp___1 = bcma_read32(cc, 176); fpdelay = (u16 )(((tmp___1 * 1000000U + slowminfreq) + 1999999U) / slowminfreq); } else { } return (fpdelay); } } bool ai_clkctl_cc(struct si_pub *sih , enum bcma_clkmode mode ) { struct si_info *sii ; struct bcma_device *cc ; struct si_pub const *__mptr ; { __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; cc = (sii->icbus)->drv_cc.core; bcma_core_set_clockmode(cc, mode); return ((unsigned int )mode == 0U); } } void ai_epa_4313war(struct si_pub *sih ) { struct si_info *sii ; struct si_pub const *__mptr ; struct bcma_device *cc ; { __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; cc = (sii->icbus)->drv_cc.core; bcma_set32(cc, 108, 64U); return; } } bool ai_deviceremoved(struct si_pub *sih ) { u32 w ; struct si_info *sii ; struct si_pub const *__mptr ; { w = 0U; __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; if ((unsigned int )(sii->icbus)->hosttype != 0U) { return (0); } else { } pci_read_config_dword((struct pci_dev const *)sii->pcibus, 0, & w); if ((w & 65535U) != 5348U) { return (1); } else { } return (0); } } bool ldv_queue_work_on_157(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_158(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_159(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_160(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_161(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static int fls(int x ) { int r ; { __asm__ ("bsrl %1,%0": "=r" (r): "rm" (x), "0" (-1)); return (r + 1); } } bool ldv_queue_work_on_171(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_173(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_172(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_175(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_174(struct workqueue_struct *ldv_func_arg1 ) ; extern u32 bcma_chipco_gpio_out(struct bcma_drv_cc * , u32 , u32 ) ; extern u32 bcma_chipco_gpio_outen(struct bcma_drv_cc * , u32 , u32 ) ; __inline static void bcma_maskset16(struct bcma_device *cc , u16 offset , u16 mask , u16 set ) { u32 tmp ; { tmp = bcma_read16(cc, (int )offset); bcma_write16(cc, (int )offset, (tmp & (u32 )mask) | (u32 )set); return; } } __inline static int lower_20_sb(int channel ) { { return (channel > 2 ? channel + -2 : 0); } } __inline static int upper_20_sb(int channel ) { { return (channel <= 221 ? channel + 2 : 0); } } u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi ) ; void wlc_phy_set_deaf(struct brcms_phy_pub *ppi , bool user_flag ) ; void wlc_phy_BSSinit(struct brcms_phy_pub *pih , bool bonlyap , int rssi ) ; u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi , uint band ) ; void wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi , uint channel , u8 *min_pwr , u8 *max_pwr , int txp_rate_idx ) ; void wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi , uint chan , u8 *max_txpwr , u8 *min_txpwr ) ; void wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi , uint bandunit , s32 *max_pwr , s32 *min_pwr , u32 *step_pwr ) ; void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi , struct txpwr_limits *txpwr ) ; void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi , bool hwpwrctrl ) ; u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi ) ; u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi ) ; bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *ppi ) ; void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih , u8 *txchain , u8 *rxchain ) ; s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih , u16 chanspec ) ; void wlc_phy_cal_perical(struct brcms_phy_pub *pih , u8 reason ) ; void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *pih ) ; void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih , bool lock ) ; void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi , u8 val ) ; void wlc_phy_clear_tssi(struct brcms_phy_pub *pih ) ; bool wlc_phy_test_ison(struct brcms_phy_pub *ppi ) ; void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi , u8 txpwr_percent ) ; void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih , bool bf_preempt ) ; void wlc_phy_runbist_config(struct brcms_phy_pub *ppi , bool start_end ) ; void wlc_phy_freqtrack_start(struct brcms_phy_pub *pih ) ; void wlc_phy_freqtrack_end(struct brcms_phy_pub *pih ) ; u16 read_phy_reg(struct brcms_phy *pi , u16 addr ) ; void write_phy_reg(struct brcms_phy *pi , u16 addr , u16 val ) ; void and_phy_reg(struct brcms_phy *pi , u16 addr , u16 val ) ; void or_phy_reg(struct brcms_phy *pi , u16 addr , u16 val ) ; void mod_phy_reg(struct brcms_phy *pi , u16 addr , u16 mask , u16 val ) ; u16 read_radio_reg(struct brcms_phy *pi , u16 addr ) ; void or_radio_reg(struct brcms_phy *pi , u16 addr , u16 val ) ; void and_radio_reg(struct brcms_phy *pi , u16 addr , u16 val ) ; void mod_radio_reg(struct brcms_phy *pi , u16 addr , u16 mask , u16 val ) ; void xor_radio_reg(struct brcms_phy *pi , u16 addr , u16 mask ) ; void write_radio_reg(struct brcms_phy *pi , u16 addr , u16 val ) ; void wlc_phyreg_enter(struct brcms_phy_pub *pih ) ; void wlc_phyreg_exit(struct brcms_phy_pub *pih ) ; void wlc_radioreg_enter(struct brcms_phy_pub *pih ) ; void wlc_radioreg_exit(struct brcms_phy_pub *pih ) ; void wlc_phy_read_table(struct brcms_phy *pi , struct phytbl_info const *ptbl_info , u16 tblAddr , u16 tblDataHi , u16 tblDataLo ) ; void wlc_phy_write_table(struct brcms_phy *pi , struct phytbl_info const *ptbl_info , u16 tblAddr , u16 tblDataHi , u16 tblDataLo ) ; void wlc_phy_table_addr(struct brcms_phy *pi , uint tbl_id , uint tbl_offset , u16 tblAddr , u16 tblDataHi , u16 tblDataLo ) ; void wlc_phy_table_data_write(struct brcms_phy *pi , uint width , u32 val ) ; void write_phy_channel_reg(struct brcms_phy *pi , uint val ) ; void wlc_phy_txpower_update_shm(struct brcms_phy *pi ) ; u8 wlc_phy_nbits(s32 value ) ; void wlc_phy_compute_dB(u32 *cmplx_pwr , s8 *p_cmplx_pwr_dB , u8 core ) ; uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi , struct radio_20xx_regs *radioregs ) ; uint wlc_phy_init_radio_regs(struct brcms_phy *pi , struct radio_regs const *radioregs , u16 core_offset ) ; void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi ) ; void wlc_phy_do_dummy_tx(struct brcms_phy *pi , bool ofdm , bool pa_on ) ; void wlc_phy_papd_decode_epsilon(u32 epsilon , s32 *eps_real , s32 *eps_imag ) ; void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi ) ; void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi ) ; bool wlc_phy_attach_nphy(struct brcms_phy *pi ) ; bool wlc_phy_attach_lcnphy(struct brcms_phy *pi ) ; int wlc_phy_channel2freq(uint channel ) ; int wlc_phy_chanspec_freq2bandrange_lpssn(uint freq ) ; int wlc_phy_chanspec_bandrange_get(struct brcms_phy *pi , u16 chanspec ) ; void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi , uint chan , u8 *max_pwr , u8 txp_rate_idx ) ; void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power , u8 rate_mcs_start , u8 rate_mcs_end , u8 rate_ofdm_start ) ; void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power , u8 rate_ofdm_start , u8 rate_ofdm_end , u8 rate_mcs_start ) ; s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi , bool mode ) ; s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi , bool mode ) ; void wlc_lcnphy_epa_switch(struct brcms_phy *pi , bool mode ) ; void wlc_phy_txpower_recalc_target(struct brcms_phy *pi ) ; void wlc_lcnphy_calib_modes(struct brcms_phy *pi , uint mode ) ; void wlc_lcnphy_deaf_mode(struct brcms_phy *pi , bool mode ) ; bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi ) ; void wlc_lcnphy_get_tssi(struct brcms_phy *pi , s8 *ofdm_pwr , s8 *cck_pwr ) ; s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi , s32 gain_index ) ; void wlc_nphy_deaf_mode(struct brcms_phy *pi , bool mode ) ; void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi , u8 caltype ) ; void wlc_phy_pa_override_nphy(struct brcms_phy *pi , bool en ) ; u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi , uint channel ) ; void wlc_phy_switch_radio_nphy(struct brcms_phy *pi , bool on ) ; s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi ) ; u16 wlc_phy_classifier_nphy(struct brcms_phy *pi , u16 mask , u16 val ) ; void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi , struct phy_iq_est *est , u16 num_samps , u8 wait_time , u8 wait_for_crs ) ; void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih , u8 rxcore_bitmask ) ; void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi , u8 ctrl_type ) ; void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi ) ; void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi ) ; int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi , struct d11rxhdr *rxh ) ; void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi , s8 *cckoffset , s8 *ofdmoffset ) ; s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi , s8 rssi , u16 chanspec ) ; bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pi ) ; static struct chan_info_basic const chan_info_all[51U] = { {1U, 2412U}, {2U, 2417U}, {3U, 2422U}, {4U, 2427U}, {5U, 2432U}, {6U, 2437U}, {7U, 2442U}, {8U, 2447U}, {9U, 2452U}, {10U, 2457U}, {11U, 2462U}, {12U, 2467U}, {13U, 2472U}, {14U, 2484U}, {34U, 5170U}, {38U, 5190U}, {42U, 5210U}, {46U, 5230U}, {36U, 5180U}, {40U, 5200U}, {44U, 5220U}, {48U, 5240U}, {52U, 5260U}, {56U, 5280U}, {60U, 5300U}, {64U, 5320U}, {100U, 5500U}, {104U, 5520U}, {108U, 5540U}, {112U, 5560U}, {116U, 5580U}, {120U, 5600U}, {124U, 5620U}, {128U, 5640U}, {132U, 5660U}, {136U, 5680U}, {140U, 5700U}, {149U, 5745U}, {153U, 5765U}, {157U, 5785U}, {161U, 5805U}, {165U, 5825U}, {184U, 4920U}, {188U, 4940U}, {192U, 4960U}, {196U, 4980U}, {200U, 5000U}, {204U, 5020U}, {208U, 5040U}, {212U, 5060U}, {216U, 5080U}}; static u8 const ofdm_rate_lookup[8U] = { 96U, 48U, 24U, 12U, 108U, 72U, 36U, 18U}; void wlc_phyreg_enter(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; wlapi_bmac_ucode_wake_override_phyreg_set((pi->sh)->physhim); return; } } void wlc_phyreg_exit(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; wlapi_bmac_ucode_wake_override_phyreg_clear((pi->sh)->physhim); return; } } void wlc_radioreg_enter(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; wlapi_bmac_mctrl((pi->sh)->physhim, 524288U, 524288U); __const_udelay(42950UL); return; } } void wlc_radioreg_exit(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; bcma_read16(pi->d11core, 992); pi->phy_wreg = 0U; wlapi_bmac_mctrl((pi->sh)->physhim, 524288U, 0U); return; } } u16 read_radio_reg(struct brcms_phy *pi , u16 addr ) { u16 data ; u32 tmp ; u32 tmp___0 ; { if ((unsigned int )addr == 1U) { return (65535U); } else { } switch (pi->pubpi.phy_type) { case 4U: ; if (pi->pubpi.phy_rev > 6U) { addr = (u16 )((unsigned int )addr | 512U); } else { addr = (u16 )((unsigned int )addr | 256U); } goto ldv_37296; case 8U: addr = (u16 )((unsigned int )addr | 512U); goto ldv_37296; default: ; goto ldv_37296; } ldv_37296: ; if ((pi->sh)->corerev > 23U || ((pi->sh)->corerev == 22U && pi->pubpi.phy_type != 6U)) { bcma_write16(pi->d11core, 984, (u32 )addr); tmp = bcma_read16(pi->d11core, 986); data = (u16 )tmp; } else { bcma_write16(pi->d11core, 1014, (u32 )addr); tmp___0 = bcma_read16(pi->d11core, 1018); data = (u16 )tmp___0; } pi->phy_wreg = 0U; return (data); } } void write_radio_reg(struct brcms_phy *pi , u16 addr , u16 val ) { { if ((pi->sh)->corerev > 23U || ((pi->sh)->corerev == 22U && pi->pubpi.phy_type != 6U)) { bcma_write16(pi->d11core, 984, (u32 )addr); bcma_write16(pi->d11core, 986, (u32 )val); } else { bcma_write16(pi->d11core, 1014, (u32 )addr); bcma_write16(pi->d11core, 1018, (u32 )val); } if ((unsigned int )((pi->d11core)->bus)->hosttype == 0U) { pi->phy_wreg = (u16 )((int )pi->phy_wreg + 1); if ((int )pi->phy_wreg >= (int )pi->phy_wreg_limit) { bcma_read32(pi->d11core, 288); pi->phy_wreg = 0U; } else { } } else { } return; } } static u32 read_radio_id(struct brcms_phy *pi ) { u32 id ; u32 b0 ; u32 b1 ; u32 b2 ; u32 tmp ; { if ((pi->sh)->corerev > 23U) { bcma_write16(pi->d11core, 984, 0U); b0 = bcma_read16(pi->d11core, 986); bcma_write16(pi->d11core, 984, 1U); b1 = bcma_read16(pi->d11core, 986); bcma_write16(pi->d11core, 984, 2U); b2 = bcma_read16(pi->d11core, 986); id = ((b0 << 28) | (((b2 << 8) | b1) << 12)) | ((b0 >> 4) & 15U); } else { bcma_write16(pi->d11core, 1014, 1U); id = bcma_read16(pi->d11core, 1018); tmp = bcma_read16(pi->d11core, 1016); id = (tmp << 16) | id; } pi->phy_wreg = 0U; return (id); } } void and_radio_reg(struct brcms_phy *pi , u16 addr , u16 val ) { u16 rval ; { rval = read_radio_reg(pi, (int )addr); write_radio_reg(pi, (int )addr, (int )rval & (int )val); return; } } void or_radio_reg(struct brcms_phy *pi , u16 addr , u16 val ) { u16 rval ; { rval = read_radio_reg(pi, (int )addr); write_radio_reg(pi, (int )addr, (int )rval | (int )val); return; } } void xor_radio_reg(struct brcms_phy *pi , u16 addr , u16 mask ) { u16 rval ; { rval = read_radio_reg(pi, (int )addr); write_radio_reg(pi, (int )addr, (int )rval ^ (int )mask); return; } } void mod_radio_reg(struct brcms_phy *pi , u16 addr , u16 mask , u16 val ) { u16 rval ; { rval = read_radio_reg(pi, (int )addr); write_radio_reg(pi, (int )addr, (int )((u16 )((~ ((int )((short )mask)) & (int )((short )rval)) | (int )((short )((int )val & (int )mask))))); return; } } void write_phy_channel_reg(struct brcms_phy *pi , uint val ) { { bcma_write16(pi->d11core, 1008, val); return; } } u16 read_phy_reg(struct brcms_phy *pi , u16 addr ) { u32 tmp ; { bcma_write16(pi->d11core, 1020, (u32 )addr); pi->phy_wreg = 0U; tmp = bcma_read16(pi->d11core, 1022); return ((u16 )tmp); } } void write_phy_reg(struct brcms_phy *pi , u16 addr , u16 val ) { { bcma_write32(pi->d11core, 1020, (u32 )((int )addr | ((int )val << 16))); if ((unsigned int )((pi->d11core)->bus)->hosttype == 0U) { pi->phy_wreg = (u16 )((int )pi->phy_wreg + 1); if ((int )pi->phy_wreg >= (int )pi->phy_wreg_limit) { pi->phy_wreg = 0U; bcma_read16(pi->d11core, 992); } else { } } else { } return; } } void and_phy_reg(struct brcms_phy *pi , u16 addr , u16 val ) { { bcma_write16(pi->d11core, 1020, (u32 )addr); bcma_mask16(pi->d11core, 1022, (int )val); pi->phy_wreg = 0U; return; } } void or_phy_reg(struct brcms_phy *pi , u16 addr , u16 val ) { { bcma_write16(pi->d11core, 1020, (u32 )addr); bcma_set16(pi->d11core, 1022, (int )val); pi->phy_wreg = 0U; return; } } void mod_phy_reg(struct brcms_phy *pi , u16 addr , u16 mask , u16 val ) { { val = (u16 )((int )val & (int )mask); bcma_write16(pi->d11core, 1020, (u32 )addr); bcma_maskset16(pi->d11core, 1022, ~ ((int )mask), (int )val); pi->phy_wreg = 0U; return; } } static void wlc_set_phy_uninitted(struct brcms_phy *pi ) { int i ; int j ; { pi->initialized = 0; pi->tx_vos = 65535U; pi->nrssi_table_delta = 2147483647; pi->rc_cal = 65535U; pi->mintxbias = 65535U; pi->txpwridx = -1; if (pi->pubpi.phy_type == 4U) { pi->phy_spuravoid = 0U; if (pi->pubpi.phy_rev > 2U && pi->pubpi.phy_rev <= 6U) { pi->phy_spuravoid = 1U; } else { } pi->nphy_papd_skip = 0U; pi->nphy_papd_epsilon_offset[0] = -2680; pi->nphy_papd_epsilon_offset[1] = -2680; pi->nphy_txpwr_idx[0] = 128U; pi->nphy_txpwr_idx[1] = 128U; pi->nphy_txpwrindex[0].index_internal = 40; pi->nphy_txpwrindex[1].index_internal = 40; pi->phy_pabias = 0U; } else { pi->phy_spuravoid = 1U; } pi->radiopwr = 65535U; i = 0; goto ldv_37374; ldv_37373: j = 0; goto ldv_37371; ldv_37370: pi->stats_11b_txpower[i][j] = -1; j = j + 1; ldv_37371: ; if (j <= 8) { goto ldv_37370; } else { } i = i + 1; ldv_37374: ; if (i <= 31) { goto ldv_37373; } else { } return; } } struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp ) { struct shared_phy *sh ; void *tmp ; { tmp = kzalloc(112UL, 32U); sh = (struct shared_phy *)tmp; if ((unsigned long )sh == (unsigned long )((struct shared_phy *)0)) { return ((struct shared_phy *)0); } else { } sh->physhim = shp->physhim; sh->unit = shp->unit; sh->corerev = shp->corerev; sh->vid = shp->vid; sh->did = shp->did; sh->chip = shp->chip; sh->chiprev = shp->chiprev; sh->chippkg = shp->chippkg; sh->sromrev = shp->sromrev; sh->boardtype = shp->boardtype; sh->boardrev = shp->boardrev; sh->boardflags = shp->boardflags; sh->boardflags2 = shp->boardflags2; sh->fast_timer = 15U; sh->slow_timer = 60U; sh->glacial_timer = 120U; sh->rssi_mode = 0U; return (sh); } } static void wlc_phy_timercb_phycal(struct brcms_phy *pi ) { uint delay ; { delay = 5U; if ((unsigned int )pi->mphase_cal_phase_id != 0U) { if (! (pi->sh)->up) { wlc_phy_cal_perical_mphase_reset(pi); return; } else { } if ((pi->measure_hold & 6U) != 0U || (pi->measure_hold & 8U) != 0U) { delay = 1000U; wlc_phy_cal_perical_mphase_restart(pi); } else { wlc_phy_cal_perical_nphy_run(pi, 0); } wlapi_add_timer(pi->phycal_timer, delay, 0); return; } else { } return; } } static u32 wlc_phy_get_radio_ver(struct brcms_phy *pi ) { u32 ver ; { ver = read_radio_id(pi); return (ver); } } struct brcms_phy_pub *wlc_phy_attach(struct shared_phy *sh , struct bcma_device *d11core , int bandtype , struct wiphy *wiphy ) { struct brcms_phy *pi ; u32 sflags ; uint phyversion ; u32 idcode ; int i ; void *tmp ; u16 tmp___0 ; u16 tmp___1 ; bool tmp___2 ; int tmp___3 ; bool tmp___4 ; int tmp___5 ; { sflags = 0U; if (sh->corerev == 4U) { sflags = 3U; } else { sflags = bcma_aread32(d11core, 1280); } if (bandtype == 1) { if ((sflags & 10U) == 0U) { return ((struct brcms_phy_pub *)0); } else { } } else { } pi = sh->phy_head; if ((sflags & 8U) != 0U && (unsigned long )pi != (unsigned long )((struct brcms_phy *)0)) { wlapi_bmac_corereset((pi->sh)->physhim, pi->pubpi.coreflags); pi->refcnt = pi->refcnt + 1U; return (& pi->pubpi_ro); } else { } tmp = kzalloc(3512UL, 32U); pi = (struct brcms_phy *)tmp; if ((unsigned long )pi == (unsigned long )((struct brcms_phy *)0)) { return ((struct brcms_phy_pub *)0); } else { } pi->wiphy = wiphy; pi->d11core = d11core; pi->sh = sh; pi->phy_init_por = 1; pi->phy_wreg_limit = 24U; pi->txpwr_percent = 100U; pi->do_initcal = 1; pi->phycal_tempdelta = 0U; if (bandtype == 2 && (int )sflags & 1) { pi->pubpi.coreflags = 8192U; } else { } wlapi_bmac_corereset((pi->sh)->physhim, pi->pubpi.coreflags); phyversion = bcma_read16(pi->d11core, 992); pi->pubpi.phy_type = (phyversion & 3840U) >> 8; pi->pubpi.phy_rev = phyversion & 15U; if (pi->pubpi.phy_type == 9U) { pi->pubpi.phy_type = 4U; pi->pubpi.phy_rev = pi->pubpi.phy_rev + 16U; } else { } pi->pubpi.phy_corenum = 2U; pi->pubpi.ana_rev = (phyversion & 61440U) >> 12; if (pi->pubpi.phy_type != 4U && pi->pubpi.phy_type != 8U) { goto err; } else { } if (bandtype == 1) { if (pi->pubpi.phy_type != 4U) { goto err; } else { } } else if (pi->pubpi.phy_type != 4U && pi->pubpi.phy_type != 8U) { goto err; } else { } wlc_phy_anacore((struct brcms_phy_pub *)pi, 1); idcode = wlc_phy_get_radio_ver(pi); pi->pubpi.radioid = (u16 )((idcode & 268431360U) >> 12); pi->pubpi.radiorev = (u8 )(idcode >> 28); pi->pubpi.radiover = (unsigned int )((u8 )idcode) & 15U; if ((pi->pubpi.phy_type != 4U || (((unsigned int )pi->pubpi.radioid != 8277U && (unsigned int )pi->pubpi.radioid != 8278U) && (unsigned int )pi->pubpi.radioid != 8279U)) && (pi->pubpi.phy_type != 8U || (unsigned int )pi->pubpi.radioid != 8292U)) { goto err; } else { } wlc_phy_switch_radio((struct brcms_phy_pub *)pi, 0); wlc_set_phy_uninitted(pi); pi->bw = 2048U; if (bandtype == 2) { tmp___0 = ch20mhz_chspec(1); pi->radio_chanspec = tmp___0; } else { tmp___1 = ch20mhz_chspec(36); pi->radio_chanspec = tmp___1; } pi->rxiq_samps = 10U; pi->rxiq_antsel = 3U; pi->watchdog_override = 1; pi->cal_type_override = 0U; pi->nphy_saved_noisevars.bufcount = 0; if (pi->pubpi.phy_type == 4U) { pi->min_txpower = 8U; } else { pi->min_txpower = 10U; } (pi->sh)->phyrxchain = 3U; pi->rx2tx_biasentry = -1; pi->phy_txcore_disable_temp = 115; pi->phy_txcore_enable_temp = 110; pi->phy_tempsense_offset = 0; pi->phy_txcore_heatedup = 0; pi->nphy_lastcal_temp = -50; pi->phynoise_polling = 1; if (pi->pubpi.phy_type == 4U || pi->pubpi.phy_type == 8U) { pi->phynoise_polling = 0; } else { } i = 0; goto ldv_37401; ldv_37400: pi->txpwr_limit[i] = 127U; pi->txpwr_env_limit[i] = 127U; pi->tx_user_target[i] = 127U; i = i + 1; ldv_37401: ; if (i <= 100) { goto ldv_37400; } else { } pi->radiopwr_override = -1; pi->user_txpwr_at_rfport = 0; if (pi->pubpi.phy_type == 4U) { pi->phycal_timer = wlapi_init_timer((pi->sh)->physhim, & wlc_phy_timercb_phycal, (void *)pi, "phycal"); if ((unsigned long )pi->phycal_timer == (unsigned long )((struct wlapi_timer *)0)) { goto err; } else { } tmp___2 = wlc_phy_attach_nphy(pi); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { goto err; } else { } } else if (pi->pubpi.phy_type == 8U) { tmp___4 = wlc_phy_attach_lcnphy(pi); if (tmp___4) { tmp___5 = 0; } else { tmp___5 = 1; } if (tmp___5) { goto err; } else { } } else { } pi->refcnt = pi->refcnt + 1U; pi->next = (pi->sh)->phy_head; sh->phy_head = pi; memcpy((void *)(& pi->pubpi_ro), (void const *)(& pi->pubpi), 28UL); return (& pi->pubpi_ro); err: kfree((void const *)pi); return ((struct brcms_phy_pub *)0); } } void wlc_phy_detach(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if ((unsigned long )pih != (unsigned long )((struct brcms_phy_pub *)0)) { pi->refcnt = pi->refcnt - 1U; if (pi->refcnt != 0U) { return; } else { } if ((unsigned long )pi->phycal_timer != (unsigned long )((struct wlapi_timer *)0)) { wlapi_free_timer(pi->phycal_timer); pi->phycal_timer = (struct wlapi_timer *)0; } else { } if ((unsigned long )(pi->sh)->phy_head == (unsigned long )pi) { (pi->sh)->phy_head = pi->next; } else if ((unsigned long )((pi->sh)->phy_head)->next == (unsigned long )pi) { ((pi->sh)->phy_head)->next = (struct brcms_phy *)0; } else { } if ((unsigned long )pi->pi_fptr.detach != (unsigned long )((void (*)(struct brcms_phy * ))0)) { (*(pi->pi_fptr.detach))(pi); } else { } kfree((void const *)pi); } else { } return; } } bool wlc_phy_get_phyversion(struct brcms_phy_pub *pih , u16 *phytype , u16 *phyrev , u16 *radioid , u16 *radiover ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; *phytype = (unsigned short )pi->pubpi.phy_type; *phyrev = (unsigned short )pi->pubpi.phy_rev; *radioid = pi->pubpi.radioid; *radiover = (u16 )pi->pubpi.radiorev; return (1); } } bool wlc_phy_get_encore(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; return (pi->pubpi.abgphy_encore); } } u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; return (pi->pubpi.coreflags); } } void wlc_phy_anacore(struct brcms_phy_pub *pih , bool on ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if (pi->pubpi.phy_type == 4U) { if ((int )on) { if (pi->pubpi.phy_rev > 2U) { write_phy_reg(pi, 166, 13); write_phy_reg(pi, 143, 0); write_phy_reg(pi, 167, 13); write_phy_reg(pi, 165, 0); } else { write_phy_reg(pi, 165, 0); } } else if (pi->pubpi.phy_rev > 2U) { write_phy_reg(pi, 143, 2047); write_phy_reg(pi, 166, 253); write_phy_reg(pi, 165, 2047); write_phy_reg(pi, 167, 253); } else { write_phy_reg(pi, 165, 32767); } } else if (pi->pubpi.phy_type == 8U) { if ((int )on) { and_phy_reg(pi, 1083, 65528); } else { or_phy_reg(pi, 1084, 7); or_phy_reg(pi, 1083, 7); } } else { } return; } } u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u32 phy_bw_clkbits ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; phy_bw_clkbits = 0U; if ((unsigned long )pi != (unsigned long )((struct brcms_phy *)0) && (pi->pubpi.phy_type == 4U || pi->pubpi.phy_type == 8U)) { switch ((int )pi->bw) { case 1024: phy_bw_clkbits = 0U; goto ldv_37446; case 2048: phy_bw_clkbits = 64U; goto ldv_37446; case 3072: phy_bw_clkbits = 128U; goto ldv_37446; default: ; goto ldv_37446; } ldv_37446: ; } else { } return (phy_bw_clkbits); } } void wlc_phy_por_inform(struct brcms_phy_pub *ppi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; pi->phy_init_por = 1; return; } } void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih , bool lock ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; pi->edcrs_threshold_lock = lock; write_phy_reg(pi, 556, 1131); write_phy_reg(pi, 557, 1131); write_phy_reg(pi, 558, 960); write_phy_reg(pi, 559, 960); return; } } void wlc_phy_initcal_enable(struct brcms_phy_pub *pih , bool initcal ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; pi->do_initcal = initcal; return; } } void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *pih , bool newstate ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if ((unsigned long )pi == (unsigned long )((struct brcms_phy *)0) || (unsigned long )pi->sh == (unsigned long )((struct shared_phy *)0)) { return; } else { } (pi->sh)->clk = newstate; return; } } void wlc_phy_hw_state_upd(struct brcms_phy_pub *pih , bool newstate ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if ((unsigned long )pi == (unsigned long )((struct brcms_phy *)0) || (unsigned long )pi->sh == (unsigned long )((struct shared_phy *)0)) { return; } else { } (pi->sh)->up = newstate; return; } } void wlc_phy_init(struct brcms_phy_pub *pih , u16 chanspec ) { u32 mc ; void (*phy_init)(struct brcms_phy * ) ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; int __ret_warn_on ; long tmp ; long tmp___0 ; int __ret_warn_on___0 ; u32 tmp___1 ; long tmp___2 ; long tmp___3 ; { phy_init = (void (*)(struct brcms_phy * ))0; __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if ((int )pi->init_in_progress) { return; } else { } pi->init_in_progress = 1; pi->radio_chanspec = chanspec; mc = bcma_read32(pi->d11core, 288); __ret_warn_on = (int )mc & 1; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c", 759, "HW error MAC running on init"); } else { } tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { return; } else { } if ((pi->measure_hold & 2U) == 0U) { pi->measure_hold = pi->measure_hold | 32U; } else { } tmp___1 = bcma_aread32(pi->d11core, 1280); __ret_warn_on___0 = (tmp___1 & 4U) == 0U; tmp___2 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___2 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c", 766, "HW error SISF_FCLKA\n"); } else { } tmp___3 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___3 != 0L) { return; } else { } phy_init = pi->pi_fptr.init; if ((unsigned long )phy_init == (unsigned long )((void (*)(struct brcms_phy * ))0)) { return; } else { } wlc_phy_anacore(pih, 1); if (((int )pi->radio_chanspec & 3072) != (int )pi->bw) { wlapi_bmac_bw_set((pi->sh)->physhim, (int )pi->radio_chanspec & 3072); } else { } pi->nphy_gain_boost = 1; wlc_phy_switch_radio((struct brcms_phy_pub *)pi, 1); (*phy_init)(pi); pi->phy_init_por = 0; if ((pi->sh)->corerev == 11U || (pi->sh)->corerev == 12U) { wlc_phy_do_dummy_tx(pi, 1, 0); } else { } if (pi->pubpi.phy_type != 4U) { wlc_phy_txpower_update_shm(pi); } else { } wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *)pi, (int )(pi->sh)->rx_antdiv); pi->init_in_progress = 0; return; } } void wlc_phy_cal_init(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; void (*cal_init)(struct brcms_phy * ) ; int __ret_warn_on ; u32 tmp ; long tmp___0 ; long tmp___1 ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; cal_init = (void (*)(struct brcms_phy * ))0; tmp = bcma_read32(pi->d11core, 288); __ret_warn_on = (int )tmp & 1; tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c", 805, "HW error: MAC enabled during phy cal\n"); } else { } tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { return; } else { } if (! pi->initialized) { cal_init = pi->pi_fptr.calinit; if ((unsigned long )cal_init != (unsigned long )((void (*)(struct brcms_phy * ))0)) { (*cal_init)(pi); } else { } pi->initialized = 1; } else { } return; } } int wlc_phy_down(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; int callbacks ; bool tmp ; int tmp___0 ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; callbacks = 0; if ((unsigned long )pi->phycal_timer != (unsigned long )((struct wlapi_timer *)0)) { tmp = wlapi_del_timer(pi->phycal_timer); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { callbacks = callbacks + 1; } else { } } else { } pi->nphy_iqcal_chanspec_2G = 0U; pi->nphy_iqcal_chanspec_5G = 0U; return (callbacks); } } void wlc_phy_table_addr(struct brcms_phy *pi , uint tbl_id , uint tbl_offset , u16 tblAddr , u16 tblDataHi , u16 tblDataLo ) { { write_phy_reg(pi, (int )tblAddr, ((int )((u16 )tbl_id) << 10U) | (int )((u16 )tbl_offset)); pi->tbl_data_hi = tblDataHi; pi->tbl_data_lo = tblDataLo; if ((pi->sh)->chip == 43224U && (pi->sh)->chiprev == 1U) { pi->tbl_addr = tblAddr; pi->tbl_save_id = tbl_id; pi->tbl_save_offset = tbl_offset; } else { } return; } } void wlc_phy_table_data_write(struct brcms_phy *pi , uint width , u32 val ) { { if (((pi->sh)->chip == 43224U && (pi->sh)->chiprev == 1U) && pi->tbl_save_id == 9U) { read_phy_reg(pi, (int )pi->tbl_data_lo); write_phy_reg(pi, (int )pi->tbl_addr, ((int )((u16 )pi->tbl_save_id) << 10U) | (int )((u16 )pi->tbl_save_offset)); pi->tbl_save_offset = pi->tbl_save_offset + 1U; } else { } if (width == 32U) { write_phy_reg(pi, (int )pi->tbl_data_hi, (int )((unsigned short )(val >> 16))); write_phy_reg(pi, (int )pi->tbl_data_lo, (int )((unsigned short )val)); } else { write_phy_reg(pi, (int )pi->tbl_data_lo, (int )((unsigned short )val)); } return; } } void wlc_phy_write_table(struct brcms_phy *pi , struct phytbl_info const *ptbl_info , u16 tblAddr , u16 tblDataHi , u16 tblDataLo ) { uint idx ; uint tbl_id ; uint tbl_offset ; uint tbl_width ; u8 const *ptbl_8b ; u16 const *ptbl_16b ; u32 const *ptbl_32b ; { tbl_id = ptbl_info->tbl_id; tbl_offset = ptbl_info->tbl_offset; tbl_width = ptbl_info->tbl_width; ptbl_8b = (u8 const *)ptbl_info->tbl_ptr; ptbl_16b = (u16 const *)ptbl_info->tbl_ptr; ptbl_32b = (u32 const *)ptbl_info->tbl_ptr; write_phy_reg(pi, (int )tblAddr, ((int )((u16 )tbl_id) << 10U) | (int )((u16 )tbl_offset)); idx = 0U; goto ldv_37543; ldv_37542: ; if (((pi->sh)->chip == 43224U && (pi->sh)->chiprev == 1U) && tbl_id == 9U) { read_phy_reg(pi, (int )tblDataLo); write_phy_reg(pi, (int )tblAddr, ((int )((u16 )tbl_id) << 10U) | ((int )((u16 )tbl_offset) + (int )((u16 )idx))); } else { } if (tbl_width == 32U) { write_phy_reg(pi, (int )tblDataHi, (int )((unsigned short )(*(ptbl_32b + (unsigned long )idx) >> 16))); write_phy_reg(pi, (int )tblDataLo, (int )((unsigned short )*(ptbl_32b + (unsigned long )idx))); } else if (tbl_width == 16U) { write_phy_reg(pi, (int )tblDataLo, (int )*(ptbl_16b + (unsigned long )idx)); } else { write_phy_reg(pi, (int )tblDataLo, (int )*(ptbl_8b + (unsigned long )idx)); } idx = idx + 1U; ldv_37543: ; if ((uint )ptbl_info->tbl_len > idx) { goto ldv_37542; } else { } return; } } void wlc_phy_read_table(struct brcms_phy *pi , struct phytbl_info const *ptbl_info , u16 tblAddr , u16 tblDataHi , u16 tblDataLo ) { uint idx ; uint tbl_id ; uint tbl_offset ; uint tbl_width ; u8 *ptbl_8b ; u16 *ptbl_16b ; u32 *ptbl_32b ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; { tbl_id = ptbl_info->tbl_id; tbl_offset = ptbl_info->tbl_offset; tbl_width = ptbl_info->tbl_width; ptbl_8b = (u8 *)ptbl_info->tbl_ptr; ptbl_16b = (u16 *)ptbl_info->tbl_ptr; ptbl_32b = (u32 *)ptbl_info->tbl_ptr; write_phy_reg(pi, (int )tblAddr, ((int )((u16 )tbl_id) << 10U) | (int )((u16 )tbl_offset)); idx = 0U; goto ldv_37560; ldv_37559: ; if ((pi->sh)->chip == 43224U && (pi->sh)->chiprev == 1U) { read_phy_reg(pi, (int )tblDataLo); write_phy_reg(pi, (int )tblAddr, ((int )((u16 )tbl_id) << 10U) | ((int )((u16 )tbl_offset) + (int )((u16 )idx))); } else { } if (tbl_width == 32U) { tmp = read_phy_reg(pi, (int )tblDataLo); *(ptbl_32b + (unsigned long )idx) = (u32 )tmp; tmp___0 = read_phy_reg(pi, (int )tblDataHi); *(ptbl_32b + (unsigned long )idx) = *(ptbl_32b + (unsigned long )idx) | (u32 )((int )tmp___0 << 16); } else if (tbl_width == 16U) { *(ptbl_16b + (unsigned long )idx) = read_phy_reg(pi, (int )tblDataLo); } else { tmp___1 = read_phy_reg(pi, (int )tblDataLo); *(ptbl_8b + (unsigned long )idx) = (unsigned char )tmp___1; } idx = idx + 1U; ldv_37560: ; if ((uint )ptbl_info->tbl_len > idx) { goto ldv_37559; } else { } return; } } uint wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi , struct radio_20xx_regs *radioregs ) { uint i ; { i = 0U; ldv_37567: ; if ((unsigned int )(radioregs + (unsigned long )i)->do_init != 0U) { write_radio_reg(pi, (int )(radioregs + (unsigned long )i)->address, (int )(radioregs + (unsigned long )i)->init); } else { } i = i + 1U; if ((unsigned int )(radioregs + (unsigned long )i)->address != 65535U) { goto ldv_37567; } else { } return (i); } } uint wlc_phy_init_radio_regs(struct brcms_phy *pi , struct radio_regs const *radioregs , u16 core_offset ) { uint i ; uint count ; { i = 0U; count = 0U; ldv_37576: ; if (((int )pi->radio_chanspec & 61440) == 4096) { if ((unsigned int )((unsigned char )(radioregs + (unsigned long )i)->do_init_a) != 0U) { write_radio_reg(pi, (int )((unsigned short )(radioregs + (unsigned long )i)->address) | (int )core_offset, (int )((unsigned short )(radioregs + (unsigned long )i)->init_a)); if (pi->pubpi.phy_type == 4U) { count = count + 1U; if ((count & 3U) == 0U) { if (pi->pubpi.phy_rev <= 2U) { bcma_read32(pi->d11core, 288); } else { } } else { } } else { } } else { } } else if ((unsigned int )((unsigned char )(radioregs + (unsigned long )i)->do_init_g) != 0U) { write_radio_reg(pi, (int )((unsigned short )(radioregs + (unsigned long )i)->address) | (int )core_offset, (int )((unsigned short )(radioregs + (unsigned long )i)->init_g)); if (pi->pubpi.phy_type == 4U) { count = count + 1U; if ((count & 3U) == 0U) { if (pi->pubpi.phy_rev <= 2U) { bcma_read32(pi->d11core, 288); } else { } } else { } } else { } } else { } i = i + 1U; if ((unsigned int )((unsigned short )(radioregs + (unsigned long )i)->address) != 65535U) { goto ldv_37576; } else { } return (i); } } void wlc_phy_do_dummy_tx(struct brcms_phy *pi , bool ofdm , bool pa_on ) { struct bcma_device *core ; int i ; int count ; u8 ofdmpkt[20U] ; u8 cckpkt[20U] ; u32 *dummypkt ; int tmp ; u32 tmp___0 ; int tmp___1 ; u32 tmp___2 ; int tmp___3 ; u32 tmp___4 ; { core = pi->d11core; ofdmpkt[0] = 204U; ofdmpkt[1] = 1U; ofdmpkt[2] = 2U; ofdmpkt[3] = 0U; ofdmpkt[4] = 0U; ofdmpkt[5] = 0U; ofdmpkt[6] = 212U; ofdmpkt[7] = 0U; ofdmpkt[8] = 0U; ofdmpkt[9] = 0U; ofdmpkt[10] = 0U; ofdmpkt[11] = 0U; ofdmpkt[12] = 0U; ofdmpkt[13] = 0U; ofdmpkt[14] = 0U; ofdmpkt[15] = 1U; ofdmpkt[16] = 0U; ofdmpkt[17] = 0U; ofdmpkt[18] = 0U; ofdmpkt[19] = 0U; cckpkt[0] = 110U; cckpkt[1] = 132U; cckpkt[2] = 11U; cckpkt[3] = 0U; cckpkt[4] = 0U; cckpkt[5] = 0U; cckpkt[6] = 212U; cckpkt[7] = 0U; cckpkt[8] = 0U; cckpkt[9] = 0U; cckpkt[10] = 0U; cckpkt[11] = 0U; cckpkt[12] = 0U; cckpkt[13] = 0U; cckpkt[14] = 0U; cckpkt[15] = 1U; cckpkt[16] = 0U; cckpkt[17] = 0U; cckpkt[18] = 0U; cckpkt[19] = 0U; dummypkt = (u32 *)((int )ofdm ? & ofdmpkt : & cckpkt); wlapi_bmac_write_template_ram((pi->sh)->physhim, 0, 20, (void *)dummypkt); bcma_write16(core, 1384, 0U); if ((pi->sh)->corerev > 10U) { bcma_write16(core, 1984, 256U); } else { bcma_write16(core, 1984, 0U); } bcma_write16(core, 1292, (u32 )((int )ofdm | 64)); if (pi->pubpi.phy_type == 4U || pi->pubpi.phy_type == 8U) { bcma_write16(core, 1300, 6658U); } else { } bcma_write16(core, 1288, 0U); bcma_write16(core, 1290, 0U); bcma_write16(core, 1356, 0U); bcma_write16(core, 1386, 20U); bcma_write16(core, 1384, 2086U); bcma_write16(core, 1280, 0U); if (! pa_on) { if (pi->pubpi.phy_type == 4U) { wlc_phy_pa_override_nphy(pi, 0); } else { } } else { } if (pi->pubpi.phy_type == 4U || pi->pubpi.phy_type == 8U) { bcma_write16(core, 1282, 208U); } else { bcma_write16(core, 1282, 48U); } bcma_read16(core, 1282); i = 0; count = (int )ofdm ? 30 : 250; goto ldv_37590; ldv_37589: __const_udelay(42950UL); ldv_37590: tmp = i; i = i + 1; if (tmp < count) { tmp___0 = bcma_read16(core, 1294); if ((tmp___0 & 128U) != 0U) { goto ldv_37589; } else { goto ldv_37591; } } else { } ldv_37591: i = 0; goto ldv_37593; ldv_37592: __const_udelay(42950UL); ldv_37593: tmp___1 = i; i = i + 1; if (tmp___1 <= 9) { tmp___2 = bcma_read16(core, 1294); if ((tmp___2 & 1024U) == 0U) { goto ldv_37592; } else { goto ldv_37594; } } else { } ldv_37594: i = 0; goto ldv_37596; ldv_37595: __const_udelay(42950UL); ldv_37596: tmp___3 = i; i = i + 1; if (tmp___3 <= 9) { tmp___4 = bcma_read16(core, 1680); if ((tmp___4 & 256U) != 0U) { goto ldv_37595; } else { goto ldv_37597; } } else { } ldv_37597: ; if (! pa_on) { if (pi->pubpi.phy_type == 4U) { wlc_phy_pa_override_nphy(pi, 1); } else { } } else { } return; } } void wlc_phy_hold_upd(struct brcms_phy_pub *pih , u32 id , bool set ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if ((int )set) { pi->measure_hold = pi->measure_hold | id; } else { pi->measure_hold = pi->measure_hold & ~ id; } return; } } void wlc_phy_mute_upd(struct brcms_phy_pub *pih , bool mute , u32 flags ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if ((int )mute) { pi->measure_hold = pi->measure_hold | 16U; } else { pi->measure_hold = pi->measure_hold & 4294967279U; } if (! mute && (int )flags & 1) { pi->nphy_perical_last = (pi->sh)->now - (pi->sh)->glacial_timer; } else { } return; } } void wlc_phy_clear_tssi(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if (pi->pubpi.phy_type == 4U) { return; } else { wlapi_bmac_write_shm((pi->sh)->physhim, 88U, 32639); wlapi_bmac_write_shm((pi->sh)->physhim, 90U, 32639); wlapi_bmac_write_shm((pi->sh)->physhim, 112U, 32639); wlapi_bmac_write_shm((pi->sh)->physhim, 114U, 32639); } return; } } static bool wlc_phy_cal_txpower_recalc_sw(struct brcms_phy *pi ) { { return (0); } } void wlc_phy_switch_radio(struct brcms_phy_pub *pih , bool on ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; bcma_read32(pi->d11core, 288); if (pi->pubpi.phy_type == 4U) { wlc_phy_switch_radio_nphy(pi, (int )on); } else if (pi->pubpi.phy_type == 8U) { if ((int )on) { and_phy_reg(pi, 1100, 57599); and_phy_reg(pi, 1200, 63479); and_phy_reg(pi, 1273, 65527); } else { and_phy_reg(pi, 1101, 33791); or_phy_reg(pi, 1100, 7936); and_phy_reg(pi, 1207, 33023); and_phy_reg(pi, 1201, 57343); or_phy_reg(pi, 1200, 2056); and_phy_reg(pi, 1274, 65527); or_phy_reg(pi, 1273, 8); } } else { } return; } } u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; return (pi->bw); } } void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi , u16 bw ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; pi->bw = bw; return; } } void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi , u16 newch ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; pi->radio_chanspec = newch; return; } } u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; return (pi->radio_chanspec); } } void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi , u16 chanspec ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u16 m_cur_channel ; void (*chanspec_set)(struct brcms_phy * , u16 ) ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; chanspec_set = (void (*)(struct brcms_phy * , u16 ))0; m_cur_channel = (u16 )((unsigned char )chanspec); if (((int )chanspec & 61440) == 4096) { m_cur_channel = (u16 )((unsigned int )m_cur_channel | 256U); } else { } if (((int )chanspec & 3072) == 3072) { m_cur_channel = (u16 )((unsigned int )m_cur_channel | 512U); } else { } wlapi_bmac_write_shm((pi->sh)->physhim, 160U, (int )m_cur_channel); chanspec_set = pi->pi_fptr.chanset; if ((unsigned long )chanspec_set != (unsigned long )((void (*)(struct brcms_phy * , u16 ))0)) { (*chanspec_set)(pi, (int )chanspec); } else { } return; } } int wlc_phy_chanspec_freq2bandrange_lpssn(uint freq ) { int range ; { range = -1; if (freq <= 2499U) { range = 0; } else if (freq <= 5320U) { range = 1; } else if (freq <= 5700U) { range = 2; } else { range = 3; } return (range); } } int wlc_phy_chanspec_bandrange_get(struct brcms_phy *pi , u16 chanspec ) { int range ; uint channel ; uint freq ; int tmp ; u8 tmp___0 ; { range = -1; channel = (uint )((unsigned char )chanspec); tmp = wlc_phy_channel2freq(channel); freq = (uint )tmp; if (pi->pubpi.phy_type == 4U) { tmp___0 = wlc_phy_get_chan_freq_range_nphy(pi, channel); range = (int )tmp___0; } else if (pi->pubpi.phy_type == 8U) { range = wlc_phy_chanspec_freq2bandrange_lpssn(freq); } else { } return (range); } } void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi , bool wide_filter ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; pi->channel_14_wide_filter = wide_filter; return; } } int wlc_phy_channel2freq(uint channel ) { uint i ; { i = 0U; goto ldv_37692; ldv_37691: ; if ((uint )chan_info_all[i].chan == channel) { return ((int )chan_info_all[i].freq); } else { } i = i + 1U; ldv_37692: ; if (i <= 50U) { goto ldv_37691; } else { } return (0); } } void wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi , uint band , struct brcms_chanvec *channels ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; uint i ; uint channel ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; memset((void *)channels, 0, 28UL); i = 0U; goto ldv_37708; ldv_37707: channel = (uint )chan_info_all[i].chan; if (((unsigned int )pi->a_band_high_disable != 0U && channel > 148U) && channel <= 165U) { goto ldv_37706; } else { } if ((band == 2U && channel <= 14U) || (band == 1U && channel > 14U)) { *((u8 *)(& channels->vec) + (unsigned long )(channel / 8U)) = (u8 )((int )((signed char )*((u8 *)(& channels->vec) + (unsigned long )(channel / 8U))) | (int )((signed char )(1 << ((int )channel & 7)))); } else { } ldv_37706: i = i + 1U; ldv_37708: ; if (i <= 50U) { goto ldv_37707; } else { } return; } } u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi , uint band ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; uint i ; uint channel ; u16 chspec ; uint j ; int tmp ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; i = 0U; goto ldv_37732; ldv_37731: channel = (uint )chan_info_all[i].chan; if (pi->pubpi.phy_type == 4U && (unsigned int )pi->bw == 3072U) { j = 0U; goto ldv_37727; ldv_37726: ; if ((uint )chan_info_all[j].chan == channel + 2U) { goto ldv_37725; } else { } j = j + 1U; ldv_37727: ; if (j <= 50U) { goto ldv_37726; } else { } ldv_37725: ; if (j == 51U) { goto ldv_37730; } else { } tmp = upper_20_sb((int )channel); channel = (uint )tmp; chspec = (unsigned int )((u16 )channel) | 3328U; if (band == 2U) { chspec = (u16 )((unsigned int )chspec | 8192U); } else { chspec = (u16 )((unsigned int )chspec | 4096U); } } else { chspec = ch20mhz_chspec((int )channel); } if (((unsigned int )pi->a_band_high_disable != 0U && channel > 148U) && channel <= 165U) { goto ldv_37730; } else { } if ((band == 2U && channel <= 14U) || (band == 1U && channel > 14U)) { return (chspec); } else { } ldv_37730: i = i + 1U; ldv_37732: ; if (i <= 50U) { goto ldv_37731; } else { } return (255U); } } int wlc_phy_txpower_get(struct brcms_phy_pub *ppi , uint *qdbm , bool *override ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; *qdbm = (uint )pi->tx_user_target[0]; if ((unsigned long )override != (unsigned long )((bool *)0)) { *override = pi->txpwroverride; } else { } return (0); } } void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi , struct txpwr_limits *txpwr ) { bool mac_enabled ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u32 tmp ; { mac_enabled = 0; __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; memcpy((void *)(& pi->tx_user_target), (void const *)(& txpwr->cck), 4UL); memcpy((void *)(& pi->tx_user_target) + 4U, (void const *)(& txpwr->ofdm), 8UL); memcpy((void *)(& pi->tx_user_target) + 12U, (void const *)(& txpwr->ofdm_cdd), 8UL); memcpy((void *)(& pi->tx_user_target) + 52U, (void const *)(& txpwr->ofdm_40_siso), 8UL); memcpy((void *)(& pi->tx_user_target) + 60U, (void const *)(& txpwr->ofdm_40_cdd), 8UL); memcpy((void *)(& pi->tx_user_target) + 20U, (void const *)(& txpwr->mcs_20_siso), 8UL); memcpy((void *)(& pi->tx_user_target) + 28U, (void const *)(& txpwr->mcs_20_cdd), 8UL); memcpy((void *)(& pi->tx_user_target) + 36U, (void const *)(& txpwr->mcs_20_stbc), 8UL); memcpy((void *)(& pi->tx_user_target) + 44U, (void const *)(& txpwr->mcs_20_mimo), 8UL); memcpy((void *)(& pi->tx_user_target) + 68U, (void const *)(& txpwr->mcs_40_siso), 8UL); memcpy((void *)(& pi->tx_user_target) + 76U, (void const *)(& txpwr->mcs_40_cdd), 8UL); memcpy((void *)(& pi->tx_user_target) + 84U, (void const *)(& txpwr->mcs_40_stbc), 8UL); memcpy((void *)(& pi->tx_user_target) + 92U, (void const *)(& txpwr->mcs_40_mimo), 8UL); tmp = bcma_read32(pi->d11core, 288); if ((int )tmp & 1) { mac_enabled = 1; } else { } if ((int )mac_enabled) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_phy_txpower_recalc_target(pi); wlc_phy_cal_txpower_recalc_sw(pi); if ((int )mac_enabled) { wlapi_enable_mac((pi->sh)->physhim); } else { } return; } } int wlc_phy_txpower_set(struct brcms_phy_pub *ppi , uint qdbm , bool override ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; int i ; bool suspend ; u32 tmp ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; if (qdbm > 127U) { return (-22); } else { } i = 0; goto ldv_37760; ldv_37759: pi->tx_user_target[i] = (unsigned char )qdbm; i = i + 1; ldv_37760: ; if (i <= 100) { goto ldv_37759; } else { } pi->txpwroverride = 0; if ((int )(pi->sh)->up) { if ((pi->measure_hold & 2U) == 0U) { tmp = bcma_read32(pi->d11core, 288); suspend = (tmp & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_phy_txpower_recalc_target(pi); wlc_phy_cal_txpower_recalc_sw(pi); if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } } else { } } else { } return (0); } } void wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi , uint channel , u8 *min_pwr , u8 *max_pwr , int txp_rate_idx ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; uint i ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; *min_pwr = (unsigned int )pi->min_txpower * 4U; if (pi->pubpi.phy_type == 4U) { if (txp_rate_idx < 0) { txp_rate_idx = 0; } else { } wlc_phy_txpower_sromlimit_get_nphy(pi, channel, max_pwr, (int )((unsigned char )txp_rate_idx)); } else if (channel <= 14U) { if (txp_rate_idx < 0) { txp_rate_idx = 0; } else { } *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx]; } else { *max_pwr = 127U; if (txp_rate_idx < 0) { txp_rate_idx = 4; } else { } i = 0U; goto ldv_37778; ldv_37777: ; if ((uint )chan_info_all[i].chan == channel) { goto ldv_37776; } else { } i = i + 1U; ldv_37778: ; if (i <= 50U) { goto ldv_37777; } else { } ldv_37776: ; if ((unsigned long )pi->hwtxpwr != (unsigned long )((u8 *)0U)) { *max_pwr = *(pi->hwtxpwr + (unsigned long )i); } else { if (i > 13U && i <= 35U) { *max_pwr = pi->tx_srom_max_rate_5g_mid[txp_rate_idx]; } else { } if (i > 35U && i <= 41U) { *max_pwr = pi->tx_srom_max_rate_5g_hi[txp_rate_idx]; } else { } if (i > 41U && i <= 50U) { *max_pwr = pi->tx_srom_max_rate_5g_low[txp_rate_idx]; } else { } } } return; } } void wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi , uint chan , u8 *max_txpwr , u8 *min_txpwr ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u8 tx_pwr_max ; u8 tx_pwr_min ; u8 max_num_rate ; u8 maxtxpwr ; u8 mintxpwr ; u8 rate ; u8 pactrl ; u8 _max1 ; u8 _max2 ; u8 _min1 ; u8 _min2 ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; tx_pwr_max = 0U; tx_pwr_min = 255U; pactrl = 0U; max_num_rate = pi->pubpi.phy_type != 4U ? (pi->pubpi.phy_type == 8U ? 28U : 12U) : 101U; rate = 0U; goto ldv_37802; ldv_37801: wlc_phy_txpower_sromlimit(ppi, chan, & mintxpwr, & maxtxpwr, (int )rate); maxtxpwr = (int )maxtxpwr > (int )pactrl ? (int )maxtxpwr - (int )pactrl : 0U; maxtxpwr = (unsigned int )maxtxpwr > 6U ? (unsigned int )maxtxpwr + 250U : 0U; _max1 = tx_pwr_max; _max2 = maxtxpwr; tx_pwr_max = (u8 )((int )_max1 > (int )_max2 ? _max1 : _max2); _min1 = tx_pwr_min; _min2 = maxtxpwr; tx_pwr_min = (u8 )((int )_min1 < (int )_min2 ? _min1 : _min2); rate = (u8 )((int )rate + 1); ldv_37802: ; if ((int )rate < (int )max_num_rate) { goto ldv_37801; } else { } *max_txpwr = tx_pwr_max; *min_txpwr = tx_pwr_min; return; } } void wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi , uint bandunit , s32 *max_pwr , s32 *min_pwr , u32 *step_pwr ) { { return; } } u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; return (pi->tx_power_min); } } u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; return (pi->tx_power_max); } } static s8 wlc_phy_env_measure_vbat(struct brcms_phy *pi ) { s8 tmp ; { if (pi->pubpi.phy_type == 8U) { tmp = wlc_lcnphy_vbatsense(pi, 0); return (tmp); } else { return (0); } } } static s8 wlc_phy_env_measure_temperature(struct brcms_phy *pi ) { s8 tmp ; { if (pi->pubpi.phy_type == 8U) { tmp = wlc_lcnphy_tempsense_degree(pi, 0); return (tmp); } else { return (0); } } } static void wlc_phy_upd_env_txpwr_rate_limits(struct brcms_phy *pi , u32 band ) { u8 i ; s8 temp ; s8 vbat ; { i = 0U; goto ldv_37837; ldv_37836: pi->txpwr_env_limit[(int )i] = 127U; i = (u8 )((int )i + 1); ldv_37837: ; if ((unsigned int )i <= 100U) { goto ldv_37836; } else { } vbat = wlc_phy_env_measure_vbat(pi); temp = wlc_phy_env_measure_temperature(pi); return; } } static s8 wlc_user_txpwr_antport_to_rfport(struct brcms_phy *pi , uint chan , u32 band , u8 rate ) { { return (0); } } void wlc_phy_txpower_recalc_target(struct brcms_phy *pi ) { u8 maxtxpwr ; u8 mintxpwr ; u8 rate ; u8 pactrl ; uint target_chan ; u8 tx_pwr_target[101U] ; u8 tx_pwr_max ; u8 tx_pwr_min ; u8 tx_pwr_max_rate_ind ; u8 max_num_rate ; u8 start_rate ; u16 chspec ; u32 band ; void (*txpwr_recalc_fn)(struct brcms_phy * ) ; int tmp ; int tmp___0 ; u32 offset_mcs ; u32 i ; s8 tmp___1 ; u8 _min1 ; u8 _min2 ; u8 _min1___0 ; u8 _min2___0 ; u8 _max1 ; u8 _max2 ; u8 _min1___1 ; u8 _min2___1 ; u8 _max1___0 ; u8 _max2___0 ; u8 _min1___2 ; u8 _min2___2 ; { tx_pwr_max = 0U; tx_pwr_min = 255U; tx_pwr_max_rate_ind = 0U; start_rate = 0U; band = ((int )pi->radio_chanspec & 61440) == 4096 ? 1U : 2U; txpwr_recalc_fn = (void (*)(struct brcms_phy * ))0; chspec = pi->radio_chanspec; if (((int )chspec & 768) == 768) { target_chan = (uint )((unsigned char )chspec); } else if (((int )chspec & 768) == 512) { tmp = upper_20_sb((int )((unsigned char )chspec)); target_chan = (uint )tmp; } else { tmp___0 = lower_20_sb((int )((unsigned char )chspec)); target_chan = (uint )tmp___0; } pactrl = 0U; if (pi->pubpi.phy_type == 8U) { if (((int )pi->radio_chanspec & 3072) == 3072) { offset_mcs = pi->mcs40_po; i = 20U; goto ldv_37866; ldv_37865: pi->tx_srom_max_rate_2g[i - 8U] = (unsigned int )pi->tx_srom_max_2g - ((unsigned int )((u8 )offset_mcs) & 15U) * 2U; offset_mcs = offset_mcs >> 4; i = i + 1U; ldv_37866: ; if (i <= 27U) { goto ldv_37865; } else { } } else { offset_mcs = pi->mcs20_po; i = 20U; goto ldv_37869; ldv_37868: pi->tx_srom_max_rate_2g[i - 8U] = (unsigned int )pi->tx_srom_max_2g - ((unsigned int )((u8 )offset_mcs) & 15U) * 2U; offset_mcs = offset_mcs >> 4; i = i + 1U; ldv_37869: ; if (i <= 27U) { goto ldv_37868; } else { } } } else { } max_num_rate = pi->pubpi.phy_type != 4U ? (pi->pubpi.phy_type == 8U ? 28U : 12U) : 101U; wlc_phy_upd_env_txpwr_rate_limits(pi, band); rate = start_rate; goto ldv_37890; ldv_37889: tx_pwr_target[(int )rate] = pi->tx_user_target[(int )rate]; if ((int )pi->user_txpwr_at_rfport) { tmp___1 = wlc_user_txpwr_antport_to_rfport(pi, target_chan, band, (int )rate); tx_pwr_target[(int )rate] = (int )tx_pwr_target[(int )rate] + (int )((u8 )tmp___1); } else { } wlc_phy_txpower_sromlimit((struct brcms_phy_pub *)pi, target_chan, & mintxpwr, & maxtxpwr, (int )rate); _min1 = maxtxpwr; _min2 = pi->txpwr_limit[(int )rate]; maxtxpwr = (u8 )((int )_min1 < (int )_min2 ? _min1 : _min2); maxtxpwr = (int )maxtxpwr > (int )pactrl ? (int )maxtxpwr - (int )pactrl : 0U; maxtxpwr = (unsigned int )maxtxpwr > 6U ? (unsigned int )maxtxpwr + 250U : 0U; _min1___0 = maxtxpwr; _min2___0 = tx_pwr_target[(int )rate]; maxtxpwr = (u8 )((int )_min1___0 < (int )_min2___0 ? _min1___0 : _min2___0); if ((unsigned int )pi->txpwr_percent <= 100U) { maxtxpwr = (u8 )(((int )maxtxpwr * (int )pi->txpwr_percent) / 100); } else { } _max1 = maxtxpwr; _max2 = mintxpwr; tx_pwr_target[(int )rate] = (u8 )((int )_max1 > (int )_max2 ? _max1 : _max2); _min1___1 = tx_pwr_target[(int )rate]; _min2___1 = pi->txpwr_env_limit[(int )rate]; tx_pwr_target[(int )rate] = (u8 )((int )_min1___1 < (int )_min2___1 ? _min1___1 : _min2___1); if ((int )tx_pwr_target[(int )rate] > (int )tx_pwr_max) { tx_pwr_max_rate_ind = rate; } else { } _max1___0 = tx_pwr_max; _max2___0 = tx_pwr_target[(int )rate]; tx_pwr_max = (u8 )((int )_max1___0 > (int )_max2___0 ? _max1___0 : _max2___0); _min1___2 = tx_pwr_min; _min2___2 = tx_pwr_target[(int )rate]; tx_pwr_min = (u8 )((int )_min1___2 < (int )_min2___2 ? _min1___2 : _min2___2); rate = (u8 )((int )rate + 1); ldv_37890: ; if ((int )rate < (int )max_num_rate) { goto ldv_37889; } else { } memset((void *)(& pi->tx_power_offset), 0, 101UL); pi->tx_power_max = tx_pwr_max; pi->tx_power_min = tx_pwr_min; pi->tx_power_max_rate_ind = tx_pwr_max_rate_ind; rate = 0U; goto ldv_37893; ldv_37892: pi->tx_power_target[(int )rate] = tx_pwr_target[(int )rate]; if (! pi->hwpwrctrl || pi->pubpi.phy_type == 4U) { pi->tx_power_offset[(int )rate] = (s8 )((int )pi->tx_power_max - (int )pi->tx_power_target[(int )rate]); } else { pi->tx_power_offset[(int )rate] = (s8 )((int )pi->tx_power_target[(int )rate] - (int )pi->tx_power_min); } rate = (u8 )((int )rate + 1); ldv_37893: ; if ((int )rate < (int )max_num_rate) { goto ldv_37892; } else { } txpwr_recalc_fn = pi->pi_fptr.txpwrrecalc; if ((unsigned long )txpwr_recalc_fn != (unsigned long )((void (*)(struct brcms_phy * ))0)) { (*txpwr_recalc_fn)(pi); } else { } return; } } static void wlc_phy_txpower_reg_limit_calc(struct brcms_phy *pi , struct txpwr_limits *txpwr , u16 chanspec ) { u8 tmp_txpwr_limit[16U] ; u8 *txpwr_ptr1 ; u8 *txpwr_ptr2 ; int rate_start_index ; int rate1 ; int rate2 ; int k ; u8 _min1 ; u8 _min2 ; u8 _min1___0 ; u8 _min2___0 ; u8 _min1___1 ; u8 _min2___1 ; { txpwr_ptr1 = (u8 *)0U; txpwr_ptr2 = (u8 *)0U; rate_start_index = 0; rate1 = 0; rate2 = 0; goto ldv_37908; ldv_37907: pi->txpwr_limit[rate1] = txpwr->cck[rate2]; rate1 = rate1 + 1; rate2 = rate2 + 1; ldv_37908: ; if (rate2 <= 3) { goto ldv_37907; } else { } rate1 = 4; rate2 = 0; goto ldv_37911; ldv_37910: pi->txpwr_limit[rate1] = txpwr->ofdm[rate2]; rate1 = rate1 + 1; rate2 = rate2 + 1; ldv_37911: ; if (rate2 <= 7) { goto ldv_37910; } else { } if (pi->pubpi.phy_type == 4U) { k = 0; goto ldv_37928; ldv_37927: ; switch (k) { case 0: txpwr_ptr1 = (u8 *)(& txpwr->mcs_20_siso); txpwr_ptr2 = (u8 *)(& txpwr->ofdm); rate_start_index = 4; goto ldv_37914; case 1: txpwr_ptr1 = (u8 *)(& txpwr->mcs_20_cdd); txpwr_ptr2 = (u8 *)(& txpwr->ofdm_cdd); rate_start_index = 12; goto ldv_37914; case 2: txpwr_ptr1 = (u8 *)(& txpwr->mcs_40_siso); txpwr_ptr2 = (u8 *)(& txpwr->ofdm_40_siso); rate_start_index = 52; goto ldv_37914; case 3: txpwr_ptr1 = (u8 *)(& txpwr->mcs_40_cdd); txpwr_ptr2 = (u8 *)(& txpwr->ofdm_40_cdd); rate_start_index = 60; goto ldv_37914; } ldv_37914: rate2 = 0; goto ldv_37919; ldv_37918: tmp_txpwr_limit[rate2] = 0U; tmp_txpwr_limit[rate2 + 8] = *(txpwr_ptr1 + (unsigned long )rate2); rate2 = rate2 + 1; ldv_37919: ; if (rate2 <= 7) { goto ldv_37918; } else { } wlc_phy_mcs_to_ofdm_powers_nphy((u8 *)(& tmp_txpwr_limit), 0, 7, 8); rate1 = rate_start_index; rate2 = 0; goto ldv_37925; ldv_37924: _min1 = *(txpwr_ptr2 + (unsigned long )rate2); _min2 = tmp_txpwr_limit[rate2]; pi->txpwr_limit[rate1] = (u8 )((int )_min1 < (int )_min2 ? _min1 : _min2); rate1 = rate1 + 1; rate2 = rate2 + 1; ldv_37925: ; if (rate2 <= 7) { goto ldv_37924; } else { } k = k + 1; ldv_37928: ; if (k <= 3) { goto ldv_37927; } else { } k = 0; goto ldv_37945; ldv_37944: ; switch (k) { case 0: txpwr_ptr1 = (u8 *)(& txpwr->ofdm); txpwr_ptr2 = (u8 *)(& txpwr->mcs_20_siso); rate_start_index = 20; goto ldv_37931; case 1: txpwr_ptr1 = (u8 *)(& txpwr->ofdm_cdd); txpwr_ptr2 = (u8 *)(& txpwr->mcs_20_cdd); rate_start_index = 28; goto ldv_37931; case 2: txpwr_ptr1 = (u8 *)(& txpwr->ofdm_40_siso); txpwr_ptr2 = (u8 *)(& txpwr->mcs_40_siso); rate_start_index = 68; goto ldv_37931; case 3: txpwr_ptr1 = (u8 *)(& txpwr->ofdm_40_cdd); txpwr_ptr2 = (u8 *)(& txpwr->mcs_40_cdd); rate_start_index = 76; goto ldv_37931; } ldv_37931: rate2 = 0; goto ldv_37936; ldv_37935: tmp_txpwr_limit[rate2] = 0U; tmp_txpwr_limit[rate2 + 8] = *(txpwr_ptr1 + (unsigned long )rate2); rate2 = rate2 + 1; ldv_37936: ; if (rate2 <= 7) { goto ldv_37935; } else { } wlc_phy_ofdm_to_mcs_powers_nphy((u8 *)(& tmp_txpwr_limit), 0, 7, 8); rate1 = rate_start_index; rate2 = 0; goto ldv_37942; ldv_37941: _min1___0 = *(txpwr_ptr2 + (unsigned long )rate2); _min2___0 = tmp_txpwr_limit[rate2]; pi->txpwr_limit[rate1] = (u8 )((int )_min1___0 < (int )_min2___0 ? _min1___0 : _min2___0); rate1 = rate1 + 1; rate2 = rate2 + 1; ldv_37942: ; if (rate2 <= 7) { goto ldv_37941; } else { } k = k + 1; ldv_37945: ; if (k <= 3) { goto ldv_37944; } else { } k = 0; goto ldv_37954; ldv_37953: ; switch (k) { case 0: rate_start_index = 36; txpwr_ptr1 = (u8 *)(& txpwr->mcs_20_stbc); goto ldv_37948; case 1: rate_start_index = 84; txpwr_ptr1 = (u8 *)(& txpwr->mcs_40_stbc); goto ldv_37948; } ldv_37948: rate1 = rate_start_index; rate2 = 0; goto ldv_37951; ldv_37950: pi->txpwr_limit[rate1] = *(txpwr_ptr1 + (unsigned long )rate2); rate1 = rate1 + 1; rate2 = rate2 + 1; ldv_37951: ; if (rate2 <= 7) { goto ldv_37950; } else { } k = k + 1; ldv_37954: ; if (k <= 1) { goto ldv_37953; } else { } k = 0; goto ldv_37963; ldv_37962: ; switch (k) { case 0: rate_start_index = 44; txpwr_ptr1 = (u8 *)(& txpwr->mcs_20_mimo); goto ldv_37957; case 1: rate_start_index = 92; txpwr_ptr1 = (u8 *)(& txpwr->mcs_40_mimo); goto ldv_37957; } ldv_37957: rate1 = rate_start_index; rate2 = 0; goto ldv_37960; ldv_37959: pi->txpwr_limit[rate1] = *(txpwr_ptr1 + (unsigned long )rate2); rate1 = rate1 + 1; rate2 = rate2 + 1; ldv_37960: ; if (rate2 <= 7) { goto ldv_37959; } else { } k = k + 1; ldv_37963: ; if (k <= 1) { goto ldv_37962; } else { } pi->txpwr_limit[100] = txpwr->mcs32; _min1___1 = pi->txpwr_limit[76]; _min2___1 = pi->txpwr_limit[100]; pi->txpwr_limit[76] = (u8 )((int )_min1___1 < (int )_min2___1 ? _min1___1 : _min2___1); pi->txpwr_limit[100] = pi->txpwr_limit[76]; } else { } return; } } void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi , u8 txpwr_percent ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; pi->txpwr_percent = txpwr_percent; return; } } void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi , u32 machwcap ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; (pi->sh)->machwcap = machwcap; return; } } void wlc_phy_runbist_config(struct brcms_phy_pub *ppi , bool start_end ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u16 rxc ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; rxc = 0U; if ((int )start_end) { if (pi->pubpi.phy_type != 4U) { return; } else { } if (pi->pubpi.phy_rev == 3U || pi->pubpi.phy_rev == 4U) { bcma_write16(pi->d11core, 1020, 160U); bcma_set16(pi->d11core, 1022, 32768); } else { } } else { if (pi->pubpi.phy_rev == 3U || pi->pubpi.phy_rev == 4U) { bcma_write16(pi->d11core, 1020, 160U); bcma_write16(pi->d11core, 1022, (u32 )rxc); } else { } wlc_phy_por_inform(ppi); } return; } } void wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi , struct txpwr_limits *txpwr , u16 chanspec ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; int i ; int j ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; wlc_phy_txpower_reg_limit_calc(pi, txpwr, (int )chanspec); if (pi->pubpi.phy_type == 8U) { i = 12; j = 0; goto ldv_38001; ldv_38000: ; if ((unsigned int )txpwr->mcs_20_siso[j] != 0U) { pi->txpwr_limit[i] = txpwr->mcs_20_siso[j]; } else { pi->txpwr_limit[i] = txpwr->ofdm[j]; } i = i + 1; j = j + 1; ldv_38001: ; if (j <= 7) { goto ldv_38000; } else { } } else { } wlapi_suspend_mac_and_wait((pi->sh)->physhim); wlc_phy_txpower_recalc_target(pi); wlc_phy_cal_txpower_recalc_sw(pi); wlapi_enable_mac((pi->sh)->physhim); return; } } void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih , bool war ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; pi->ofdm_rateset_war = war; return; } } void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih , bool bf_preempt ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; pi->bf_preempt_4306 = bf_preempt; return; } } void wlc_phy_txpower_update_shm(struct brcms_phy *pi ) { int j ; u16 offset ; u8 ucode_ofdm_rates[8U] ; int i ; int __y ; { if (pi->pubpi.phy_type == 4U) { return; } else { } if (! (pi->sh)->clk) { return; } else { } if ((int )pi->hwpwrctrl) { wlapi_bmac_write_shm((pi->sh)->physhim, 40U, 63); wlapi_bmac_write_shm((pi->sh)->physhim, 36U, 16); wlapi_bmac_write_shm((pi->sh)->physhim, 38U, (int )((u16 )pi->tx_power_min) << 4U); wlapi_bmac_write_shm((pi->sh)->physhim, 50U, (int )pi->hwpwr_txcur); j = 4; goto ldv_38024; ldv_38023: ucode_ofdm_rates[0] = 12U; ucode_ofdm_rates[1] = 18U; ucode_ofdm_rates[2] = 24U; ucode_ofdm_rates[3] = 36U; ucode_ofdm_rates[4] = 48U; ucode_ofdm_rates[5] = 72U; ucode_ofdm_rates[6] = 96U; ucode_ofdm_rates[7] = 108U; offset = wlapi_bmac_rate_shm_offset((pi->sh)->physhim, (int )ucode_ofdm_rates[j + -4]); wlapi_bmac_write_shm((pi->sh)->physhim, (uint )((int )offset + 6), (int )((u16 )pi->tx_power_offset[j])); wlapi_bmac_write_shm((pi->sh)->physhim, (uint )((int )offset + 14), - ((int )((u16 )((int )pi->tx_power_offset[j] / 2)))); j = j + 1; ldv_38024: ; if (j <= 11) { goto ldv_38023; } else { } wlapi_bmac_mhf((pi->sh)->physhim, 1, 128, 128, 3); } else { i = 4; goto ldv_38030; ldv_38029: __y = 8; pi->tx_power_offset[i] = (s8 )((((int )pi->tx_power_offset[i] + (__y + -1)) / __y) * __y); i = i + 1; ldv_38030: ; if (i <= 11) { goto ldv_38029; } else { } wlapi_bmac_write_shm((pi->sh)->physhim, 78U, (int )((unsigned short )(((int )pi->tx_power_offset[4] + 7) >> 3))); } return; } } bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; if (pi->pubpi.phy_type == 4U) { return ((unsigned int )pi->nphy_txpwrctrl != 0U); } else { return (pi->hwpwrctrl); } } } void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi , bool hwpwrctrl ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; bool suspend ; u32 tmp ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; if (! pi->hwpwrctrl_capable) { return; } else { } pi->hwpwrctrl = hwpwrctrl; pi->nphy_txpwrctrl = (u8 )hwpwrctrl; pi->txpwrctrl = (u8 )hwpwrctrl; if (pi->pubpi.phy_type == 4U) { tmp = bcma_read32(pi->d11core, 288); suspend = (tmp & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_phy_txpwrctrl_enable_nphy(pi, (int )pi->nphy_txpwrctrl); if ((unsigned int )pi->nphy_txpwrctrl == 0U) { wlc_phy_txpwr_fixpower_nphy(pi); } else { mod_phy_reg(pi, 487, 127, (int )pi->saved_txpwr_idx); } if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } } else { } return; } } void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi ) { { if (pi->pubpi.phy_rev > 2U) { pi->ipa2g_on = (unsigned int )pi->srom_fem2g.extpagain == 2U; pi->ipa5g_on = (unsigned int )pi->srom_fem5g.extpagain == 2U; } else { pi->ipa2g_on = 0; pi->ipa5g_on = 0; } return; } } static u32 wlc_phy_txpower_est_power_nphy(struct brcms_phy *pi ) { s16 tx0_status ; s16 tx1_status ; u16 estPower1 ; u16 estPower2 ; u8 pwr0 ; u8 pwr1 ; u8 adj_pwr0 ; u8 adj_pwr1 ; u32 est_pwr ; u16 tmp ; u16 tmp___0 ; { estPower1 = read_phy_reg(pi, 280); estPower2 = read_phy_reg(pi, 281); if (((int )estPower1 & 256) != 0) { pwr0 = (u8 )estPower1; } else { pwr0 = 128U; } if (((int )estPower2 & 256) != 0) { pwr1 = (u8 )estPower2; } else { pwr1 = 128U; } tmp = read_phy_reg(pi, 493); tx0_status = (s16 )tmp; tmp___0 = read_phy_reg(pi, 494); tx1_status = (s16 )tmp___0; if ((int )tx0_status < 0) { adj_pwr0 = (u8 )tx0_status; } else { adj_pwr0 = 128U; } if ((int )tx1_status < 0) { adj_pwr1 = (u8 )tx1_status; } else { adj_pwr1 = 128U; } est_pwr = (unsigned int )(((((int )pwr0 << 24) | ((int )pwr1 << 16)) | ((int )adj_pwr0 << 8)) | (int )adj_pwr1); return (est_pwr); } } void wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi , struct tx_power *power , uint channel ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; uint rate ; uint num_rates ; u8 min_pwr ; u8 max_pwr ; u32 est_pout ; bool tmp ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; if (pi->pubpi.phy_type == 4U) { power->rf_cores = 2U; power->flags = power->flags | 4U; if ((unsigned int )pi->nphy_txpwrctrl == 1U) { power->flags = power->flags | 3U; } else { } } else if (pi->pubpi.phy_type == 8U) { power->rf_cores = 1U; power->flags = power->flags | 8U; if ((int )pi->radiopwr_override == -1) { power->flags = power->flags | 1U; } else { } if ((int )pi->hwpwrctrl) { power->flags = power->flags | 2U; } else { } } else { } num_rates = pi->pubpi.phy_type != 4U ? (pi->pubpi.phy_type == 8U ? 20U : 12U) : 101U; rate = 0U; goto ldv_38074; ldv_38073: power->user_limit[rate] = pi->tx_user_target[rate]; wlc_phy_txpower_sromlimit(ppi, channel, & min_pwr, & max_pwr, (int )rate); power->board_limit[rate] = max_pwr; power->target[rate] = pi->tx_power_target[rate]; rate = rate + 1U; ldv_38074: ; if (rate < num_rates) { goto ldv_38073; } else { } if (pi->pubpi.phy_type == 4U) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); wlc_phyreg_enter((struct brcms_phy_pub *)pi); est_pout = wlc_phy_txpower_est_power_nphy(pi); wlc_phyreg_exit((struct brcms_phy_pub *)pi); wlapi_enable_mac((pi->sh)->physhim); power->est_Pout[0] = (u8 )(est_pout >> 8); power->est_Pout[1] = (u8 )est_pout; power->est_Pout_act[0] = (u8 )(est_pout >> 24); power->est_Pout_act[1] = (u8 )(est_pout >> 16); if ((unsigned int )power->est_Pout[0] == 128U) { power->est_Pout[0] = 0U; } else { } if ((unsigned int )power->est_Pout[1] == 128U) { power->est_Pout[1] = 0U; } else { } if ((unsigned int )power->est_Pout_act[0] == 128U) { power->est_Pout_act[0] = 0U; } else { } if ((unsigned int )power->est_Pout_act[1] == 128U) { power->est_Pout_act[1] = 0U; } else { } power->est_Pout_cck = 0U; power->tx_power_max[0] = pi->tx_power_max; power->tx_power_max[1] = pi->tx_power_max; power->tx_power_max_rate_ind[0] = pi->tx_power_max_rate_ind; power->tx_power_max_rate_ind[1] = pi->tx_power_max_rate_ind; } else if ((int )pi->hwpwrctrl && (int )(pi->sh)->up) { wlc_phyreg_enter(ppi); if (pi->pubpi.phy_type == 8U) { power->tx_power_max[0] = pi->tx_power_max; power->tx_power_max[1] = pi->tx_power_max; power->tx_power_max_rate_ind[0] = pi->tx_power_max_rate_ind; power->tx_power_max_rate_ind[1] = pi->tx_power_max_rate_ind; tmp = wlc_phy_tpc_isenabled_lcnphy(pi); if ((int )tmp) { power->flags = power->flags | 3U; } else { power->flags = power->flags & 4294967292U; } wlc_lcnphy_get_tssi(pi, (s8 *)(& power->est_Pout), (s8 *)(& power->est_Pout_cck)); } else { } wlc_phyreg_exit(ppi); } else { } return; } } void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi , u8 antsel_type ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; pi->antsel_type = antsel_type; return; } } bool wlc_phy_test_ison(struct brcms_phy_pub *ppi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; return (pi->phytest_on); } } void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi , u8 val ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; bool suspend ; u32 tmp ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; (pi->sh)->rx_antdiv = val; if (pi->pubpi.phy_type != 4U || (pi->sh)->corerev != 16U) { if ((unsigned int )val > 1U) { wlapi_bmac_mhf((pi->sh)->physhim, 0, 1, 1, 3); } else { wlapi_bmac_mhf((pi->sh)->physhim, 0, 1, 0, 3); } } else { } if (pi->pubpi.phy_type == 4U) { return; } else { } if (! (pi->sh)->clk) { return; } else { } tmp = bcma_read32(pi->d11core, 288); suspend = (tmp & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } if (pi->pubpi.phy_type == 8U) { if ((unsigned int )val > 1U) { mod_phy_reg(pi, 1040, 2, 2); mod_phy_reg(pi, 1040, 1, (unsigned int )val == 2U); } else { mod_phy_reg(pi, 1040, 2, 0); mod_phy_reg(pi, 1040, 1, (int )val); } } else { } if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } return; } } static bool wlc_phy_noise_calc_phy(struct brcms_phy *pi , u32 *cmplx_pwr , s8 *pwr_ant ) { s8 cmplx_pwr_dbm[4U] ; u8 i ; { memset((void *)(& cmplx_pwr_dbm), 0, 4UL); wlc_phy_compute_dB(cmplx_pwr, (s8 *)(& cmplx_pwr_dbm), (int )pi->pubpi.phy_corenum); i = 0U; goto ldv_38106; ldv_38105: ; if (pi->pubpi.phy_rev > 2U) { cmplx_pwr_dbm[(int )i] = (s8 )((unsigned int )((unsigned char )cmplx_pwr_dbm[(int )i]) + 153U); } else { cmplx_pwr_dbm[(int )i] = (s8 )((unsigned int )((unsigned char )cmplx_pwr_dbm[(int )i]) + 157U); } i = (u8 )((int )i + 1); ldv_38106: ; if ((int )pi->pubpi.phy_corenum > (int )i) { goto ldv_38105; } else { } i = 0U; goto ldv_38109; ldv_38108: pi->nphy_noise_win[(int )i][(int )pi->nphy_noise_index] = (s16 )cmplx_pwr_dbm[(int )i]; *(pwr_ant + (unsigned long )i) = cmplx_pwr_dbm[(int )i]; i = (u8 )((int )i + 1); ldv_38109: ; if ((int )pi->pubpi.phy_corenum > (int )i) { goto ldv_38108; } else { } pi->nphy_noise_index = (unsigned int )((u8 )((unsigned int )pi->nphy_noise_index + 1U)) & 15U; return (1); } } static void wlc_phy_noise_cb(struct brcms_phy *pi , u8 channel , s8 noise_dbm ) { { if ((unsigned int )pi->phynoise_state == 0U) { return; } else { } if ((int )pi->phynoise_state & 1) { if (pi->phynoise_chan_watchdog == (int )channel) { (pi->sh)->phy_noise_window[(pi->sh)->phy_noise_index] = noise_dbm; (pi->sh)->phy_noise_index = (pi->sh)->phy_noise_index != 7U ? (pi->sh)->phy_noise_index + 1U : 0U; } else { } pi->phynoise_state = (unsigned int )pi->phynoise_state & 254U; } else { } if (((int )pi->phynoise_state & 2) != 0) { pi->phynoise_state = (unsigned int )pi->phynoise_state & 253U; } else { } return; } } static s8 wlc_phy_noise_read_shmem(struct brcms_phy *pi ) { u32 cmplx_pwr[4U] ; s8 noise_dbm_ant[4U] ; u16 lo ; u16 hi ; u32 cmplx_pwr_tot ; s8 noise_dbm ; u8 idx ; u8 core ; { cmplx_pwr_tot = 0U; noise_dbm = -92; memset((void *)(& cmplx_pwr), 0, 16UL); memset((void *)(& noise_dbm_ant), 0, 4UL); idx = 0U; core = 0U; goto ldv_38128; ldv_38127: lo = wlapi_bmac_read_shm((pi->sh)->physhim, (uint )(((int )idx << 1) + 776)); hi = wlapi_bmac_read_shm((pi->sh)->physhim, (uint )((((int )idx + 1) << 1) + 776)); cmplx_pwr[(int )core] = (u32 )(((int )hi << 16) + (int )lo); cmplx_pwr_tot = cmplx_pwr[(int )core] + cmplx_pwr_tot; if (cmplx_pwr[(int )core] == 0U) { noise_dbm_ant[(int )core] = -92; } else { cmplx_pwr[(int )core] = cmplx_pwr[(int )core] >> 9; } idx = (unsigned int )idx + 2U; core = (u8 )((int )core + 1); ldv_38128: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38127; } else { } if (cmplx_pwr_tot != 0U) { wlc_phy_noise_calc_phy(pi, (u32 *)(& cmplx_pwr), (s8 *)(& noise_dbm_ant)); } else { } core = 0U; goto ldv_38131; ldv_38130: pi->nphy_noise_win[(int )core][(int )pi->nphy_noise_index] = (s16 )noise_dbm_ant[(int )core]; if ((int )noise_dbm_ant[(int )core] > (int )noise_dbm) { noise_dbm = noise_dbm_ant[(int )core]; } else { } core = (u8 )((int )core + 1); ldv_38131: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38130; } else { } pi->nphy_noise_index = (unsigned int )((u8 )((unsigned int )pi->nphy_noise_index + 1U)) & 15U; return (noise_dbm); } } void wlc_phy_noise_sample_intr(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u16 jssi_aux ; u8 channel ; s8 noise_dbm ; u32 cmplx_pwr ; u32 cmplx_pwr0 ; u32 cmplx_pwr1 ; u16 lo ; u16 hi ; s32 pwr_offset_dB ; s32 gain_dB ; u16 status_0 ; u16 status_1 ; u16 tmp ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; channel = 0U; noise_dbm = -92; if (pi->pubpi.phy_type == 8U) { jssi_aux = wlapi_bmac_read_shm((pi->sh)->physhim, 140U); channel = (u8 )jssi_aux; lo = wlapi_bmac_read_shm((pi->sh)->physhim, 776U); hi = wlapi_bmac_read_shm((pi->sh)->physhim, 778U); cmplx_pwr0 = (u32 )(((int )hi << 16) + (int )lo); lo = wlapi_bmac_read_shm((pi->sh)->physhim, 780U); hi = wlapi_bmac_read_shm((pi->sh)->physhim, 782U); cmplx_pwr1 = (u32 )(((int )hi << 16) + (int )lo); cmplx_pwr = (cmplx_pwr0 + cmplx_pwr1) >> 6; status_0 = 68U; status_1 = wlapi_bmac_read_shm((pi->sh)->physhim, 136U); if ((cmplx_pwr != 0U && cmplx_pwr <= 499U) && ((int )status_1 & 49152) == 16384) { wlc_phy_compute_dB(& cmplx_pwr, & noise_dbm, (int )pi->pubpi.phy_corenum); tmp = read_phy_reg(pi, 1076); pwr_offset_dB = (int )tmp & 255; if (pwr_offset_dB > 127) { pwr_offset_dB = pwr_offset_dB + -256; } else { } noise_dbm = (s8 )((unsigned int )((int )((unsigned char )pwr_offset_dB) + (int )((unsigned char )noise_dbm)) - 30U); gain_dB = (int )status_0 & 511; noise_dbm = (s8 )((int )((unsigned char )noise_dbm) - (int )((unsigned char )gain_dB)); } else { noise_dbm = -92; } } else if (pi->pubpi.phy_type == 4U) { jssi_aux = wlapi_bmac_read_shm((pi->sh)->physhim, 140U); channel = (u8 )jssi_aux; noise_dbm = wlc_phy_noise_read_shmem(pi); } else { } wlc_phy_noise_cb(pi, (int )channel, (int )noise_dbm); return; } } static void wlc_phy_noise_sample_request(struct brcms_phy_pub *pih , u8 reason , u8 ch ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; s8 noise_dbm ; bool sampling_in_progress ; bool wait_for_intr ; s32 tmp ; struct phy_iq_est est[4U] ; u32 cmplx_pwr[4U] ; s8 noise_dbm_ant[4U] ; u16 log_num_samps ; u16 num_samps ; u16 classif_state ; u8 wait_time ; u8 wait_crs ; u8 i ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; noise_dbm = -92; sampling_in_progress = (unsigned int )pi->phynoise_state != 0U; wait_for_intr = 1; switch ((int )reason) { case 1: pi->phynoise_chan_watchdog = (int )ch; pi->phynoise_state = (u8 )((unsigned int )pi->phynoise_state | 1U); goto ldv_38163; case 2: pi->phynoise_state = (u8 )((unsigned int )pi->phynoise_state | 2U); goto ldv_38163; default: ; goto ldv_38163; } ldv_38163: ; if ((int )sampling_in_progress) { return; } else { } pi->phynoise_now = (pi->sh)->now; if ((int )pi->phy_fixed_noise) { if (pi->pubpi.phy_type == 4U) { pi->nphy_noise_win[0][(int )pi->nphy_noise_index] = -92; pi->nphy_noise_win[1][(int )pi->nphy_noise_index] = -92; pi->nphy_noise_index = (unsigned int )((u8 )((unsigned int )pi->nphy_noise_index + 1U)) & 15U; noise_dbm = -92; } else { noise_dbm = -95; } wait_for_intr = 0; goto done; } else { } if (pi->pubpi.phy_type == 8U) { if (! pi->phynoise_polling || (unsigned int )reason == 2U) { wlapi_bmac_write_shm((pi->sh)->physhim, 136U, 0); wlapi_bmac_write_shm((pi->sh)->physhim, 776U, 0); wlapi_bmac_write_shm((pi->sh)->physhim, 778U, 0); wlapi_bmac_write_shm((pi->sh)->physhim, 780U, 0); wlapi_bmac_write_shm((pi->sh)->physhim, 782U, 0); bcma_set32(pi->d11core, 292, 16U); } else { wlapi_suspend_mac_and_wait((pi->sh)->physhim); wlc_lcnphy_deaf_mode(pi, 0); tmp = wlc_lcnphy_rx_signal_power(pi, 20); noise_dbm = (signed char )tmp; wlc_lcnphy_deaf_mode(pi, 1); wlapi_enable_mac((pi->sh)->physhim); wait_for_intr = 0; } } else if (pi->pubpi.phy_type == 4U) { if (! pi->phynoise_polling || (unsigned int )reason == 2U) { wlapi_bmac_write_shm((pi->sh)->physhim, 776U, 0); wlapi_bmac_write_shm((pi->sh)->physhim, 778U, 0); wlapi_bmac_write_shm((pi->sh)->physhim, 780U, 0); wlapi_bmac_write_shm((pi->sh)->physhim, 782U, 0); bcma_set32(pi->d11core, 292, 16U); } else { classif_state = 0U; wait_time = 32U; wait_crs = 0U; memset((void *)(& est), 0, 48UL); memset((void *)(& cmplx_pwr), 0, 16UL); memset((void *)(& noise_dbm_ant), 0, 4UL); log_num_samps = 10U; num_samps = (u16 )(1 << (int )log_num_samps); wlapi_suspend_mac_and_wait((pi->sh)->physhim); classif_state = wlc_phy_classifier_nphy(pi, 0, 0); wlc_phy_classifier_nphy(pi, 3, 0); wlc_phy_rx_iq_est_nphy(pi, (struct phy_iq_est *)(& est), (int )num_samps, (int )wait_time, (int )wait_crs); wlc_phy_classifier_nphy(pi, 7, (int )classif_state); wlapi_enable_mac((pi->sh)->physhim); i = 0U; goto ldv_38177; ldv_38176: cmplx_pwr[(int )i] = (est[(int )i].i_pwr + est[(int )i].q_pwr) >> (int )log_num_samps; i = (u8 )((int )i + 1); ldv_38177: ; if ((int )pi->pubpi.phy_corenum > (int )i) { goto ldv_38176; } else { } wlc_phy_noise_calc_phy(pi, (u32 *)(& cmplx_pwr), (s8 *)(& noise_dbm_ant)); i = 0U; goto ldv_38180; ldv_38179: pi->nphy_noise_win[(int )i][(int )pi->nphy_noise_index] = (s16 )noise_dbm_ant[(int )i]; if ((int )noise_dbm_ant[(int )i] > (int )noise_dbm) { noise_dbm = noise_dbm_ant[(int )i]; } else { } i = (u8 )((int )i + 1); ldv_38180: ; if ((int )pi->pubpi.phy_corenum > (int )i) { goto ldv_38179; } else { } pi->nphy_noise_index = (unsigned int )((u8 )((unsigned int )pi->nphy_noise_index + 1U)) & 15U; wait_for_intr = 0; } } else { } done: ; if (! wait_for_intr) { wlc_phy_noise_cb(pi, (int )ch, (int )noise_dbm); } else { } return; } } void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *pih ) { u8 channel ; u16 tmp ; { tmp = wlc_phy_chanspec_get(pih); channel = (unsigned char )tmp; wlc_phy_noise_sample_request(pih, 2, (int )channel); return; } } static s8 const lcnphy_gain_index_offset_for_pkt_rssi[38U] = { 8, 8, 8, 8, 8, 8, 8, 9, 10, 8, 8, 7, 7, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0}; void wlc_phy_compute_dB(u32 *cmplx_pwr , s8 *p_cmplx_pwr_dB , u8 core ) { u8 msb ; u8 secondmsb ; u8 i ; u32 tmp ; int tmp___0 ; { i = 0U; goto ldv_38197; ldv_38196: secondmsb = 0U; tmp = *(cmplx_pwr + (unsigned long )i); tmp___0 = fls((int )tmp); msb = (u8 )tmp___0; if ((unsigned int )msb != 0U) { msb = (u8 )((int )msb - 1); secondmsb = (unsigned int )((unsigned char )(tmp >> ((int )msb + -1))) & 1U; } else { } *(p_cmplx_pwr_dB + (unsigned long )i) = (signed char )((unsigned int )msb * 3U + (unsigned int )secondmsb * 2U); i = (u8 )((int )i + 1); ldv_38197: ; if ((int )i < (int )core) { goto ldv_38196; } else { } return; } } int wlc_phy_rssi_compute(struct brcms_phy_pub *pih , struct d11rxhdr *rxh ) { int rssi ; uint radioid ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u8 gidx ; struct brcms_phy_lcnphy *pi_lcn ; { rssi = (int )rxh->PhyRxStatus_1 & 255; radioid = (uint )pih->radioid; __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if ((pi->sh)->corerev > 10U && ((int )rxh->RxStatus2 & 256) == 0) { rssi = 0; goto end; } else { } if (pi->pubpi.phy_type == 8U) { gidx = (u8 )((int )rxh->PhyRxStatus_2 >> 10); pi_lcn = pi->u.pi_lcnphy; if (rssi > 127) { rssi = rssi + -256; } else { } rssi = (int )lcnphy_gain_index_offset_for_pkt_rssi[(int )gidx] + rssi; if (rssi >= -45 && (unsigned int )gidx > 18U) { rssi = rssi + 7; } else { } rssi = (int )pi_lcn->lcnphy_pkteng_rssi_slope + rssi; rssi = rssi + 2; } else { } if (pi->pubpi.phy_type == 8U) { if (rssi > 127) { rssi = rssi + -256; } else { } } else if ((radioid == 8277U || radioid == 8278U) || radioid == 8279U) { rssi = wlc_phy_rssi_compute_nphy(pi, rxh); } else { } end: ; return (rssi); } } void wlc_phy_freqtrack_start(struct brcms_phy_pub *pih ) { { return; } } void wlc_phy_freqtrack_end(struct brcms_phy_pub *pih ) { { return; } } void wlc_phy_set_deaf(struct brcms_phy_pub *ppi , bool user_flag ) { struct brcms_phy *pi ; { pi = (struct brcms_phy *)ppi; if (pi->pubpi.phy_type == 8U) { wlc_lcnphy_deaf_mode(pi, 1); } else if (pi->pubpi.phy_type == 4U) { wlc_nphy_deaf_mode(pi, 1); } else { } return; } } void wlc_phy_watchdog(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; bool delay_phy_cal ; bool tmp ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; delay_phy_cal = 0; (pi->sh)->now = (pi->sh)->now + 1U; if (! pi->watchdog_override) { return; } else { } if ((pi->measure_hold & 6U) == 0U && (pi->measure_hold & 8U) == 0U) { wlc_phy_noise_sample_request((struct brcms_phy_pub *)pi, 1, (int )((unsigned char )pi->radio_chanspec)); } else { } if ((unsigned int )pi->phynoise_state != 0U && (pi->sh)->now - pi->phynoise_now > 5U) { pi->phynoise_state = 0U; } else { } if (pi->phycal_txpower == 0U || (pi->sh)->now - pi->phycal_txpower >= (pi->sh)->fast_timer) { if ((pi->measure_hold & 2U) == 0U) { tmp = wlc_phy_cal_txpower_recalc_sw(pi); if ((int )tmp) { pi->phycal_txpower = (pi->sh)->now; } else { } } else { } } else { } if (((pi->measure_hold & 6U) != 0U || (pi->measure_hold & 8U) != 0U) || (int )pi->measure_hold & 1) { return; } else { } if ((pi->pubpi.phy_type == 4U && ! pi->disable_percal) && ! delay_phy_cal) { if (((unsigned int )pi->nphy_perical != 0U && (unsigned int )pi->nphy_perical != 3U) && (pi->sh)->now - pi->nphy_perical_last >= (pi->sh)->glacial_timer) { wlc_phy_cal_perical((struct brcms_phy_pub *)pi, 2); } else { } wlc_phy_txpwr_papd_cal_nphy(pi); } else { } if (pi->pubpi.phy_type == 8U) { if ((int )pi->phy_forcecal || (pi->sh)->now - pi->phy_lastcal >= (pi->sh)->glacial_timer) { if ((pi->measure_hold & 6U) == 0U && (pi->measure_hold & 1U) == 0U) { wlc_lcnphy_calib_modes(pi, 9U); } else { } if (((((pi->measure_hold & 6U) == 0U && (pi->measure_hold & 8U) == 0U) && (pi->measure_hold & 1U) == 0U) && (int )pi->carrier_suppr_disable == 0) && ! pi->disable_percal) { wlc_lcnphy_calib_modes(pi, 2U); } else { } } else { } } else { } return; } } void wlc_phy_BSSinit(struct brcms_phy_pub *pih , bool bonlyap , int rssi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; uint i ; uint k ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; i = 0U; goto ldv_38240; ldv_38239: (pi->sh)->phy_noise_window[i] = (signed char )rssi; i = i + 1U; ldv_38240: ; if (i <= 7U) { goto ldv_38239; } else { } if (pi->pubpi.phy_type == 8U) { i = 0U; goto ldv_38243; ldv_38242: (pi->sh)->phy_noise_window[i] = -92; i = i + 1U; ldv_38243: ; if (i <= 7U) { goto ldv_38242; } else { } } else { } (pi->sh)->phy_noise_index = 0U; i = 0U; goto ldv_38249; ldv_38248: k = 0U; goto ldv_38246; ldv_38245: pi->nphy_noise_win[k][i] = -92; k = k + 1U; ldv_38246: ; if (k <= 1U) { goto ldv_38245; } else { } i = i + 1U; ldv_38249: ; if (i <= 15U) { goto ldv_38248; } else { } pi->nphy_noise_index = 0U; return; } } void wlc_phy_papd_decode_epsilon(u32 epsilon , s32 *eps_real , s32 *eps_imag ) { { *eps_imag = (s32 )(epsilon >> 13); if (*eps_imag > 4095) { *eps_imag = *eps_imag + -8192; } else { } *eps_real = (s32 )epsilon & 8191; if (*eps_real > 4095) { *eps_real = *eps_real + -8192; } else { } return; } } void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi ) { { wlapi_del_timer(pi->phycal_timer); pi->cal_type_override = 0U; pi->mphase_cal_phase_id = 0U; pi->mphase_txcal_cmdidx = 0U; return; } } static void wlc_phy_cal_perical_mphase_schedule(struct brcms_phy *pi , uint delay ) { { if ((unsigned int )pi->nphy_perical != 2U && (unsigned int )pi->nphy_perical != 3U) { return; } else { } wlapi_del_timer(pi->phycal_timer); pi->mphase_cal_phase_id = 1U; wlapi_add_timer(pi->phycal_timer, delay, 0); return; } } void wlc_phy_cal_perical(struct brcms_phy_pub *pih , u8 reason ) { s16 nphy_currtemp ; s16 delta_temp ; bool do_periodic_cal ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { nphy_currtemp = 0; delta_temp = 0; do_periodic_cal = 1; __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; if (pi->pubpi.phy_type != 4U) { return; } else { } if ((unsigned int )pi->nphy_perical == 0U || (unsigned int )pi->nphy_perical == 3U) { return; } else { } switch ((int )reason) { case 1: ; goto ldv_38274; case 3: ; if ((unsigned int )pi->nphy_perical == 2U) { if ((unsigned int )pi->mphase_cal_phase_id != 0U) { wlc_phy_cal_perical_mphase_reset(pi); } else { } wlc_phy_cal_perical_mphase_schedule(pi, 5U); } else { } goto ldv_38274; case 4: ; case 5: ; case 6: ; if ((unsigned int )pi->nphy_perical == 2U && (unsigned int )pi->mphase_cal_phase_id != 0U) { wlc_phy_cal_perical_mphase_reset(pi); } else { } pi->first_cal_after_assoc = 1; pi->cal_type_override = 1U; if ((unsigned int )pi->phycal_tempdelta != 0U) { pi->nphy_lastcal_temp = wlc_phy_tempsense_nphy(pi); } else { } wlc_phy_cal_perical_nphy_run(pi, 1); goto ldv_38274; case 2: ; if ((unsigned int )pi->phycal_tempdelta != 0U) { nphy_currtemp = wlc_phy_tempsense_nphy(pi); delta_temp = (int )pi->nphy_lastcal_temp < (int )nphy_currtemp ? (s16 )((int )((unsigned short )nphy_currtemp) - (int )((unsigned short )pi->nphy_lastcal_temp)) : (s16 )((int )((unsigned short )pi->nphy_lastcal_temp) - (int )((unsigned short )nphy_currtemp)); if ((int )delta_temp < (int )pi->phycal_tempdelta && (int )pi->nphy_txiqlocal_chanspec == (int )pi->radio_chanspec) { do_periodic_cal = 0; } else { pi->nphy_lastcal_temp = nphy_currtemp; } } else { } if ((int )do_periodic_cal) { if ((unsigned int )pi->nphy_perical == 2U) { if ((unsigned int )pi->mphase_cal_phase_id == 0U) { wlc_phy_cal_perical_mphase_schedule(pi, 5U); } else { } } else if ((unsigned int )pi->nphy_perical == 1U) { wlc_phy_cal_perical_nphy_run(pi, 0); } else { } } else { } goto ldv_38274; default: ; goto ldv_38274; } ldv_38274: ; return; } } void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi ) { { pi->mphase_cal_phase_id = 1U; pi->mphase_txcal_cmdidx = 0U; return; } } u8 wlc_phy_nbits(s32 value ) { s32 abs_val ; u8 nbits ; long ret ; int __x___0 ; { nbits = 0U; __x___0 = value; ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); abs_val = (s32 )ret; goto ldv_38294; ldv_38293: nbits = (u8 )((int )nbits + 1); ldv_38294: ; if (abs_val >> (int )nbits > 0) { goto ldv_38293; } else { } return (nbits); } } void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih , u8 txchain , u8 rxchain ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; unsigned int tmp ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; (pi->sh)->hw_phytxchain = txchain; (pi->sh)->hw_phyrxchain = rxchain; (pi->sh)->phytxchain = txchain; (pi->sh)->phyrxchain = rxchain; tmp = __arch_hweight8((unsigned int )(pi->sh)->phyrxchain); pi->pubpi.phy_corenum = (unsigned char )tmp; return; } } void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih , u8 txchain , u8 rxchain ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; unsigned int tmp ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; (pi->sh)->phytxchain = txchain; if (pi->pubpi.phy_type == 4U) { wlc_phy_rxcore_setstate_nphy(pih, (int )rxchain); } else { } tmp = __arch_hweight8((unsigned int )(pi->sh)->phyrxchain); pi->pubpi.phy_corenum = (unsigned char )tmp; return; } } void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih , u8 *txchain , u8 *rxchain ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; *txchain = (pi->sh)->phytxchain; *rxchain = (pi->sh)->phyrxchain; return; } } u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih ) { s16 nphy_currtemp ; u8 active_bitmap ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; active_bitmap = (int )pi->phy_txcore_heatedup ? 49U : 51U; if (! pi->watchdog_override) { return (active_bitmap); } else { } if (pi->pubpi.phy_rev > 5U) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); nphy_currtemp = wlc_phy_tempsense_nphy(pi); wlapi_enable_mac((pi->sh)->physhim); if (! pi->phy_txcore_heatedup) { if ((int )pi->phy_txcore_disable_temp <= (int )nphy_currtemp) { active_bitmap = (unsigned int )active_bitmap & 253U; pi->phy_txcore_heatedup = 1; } else { } } else if ((int )pi->phy_txcore_enable_temp >= (int )nphy_currtemp) { active_bitmap = (u8 )((unsigned int )active_bitmap | 2U); pi->phy_txcore_heatedup = 0; } else { } } else { } return (active_bitmap); } } s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih , u16 chanspec ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u8 siso_mcs_id ; u8 cdd_mcs_id ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; siso_mcs_id = ((int )chanspec & 3072) == 3072 ? 68U : 20U; cdd_mcs_id = ((int )chanspec & 3072) == 3072 ? 76U : 28U; if ((int )pi->tx_power_target[(int )siso_mcs_id] > (int )pi->tx_power_target[(int )cdd_mcs_id] + 12) { return (0); } else { return (1); } } } u8 const *wlc_phy_get_ofdm_rate_lookup(void) { { return ((u8 const *)(& ofdm_rate_lookup)); } } void wlc_lcnphy_epa_switch(struct brcms_phy *pi , bool mode ) { u16 txant ; { if ((pi->sh)->chip == 17171U && ((pi->sh)->boardflags & 2048U) != 0U) { if ((int )mode) { txant = 0U; txant = wlapi_bmac_get_txant((pi->sh)->physhim); if ((unsigned int )txant == 1U) { mod_phy_reg(pi, 1101, 4, 4); mod_phy_reg(pi, 1100, 4, 4); } else { } bcma_chipco_gpio_control(& ((pi->d11core)->bus)->drv_cc, 0U, 0U); bcma_chipco_gpio_out(& ((pi->d11core)->bus)->drv_cc, 4294967231U, 64U); bcma_chipco_gpio_outen(& ((pi->d11core)->bus)->drv_cc, 4294967231U, 64U); } else { mod_phy_reg(pi, 1100, 4, 0); mod_phy_reg(pi, 1101, 4, 0); bcma_chipco_gpio_out(& ((pi->d11core)->bus)->drv_cc, 4294967231U, 0U); bcma_chipco_gpio_outen(& ((pi->d11core)->bus)->drv_cc, 4294967231U, 0U); bcma_chipco_gpio_control(& ((pi->d11core)->bus)->drv_cc, 0U, 64U); } } else { } return; } } void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi , bool ldpc ) { { return; } } void wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi , s8 *cckoffset , s8 *ofdmoffset ) { { *cckoffset = 0; *ofdmoffset = 0; return; } } s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi , s8 rssi , u16 chanspec ) { { return (rssi); } } bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *ppi ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; bool tmp ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; if (pi->pubpi.phy_type == 4U) { tmp = wlc_phy_n_txpower_ipa_ison(pi); return (tmp); } else { return (0); } } } bool ldv_queue_work_on_171(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_172(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_173(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_174(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_175(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; __inline static int ffs(int x ) { int r ; { __asm__ ("bsfl %1,%0": "=r" (r): "rm" (x), "0" (-1)); return (r + 1); } } extern unsigned long int_sqrt(unsigned long ) ; bool ldv_queue_work_on_185(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_187(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_186(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_189(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_188(struct workqueue_struct *ldv_func_arg1 ) ; extern struct cordic_iq cordic_calc_iq(s32 ) ; extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc * ) ; extern void bcma_chipco_pll_write(struct bcma_drv_cc * , u32 , u32 ) ; extern void bcma_chipco_pll_maskset(struct bcma_drv_cc * , u32 , u32 , u32 ) ; extern void bcma_chipco_chipctl_maskset(struct bcma_drv_cc * , u32 , u32 , u32 ) ; extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc * , u32 , u32 , u32 ) ; s16 qm_sub16(s16 op1 , s16 op2 ) ; s16 qm_shr16(s16 op , int shift ) ; void qm_log10(s32 N , s16 qN , s16 *log10N , s16 *qLog10N ) ; void wlc_phy_detach_lcnphy(struct brcms_phy *pi ) ; void wlc_phy_init_lcnphy(struct brcms_phy *pi ) ; void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi ) ; void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi , u16 chanspec ) ; void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi , u16 mode ) ; s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi ) ; void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi ) ; void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi ) ; void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi , int index ) ; void wlc_lcnphy_tx_pu(struct brcms_phy *pi , bool bEnable ) ; void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi ) ; void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi , s32 f_kHz , u16 max_val , bool iqcalmode ) ; u16 wlc_lcnphy_tempsense(struct brcms_phy *pi , bool mode ) ; s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi , bool mode ) ; void wlc_lcnphy_crsuprs(struct brcms_phy *pi , int channel ) ; void wlc_2064_vco_cal(struct brcms_phy *pi ) ; void wlc_lcnphy_write_table(struct brcms_phy *pi , struct phytbl_info const *pti ) ; void wlc_lcnphy_read_table(struct brcms_phy *pi , struct phytbl_info *pti ) ; void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi , u16 a , u16 b ) ; void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi , u16 didq ) ; void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi , u16 *a , u16 *b ) ; u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi ) ; void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi , u8 *ei0 , u8 *eq0 , u8 *fi0 , u8 *fq0 ) ; void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi ) ; s32 wlc_lcnphy_tssi2dbm(s32 tssi , s32 a1 , s32 b0 , s32 b1 ) ; void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi ) ; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313 ; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313_bt_ipa ; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313_epa ; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313_bt_epa ; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 ; struct phytbl_info const dot11lcnphytbl_info_rev0[14U] ; unsigned int const dot11lcnphytbl_info_sz_rev0 ; struct phytbl_info const dot11lcnphytbl_rx_gain_info_2G_rev2[4U] ; unsigned int const dot11lcnphytbl_rx_gain_info_2G_rev2_sz ; struct phytbl_info const dot11lcnphytbl_rx_gain_info_5G_rev2[4U] ; unsigned int const dot11lcnphytbl_rx_gain_info_5G_rev2_sz ; struct phytbl_info const dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[4U] ; struct phytbl_info const dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[4U] ; struct lcnphy_tx_gain_tbl_entry const dot11lcnphy_2GHz_gaintable_rev0[128U] ; struct lcnphy_tx_gain_tbl_entry const dot11lcnphy_2GHz_extPA_gaintable_rev0[128U] ; static iqcal_gain_params_lcnphy const tbl_iqcal_gainparams_lcnphy_2G[1U][9U] = { { { 0U}, { 0U}, { 0U}, { 0U}, { 0U}, { 0U}, { 0U}, { 0U}, { 0U}}}; static iqcal_gain_params_lcnphy const *tbl_iqcal_gainparams_lcnphy[1U] = { (iqcal_gain_params_lcnphy const *)(& tbl_iqcal_gainparams_lcnphy_2G)}; static u16 const iqcal_gainparams_numgains_lcnphy[1U] = { 1U}; static struct lcnphy_sfo_cfg const lcnphy_sfo_cfg[14U] = { {965U, 1087U}, {967U, 1085U}, {969U, 1082U}, {971U, 1080U}, {973U, 1078U}, {975U, 1076U}, {977U, 1073U}, {979U, 1071U}, {981U, 1069U}, {983U, 1067U}, {985U, 1065U}, {987U, 1063U}, {989U, 1060U}, {994U, 1055U}}; static u16 const lcnphy_iqcal_loft_gainladder[20U] = { 512U, 768U, 1024U, 1536U, 2048U, 2816U, 4096U, 4097U, 4098U, 4099U, 4100U, 4101U, 4102U, 4103U, 5895U, 8199U, 11527U, 16391U, 23303U, 32775U}; static u16 const lcnphy_iqcal_ir_gainladder[20U] = { 256U, 512U, 1024U, 1536U, 2048U, 2816U, 4096U, 5888U, 8192U, 11520U, 16384U, 16385U, 16386U, 16387U, 16388U, 16389U, 16390U, 16391U, 23303U, 32775U}; static struct lcnphy_spb_tone const lcnphy_spb_tone_3750[32U] = { {88, 0}, {73, 49}, {34, 81}, {-17, 86}, {-62, 62}, {-86, 17}, {-81, -34}, {-49, -73}, {0, -88}, {49, -73}, {81, -34}, {86, 17}, {62, 62}, {17, 86}, {-34, 81}, {-73, 49}, {-88, 0}, {-73, -49}, {-34, -81}, {17, -86}, {62, -62}, {86, -17}, {81, 34}, {49, 73}, {0, 88}, {-49, 73}, {-81, 34}, {-86, -17}, {-62, -62}, {-17, -86}, {34, -81}, {73, -49}}; static u16 const iqlo_loopback_rf_regs[20U] = { 54U, 282U, 58U, 37U, 40U, 5U, 274U, 255U, 287U, 11U, 275U, 7U, 252U, 253U, 18U, 87U, 89U, 92U, 120U, 146U}; static u16 const tempsense_phy_regs[14U] = { 1283U, 1188U, 1232U, 1241U, 1242U, 1190U, 2360U, 2361U, 1240U, 1232U, 1239U, 1189U, 1037U, 1186U}; static u16 const rxiq_cal_rf_reg[11U] = { 152U, 278U, 300U, 106U, 11U, 27U, 275U, 29U, 276U, 46U, 298U}; static struct lcnphy_rx_iqcomp const lcnphy_rx_iqcomp_table_rev0[51U] = { {1U, 0, 0}, {2U, 0, 0}, {3U, 0, 0}, {4U, 0, 0}, {5U, 0, 0}, {6U, 0, 0}, {7U, 0, 0}, {8U, 0, 0}, {9U, 0, 0}, {10U, 0, 0}, {11U, 0, 0}, {12U, 0, 0}, {13U, 0, 0}, {14U, 0, 0}, {34U, 0, 0}, {38U, 0, 0}, {42U, 0, 0}, {46U, 0, 0}, {36U, 0, 0}, {40U, 0, 0}, {44U, 0, 0}, {48U, 0, 0}, {52U, 0, 0}, {56U, 0, 0}, {60U, 0, 0}, {64U, 0, 0}, {100U, 0, 0}, {104U, 0, 0}, {108U, 0, 0}, {112U, 0, 0}, {116U, 0, 0}, {120U, 0, 0}, {124U, 0, 0}, {128U, 0, 0}, {132U, 0, 0}, {136U, 0, 0}, {140U, 0, 0}, {149U, 0, 0}, {153U, 0, 0}, {157U, 0, 0}, {161U, 0, 0}, {165U, 0, 0}, {184U, 0, 0}, {188U, 0, 0}, {192U, 0, 0}, {196U, 0, 0}, {200U, 0, 0}, {204U, 0, 0}, {208U, 0, 0}, {212U, 0, 0}, {216U, 0, 0}}; static u32 const lcnphy_23bitgaincode_table[37U] = { 2097408U, 2097664U, 2097156U, 2097172U, 2097188U, 2097204U, 2097460U, 2097716U, 2097972U, 2098228U, 2097207U, 2097463U, 2097719U, 2097975U, 2098231U, 53U, 309U, 565U, 55U, 311U, 567U, 823U, 319U, 575U, 831U, 847U, 1103U, 5199U, 9295U, 9551U, 13647U, 17743U, 17999U, 83535U, 149071U, 214607U, 280143U}; static s8 const lcnphy_gain_table[37U] = { -16, -13, 10, 7, 4, 0, 3, 6, 9, 12, 15, 18, 21, 24, 27, 30, 33, 36, 39, 42, 45, 48, 50, 53, 56, 59, 62, 65, 68, 71, 74, 77, 80, 83, 86, 89, 92}; static s8 const lcnphy_gain_index_offset_for_rssi[38U] = { 7, 7, 7, 7, 7, 7, 7, 8, 7, 7, 6, 7, 7, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 4, 2, 2, 2, 2, 2, 2, -1, -2, -2, -2}; static struct chan_info_2064_lcnphy const chan_info_2064_lcnphy[14U] = { {1U, 2412U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {2U, 2417U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {3U, 2422U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {4U, 2427U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {5U, 2432U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {6U, 2437U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {7U, 2442U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {8U, 2447U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {9U, 2452U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {10U, 2457U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {11U, 2462U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {12U, 2467U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {13U, 2472U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}, {14U, 2484U, 11U, 10U, 0U, 7U, 10U, 136U, 136U, 128U}}; static struct lcnphy_radio_regs const lcnphy_radio_regs_2064[306U] = { {0U, 0U, 0U, 0U, 0U}, {1U, 100U, 100U, 0U, 0U}, {2U, 32U, 32U, 0U, 0U}, {3U, 102U, 102U, 0U, 0U}, {4U, 248U, 248U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 16U, 16U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 55U, 55U, 0U, 0U}, {11U, 6U, 6U, 0U, 0U}, {12U, 85U, 85U, 0U, 0U}, {13U, 139U, 139U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 5U, 5U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 14U, 14U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 11U, 11U, 0U, 0U}, {20U, 2U, 2U, 0U, 0U}, {21U, 18U, 18U, 0U, 0U}, {22U, 18U, 18U, 0U, 0U}, {23U, 12U, 12U, 0U, 0U}, {24U, 12U, 12U, 0U, 0U}, {25U, 12U, 12U, 0U, 0U}, {26U, 8U, 8U, 0U, 0U}, {27U, 2U, 2U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 1U, 1U, 0U, 0U}, {30U, 18U, 18U, 0U, 0U}, {31U, 110U, 110U, 0U, 0U}, {32U, 2U, 2U, 0U, 0U}, {33U, 35U, 35U, 0U, 0U}, {34U, 8U, 8U, 0U, 0U}, {35U, 0U, 0U, 0U, 0U}, {36U, 0U, 0U, 0U, 0U}, {37U, 12U, 12U, 0U, 0U}, {38U, 51U, 51U, 0U, 0U}, {39U, 85U, 85U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 48U, 48U, 0U, 0U}, {42U, 11U, 11U, 0U, 0U}, {43U, 27U, 27U, 0U, 0U}, {44U, 3U, 3U, 0U, 0U}, {45U, 27U, 27U, 0U, 0U}, {46U, 0U, 0U, 0U, 0U}, {47U, 32U, 32U, 0U, 0U}, {48U, 10U, 10U, 0U, 0U}, {49U, 0U, 0U, 0U, 0U}, {50U, 98U, 98U, 0U, 0U}, {51U, 25U, 25U, 0U, 0U}, {52U, 51U, 51U, 0U, 0U}, {53U, 119U, 119U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 112U, 112U, 0U, 0U}, {56U, 3U, 3U, 0U, 0U}, {57U, 15U, 15U, 0U, 0U}, {58U, 6U, 6U, 0U, 0U}, {59U, 207U, 207U, 0U, 0U}, {60U, 26U, 26U, 0U, 0U}, {61U, 6U, 6U, 0U, 0U}, {62U, 66U, 66U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 251U, 251U, 0U, 0U}, {65U, 154U, 154U, 0U, 0U}, {66U, 122U, 122U, 0U, 0U}, {67U, 41U, 41U, 0U, 0U}, {68U, 0U, 0U, 0U, 0U}, {69U, 8U, 8U, 0U, 0U}, {70U, 206U, 206U, 0U, 0U}, {71U, 39U, 39U, 0U, 0U}, {72U, 98U, 98U, 0U, 0U}, {73U, 6U, 6U, 0U, 0U}, {74U, 88U, 88U, 0U, 0U}, {75U, 247U, 247U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 179U, 179U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 2U, 2U, 0U, 0U}, {80U, 0U, 0U, 0U, 0U}, {81U, 9U, 9U, 0U, 0U}, {82U, 5U, 5U, 0U, 0U}, {83U, 23U, 23U, 0U, 0U}, {84U, 56U, 56U, 0U, 0U}, {85U, 0U, 0U, 0U, 0U}, {86U, 0U, 0U, 0U, 0U}, {87U, 11U, 11U, 0U, 0U}, {88U, 0U, 0U, 0U, 0U}, {89U, 0U, 0U, 0U, 0U}, {90U, 0U, 0U, 0U, 0U}, {91U, 0U, 0U, 0U, 0U}, {92U, 0U, 0U, 0U, 0U}, {93U, 0U, 0U, 0U, 0U}, {94U, 136U, 136U, 0U, 0U}, {95U, 204U, 204U, 0U, 0U}, {96U, 116U, 116U, 0U, 0U}, {97U, 116U, 116U, 0U, 0U}, {98U, 116U, 116U, 0U, 0U}, {99U, 68U, 68U, 0U, 0U}, {100U, 119U, 119U, 0U, 0U}, {101U, 68U, 68U, 0U, 0U}, {102U, 119U, 119U, 0U, 0U}, {103U, 85U, 85U, 0U, 0U}, {104U, 119U, 119U, 0U, 0U}, {105U, 119U, 119U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 127U, 127U, 0U, 0U}, {108U, 8U, 8U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 136U, 136U, 0U, 0U}, {111U, 102U, 102U, 0U, 0U}, {112U, 102U, 102U, 0U, 0U}, {113U, 40U, 40U, 0U, 0U}, {114U, 85U, 85U, 0U, 0U}, {115U, 4U, 4U, 0U, 0U}, {116U, 0U, 0U, 0U, 0U}, {117U, 0U, 0U, 0U, 0U}, {118U, 0U, 0U, 0U, 0U}, {119U, 1U, 1U, 0U, 0U}, {120U, 214U, 214U, 0U, 0U}, {121U, 0U, 0U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 180U, 180U, 0U, 0U}, {132U, 1U, 1U, 0U, 0U}, {133U, 32U, 32U, 0U, 0U}, {134U, 5U, 5U, 0U, 0U}, {135U, 255U, 255U, 0U, 0U}, {136U, 7U, 7U, 0U, 0U}, {137U, 119U, 119U, 0U, 0U}, {138U, 119U, 119U, 0U, 0U}, {139U, 119U, 119U, 0U, 0U}, {140U, 119U, 119U, 0U, 0U}, {141U, 8U, 8U, 0U, 0U}, {142U, 10U, 10U, 0U, 0U}, {143U, 8U, 8U, 0U, 0U}, {144U, 24U, 24U, 0U, 0U}, {145U, 5U, 5U, 0U, 0U}, {146U, 31U, 31U, 0U, 0U}, {147U, 16U, 16U, 0U, 0U}, {148U, 3U, 3U, 0U, 0U}, {149U, 0U, 0U, 0U, 0U}, {150U, 0U, 0U, 0U, 0U}, {151U, 170U, 170U, 0U, 0U}, {152U, 0U, 0U, 0U, 0U}, {153U, 35U, 35U, 0U, 0U}, {154U, 7U, 7U, 0U, 0U}, {155U, 15U, 15U, 0U, 0U}, {156U, 16U, 16U, 0U, 0U}, {157U, 3U, 3U, 0U, 0U}, {158U, 4U, 4U, 0U, 0U}, {159U, 32U, 32U, 0U, 0U}, {160U, 0U, 0U, 0U, 0U}, {161U, 0U, 0U, 0U, 0U}, {162U, 0U, 0U, 0U, 0U}, {163U, 0U, 0U, 0U, 0U}, {164U, 1U, 1U, 0U, 0U}, {165U, 119U, 119U, 0U, 0U}, {166U, 119U, 119U, 0U, 0U}, {167U, 119U, 119U, 0U, 0U}, {168U, 119U, 119U, 0U, 0U}, {169U, 140U, 140U, 0U, 0U}, {170U, 136U, 136U, 0U, 0U}, {171U, 120U, 120U, 0U, 0U}, {172U, 87U, 87U, 0U, 0U}, {173U, 136U, 136U, 0U, 0U}, {174U, 0U, 0U, 0U, 0U}, {175U, 8U, 8U, 0U, 0U}, {176U, 136U, 136U, 0U, 0U}, {177U, 0U, 0U, 0U, 0U}, {178U, 27U, 27U, 0U, 0U}, {179U, 3U, 3U, 0U, 0U}, {180U, 36U, 36U, 0U, 0U}, {181U, 3U, 3U, 0U, 0U}, {182U, 27U, 27U, 0U, 0U}, {183U, 36U, 36U, 0U, 0U}, {184U, 3U, 3U, 0U, 0U}, {185U, 0U, 0U, 0U, 0U}, {186U, 170U, 170U, 0U, 0U}, {187U, 0U, 0U, 0U, 0U}, {188U, 4U, 4U, 0U, 0U}, {189U, 0U, 0U, 0U, 0U}, {190U, 8U, 8U, 0U, 0U}, {191U, 17U, 17U, 0U, 0U}, {192U, 0U, 0U, 0U, 0U}, {193U, 0U, 0U, 0U, 0U}, {194U, 98U, 98U, 0U, 0U}, {195U, 30U, 30U, 0U, 0U}, {196U, 51U, 51U, 0U, 0U}, {197U, 55U, 55U, 0U, 0U}, {198U, 0U, 0U, 0U, 0U}, {199U, 112U, 112U, 0U, 0U}, {200U, 30U, 30U, 0U, 0U}, {201U, 6U, 6U, 0U, 0U}, {202U, 4U, 4U, 0U, 0U}, {203U, 47U, 47U, 0U, 0U}, {204U, 15U, 15U, 0U, 0U}, {205U, 0U, 0U, 0U, 0U}, {206U, 255U, 255U, 0U, 0U}, {207U, 8U, 8U, 0U, 0U}, {208U, 63U, 63U, 0U, 0U}, {209U, 63U, 63U, 0U, 0U}, {210U, 63U, 63U, 0U, 0U}, {211U, 0U, 0U, 0U, 0U}, {212U, 0U, 0U, 0U, 0U}, {213U, 0U, 0U, 0U, 0U}, {214U, 204U, 204U, 0U, 0U}, {215U, 0U, 0U, 0U, 0U}, {216U, 8U, 8U, 0U, 0U}, {217U, 8U, 8U, 0U, 0U}, {218U, 8U, 8U, 0U, 0U}, {219U, 17U, 17U, 0U, 0U}, {220U, 0U, 0U, 0U, 0U}, {221U, 135U, 135U, 0U, 0U}, {222U, 136U, 136U, 0U, 0U}, {223U, 8U, 8U, 0U, 0U}, {224U, 8U, 8U, 0U, 0U}, {225U, 8U, 8U, 0U, 0U}, {226U, 0U, 0U, 0U, 0U}, {227U, 0U, 0U, 0U, 0U}, {228U, 0U, 0U, 0U, 0U}, {229U, 245U, 245U, 0U, 0U}, {230U, 48U, 48U, 0U, 0U}, {231U, 1U, 1U, 0U, 0U}, {232U, 0U, 0U, 0U, 0U}, {233U, 255U, 255U, 0U, 0U}, {234U, 0U, 0U, 0U, 0U}, {235U, 0U, 0U, 0U, 0U}, {236U, 34U, 34U, 0U, 0U}, {237U, 0U, 0U, 0U, 0U}, {238U, 0U, 0U, 0U, 0U}, {239U, 0U, 0U, 0U, 0U}, {240U, 3U, 3U, 0U, 0U}, {241U, 1U, 1U, 0U, 0U}, {242U, 0U, 0U, 0U, 0U}, {243U, 0U, 0U, 0U, 0U}, {244U, 0U, 0U, 0U, 0U}, {245U, 0U, 0U, 0U, 0U}, {246U, 0U, 0U, 0U, 0U}, {247U, 6U, 6U, 0U, 0U}, {248U, 0U, 0U, 0U, 0U}, {249U, 0U, 0U, 0U, 0U}, {250U, 64U, 64U, 0U, 0U}, {251U, 0U, 0U, 0U, 0U}, {252U, 1U, 1U, 0U, 0U}, {253U, 128U, 128U, 0U, 0U}, {254U, 2U, 2U, 0U, 0U}, {255U, 16U, 16U, 0U, 0U}, {256U, 2U, 2U, 0U, 0U}, {257U, 30U, 30U, 0U, 0U}, {258U, 30U, 30U, 0U, 0U}, {259U, 0U, 0U, 0U, 0U}, {260U, 31U, 31U, 0U, 0U}, {261U, 0U, 8U, 0U, 1U}, {262U, 42U, 42U, 0U, 0U}, {263U, 15U, 15U, 0U, 0U}, {264U, 0U, 0U, 0U, 0U}, {265U, 0U, 0U, 0U, 0U}, {266U, 0U, 0U, 0U, 0U}, {267U, 0U, 0U, 0U, 0U}, {268U, 0U, 0U, 0U, 0U}, {269U, 0U, 0U, 0U, 0U}, {270U, 0U, 0U, 0U, 0U}, {271U, 0U, 0U, 0U, 0U}, {272U, 0U, 0U, 0U, 0U}, {273U, 0U, 0U, 0U, 0U}, {274U, 0U, 0U, 0U, 0U}, {275U, 0U, 0U, 0U, 0U}, {276U, 0U, 0U, 0U, 0U}, {277U, 0U, 0U, 0U, 0U}, {278U, 0U, 0U, 0U, 0U}, {279U, 0U, 0U, 0U, 0U}, {280U, 0U, 0U, 0U, 0U}, {281U, 0U, 0U, 0U, 0U}, {282U, 0U, 0U, 0U, 0U}, {283U, 0U, 0U, 0U, 0U}, {284U, 1U, 1U, 0U, 0U}, {285U, 0U, 0U, 0U, 0U}, {286U, 0U, 0U, 0U, 0U}, {287U, 0U, 0U, 0U, 0U}, {288U, 0U, 0U, 0U, 0U}, {289U, 0U, 0U, 0U, 0U}, {290U, 128U, 128U, 0U, 0U}, {291U, 0U, 0U, 0U, 0U}, {292U, 248U, 248U, 0U, 0U}, {293U, 0U, 0U, 0U, 0U}, {294U, 0U, 0U, 0U, 0U}, {295U, 0U, 0U, 0U, 0U}, {296U, 0U, 0U, 0U, 0U}, {297U, 0U, 0U, 0U, 0U}, {298U, 0U, 0U, 0U, 0U}, {299U, 0U, 0U, 0U, 0U}, {300U, 0U, 0U, 0U, 0U}, {301U, 0U, 0U, 0U, 0U}, {302U, 0U, 0U, 0U, 0U}, {303U, 0U, 0U, 0U, 0U}, {304U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static u16 const LCNPHY_txdigfiltcoeffs_cck[13U][17U] = { { 0U, 1U, 415U, 1874U, 64U, 128U, 64U, 792U, 1656U, 64U, 128U, 64U, 778U, 1582U, 64U, 128U, 64U}, { 1U, 1U, 402U, 1847U, 259U, 59U, 259U, 671U, 1794U, 68U, 54U, 68U, 608U, 1863U, 93U, 167U, 93U}, { 2U, 1U, 415U, 1874U, 64U, 128U, 64U, 792U, 1656U, 192U, 384U, 192U, 778U, 1582U, 64U, 128U, 64U}, { 3U, 1U, 302U, 1841U, 129U, 258U, 129U, 658U, 1720U, 205U, 410U, 205U, 754U, 1760U, 170U, 340U, 170U}, { 20U, 1U, 360U, 1884U, 242U, 1734U, 242U, 752U, 1720U, 205U, 1845U, 205U, 767U, 1760U, 256U, 185U, 256U}, { 21U, 1U, 360U, 1884U, 149U, 1874U, 149U, 752U, 1720U, 205U, 1883U, 205U, 767U, 1760U, 256U, 273U, 256U}, { 22U, 1U, 360U, 1884U, 98U, 1948U, 98U, 752U, 1720U, 205U, 1924U, 205U, 767U, 1760U, 256U, 352U, 256U}, { 23U, 1U, 350U, 1884U, 116U, 1966U, 116U, 752U, 1720U, 205U, 2008U, 205U, 767U, 1760U, 128U, 233U, 128U}, { 24U, 1U, 325U, 1884U, 32U, 40U, 32U, 756U, 1720U, 256U, 471U, 256U, 766U, 1760U, 256U, 1881U, 256U}, { 25U, 1U, 299U, 1884U, 51U, 64U, 51U, 736U, 1720U, 256U, 471U, 256U, 765U, 1760U, 256U, 1881U, 256U}, { 26U, 1U, 277U, 1943U, 39U, 117U, 88U, 637U, 1838U, 64U, 192U, 144U, 614U, 1864U, 128U, 384U, 288U}, { 27U, 1U, 245U, 1943U, 49U, 147U, 110U, 626U, 1838U, 256U, 768U, 576U, 613U, 1864U, 128U, 384U, 288U}, { 30U, 1U, 302U, 1841U, 61U, 122U, 61U, 658U, 1720U, 205U, 410U, 205U, 754U, 1760U, 170U, 340U, 170U}}; static u16 const LCNPHY_txdigfiltcoeffs_ofdm[3U][17U] = { { 0U, 0U, 162U, 0U, 256U, 256U, 0U, 0U, 0U, 256U, 0U, 0U, 632U, 65184U, 128U, 256U, 128U}, { 1U, 0U, 374U, 65401U, 16U, 32U, 16U, 799U, 65140U, 50U, 32U, 50U, 750U, 65067U, 212U, 65486U, 212U}, { 2U, 0U, 375U, 65302U, 37U, 76U, 37U, 799U, 65140U, 32U, 20U, 32U, 748U, 65266U, 128U, 65506U, 128U}}; void wlc_lcnphy_write_table(struct brcms_phy *pi , struct phytbl_info const *pti ) { { wlc_phy_write_table(pi, pti, 1109, 1111, 1110); return; } } void wlc_lcnphy_read_table(struct brcms_phy *pi , struct phytbl_info *pti ) { { wlc_phy_read_table(pi, (struct phytbl_info const *)pti, 1109, 1111, 1110); return; } } static void wlc_lcnphy_common_read_table(struct brcms_phy *pi , u32 tbl_id , u16 const *tbl_ptr , u32 tbl_len , u32 tbl_width , u32 tbl_offset ) { struct phytbl_info tab ; { tab.tbl_id = tbl_id; tab.tbl_ptr = (void const *)tbl_ptr; tab.tbl_len = tbl_len; tab.tbl_width = tbl_width; tab.tbl_offset = tbl_offset; wlc_lcnphy_read_table(pi, & tab); return; } } static void wlc_lcnphy_common_write_table(struct brcms_phy *pi , u32 tbl_id , u16 const *tbl_ptr , u32 tbl_len , u32 tbl_width , u32 tbl_offset ) { struct phytbl_info tab ; { tab.tbl_id = tbl_id; tab.tbl_ptr = (void const *)tbl_ptr; tab.tbl_len = tbl_len; tab.tbl_width = tbl_width; tab.tbl_offset = tbl_offset; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); return; } } static u32 wlc_lcnphy_qdiv_roundup(u32 dividend , u32 divisor , u8 precision ) { u32 quotient ; u32 remainder ; u32 roundup ; u32 rbit ; u8 tmp ; { quotient = dividend / divisor; remainder = dividend % divisor; rbit = divisor & 1U; roundup = (divisor >> 1) + rbit; goto ldv_37198; ldv_37197: quotient = quotient << 1; if (remainder >= roundup) { quotient = quotient + 1U; remainder = ((remainder - roundup) << 1) + rbit; } else { remainder = remainder << 1; } ldv_37198: tmp = precision; precision = (u8 )((int )precision - 1); if ((unsigned int )tmp != 0U) { goto ldv_37197; } else { } if (remainder >= roundup) { quotient = quotient + 1U; } else { } return (quotient); } } static int wlc_lcnphy_calc_floor(s16 coeff_x , int type ) { int k ; { k = 0; if (type == 0) { if ((int )coeff_x < 0) { k = ((int )coeff_x + -1) / 2; } else { k = (int )coeff_x / 2; } } else { } if (type == 1) { if ((int )coeff_x + 1 < 0) { k = (int )coeff_x / 2; } else { k = ((int )coeff_x + 1) / 2; } } else { } return (k); } } static void wlc_lcnphy_get_tx_gain(struct brcms_phy *pi , struct lcnphy_txgains *gains ) { u16 dac_gain ; u16 rfgain0 ; u16 rfgain1 ; u16 tmp ; { dac_gain = read_phy_reg(pi, 1081); gains->dac_gain = (u16 )(((int )dac_gain & 896) >> 7); rfgain0 = read_phy_reg(pi, 1205); tmp = read_phy_reg(pi, 1275); rfgain1 = (unsigned int )tmp & 32767U; gains->gm_gain = (unsigned int )rfgain0 & 255U; gains->pga_gain = (u16 )((int )rfgain0 >> 8); gains->pad_gain = (unsigned int )rfgain1 & 255U; return; } } static void wlc_lcnphy_set_dac_gain(struct brcms_phy *pi , u16 dac_gain ) { u16 dac_ctrl ; { dac_ctrl = read_phy_reg(pi, 1081); dac_ctrl = (unsigned int )dac_ctrl & 3199U; dac_ctrl = (u16 )((int )((short )((int )dac_gain << 7)) | (int )((short )dac_ctrl)); mod_phy_reg(pi, 1081, 4095, (int )dac_ctrl); return; } } static void wlc_lcnphy_set_tx_gain_override(struct brcms_phy *pi , bool bEnable ) { u16 bit ; { bit = (u16 )bEnable; mod_phy_reg(pi, 1200, 128, (int )bit << 7U); mod_phy_reg(pi, 1200, 16384, (int )bit << 14U); mod_phy_reg(pi, 1083, 64, (int )bit << 6U); return; } } static void wlc_lcnphy_rx_gain_override_enable(struct brcms_phy *pi , bool enable ) { u16 ebit ; { ebit = (u16 )enable; mod_phy_reg(pi, 1200, 256, (int )ebit << 8U); mod_phy_reg(pi, 1100, 1, (int )ebit); if (pi->pubpi.phy_rev <= 1U) { mod_phy_reg(pi, 1100, 16, (int )ebit << 4U); mod_phy_reg(pi, 1100, 64, (int )ebit << 6U); mod_phy_reg(pi, 1200, 32, (int )ebit << 5U); mod_phy_reg(pi, 1200, 64, (int )ebit << 6U); } else { mod_phy_reg(pi, 1200, 4096, (int )ebit << 12U); mod_phy_reg(pi, 1200, 8192, (int )ebit << 13U); mod_phy_reg(pi, 1200, 32, (int )ebit << 5U); } if (((int )pi->radio_chanspec & 61440) == 8192) { mod_phy_reg(pi, 1200, 1024, (int )ebit << 10U); mod_phy_reg(pi, 1253, 8, (int )ebit << 3U); } else { } return; } } static void wlc_lcnphy_set_rx_gain_by_distribution(struct brcms_phy *pi , u16 trsw , u16 ext_lna , u16 biq2 , u16 biq1 , u16 tia , u16 lna2 , u16 lna1 ) { u16 gain0_15 ; u16 gain16_19 ; { gain16_19 = (unsigned int )biq2 & 15U; gain0_15 = (u16 )((((((int )((short )((int )biq1 << 12)) | (int )((short )(((int )tia & 15) << 8))) | ((int )((short )((int )lna2 << 6)) & 255)) | (int )((short )(((int )lna2 & 3) << 4))) | (int )((short )(((int )lna1 & 3) << 2))) | ((int )((short )lna1) & 3)); mod_phy_reg(pi, 1206, 65535, (int )gain0_15); mod_phy_reg(pi, 1207, 15, (int )gain16_19); mod_phy_reg(pi, 1201, 6144, (int )lna1 << 11U); if (pi->pubpi.phy_rev <= 1U) { mod_phy_reg(pi, 1201, 512, (int )ext_lna << 9U); mod_phy_reg(pi, 1201, 1024, (int )ext_lna << 10U); } else { mod_phy_reg(pi, 1201, 1024, 0); mod_phy_reg(pi, 1201, 32768, 0); mod_phy_reg(pi, 1201, 512, (int )ext_lna << 9U); } mod_phy_reg(pi, 1101, 1, (unsigned int )trsw == 0U); return; } } static void wlc_lcnphy_set_trsw_override(struct brcms_phy *pi , bool tx , bool rx ) { { mod_phy_reg(pi, 1101, 3, (int )((u16 )(((int )tx ? 2 : 0) | (int )((short )rx)))); or_phy_reg(pi, 1100, 3); return; } } static void wlc_lcnphy_clear_trsw_override(struct brcms_phy *pi ) { { and_phy_reg(pi, 1100, 65532); return; } } static void wlc_lcnphy_set_rx_iq_comp(struct brcms_phy *pi , u16 a , u16 b ) { { mod_phy_reg(pi, 1605, 1023, (int )a); mod_phy_reg(pi, 1606, 1023, (int )b); mod_phy_reg(pi, 1607, 1023, (int )a); mod_phy_reg(pi, 1608, 1023, (int )b); mod_phy_reg(pi, 1609, 1023, (int )a); mod_phy_reg(pi, 1610, 1023, (int )b); return; } } static bool wlc_lcnphy_rx_iq_est(struct brcms_phy *pi , u16 num_samps , u8 wait_time , struct lcnphy_iq_est *iq_est ) { int wait_count ; bool result ; u8 phybw40 ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; u16 tmp___3 ; u16 tmp___4 ; u16 tmp___5 ; { wait_count = 0; result = 1; phybw40 = ((int )pi->radio_chanspec & 3072) == 3072; mod_phy_reg(pi, 1754, 32, 32); mod_phy_reg(pi, 1040, 8, 0); mod_phy_reg(pi, 1154, 65535, (int )num_samps); mod_phy_reg(pi, 1153, 255, (int )wait_time); mod_phy_reg(pi, 1153, 256, 0); mod_phy_reg(pi, 1153, 512, 512); goto ldv_37263; ldv_37262: ; if (wait_count > 5000) { result = 0; goto cleanup; } else { } __const_udelay(429500UL); wait_count = wait_count + 1; ldv_37263: tmp = read_phy_reg(pi, 1153); if (((int )tmp & 512) != 0) { goto ldv_37262; } else { } tmp___0 = read_phy_reg(pi, 1155); tmp___1 = read_phy_reg(pi, 1156); iq_est->iq_prod = ((unsigned int )tmp___0 << 16) | (unsigned int )tmp___1; tmp___2 = read_phy_reg(pi, 1157); tmp___3 = read_phy_reg(pi, 1158); iq_est->i_pwr = ((unsigned int )tmp___2 << 16) | (unsigned int )tmp___3; tmp___4 = read_phy_reg(pi, 1159); tmp___5 = read_phy_reg(pi, 1160); iq_est->q_pwr = ((unsigned int )tmp___4 << 16) | (unsigned int )tmp___5; cleanup: mod_phy_reg(pi, 1040, 8, 8); mod_phy_reg(pi, 1754, 32, 0); return (result); } } static bool wlc_lcnphy_calc_rx_iq_comp(struct brcms_phy *pi , u16 num_samps ) { bool result ; u16 a0_new ; u16 b0_new ; struct lcnphy_iq_est iq_est ; s32 a ; s32 b ; s32 temp ; s16 iq_nbits ; s16 qq_nbits ; s16 arsh ; s16 brsh ; s32 iq ; u32 ii ; u32 qq ; struct brcms_phy_lcnphy *pi_lcn ; u16 tmp ; u16 tmp___0 ; u8 tmp___1 ; u8 tmp___2 ; unsigned long tmp___3 ; { iq_est.iq_prod = 0U; iq_est.i_pwr = 0U; iq_est.q_pwr = 0U; pi_lcn = pi->u.pi_lcnphy; tmp = read_phy_reg(pi, 1605); a0_new = (unsigned int )tmp & 1023U; tmp___0 = read_phy_reg(pi, 1606); b0_new = (unsigned int )tmp___0 & 1023U; mod_phy_reg(pi, 1745, 4, 0); mod_phy_reg(pi, 1611, 64, 64); wlc_lcnphy_set_rx_iq_comp(pi, 0, 0); result = wlc_lcnphy_rx_iq_est(pi, (int )num_samps, 32, & iq_est); if (! result) { goto cleanup; } else { } iq = (int )iq_est.iq_prod; ii = iq_est.i_pwr; qq = iq_est.q_pwr; if (ii + qq <= 1U) { result = 0; goto cleanup; } else { } tmp___1 = wlc_phy_nbits(iq); iq_nbits = (s16 )tmp___1; tmp___2 = wlc_phy_nbits((s32 )qq); qq_nbits = (s16 )tmp___2; arsh = (s16 )((unsigned int )((unsigned short )iq_nbits) + 65516U); if ((int )arsh >= 0) { a = (s32 )((ii >> ((int )arsh + 1)) - (u32 )(iq << (30 - (int )iq_nbits))); temp = (int )(ii >> (int )arsh); if (temp == 0) { return (0); } else { } } else { a = (s32 )((ii << ~ ((int )arsh)) - (u32 )(iq << (30 - (int )iq_nbits))); temp = (int )(ii << - ((int )arsh)); if (temp == 0) { return (0); } else { } } a = a / temp; brsh = (s16 )((unsigned int )((unsigned short )qq_nbits) + 65525U); if ((int )brsh >= 0) { b = (s32 )(qq << (31 - (int )qq_nbits)); temp = (int )(ii >> (int )brsh); if (temp == 0) { return (0); } else { } } else { b = (s32 )(qq << (31 - (int )qq_nbits)); temp = (int )(ii << - ((int )brsh)); if (temp == 0) { return (0); } else { } } b = b / temp; b = b - a * a; tmp___3 = int_sqrt((unsigned long )b); b = (int )tmp___3; b = b + -1024; a0_new = (unsigned int )((unsigned short )a) & 1023U; b0_new = (unsigned int )((unsigned short )b) & 1023U; cleanup: wlc_lcnphy_set_rx_iq_comp(pi, (int )a0_new, (int )b0_new); mod_phy_reg(pi, 1611, 1, 1); mod_phy_reg(pi, 1611, 8, 8); pi_lcn->lcnphy_cal_results.rxiqcal_coeff_a0 = a0_new; pi_lcn->lcnphy_cal_results.rxiqcal_coeff_b0 = b0_new; return (result); } } static u32 wlc_lcnphy_measure_digital_power(struct brcms_phy *pi , u16 nsamples ) { struct lcnphy_iq_est iq_est ; bool tmp ; int tmp___0 ; { iq_est.iq_prod = 0U; iq_est.i_pwr = 0U; iq_est.q_pwr = 0U; tmp = wlc_lcnphy_rx_iq_est(pi, (int )nsamples, 32, & iq_est); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0U); } else { } return ((iq_est.i_pwr + iq_est.q_pwr) / (u32 )nsamples); } } static bool wlc_lcnphy_rx_iq_cal_gain(struct brcms_phy *pi , u16 biq1_gain , u16 tia_gain , u16 lna2_gain ) { u32 i_thresh_l ; u32 q_thresh_l ; u32 i_thresh_h ; u32 q_thresh_h ; struct lcnphy_iq_est iq_est_h ; struct lcnphy_iq_est iq_est_l ; bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; { wlc_lcnphy_set_rx_gain_by_distribution(pi, 0, 0, 0, (int )biq1_gain, (int )tia_gain, (int )lna2_gain, 0); wlc_lcnphy_rx_gain_override_enable(pi, 1); wlc_lcnphy_start_tx_tone(pi, 2000, 20, 0); __const_udelay(2147500UL); write_radio_reg(pi, 274, 0); tmp = wlc_lcnphy_rx_iq_est(pi, 1024, 32, & iq_est_l); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } wlc_lcnphy_start_tx_tone(pi, 2000, 40, 0); __const_udelay(2147500UL); write_radio_reg(pi, 274, 0); tmp___1 = wlc_lcnphy_rx_iq_est(pi, 1024, 32, & iq_est_h); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (0); } else { } i_thresh_l = iq_est_l.i_pwr << 1; i_thresh_h = (iq_est_l.i_pwr << 2) + iq_est_l.i_pwr; q_thresh_l = iq_est_l.q_pwr << 1; q_thresh_h = (iq_est_l.q_pwr << 2) + iq_est_l.q_pwr; if (((iq_est_h.i_pwr > i_thresh_l && iq_est_h.i_pwr < i_thresh_h) && iq_est_h.q_pwr > q_thresh_l) && iq_est_h.q_pwr < q_thresh_h) { return (1); } else { } return (0); } } static bool wlc_lcnphy_rx_iq_cal(struct brcms_phy *pi , struct lcnphy_rx_iqcomp const *iqcomp , int iqcomp_sz , bool tx_switch , bool rx_switch , int module , int tx_gain_idx ) { struct lcnphy_txgains old_gains ; u16 tx_pwr_ctrl ; u8 tx_gain_index_old ; bool result ; bool tx_gain_override_old ; u16 i ; u16 Core1TxControl_old ; u16 RFOverride0_old ; u16 RFOverrideVal0_old ; u16 rfoverride2_old ; u16 rfoverride2val_old ; u16 rfoverride3_old ; u16 rfoverride3val_old ; u16 rfoverride4_old ; u16 rfoverride4val_old ; u16 afectrlovr_old ; u16 afectrlovrval_old ; int tia_gain ; int lna2_gain ; int biq1_gain ; bool set_gain ; u16 old_sslpnCalibClkEnCtrl ; u16 old_sslpnRxFeClkEnCtrl ; u16 values_to_save[11U] ; s16 *ptr ; struct brcms_phy_lcnphy *pi_lcn ; void *tmp ; int tmp___0 ; int __ret_warn_on ; long tmp___1 ; u16 tmp___2 ; u16 tmp___3 ; { tx_gain_index_old = 0U; result = 0; tx_gain_override_old = 0; pi_lcn = pi->u.pi_lcnphy; tmp = kmalloc(262UL, 32U); ptr = (s16 *)tmp; if ((unsigned long )ptr == (unsigned long )((s16 *)0)) { return (0); } else { } if (module == 2) { goto ldv_37339; ldv_37338: ; if ((int )((unsigned char )(iqcomp + (unsigned long )iqcomp_sz)->chan) == (int )((unsigned char )pi->radio_chanspec)) { wlc_lcnphy_set_rx_iq_comp(pi, (int )((unsigned short )(iqcomp + (unsigned long )iqcomp_sz)->a), (int )((unsigned short )(iqcomp + (unsigned long )iqcomp_sz)->b)); result = 1; goto ldv_37337; } else { } ldv_37339: tmp___0 = iqcomp_sz; iqcomp_sz = iqcomp_sz - 1; if (tmp___0 != 0) { goto ldv_37338; } else { } ldv_37337: ; goto cal_done; } else { } __ret_warn_on = module != 1; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c", 1409); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); tmp___2 = read_phy_reg(pi, 1188); tx_pwr_ctrl = (unsigned int )tmp___2 & 57344U; wlc_lcnphy_set_tx_pwr_ctrl(pi, 0); i = 0U; goto ldv_37344; ldv_37343: values_to_save[(int )i] = read_radio_reg(pi, (int )rxiq_cal_rf_reg[(int )i]); i = (u16 )((int )i + 1); ldv_37344: ; if ((unsigned int )i <= 10U) { goto ldv_37343; } else { } Core1TxControl_old = read_phy_reg(pi, 1585); or_phy_reg(pi, 1585, 21); RFOverride0_old = read_phy_reg(pi, 1100); RFOverrideVal0_old = read_phy_reg(pi, 1101); rfoverride2_old = read_phy_reg(pi, 1200); rfoverride2val_old = read_phy_reg(pi, 1201); rfoverride3_old = read_phy_reg(pi, 1273); rfoverride3val_old = read_phy_reg(pi, 1274); rfoverride4_old = read_phy_reg(pi, 2360); rfoverride4val_old = read_phy_reg(pi, 2361); afectrlovr_old = read_phy_reg(pi, 1083); afectrlovrval_old = read_phy_reg(pi, 1084); old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 1754); old_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 1755); tmp___3 = read_phy_reg(pi, 1083); tx_gain_override_old = ((int )tmp___3 & 64) != 0; if ((int )tx_gain_override_old) { wlc_lcnphy_get_tx_gain(pi, & old_gains); tx_gain_index_old = pi_lcn->lcnphy_current_index; } else { } wlc_lcnphy_set_tx_pwr_by_index(pi, tx_gain_idx); mod_phy_reg(pi, 1273, 1, 1); mod_phy_reg(pi, 1274, 1, 0); mod_phy_reg(pi, 1083, 2, 2); mod_phy_reg(pi, 1084, 2, 0); write_radio_reg(pi, 278, 6); write_radio_reg(pi, 300, 7); write_radio_reg(pi, 106, 211); write_radio_reg(pi, 152, 3); write_radio_reg(pi, 11, 7); mod_radio_reg(pi, 275, 16, 16); write_radio_reg(pi, 29, 1); write_radio_reg(pi, 276, 1); write_radio_reg(pi, 46, 16); write_radio_reg(pi, 298, 8); mod_phy_reg(pi, 2360, 1, 1); mod_phy_reg(pi, 2361, 1, 0); mod_phy_reg(pi, 2360, 2, 2); mod_phy_reg(pi, 2361, 2, 2); mod_phy_reg(pi, 2360, 4, 4); mod_phy_reg(pi, 2361, 4, 4); mod_phy_reg(pi, 2360, 8, 8); mod_phy_reg(pi, 2361, 8, 8); mod_phy_reg(pi, 2360, 32, 32); mod_phy_reg(pi, 2361, 32, 0); mod_phy_reg(pi, 1083, 1, 1); mod_phy_reg(pi, 1084, 1, 0); write_phy_reg(pi, 1754, 65535); or_phy_reg(pi, 1755, 3); wlc_lcnphy_set_trsw_override(pi, (int )tx_switch, (int )rx_switch); lna2_gain = 3; goto ldv_37355; ldv_37354: tia_gain = 4; goto ldv_37352; ldv_37351: biq1_gain = 6; goto ldv_37349; ldv_37348: set_gain = wlc_lcnphy_rx_iq_cal_gain(pi, (int )((unsigned short )biq1_gain), (int )((unsigned short )tia_gain), (int )((unsigned short )lna2_gain)); if (! set_gain) { goto ldv_37346; } else { } result = wlc_lcnphy_calc_rx_iq_comp(pi, 1024); goto stop_tone; ldv_37346: biq1_gain = biq1_gain - 1; ldv_37349: ; if (biq1_gain >= 0) { goto ldv_37348; } else { } tia_gain = tia_gain - 1; ldv_37352: ; if (tia_gain >= 0) { goto ldv_37351; } else { } lna2_gain = lna2_gain - 1; ldv_37355: ; if (lna2_gain >= 0) { goto ldv_37354; } else { } stop_tone: wlc_lcnphy_stop_tx_tone(pi); write_phy_reg(pi, 1585, (int )Core1TxControl_old); write_phy_reg(pi, 1100, (int )RFOverrideVal0_old); write_phy_reg(pi, 1101, (int )RFOverrideVal0_old); write_phy_reg(pi, 1200, (int )rfoverride2_old); write_phy_reg(pi, 1201, (int )rfoverride2val_old); write_phy_reg(pi, 1273, (int )rfoverride3_old); write_phy_reg(pi, 1274, (int )rfoverride3val_old); write_phy_reg(pi, 2360, (int )rfoverride4_old); write_phy_reg(pi, 2361, (int )rfoverride4val_old); write_phy_reg(pi, 1083, (int )afectrlovr_old); write_phy_reg(pi, 1084, (int )afectrlovrval_old); write_phy_reg(pi, 1754, (int )old_sslpnCalibClkEnCtrl); write_phy_reg(pi, 1755, (int )old_sslpnRxFeClkEnCtrl); wlc_lcnphy_clear_trsw_override(pi); mod_phy_reg(pi, 1100, 4, 0); i = 0U; goto ldv_37358; ldv_37357: write_radio_reg(pi, (int )rxiq_cal_rf_reg[(int )i], (int )values_to_save[(int )i]); i = (u16 )((int )i + 1); ldv_37358: ; if ((unsigned int )i <= 10U) { goto ldv_37357; } else { } if ((int )tx_gain_override_old) { wlc_lcnphy_set_tx_pwr_by_index(pi, (int )tx_gain_index_old); } else { wlc_lcnphy_set_tx_gain_override(pi, 0); } wlc_lcnphy_set_tx_pwr_ctrl(pi, (int )tx_pwr_ctrl); wlc_lcnphy_rx_gain_override_enable(pi, 0); cal_done: kfree((void const *)ptr); return (result); } } s8 wlc_lcnphy_get_current_tx_pwr_idx(struct brcms_phy *pi ) { s8 index ; struct brcms_phy_lcnphy *pi_lcn ; u16 tmp ; u16 tmp___0 ; { pi_lcn = pi->u.pi_lcnphy; tmp___0 = read_phy_reg(pi, 1188); if ((unsigned int )((int )tmp___0 >> 13) != 7U) { index = (s8 )pi_lcn->lcnphy_current_index; } else if ((int )pi->hwpwrctrl_capable) { tmp = read_phy_reg(pi, 1139); index = (signed char )(((int )tmp & 511) / 2); } else { index = (s8 )pi_lcn->lcnphy_current_index; } return (index); } } void wlc_lcnphy_crsuprs(struct brcms_phy *pi , int channel ) { u16 afectrlovr ; u16 afectrlovrval ; { afectrlovr = read_phy_reg(pi, 1083); afectrlovrval = read_phy_reg(pi, 1084); if (channel != 0) { mod_phy_reg(pi, 1083, 2, 2); mod_phy_reg(pi, 1084, 2, 0); mod_phy_reg(pi, 1083, 16, 16); mod_phy_reg(pi, 1084, 64, 0); write_phy_reg(pi, 1099, 65535); wlc_lcnphy_tx_pu(pi, 1); mod_phy_reg(pi, 1588, 65280, 0); or_phy_reg(pi, 1754, 128); or_phy_reg(pi, 10, 552); } else { and_phy_reg(pi, 10, 64983); and_phy_reg(pi, 1754, 65407); write_phy_reg(pi, 1083, (int )afectrlovr); write_phy_reg(pi, 1084, (int )afectrlovrval); } return; } } static void wlc_lcnphy_toggle_afe_pwdn(struct brcms_phy *pi ) { u16 save_AfeCtrlOvrVal ; u16 save_AfeCtrlOvr ; { save_AfeCtrlOvrVal = read_phy_reg(pi, 1084); save_AfeCtrlOvr = read_phy_reg(pi, 1083); write_phy_reg(pi, 1084, (int )((unsigned int )save_AfeCtrlOvrVal | 1U)); write_phy_reg(pi, 1083, (int )((unsigned int )save_AfeCtrlOvr | 1U)); write_phy_reg(pi, 1084, (int )save_AfeCtrlOvrVal & 65534); write_phy_reg(pi, 1083, (int )save_AfeCtrlOvr & 65534); write_phy_reg(pi, 1084, (int )save_AfeCtrlOvrVal); write_phy_reg(pi, 1083, (int )save_AfeCtrlOvr); return; } } static void wlc_lcnphy_txrx_spur_avoidance_mode(struct brcms_phy *pi , bool enable ) { { if ((int )enable) { write_phy_reg(pi, 2370, 7); write_phy_reg(pi, 2363, 8215); write_phy_reg(pi, 2364, 10181); write_phy_reg(pi, 1098, 132); write_phy_reg(pi, 1098, 128); write_phy_reg(pi, 1747, 8738); write_phy_reg(pi, 1747, 8736); } else { write_phy_reg(pi, 2370, 0); write_phy_reg(pi, 2363, 23); write_phy_reg(pi, 2364, 1989); } wlapi_switch_macfreq((pi->sh)->physhim, (int )enable); return; } } static void wlc_lcnphy_set_chanspec_tweaks(struct brcms_phy *pi , u16 chanspec ) { u8 channel ; struct brcms_phy_lcnphy *pi_lcn ; u32 tmp ; u32 tmp___0 ; { channel = (unsigned char )chanspec; pi_lcn = pi->u.pi_lcnphy; if ((unsigned int )channel == 14U) { mod_phy_reg(pi, 1096, 768, 512); } else { mod_phy_reg(pi, 1096, 768, 256); } pi_lcn->lcnphy_bandedge_corr = 2U; if ((unsigned int )channel == 1U) { pi_lcn->lcnphy_bandedge_corr = 4U; } else { } if ((((((((unsigned int )channel == 1U || (unsigned int )channel == 2U) || (unsigned int )channel == 3U) || (unsigned int )channel == 4U) || (unsigned int )channel == 9U) || (unsigned int )channel == 10U) || (unsigned int )channel == 11U) || (unsigned int )channel == 12U) { bcma_chipco_pll_write(& ((pi->d11core)->bus)->drv_cc, 2U, 50334724U); bcma_chipco_pll_maskset(& ((pi->d11core)->bus)->drv_cc, 3U, 4278190080U, 0U); bcma_chipco_pll_write(& ((pi->d11core)->bus)->drv_cc, 4U, 536872384U); tmp = bcma_read32(((pi->d11core)->bus)->drv_cc.core, 1536); bcma_write32(((pi->d11core)->bus)->drv_cc.core, 1536, tmp | 1024U); write_phy_reg(pi, 2370, 0); wlc_lcnphy_txrx_spur_avoidance_mode(pi, 0); pi_lcn->lcnphy_spurmod = 0; mod_phy_reg(pi, 1060, 65280, 6912); write_phy_reg(pi, 1061, 22791); } else { bcma_chipco_pll_write(& ((pi->d11core)->bus)->drv_cc, 2U, 51645444U); bcma_chipco_pll_maskset(& ((pi->d11core)->bus)->drv_cc, 3U, 4278190080U, 3355443U); bcma_chipco_pll_write(& ((pi->d11core)->bus)->drv_cc, 4U, 539764768U); tmp___0 = bcma_read32(((pi->d11core)->bus)->drv_cc.core, 1536); bcma_write32(((pi->d11core)->bus)->drv_cc.core, 1536, tmp___0 | 1024U); write_phy_reg(pi, 2370, 0); wlc_lcnphy_txrx_spur_avoidance_mode(pi, 1); pi_lcn->lcnphy_spurmod = 0; mod_phy_reg(pi, 1060, 65280, 7936); write_phy_reg(pi, 1061, 22794); } or_phy_reg(pi, 1098, 68); write_phy_reg(pi, 1098, 128); return; } } static void wlc_lcnphy_radio_2064_channel_tune_4313(struct brcms_phy *pi , u8 channel ) { uint i ; struct chan_info_2064_lcnphy const *ci ; u8 rfpll_doubler ; u8 pll_pwrup ; u8 pll_pwrup_ovr ; s32 qFxtal ; s32 qFref ; s32 qFvco ; s32 qFcal ; u8 d15 ; u8 d16 ; u8 f16 ; u8 e44 ; u8 e45 ; u32 div_int ; u32 div_frac ; u32 fvco3 ; u32 fpfd ; u32 fref3 ; u32 fcal_div ; u16 loop_bw ; u16 d30 ; u16 setCount ; u8 h29 ; u8 h28_ten ; u8 e30 ; u8 h30_ten ; u8 cp_current ; u16 g30 ; u16 d28 ; u16 tmp ; u16 tmp___0 ; u32 tmp___1 ; u32 tmp___2 ; u32 tmp___3 ; u8 reg038[14U] ; { rfpll_doubler = 0U; ci = (struct chan_info_2064_lcnphy const *)(& chan_info_2064_lcnphy); rfpll_doubler = 1U; mod_radio_reg(pi, 157, 4, 4); write_radio_reg(pi, 158, 15); if ((unsigned int )rfpll_doubler == 0U) { loop_bw = 260U; d30 = 8000U; } else { loop_bw = 200U; d30 = 10500U; } if (((int )pi->radio_chanspec & 61440) == 8192) { i = 0U; goto ldv_37424; ldv_37423: ; if ((unsigned int )chan_info_2064_lcnphy[i].chan == (unsigned int )channel) { goto ldv_37422; } else { } i = i + 1U; ldv_37424: ; if (i <= 13U) { goto ldv_37423; } else { } ldv_37422: ; if (i > 13U) { return; } else { } ci = (struct chan_info_2064_lcnphy const *)(& chan_info_2064_lcnphy) + (unsigned long )i; } else { } write_radio_reg(pi, 42, (int )ci->logen_buftune); mod_radio_reg(pi, 48, 3, (int )ci->logen_rccr_tx); mod_radio_reg(pi, 145, 3, (int )ci->txrf_mix_tune_ctrl); mod_radio_reg(pi, 56, 15, (int )ci->pa_input_tune_g); mod_radio_reg(pi, 48, 12, (int )((u16 )ci->logen_rccr_rx) << 2U); mod_radio_reg(pi, 94, 15, (int )ci->pa_rxrf_lna1_freq_tune); mod_radio_reg(pi, 94, 240, (int )((u16 )ci->pa_rxrf_lna2_freq_tune) << 4U); write_radio_reg(pi, 108, (int )ci->rxrf_rxrf_spare1); tmp = read_radio_reg(pi, 68); pll_pwrup = (unsigned char )tmp; tmp___0 = read_radio_reg(pi, 299); pll_pwrup_ovr = (unsigned char )tmp___0; or_radio_reg(pi, 68, 7); or_radio_reg(pi, 299, 14); e44 = 0U; e45 = 0U; fpfd = (unsigned int )rfpll_doubler != 0U ? pi->xtalfreq << 1 : pi->xtalfreq; if (pi->xtalfreq > 26000000U) { e44 = 1U; } else { } if (pi->xtalfreq > 52000000U) { e45 = 1U; } else { } if ((unsigned int )e44 == 0U) { fcal_div = 1U; } else if ((unsigned int )e45 == 0U) { fcal_div = 2U; } else { fcal_div = 4U; } fvco3 = (unsigned int )ci->freq * 3U; fref3 = fpfd * 2U; tmp___1 = wlc_lcnphy_qdiv_roundup(pi->xtalfreq, 1000000U, 16); qFxtal = (s32 )tmp___1; tmp___2 = wlc_lcnphy_qdiv_roundup(fpfd, 1000000U, 16); qFref = (s32 )tmp___2; qFcal = (s32 )((pi->xtalfreq * fcal_div) / 1000000U); tmp___3 = wlc_lcnphy_qdiv_roundup(fvco3, 2U, 16); qFvco = (s32 )tmp___3; write_radio_reg(pi, 79, 2); d15 = (unsigned int )((u8 )(((pi->xtalfreq * fcal_div) * 4U) / 5000000U)) - 1U; write_radio_reg(pi, 82, ((int )d15 >> 2) & 7); write_radio_reg(pi, 83, (int )(((unsigned int )((u16 )d15) & 3U) << 5U)); d16 = (unsigned int )((u8 )((qFcal * 8) / ((int )d15 + 1))) + 255U; write_radio_reg(pi, 81, (int )d16); f16 = (u8 )((((int )d16 + 1) * ((int )d15 + 1)) / qFcal); setCount = (unsigned int )((u16 )((((unsigned int )f16 * (unsigned int )ci->freq) * 3U) / 32U)) - 1U; mod_radio_reg(pi, 83, 15, (int )((unsigned char )((int )setCount >> 8))); or_radio_reg(pi, 83, 16); write_radio_reg(pi, 84, (int )((unsigned char )setCount)); div_int = (fvco3 * 62500U) / fref3 << 4; div_frac = (fvco3 * 62500U) % fref3 << 4; goto ldv_37428; ldv_37427: div_int = div_int + 1U; div_frac = div_frac - fref3; ldv_37428: ; if (div_frac >= fref3) { goto ldv_37427; } else { } div_frac = wlc_lcnphy_qdiv_roundup(div_frac, fref3, 20); mod_radio_reg(pi, 69, 31, (int )((unsigned char )(div_int >> 4))); mod_radio_reg(pi, 70, 496, (int )((unsigned char )div_int) << 4U); mod_radio_reg(pi, 70, 15, (int )((unsigned char )(div_frac >> 16))); write_radio_reg(pi, 71, (int )((unsigned char )(div_frac >> 8))); write_radio_reg(pi, 72, (int )((unsigned char )div_frac)); write_radio_reg(pi, 64, 251); write_radio_reg(pi, 65, 154); write_radio_reg(pi, 66, 163); write_radio_reg(pi, 67, 12); h29 = (u8 )(200 / (int )loop_bw); d28 = (unsigned int )((u16 )(((fvco3 / 2U) * 41U + 4294844296U) / 1200U)) + 27U; h28_ten = (u8 )(((int )d28 * 10) / 30); e30 = (u8 )(((int )d30 + -680) / 490); g30 = (unsigned int )((u16 )e30) * 490U + 680U; h30_ten = (u8 )(((int )g30 * 10) / 2640); cp_current = (u8 )((((int )h29 * 125000) / (int )h28_ten) / (int )h30_ten); mod_radio_reg(pi, 60, 63, (int )cp_current); if ((unsigned int )channel != 0U && (unsigned int )channel <= 5U) { write_radio_reg(pi, 60, 8); } else { write_radio_reg(pi, 60, 7); } write_radio_reg(pi, 61, 3); mod_radio_reg(pi, 68, 12, 12); __const_udelay(4295UL); wlc_2064_vco_cal(pi); write_radio_reg(pi, 68, (int )pll_pwrup); write_radio_reg(pi, 299, (int )pll_pwrup_ovr); if (pi->pubpi.phy_rev == 1U) { write_radio_reg(pi, 56, 3); write_radio_reg(pi, 145, 7); } else { } if (((pi->sh)->boardflags & 2048U) == 0U) { reg038[0] = 13U; reg038[1] = 14U; reg038[2] = 13U; reg038[3] = 13U; reg038[4] = 13U; reg038[5] = 12U; reg038[6] = 10U; reg038[7] = 11U; reg038[8] = 11U; reg038[9] = 3U; reg038[10] = 3U; reg038[11] = 2U; reg038[12] = 0U; reg038[13] = 0U; write_radio_reg(pi, 42, 15); write_radio_reg(pi, 145, 3); write_radio_reg(pi, 56, 3); write_radio_reg(pi, 56, (int )reg038[(int )channel + -1]); } else { } return; } } static int wlc_lcnphy_load_tx_iir_filter(struct brcms_phy *pi , bool is_ofdm , s16 filt_type ) { s16 filt_index ; int j ; u16 addr[16U] ; u16 addr_ofdm[16U] ; { filt_index = -1; addr[0] = 2320U; addr[1] = 2334U; addr[2] = 2335U; addr[3] = 2340U; addr[4] = 2341U; addr[5] = 2342U; addr[6] = 2336U; addr[7] = 2337U; addr[8] = 2343U; addr[9] = 2344U; addr[10] = 2345U; addr[11] = 2338U; addr[12] = 2339U; addr[13] = 2352U; addr[14] = 2353U; addr[15] = 2354U; addr_ofdm[0] = 2319U; addr_ofdm[1] = 2304U; addr_ofdm[2] = 2305U; addr_ofdm[3] = 2310U; addr_ofdm[4] = 2311U; addr_ofdm[5] = 2312U; addr_ofdm[6] = 2306U; addr_ofdm[7] = 2307U; addr_ofdm[8] = 2313U; addr_ofdm[9] = 2314U; addr_ofdm[10] = 2315U; addr_ofdm[11] = 2308U; addr_ofdm[12] = 2309U; addr_ofdm[13] = 2316U; addr_ofdm[14] = 2317U; addr_ofdm[15] = 2318U; if (! is_ofdm) { j = 0; goto ldv_37442; ldv_37441: ; if ((int )filt_type == (int )LCNPHY_txdigfiltcoeffs_cck[j][0]) { filt_index = (short )j; goto ldv_37440; } else { } j = j + 1; ldv_37442: ; if (j <= 12) { goto ldv_37441; } else { } ldv_37440: ; if ((int )filt_index != -1) { j = 0; goto ldv_37444; ldv_37443: write_phy_reg(pi, (int )addr[j], (int )LCNPHY_txdigfiltcoeffs_cck[(int )filt_index][j + 1]); j = j + 1; ldv_37444: ; if (j <= 15) { goto ldv_37443; } else { } } else { } } else { j = 0; goto ldv_37448; ldv_37447: ; if ((int )filt_type == (int )LCNPHY_txdigfiltcoeffs_ofdm[j][0]) { filt_index = (short )j; goto ldv_37446; } else { } j = j + 1; ldv_37448: ; if (j <= 2) { goto ldv_37447; } else { } ldv_37446: ; if ((int )filt_index != -1) { j = 0; goto ldv_37450; ldv_37449: write_phy_reg(pi, (int )addr_ofdm[j], (int )LCNPHY_txdigfiltcoeffs_ofdm[(int )filt_index][j + 1]); j = j + 1; ldv_37450: ; if (j <= 15) { goto ldv_37449; } else { } } else { } } return ((int )filt_index != -1 ? 0 : -1); } } static u16 wlc_lcnphy_get_pa_gain(struct brcms_phy *pi ) { u16 pa_gain ; u16 tmp ; { tmp = read_phy_reg(pi, 1275); pa_gain = (u16 )(((int )tmp & 32512) >> 8); return (pa_gain); } } static void wlc_lcnphy_set_tx_gain(struct brcms_phy *pi , struct lcnphy_txgains *target_gains ) { u16 pa_gain ; u16 tmp ; { tmp = wlc_lcnphy_get_pa_gain(pi); pa_gain = tmp; mod_phy_reg(pi, 1205, 65535, (int )((u16 )((int )((short )target_gains->gm_gain) | (int )((short )((int )target_gains->pga_gain << 8))))); mod_phy_reg(pi, 1275, 32767, (int )((u16 )((int )((short )target_gains->pad_gain) | (int )((short )((int )pa_gain << 8))))); mod_phy_reg(pi, 1276, 65535, (int )((u16 )((int )((short )target_gains->gm_gain) | (int )((short )((int )target_gains->pga_gain << 8))))); mod_phy_reg(pi, 1277, 32767, (int )((u16 )((int )((short )target_gains->pad_gain) | (int )((short )((int )pa_gain << 8))))); wlc_lcnphy_set_dac_gain(pi, (int )target_gains->dac_gain); wlc_lcnphy_set_tx_gain_override(pi, 1); return; } } static u8 wlc_lcnphy_get_bbmult(struct brcms_phy *pi ) { u16 m0m1 ; struct phytbl_info tab ; { tab.tbl_ptr = (void const *)(& m0m1); tab.tbl_len = 1U; tab.tbl_id = 0U; tab.tbl_offset = 87U; tab.tbl_width = 16U; wlc_lcnphy_read_table(pi, & tab); return ((u8 )((int )m0m1 >> 8)); } } static void wlc_lcnphy_set_bbmult(struct brcms_phy *pi , u8 m0 ) { u16 m0m1 ; struct phytbl_info tab ; { m0m1 = (int )((u16 )m0) << 8U; tab.tbl_ptr = (void const *)(& m0m1); tab.tbl_len = 1U; tab.tbl_id = 0U; tab.tbl_offset = 87U; tab.tbl_width = 16U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); return; } } static void wlc_lcnphy_clear_tx_power_offsets(struct brcms_phy *pi ) { u32 data_buf[64U] ; struct phytbl_info tab ; { memset((void *)(& data_buf), 0, 256UL); tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_ptr = (void const *)(& data_buf); if (! pi->temppwrctrl_capable) { tab.tbl_len = 30U; tab.tbl_offset = 832U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); } else { } tab.tbl_len = 64U; tab.tbl_offset = 128U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); return; } } static void wlc_lcnphy_set_tssi_mux(struct brcms_phy *pi , enum lcnphy_tssi_mode pos ) { { mod_phy_reg(pi, 1239, 1, 1); mod_phy_reg(pi, 1239, 64, 64); if ((unsigned int )pos == 1U) { mod_phy_reg(pi, 1241, 4, 0); mod_phy_reg(pi, 1241, 8, 8); if (pi->pubpi.phy_rev == 2U) { mod_radio_reg(pi, 134, 4, 4); } else { mod_radio_reg(pi, 58, 1, 1); mod_radio_reg(pi, 282, 8, 8); mod_radio_reg(pi, 40, 1, 0); mod_radio_reg(pi, 282, 4, 4); mod_radio_reg(pi, 54, 16, 0); mod_radio_reg(pi, 282, 16, 16); mod_radio_reg(pi, 54, 3, 0); mod_radio_reg(pi, 53, 255, 119); mod_radio_reg(pi, 40, 30, 28); mod_radio_reg(pi, 274, 128, 128); mod_radio_reg(pi, 5, 7, 2); mod_radio_reg(pi, 41, 240, 0); } } else { mod_phy_reg(pi, 1241, 4, 4); mod_phy_reg(pi, 1241, 8, 0); if (pi->pubpi.phy_rev == 2U) { mod_radio_reg(pi, 134, 4, 4); } else { mod_radio_reg(pi, 58, 1, 0); mod_radio_reg(pi, 282, 8, 8); } } mod_phy_reg(pi, 1591, 49152, 0); if ((unsigned int )pos == 2U) { write_radio_reg(pi, 127, 1); mod_radio_reg(pi, 5, 7, 2); mod_radio_reg(pi, 274, 128, 128); mod_radio_reg(pi, 40, 31, 3); } else { } return; } } static u16 wlc_lcnphy_rfseq_tbl_adc_pwrup(struct brcms_phy *pi ) { u16 N1 ; u16 N2 ; u16 N3 ; u16 N4 ; u16 N5 ; u16 N6 ; u16 N ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; u16 tmp___3 ; u16 tmp___4 ; { tmp = read_phy_reg(pi, 1189); N1 = (unsigned int )tmp & 255U; tmp___0 = read_phy_reg(pi, 1189); N2 = (u16 )(1 << (((int )tmp___0 & 28672) >> 12)); tmp___1 = read_phy_reg(pi, 1037); N3 = (unsigned int )tmp___1 & 255U; tmp___2 = read_phy_reg(pi, 1037); N4 = (u16 )(1 << (((int )tmp___2 & 1792) >> 8)); tmp___3 = read_phy_reg(pi, 1186); N5 = (unsigned int )tmp___3 & 255U; tmp___4 = read_phy_reg(pi, 1186); N6 = (u16 )(1 << (((int )tmp___4 & 1792) >> 8)); N = (unsigned int )((u16 )((((((int )N1 + (int )N2) + (int )N3) + (int )N4) + ((int )N5 + (int )N6) * 2) + 40)) * 2U; if ((unsigned int )N <= 1599U) { N = 1600U; } else { } return (N); } } static void wlc_lcnphy_pwrctrl_rssiparams(struct brcms_phy *pi ) { u16 auxpga_vmid ; u16 auxpga_vmid_temp ; u16 auxpga_gain_temp ; struct brcms_phy_lcnphy *pi_lcn ; { pi_lcn = pi->u.pi_lcnphy; auxpga_vmid = (u16 )(((int )((short )((int )pi_lcn->lcnphy_rssi_vc << 4)) | 512) | (int )((short )pi_lcn->lcnphy_rssi_vf)); auxpga_vmid_temp = 644U; auxpga_gain_temp = 2U; mod_phy_reg(pi, 1240, 1, 0); mod_phy_reg(pi, 1240, 2, 0); mod_phy_reg(pi, 1239, 8, 0); mod_phy_reg(pi, 1243, 29695, (int )((u16 )((int )((short )((int )pi_lcn->lcnphy_rssi_gs << 12)) | (int )((short )auxpga_vmid)))); mod_phy_reg(pi, 1244, 29695, (int )((u16 )((int )((short )((int )pi_lcn->lcnphy_rssi_gs << 12)) | (int )((short )auxpga_vmid)))); mod_phy_reg(pi, 1034, 29695, (int )((u16 )((int )((short )((int )pi_lcn->lcnphy_rssi_gs << 12)) | (int )((short )auxpga_vmid)))); mod_phy_reg(pi, 1035, 29695, (int )((u16 )((int )((short )((int )auxpga_gain_temp << 12)) | (int )((short )auxpga_vmid_temp)))); mod_phy_reg(pi, 1036, 29695, (int )((u16 )((int )((short )((int )auxpga_gain_temp << 12)) | (int )((short )auxpga_vmid_temp)))); mod_radio_reg(pi, 130, 32, 32); mod_radio_reg(pi, 124, 1, 1); return; } } static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi ) { struct phytbl_info tab ; u32 rfseq ; u32 ind ; enum lcnphy_tssi_mode mode ; u8 tssi_sel ; u16 tmp ; { if (((pi->sh)->boardflags & 2048U) != 0U) { tssi_sel = 1U; mode = 2; } else { tssi_sel = 14U; mode = 1; } tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_ptr = (void const *)(& ind); tab.tbl_len = 1U; tab.tbl_offset = 0U; ind = 0U; goto ldv_37511; ldv_37510: wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); tab.tbl_offset = tab.tbl_offset + 1U; ind = ind + 1U; ldv_37511: ; if (ind <= 127U) { goto ldv_37510; } else { } tab.tbl_offset = 704U; ind = 0U; goto ldv_37514; ldv_37513: wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); tab.tbl_offset = tab.tbl_offset + 1U; ind = ind + 1U; ldv_37514: ; if (ind <= 127U) { goto ldv_37513; } else { } mod_phy_reg(pi, 1283, 1, 0); mod_phy_reg(pi, 1283, 4, 0); mod_phy_reg(pi, 1283, 16, 16); wlc_lcnphy_set_tssi_mux(pi, mode); mod_phy_reg(pi, 1188, 16384, 0); mod_phy_reg(pi, 1188, 32768, 32768); mod_phy_reg(pi, 1232, 32, 0); mod_phy_reg(pi, 1188, 511, 0); mod_phy_reg(pi, 1189, 255, 255); mod_phy_reg(pi, 1189, 28672, 20480); mod_phy_reg(pi, 1189, 1792, 0); mod_phy_reg(pi, 1037, 255, 64); mod_phy_reg(pi, 1037, 1792, 1024); mod_phy_reg(pi, 1186, 255, 64); mod_phy_reg(pi, 1186, 1792, 1024); mod_phy_reg(pi, 1232, 32704, 0); mod_phy_reg(pi, 1192, 255, 1); wlc_lcnphy_clear_tx_power_offsets(pi); mod_phy_reg(pi, 1190, 32768, 32768); mod_phy_reg(pi, 1190, 511, 255); mod_phy_reg(pi, 1178, 511, 255); if (pi->pubpi.phy_rev == 2U) { mod_radio_reg(pi, 40, 15, (int )tssi_sel); mod_radio_reg(pi, 134, 4, 4); } else { mod_radio_reg(pi, 40, 30, (int )((u16 )tssi_sel) << 1U); mod_radio_reg(pi, 58, 1, 1); mod_radio_reg(pi, 282, 8, 8); } write_radio_reg(pi, 37, 12); if (pi->pubpi.phy_rev == 2U) { mod_radio_reg(pi, 58, 1, 1); } else if (((int )pi->radio_chanspec & 61440) == 8192) { mod_radio_reg(pi, 58, 2, 2); } else { mod_radio_reg(pi, 58, 2, 0); } if (pi->pubpi.phy_rev == 2U) { mod_radio_reg(pi, 58, 2, 2); } else { mod_radio_reg(pi, 58, 4, 4); } mod_radio_reg(pi, 282, 1, 1); mod_radio_reg(pi, 5, 8, 8); if (! pi->temppwrctrl_capable) { mod_phy_reg(pi, 1239, 28680, 8192); } else { } tmp = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi); rfseq = (u32 )tmp; tab.tbl_id = 8U; tab.tbl_width = 16U; tab.tbl_ptr = (void const *)(& rfseq); tab.tbl_len = 1U; tab.tbl_offset = 6U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); mod_phy_reg(pi, 2360, 4, 4); mod_phy_reg(pi, 2361, 4, 4); mod_phy_reg(pi, 1188, 4096, 4096); mod_phy_reg(pi, 1239, 4, 4); mod_phy_reg(pi, 1239, 3840, 0); mod_radio_reg(pi, 53, 255, 0); mod_radio_reg(pi, 54, 3, 0); mod_radio_reg(pi, 282, 8, 8); wlc_lcnphy_pwrctrl_rssiparams(pi); return; } } void wlc_lcnphy_tx_pwr_update_npt(struct brcms_phy *pi ) { u16 tx_cnt ; u16 tx_total ; u16 npt ; struct brcms_phy_lcnphy *pi_lcn ; u16 tmp ; s8 tmp___0 ; { pi_lcn = pi->u.pi_lcnphy; tx_total = wlapi_bmac_read_shm((pi->sh)->physhim, 224U); tx_cnt = (int )tx_total - (int )pi_lcn->lcnphy_tssi_tx_cnt; tmp = read_phy_reg(pi, 1189); npt = (u16 )(((int )tmp & 1792) >> 8); if ((int )tx_cnt > 1 << (int )npt) { pi_lcn->lcnphy_tssi_tx_cnt = tx_total; tmp___0 = wlc_lcnphy_get_current_tx_pwr_idx(pi); pi_lcn->lcnphy_tssi_idx = (u16 )tmp___0; pi_lcn->lcnphy_tssi_npt = npt; } else { } return; } } s32 wlc_lcnphy_tssi2dbm(s32 tssi , s32 a1 , s32 b0 , s32 b1 ) { s32 a ; s32 b ; s32 p ; { a = a1 * tssi + 32768; b = b0 * 1024 + (b1 * 64) * tssi; p = (b * 2 + a) / (a * 2); return (p); } } static void wlc_lcnphy_txpower_reset_npt(struct brcms_phy *pi ) { struct brcms_phy_lcnphy *pi_lcn ; { pi_lcn = pi->u.pi_lcnphy; if ((int )pi->temppwrctrl_capable) { return; } else { } pi_lcn->lcnphy_tssi_idx = 140U; pi_lcn->lcnphy_tssi_npt = 1U; return; } } void wlc_lcnphy_txpower_recalc_target(struct brcms_phy *pi ) { struct phytbl_info tab ; u32 rate_table[20U] ; uint i ; uint j ; u16 tmp ; { if ((int )pi->temppwrctrl_capable) { return; } else { } i = 0U; j = 0U; goto ldv_37546; ldv_37545: ; if (i == 12U) { j = 20U; } else { } rate_table[i] = (unsigned int )(- ((int )pi->tx_power_offset[j])); i = i + 1U; j = j + 1U; ldv_37546: ; if (i <= 19U) { goto ldv_37545; } else { } tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_len = 20U; tab.tbl_ptr = (void const *)(& rate_table); tab.tbl_offset = 832U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); tmp = read_phy_reg(pi, 1191); if (((int )tmp & 255) != (int )pi->tx_power_min) { mod_phy_reg(pi, 1191, 255, (int )pi->tx_power_min); wlc_lcnphy_txpower_reset_npt(pi); } else { } return; } } static void wlc_lcnphy_set_tx_pwr_soft_ctrl(struct brcms_phy *pi , s8 index ) { u32 cck_offset[4U] ; u32 ofdm_offset ; u32 reg_offset_cck ; int i ; u16 index2 ; struct phytbl_info tab ; { cck_offset[0] = 22U; cck_offset[1] = 22U; cck_offset[2] = 22U; cck_offset[3] = 22U; if ((int )pi->hwpwrctrl_capable) { return; } else { } mod_phy_reg(pi, 1188, 16384, 16384); mod_phy_reg(pi, 1188, 16384, 0); or_phy_reg(pi, 1754, 64); reg_offset_cck = 0U; i = 0; goto ldv_37561; ldv_37560: cck_offset[i] = cck_offset[i] - reg_offset_cck; i = i + 1; ldv_37561: ; if (i <= 3) { goto ldv_37560; } else { } tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_len = 4U; tab.tbl_ptr = (void const *)(& cck_offset); tab.tbl_offset = 832U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); ofdm_offset = 0U; tab.tbl_len = 1U; tab.tbl_ptr = (void const *)(& ofdm_offset); i = 836; goto ldv_37564; ldv_37563: tab.tbl_offset = (u32 )i; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); i = i + 1; ldv_37564: ; if (i <= 861) { goto ldv_37563; } else { } mod_phy_reg(pi, 1188, 32768, 32768); mod_phy_reg(pi, 1188, 16384, 16384); mod_phy_reg(pi, 1188, 8192, 8192); mod_phy_reg(pi, 1200, 128, 0); mod_phy_reg(pi, 1083, 64, 0); mod_phy_reg(pi, 1193, 32768, 32768); index2 = (unsigned int )((unsigned short )index) * 2U; mod_phy_reg(pi, 1193, 511, (int )index2); mod_phy_reg(pi, 1699, 16, 0); return; } } static s8 wlc_lcnphy_tempcompensated_txpwrctrl(struct brcms_phy *pi ) { s8 index ; s8 delta_brd ; s8 delta_temp ; s8 new_index ; s8 tempcorrx ; s16 manp ; s16 meas_temp ; s16 temp_diff ; bool neg ; u16 temp ; struct brcms_phy_lcnphy *pi_lcn ; u32 tmp ; { neg = 0; pi_lcn = pi->u.pi_lcnphy; if ((int )pi->hwpwrctrl_capable) { return ((s8 )pi_lcn->lcnphy_current_index); } else { } index = 78; if ((unsigned int )pi_lcn->lcnphy_tempsense_slope == 0U) { return (index); } else { } temp = wlc_lcnphy_tempsense(pi, 0); meas_temp = (unsigned int )temp > 255U ? (short )((unsigned int )temp - 512U) : (short )temp; if ((unsigned int )pi->tx_power_min != 0U) { delta_brd = (s8 )((int )pi_lcn->lcnphy_measPower - (int )pi->tx_power_min); } else { delta_brd = 0; } manp = (unsigned int )pi_lcn->lcnphy_rawtempsense > 255U ? (short )((unsigned int )pi_lcn->lcnphy_rawtempsense - 512U) : (short )pi_lcn->lcnphy_rawtempsense; temp_diff = (s16 )((int )((unsigned short )manp) - (int )((unsigned short )meas_temp)); if ((int )temp_diff < 0) { neg = 1; temp_diff = (s16 )(- ((int )((unsigned short )temp_diff))); } else { } tmp = wlc_lcnphy_qdiv_roundup((unsigned int )((int )temp_diff * 192), (unsigned int )((int )pi_lcn->lcnphy_tempsense_slope * 10), 0); delta_temp = (signed char )tmp; if ((int )neg) { delta_temp = (s8 )(- ((int )((unsigned char )delta_temp))); } else { } if ((unsigned int )pi_lcn->lcnphy_tempsense_option == 3U && pi->pubpi.phy_rev == 0U) { delta_temp = 0; } else { } if ((unsigned int )pi_lcn->lcnphy_tempcorrx > 31U) { tempcorrx = (signed char )((unsigned int )pi_lcn->lcnphy_tempcorrx - 64U); } else { tempcorrx = (signed char )pi_lcn->lcnphy_tempcorrx; } if (pi->pubpi.phy_rev == 1U) { tempcorrx = 4; } else { } new_index = (s8 )((((int )((unsigned char )index) + (int )((unsigned char )delta_brd)) + (int )((unsigned char )delta_temp)) - (int )((unsigned char )pi_lcn->lcnphy_bandedge_corr)); new_index = (s8 )((int )((unsigned char )new_index) + (int )((unsigned char )tempcorrx)); if (pi->pubpi.phy_rev == 1U) { index = 127; } else { } if ((int )new_index < 0 || (int )new_index == 127) { return (index); } else { } return (new_index); } } static u16 wlc_lcnphy_set_tx_pwr_ctrl_mode(struct brcms_phy *pi , u16 mode ) { u16 current_mode ; { current_mode = mode; if ((int )pi->temppwrctrl_capable && (unsigned int )mode == 57344U) { current_mode = 57345U; } else { } if ((int )pi->hwpwrctrl_capable && (unsigned int )mode == 57345U) { current_mode = 57344U; } else { } return (current_mode); } } void wlc_lcnphy_set_tx_pwr_ctrl(struct brcms_phy *pi , u16 mode ) { u16 old_mode ; u16 tmp ; s8 index ; struct brcms_phy_lcnphy *pi_lcn ; u16 tmp___0 ; { tmp = read_phy_reg(pi, 1188); old_mode = (unsigned int )tmp & 57344U; pi_lcn = pi->u.pi_lcnphy; mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, (int )mode); old_mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, (int )old_mode); mod_phy_reg(pi, 1754, 64, (unsigned int )mode == 57344U ? 64 : 0); mod_phy_reg(pi, 1699, 16, (unsigned int )mode != 57344U ? 16 : 0); if ((int )old_mode != (int )mode) { if ((unsigned int )old_mode == 57344U) { wlc_lcnphy_tx_pwr_update_npt(pi); wlc_lcnphy_clear_tx_power_offsets(pi); } else { } if ((unsigned int )mode == 57344U) { wlc_lcnphy_txpower_recalc_target(pi); mod_phy_reg(pi, 1188, 511, (int )pi_lcn->lcnphy_tssi_idx); mod_phy_reg(pi, 1189, 1792, (int )pi_lcn->lcnphy_tssi_npt << 8U); mod_radio_reg(pi, 287, 4, 0); pi_lcn->lcnphy_tssi_tx_cnt = wlapi_bmac_read_shm((pi->sh)->physhim, 224U); wlc_lcnphy_set_tx_gain_override(pi, 0); pi_lcn->lcnphy_tx_power_idx_override = -1; } else { wlc_lcnphy_set_tx_gain_override(pi, 1); } mod_phy_reg(pi, 1188, 57344, (int )mode); if ((unsigned int )mode == 57345U) { index = wlc_lcnphy_tempcompensated_txpwrctrl(pi); wlc_lcnphy_set_tx_pwr_soft_ctrl(pi, (int )index); tmp___0 = read_phy_reg(pi, 1193); pi_lcn->lcnphy_current_index = (u8 )(((int )tmp___0 & 255) / 2); } else { } } else { } return; } } static void wlc_lcnphy_tx_iqlo_loopback(struct brcms_phy *pi , u16 *values_to_save ) { u16 vmid ; int i ; { i = 0; goto ldv_37599; ldv_37598: *(values_to_save + (unsigned long )i) = read_radio_reg(pi, (int )iqlo_loopback_rf_regs[i]); i = i + 1; ldv_37599: ; if (i <= 19) { goto ldv_37598; } else { } mod_phy_reg(pi, 1100, 4096, 4096); mod_phy_reg(pi, 1101, 16384, 16384); mod_phy_reg(pi, 1100, 2048, 2048); mod_phy_reg(pi, 1101, 8192, 0); mod_phy_reg(pi, 1083, 2, 2); mod_phy_reg(pi, 1084, 2, 0); mod_phy_reg(pi, 1083, 1, 1); mod_phy_reg(pi, 1084, 1, 0); if (pi->pubpi.phy_rev == 2U) { and_radio_reg(pi, 58, 253); } else { and_radio_reg(pi, 58, 249); } or_radio_reg(pi, 282, 1); or_radio_reg(pi, 54, 1); or_radio_reg(pi, 282, 24); __const_udelay(85900UL); if (pi->pubpi.phy_rev == 2U) { if (((int )pi->radio_chanspec & 61440) == 4096) { mod_radio_reg(pi, 58, 1, 0); } else { or_radio_reg(pi, 58, 1); } } else if (((int )pi->radio_chanspec & 61440) == 4096) { mod_radio_reg(pi, 58, 3, 1); } else { or_radio_reg(pi, 58, 3); } __const_udelay(85900UL); write_radio_reg(pi, 37, 15); if (pi->pubpi.phy_rev == 2U) { if (((int )pi->radio_chanspec & 61440) == 4096) { mod_radio_reg(pi, 40, 15, 4); } else { mod_radio_reg(pi, 40, 15, 6); } } else if (((int )pi->radio_chanspec & 61440) == 4096) { mod_radio_reg(pi, 40, 30, 8); } else { mod_radio_reg(pi, 40, 30, 12); } __const_udelay(85900UL); write_radio_reg(pi, 5, 8); or_radio_reg(pi, 274, 128); __const_udelay(85900UL); or_radio_reg(pi, 255, 16); or_radio_reg(pi, 287, 68); __const_udelay(85900UL); or_radio_reg(pi, 11, 7); or_radio_reg(pi, 275, 16); __const_udelay(85900UL); write_radio_reg(pi, 7, 1); __const_udelay(85900UL); vmid = 678U; mod_radio_reg(pi, 252, 3, ((int )vmid >> 8) & 3); write_radio_reg(pi, 253, (int )vmid & 255); or_radio_reg(pi, 287, 68); __const_udelay(85900UL); or_radio_reg(pi, 255, 16); __const_udelay(85900UL); write_radio_reg(pi, 18, 2); or_radio_reg(pi, 274, 6); write_radio_reg(pi, 54, 17); write_radio_reg(pi, 89, 204); write_radio_reg(pi, 92, 46); write_radio_reg(pi, 120, 215); write_radio_reg(pi, 146, 21); return; } } static bool wlc_lcnphy_iqcal_wait(struct brcms_phy *pi ) { uint delay_count ; u16 tmp ; u16 tmp___0 ; { delay_count = 0U; goto ldv_37607; ldv_37606: __const_udelay(429500UL); delay_count = delay_count + 1U; if (delay_count > 5000U) { goto ldv_37605; } else { } ldv_37607: tmp = read_phy_reg(pi, 1105); if (((int )tmp & 49152) != 0) { goto ldv_37606; } else { } ldv_37605: tmp___0 = read_phy_reg(pi, 1105); return (((int )tmp___0 & 49152) == 0); } } static void wlc_lcnphy_tx_iqlo_loopback_cleanup(struct brcms_phy *pi , u16 *values_to_save ) { int i ; { and_phy_reg(pi, 1100, 0); and_phy_reg(pi, 1083, 12); i = 0; goto ldv_37614; ldv_37613: write_radio_reg(pi, (int )iqlo_loopback_rf_regs[i], (int )*(values_to_save + (unsigned long )i)); i = i + 1; ldv_37614: ; if (i <= 19) { goto ldv_37613; } else { } return; } } static void wlc_lcnphy_tx_iqlo_cal(struct brcms_phy *pi , struct lcnphy_txgains *target_gains , enum lcnphy_cal_mode cal_mode , bool keep_tone ) { struct lcnphy_txgains cal_gains ; struct lcnphy_txgains temp_gains ; u16 hash ; u8 band_idx ; int j ; u16 ncorr_override[5U] ; u16 syst_coeffs[11U] ; u16 commands_fullcal[6U] ; u16 commands_recal[6U] ; u16 command_nums_fullcal[6U] ; u16 command_nums_recal[6U] ; u16 *command_nums ; u16 *start_coeffs ; u16 *cal_cmds ; u16 cal_type ; u16 diq_start ; u16 tx_pwr_ctrl_old ; u16 save_txpwrctrlrfctrl2 ; u16 save_sslpnCalibClkEnCtrl ; u16 save_sslpnRxFeClkEnCtrl ; bool tx_gain_override_old ; struct lcnphy_txgains old_gains ; uint i ; uint n_cal_cmds ; uint n_cal_start ; u16 *values_to_save ; struct brcms_phy_lcnphy *pi_lcn ; void *tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 zero_diq ; u16 best_coeffs[11U] ; u16 command_num ; bool tmp___2 ; int tmp___3 ; { syst_coeffs[0] = 0U; syst_coeffs[1] = 0U; syst_coeffs[2] = 0U; syst_coeffs[3] = 0U; syst_coeffs[4] = 0U; syst_coeffs[5] = 0U; syst_coeffs[6] = 0U; syst_coeffs[7] = 0U; syst_coeffs[8] = 0U; syst_coeffs[9] = 0U; syst_coeffs[10] = 0U; commands_fullcal[0] = 33844U; commands_fullcal[1] = 33588U; commands_fullcal[2] = 32900U; commands_fullcal[3] = 33383U; commands_fullcal[4] = 32854U; commands_fullcal[5] = 33332U; commands_recal[0] = 33844U; commands_recal[1] = 33588U; commands_recal[2] = 32900U; commands_recal[3] = 33383U; commands_recal[4] = 32854U; commands_recal[5] = 33332U; command_nums_fullcal[0] = 31383U; command_nums_fullcal[1] = 31383U; command_nums_fullcal[2] = 31383U; command_nums_fullcal[3] = 31367U; command_nums_fullcal[4] = 31367U; command_nums_fullcal[5] = 31639U; command_nums_recal[0] = 31383U; command_nums_recal[1] = 31383U; command_nums_recal[2] = 31383U; command_nums_recal[3] = 31367U; command_nums_recal[4] = 31367U; command_nums_recal[5] = 31639U; command_nums = (u16 *)(& command_nums_fullcal); start_coeffs = (u16 *)0U; cal_cmds = (u16 *)0U; n_cal_cmds = 0U; n_cal_start = 0U; pi_lcn = pi->u.pi_lcnphy; tmp = kmalloc(40UL, 32U); values_to_save = (u16 *)tmp; if ((unsigned long )values_to_save == (unsigned long )((u16 *)0U)) { return; } else { } save_sslpnRxFeClkEnCtrl = read_phy_reg(pi, 1755); save_sslpnCalibClkEnCtrl = read_phy_reg(pi, 1754); or_phy_reg(pi, 1754, 64); or_phy_reg(pi, 1755, 3); switch ((unsigned int )cal_mode) { case 0U: start_coeffs = (u16 *)(& syst_coeffs); cal_cmds = (u16 *)(& commands_fullcal); n_cal_cmds = 6U; goto ldv_37652; case 1U: start_coeffs = (u16 *)(& syst_coeffs); cal_cmds = (u16 *)(& commands_recal); n_cal_cmds = 6U; command_nums = (u16 *)(& command_nums_recal); goto ldv_37652; default: ; goto ldv_37652; } ldv_37652: wlc_lcnphy_common_write_table(pi, 0U, (u16 const *)start_coeffs, 11U, 16U, 64U); write_phy_reg(pi, 1754, 65535); mod_phy_reg(pi, 1283, 8, 8); tmp___0 = read_phy_reg(pi, 1188); tx_pwr_ctrl_old = (unsigned int )tmp___0 & 57344U; mod_phy_reg(pi, 1188, 4096, 4096); wlc_lcnphy_set_tx_pwr_ctrl(pi, 0); save_txpwrctrlrfctrl2 = read_phy_reg(pi, 1243); mod_phy_reg(pi, 1243, 1023, 678); mod_phy_reg(pi, 1243, 28672, 8192); wlc_lcnphy_tx_iqlo_loopback(pi, values_to_save); tmp___1 = read_phy_reg(pi, 1083); tx_gain_override_old = ((int )tmp___1 & 64) != 0; if ((int )tx_gain_override_old) { wlc_lcnphy_get_tx_gain(pi, & old_gains); } else { } if ((unsigned long )target_gains == (unsigned long )((struct lcnphy_txgains *)0)) { if (! tx_gain_override_old) { wlc_lcnphy_set_tx_pwr_by_index(pi, (int )pi_lcn->lcnphy_tssi_idx); } else { } wlc_lcnphy_get_tx_gain(pi, & temp_gains); target_gains = & temp_gains; } else { } hash = (u16 )(((int )((short )((int )target_gains->gm_gain << 8)) | (int )((short )((int )target_gains->pga_gain << 4))) | (int )((short )target_gains->pad_gain)); band_idx = ((int )pi->radio_chanspec & 61440) == 4096; cal_gains = *target_gains; memset((void *)(& ncorr_override), 0, 10UL); j = 0; goto ldv_37659; ldv_37658: ; if ((int )(*(tbl_iqcal_gainparams_lcnphy[(int )band_idx] + (unsigned long )j))[0] == (int )hash) { cal_gains.gm_gain = (*(tbl_iqcal_gainparams_lcnphy[(int )band_idx] + (unsigned long )j))[1]; cal_gains.pga_gain = (*(tbl_iqcal_gainparams_lcnphy[(int )band_idx] + (unsigned long )j))[2]; cal_gains.pad_gain = (*(tbl_iqcal_gainparams_lcnphy[(int )band_idx] + (unsigned long )j))[3]; memcpy((void *)(& ncorr_override), (void const *)tbl_iqcal_gainparams_lcnphy[(int )band_idx] + ((unsigned long )j + 3UL), 10UL); goto ldv_37657; } else { } j = j + 1; ldv_37659: ; if ((int )iqcal_gainparams_numgains_lcnphy[(int )band_idx] > j) { goto ldv_37658; } else { } ldv_37657: wlc_lcnphy_set_tx_gain(pi, & cal_gains); write_phy_reg(pi, 1107, 2729); write_phy_reg(pi, 2365, 192); wlc_lcnphy_common_write_table(pi, 0U, (u16 const *)(& lcnphy_iqcal_loft_gainladder), 20U, 16U, 0U); wlc_lcnphy_common_write_table(pi, 0U, (u16 const *)(& lcnphy_iqcal_ir_gainladder), 20U, 16U, 32U); if (pi->phy_tx_tone_freq != 0U) { wlc_lcnphy_stop_tx_tone(pi); __const_udelay(21475UL); wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1); } else { wlc_lcnphy_start_tx_tone(pi, 3750, 88, 1); } write_phy_reg(pi, 1754, 65535); i = n_cal_start; goto ldv_37675; ldv_37674: zero_diq = 0U; cal_type = (u16 )(((int )*(cal_cmds + (unsigned long )i) & 3840) >> 8); command_num = *(command_nums + (unsigned long )i); if ((unsigned int )ncorr_override[(int )cal_type] != 0U) { command_num = (u16 )((int )((short )((int )ncorr_override[(int )cal_type] << 8)) | ((int )((short )command_num) & 255)); } else { } write_phy_reg(pi, 1106, (int )command_num); if ((unsigned int )cal_type == 3U || (unsigned int )cal_type == 4U) { wlc_lcnphy_common_read_table(pi, 0U, (u16 const *)(& diq_start), 1U, 16U, 69U); wlc_lcnphy_common_write_table(pi, 0U, (u16 const *)(& zero_diq), 1U, 16U, 69U); } else { } write_phy_reg(pi, 1105, (int )*(cal_cmds + (unsigned long )i)); tmp___2 = wlc_lcnphy_iqcal_wait(pi); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { goto cleanup; } else { } wlc_lcnphy_common_read_table(pi, 0U, (u16 const *)(& best_coeffs), 11U, 16U, 96U); wlc_lcnphy_common_write_table(pi, 0U, (u16 const *)(& best_coeffs), 11U, 16U, 64U); if ((unsigned int )cal_type == 3U || (unsigned int )cal_type == 4U) { wlc_lcnphy_common_write_table(pi, 0U, (u16 const *)(& diq_start), 1U, 16U, 69U); } else { } wlc_lcnphy_common_read_table(pi, 0U, (u16 const *)(& pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs), 11U, 16U, 96U); i = i + 1U; ldv_37675: ; if (i < n_cal_cmds) { goto ldv_37674; } else { } wlc_lcnphy_common_read_table(pi, 0U, (u16 const *)(& pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs), 11U, 16U, 96U); pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs_valid = 1U; wlc_lcnphy_common_write_table(pi, 0U, (u16 const *)(& pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs), 4U, 16U, 80U); wlc_lcnphy_common_write_table(pi, 0U, (u16 const *)(& pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs) + 5U, 2U, 16U, 85U); cleanup: wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, values_to_save); kfree((void const *)values_to_save); if (! keep_tone) { wlc_lcnphy_stop_tx_tone(pi); } else { } write_phy_reg(pi, 1243, (int )save_txpwrctrlrfctrl2); write_phy_reg(pi, 1107, 0); if ((int )tx_gain_override_old) { wlc_lcnphy_set_tx_gain(pi, & old_gains); } else { } wlc_lcnphy_set_tx_pwr_ctrl(pi, (int )tx_pwr_ctrl_old); write_phy_reg(pi, 1754, (int )save_sslpnCalibClkEnCtrl); write_phy_reg(pi, 1755, (int )save_sslpnRxFeClkEnCtrl); return; } } static void wlc_lcnphy_idle_tssi_est(struct brcms_phy_pub *ppi ) { bool suspend ; bool tx_gain_override_old ; struct lcnphy_txgains old_gains ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u16 idleTssi ; u16 idleTssi0_2C ; u16 idleTssi0_OB ; u16 idleTssi0_regvalue_OB ; u16 idleTssi0_regvalue_2C ; u16 SAVE_txpwrctrl ; u16 tmp ; u16 SAVE_lpfgain ; u16 tmp___0 ; u16 SAVE_jtag_bb_afe_switch ; u16 tmp___1 ; u16 SAVE_jtag_auxpga ; u16 tmp___2 ; u16 SAVE_iqadc_aux_en ; u16 tmp___3 ; u8 SAVE_bbmult ; u8 tmp___4 ; u32 tmp___5 ; u16 tmp___6 ; u16 tmp___7 ; u16 tmp___8 ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; tmp = read_phy_reg(pi, 1188); SAVE_txpwrctrl = (unsigned int )tmp & 57344U; tmp___0 = read_radio_reg(pi, 274); SAVE_lpfgain = tmp___0; tmp___1 = read_radio_reg(pi, 7); SAVE_jtag_bb_afe_switch = (unsigned int )tmp___1 & 1U; tmp___2 = read_radio_reg(pi, 255); SAVE_jtag_auxpga = (unsigned int )tmp___2 & 16U; tmp___3 = read_radio_reg(pi, 287); SAVE_iqadc_aux_en = (unsigned int )tmp___3 & 4U; tmp___4 = wlc_lcnphy_get_bbmult(pi); SAVE_bbmult = tmp___4; idleTssi = read_phy_reg(pi, 1195); tmp___5 = bcma_read32(pi->d11core, 288); suspend = (tmp___5 & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_lcnphy_set_tx_pwr_ctrl(pi, 0); tmp___6 = read_phy_reg(pi, 1083); tx_gain_override_old = ((int )tmp___6 & 64) != 0; wlc_lcnphy_get_tx_gain(pi, & old_gains); wlc_lcnphy_set_tx_gain_override(pi, 1); wlc_lcnphy_set_tx_pwr_by_index(pi, 127); write_radio_reg(pi, 274, 6); mod_radio_reg(pi, 7, 1, 1); mod_radio_reg(pi, 255, 16, 16); mod_radio_reg(pi, 287, 4, 4); wlc_lcnphy_tssi_setup(pi); mod_phy_reg(pi, 1239, 1, 1); mod_phy_reg(pi, 1239, 64, 64); wlc_lcnphy_set_bbmult(pi, 0); wlc_phy_do_dummy_tx(pi, 1, 0); tmp___7 = read_phy_reg(pi, 1195); idleTssi = (unsigned int )tmp___7 & 511U; tmp___8 = read_phy_reg(pi, 1598); idleTssi0_2C = (unsigned int )tmp___8 & 511U; if ((unsigned int )idleTssi0_2C > 255U) { idleTssi0_OB = (unsigned int )idleTssi0_2C + 65280U; } else { idleTssi0_OB = (unsigned int )idleTssi0_2C + 256U; } idleTssi0_regvalue_OB = idleTssi0_OB; if ((unsigned int )idleTssi0_regvalue_OB > 255U) { idleTssi0_regvalue_2C = (unsigned int )idleTssi0_regvalue_OB + 65280U; } else { idleTssi0_regvalue_2C = (unsigned int )idleTssi0_regvalue_OB + 256U; } mod_phy_reg(pi, 1190, 511, (int )idleTssi0_regvalue_2C); mod_phy_reg(pi, 1100, 4096, 0); wlc_lcnphy_set_bbmult(pi, (int )SAVE_bbmult); wlc_lcnphy_set_tx_gain_override(pi, (int )tx_gain_override_old); wlc_lcnphy_set_tx_gain(pi, & old_gains); wlc_lcnphy_set_tx_pwr_ctrl(pi, (int )SAVE_txpwrctrl); write_radio_reg(pi, 274, (int )SAVE_lpfgain); mod_radio_reg(pi, 7, 1, (int )SAVE_jtag_bb_afe_switch); mod_radio_reg(pi, 255, 16, (int )SAVE_jtag_auxpga); mod_radio_reg(pi, 287, 4, (int )SAVE_iqadc_aux_en); mod_radio_reg(pi, 274, 128, 128); if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } return; } } static void wlc_lcnphy_vbat_temp_sense_setup(struct brcms_phy *pi , u8 mode ) { bool suspend ; u16 save_txpwrCtrlEn ; u8 auxpga_vmidcourse ; u8 auxpga_vmidfine ; u8 auxpga_gain ; u16 auxpga_vmid ; struct phytbl_info tab ; u32 val ; u8 save_reg007 ; u8 save_reg0FF ; u8 save_reg11F ; u8 save_reg005 ; u8 save_reg025 ; u8 save_reg112 ; u16 values_to_save[14U] ; s8 index ; int i ; struct brcms_phy_lcnphy *pi_lcn ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; u16 tmp___3 ; u16 tmp___4 ; u32 tmp___5 ; u16 tmp___6 ; u16 tmp___7 ; { pi_lcn = pi->u.pi_lcnphy; __const_udelay(4290705UL); tmp = read_radio_reg(pi, 7); save_reg007 = (unsigned char )tmp; tmp___0 = read_radio_reg(pi, 255); save_reg0FF = (unsigned char )tmp___0; tmp___1 = read_radio_reg(pi, 287); save_reg11F = (unsigned char )tmp___1; tmp___2 = read_radio_reg(pi, 5); save_reg005 = (unsigned char )tmp___2; tmp___3 = read_radio_reg(pi, 37); save_reg025 = (unsigned char )tmp___3; tmp___4 = read_radio_reg(pi, 274); save_reg112 = (unsigned char )tmp___4; i = 0; goto ldv_37722; ldv_37721: values_to_save[i] = read_phy_reg(pi, (int )tempsense_phy_regs[i]); i = i + 1; ldv_37722: ; if (i <= 13) { goto ldv_37721; } else { } tmp___5 = bcma_read32(pi->d11core, 288); suspend = (tmp___5 & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } save_txpwrCtrlEn = read_radio_reg(pi, 1188); wlc_lcnphy_set_tx_pwr_ctrl(pi, 0); index = (s8 )pi_lcn->lcnphy_current_index; wlc_lcnphy_set_tx_pwr_by_index(pi, 127); mod_radio_reg(pi, 7, 1, 1); mod_radio_reg(pi, 255, 16, 16); mod_radio_reg(pi, 287, 4, 4); mod_phy_reg(pi, 1283, 1, 0); mod_phy_reg(pi, 1283, 4, 0); mod_phy_reg(pi, 1188, 16384, 0); mod_phy_reg(pi, 1188, 32768, 0); mod_phy_reg(pi, 1232, 32, 0); mod_phy_reg(pi, 1189, 255, 255); mod_phy_reg(pi, 1189, 28672, 20480); mod_phy_reg(pi, 1189, 1792, 0); mod_phy_reg(pi, 1037, 255, 64); mod_phy_reg(pi, 1037, 1792, 1536); mod_phy_reg(pi, 1186, 255, 64); mod_phy_reg(pi, 1186, 1792, 1536); mod_phy_reg(pi, 1241, 112, 32); mod_phy_reg(pi, 1241, 1792, 768); mod_phy_reg(pi, 1241, 28672, 4096); mod_phy_reg(pi, 1242, 4096, 0); mod_phy_reg(pi, 1242, 8192, 8192); mod_phy_reg(pi, 1190, 32768, 32768); write_radio_reg(pi, 37, 12); mod_radio_reg(pi, 5, 8, 8); mod_phy_reg(pi, 2360, 4, 4); mod_phy_reg(pi, 2361, 4, 4); mod_phy_reg(pi, 1188, 4096, 4096); tmp___6 = wlc_lcnphy_rfseq_tbl_adc_pwrup(pi); val = (u32 )tmp___6; tab.tbl_id = 8U; tab.tbl_width = 16U; tab.tbl_len = 1U; tab.tbl_ptr = (void const *)(& val); tab.tbl_offset = 6U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); if ((unsigned int )mode == 1U) { mod_phy_reg(pi, 1239, 8, 8); mod_phy_reg(pi, 1239, 28672, 4096); auxpga_vmidcourse = 8U; auxpga_vmidfine = 4U; auxpga_gain = 2U; mod_radio_reg(pi, 130, 32, 32); } else { mod_phy_reg(pi, 1239, 8, 8); mod_phy_reg(pi, 1239, 28672, 12288); auxpga_vmidcourse = 7U; auxpga_vmidfine = 10U; auxpga_gain = 2U; } auxpga_vmid = (unsigned short )(((int )((short )((int )auxpga_vmidcourse << 4)) | 512) | (int )((short )auxpga_vmidfine)); mod_phy_reg(pi, 1240, 1, 1); mod_phy_reg(pi, 1240, 4092, (int )auxpga_vmid << 2U); mod_phy_reg(pi, 1240, 2, 2); mod_phy_reg(pi, 1240, 28672, (int )((u16 )auxpga_gain) << 12U); mod_phy_reg(pi, 1232, 32, 32); write_radio_reg(pi, 274, 6); wlc_phy_do_dummy_tx(pi, 1, 0); tmp___7 = read_phy_reg(pi, 1142); if ((int )((short )tmp___7) >= 0) { __const_udelay(42950UL); } else { } write_radio_reg(pi, 7, (int )save_reg007); write_radio_reg(pi, 255, (int )save_reg0FF); write_radio_reg(pi, 287, (int )save_reg11F); write_radio_reg(pi, 5, (int )save_reg005); write_radio_reg(pi, 37, (int )save_reg025); write_radio_reg(pi, 274, (int )save_reg112); i = 0; goto ldv_37725; ldv_37724: write_phy_reg(pi, (int )tempsense_phy_regs[i], (int )values_to_save[i]); i = i + 1; ldv_37725: ; if (i <= 13) { goto ldv_37724; } else { } wlc_lcnphy_set_tx_pwr_by_index(pi, (int )index); write_radio_reg(pi, 1188, (int )save_txpwrCtrlEn); if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } __const_udelay(4290705UL); return; } } static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi ) { struct lcnphy_txgains tx_gains ; u8 bbmult ; struct phytbl_info tab ; s32 a1 ; s32 b0 ; s32 b1 ; s32 tssi ; s32 pwr ; s32 maxtargetpwr ; s32 mintargetpwr ; bool suspend ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u32 tmp ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; tmp = bcma_read32(pi->d11core, 288); suspend = (tmp & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } if (! pi->hwpwrctrl_capable) { if (((int )pi->radio_chanspec & 61440) == 8192) { tx_gains.gm_gain = 4U; tx_gains.pga_gain = 12U; tx_gains.pad_gain = 12U; tx_gains.dac_gain = 0U; bbmult = 150U; } else { tx_gains.gm_gain = 7U; tx_gains.pga_gain = 15U; tx_gains.pad_gain = 14U; tx_gains.dac_gain = 0U; bbmult = 150U; } wlc_lcnphy_set_tx_gain(pi, & tx_gains); wlc_lcnphy_set_bbmult(pi, (int )bbmult); wlc_lcnphy_vbat_temp_sense_setup(pi, 1); } else { wlc_lcnphy_idle_tssi_est(ppi); wlc_lcnphy_clear_tx_power_offsets(pi); b0 = (s32 )pi->txpa_2g[0]; b1 = (s32 )pi->txpa_2g[1]; a1 = (s32 )pi->txpa_2g[2]; maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1); mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1); tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_ptr = (void const *)(& pwr); tab.tbl_len = 1U; tab.tbl_offset = 0U; tssi = 0; goto ldv_37745; ldv_37744: pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1); pwr = mintargetpwr > pwr ? mintargetpwr : pwr; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); tab.tbl_offset = tab.tbl_offset + 1U; tssi = tssi + 1; ldv_37745: ; if (tssi <= 127) { goto ldv_37744; } else { } mod_phy_reg(pi, 1232, 1, 0); mod_phy_reg(pi, 1235, 255, 0); mod_phy_reg(pi, 1235, 65280, 0); mod_phy_reg(pi, 1232, 16, 0); mod_phy_reg(pi, 1232, 4, 0); mod_phy_reg(pi, 1040, 128, 0); write_phy_reg(pi, 1192, 10); mod_phy_reg(pi, 1191, 255, 60); wlc_lcnphy_set_tx_pwr_ctrl(pi, 57344); } if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } return; } } static void wlc_lcnphy_set_pa_gain(struct brcms_phy *pi , u16 gain ) { { mod_phy_reg(pi, 1275, 32512, (int )gain << 8U); mod_phy_reg(pi, 1277, 32512, (int )gain << 8U); return; } } void wlc_lcnphy_get_radio_loft(struct brcms_phy *pi , u8 *ei0 , u8 *eq0 , u8 *fi0 , u8 *fq0 ) { u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; u16 tmp___3 ; u16 tmp___4 ; u16 tmp___5 ; u16 tmp___6 ; { tmp = read_radio_reg(pi, 137); tmp___0 = read_radio_reg(pi, 137); *ei0 = ((unsigned int )((unsigned char )tmp) & 15U) - (unsigned int )((unsigned char )(((int )tmp___0 & 240) >> 4)); tmp___1 = read_radio_reg(pi, 138); tmp___2 = read_radio_reg(pi, 138); *eq0 = ((unsigned int )((unsigned char )tmp___1) & 15U) - (unsigned int )((unsigned char )(((int )tmp___2 & 240) >> 4)); tmp___3 = read_radio_reg(pi, 139); tmp___4 = read_radio_reg(pi, 139); *fi0 = ((unsigned int )((unsigned char )tmp___3) & 15U) - (unsigned int )((unsigned char )(((int )tmp___4 & 240) >> 4)); tmp___5 = read_radio_reg(pi, 140); tmp___6 = read_radio_reg(pi, 140); *fq0 = ((unsigned int )((unsigned char )tmp___5) & 15U) - (unsigned int )((unsigned char )(((int )tmp___6 & 240) >> 4)); return; } } void wlc_lcnphy_set_tx_iqcc(struct brcms_phy *pi , u16 a , u16 b ) { struct phytbl_info tab ; u16 iqcc[2U] ; { iqcc[0] = a; iqcc[1] = b; tab.tbl_id = 0U; tab.tbl_width = 16U; tab.tbl_ptr = (void const *)(& iqcc); tab.tbl_len = 2U; tab.tbl_offset = 80U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); return; } } void wlc_lcnphy_set_tx_locc(struct brcms_phy *pi , u16 didq ) { struct phytbl_info tab ; { tab.tbl_id = 0U; tab.tbl_width = 16U; tab.tbl_ptr = (void const *)(& didq); tab.tbl_len = 1U; tab.tbl_offset = 85U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); return; } } void wlc_lcnphy_set_tx_pwr_by_index(struct brcms_phy *pi , int index ) { struct phytbl_info tab ; u16 a ; u16 b ; u8 bb_mult ; u32 bbmultiqcomp ; u32 txgain ; u32 locoeffs ; u32 rfpower ; struct lcnphy_txgains gains ; struct brcms_phy_lcnphy *pi_lcn ; { pi_lcn = pi->u.pi_lcnphy; pi_lcn->lcnphy_tx_power_idx_override = (signed char )index; pi_lcn->lcnphy_current_index = (unsigned char )index; tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_len = 1U; wlc_lcnphy_set_tx_pwr_ctrl(pi, 0); tab.tbl_offset = (u32 )(index + 320); tab.tbl_ptr = (void const *)(& bbmultiqcomp); wlc_lcnphy_read_table(pi, & tab); tab.tbl_offset = (u32 )(index + 192); tab.tbl_width = 32U; tab.tbl_ptr = (void const *)(& txgain); wlc_lcnphy_read_table(pi, & tab); gains.gm_gain = (unsigned int )((unsigned short )txgain) & 255U; gains.pga_gain = (unsigned int )((u16 )(txgain >> 8)) & 255U; gains.pad_gain = (unsigned int )((u16 )(txgain >> 16)) & 255U; gains.dac_gain = (unsigned int )((u16 )(bbmultiqcomp >> 28)) & 7U; wlc_lcnphy_set_tx_gain(pi, & gains); wlc_lcnphy_set_pa_gain(pi, (int )((u16 )(txgain >> 24)) & 127); bb_mult = (unsigned char )(bbmultiqcomp >> 20); wlc_lcnphy_set_bbmult(pi, (int )bb_mult); wlc_lcnphy_set_tx_gain_override(pi, 1); if (! pi->temppwrctrl_capable) { a = (unsigned int )((unsigned short )(bbmultiqcomp >> 10)) & 1023U; b = (unsigned int )((unsigned short )bbmultiqcomp) & 1023U; wlc_lcnphy_set_tx_iqcc(pi, (int )a, (int )b); tab.tbl_offset = (u32 )(index + 448); tab.tbl_ptr = (void const *)(& locoeffs); wlc_lcnphy_read_table(pi, & tab); wlc_lcnphy_set_tx_locc(pi, (int )((unsigned short )locoeffs)); tab.tbl_offset = (u32 )(index + 576); tab.tbl_ptr = (void const *)(& rfpower); wlc_lcnphy_read_table(pi, & tab); mod_phy_reg(pi, 1702, 8191, (int )((unsigned int )((u16 )rfpower) * 8U)); } else { } return; } } static void wlc_lcnphy_clear_papd_comptable(struct brcms_phy *pi ) { u32 j ; struct phytbl_info tab ; u32 temp_offset[128U] ; { tab.tbl_ptr = (void const *)(& temp_offset); tab.tbl_len = 128U; tab.tbl_id = 24U; tab.tbl_width = 32U; tab.tbl_offset = 0U; memset((void *)(& temp_offset), 0, 512UL); j = 1U; goto ldv_37791; ldv_37790: temp_offset[j] = 524288U; j = j + 2U; ldv_37791: ; if (j <= 127U) { goto ldv_37790; } else { } wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); return; } } void wlc_lcnphy_tx_pu(struct brcms_phy *pi , bool bEnable ) { { if (! bEnable) { and_phy_reg(pi, 1083, 65517); mod_phy_reg(pi, 1084, 2, 2); and_phy_reg(pi, 1100, 61392); and_phy_reg(pi, 1101, 49111); mod_phy_reg(pi, 1101, 4, 4); mod_phy_reg(pi, 1101, 3, 1); and_phy_reg(pi, 1273, 65528); and_phy_reg(pi, 1274, 65528); } else { mod_phy_reg(pi, 1083, 2, 2); mod_phy_reg(pi, 1084, 2, 0); mod_phy_reg(pi, 1083, 16, 16); mod_phy_reg(pi, 1084, 64, 0); mod_phy_reg(pi, 1100, 4096, 4096); mod_phy_reg(pi, 1101, 16384, 16384); wlc_lcnphy_set_trsw_override(pi, 1, 0); mod_phy_reg(pi, 1101, 4, 0); mod_phy_reg(pi, 1100, 4, 4); if (((int )pi->radio_chanspec & 61440) == 8192) { mod_phy_reg(pi, 1100, 8, 8); mod_phy_reg(pi, 1101, 8, 8); mod_phy_reg(pi, 1100, 32, 32); mod_phy_reg(pi, 1101, 32, 0); mod_phy_reg(pi, 1273, 2, 2); mod_phy_reg(pi, 1274, 2, 2); mod_phy_reg(pi, 1273, 4, 4); mod_phy_reg(pi, 1274, 4, 4); mod_phy_reg(pi, 1273, 1, 1); mod_phy_reg(pi, 1274, 1, 1); } else { mod_phy_reg(pi, 1100, 8, 8); mod_phy_reg(pi, 1101, 8, 0); mod_phy_reg(pi, 1100, 32, 32); mod_phy_reg(pi, 1101, 32, 32); mod_phy_reg(pi, 1273, 2, 2); mod_phy_reg(pi, 1274, 2, 0); mod_phy_reg(pi, 1273, 4, 4); mod_phy_reg(pi, 1274, 4, 0); mod_phy_reg(pi, 1273, 1, 1); mod_phy_reg(pi, 1274, 1, 0); } } return; } } static void wlc_lcnphy_run_samples(struct brcms_phy *pi , u16 num_samps , u16 num_loops , u16 wait , bool iqcalmode ) { { or_phy_reg(pi, 1754, 32896); mod_phy_reg(pi, 1602, 127, (int )((unsigned int )num_samps + 65535U)); if ((unsigned int )num_loops != 65535U) { num_loops = (u16 )((int )num_loops - 1); } else { } mod_phy_reg(pi, 1600, 65535, (int )num_loops); mod_phy_reg(pi, 1601, 65535, (int )wait); if ((int )iqcalmode) { and_phy_reg(pi, 1107, 32767); or_phy_reg(pi, 1107, 32768); } else { write_phy_reg(pi, 1599, 1); wlc_lcnphy_tx_pu(pi, 1); } or_radio_reg(pi, 274, 6); return; } } void wlc_lcnphy_deaf_mode(struct brcms_phy *pi , bool mode ) { u8 phybw40 ; { phybw40 = ((int )pi->radio_chanspec & 3072) == 3072; if (pi->pubpi.phy_rev <= 1U) { mod_phy_reg(pi, 1200, 32, (int )((u16 )mode) << 5U); mod_phy_reg(pi, 1201, 512, 0); } else { mod_phy_reg(pi, 1200, 32, (int )((u16 )mode) << 5U); mod_phy_reg(pi, 1201, 512, 0); } if ((unsigned int )phybw40 == 0U) { mod_phy_reg(pi, 1040, 96, (int )((u16 )((((int )pi->radio_chanspec & 61440) == 8192 ? (short )(! mode << 6) : 0) | (int )((short )(! mode << 5))))); mod_phy_reg(pi, 1040, 128, (int )((u16 )mode) << 7U); } else { } return; } } void wlc_lcnphy_start_tx_tone(struct brcms_phy *pi , s32 f_kHz , u16 max_val , bool iqcalmode ) { u8 phy_bw ; u16 num_samps ; u16 t ; u16 k ; u32 bw ; s32 theta ; s32 rot ; struct cordic_iq tone_samp ; u32 data_buf[64U] ; u16 i_samp ; u16 q_samp ; struct phytbl_info tab ; struct brcms_phy_lcnphy *pi_lcn ; long ret ; int __x___0 ; long ret___0 ; int __x___2 ; { theta = 0; rot = 0; pi_lcn = pi->u.pi_lcnphy; pi->phy_tx_tone_freq = (u32 )f_kHz; wlc_lcnphy_deaf_mode(pi, 1); phy_bw = 40U; if ((int )pi_lcn->lcnphy_spurmod) { write_phy_reg(pi, 2370, 2); write_phy_reg(pi, 2363, 0); write_phy_reg(pi, 2364, 0); wlc_lcnphy_txrx_spur_avoidance_mode(pi, 0); } else { } if (f_kHz != 0) { k = 1U; ldv_37836: bw = (u32 )(((int )phy_bw * 1000) * (int )k); __x___0 = f_kHz; ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); num_samps = (u16 )((long )bw / ret); k = (u16 )((int )k + 1); __x___2 = f_kHz; ret___0 = (long )(__x___2 < 0 ? - __x___2 : __x___2); if ((unsigned int )num_samps * (unsigned int )ret___0 != bw) { goto ldv_37836; } else { } } else { num_samps = 2U; } rot = ((f_kHz * 36) / (int )phy_bw) / 100; theta = 0; t = 0U; goto ldv_37839; ldv_37838: tone_samp = cordic_calc_iq(theta); theta = theta + rot; i_samp = tone_samp.i * (int )max_val >= 0 ? (unsigned int )((unsigned short )(((tone_samp.i * (int )max_val >> 15) + 1) >> 1)) & 1023U : (unsigned int )(- ((int )((unsigned short )(((- (tone_samp.i * (int )max_val) >> 15) + 1) >> 1)))) & 1023U; q_samp = tone_samp.q * (int )max_val >= 0 ? (unsigned int )((unsigned short )(((tone_samp.q * (int )max_val >> 15) + 1) >> 1)) & 1023U : (unsigned int )(- ((int )((unsigned short )(((- (tone_samp.q * (int )max_val) >> 15) + 1) >> 1)))) & 1023U; data_buf[(int )t] = (u32 )(((int )i_samp << 10) | (int )q_samp); t = (u16 )((int )t + 1); ldv_37839: ; if ((int )t < (int )num_samps) { goto ldv_37838; } else { } mod_phy_reg(pi, 1750, 3, 0); mod_phy_reg(pi, 1754, 8, 8); tab.tbl_ptr = (void const *)(& data_buf); tab.tbl_len = (u32 )num_samps; tab.tbl_id = 21U; tab.tbl_offset = 0U; tab.tbl_width = 32U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); wlc_lcnphy_run_samples(pi, (int )num_samps, 65535, 0, (int )iqcalmode); return; } } void wlc_lcnphy_stop_tx_tone(struct brcms_phy *pi ) { s16 playback_status ; struct brcms_phy_lcnphy *pi_lcn ; u16 tmp ; { pi_lcn = pi->u.pi_lcnphy; pi->phy_tx_tone_freq = 0U; if ((int )pi_lcn->lcnphy_spurmod) { write_phy_reg(pi, 2370, 7); write_phy_reg(pi, 2363, 8215); write_phy_reg(pi, 2364, 10181); wlc_lcnphy_txrx_spur_avoidance_mode(pi, 1); } else { } tmp = read_phy_reg(pi, 1604); playback_status = (s16 )tmp; if ((int )playback_status & 1) { wlc_lcnphy_tx_pu(pi, 0); mod_phy_reg(pi, 1599, 2, 2); } else if (((int )playback_status & 2) != 0) { mod_phy_reg(pi, 1107, 32768, 0); } else { } mod_phy_reg(pi, 1750, 3, 1); mod_phy_reg(pi, 1754, 8, 0); mod_phy_reg(pi, 1754, 128, 0); and_radio_reg(pi, 274, 65529); wlc_lcnphy_deaf_mode(pi, 0); return; } } static void wlc_lcnphy_set_cc(struct brcms_phy *pi , int cal_type , s16 coeff_x , s16 coeff_y ) { u16 di0dq0 ; u16 x ; u16 y ; u16 data_rf ; int k ; { switch (cal_type) { case 0: wlc_lcnphy_set_tx_iqcc(pi, (int )((u16 )coeff_x), (int )((u16 )coeff_y)); goto ldv_37858; case 2: di0dq0 = (u16 )((int )((short )((int )coeff_x << 8)) | ((int )coeff_y & 255)); wlc_lcnphy_set_tx_locc(pi, (int )di0dq0); goto ldv_37858; case 3: k = wlc_lcnphy_calc_floor((int )coeff_x, 0); y = (unsigned int )((u16 )k) + 8U; k = wlc_lcnphy_calc_floor((int )coeff_x, 1); x = 8U - (unsigned int )((u16 )k); data_rf = (unsigned int )x * 16U + (unsigned int )y; write_radio_reg(pi, 137, (int )data_rf); k = wlc_lcnphy_calc_floor((int )coeff_y, 0); y = (unsigned int )((u16 )k) + 8U; k = wlc_lcnphy_calc_floor((int )coeff_y, 1); x = 8U - (unsigned int )((u16 )k); data_rf = (unsigned int )x * 16U + (unsigned int )y; write_radio_reg(pi, 138, (int )data_rf); goto ldv_37858; case 4: k = wlc_lcnphy_calc_floor((int )coeff_x, 0); y = (unsigned int )((u16 )k) + 8U; k = wlc_lcnphy_calc_floor((int )coeff_x, 1); x = 8U - (unsigned int )((u16 )k); data_rf = (unsigned int )x * 16U + (unsigned int )y; write_radio_reg(pi, 139, (int )data_rf); k = wlc_lcnphy_calc_floor((int )coeff_y, 0); y = (unsigned int )((u16 )k) + 8U; k = wlc_lcnphy_calc_floor((int )coeff_y, 1); x = 8U - (unsigned int )((u16 )k); data_rf = (unsigned int )x * 16U + (unsigned int )y; write_radio_reg(pi, 140, (int )data_rf); goto ldv_37858; } ldv_37858: ; return; } } static struct lcnphy_unsign16_struct wlc_lcnphy_get_cc(struct brcms_phy *pi , int cal_type ) { u16 a ; u16 b ; u16 didq ; u8 di0 ; u8 dq0 ; u8 ei ; u8 eq ; u8 fi ; u8 fq ; struct lcnphy_unsign16_struct cc ; { cc.re = 0U; cc.im = 0U; switch (cal_type) { case 0: wlc_lcnphy_get_tx_iqcc(pi, & a, & b); cc.re = a; cc.im = b; goto ldv_37877; case 2: didq = wlc_lcnphy_get_tx_locc(pi); di0 = (u8 )((((int )didq & 65280) << 16) >> 24); dq0 = (u8 )(((int )didq << 24) >> 24); cc.re = (unsigned short )di0; cc.im = (unsigned short )dq0; goto ldv_37877; case 3: wlc_lcnphy_get_radio_loft(pi, & ei, & eq, & fi, & fq); cc.re = (unsigned short )ei; cc.im = (unsigned short )eq; goto ldv_37877; case 4: wlc_lcnphy_get_radio_loft(pi, & ei, & eq, & fi, & fq); cc.re = (unsigned short )fi; cc.im = (unsigned short )fq; goto ldv_37877; } ldv_37877: ; return (cc); } } static void wlc_lcnphy_samp_cap(struct brcms_phy *pi , int clip_detect_algo , u16 thresh , s16 *ptr , int mode ) { u32 curval1 ; u32 curval2 ; u32 stpptr ; u32 curptr ; u32 strptr ; u32 val ; u16 sslpnCalibClkEnCtrl ; u16 timer ; u16 old_sslpnCalibClkEnCtrl ; s16 imag ; s16 real ; struct brcms_phy_lcnphy *pi_lcn ; { pi_lcn = pi->u.pi_lcnphy; timer = 0U; old_sslpnCalibClkEnCtrl = read_phy_reg(pi, 1754); curval1 = bcma_read16(pi->d11core, 1264); *(ptr + 130UL) = 0; bcma_write16(pi->d11core, 1264, curval1 | 64U); bcma_write16(pi->d11core, 1362, 32256U); bcma_write16(pi->d11core, 1364, 32768U); __const_udelay(85900UL); curval2 = bcma_read16(pi->d11core, 1170); bcma_write16(pi->d11core, 1170, curval2 | 48U); write_phy_reg(pi, 1365, 0); write_phy_reg(pi, 1446, 5); write_phy_reg(pi, 1442, (int )((unsigned short )((int )((short )mode) | (int )((short )(mode << 6))))); write_phy_reg(pi, 1487, 3); write_phy_reg(pi, 1445, 3); write_phy_reg(pi, 1411, 0); write_phy_reg(pi, 1412, 0); write_phy_reg(pi, 1413, 4095); write_phy_reg(pi, 1414, 0); write_phy_reg(pi, 1408, 17665); sslpnCalibClkEnCtrl = read_phy_reg(pi, 1754); write_phy_reg(pi, 1754, (int )((unsigned int )sslpnCalibClkEnCtrl | 8200U)); stpptr = bcma_read16(pi->d11core, 1364); curptr = bcma_read16(pi->d11core, 1366); ldv_37900: __const_udelay(42950UL); curptr = bcma_read16(pi->d11core, 1366); timer = (u16 )((int )timer + 1); if (curptr != stpptr && (unsigned int )timer <= 499U) { goto ldv_37900; } else { } bcma_write16(pi->d11core, 1170, 2U); strptr = 32256U; bcma_write32(pi->d11core, 304, strptr); goto ldv_37903; ldv_37902: val = bcma_read32(pi->d11core, 308); imag = (int )((s16 )(val >> 16)) & 1023; real = (int )((s16 )val) & 1023; if ((int )imag > 511) { imag = (s16 )((unsigned int )((unsigned short )imag) + 64512U); } else { } if ((int )real > 511) { real = (s16 )((unsigned int )((unsigned short )real) + 64512U); } else { } if ((int )pi_lcn->lcnphy_iqcal_swp_dis) { *(ptr + (unsigned long )((strptr - 32256U) / 4U)) = real; } else { *(ptr + (unsigned long )((strptr - 32256U) / 4U)) = imag; } if (clip_detect_algo != 0) { if ((int )imag > (int )thresh || (int )imag < - ((int )thresh)) { strptr = 32768U; *(ptr + 130UL) = 1; } else { } } else { } strptr = strptr + 4U; ldv_37903: ; if (strptr <= 32767U) { goto ldv_37902; } else { } write_phy_reg(pi, 1754, (int )old_sslpnCalibClkEnCtrl); bcma_write16(pi->d11core, 1170, curval2); bcma_write16(pi->d11core, 1264, curval1); return; } } static void wlc_lcnphy_a1(struct brcms_phy *pi , int cal_type , int num_levels , int step_size_lg2 ) { struct lcnphy_spb_tone const *phy_c1 ; struct lcnphy_spb_tone phy_c2 ; struct lcnphy_unsign16_struct phy_c3 ; int phy_c4 ; int phy_c5 ; int k ; int l ; int j ; int phy_c6 ; u16 phy_c7 ; u16 phy_c8 ; u16 phy_c9 ; s16 phy_c10 ; s16 phy_c11 ; s16 phy_c12 ; s16 phy_c13 ; s16 phy_c14 ; s16 phy_c15 ; s16 phy_c16 ; s16 *ptr ; s16 phy_c17 ; s32 phy_c18 ; s32 phy_c19 ; u32 phy_c20 ; u32 phy_c21 ; bool phy_c22 ; bool phy_c23 ; bool phy_c24 ; bool phy_c25 ; u16 phy_c26 ; u16 phy_c27 ; u16 phy_c28 ; u16 phy_c29 ; u16 phy_c30 ; u16 phy_c31 ; u16 *phy_c32 ; void *tmp ; void *tmp___0 ; { phy_c21 = 0U; phy_c8 = 0U; phy_c14 = 0; phy_c13 = phy_c14; phy_c10 = phy_c13; tmp = kmalloc(262UL, 32U); ptr = (s16 *)tmp; if ((unsigned long )ptr == (unsigned long )((s16 *)0)) { return; } else { } tmp___0 = kmalloc(40UL, 32U); phy_c32 = (u16 *)tmp___0; if ((unsigned long )phy_c32 == (unsigned long )((u16 *)0U)) { kfree((void const *)ptr); return; } else { } phy_c26 = read_phy_reg(pi, 1754); phy_c27 = read_phy_reg(pi, 1755); phy_c31 = read_radio_reg(pi, 38); write_phy_reg(pi, 2365, 192); wlc_lcnphy_start_tx_tone(pi, 3750, 88, 0); write_phy_reg(pi, 1754, 65535); or_phy_reg(pi, 1755, 3); wlc_lcnphy_tx_iqlo_loopback(pi, phy_c32); __const_udelay(2147500UL); phy_c28 = read_phy_reg(pi, 2360); phy_c29 = read_phy_reg(pi, 1239); phy_c30 = read_phy_reg(pi, 1240); or_phy_reg(pi, 2360, 4); or_phy_reg(pi, 1239, 4); or_phy_reg(pi, 1239, 8); mod_phy_reg(pi, 1239, 28672, 8192); or_phy_reg(pi, 1240, 1); or_phy_reg(pi, 1240, 2); mod_phy_reg(pi, 1240, 4092, 2280); mod_phy_reg(pi, 1240, 28672, 28672); phy_c1 = (struct lcnphy_spb_tone const *)(& lcnphy_spb_tone_3750); phy_c4 = 32; if (num_levels == 0) { if (cal_type != 0) { num_levels = 4; } else { num_levels = 9; } } else { } if (step_size_lg2 == 0) { if (cal_type != 0) { step_size_lg2 = 3; } else { step_size_lg2 = 8; } } else { } phy_c7 = (u16 )(1 << step_size_lg2); phy_c3 = wlc_lcnphy_get_cc(pi, cal_type); phy_c15 = (short )phy_c3.re; phy_c16 = (short )phy_c3.im; if (cal_type == 2) { if ((unsigned int )phy_c3.re > 127U) { phy_c15 = (s16 )((unsigned int )phy_c3.re + 65280U); } else { } if ((unsigned int )phy_c3.im > 127U) { phy_c16 = (s16 )((unsigned int )phy_c3.im + 65280U); } else { } } else { } wlc_lcnphy_set_cc(pi, cal_type, (int )phy_c15, (int )phy_c16); __const_udelay(85900UL); phy_c8 = 0U; goto ldv_37964; ldv_37963: phy_c23 = 1; phy_c22 = 0; switch (cal_type) { case 0: phy_c10 = 511; goto ldv_37948; case 2: phy_c10 = 127; goto ldv_37948; case 3: phy_c10 = 15; goto ldv_37948; case 4: phy_c10 = 15; goto ldv_37948; } ldv_37948: phy_c9 = read_phy_reg(pi, 2365); phy_c9 = (unsigned int )phy_c9 * 2U; phy_c24 = 0; phy_c5 = 7; phy_c25 = 1; ldv_37953: write_radio_reg(pi, 38, (int )((u16 )(((int )((short )phy_c5) & 7) | (int )((short )((phy_c5 & 7) << 4))))); __const_udelay(214750UL); phy_c22 = 0; *(ptr + 130UL) = 0; wlc_lcnphy_samp_cap(pi, 1, (int )phy_c9, ptr, 2); if ((int )*(ptr + 130UL) == 1) { phy_c22 = 1; } else { } if ((int )phy_c22) { phy_c5 = phy_c5 + -1; } else { } if ((int )phy_c22 != (int )phy_c24 && ! phy_c25) { goto ldv_37952; } else { } if (! phy_c22) { phy_c5 = phy_c5 + 1; } else { } if (phy_c5 <= 0 || phy_c5 > 6) { goto ldv_37952; } else { } phy_c24 = phy_c22; phy_c25 = 0; goto ldv_37953; ldv_37952: ; if (phy_c5 < 0) { phy_c5 = 0; } else if (phy_c5 > 7) { phy_c5 = 7; } else { } k = - ((int )phy_c7); goto ldv_37961; ldv_37960: l = - ((int )phy_c7); goto ldv_37958; ldv_37957: phy_c11 = (s16 )((int )((unsigned short )k) + (int )((unsigned short )phy_c15)); phy_c12 = (s16 )((int )((unsigned short )l) + (int )((unsigned short )phy_c16)); if ((int )phy_c11 < - ((int )phy_c10)) { phy_c11 = (s16 )(- ((int )((unsigned short )phy_c10))); } else if ((int )phy_c11 > (int )phy_c10) { phy_c11 = phy_c10; } else { } if ((int )phy_c12 < - ((int )phy_c10)) { phy_c12 = (s16 )(- ((int )((unsigned short )phy_c10))); } else if ((int )phy_c12 > (int )phy_c10) { phy_c12 = phy_c10; } else { } wlc_lcnphy_set_cc(pi, cal_type, (int )phy_c11, (int )phy_c12); __const_udelay(85900UL); wlc_lcnphy_samp_cap(pi, 0, 0, ptr, 2); phy_c18 = 0; phy_c19 = 0; j = 0; goto ldv_37955; ldv_37954: ; if (cal_type != 0) { phy_c6 = j % phy_c4; } else { phy_c6 = (j * 2) % phy_c4; } phy_c2.re = (phy_c1 + (unsigned long )phy_c6)->re; phy_c2.im = (phy_c1 + (unsigned long )phy_c6)->im; phy_c17 = *(ptr + (unsigned long )j); phy_c18 = (int )phy_c17 * (int )phy_c2.re + phy_c18; phy_c19 = (int )phy_c17 * (int )phy_c2.im + phy_c19; j = j + 1; ldv_37955: ; if (j <= 127) { goto ldv_37954; } else { } phy_c18 = phy_c18 >> 10; phy_c19 = phy_c19 >> 10; phy_c20 = (u32 )(phy_c18 * phy_c18 + phy_c19 * phy_c19); if ((int )phy_c23 || phy_c20 < phy_c21) { phy_c21 = phy_c20; phy_c13 = phy_c11; phy_c14 = phy_c12; } else { } phy_c23 = 0; l = (int )phy_c7 + l; ldv_37958: ; if ((int )phy_c7 >= l) { goto ldv_37957; } else { } k = (int )phy_c7 + k; ldv_37961: ; if ((int )phy_c7 >= k) { goto ldv_37960; } else { } phy_c23 = 1; phy_c15 = phy_c13; phy_c16 = phy_c14; phy_c7 = (u16 )((int )phy_c7 >> 1); wlc_lcnphy_set_cc(pi, cal_type, (int )phy_c15, (int )phy_c16); __const_udelay(85900UL); phy_c8 = (u16 )((int )phy_c8 + 1); ldv_37964: ; if ((unsigned int )phy_c7 != 0U && (int )phy_c8 < num_levels) { goto ldv_37963; } else { } goto cleanup; cleanup: wlc_lcnphy_tx_iqlo_loopback_cleanup(pi, phy_c32); wlc_lcnphy_stop_tx_tone(pi); write_phy_reg(pi, 1754, (int )phy_c26); write_phy_reg(pi, 1755, (int )phy_c27); write_phy_reg(pi, 2360, (int )phy_c28); write_phy_reg(pi, 1239, (int )phy_c29); write_phy_reg(pi, 1240, (int )phy_c30); write_radio_reg(pi, 38, (int )phy_c31); kfree((void const *)phy_c32); kfree((void const *)ptr); return; } } void wlc_lcnphy_get_tx_iqcc(struct brcms_phy *pi , u16 *a , u16 *b ) { u16 iqcc[2U] ; struct phytbl_info tab ; { tab.tbl_ptr = (void const *)(& iqcc); tab.tbl_len = 2U; tab.tbl_id = 0U; tab.tbl_offset = 80U; tab.tbl_width = 16U; wlc_lcnphy_read_table(pi, & tab); *a = iqcc[0]; *b = iqcc[1]; return; } } static void wlc_lcnphy_tx_iqlo_soft_cal_full(struct brcms_phy *pi ) { struct lcnphy_unsign16_struct iqcc0 ; struct lcnphy_unsign16_struct locc2 ; struct lcnphy_unsign16_struct locc3 ; struct lcnphy_unsign16_struct locc4 ; { wlc_lcnphy_set_cc(pi, 0, 0, 0); wlc_lcnphy_set_cc(pi, 2, 0, 0); wlc_lcnphy_set_cc(pi, 3, 0, 0); wlc_lcnphy_set_cc(pi, 4, 0, 0); wlc_lcnphy_a1(pi, 4, 0, 0); wlc_lcnphy_a1(pi, 3, 0, 0); wlc_lcnphy_a1(pi, 2, 3, 2); wlc_lcnphy_a1(pi, 0, 5, 8); wlc_lcnphy_a1(pi, 2, 2, 1); wlc_lcnphy_a1(pi, 0, 4, 3); iqcc0 = wlc_lcnphy_get_cc(pi, 0); locc2 = wlc_lcnphy_get_cc(pi, 2); locc3 = wlc_lcnphy_get_cc(pi, 3); locc4 = wlc_lcnphy_get_cc(pi, 4); return; } } u16 wlc_lcnphy_get_tx_locc(struct brcms_phy *pi ) { struct phytbl_info tab ; u16 didq ; { tab.tbl_id = 0U; tab.tbl_width = 16U; tab.tbl_ptr = (void const *)(& didq); tab.tbl_len = 1U; tab.tbl_offset = 85U; wlc_lcnphy_read_table(pi, & tab); return (didq); } } static void wlc_lcnphy_txpwrtbl_iqlo_cal(struct brcms_phy *pi ) { struct lcnphy_txgains target_gains ; struct lcnphy_txgains old_gains ; u8 save_bb_mult ; u16 a ; u16 b ; u16 didq ; u16 save_pa_gain ; uint idx ; uint SAVE_txpwrindex ; u32 val ; u16 SAVE_txpwrctrl ; u16 tmp ; struct phytbl_info tab ; u8 ei0 ; u8 eq0 ; u8 fi0 ; u8 fq0 ; struct brcms_phy_lcnphy *pi_lcn ; s8 tmp___0 ; long ret ; int __x___0 ; long ret___0 ; int __x___2 ; { save_pa_gain = 0U; SAVE_txpwrindex = 255U; tmp = read_phy_reg(pi, 1188); SAVE_txpwrctrl = (unsigned int )tmp & 57344U; pi_lcn = pi->u.pi_lcnphy; wlc_lcnphy_get_tx_gain(pi, & old_gains); save_pa_gain = wlc_lcnphy_get_pa_gain(pi); save_bb_mult = wlc_lcnphy_get_bbmult(pi); if ((unsigned int )SAVE_txpwrctrl == 0U) { tmp___0 = wlc_lcnphy_get_current_tx_pwr_idx(pi); SAVE_txpwrindex = (uint )tmp___0; } else { } wlc_lcnphy_set_tx_pwr_ctrl(pi, 0); target_gains.gm_gain = 7U; target_gains.pga_gain = 0U; target_gains.pad_gain = 21U; target_gains.dac_gain = 0U; wlc_lcnphy_set_tx_gain(pi, & target_gains); if (pi->pubpi.phy_rev == 1U || (int )pi_lcn->lcnphy_hw_iqcal_en) { wlc_lcnphy_set_tx_pwr_by_index(pi, 30); wlc_lcnphy_tx_iqlo_cal(pi, & target_gains, (enum lcnphy_cal_mode )pi_lcn->lcnphy_recal, 0); } else { wlc_lcnphy_set_tx_pwr_by_index(pi, 16); wlc_lcnphy_tx_iqlo_soft_cal_full(pi); } wlc_lcnphy_get_radio_loft(pi, & ei0, & eq0, & fi0, & fq0); __x___0 = (int )((signed char )fi0); ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); if (ret == 15L) { __x___2 = (int )((signed char )fq0); ret___0 = (long )(__x___2 < 0 ? - __x___2 : __x___2); if (ret___0 == 15L) { if (((int )pi->radio_chanspec & 61440) == 4096) { target_gains.gm_gain = 255U; target_gains.pga_gain = 255U; target_gains.pad_gain = 240U; target_gains.dac_gain = 0U; } else { target_gains.gm_gain = 7U; target_gains.pga_gain = 45U; target_gains.pad_gain = 186U; target_gains.dac_gain = 0U; } if (pi->pubpi.phy_rev == 1U || (int )pi_lcn->lcnphy_hw_iqcal_en) { target_gains.pga_gain = 0U; target_gains.pad_gain = 30U; wlc_lcnphy_set_tx_pwr_by_index(pi, 16); wlc_lcnphy_tx_iqlo_cal(pi, & target_gains, 0, 0); } else { wlc_lcnphy_tx_iqlo_soft_cal_full(pi); } } else { } } else { } wlc_lcnphy_get_tx_iqcc(pi, & a, & b); didq = wlc_lcnphy_get_tx_locc(pi); tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_ptr = (void const *)(& val); tab.tbl_len = 1U; tab.tbl_offset = 832U; idx = 0U; goto ldv_38015; ldv_38014: tab.tbl_offset = idx + 320U; wlc_lcnphy_read_table(pi, & tab); val = ((val & 4293918720U) | (((unsigned int )a & 1023U) << 10)) | ((u32 )b & 1023U); wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); val = (u32 )didq; tab.tbl_offset = idx + 448U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); idx = idx + 1U; ldv_38015: ; if (idx <= 127U) { goto ldv_38014; } else { } pi_lcn->lcnphy_cal_results.txiqlocal_a = a; pi_lcn->lcnphy_cal_results.txiqlocal_b = b; pi_lcn->lcnphy_cal_results.txiqlocal_didq = didq; pi_lcn->lcnphy_cal_results.txiqlocal_ei0 = ei0; pi_lcn->lcnphy_cal_results.txiqlocal_eq0 = eq0; pi_lcn->lcnphy_cal_results.txiqlocal_fi0 = fi0; pi_lcn->lcnphy_cal_results.txiqlocal_fq0 = fq0; wlc_lcnphy_set_bbmult(pi, (int )save_bb_mult); wlc_lcnphy_set_pa_gain(pi, (int )save_pa_gain); wlc_lcnphy_set_tx_gain(pi, & old_gains); if ((unsigned int )SAVE_txpwrctrl != 0U) { wlc_lcnphy_set_tx_pwr_ctrl(pi, (int )SAVE_txpwrctrl); } else { wlc_lcnphy_set_tx_pwr_by_index(pi, (int )SAVE_txpwrindex); } return; } } s16 wlc_lcnphy_tempsense_new(struct brcms_phy *pi , bool mode ) { u16 tempsenseval1 ; u16 tempsenseval2 ; s16 avg ; bool suspend ; u32 tmp ; u16 tmp___0 ; u16 tmp___1 ; { avg = 0; suspend = 0; if ((int )mode) { tmp = bcma_read32(pi->d11core, 288); suspend = (tmp & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_lcnphy_vbat_temp_sense_setup(pi, 1); } else { } tmp___0 = read_phy_reg(pi, 1142); tempsenseval1 = (unsigned int )tmp___0 & 511U; tmp___1 = read_phy_reg(pi, 1143); tempsenseval2 = (unsigned int )tmp___1 & 511U; if ((unsigned int )tempsenseval1 > 255U) { avg = (short )((unsigned int )tempsenseval1 - 512U); } else { avg = (short )tempsenseval1; } if ((unsigned int )tempsenseval2 > 255U) { avg = (s16 )((unsigned int )((int )tempsenseval2 + (int )((unsigned short )avg)) - 512U); } else { avg = (s16 )((int )((unsigned short )avg) + (int )tempsenseval2); } avg = (s16 )((int )avg / 2); if ((int )mode) { mod_phy_reg(pi, 1096, 16384, 16384); __const_udelay(429500UL); mod_phy_reg(pi, 1096, 16384, 0); if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } } else { } return (avg); } } u16 wlc_lcnphy_tempsense(struct brcms_phy *pi , bool mode ) { u16 tempsenseval1 ; u16 tempsenseval2 ; s32 avg ; bool suspend ; u16 SAVE_txpwrctrl ; u16 tmp ; struct brcms_phy_lcnphy *pi_lcn ; u32 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; { avg = 0; suspend = 0; tmp = read_phy_reg(pi, 1188); SAVE_txpwrctrl = (unsigned int )tmp & 57344U; pi_lcn = pi->u.pi_lcnphy; if ((int )mode) { tmp___0 = bcma_read32(pi->d11core, 288); suspend = (tmp___0 & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_lcnphy_vbat_temp_sense_setup(pi, 1); } else { } tmp___1 = read_phy_reg(pi, 1142); tempsenseval1 = (unsigned int )tmp___1 & 511U; tmp___2 = read_phy_reg(pi, 1143); tempsenseval2 = (unsigned int )tmp___2 & 511U; if ((unsigned int )tempsenseval1 > 255U) { avg = (int )tempsenseval1 + -512; } else { avg = (int )tempsenseval1; } if ((unsigned int )pi_lcn->lcnphy_tempsense_option == 1U || (int )pi->hwpwrctrl_capable) { if ((unsigned int )tempsenseval2 > 255U) { avg = (avg - (int )tempsenseval2) + 512; } else { avg = avg - (int )tempsenseval2; } } else { if ((unsigned int )tempsenseval2 > 255U) { avg = ((int )tempsenseval2 + avg) + -512; } else { avg = (int )tempsenseval2 + avg; } avg = avg / 2; } if (avg < 0) { avg = avg + 512; } else { } if ((unsigned int )pi_lcn->lcnphy_tempsense_option == 2U) { avg = (s32 )tempsenseval1; } else { } if ((int )mode) { wlc_lcnphy_set_tx_pwr_ctrl(pi, (int )SAVE_txpwrctrl); } else { } if ((int )mode) { mod_phy_reg(pi, 1096, 16384, 16384); __const_udelay(429500UL); mod_phy_reg(pi, 1096, 16384, 0); if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } } else { } return ((u16 )avg); } } s8 wlc_lcnphy_tempsense_degree(struct brcms_phy *pi , bool mode ) { s32 degree ; s16 tmp ; { tmp = wlc_lcnphy_tempsense_new(pi, (int )mode); degree = (s32 )tmp; degree = ((degree << 10) + 82135) / 2647; return ((s8 )degree); } } s8 wlc_lcnphy_vbatsense(struct brcms_phy *pi , bool mode ) { u16 vbatsenseval ; s32 avg ; bool suspend ; u32 tmp ; u16 tmp___0 ; { avg = 0; suspend = 0; if ((int )mode) { tmp = bcma_read32(pi->d11core, 288); suspend = (tmp & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_lcnphy_vbat_temp_sense_setup(pi, 2); } else { } tmp___0 = read_phy_reg(pi, 1141); vbatsenseval = (unsigned int )tmp___0 & 511U; if ((unsigned int )vbatsenseval > 255U) { avg = (int )vbatsenseval + -512; } else { avg = (int )vbatsenseval; } avg = (avg * 53 + 216) / 432; if ((int )mode) { if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } } else { } return ((s8 )avg); } } static void wlc_lcnphy_afe_clk_init(struct brcms_phy *pi , u8 mode ) { u8 phybw40 ; { phybw40 = ((int )pi->radio_chanspec & 3072) == 3072; mod_phy_reg(pi, 1745, 128, 128); if (((unsigned int )mode == 0U && (unsigned int )phybw40 == 0U) || (unsigned int )mode == 1U) { write_phy_reg(pi, 1744, 7); } else { } wlc_lcnphy_toggle_afe_pwdn(pi); return; } } static void wlc_lcnphy_temp_adj(struct brcms_phy *pi ) { { return; } } static void wlc_lcnphy_glacial_timer_based_cal(struct brcms_phy *pi ) { bool suspend ; s8 index ; u16 SAVE_pwrctrl ; u16 tmp ; struct brcms_phy_lcnphy *pi_lcn ; u32 tmp___0 ; { tmp = read_phy_reg(pi, 1188); SAVE_pwrctrl = (unsigned int )tmp & 57344U; pi_lcn = pi->u.pi_lcnphy; tmp___0 = bcma_read32(pi->d11core, 288); suspend = (tmp___0 & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_lcnphy_deaf_mode(pi, 1); pi->phy_lastcal = (pi->sh)->now; pi->phy_forcecal = 0; index = (s8 )pi_lcn->lcnphy_current_index; wlc_lcnphy_txpwrtbl_iqlo_cal(pi); wlc_lcnphy_set_tx_pwr_by_index(pi, (int )index); wlc_lcnphy_set_tx_pwr_ctrl(pi, (int )SAVE_pwrctrl); wlc_lcnphy_deaf_mode(pi, 0); if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } return; } } static void wlc_lcnphy_periodic_cal(struct brcms_phy *pi ) { bool suspend ; bool full_cal ; struct lcnphy_rx_iqcomp const *rx_iqcomp ; int rx_iqcomp_sz ; u16 SAVE_pwrctrl ; u16 tmp ; s8 index ; struct phytbl_info tab ; s32 a1 ; s32 b0 ; s32 b1 ; s32 tssi ; s32 pwr ; s32 maxtargetpwr ; s32 mintargetpwr ; struct brcms_phy_lcnphy *pi_lcn ; u32 tmp___0 ; { tmp = read_phy_reg(pi, 1188); SAVE_pwrctrl = (unsigned int )tmp & 57344U; pi_lcn = pi->u.pi_lcnphy; pi->phy_lastcal = (pi->sh)->now; pi->phy_forcecal = 0; full_cal = (int )pi_lcn->lcnphy_full_cal_channel != (int )((unsigned char )pi->radio_chanspec); pi_lcn->lcnphy_full_cal_channel = (unsigned char )pi->radio_chanspec; index = (s8 )pi_lcn->lcnphy_current_index; tmp___0 = bcma_read32(pi->d11core, 288); suspend = (tmp___0 & 1U) == 0U; if (! suspend) { wlapi_bmac_write_shm((pi->sh)->physhim, 184U, 10000); wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_lcnphy_deaf_mode(pi, 1); wlc_lcnphy_txpwrtbl_iqlo_cal(pi); rx_iqcomp = (struct lcnphy_rx_iqcomp const *)(& lcnphy_rx_iqcomp_table_rev0); rx_iqcomp_sz = 51; if (pi->pubpi.phy_rev == 1U) { wlc_lcnphy_rx_iq_cal(pi, (struct lcnphy_rx_iqcomp const *)0, 0, 1, 0, 1, 40); } else { wlc_lcnphy_rx_iq_cal(pi, (struct lcnphy_rx_iqcomp const *)0, 0, 1, 0, 1, 127); } if ((int )pi->hwpwrctrl_capable) { wlc_lcnphy_idle_tssi_est((struct brcms_phy_pub *)pi); b0 = (s32 )pi->txpa_2g[0]; b1 = (s32 )pi->txpa_2g[1]; a1 = (s32 )pi->txpa_2g[2]; maxtargetpwr = wlc_lcnphy_tssi2dbm(10, a1, b0, b1); mintargetpwr = wlc_lcnphy_tssi2dbm(125, a1, b0, b1); tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_ptr = (void const *)(& pwr); tab.tbl_len = 1U; tab.tbl_offset = 0U; tssi = 0; goto ldv_38083; ldv_38082: pwr = wlc_lcnphy_tssi2dbm(tssi, a1, b0, b1); pwr = mintargetpwr > pwr ? mintargetpwr : pwr; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); tab.tbl_offset = tab.tbl_offset + 1U; tssi = tssi + 1; ldv_38083: ; if (tssi <= 127) { goto ldv_38082; } else { } } else { } wlc_lcnphy_set_tx_pwr_by_index(pi, (int )index); wlc_lcnphy_set_tx_pwr_ctrl(pi, (int )SAVE_pwrctrl); wlc_lcnphy_deaf_mode(pi, 0); if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } return; } } void wlc_lcnphy_calib_modes(struct brcms_phy *pi , uint mode ) { u16 temp_new ; int temp1 ; int temp2 ; int temp_diff ; struct brcms_phy_lcnphy *pi_lcn ; { pi_lcn = pi->u.pi_lcnphy; switch (mode) { case 7U: ; goto ldv_38095; case 8U: wlc_lcnphy_periodic_cal(pi); goto ldv_38095; case 3U: wlc_lcnphy_periodic_cal(pi); goto ldv_38095; case 2U: ; if ((int )pi->temppwrctrl_capable) { temp_new = wlc_lcnphy_tempsense(pi, 0); temp1 = (unsigned int )temp_new > 255U ? (short )((unsigned int )temp_new - 512U) : (short )temp_new; temp2 = (unsigned int )pi_lcn->lcnphy_cal_temper > 255U ? (short )((unsigned int )pi_lcn->lcnphy_cal_temper - 512U) : (short )pi_lcn->lcnphy_cal_temper; temp_diff = temp1 - temp2; if (((unsigned int )pi_lcn->lcnphy_cal_counter > 90U || temp_diff > 60) || temp_diff < -60) { wlc_lcnphy_glacial_timer_based_cal(pi); wlc_2064_vco_cal(pi); pi_lcn->lcnphy_cal_temper = temp_new; pi_lcn->lcnphy_cal_counter = 0U; } else { pi_lcn->lcnphy_cal_counter = (u8 )((int )pi_lcn->lcnphy_cal_counter + 1); } } else { } goto ldv_38095; case 9U: ; if ((int )pi->temppwrctrl_capable) { wlc_lcnphy_tx_power_adjustment((struct brcms_phy_pub *)pi); } else { } goto ldv_38095; } ldv_38095: ; return; } } void wlc_lcnphy_get_tssi(struct brcms_phy *pi , s8 *ofdm_pwr , s8 *cck_pwr ) { s8 cck_offset ; u16 status ; u16 tmp ; bool tmp___0 ; { status = read_phy_reg(pi, 1195); if ((int )pi->hwpwrctrl_capable && (int )((short )status) < 0) { tmp = read_phy_reg(pi, 1195); *ofdm_pwr = (signed char )(((int )tmp & 511) >> 1); tmp___0 = wlc_phy_tpc_isenabled_lcnphy(pi); if ((int )tmp___0) { cck_offset = pi->tx_power_offset[0]; } else { cck_offset = 0; } *cck_pwr = (s8 )((int )((unsigned char )*ofdm_pwr) + (int )((unsigned char )cck_offset)); } else { *cck_pwr = 0; *ofdm_pwr = 0; } return; } } void wlc_phy_cal_init_lcnphy(struct brcms_phy *pi ) { { return; } } void wlc_lcnphy_tx_power_adjustment(struct brcms_phy_pub *ppi ) { s8 index ; u16 index2 ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; struct brcms_phy_lcnphy *pi_lcn ; u16 SAVE_txpwrctrl ; u16 tmp ; u16 tmp___0 ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; pi_lcn = pi->u.pi_lcnphy; tmp = read_phy_reg(pi, 1188); SAVE_txpwrctrl = (unsigned int )tmp & 57344U; if ((int )pi->temppwrctrl_capable && (unsigned int )SAVE_txpwrctrl != 0U) { index = wlc_lcnphy_tempcompensated_txpwrctrl(pi); index2 = (unsigned int )((unsigned short )index) * 2U; mod_phy_reg(pi, 1193, 511, (int )index2); tmp___0 = read_phy_reg(pi, 1193); pi_lcn->lcnphy_current_index = (u8 )(((int )tmp___0 & 255) / 2); } else { } return; } } static void wlc_lcnphy_load_tx_gain_table(struct brcms_phy *pi , struct lcnphy_tx_gain_tbl_entry const *gain_table ) { u32 j ; struct phytbl_info tab ; u32 val ; u16 pa_gain ; u16 gm_gain ; { if (((pi->sh)->boardflags & 2048U) != 0U) { pa_gain = 16U; } else { pa_gain = 96U; } tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_len = 1U; tab.tbl_ptr = (void const *)(& val); gm_gain = 15U; j = 0U; goto ldv_38130; ldv_38129: ; if (((pi->sh)->boardflags & 2048U) != 0U) { gm_gain = (u16 )(gain_table + (unsigned long )j)->gm; } else { } val = ((((unsigned int )pa_gain << 24) | (unsigned int )((int )(gain_table + (unsigned long )j)->pad << 16)) | (unsigned int )((int )(gain_table + (unsigned long )j)->pga << 8)) | (unsigned int )gm_gain; tab.tbl_offset = j + 192U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); val = (u32 )(((int )(gain_table + (unsigned long )j)->dac << 28) | ((int )(gain_table + (unsigned long )j)->bb_mult << 20)); tab.tbl_offset = j + 320U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); j = j + 1U; ldv_38130: ; if (j <= 127U) { goto ldv_38129; } else { } return; } } static void wlc_lcnphy_load_rfpower(struct brcms_phy *pi ) { struct phytbl_info tab ; u32 val ; u32 bbmult ; u32 rfgain ; u8 index ; u8 scale_factor ; s16 temp ; s16 temp1 ; s16 temp2 ; s16 qQ ; s16 qQ1 ; s16 qQ2 ; s16 shift ; { scale_factor = 1U; tab.tbl_id = 7U; tab.tbl_width = 32U; tab.tbl_len = 1U; index = 0U; goto ldv_38149; ldv_38148: tab.tbl_ptr = (void const *)(& bbmult); tab.tbl_offset = (u32 )((int )index + 320); wlc_lcnphy_read_table(pi, & tab); bbmult = bbmult >> 20; tab.tbl_ptr = (void const *)(& rfgain); tab.tbl_offset = (u32 )((int )index + 192); wlc_lcnphy_read_table(pi, & tab); qm_log10((int )bbmult, 0, & temp1, & qQ1); qm_log10(64, 0, & temp2, & qQ2); if ((int )qQ1 < (int )qQ2) { temp2 = qm_shr16((int )temp2, (int )qQ2 - (int )qQ1); qQ = qQ1; } else { temp1 = qm_shr16((int )temp1, (int )qQ1 - (int )qQ2); qQ = qQ2; } temp = qm_sub16((int )temp1, (int )temp2); if ((int )qQ > 3) { shift = (s16 )((unsigned int )((unsigned short )qQ) + 65532U); } else { shift = (s16 )(4U - (unsigned int )((unsigned short )qQ)); } val = (u32 )(((((int )index << (int )shift) + (int )temp * 5) + (1 << (((int )scale_factor + (int )shift) + -3))) >> (((int )scale_factor + (int )shift) + -2)); tab.tbl_ptr = (void const *)(& val); tab.tbl_offset = (u32 )((int )index + 576); wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); index = (u8 )((int )index + 1); ldv_38149: ; if ((int )((signed char )index) >= 0) { goto ldv_38148; } else { } return; } } static void wlc_lcnphy_bu_tweaks(struct brcms_phy *pi ) { { or_phy_reg(pi, 2053, 1); mod_phy_reg(pi, 1071, 7, 3); mod_phy_reg(pi, 48, 7, 3); write_phy_reg(pi, 1044, 7696); write_phy_reg(pi, 1045, 1600); mod_phy_reg(pi, 1247, 65280, 63232); or_phy_reg(pi, 1098, 68); write_phy_reg(pi, 1098, 128); mod_phy_reg(pi, 1076, 255, 253); mod_phy_reg(pi, 1056, 255, 16); if ((pi->sh)->boardrev > 4611U) { mod_radio_reg(pi, 155, 240, 240); } else { } write_phy_reg(pi, 2006, 2306); mod_phy_reg(pi, 1065, 15, 9); mod_phy_reg(pi, 1065, 1008, 224); if (pi->pubpi.phy_rev == 1U) { mod_phy_reg(pi, 1059, 255, 70); mod_phy_reg(pi, 1041, 255, 1); mod_phy_reg(pi, 1076, 255, 255); mod_phy_reg(pi, 1622, 15, 2); mod_phy_reg(pi, 1101, 4, 4); mod_radio_reg(pi, 247, 4, 4); mod_radio_reg(pi, 241, 3, 0); mod_radio_reg(pi, 242, 248, 144); mod_radio_reg(pi, 243, 3, 2); mod_radio_reg(pi, 243, 240, 160); mod_radio_reg(pi, 287, 2, 2); wlc_lcnphy_clear_tx_power_offsets(pi); mod_phy_reg(pi, 1232, 32704, 640); } else { } return; } } static void wlc_lcnphy_rcal(struct brcms_phy *pi ) { u8 rcal_value ; unsigned long __ms ; unsigned long tmp ; uint countdown ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; { and_radio_reg(pi, 91, 253); or_radio_reg(pi, 4, 64); or_radio_reg(pi, 288, 16); or_radio_reg(pi, 120, 128); or_radio_reg(pi, 297, 2); or_radio_reg(pi, 87, 1); or_radio_reg(pi, 91, 2); if (1) { __const_udelay(21475000UL); } else { __ms = 5UL; goto ldv_38160; ldv_38159: __const_udelay(4295000UL); ldv_38160: tmp = __ms; __ms = __ms - 1UL; if (tmp != 0UL) { goto ldv_38159; } else { } } countdown = 10000009U; goto ldv_38164; ldv_38163: __const_udelay(42950UL); countdown = countdown - 10U; ldv_38164: tmp___0 = read_radio_reg(pi, 92); if (((int )tmp___0 & 32) == 0 && countdown > 9U) { goto ldv_38163; } else { } tmp___2 = read_radio_reg(pi, 92); if (((int )tmp___2 & 32) != 0) { tmp___1 = read_radio_reg(pi, 92); rcal_value = (unsigned char )tmp___1; rcal_value = (unsigned int )rcal_value & 31U; } else { } and_radio_reg(pi, 91, 253); and_radio_reg(pi, 87, 254); return; } } static void wlc_lcnphy_rc_cal(struct brcms_phy *pi ) { u8 dflt_rc_cal_val ; u16 flt_val ; { dflt_rc_cal_val = 7U; if (pi->pubpi.phy_rev == 1U) { dflt_rc_cal_val = 11U; } else { } flt_val = (u16 )(((int )((short )((int )dflt_rc_cal_val << 10)) | (int )((short )((int )dflt_rc_cal_val << 5))) | (int )((short )dflt_rc_cal_val)); write_phy_reg(pi, 2355, (int )flt_val); write_phy_reg(pi, 2356, (int )flt_val); write_phy_reg(pi, 2357, (int )flt_val); write_phy_reg(pi, 2358, (int )flt_val); write_phy_reg(pi, 2359, (int )flt_val & 511); return; } } static void wlc_radio_2064_init(struct brcms_phy *pi ) { u32 i ; struct lcnphy_radio_regs const *lcnphyregs ; { lcnphyregs = (struct lcnphy_radio_regs const *)0; lcnphyregs = (struct lcnphy_radio_regs const *)(& lcnphy_radio_regs_2064); i = 0U; goto ldv_38177; ldv_38176: ; if (((int )pi->radio_chanspec & 61440) == 4096 && (unsigned int )((unsigned char )(lcnphyregs + (unsigned long )i)->do_init_a) != 0U) { write_radio_reg(pi, (int )(lcnphyregs + (unsigned long )i)->address & 16383, (int )(lcnphyregs + (unsigned long )i)->init_a); } else if ((unsigned int )((unsigned char )(lcnphyregs + (unsigned long )i)->do_init_g) != 0U) { write_radio_reg(pi, (int )(lcnphyregs + (unsigned long )i)->address & 16383, (int )(lcnphyregs + (unsigned long )i)->init_g); } else { } i = i + 1U; ldv_38177: ; if ((unsigned int )((unsigned short )(lcnphyregs + (unsigned long )i)->address) != 65535U) { goto ldv_38176; } else { } write_radio_reg(pi, 50, 98); write_radio_reg(pi, 51, 25); write_radio_reg(pi, 144, 16); write_radio_reg(pi, 16, 0); if (pi->pubpi.phy_rev == 1U) { write_radio_reg(pi, 96, 127); write_radio_reg(pi, 97, 114); write_radio_reg(pi, 98, 127); } else { } write_radio_reg(pi, 29, 2); write_radio_reg(pi, 30, 6); mod_phy_reg(pi, 1258, 7, 0); mod_phy_reg(pi, 1258, 56, 8); mod_phy_reg(pi, 1258, 448, 128); mod_phy_reg(pi, 1258, 3584, 1536); mod_phy_reg(pi, 1258, 28672, 16384); write_phy_reg(pi, 1258, 18056); if (((pi->sh)->boardflags & 2048U) != 0U) { mod_phy_reg(pi, 1259, 7, 2); } else { mod_phy_reg(pi, 1259, 7, 3); } mod_phy_reg(pi, 1259, 448, 0); mod_phy_reg(pi, 1130, 65535, 25); wlc_lcnphy_set_tx_locc(pi, 0); wlc_lcnphy_rcal(pi); wlc_lcnphy_rc_cal(pi); if (((pi->sh)->boardflags & 2048U) == 0U) { write_radio_reg(pi, 50, 111); write_radio_reg(pi, 51, 25); write_radio_reg(pi, 57, 14); } else { } return; } } static void wlc_lcnphy_radio_init(struct brcms_phy *pi ) { { wlc_radio_2064_init(pi); return; } } static void wlc_lcnphy_tbl_init(struct brcms_phy *pi ) { uint idx ; u8 phybw40 ; struct phytbl_info tab ; struct phytbl_info const *tb ; u32 val ; int l ; { phybw40 = ((int )pi->radio_chanspec & 3072) == 3072; idx = 0U; goto ldv_38191; ldv_38190: wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& dot11lcnphytbl_info_rev0) + (unsigned long )idx); idx = idx + 1U; ldv_38191: ; if (idx < (uint )dot11lcnphytbl_info_sz_rev0) { goto ldv_38190; } else { } if (((pi->sh)->boardflags & 4194304U) != 0U) { tab.tbl_id = 8U; tab.tbl_width = 16U; tab.tbl_ptr = (void const *)(& val); tab.tbl_len = 1U; val = 100U; tab.tbl_offset = 4U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); } else { } if (((pi->sh)->boardflags & 2048U) == 0U) { tab.tbl_id = 8U; tab.tbl_width = 16U; tab.tbl_ptr = (void const *)(& val); tab.tbl_len = 1U; val = 150U; tab.tbl_offset = 0U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); val = 220U; tab.tbl_offset = 1U; wlc_lcnphy_write_table(pi, (struct phytbl_info const *)(& tab)); } else { } if (((int )pi->radio_chanspec & 61440) == 8192) { if (((pi->sh)->boardflags & 2048U) != 0U) { wlc_lcnphy_load_tx_gain_table(pi, (struct lcnphy_tx_gain_tbl_entry const *)(& dot11lcnphy_2GHz_extPA_gaintable_rev0)); } else { wlc_lcnphy_load_tx_gain_table(pi, (struct lcnphy_tx_gain_tbl_entry const *)(& dot11lcnphy_2GHz_gaintable_rev0)); } } else { } if (pi->pubpi.phy_rev == 2U) { if (((int )pi->radio_chanspec & 61440) == 8192) { l = (int )dot11lcnphytbl_rx_gain_info_2G_rev2_sz; if (((pi->sh)->boardflags & 4096U) != 0U) { tb = (struct phytbl_info const *)(& dot11lcnphytbl_rx_gain_info_extlna_2G_rev2); } else { tb = (struct phytbl_info const *)(& dot11lcnphytbl_rx_gain_info_2G_rev2); } } else { l = (int )dot11lcnphytbl_rx_gain_info_5G_rev2_sz; if (((pi->sh)->boardflags & 268435456U) != 0U) { tb = (struct phytbl_info const *)(& dot11lcnphytbl_rx_gain_info_extlna_5G_rev2); } else { tb = (struct phytbl_info const *)(& dot11lcnphytbl_rx_gain_info_5G_rev2); } } idx = 0U; goto ldv_38195; ldv_38194: wlc_lcnphy_write_table(pi, tb + (unsigned long )idx); idx = idx + 1U; ldv_38195: ; if ((uint )l > idx) { goto ldv_38194; } else { } } else { } if (((pi->sh)->boardflags & 2048U) != 0U) { if (((pi->sh)->boardflags & 4194304U) != 0U) { if ((pi->sh)->boardrev <= 4687U) { tb = & dot11lcn_sw_ctrl_tbl_info_4313_bt_epa; } else { tb = & dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250; } } else { tb = & dot11lcn_sw_ctrl_tbl_info_4313_epa; } } else if (((pi->sh)->boardflags & 4194304U) != 0U) { tb = & dot11lcn_sw_ctrl_tbl_info_4313_bt_ipa; } else { tb = & dot11lcn_sw_ctrl_tbl_info_4313; } wlc_lcnphy_write_table(pi, tb); wlc_lcnphy_load_rfpower(pi); wlc_lcnphy_clear_papd_comptable(pi); return; } } static void wlc_lcnphy_rev0_baseband_init(struct brcms_phy *pi ) { struct brcms_phy_lcnphy *pi_lcn ; { pi_lcn = pi->u.pi_lcnphy; write_radio_reg(pi, 284, 0); write_phy_reg(pi, 1083, 0); write_phy_reg(pi, 1084, 0); write_phy_reg(pi, 1100, 0); write_phy_reg(pi, 1254, 0); write_phy_reg(pi, 1273, 0); write_phy_reg(pi, 1200, 0); write_phy_reg(pi, 2360, 0); write_phy_reg(pi, 1200, 0); write_phy_reg(pi, 1102, 0); or_phy_reg(pi, 1383, 3); or_phy_reg(pi, 1098, 68); write_phy_reg(pi, 1098, 128); if (((pi->sh)->boardflags & 2048U) == 0U) { wlc_lcnphy_set_tx_pwr_by_index(pi, 52); } else { } mod_phy_reg(pi, 1588, 255, 12); if (((pi->sh)->boardflags & 2048U) != 0U) { mod_phy_reg(pi, 1588, 255, 10); write_phy_reg(pi, 2320, 1); } else { } mod_phy_reg(pi, 1096, 768, 256); mod_phy_reg(pi, 1544, 255, 23); mod_phy_reg(pi, 1540, 2047, 1002); return; } } static void wlc_lcnphy_rev2_baseband_init(struct brcms_phy *pi ) { { if (((int )pi->radio_chanspec & 61440) == 4096) { mod_phy_reg(pi, 1046, 255, 80); mod_phy_reg(pi, 1046, 65280, 20480); } else { } return; } } static void wlc_lcnphy_agc_temp_init(struct brcms_phy *pi ) { s16 temp ; struct phytbl_info tab ; u32 tableBuffer[2U] ; struct brcms_phy_lcnphy *pi_lcn ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; { pi_lcn = pi->u.pi_lcnphy; tmp = read_phy_reg(pi, 1247); temp = (short )tmp; pi_lcn->lcnphy_ofdmgainidxtableoffset = (int )temp & 255; if ((int )pi_lcn->lcnphy_ofdmgainidxtableoffset > 127) { pi_lcn->lcnphy_ofdmgainidxtableoffset = (s16 )((unsigned int )((unsigned short )pi_lcn->lcnphy_ofdmgainidxtableoffset) + 65280U); } else { } pi_lcn->lcnphy_dsssgainidxtableoffset = (s16 )(((int )temp & 65280) >> 8); if ((int )pi_lcn->lcnphy_dsssgainidxtableoffset > 127) { pi_lcn->lcnphy_dsssgainidxtableoffset = (s16 )((unsigned int )((unsigned short )pi_lcn->lcnphy_dsssgainidxtableoffset) + 65280U); } else { } tab.tbl_ptr = (void const *)(& tableBuffer); tab.tbl_len = 2U; tab.tbl_id = 17U; tab.tbl_offset = 59U; tab.tbl_width = 32U; wlc_lcnphy_read_table(pi, & tab); if (tableBuffer[0] > 63U) { tableBuffer[0] = tableBuffer[0] - 128U; } else { } pi_lcn->lcnphy_tr_R_gain_val = tableBuffer[0]; if (tableBuffer[1] > 63U) { tableBuffer[1] = tableBuffer[1] - 128U; } else { } pi_lcn->lcnphy_tr_T_gain_val = tableBuffer[1]; tmp___0 = read_phy_reg(pi, 1076); temp = (int )((short )tmp___0) & 255; if ((int )temp > 127) { temp = (s16 )((unsigned int )((unsigned short )temp) + 65280U); } else { } pi_lcn->lcnphy_input_pwr_offset_db = (signed char )temp; tmp___1 = read_phy_reg(pi, 1060); pi_lcn->lcnphy_Med_Low_Gain_db = (int )tmp___1 >> 8; tmp___2 = read_phy_reg(pi, 1061); pi_lcn->lcnphy_Very_Low_Gain_db = (unsigned int )tmp___2 & 255U; tab.tbl_ptr = (void const *)(& tableBuffer); tab.tbl_len = 2U; tab.tbl_id = 13U; tab.tbl_offset = 28U; tab.tbl_width = 32U; wlc_lcnphy_read_table(pi, & tab); pi_lcn->lcnphy_gain_idx_14_lowword = tableBuffer[0]; pi_lcn->lcnphy_gain_idx_14_hiword = tableBuffer[1]; return; } } static void wlc_lcnphy_baseband_init(struct brcms_phy *pi ) { { wlc_lcnphy_tbl_init(pi); wlc_lcnphy_rev0_baseband_init(pi); if (pi->pubpi.phy_rev == 2U) { wlc_lcnphy_rev2_baseband_init(pi); } else { } wlc_lcnphy_bu_tweaks(pi); return; } } void wlc_phy_init_lcnphy(struct brcms_phy *pi ) { u8 phybw40 ; struct brcms_phy_lcnphy *pi_lcn ; { pi_lcn = pi->u.pi_lcnphy; phybw40 = ((int )pi->radio_chanspec & 3072) == 3072; pi_lcn->lcnphy_cal_counter = 0U; pi_lcn->lcnphy_cal_temper = pi_lcn->lcnphy_rawtempsense; or_phy_reg(pi, 1098, 128); and_phy_reg(pi, 1098, 127); wlc_lcnphy_afe_clk_init(pi, 1); write_phy_reg(pi, 1546, 160); write_phy_reg(pi, 1130, 25); wlc_lcnphy_baseband_init(pi); wlc_lcnphy_radio_init(pi); if (((int )pi->radio_chanspec & 61440) == 8192) { wlc_lcnphy_tx_pwr_ctrl_init((struct brcms_phy_pub *)pi); } else { } wlc_phy_chanspec_set((struct brcms_phy_pub *)pi, (int )pi->radio_chanspec); bcma_chipco_regctl_maskset(& ((pi->d11core)->bus)->drv_cc, 0U, 4294967280U, 9U); bcma_chipco_chipctl_maskset(& ((pi->d11core)->bus)->drv_cc, 0U, 0U, 63823325U); if (((pi->sh)->boardflags & 2048U) != 0U && (int )pi->temppwrctrl_capable) { wlc_lcnphy_set_tx_pwr_by_index(pi, 78); } else { } wlc_lcnphy_agc_temp_init(pi); wlc_lcnphy_temp_adj(pi); mod_phy_reg(pi, 1096, 16384, 16384); __const_udelay(429500UL); mod_phy_reg(pi, 1096, 16384, 0); wlc_lcnphy_set_tx_pwr_ctrl(pi, 57344); pi_lcn->lcnphy_noise_samples = 5000U; wlc_lcnphy_calib_modes(pi, 3U); return; } } static bool wlc_phy_txpwr_srom_read_lcnphy(struct brcms_phy *pi ) { s8 txpwr ; int i ; struct brcms_phy_lcnphy *pi_lcn ; struct ssb_sprom *sprom ; u16 cckpo ; u32 offset_ofdm ; u32 offset_mcs ; uint max_pwr_chan ; u8 opo ; { txpwr = 0; pi_lcn = pi->u.pi_lcnphy; sprom = & ((pi->d11core)->bus)->sprom; if (((int )pi->radio_chanspec & 61440) == 8192) { cckpo = 0U; pi_lcn->lcnphy_tr_isolation_mid = sprom->fem.ghz2.tr_iso; pi_lcn->lcnphy_rx_power_offset = (u8 )sprom->rxpo2g; pi->txpa_2g[0] = (s16 )sprom->pa0b0; pi->txpa_2g[1] = (s16 )sprom->pa0b1; pi->txpa_2g[2] = (s16 )sprom->pa0b2; pi_lcn->lcnphy_rssi_vf = sprom->rssismf2g; pi_lcn->lcnphy_rssi_vc = sprom->rssismc2g; pi_lcn->lcnphy_rssi_gs = sprom->rssisav2g; pi_lcn->lcnphy_rssi_vf_lowtemp = pi_lcn->lcnphy_rssi_vf; pi_lcn->lcnphy_rssi_vc_lowtemp = pi_lcn->lcnphy_rssi_vc; pi_lcn->lcnphy_rssi_gs_lowtemp = pi_lcn->lcnphy_rssi_gs; pi_lcn->lcnphy_rssi_vf_hightemp = pi_lcn->lcnphy_rssi_vf; pi_lcn->lcnphy_rssi_vc_hightemp = pi_lcn->lcnphy_rssi_vc; pi_lcn->lcnphy_rssi_gs_hightemp = pi_lcn->lcnphy_rssi_gs; txpwr = (s8 )sprom->core_pwr_info[0].maxpwr_2g; pi->tx_srom_max_2g = (u8 )txpwr; i = 0; goto ldv_38231; ldv_38230: pi->txpa_2g_low_temp[i] = pi->txpa_2g[i]; pi->txpa_2g_high_temp[i] = pi->txpa_2g[i]; i = i + 1; ldv_38231: ; if (i <= 2) { goto ldv_38230; } else { } cckpo = sprom->cck2gpo; offset_ofdm = sprom->ofdm2gpo; if ((unsigned int )cckpo != 0U) { max_pwr_chan = (uint )txpwr; i = 0; goto ldv_38235; ldv_38234: pi->tx_srom_max_rate_2g[i] = ((unsigned int )((u8 )cckpo) & 15U) * 254U + (unsigned int )((u8 )max_pwr_chan); cckpo = (u16 )((int )cckpo >> 4); i = i + 1; ldv_38235: ; if (i <= 3) { goto ldv_38234; } else { } i = 4; goto ldv_38238; ldv_38237: pi->tx_srom_max_rate_2g[i] = (unsigned int )((u8 )max_pwr_chan) - ((unsigned int )((u8 )offset_ofdm) & 15U) * 2U; offset_ofdm = offset_ofdm >> 4; i = i + 1; ldv_38238: ; if (i <= 11) { goto ldv_38237; } else { } } else { opo = 0U; opo = sprom->opo; i = 0; goto ldv_38242; ldv_38241: pi->tx_srom_max_rate_2g[i] = (u8 )txpwr; i = i + 1; ldv_38242: ; if (i <= 3) { goto ldv_38241; } else { } i = 4; goto ldv_38245; ldv_38244: pi->tx_srom_max_rate_2g[i] = (unsigned int )((u8 )txpwr) - ((unsigned int )((u8 )offset_ofdm) & 15U) * 2U; offset_ofdm = offset_ofdm >> 4; i = i + 1; ldv_38245: ; if (i <= 11) { goto ldv_38244; } else { } offset_mcs = (u32 )((int )sprom->mcs2gpo[1] << 16); offset_mcs = (u32 )sprom->mcs2gpo[0] | offset_mcs; pi_lcn->lcnphy_mcs20_po = offset_mcs; i = 20; goto ldv_38248; ldv_38247: pi->tx_srom_max_rate_2g[i] = (unsigned int )((u8 )txpwr) - ((unsigned int )((u8 )offset_mcs) & 15U) * 2U; offset_mcs = offset_mcs >> 4; i = i + 1; ldv_38248: ; if (i <= 27) { goto ldv_38247; } else { } } pi_lcn->lcnphy_rawtempsense = sprom->rawtempsense; pi_lcn->lcnphy_measPower = sprom->measpower; pi_lcn->lcnphy_tempsense_slope = sprom->tempsense_slope; pi_lcn->lcnphy_hw_iqcal_en = (unsigned int )sprom->hw_iqcal_en != 0U; pi_lcn->lcnphy_iqcal_swp_dis = (unsigned int )sprom->iqcal_swp_dis != 0U; pi_lcn->lcnphy_tempcorrx = sprom->tempcorrx; pi_lcn->lcnphy_tempsense_option = sprom->tempsense_option; pi_lcn->lcnphy_freqoffset_corr = sprom->freqoffset_corr; if ((unsigned int )sprom->ant_available_bg > 1U) { wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *)pi, (int )sprom->ant_available_bg); } else { } } else { } pi_lcn->lcnphy_cck_dig_filt_type = -1; return (1); } } void wlc_2064_vco_cal(struct brcms_phy *pi ) { u8 calnrst ; u16 tmp ; { mod_radio_reg(pi, 87, 8, 8); tmp = read_radio_reg(pi, 86); calnrst = (unsigned int )((u8 )tmp) & 248U; write_radio_reg(pi, 86, (int )calnrst); __const_udelay(4295UL); write_radio_reg(pi, 86, (int )((unsigned int )calnrst | 3U)); __const_udelay(4295UL); write_radio_reg(pi, 86, (int )((unsigned int )calnrst | 7U)); __const_udelay(1288500UL); mod_radio_reg(pi, 87, 8, 0); return; } } bool wlc_phy_tpc_isenabled_lcnphy(struct brcms_phy *pi ) { u16 tmp ; { if ((int )pi->temppwrctrl_capable) { return (0); } else { tmp = read_phy_reg(pi, 1188); return (((int )tmp & 57344) == 57344); } } } void wlc_phy_txpower_recalc_target_lcnphy(struct brcms_phy *pi ) { u16 pwr_ctrl ; u16 tmp ; { if ((int )pi->temppwrctrl_capable) { wlc_lcnphy_calib_modes(pi, 9U); } else if ((int )pi->hwpwrctrl_capable) { tmp = read_phy_reg(pi, 1188); pwr_ctrl = (unsigned int )tmp & 57344U; wlc_lcnphy_set_tx_pwr_ctrl(pi, 0); wlc_lcnphy_txpower_recalc_target(pi); wlc_lcnphy_set_tx_pwr_ctrl(pi, (int )pwr_ctrl); } else { } return; } } void wlc_phy_chanspec_set_lcnphy(struct brcms_phy *pi , u16 chanspec ) { u8 channel ; { channel = (unsigned char )chanspec; wlc_phy_chanspec_radio_set((struct brcms_phy_pub *)pi, (int )chanspec); wlc_lcnphy_set_chanspec_tweaks(pi, (int )pi->radio_chanspec); or_phy_reg(pi, 1098, 68); write_phy_reg(pi, 1098, 128); wlc_lcnphy_radio_2064_channel_tune_4313(pi, (int )channel); __const_udelay(4295000UL); wlc_lcnphy_toggle_afe_pwdn(pi); write_phy_reg(pi, 1623, (int )lcnphy_sfo_cfg[(int )channel + -1].ptcentreTs20); write_phy_reg(pi, 1624, (int )lcnphy_sfo_cfg[(int )channel + -1].ptcentreFactor); if ((unsigned int )((unsigned char )pi->radio_chanspec) == 14U) { mod_phy_reg(pi, 1096, 768, 512); wlc_lcnphy_load_tx_iir_filter(pi, 0, 3); } else { mod_phy_reg(pi, 1096, 768, 256); wlc_lcnphy_load_tx_iir_filter(pi, 0, 2); } if (((pi->sh)->boardflags & 2048U) != 0U) { wlc_lcnphy_load_tx_iir_filter(pi, 1, 0); } else { wlc_lcnphy_load_tx_iir_filter(pi, 1, 3); } mod_phy_reg(pi, 1259, 56, 8); if ((int )pi->hwpwrctrl_capable) { wlc_lcnphy_tssi_setup(pi); } else { } return; } } void wlc_phy_detach_lcnphy(struct brcms_phy *pi ) { { kfree((void const *)pi->u.pi_lcnphy); return; } } bool wlc_phy_attach_lcnphy(struct brcms_phy *pi ) { struct brcms_phy_lcnphy *pi_lcn ; void *tmp ; bool tmp___0 ; int tmp___1 ; { tmp = kzalloc(680UL, 32U); pi->u.pi_lcnphy = (struct brcms_phy_lcnphy *)tmp; if ((unsigned long )pi->u.pi_lcnphy == (unsigned long )((struct brcms_phy_lcnphy *)0)) { return (0); } else { } pi_lcn = pi->u.pi_lcnphy; if (((pi->sh)->boardflags & 65536U) == 0U) { pi->hwpwrctrl = 1; pi->hwpwrctrl_capable = 1; } else { } pi->xtalfreq = bcma_chipco_get_alp_clock(& ((pi->d11core)->bus)->drv_cc); pi_lcn->lcnphy_papd_rxGnCtrl_init = 0U; pi->pi_fptr.init = & wlc_phy_init_lcnphy; pi->pi_fptr.calinit = & wlc_phy_cal_init_lcnphy; pi->pi_fptr.chanset = & wlc_phy_chanspec_set_lcnphy; pi->pi_fptr.txpwrrecalc = & wlc_phy_txpower_recalc_target_lcnphy; pi->pi_fptr.txiqccget = & wlc_lcnphy_get_tx_iqcc; pi->pi_fptr.txiqccset = & wlc_lcnphy_set_tx_iqcc; pi->pi_fptr.txloccget = & wlc_lcnphy_get_tx_locc; pi->pi_fptr.radioloftget = & wlc_lcnphy_get_radio_loft; pi->pi_fptr.detach = & wlc_phy_detach_lcnphy; tmp___0 = wlc_phy_txpwr_srom_read_lcnphy(pi); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return (0); } else { } if (pi->pubpi.phy_rev == 1U) { if ((unsigned int )pi_lcn->lcnphy_tempsense_option == 3U) { pi->hwpwrctrl = 1; pi->hwpwrctrl_capable = 1; pi->temppwrctrl_capable = 0; } else { pi->hwpwrctrl = 0; pi->hwpwrctrl_capable = 0; pi->temppwrctrl_capable = 1; } } else { } return (1); } } static void wlc_lcnphy_set_rx_gain(struct brcms_phy *pi , u32 gain ) { u16 trsw ; u16 ext_lna ; u16 lna1 ; u16 lna2 ; u16 tia ; u16 biq0 ; u16 biq1 ; u16 gain0_15 ; u16 gain16_19 ; { trsw = (gain & 268435456U) == 0U; ext_lna = (unsigned int )((u16 )(gain >> 29)) & 1U; lna1 = (unsigned int )((u16 )gain) & 15U; lna2 = (unsigned int )((u16 )(gain >> 4)) & 15U; tia = (unsigned int )((u16 )(gain >> 8)) & 15U; biq0 = (unsigned int )((u16 )(gain >> 12)) & 15U; biq1 = (unsigned int )((u16 )(gain >> 16)) & 15U; gain0_15 = (unsigned short )(((((((int )((short )lna1) & 3) | (int )((short )(((int )lna1 & 3) << 2))) | (int )((short )(((int )lna2 & 3) << 4))) | ((int )((short )((int )lna2 << 6)) & 255)) | (int )((short )(((int )tia & 15) << 8))) | (int )((short )((int )biq0 << 12))); gain16_19 = biq1; mod_phy_reg(pi, 1101, 1, (int )trsw); mod_phy_reg(pi, 1201, 512, (int )ext_lna << 9U); mod_phy_reg(pi, 1201, 1024, (int )ext_lna << 10U); mod_phy_reg(pi, 1206, 65535, (int )gain0_15); mod_phy_reg(pi, 1207, 15, (int )gain16_19); if (((int )pi->radio_chanspec & 61440) == 8192) { mod_phy_reg(pi, 1201, 6144, (int )lna1 << 11U); mod_phy_reg(pi, 1254, 24, (int )lna1 << 3U); } else { } wlc_lcnphy_rx_gain_override_enable(pi, 1); return; } } static u32 wlc_lcnphy_get_receive_power(struct brcms_phy *pi , s32 *gain_index ) { u32 received_power ; s32 max_index ; u32 gain_code ; struct brcms_phy_lcnphy *pi_lcn ; { received_power = 0U; max_index = 0; gain_code = 0U; pi_lcn = pi->u.pi_lcnphy; max_index = 36; if (*gain_index >= 0) { gain_code = lcnphy_23bitgaincode_table[*gain_index]; } else { } if (*gain_index == -1) { *gain_index = 0; goto ldv_38295; ldv_38294: wlc_lcnphy_set_rx_gain(pi, lcnphy_23bitgaincode_table[*gain_index]); received_power = wlc_lcnphy_measure_digital_power(pi, (int )pi_lcn->lcnphy_noise_samples); *gain_index = *gain_index + 1; ldv_38295: ; if (*gain_index <= max_index && received_power <= 699U) { goto ldv_38294; } else { } *gain_index = *gain_index - 1; } else { wlc_lcnphy_set_rx_gain(pi, gain_code); received_power = wlc_lcnphy_measure_digital_power(pi, (int )pi_lcn->lcnphy_noise_samples); } return (received_power); } } s32 wlc_lcnphy_rx_signal_power(struct brcms_phy *pi , s32 gain_index ) { s32 gain ; s32 nominal_power_db ; s32 log_val ; s32 gain_mismatch ; s32 desired_gain ; s32 input_power_offset_db ; s32 input_power_db ; s32 received_power ; s32 temperature ; u32 power ; u32 msb1 ; u32 msb2 ; u32 val1 ; u32 val2 ; u32 diff1 ; u32 diff2 ; uint freq ; struct brcms_phy_lcnphy *pi_lcn ; u32 tmp ; u16 tmp___0 ; int tmp___1 ; u16 tmp___2 ; int tmp___3 ; { gain = 0; pi_lcn = pi->u.pi_lcnphy; tmp = wlc_lcnphy_get_receive_power(pi, & gain_index); received_power = (s32 )tmp; gain = (s32 )lcnphy_gain_table[gain_index]; tmp___0 = read_phy_reg(pi, 1061); nominal_power_db = (int )tmp___0 >> 8; power = (u32 )(received_power * 16); tmp___1 = ffs((int )power); msb1 = (u32 )(tmp___1 + -1); msb2 = msb1 + 1U; val1 = (u32 )(1 << (int )msb1); val2 = (u32 )(1 << (int )msb2); diff1 = power - val1; diff2 = val2 - power; if (diff1 < diff2) { log_val = (s32 )msb1; } else { log_val = (s32 )msb2; } log_val = log_val * 3; gain_mismatch = nominal_power_db / 2 - log_val; desired_gain = gain + gain_mismatch; tmp___2 = read_phy_reg(pi, 1076); input_power_offset_db = (int )tmp___2 & 255; if (input_power_offset_db > 127) { input_power_offset_db = input_power_offset_db + -256; } else { } input_power_db = input_power_offset_db - desired_gain; input_power_db = (int )lcnphy_gain_index_offset_for_rssi[gain_index] + input_power_db; tmp___3 = wlc_phy_channel2freq((uint )((unsigned char )pi->radio_chanspec)); freq = (uint )tmp___3; if (freq > 2427U && freq <= 2467U) { input_power_db = input_power_db + -1; } else { } temperature = (s32 )pi_lcn->lcnphy_lastsensed_temperature; if (temperature + -15 < -30) { input_power_db = (((temperature * 286 + -10010) >> 12) + input_power_db) + -7; } else if (temperature + -15 <= 3) { input_power_db = (((temperature * 286 + -10010) >> 12) + input_power_db) + -3; } else { input_power_db = ((temperature * 286 + -10010) >> 12) + input_power_db; } wlc_lcnphy_rx_gain_override_enable(pi, 0); return (input_power_db); } } bool ldv_queue_work_on_185(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_186(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_187(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_188(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_189(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; extern void __dynamic_pr_debug(struct _ddebug * , char const * , ...) ; bool ldv_queue_work_on_199(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_201(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_200(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_203(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_202(struct workqueue_struct *ldv_func_arg1 ) ; extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc * , int ) ; void wlc_phy_init_nphy(struct brcms_phy *pi ) ; void wlc_phy_cal_init_nphy(struct brcms_phy *pi ) ; void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi , u16 chanspec ) ; void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi ) ; void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi , bool enable ) ; void wlc_phy_table_read_nphy(struct brcms_phy *pi , u32 id , u32 len , u32 offset , u32 width , void *data ) ; void wlc_phy_table_write_nphy(struct brcms_phy *pi , u32 id , u32 len , u32 offset , u32 width , void const *data ) ; void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi ) ; void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi , u8 cmd ) ; void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi , u8 write , struct nphy_iq_comp *pcomp ) ; u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih ) ; void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi ) ; u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi ) ; struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi ) ; int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi , struct nphy_txgains target_gain , bool fullcal , bool mphase ) ; int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi , struct nphy_txgains target_gain , u8 cal_type , bool debug ) ; void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi , u8 core_mask , s8 txpwrindex , bool restore_cals ) ; void wlc_phy_rssisel_nphy(struct brcms_phy *pi , u8 core_code , u8 rssi_type ) ; int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi , u8 rssi_type , s32 *rssi_buf , u8 nsamps ) ; void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi ) ; void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi , s32 dBm_targetpower , bool debug ) ; int wlc_phy_tx_tone_nphy(struct brcms_phy *pi , u32 f_kHz , u16 max_val , u8 iqmode , u8 dac_test_mode , bool modify_bbmult ) ; void wlc_phy_stopplayback_nphy(struct brcms_phy *pi ) ; void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi , s32 *qdBm_pwrbuf , u8 num_samps ) ; void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi ) ; void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi , u8 rifs ) ; bool wlc_phy_bist_check_phy(struct brcms_phy_pub *pih ) ; struct phytbl_info const mimophytbl_info_rev0[14U] ; struct phytbl_info const mimophytbl_info_rev0_volatile[12U] ; unsigned int const mimophytbl_info_sz_rev0 ; unsigned int const mimophytbl_info_sz_rev0_volatile ; struct phytbl_info const mimophytbl_info_rev3[24U] ; struct phytbl_info const mimophytbl_info_rev3_volatile[1U] ; struct phytbl_info const mimophytbl_info_rev3_volatile1[1U] ; struct phytbl_info const mimophytbl_info_rev3_volatile2[1U] ; struct phytbl_info const mimophytbl_info_rev3_volatile3[1U] ; unsigned int const mimophytbl_info_sz_rev3 ; unsigned int const mimophytbl_info_sz_rev3_volatile ; u32 const noise_var_tbl_rev3[256U] ; struct phytbl_info const mimophytbl_info_rev7[30U] ; unsigned int const mimophytbl_info_sz_rev7 ; u32 const noise_var_tbl_rev7[256U] ; struct phytbl_info const mimophytbl_info_rev16[11U] ; unsigned int const mimophytbl_info_sz_rev16 ; static struct nphy_ipa_txrxgain const nphy_ipa_rxcal_gaintbl_5GHz[6U] = { {0U, 0U, 0U, 0U, 0U, 100}, {0U, 0U, 0U, 0U, 0U, 50}, {0U, 0U, 0U, 0U, 0U, -1}, {0U, 0U, 0U, 3U, 0U, -1}, {0U, 0U, 3U, 3U, 0U, -1}, {0U, 2U, 3U, 3U, 0U, -1}}; static struct nphy_ipa_txrxgain const nphy_ipa_rxcal_gaintbl_2GHz[6U] = { {0U, 0U, 0U, 0U, 0U, -128}, {0U, 0U, 0U, 0U, 0U, 70}, {0U, 0U, 0U, 0U, 0U, 20}, {0U, 0U, 0U, 3U, 0U, 20}, {0U, 0U, 3U, 3U, 0U, 20}, {0U, 2U, 3U, 3U, 0U, 20}}; static struct nphy_ipa_txrxgain const nphy_ipa_rxcal_gaintbl_5GHz_rev7[6U] = { {0U, 0U, 0U, 0U, 0U, 100}, {0U, 0U, 0U, 0U, 0U, 50}, {0U, 0U, 0U, 0U, 0U, -1}, {0U, 0U, 0U, 3U, 0U, -1}, {0U, 0U, 3U, 3U, 0U, -1}, {0U, 0U, 5U, 3U, 0U, -1}}; static struct nphy_ipa_txrxgain const nphy_ipa_rxcal_gaintbl_2GHz_rev7[6U] = { {0U, 0U, 0U, 0U, 0U, 10}, {0U, 0U, 0U, 1U, 0U, 10}, {0U, 0U, 1U, 2U, 0U, 10}, {0U, 0U, 1U, 3U, 0U, 10}, {0U, 0U, 4U, 3U, 0U, 10}, {0U, 0U, 6U, 3U, 0U, 10}}; static u16 const NPHY_IPA_REV4_txdigi_filtcoeffs[7U][15U] = { { 65159U, 137U, 65129U, 208U, 64009U, 956U, 93U, 186U, 93U, 230U, 65492U, 230U, 201U, 65345U, 201U}, { 65459U, 20U, 65438U, 49U, 65443U, 60U, 56U, 111U, 56U, 26U, 65531U, 26U, 34U, 65504U, 34U}, { 65176U, 164U, 65160U, 164U, 64003U, 576U, 308U, 65222U, 308U, 121U, 65463U, 121U, 91U, 124U, 91U}, { 65241U, 200U, 65173U, 142U, 64145U, 826U, 151U, 301U, 151U, 151U, 301U, 151U, 602U, 64784U, 602U}, { 65444U, 58U, 65440U, 49U, 65432U, 44U, 17U, 35U, 17U, 12U, 25U, 12U, 13U, 27U, 13U}, { 65161U, 136U, 65137U, 209U, 64057U, 949U, 130U, 260U, 130U, 230U, 65492U, 230U, 201U, 65345U, 201U}, { 3801U, 200U, 3733U, 142U, 2705U, 826U, 151U, 301U, 151U, 151U, 301U, 151U, 602U, 3344U, 602U}}; static struct chan_info_nphy_2055 const chan_info_nphy_2055[124U] = { {184U, 4920U, 3280U, 113U, 1U, 236U, 15U, 255U, 1U, 4U, 10U, 0U, 143U, 255U, 255U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 3287U, 113U, 1U, 237U, 15U, 255U, 1U, 4U, 10U, 0U, 143U, 255U, 255U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 3293U, 113U, 1U, 238U, 15U, 255U, 1U, 4U, 10U, 0U, 143U, 238U, 238U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 3300U, 113U, 1U, 239U, 15U, 255U, 1U, 4U, 10U, 0U, 143U, 238U, 238U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 3307U, 113U, 1U, 240U, 15U, 255U, 1U, 4U, 10U, 0U, 143U, 238U, 238U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 3313U, 113U, 1U, 241U, 15U, 255U, 1U, 4U, 10U, 0U, 143U, 238U, 238U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 3320U, 113U, 1U, 242U, 14U, 255U, 1U, 4U, 10U, 0U, 143U, 221U, 221U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 3327U, 113U, 1U, 243U, 14U, 255U, 1U, 4U, 10U, 0U, 143U, 221U, 221U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 3333U, 113U, 1U, 244U, 14U, 255U, 1U, 4U, 10U, 0U, 143U, 221U, 221U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 3340U, 113U, 1U, 245U, 14U, 255U, 1U, 4U, 10U, 0U, 143U, 221U, 221U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 3347U, 113U, 1U, 246U, 14U, 247U, 1U, 4U, 10U, 0U, 143U, 204U, 204U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 3353U, 113U, 1U, 247U, 14U, 247U, 1U, 4U, 10U, 0U, 143U, 204U, 204U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 3360U, 113U, 1U, 248U, 13U, 239U, 1U, 4U, 10U, 0U, 143U, 204U, 204U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 3367U, 113U, 1U, 249U, 13U, 239U, 1U, 4U, 10U, 0U, 143U, 204U, 204U, 255U, 0U, 15U, 15U, 143U, 255U, 0U, 15U, 15U, 143U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 3373U, 113U, 1U, 250U, 13U, 230U, 1U, 4U, 10U, 0U, 143U, 187U, 187U, 255U, 0U, 14U, 15U, 142U, 255U, 0U, 14U, 15U, 142U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 3380U, 113U, 1U, 251U, 13U, 230U, 1U, 4U, 10U, 0U, 143U, 187U, 187U, 255U, 0U, 14U, 15U, 142U, 255U, 0U, 14U, 15U, 142U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 3387U, 113U, 1U, 252U, 13U, 222U, 1U, 4U, 10U, 0U, 142U, 187U, 187U, 238U, 0U, 14U, 15U, 141U, 238U, 0U, 14U, 15U, 141U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 3393U, 113U, 1U, 253U, 13U, 222U, 1U, 4U, 10U, 0U, 142U, 187U, 187U, 238U, 0U, 14U, 15U, 141U, 238U, 0U, 14U, 15U, 141U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 3400U, 113U, 1U, 254U, 12U, 214U, 1U, 4U, 10U, 0U, 142U, 170U, 170U, 238U, 0U, 13U, 15U, 141U, 238U, 0U, 13U, 15U, 141U, 2044U, 2040U, 2036U, 513U, 514U, 515U}, {222U, 5110U, 3407U, 113U, 1U, 255U, 12U, 214U, 1U, 4U, 10U, 0U, 142U, 170U, 170U, 238U, 0U, 13U, 15U, 141U, 238U, 0U, 13U, 15U, 141U, 2048U, 2044U, 2040U, 512U, 513U, 514U}, {224U, 5120U, 3413U, 113U, 2U, 0U, 12U, 206U, 1U, 4U, 10U, 0U, 141U, 170U, 170U, 221U, 0U, 13U, 15U, 140U, 221U, 0U, 13U, 15U, 140U, 2052U, 2048U, 2044U, 511U, 512U, 513U}, {226U, 5130U, 3420U, 113U, 2U, 1U, 12U, 206U, 1U, 4U, 10U, 0U, 141U, 170U, 170U, 221U, 0U, 13U, 15U, 140U, 221U, 0U, 13U, 15U, 140U, 2056U, 2052U, 2048U, 510U, 511U, 512U}, {228U, 5140U, 3427U, 113U, 2U, 2U, 12U, 198U, 1U, 4U, 10U, 0U, 141U, 153U, 153U, 221U, 0U, 12U, 14U, 139U, 221U, 0U, 12U, 14U, 139U, 2060U, 2056U, 2052U, 509U, 510U, 511U}, {32U, 5160U, 3440U, 113U, 2U, 4U, 11U, 190U, 1U, 4U, 10U, 0U, 140U, 153U, 153U, 204U, 0U, 11U, 13U, 138U, 204U, 0U, 11U, 13U, 138U, 2068U, 2064U, 2060U, 507U, 508U, 509U}, {34U, 5170U, 3447U, 113U, 2U, 5U, 11U, 190U, 1U, 4U, 10U, 0U, 140U, 153U, 153U, 204U, 0U, 11U, 13U, 138U, 204U, 0U, 11U, 13U, 138U, 2072U, 2068U, 2064U, 506U, 507U, 508U}, {36U, 5180U, 3453U, 113U, 2U, 6U, 11U, 182U, 1U, 4U, 10U, 0U, 140U, 136U, 136U, 204U, 0U, 11U, 12U, 137U, 204U, 0U, 11U, 12U, 137U, 2076U, 2072U, 2068U, 505U, 506U, 507U}, {38U, 5190U, 3460U, 113U, 2U, 7U, 11U, 182U, 1U, 4U, 10U, 0U, 140U, 136U, 136U, 204U, 0U, 11U, 12U, 137U, 204U, 0U, 11U, 12U, 137U, 2080U, 2076U, 2072U, 504U, 505U, 506U}, {40U, 5200U, 3467U, 113U, 2U, 8U, 11U, 175U, 1U, 4U, 10U, 0U, 139U, 136U, 136U, 187U, 0U, 10U, 11U, 137U, 187U, 0U, 10U, 11U, 137U, 2084U, 2080U, 2076U, 503U, 504U, 505U}, {42U, 5210U, 3473U, 113U, 2U, 9U, 11U, 175U, 1U, 4U, 10U, 0U, 139U, 136U, 136U, 187U, 0U, 10U, 11U, 137U, 187U, 0U, 10U, 11U, 137U, 2088U, 2084U, 2080U, 502U, 503U, 504U}, {44U, 5220U, 3480U, 113U, 2U, 10U, 10U, 167U, 1U, 4U, 10U, 0U, 139U, 119U, 119U, 187U, 0U, 9U, 10U, 136U, 187U, 0U, 9U, 10U, 136U, 2092U, 2088U, 2084U, 501U, 502U, 503U}, {46U, 5230U, 3487U, 113U, 2U, 11U, 10U, 167U, 1U, 4U, 10U, 0U, 139U, 119U, 119U, 187U, 0U, 9U, 10U, 136U, 187U, 0U, 9U, 10U, 136U, 2096U, 2092U, 2088U, 500U, 501U, 502U}, {48U, 5240U, 3493U, 113U, 2U, 12U, 10U, 160U, 1U, 4U, 10U, 0U, 138U, 119U, 119U, 170U, 0U, 9U, 10U, 135U, 170U, 0U, 9U, 10U, 135U, 2100U, 2096U, 2092U, 499U, 500U, 501U}, {50U, 5250U, 3500U, 113U, 2U, 13U, 10U, 160U, 1U, 4U, 10U, 0U, 138U, 119U, 119U, 170U, 0U, 9U, 10U, 135U, 170U, 0U, 9U, 10U, 135U, 2104U, 2100U, 2096U, 498U, 499U, 500U}, {52U, 5260U, 3507U, 113U, 2U, 14U, 10U, 152U, 1U, 4U, 10U, 0U, 138U, 102U, 102U, 170U, 0U, 8U, 9U, 135U, 170U, 0U, 8U, 9U, 135U, 2108U, 2104U, 2100U, 497U, 498U, 499U}, {54U, 5270U, 3513U, 113U, 2U, 15U, 10U, 152U, 1U, 4U, 10U, 0U, 138U, 102U, 102U, 170U, 0U, 8U, 9U, 135U, 170U, 0U, 8U, 9U, 135U, 2112U, 2108U, 2104U, 496U, 497U, 498U}, {56U, 5280U, 3520U, 113U, 2U, 16U, 9U, 145U, 1U, 4U, 10U, 0U, 137U, 102U, 102U, 153U, 0U, 8U, 8U, 134U, 153U, 0U, 8U, 8U, 134U, 2116U, 2112U, 2108U, 496U, 496U, 497U}, {58U, 5290U, 3527U, 113U, 2U, 17U, 9U, 145U, 1U, 4U, 10U, 0U, 137U, 102U, 102U, 153U, 0U, 8U, 8U, 134U, 153U, 0U, 8U, 8U, 134U, 2120U, 2116U, 2112U, 495U, 496U, 496U}, {60U, 5300U, 3533U, 113U, 2U, 18U, 9U, 138U, 1U, 4U, 10U, 0U, 137U, 85U, 85U, 153U, 0U, 8U, 7U, 133U, 153U, 0U, 8U, 7U, 133U, 2124U, 2120U, 2116U, 494U, 495U, 496U}, {62U, 5310U, 3540U, 113U, 2U, 19U, 9U, 138U, 1U, 4U, 10U, 0U, 137U, 85U, 85U, 153U, 0U, 8U, 7U, 133U, 153U, 0U, 8U, 7U, 133U, 2128U, 2124U, 2120U, 493U, 494U, 495U}, {64U, 5320U, 3547U, 113U, 2U, 20U, 9U, 131U, 1U, 4U, 10U, 0U, 136U, 85U, 85U, 136U, 0U, 7U, 7U, 132U, 136U, 0U, 7U, 7U, 132U, 2132U, 2128U, 2124U, 492U, 493U, 494U}, {66U, 5330U, 3553U, 113U, 2U, 21U, 9U, 131U, 1U, 4U, 10U, 0U, 136U, 85U, 85U, 136U, 0U, 7U, 7U, 132U, 136U, 0U, 7U, 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158U, 15U, 0U, 1U, 7U, 21U, 1U, 143U, 255U, 255U, 255U, 136U, 8U, 4U, 128U, 255U, 136U, 8U, 4U, 128U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 3289U, 115U, 9U, 163U, 15U, 0U, 1U, 7U, 21U, 1U, 143U, 255U, 255U, 255U, 136U, 8U, 3U, 128U, 255U, 136U, 8U, 3U, 128U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 3296U, 115U, 9U, 168U, 15U, 0U, 1U, 7U, 21U, 1U, 143U, 255U, 255U, 255U, 136U, 7U, 3U, 128U, 255U, 136U, 7U, 3U, 128U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 3312U, 115U, 9U, 180U, 15U, 255U, 1U, 7U, 21U, 1U, 143U, 255U, 255U, 255U, 136U, 7U, 1U, 128U, 255U, 136U, 7U, 1U, 128U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio205x const chan_info_nphyrev3_2056[124U] = { {184U, 4920U, 255U, 1U, 1U, 1U, 236U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 255U, 1U, 1U, 1U, 237U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 255U, 1U, 1U, 1U, 238U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 255U, 1U, 1U, 1U, 239U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 255U, 1U, 1U, 1U, 240U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 255U, 1U, 1U, 1U, 241U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 255U, 1U, 1U, 1U, 242U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 255U, 1U, 1U, 1U, 243U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 8U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 255U, 1U, 1U, 1U, 244U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 255U, 1U, 1U, 1U, 245U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 247U, 1U, 1U, 1U, 246U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 247U, 1U, 1U, 1U, 247U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 239U, 1U, 1U, 1U, 248U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 239U, 1U, 1U, 1U, 249U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 230U, 1U, 1U, 1U, 250U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 230U, 1U, 1U, 1U, 251U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 222U, 1U, 1U, 1U, 252U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 222U, 1U, 1U, 1U, 253U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 214U, 1U, 1U, 1U, 254U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 255U, 0U, 2044U, 2040U, 2036U, 513U, 514U, 515U}, {222U, 5110U, 214U, 1U, 1U, 1U, 255U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 2048U, 2044U, 2040U, 512U, 513U, 514U}, {224U, 5120U, 206U, 1U, 1U, 2U, 0U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 2052U, 2048U, 2044U, 511U, 512U, 513U}, {226U, 5130U, 206U, 1U, 1U, 2U, 1U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 2056U, 2052U, 2048U, 510U, 511U, 512U}, {228U, 5140U, 198U, 1U, 1U, 2U, 2U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 2060U, 2056U, 2052U, 509U, 510U, 511U}, {32U, 5160U, 190U, 1U, 1U, 2U, 4U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 2068U, 2064U, 2060U, 507U, 508U, 509U}, {34U, 5170U, 190U, 1U, 1U, 2U, 5U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 255U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 2072U, 2068U, 2064U, 506U, 507U, 508U}, {36U, 5180U, 182U, 1U, 1U, 2U, 6U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 239U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 239U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 2076U, 2072U, 2068U, 505U, 506U, 507U}, {38U, 5190U, 182U, 1U, 1U, 2U, 7U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 239U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 239U, 0U, 7U, 0U, 127U, 0U, 11U, 0U, 252U, 0U, 2080U, 2076U, 2072U, 504U, 505U, 506U}, {40U, 5200U, 175U, 1U, 1U, 2U, 8U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 239U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 239U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2084U, 2080U, 2076U, 503U, 504U, 505U}, {42U, 5210U, 175U, 1U, 1U, 2U, 9U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 223U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 223U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2088U, 2084U, 2080U, 502U, 503U, 504U}, {44U, 5220U, 167U, 1U, 1U, 2U, 10U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 223U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 223U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2092U, 2088U, 2084U, 501U, 502U, 503U}, {46U, 5230U, 167U, 1U, 1U, 2U, 11U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 223U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 223U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2096U, 2092U, 2088U, 500U, 501U, 502U}, {48U, 5240U, 160U, 1U, 1U, 2U, 12U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 207U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 207U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2100U, 2096U, 2092U, 499U, 500U, 501U}, {50U, 5250U, 160U, 1U, 1U, 2U, 13U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 207U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 207U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2104U, 2100U, 2096U, 498U, 499U, 500U}, {52U, 5260U, 152U, 1U, 1U, 2U, 14U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 207U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 207U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2108U, 2104U, 2100U, 497U, 498U, 499U}, {54U, 5270U, 152U, 1U, 1U, 2U, 15U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 143U, 15U, 0U, 255U, 207U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 207U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2112U, 2108U, 2104U, 496U, 497U, 498U}, {56U, 5280U, 145U, 1U, 1U, 2U, 16U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 143U, 15U, 0U, 255U, 191U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 191U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 2116U, 2112U, 2108U, 496U, 496U, 497U}, {58U, 5290U, 145U, 1U, 1U, 2U, 17U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 143U, 15U, 0U, 255U, 191U, 0U, 6U, 0U, 127U, 0U, 10U, 0U, 252U, 0U, 191U, 0U, 6U, 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0U, 64U, 5U, 0U, 2U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 5U, 0U, 2U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2316U, 2312U, 2308U, 453U, 454U, 454U}, {157U, 5785U, 242U, 0U, 2U, 4U, 133U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 138U, 6U, 0U, 64U, 4U, 0U, 2U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 4U, 0U, 2U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2318U, 2314U, 2310U, 452U, 453U, 454U}, {158U, 5790U, 10U, 1U, 1U, 2U, 67U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 138U, 6U, 0U, 64U, 4U, 0U, 2U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 4U, 0U, 2U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2320U, 2316U, 2312U, 452U, 453U, 454U}, {159U, 5795U, 242U, 0U, 2U, 4U, 135U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 138U, 6U, 0U, 64U, 4U, 0U, 2U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 4U, 0U, 2U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2322U, 2318U, 2314U, 452U, 452U, 453U}, {160U, 5800U, 10U, 1U, 1U, 2U, 68U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 4U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 4U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2324U, 2320U, 2316U, 451U, 452U, 453U}, {161U, 5805U, 237U, 0U, 2U, 4U, 137U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 4U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 4U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2326U, 2322U, 2318U, 451U, 452U, 452U}, {162U, 5810U, 10U, 1U, 1U, 2U, 69U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 4U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 4U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2328U, 2324U, 2320U, 450U, 451U, 452U}, {163U, 5815U, 237U, 0U, 2U, 4U, 139U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 4U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 4U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2330U, 2326U, 2322U, 450U, 451U, 452U}, {164U, 5820U, 10U, 1U, 1U, 2U, 70U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2332U, 2328U, 2324U, 450U, 450U, 451U}, {165U, 5825U, 237U, 0U, 2U, 4U, 141U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2334U, 2330U, 2326U, 449U, 450U, 451U}, {166U, 5830U, 10U, 1U, 1U, 2U, 71U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2336U, 2332U, 2328U, 449U, 450U, 450U}, {168U, 5840U, 10U, 1U, 1U, 2U, 72U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2340U, 2336U, 2332U, 448U, 449U, 450U}, {170U, 5850U, 224U, 0U, 1U, 2U, 73U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 244U, 0U, 2344U, 2340U, 2336U, 447U, 448U, 449U}, {172U, 5860U, 222U, 0U, 1U, 2U, 74U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 242U, 0U, 3U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 242U, 0U, 2348U, 2344U, 2340U, 447U, 447U, 448U}, {174U, 5870U, 219U, 0U, 1U, 2U, 75U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 2U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 242U, 0U, 2U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 242U, 0U, 2352U, 2348U, 2344U, 446U, 447U, 447U}, {176U, 5880U, 216U, 0U, 1U, 2U, 76U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 2U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 242U, 0U, 2U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 242U, 0U, 2356U, 2352U, 2348U, 445U, 446U, 447U}, {178U, 5890U, 214U, 0U, 1U, 2U, 77U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 2U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 242U, 0U, 2U, 0U, 0U, 0U, 127U, 0U, 6U, 0U, 242U, 0U, 2360U, 2356U, 2352U, 444U, 445U, 446U}, {180U, 5900U, 211U, 0U, 1U, 2U, 78U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 135U, 3U, 0U, 0U, 2U, 0U, 0U, 0U, 127U, 0U, 5U, 0U, 242U, 0U, 2U, 0U, 0U, 0U, 127U, 0U, 5U, 0U, 242U, 0U, 2364U, 2360U, 2356U, 444U, 444U, 445U}, {182U, 5910U, 214U, 0U, 1U, 2U, 79U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 135U, 3U, 0U, 0U, 1U, 0U, 0U, 0U, 127U, 0U, 5U, 0U, 242U, 0U, 1U, 0U, 0U, 0U, 127U, 0U, 5U, 0U, 242U, 0U, 2368U, 2364U, 2360U, 443U, 444U, 444U}, {1U, 2412U, 0U, 1U, 3U, 9U, 108U, 8U, 8U, 4U, 22U, 1U, 4U, 4U, 4U, 143U, 48U, 0U, 0U, 0U, 255U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 255U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 0U, 1U, 3U, 9U, 113U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 255U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 255U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 0U, 1U, 3U, 9U, 118U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 255U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 255U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 0U, 1U, 3U, 9U, 123U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 253U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 253U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 0U, 1U, 3U, 9U, 128U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 251U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 251U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 0U, 1U, 3U, 9U, 133U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 250U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 250U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 0U, 1U, 3U, 9U, 138U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 248U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 248U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 0U, 1U, 3U, 9U, 143U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 247U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 247U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 0U, 1U, 3U, 9U, 148U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 246U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 0U, 246U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 15U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 0U, 1U, 3U, 9U, 153U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 245U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 0U, 245U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 0U, 1U, 3U, 9U, 158U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 244U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 0U, 244U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 0U, 1U, 3U, 9U, 163U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 243U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 0U, 243U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 0U, 1U, 3U, 9U, 168U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 242U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 0U, 242U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 255U, 1U, 3U, 9U, 180U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 240U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 0U, 240U, 0U, 5U, 0U, 112U, 0U, 15U, 0U, 13U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio205x const chan_info_nphyrev4_2056_A1[124U] = { {184U, 4920U, 255U, 1U, 1U, 1U, 236U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 14U, 0U, 127U, 0U, 15U, 0U, 255U, 0U, 255U, 0U, 14U, 0U, 127U, 0U, 15U, 0U, 255U, 0U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 255U, 1U, 1U, 1U, 237U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 14U, 0U, 127U, 0U, 15U, 0U, 255U, 0U, 255U, 0U, 14U, 0U, 127U, 0U, 15U, 0U, 255U, 0U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 255U, 1U, 1U, 1U, 238U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 14U, 0U, 127U, 0U, 15U, 0U, 255U, 0U, 255U, 0U, 14U, 0U, 127U, 0U, 15U, 0U, 255U, 0U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 255U, 1U, 1U, 1U, 239U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 14U, 0U, 127U, 0U, 15U, 0U, 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445U, 446U, 447U}, {178U, 5890U, 214U, 0U, 1U, 2U, 77U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 136U, 4U, 0U, 32U, 2U, 0U, 2U, 0U, 127U, 0U, 9U, 0U, 240U, 0U, 2U, 0U, 2U, 0U, 127U, 0U, 9U, 0U, 240U, 0U, 2360U, 2356U, 2352U, 444U, 445U, 446U}, {180U, 5900U, 211U, 0U, 1U, 2U, 78U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 135U, 3U, 0U, 0U, 2U, 0U, 0U, 0U, 127U, 0U, 7U, 0U, 240U, 0U, 2U, 0U, 0U, 0U, 127U, 0U, 7U, 0U, 240U, 0U, 2364U, 2360U, 2356U, 444U, 444U, 445U}, {182U, 5910U, 214U, 0U, 1U, 2U, 79U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 135U, 3U, 0U, 0U, 1U, 0U, 0U, 0U, 127U, 0U, 7U, 0U, 240U, 0U, 1U, 0U, 0U, 0U, 127U, 0U, 7U, 0U, 240U, 0U, 2368U, 2364U, 2360U, 443U, 444U, 444U}, {1U, 2412U, 0U, 1U, 3U, 9U, 108U, 8U, 8U, 4U, 22U, 1U, 4U, 4U, 4U, 143U, 48U, 0U, 0U, 0U, 255U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 255U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 0U, 1U, 3U, 9U, 113U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 255U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 255U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 0U, 1U, 3U, 9U, 118U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 255U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 255U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 0U, 1U, 3U, 9U, 123U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 253U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 253U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 0U, 1U, 3U, 9U, 128U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 251U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 251U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 0U, 1U, 3U, 9U, 133U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 250U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 250U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 0U, 1U, 3U, 9U, 138U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 248U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 248U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 0U, 1U, 3U, 9U, 143U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 247U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 247U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 0U, 1U, 3U, 9U, 148U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 246U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 246U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 0U, 1U, 3U, 9U, 153U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 245U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 245U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 0U, 1U, 3U, 9U, 158U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 244U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 244U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 0U, 1U, 3U, 9U, 163U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 243U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 243U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 0U, 1U, 3U, 9U, 168U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 242U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 242U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 255U, 1U, 3U, 9U, 180U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 240U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 0U, 240U, 0U, 4U, 0U, 112U, 0U, 15U, 0U, 14U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio205x const chan_info_nphyrev5_2056v5[124U] = { {184U, 4920U, 255U, 1U, 1U, 1U, 236U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 11U, 0U, 112U, 0U, 15U, 0U, 159U, 0U, 255U, 0U, 11U, 0U, 112U, 0U, 15U, 0U, 111U, 0U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 255U, 1U, 1U, 1U, 237U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 159U, 0U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 111U, 0U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 255U, 1U, 1U, 1U, 238U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 159U, 0U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 111U, 0U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 255U, 1U, 1U, 1U, 239U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 159U, 0U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 111U, 0U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 255U, 1U, 1U, 1U, 240U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 14U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 14U, 0U, 111U, 0U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 255U, 1U, 1U, 1U, 241U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 255U, 1U, 1U, 1U, 242U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 255U, 1U, 1U, 1U, 243U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 255U, 1U, 1U, 1U, 244U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 255U, 1U, 1U, 1U, 245U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 247U, 1U, 1U, 1U, 246U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 9U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 9U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 247U, 1U, 1U, 1U, 247U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 159U, 0U, 255U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 111U, 0U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 239U, 1U, 1U, 1U, 248U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 159U, 0U, 254U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 111U, 0U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 239U, 1U, 1U, 1U, 249U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 159U, 0U, 254U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 111U, 0U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 230U, 1U, 1U, 1U, 250U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 159U, 0U, 253U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 111U, 0U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 230U, 1U, 1U, 1U, 251U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 253U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 222U, 1U, 1U, 1U, 252U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 222U, 1U, 1U, 1U, 253U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 214U, 1U, 1U, 1U, 254U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 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0U, 2U, 0U, 112U, 0U, 14U, 0U, 9U, 0U, 7U, 0U, 2U, 0U, 112U, 0U, 14U, 0U, 9U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 0U, 1U, 3U, 9U, 153U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 6U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 9U, 0U, 6U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 9U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 0U, 1U, 3U, 9U, 158U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 5U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 9U, 0U, 5U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 9U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 0U, 1U, 3U, 9U, 163U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 4U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 0U, 4U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 0U, 1U, 3U, 9U, 168U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 3U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 0U, 3U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 255U, 1U, 3U, 9U, 180U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio205x const chan_info_nphyrev6_2056v6[124U] = { {184U, 4920U, 255U, 1U, 1U, 1U, 236U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 255U, 1U, 1U, 1U, 237U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 255U, 1U, 1U, 1U, 238U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 255U, 1U, 1U, 1U, 239U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 255U, 1U, 1U, 1U, 240U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 255U, 1U, 1U, 1U, 241U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 255U, 1U, 1U, 1U, 242U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 255U, 1U, 1U, 1U, 243U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 255U, 1U, 1U, 1U, 244U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 255U, 1U, 1U, 1U, 245U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 247U, 1U, 1U, 1U, 246U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 247U, 1U, 1U, 1U, 247U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 239U, 1U, 1U, 1U, 248U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 239U, 1U, 1U, 1U, 249U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 230U, 1U, 1U, 1U, 250U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 230U, 1U, 1U, 1U, 251U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 222U, 1U, 1U, 1U, 252U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 222U, 1U, 1U, 1U, 253U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 214U, 1U, 1U, 1U, 254U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 253U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 253U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2044U, 2040U, 2036U, 513U, 514U, 515U}, {222U, 5110U, 214U, 1U, 1U, 1U, 255U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2048U, 2044U, 2040U, 512U, 513U, 514U}, {224U, 5120U, 206U, 1U, 1U, 2U, 0U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2052U, 2048U, 2044U, 511U, 512U, 513U}, {226U, 5130U, 206U, 1U, 1U, 2U, 1U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2056U, 2052U, 2048U, 510U, 511U, 512U}, {228U, 5140U, 198U, 1U, 1U, 2U, 2U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 251U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 251U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2060U, 2056U, 2052U, 509U, 510U, 511U}, {32U, 5160U, 190U, 1U, 1U, 2U, 4U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 250U, 0U, 7U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 250U, 0U, 7U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 2068U, 2064U, 2060U, 507U, 508U, 509U}, {34U, 5170U, 190U, 1U, 1U, 2U, 5U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 250U, 0U, 7U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 250U, 0U, 7U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 2072U, 2068U, 2064U, 506U, 507U, 508U}, {36U, 5180U, 182U, 1U, 1U, 2U, 6U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 249U, 0U, 6U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 249U, 0U, 6U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 2076U, 2072U, 2068U, 505U, 506U, 507U}, {38U, 5190U, 182U, 1U, 1U, 2U, 7U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 249U, 0U, 6U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 249U, 0U, 6U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 2080U, 2076U, 2072U, 504U, 505U, 506U}, {40U, 5200U, 175U, 1U, 1U, 2U, 8U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 249U, 0U, 5U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 249U, 0U, 5U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 2084U, 2080U, 2076U, 503U, 504U, 505U}, {42U, 5210U, 175U, 1U, 1U, 2U, 9U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 249U, 0U, 5U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 249U, 0U, 5U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 2088U, 2084U, 2080U, 502U, 503U, 504U}, {44U, 5220U, 167U, 1U, 1U, 2U, 10U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 142U, 15U, 0U, 254U, 216U, 0U, 5U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 216U, 0U, 5U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 2092U, 2088U, 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119U, 0U, 5U, 0U, 108U, 0U, 2310U, 2306U, 2302U, 454U, 455U, 456U}, {154U, 5770U, 10U, 1U, 1U, 2U, 65U, 5U, 5U, 4U, 12U, 1U, 5U, 5U, 5U, 134U, 4U, 0U, 16U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 2312U, 2308U, 2304U, 454U, 454U, 455U}, {155U, 5775U, 248U, 0U, 2U, 4U, 131U, 7U, 7U, 4U, 16U, 1U, 5U, 5U, 5U, 134U, 4U, 0U, 16U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 2314U, 2310U, 2306U, 453U, 454U, 455U}, {156U, 5780U, 10U, 1U, 1U, 2U, 66U, 5U, 5U, 4U, 12U, 1U, 5U, 5U, 5U, 134U, 4U, 0U, 16U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 2316U, 2312U, 2308U, 453U, 454U, 454U}, {157U, 5785U, 242U, 0U, 2U, 4U, 133U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 2318U, 2314U, 2310U, 452U, 453U, 454U}, {158U, 5790U, 10U, 1U, 1U, 2U, 67U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 16U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 2320U, 2316U, 2312U, 452U, 453U, 454U}, {159U, 5795U, 242U, 0U, 2U, 4U, 135U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 2322U, 2318U, 2314U, 452U, 452U, 453U}, {160U, 5800U, 10U, 1U, 1U, 2U, 68U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 107U, 0U, 2324U, 2320U, 2316U, 451U, 452U, 453U}, {161U, 5805U, 237U, 0U, 2U, 4U, 137U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 106U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 106U, 0U, 2326U, 2322U, 2318U, 451U, 452U, 452U}, {162U, 5810U, 10U, 1U, 1U, 2U, 69U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 106U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 106U, 0U, 2328U, 2324U, 2320U, 450U, 451U, 452U}, {163U, 5815U, 237U, 0U, 2U, 4U, 139U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 106U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 106U, 0U, 2330U, 2326U, 2322U, 450U, 451U, 452U}, {164U, 5820U, 10U, 1U, 1U, 2U, 70U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 106U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 106U, 0U, 2332U, 2328U, 2324U, 450U, 450U, 451U}, {165U, 5825U, 237U, 0U, 2U, 4U, 141U, 7U, 7U, 4U, 16U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 105U, 0U, 2334U, 2330U, 2326U, 449U, 450U, 451U}, {166U, 5830U, 10U, 1U, 1U, 2U, 71U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 105U, 0U, 2336U, 2332U, 2328U, 449U, 450U, 450U}, {168U, 5840U, 10U, 1U, 1U, 2U, 72U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 2340U, 2336U, 2332U, 448U, 449U, 450U}, {170U, 5850U, 224U, 0U, 1U, 2U, 73U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 2344U, 2340U, 2336U, 447U, 448U, 449U}, {172U, 5860U, 222U, 0U, 1U, 2U, 74U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 2348U, 2344U, 2340U, 447U, 447U, 448U}, {174U, 5870U, 219U, 0U, 1U, 2U, 75U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 2352U, 2348U, 2344U, 446U, 447U, 447U}, {176U, 5880U, 216U, 0U, 1U, 2U, 76U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 2356U, 2352U, 2348U, 445U, 446U, 447U}, {178U, 5890U, 214U, 0U, 1U, 2U, 77U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 2360U, 2356U, 2352U, 444U, 445U, 446U}, {180U, 5900U, 211U, 0U, 1U, 2U, 78U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 2364U, 2360U, 2356U, 444U, 444U, 445U}, {182U, 5910U, 214U, 0U, 1U, 2U, 79U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 104U, 0U, 2368U, 2364U, 2360U, 443U, 444U, 444U}, {1U, 2412U, 0U, 1U, 3U, 9U, 108U, 8U, 8U, 4U, 22U, 1U, 4U, 4U, 4U, 143U, 48U, 0U, 0U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 0U, 1U, 3U, 9U, 113U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 0U, 1U, 3U, 9U, 118U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 103U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 0U, 103U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 0U, 1U, 3U, 9U, 123U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 87U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 0U, 87U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 0U, 1U, 3U, 9U, 128U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 86U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 0U, 86U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 0U, 1U, 3U, 9U, 133U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 70U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 0U, 70U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 0U, 1U, 3U, 9U, 138U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 69U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 10U, 0U, 69U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 10U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 0U, 1U, 3U, 9U, 143U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 52U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 52U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 0U, 1U, 3U, 9U, 148U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 35U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 35U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 0U, 1U, 3U, 9U, 153U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 18U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 18U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 0U, 1U, 3U, 9U, 158U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 2U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 2U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 0U, 1U, 3U, 9U, 163U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 1U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 1U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 0U, 1U, 3U, 9U, 168U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 1U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 1U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 255U, 1U, 3U, 9U, 180U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 32U, 0U, 0U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio205x const chan_info_nphyrev5n6_2056v7[124U] = { {184U, 4920U, 255U, 1U, 1U, 1U, 236U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 11U, 0U, 112U, 0U, 15U, 0U, 159U, 0U, 255U, 0U, 11U, 0U, 112U, 0U, 15U, 0U, 111U, 0U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 255U, 1U, 1U, 1U, 237U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 159U, 0U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 111U, 0U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 255U, 1U, 1U, 1U, 238U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 159U, 0U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 111U, 0U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 255U, 1U, 1U, 1U, 239U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 159U, 0U, 255U, 0U, 11U, 0U, 112U, 0U, 14U, 0U, 111U, 0U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 255U, 1U, 1U, 1U, 240U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 14U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 14U, 0U, 111U, 0U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 255U, 1U, 1U, 1U, 241U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 255U, 1U, 1U, 1U, 242U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 255U, 1U, 1U, 1U, 243U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 255U, 1U, 1U, 1U, 244U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 255U, 1U, 1U, 1U, 245U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 10U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 247U, 1U, 1U, 1U, 246U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 9U, 0U, 112U, 0U, 13U, 0U, 159U, 0U, 255U, 0U, 9U, 0U, 112U, 0U, 13U, 0U, 111U, 0U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 247U, 1U, 1U, 1U, 247U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 255U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 159U, 0U, 255U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 111U, 0U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 239U, 1U, 1U, 1U, 248U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 159U, 0U, 254U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 111U, 0U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 239U, 1U, 1U, 1U, 249U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 159U, 0U, 254U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 111U, 0U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 230U, 1U, 1U, 1U, 250U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 159U, 0U, 253U, 0U, 9U, 0U, 112U, 0U, 12U, 0U, 111U, 0U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 230U, 1U, 1U, 1U, 251U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 253U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 222U, 1U, 1U, 1U, 252U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 222U, 1U, 1U, 1U, 253U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 214U, 1U, 1U, 1U, 254U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2044U, 2040U, 2036U, 513U, 514U, 515U}, {222U, 5110U, 214U, 1U, 1U, 1U, 255U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2048U, 2044U, 2040U, 512U, 513U, 514U}, {224U, 5120U, 206U, 1U, 1U, 2U, 0U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 159U, 0U, 252U, 0U, 8U, 0U, 112U, 0U, 11U, 0U, 111U, 0U, 2052U, 2048U, 2044U, 511U, 512U, 513U}, {226U, 5130U, 206U, 1U, 1U, 2U, 1U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 251U, 0U, 8U, 0U, 112U, 0U, 10U, 0U, 159U, 0U, 251U, 0U, 8U, 0U, 112U, 0U, 10U, 0U, 111U, 0U, 2056U, 2052U, 2048U, 510U, 511U, 512U}, {228U, 5140U, 198U, 1U, 1U, 2U, 2U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 251U, 0U, 7U, 0U, 112U, 0U, 10U, 0U, 159U, 0U, 251U, 0U, 7U, 0U, 112U, 0U, 10U, 0U, 111U, 0U, 2060U, 2056U, 2052U, 509U, 510U, 511U}, {32U, 5160U, 190U, 1U, 1U, 2U, 4U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 251U, 0U, 7U, 0U, 112U, 0U, 9U, 0U, 158U, 0U, 251U, 0U, 7U, 0U, 112U, 0U, 9U, 0U, 110U, 0U, 2068U, 2064U, 2060U, 507U, 508U, 509U}, {34U, 5170U, 190U, 1U, 1U, 2U, 5U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 251U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 158U, 0U, 251U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 110U, 0U, 2072U, 2068U, 2064U, 506U, 507U, 508U}, {36U, 5180U, 182U, 1U, 1U, 2U, 6U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 158U, 0U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 110U, 0U, 2076U, 2072U, 2068U, 505U, 506U, 507U}, {38U, 5190U, 182U, 1U, 1U, 2U, 7U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 158U, 0U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 110U, 0U, 2080U, 2076U, 2072U, 504U, 505U, 506U}, {40U, 5200U, 175U, 1U, 1U, 2U, 8U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 158U, 0U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 110U, 0U, 2084U, 2080U, 2076U, 503U, 504U, 505U}, {42U, 5210U, 175U, 1U, 1U, 2U, 9U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 158U, 0U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 110U, 0U, 2088U, 2084U, 2080U, 502U, 503U, 504U}, {44U, 5220U, 167U, 1U, 1U, 2U, 10U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 142U, 15U, 0U, 254U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 158U, 0U, 250U, 0U, 6U, 0U, 112U, 0U, 9U, 0U, 110U, 0U, 2092U, 2088U, 2084U, 501U, 502U, 503U}, {46U, 5230U, 167U, 1U, 1U, 2U, 11U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 142U, 15U, 0U, 238U, 234U, 0U, 6U, 0U, 112U, 0U, 8U, 0U, 158U, 0U, 234U, 0U, 6U, 0U, 112U, 0U, 8U, 0U, 110U, 0U, 2096U, 2092U, 2088U, 500U, 501U, 502U}, {48U, 5240U, 160U, 1U, 1U, 2U, 12U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 142U, 15U, 0U, 238U, 233U, 0U, 5U, 0U, 112U, 0U, 8U, 0U, 157U, 0U, 233U, 0U, 5U, 0U, 112U, 0U, 8U, 0U, 109U, 0U, 2100U, 2096U, 2092U, 499U, 500U, 501U}, {50U, 5250U, 160U, 1U, 1U, 2U, 13U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 142U, 15U, 0U, 237U, 233U, 0U, 5U, 0U, 112U, 0U, 8U, 0U, 157U, 0U, 233U, 0U, 5U, 0U, 112U, 0U, 8U, 0U, 109U, 0U, 2104U, 2100U, 2096U, 498U, 499U, 500U}, {52U, 5260U, 152U, 1U, 1U, 2U, 14U, 5U, 5U, 4U, 12U, 1U, 2U, 2U, 2U, 142U, 14U, 0U, 237U, 217U, 0U, 5U, 0U, 112U, 0U, 8U, 0U, 157U, 0U, 217U, 0U, 5U, 0U, 112U, 0U, 8U, 0U, 109U, 0U, 2108U, 2104U, 2100U, 497U, 498U, 499U}, {54U, 5270U, 152U, 1U, 1U, 2U, 15U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 142U, 14U, 0U, 237U, 216U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 156U, 0U, 216U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 108U, 0U, 2112U, 2108U, 2104U, 496U, 497U, 498U}, {56U, 5280U, 145U, 1U, 1U, 2U, 16U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 141U, 14U, 0U, 220U, 200U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 156U, 0U, 200U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 108U, 0U, 2116U, 2112U, 2108U, 496U, 496U, 497U}, {58U, 5290U, 145U, 1U, 1U, 2U, 17U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 141U, 14U, 0U, 220U, 200U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 156U, 0U, 200U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 108U, 0U, 2120U, 2116U, 2112U, 495U, 496U, 496U}, {60U, 5300U, 138U, 1U, 1U, 2U, 18U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 141U, 14U, 0U, 220U, 200U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 156U, 0U, 200U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 108U, 0U, 2124U, 2120U, 2116U, 494U, 495U, 496U}, {62U, 5310U, 138U, 1U, 1U, 2U, 19U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 141U, 14U, 0U, 220U, 200U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 156U, 0U, 200U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 108U, 0U, 2128U, 2124U, 2120U, 493U, 494U, 495U}, {64U, 5320U, 131U, 1U, 1U, 2U, 20U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 141U, 14U, 0U, 219U, 184U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 156U, 0U, 184U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 108U, 0U, 2132U, 2128U, 2124U, 492U, 493U, 494U}, {66U, 5330U, 131U, 1U, 1U, 2U, 21U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 141U, 13U, 0U, 203U, 183U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 155U, 0U, 183U, 0U, 4U, 0U, 112U, 0U, 7U, 0U, 107U, 0U, 2136U, 2132U, 2128U, 491U, 492U, 493U}, {68U, 5340U, 124U, 1U, 1U, 2U, 22U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 141U, 13U, 0U, 202U, 183U, 0U, 3U, 0U, 112U, 0U, 7U, 0U, 155U, 0U, 183U, 0U, 3U, 0U, 112U, 0U, 7U, 0U, 107U, 0U, 2140U, 2136U, 2132U, 490U, 491U, 492U}, {70U, 5350U, 124U, 1U, 1U, 2U, 23U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 140U, 13U, 0U, 202U, 167U, 0U, 3U, 0U, 112U, 0U, 6U, 0U, 155U, 0U, 167U, 0U, 3U, 0U, 112U, 0U, 6U, 0U, 107U, 0U, 2144U, 2140U, 2136U, 489U, 490U, 491U}, {72U, 5360U, 117U, 1U, 1U, 2U, 24U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 140U, 13U, 0U, 201U, 166U, 0U, 3U, 0U, 112U, 0U, 6U, 0U, 155U, 0U, 166U, 0U, 3U, 0U, 112U, 0U, 6U, 0U, 107U, 0U, 2148U, 2144U, 2140U, 488U, 489U, 490U}, {74U, 5370U, 117U, 1U, 1U, 2U, 25U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 140U, 13U, 0U, 201U, 166U, 0U, 3U, 0U, 112U, 0U, 6U, 0U, 155U, 0U, 166U, 0U, 3U, 0U, 112U, 0U, 6U, 0U, 123U, 0U, 2152U, 2148U, 2144U, 487U, 488U, 489U}, {76U, 5380U, 110U, 1U, 1U, 2U, 26U, 5U, 5U, 4U, 12U, 1U, 3U, 3U, 3U, 140U, 12U, 0U, 184U, 150U, 0U, 3U, 0U, 112U, 0U, 6U, 0U, 154U, 0U, 150U, 0U, 3U, 0U, 112U, 0U, 6U, 0U, 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112U, 0U, 0U, 0U, 146U, 0U, 16U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 2334U, 2330U, 2326U, 449U, 450U, 451U}, {166U, 5830U, 10U, 1U, 1U, 2U, 71U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 16U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 16U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 2336U, 2332U, 2328U, 449U, 450U, 450U}, {168U, 5840U, 10U, 1U, 1U, 2U, 72U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 16U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 16U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 2340U, 2336U, 2332U, 448U, 449U, 450U}, {170U, 5850U, 224U, 0U, 1U, 2U, 73U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 2344U, 2340U, 2336U, 447U, 448U, 449U}, {172U, 5860U, 222U, 0U, 1U, 2U, 74U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 146U, 0U, 2348U, 2344U, 2340U, 447U, 447U, 448U}, {174U, 5870U, 219U, 0U, 1U, 2U, 75U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 2352U, 2348U, 2344U, 446U, 447U, 447U}, {176U, 5880U, 216U, 0U, 1U, 2U, 76U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 2356U, 2352U, 2348U, 445U, 446U, 447U}, {178U, 5890U, 214U, 0U, 1U, 2U, 77U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 2360U, 2356U, 2352U, 444U, 445U, 446U}, {180U, 5900U, 211U, 0U, 1U, 2U, 78U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 2364U, 2360U, 2356U, 444U, 444U, 445U}, {182U, 5910U, 214U, 0U, 1U, 2U, 79U, 5U, 5U, 4U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 0U, 0U, 0U, 0U, 112U, 0U, 0U, 0U, 145U, 0U, 2368U, 2364U, 2360U, 443U, 444U, 444U}, {1U, 2412U, 0U, 1U, 3U, 9U, 108U, 8U, 8U, 4U, 22U, 1U, 4U, 4U, 4U, 143U, 48U, 0U, 0U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 15U, 0U, 11U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 15U, 0U, 11U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 0U, 1U, 3U, 9U, 113U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 15U, 0U, 10U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 15U, 0U, 10U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 0U, 1U, 3U, 9U, 118U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 15U, 0U, 10U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 15U, 0U, 10U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 0U, 1U, 3U, 9U, 123U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 14U, 0U, 10U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 14U, 0U, 10U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 0U, 1U, 3U, 9U, 128U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 119U, 0U, 3U, 0U, 112U, 0U, 14U, 0U, 10U, 0U, 119U, 0U, 3U, 0U, 112U, 0U, 14U, 0U, 10U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 0U, 1U, 3U, 9U, 133U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 118U, 0U, 3U, 0U, 112U, 0U, 14U, 0U, 10U, 0U, 118U, 0U, 3U, 0U, 112U, 0U, 14U, 0U, 10U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 0U, 1U, 3U, 9U, 138U, 8U, 8U, 4U, 22U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 102U, 0U, 3U, 0U, 112U, 0U, 14U, 0U, 10U, 0U, 102U, 0U, 3U, 0U, 112U, 0U, 14U, 0U, 10U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 0U, 1U, 3U, 9U, 143U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 85U, 0U, 2U, 0U, 112U, 0U, 14U, 0U, 9U, 0U, 85U, 0U, 2U, 0U, 112U, 0U, 14U, 0U, 9U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 0U, 1U, 3U, 9U, 148U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 69U, 0U, 2U, 0U, 112U, 0U, 14U, 0U, 9U, 0U, 69U, 0U, 2U, 0U, 112U, 0U, 14U, 0U, 9U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 0U, 1U, 3U, 9U, 153U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 52U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 9U, 0U, 52U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 9U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 0U, 1U, 3U, 9U, 158U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 51U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 9U, 0U, 51U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 9U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 0U, 1U, 3U, 9U, 163U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 34U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 0U, 34U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 0U, 1U, 3U, 9U, 168U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 17U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 0U, 17U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 255U, 1U, 3U, 9U, 180U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 32U, 0U, 0U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 13U, 0U, 8U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio205x const chan_info_nphyrev6_2056v8[124U] = { {184U, 4920U, 255U, 1U, 1U, 1U, 236U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 255U, 1U, 1U, 1U, 237U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 255U, 1U, 1U, 1U, 238U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 255U, 1U, 1U, 1U, 239U, 5U, 5U, 4U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 255U, 1U, 1U, 1U, 240U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 255U, 1U, 1U, 1U, 241U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 255U, 1U, 1U, 1U, 242U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 255U, 1U, 1U, 1U, 243U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 255U, 1U, 1U, 1U, 244U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 255U, 1U, 1U, 1U, 245U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 247U, 1U, 1U, 1U, 246U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 247U, 1U, 1U, 1U, 247U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 239U, 1U, 1U, 1U, 248U, 5U, 5U, 4U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 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0U, 10U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 0U, 1U, 3U, 9U, 143U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 52U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 85U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 0U, 1U, 3U, 9U, 148U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 35U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 69U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 0U, 1U, 3U, 9U, 153U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 18U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 52U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 0U, 1U, 3U, 9U, 158U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 2U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 51U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 0U, 1U, 3U, 9U, 163U, 8U, 8U, 4U, 22U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 1U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 34U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 0U, 1U, 3U, 9U, 168U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 1U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 17U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 255U, 1U, 3U, 9U, 180U, 8U, 8U, 4U, 22U, 1U, 7U, 7U, 7U, 143U, 32U, 0U, 0U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio205x const chan_info_nphyrev6_2056v11[124U] = { {184U, 4920U, 255U, 1U, 1U, 1U, 236U, 5U, 5U, 2U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 255U, 1U, 1U, 1U, 237U, 5U, 5U, 2U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 255U, 1U, 1U, 1U, 238U, 5U, 5U, 2U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 255U, 1U, 1U, 1U, 239U, 5U, 5U, 2U, 12U, 1U, 0U, 0U, 0U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 255U, 1U, 1U, 1U, 240U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 255U, 1U, 1U, 1U, 241U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 255U, 1U, 1U, 1U, 242U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 255U, 1U, 1U, 1U, 243U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 255U, 1U, 1U, 1U, 244U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 255U, 1U, 1U, 1U, 245U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 247U, 1U, 1U, 1U, 246U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 247U, 1U, 1U, 1U, 247U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 239U, 1U, 1U, 1U, 248U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 239U, 1U, 1U, 1U, 249U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 230U, 1U, 1U, 1U, 250U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 254U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 230U, 1U, 1U, 1U, 251U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 222U, 1U, 1U, 1U, 252U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 222U, 1U, 1U, 1U, 253U, 5U, 5U, 2U, 12U, 1U, 1U, 1U, 1U, 143U, 15U, 0U, 255U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 253U, 0U, 9U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 214U, 1U, 1U, 1U, 254U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 253U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 253U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2044U, 2040U, 2036U, 513U, 514U, 515U}, {222U, 5110U, 214U, 1U, 1U, 1U, 255U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2048U, 2044U, 2040U, 512U, 513U, 514U}, {224U, 5120U, 206U, 1U, 1U, 2U, 0U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2052U, 2048U, 2044U, 511U, 512U, 513U}, {226U, 5130U, 206U, 1U, 1U, 2U, 1U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 252U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2056U, 2052U, 2048U, 510U, 511U, 512U}, {228U, 5140U, 198U, 1U, 1U, 2U, 2U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 251U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 251U, 0U, 8U, 0U, 119U, 0U, 15U, 0U, 111U, 0U, 2060U, 2056U, 2052U, 509U, 510U, 511U}, {32U, 5160U, 190U, 1U, 1U, 2U, 4U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 250U, 0U, 7U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 250U, 0U, 7U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 2068U, 2064U, 2060U, 507U, 508U, 509U}, {34U, 5170U, 190U, 1U, 1U, 2U, 5U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 250U, 0U, 7U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 250U, 0U, 7U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 2072U, 2068U, 2064U, 506U, 507U, 508U}, {36U, 5180U, 182U, 1U, 1U, 2U, 6U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 249U, 0U, 6U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 249U, 0U, 6U, 0U, 119U, 0U, 14U, 0U, 111U, 0U, 2076U, 2072U, 2068U, 505U, 506U, 507U}, {38U, 5190U, 182U, 1U, 1U, 2U, 7U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 249U, 0U, 6U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 249U, 0U, 6U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 2080U, 2076U, 2072U, 504U, 505U, 506U}, {40U, 5200U, 175U, 1U, 1U, 2U, 8U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 143U, 15U, 0U, 255U, 249U, 0U, 5U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 249U, 0U, 5U, 0U, 119U, 0U, 13U, 0U, 111U, 0U, 2084U, 2080U, 2076U, 503U, 504U, 505U}, {42U, 5210U, 175U, 1U, 1U, 2U, 9U, 5U, 5U, 2U, 12U, 1U, 2U, 2U, 2U, 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2326U, 449U, 450U, 451U}, {166U, 5830U, 10U, 1U, 1U, 2U, 71U, 5U, 5U, 2U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 5U, 0U, 105U, 0U, 2336U, 2332U, 2328U, 449U, 450U, 450U}, {168U, 5840U, 10U, 1U, 1U, 2U, 72U, 5U, 5U, 2U, 12U, 1U, 6U, 6U, 6U, 134U, 4U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 2340U, 2336U, 2332U, 448U, 449U, 450U}, {170U, 5850U, 224U, 0U, 1U, 2U, 73U, 5U, 5U, 2U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 2344U, 2340U, 2336U, 447U, 448U, 449U}, {172U, 5860U, 222U, 0U, 1U, 2U, 74U, 5U, 5U, 2U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 0U, 0U, 0U, 0U, 119U, 0U, 4U, 0U, 105U, 0U, 2348U, 2344U, 2340U, 447U, 447U, 448U}, {174U, 5870U, 219U, 0U, 1U, 2U, 75U, 5U, 5U, 2U, 12U, 1U, 6U, 6U, 6U, 133U, 3U, 0U, 0U, 0U, 0U, 0U, 0U, 119U, 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108U, 6U, 6U, 4U, 43U, 1U, 4U, 4U, 4U, 143U, 48U, 0U, 0U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 0U, 1U, 3U, 9U, 113U, 6U, 6U, 4U, 43U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 0U, 1U, 3U, 9U, 118U, 6U, 6U, 4U, 43U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 103U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 0U, 137U, 0U, 3U, 0U, 112U, 0U, 11U, 0U, 10U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 0U, 1U, 3U, 9U, 123U, 6U, 6U, 4U, 43U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 87U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 0U, 120U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 0U, 1U, 3U, 9U, 128U, 6U, 6U, 4U, 43U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 86U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 0U, 119U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 0U, 1U, 3U, 9U, 133U, 6U, 6U, 4U, 43U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 70U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 0U, 118U, 0U, 3U, 0U, 112U, 0U, 10U, 0U, 10U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 0U, 1U, 3U, 9U, 138U, 6U, 6U, 4U, 43U, 1U, 5U, 5U, 5U, 143U, 48U, 0U, 0U, 0U, 69U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 10U, 0U, 102U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 10U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 0U, 1U, 3U, 9U, 143U, 6U, 6U, 4U, 43U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 52U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 85U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 0U, 1U, 3U, 9U, 148U, 6U, 6U, 4U, 43U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 35U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 69U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 0U, 1U, 3U, 9U, 153U, 6U, 6U, 4U, 43U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 18U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 0U, 52U, 0U, 2U, 0U, 112U, 0U, 10U, 0U, 9U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 0U, 1U, 3U, 9U, 158U, 6U, 6U, 4U, 43U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 2U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 51U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 0U, 1U, 3U, 9U, 163U, 6U, 6U, 4U, 43U, 1U, 6U, 6U, 6U, 143U, 48U, 0U, 0U, 0U, 1U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 34U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 0U, 1U, 3U, 9U, 168U, 6U, 6U, 4U, 43U, 1U, 7U, 7U, 7U, 143U, 48U, 0U, 0U, 0U, 1U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 17U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 255U, 1U, 3U, 9U, 180U, 6U, 6U, 4U, 43U, 1U, 7U, 7U, 7U, 143U, 32U, 0U, 0U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 0U, 0U, 0U, 2U, 0U, 112U, 0U, 9U, 0U, 9U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio2057 const chan_info_nphyrev7_2057_rev4[123U] = { {184U, 4920U, 104U, 22U, 16U, 12U, 12U, 12U, 48U, 236U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 107U, 22U, 16U, 12U, 12U, 12U, 48U, 237U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 110U, 22U, 16U, 12U, 12U, 12U, 48U, 238U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 114U, 22U, 16U, 12U, 12U, 12U, 48U, 239U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 117U, 22U, 16U, 12U, 12U, 12U, 48U, 240U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 120U, 22U, 16U, 12U, 12U, 12U, 48U, 241U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 124U, 22U, 16U, 12U, 12U, 12U, 48U, 242U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 127U, 22U, 16U, 12U, 12U, 12U, 48U, 243U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 130U, 22U, 16U, 12U, 12U, 12U, 48U, 244U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 134U, 22U, 16U, 12U, 12U, 12U, 48U, 245U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 137U, 22U, 16U, 12U, 12U, 12U, 48U, 246U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 140U, 22U, 16U, 12U, 12U, 12U, 48U, 247U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 144U, 22U, 16U, 12U, 12U, 12U, 48U, 248U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 147U, 22U, 16U, 12U, 12U, 12U, 48U, 249U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 0U, 0U, 15U, 15U, 243U, 0U, 239U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 150U, 22U, 16U, 12U, 12U, 12U, 48U, 250U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 227U, 0U, 239U, 0U, 0U, 15U, 15U, 227U, 0U, 239U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 154U, 22U, 16U, 12U, 12U, 12U, 48U, 251U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 14U, 15U, 227U, 0U, 239U, 0U, 0U, 14U, 15U, 227U, 0U, 239U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 157U, 22U, 16U, 12U, 12U, 12U, 48U, 252U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 14U, 15U, 227U, 0U, 239U, 0U, 0U, 14U, 15U, 227U, 0U, 239U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 160U, 22U, 16U, 12U, 12U, 12U, 48U, 253U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 164U, 22U, 16U, 12U, 12U, 12U, 48U, 254U, 1U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 2044U, 2040U, 2036U, 513U, 514U, 515U}, {222U, 5110U, 167U, 22U, 16U, 12U, 12U, 12U, 48U, 255U, 1U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 2048U, 2044U, 2040U, 512U, 513U, 514U}, {224U, 5120U, 170U, 22U, 16U, 12U, 12U, 12U, 48U, 0U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 2052U, 2048U, 2044U, 511U, 512U, 513U}, {226U, 5130U, 174U, 22U, 16U, 12U, 12U, 12U, 48U, 1U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 0U, 0U, 14U, 15U, 227U, 0U, 214U, 2056U, 2052U, 2048U, 510U, 511U, 512U}, {228U, 5140U, 177U, 22U, 16U, 12U, 12U, 12U, 48U, 2U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 14U, 14U, 227U, 0U, 214U, 0U, 0U, 14U, 14U, 227U, 0U, 214U, 2060U, 2056U, 2052U, 509U, 510U, 511U}, {32U, 5160U, 184U, 22U, 16U, 12U, 12U, 12U, 48U, 4U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 13U, 14U, 227U, 0U, 214U, 0U, 0U, 13U, 14U, 227U, 0U, 214U, 2068U, 2064U, 2060U, 507U, 508U, 509U}, {34U, 5170U, 187U, 22U, 16U, 12U, 12U, 12U, 48U, 5U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 13U, 14U, 227U, 0U, 214U, 0U, 0U, 13U, 14U, 227U, 0U, 214U, 2072U, 2068U, 2064U, 506U, 507U, 508U}, {36U, 5180U, 190U, 22U, 16U, 12U, 12U, 12U, 48U, 6U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 13U, 14U, 211U, 0U, 214U, 0U, 0U, 13U, 14U, 211U, 0U, 214U, 2076U, 2072U, 2068U, 505U, 506U, 507U}, {38U, 5190U, 194U, 22U, 16U, 12U, 12U, 12U, 48U, 7U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 13U, 14U, 211U, 0U, 214U, 0U, 0U, 13U, 14U, 211U, 0U, 214U, 2080U, 2076U, 2072U, 504U, 505U, 506U}, {40U, 5200U, 197U, 22U, 16U, 12U, 12U, 12U, 48U, 8U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 13U, 14U, 211U, 0U, 214U, 0U, 0U, 13U, 14U, 211U, 0U, 214U, 2084U, 2080U, 2076U, 503U, 504U, 505U}, {42U, 5210U, 200U, 22U, 16U, 12U, 12U, 12U, 48U, 9U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 13U, 14U, 211U, 0U, 214U, 0U, 0U, 13U, 14U, 211U, 0U, 214U, 2088U, 2084U, 2080U, 502U, 503U, 504U}, {44U, 5220U, 204U, 22U, 16U, 12U, 12U, 12U, 48U, 10U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 12U, 14U, 211U, 0U, 214U, 0U, 0U, 12U, 14U, 211U, 0U, 214U, 2092U, 2088U, 2084U, 501U, 502U, 503U}, {46U, 5230U, 207U, 22U, 16U, 12U, 12U, 12U, 48U, 11U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 12U, 14U, 211U, 0U, 214U, 0U, 0U, 12U, 14U, 211U, 0U, 214U, 2096U, 2092U, 2088U, 500U, 501U, 502U}, {48U, 5240U, 210U, 22U, 16U, 12U, 12U, 12U, 48U, 12U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 12U, 14U, 211U, 0U, 214U, 0U, 0U, 12U, 14U, 211U, 0U, 214U, 2100U, 2096U, 2092U, 499U, 500U, 501U}, {50U, 5250U, 214U, 22U, 16U, 12U, 12U, 12U, 48U, 13U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 12U, 14U, 211U, 0U, 214U, 0U, 0U, 12U, 14U, 211U, 0U, 214U, 2104U, 2100U, 2096U, 498U, 499U, 500U}, {52U, 5260U, 217U, 22U, 16U, 12U, 12U, 12U, 48U, 14U, 2U, 11U, 0U, 11U, 0U, 187U, 0U, 0U, 12U, 13U, 211U, 0U, 214U, 0U, 0U, 12U, 13U, 211U, 0U, 214U, 2108U, 2104U, 2100U, 497U, 498U, 499U}, {54U, 5270U, 220U, 22U, 16U, 12U, 12U, 12U, 48U, 15U, 2U, 11U, 0U, 11U, 0U, 187U, 0U, 0U, 12U, 13U, 211U, 0U, 214U, 0U, 0U, 12U, 13U, 211U, 0U, 214U, 2112U, 2108U, 2104U, 496U, 497U, 498U}, {56U, 5280U, 224U, 22U, 16U, 12U, 12U, 12U, 48U, 16U, 2U, 11U, 0U, 11U, 0U, 187U, 0U, 0U, 12U, 12U, 195U, 0U, 212U, 0U, 0U, 12U, 12U, 195U, 0U, 212U, 2116U, 2112U, 2108U, 496U, 496U, 497U}, {58U, 5290U, 227U, 22U, 16U, 12U, 12U, 12U, 48U, 17U, 2U, 11U, 0U, 11U, 0U, 187U, 0U, 0U, 12U, 12U, 195U, 0U, 212U, 0U, 0U, 12U, 12U, 195U, 0U, 212U, 2120U, 2116U, 2112U, 495U, 496U, 496U}, {60U, 5300U, 230U, 22U, 16U, 12U, 12U, 12U, 48U, 18U, 2U, 11U, 0U, 11U, 0U, 187U, 0U, 0U, 12U, 12U, 195U, 0U, 212U, 0U, 0U, 12U, 12U, 195U, 0U, 212U, 2124U, 2120U, 2116U, 494U, 495U, 496U}, {62U, 5310U, 234U, 22U, 16U, 12U, 12U, 12U, 48U, 19U, 2U, 11U, 0U, 11U, 0U, 187U, 0U, 0U, 11U, 12U, 195U, 0U, 212U, 0U, 0U, 11U, 12U, 195U, 0U, 212U, 2128U, 2124U, 2120U, 493U, 494U, 495U}, {64U, 5320U, 237U, 22U, 16U, 12U, 12U, 12U, 48U, 20U, 2U, 11U, 0U, 11U, 0U, 187U, 0U, 0U, 11U, 12U, 195U, 0U, 212U, 0U, 0U, 11U, 12U, 195U, 0U, 212U, 2132U, 2128U, 2124U, 492U, 493U, 494U}, {66U, 5330U, 240U, 22U, 16U, 12U, 12U, 12U, 48U, 21U, 2U, 11U, 0U, 11U, 0U, 187U, 0U, 0U, 11U, 12U, 195U, 0U, 212U, 0U, 0U, 11U, 12U, 195U, 0U, 212U, 2136U, 2132U, 2128U, 491U, 492U, 493U}, {68U, 5340U, 244U, 22U, 16U, 12U, 12U, 12U, 48U, 22U, 2U, 10U, 0U, 10U, 0U, 170U, 0U, 0U, 10U, 12U, 195U, 0U, 161U, 0U, 0U, 10U, 12U, 195U, 0U, 161U, 2140U, 2136U, 2132U, 490U, 491U, 492U}, {70U, 5350U, 247U, 22U, 16U, 12U, 12U, 12U, 48U, 23U, 2U, 10U, 0U, 10U, 0U, 170U, 0U, 0U, 10U, 11U, 179U, 0U, 161U, 0U, 0U, 10U, 11U, 179U, 0U, 161U, 2144U, 2140U, 2136U, 489U, 490U, 491U}, {72U, 5360U, 250U, 22U, 16U, 12U, 12U, 12U, 48U, 24U, 2U, 10U, 0U, 10U, 0U, 170U, 0U, 0U, 10U, 11U, 179U, 0U, 161U, 0U, 0U, 10U, 11U, 179U, 0U, 161U, 2148U, 2144U, 2140U, 488U, 489U, 490U}, {74U, 5370U, 254U, 22U, 16U, 12U, 12U, 12U, 48U, 25U, 2U, 10U, 0U, 10U, 0U, 170U, 0U, 0U, 10U, 11U, 179U, 0U, 161U, 0U, 0U, 10U, 11U, 179U, 0U, 161U, 2152U, 2148U, 2144U, 487U, 488U, 489U}, {76U, 5380U, 1U, 23U, 16U, 12U, 12U, 12U, 48U, 26U, 2U, 10U, 0U, 10U, 0U, 170U, 0U, 0U, 10U, 11U, 179U, 0U, 161U, 0U, 0U, 10U, 11U, 179U, 0U, 161U, 2156U, 2152U, 2148U, 486U, 487U, 488U}, {78U, 5390U, 4U, 23U, 16U, 12U, 12U, 12U, 48U, 27U, 2U, 10U, 0U, 10U, 0U, 170U, 0U, 0U, 10U, 10U, 163U, 0U, 161U, 0U, 0U, 10U, 10U, 163U, 0U, 161U, 2160U, 2156U, 2152U, 485U, 486U, 487U}, {80U, 5400U, 8U, 23U, 16U, 12U, 12U, 12U, 48U, 28U, 2U, 10U, 0U, 10U, 0U, 170U, 0U, 0U, 9U, 10U, 163U, 0U, 144U, 0U, 0U, 9U, 10U, 163U, 0U, 144U, 2164U, 2160U, 2156U, 485U, 485U, 486U}, {82U, 5410U, 11U, 23U, 16U, 12U, 12U, 12U, 48U, 29U, 2U, 10U, 0U, 10U, 0U, 170U, 0U, 0U, 9U, 10U, 163U, 0U, 144U, 0U, 0U, 9U, 10U, 163U, 0U, 144U, 2168U, 2164U, 2160U, 484U, 485U, 485U}, {84U, 5420U, 14U, 23U, 16U, 12U, 12U, 12U, 48U, 30U, 2U, 9U, 0U, 9U, 0U, 153U, 0U, 0U, 9U, 9U, 163U, 0U, 144U, 0U, 0U, 9U, 9U, 163U, 0U, 144U, 2172U, 2168U, 2164U, 483U, 484U, 485U}, {86U, 5430U, 18U, 23U, 16U, 12U, 12U, 12U, 48U, 31U, 2U, 9U, 0U, 9U, 0U, 153U, 0U, 0U, 9U, 9U, 147U, 0U, 144U, 0U, 0U, 9U, 9U, 147U, 0U, 144U, 2176U, 2172U, 2168U, 482U, 483U, 484U}, {88U, 5440U, 21U, 23U, 16U, 12U, 12U, 12U, 48U, 32U, 2U, 9U, 0U, 9U, 0U, 153U, 0U, 0U, 9U, 9U, 147U, 0U, 144U, 0U, 0U, 9U, 9U, 147U, 0U, 144U, 2180U, 2176U, 2172U, 481U, 482U, 483U}, {90U, 5450U, 24U, 23U, 16U, 12U, 12U, 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6U, 0U, 102U, 0U, 0U, 4U, 1U, 83U, 0U, 0U, 0U, 0U, 4U, 1U, 83U, 0U, 0U, 2304U, 2300U, 2296U, 455U, 456U, 457U}, {151U, 5755U, 126U, 23U, 32U, 20U, 8U, 8U, 48U, 127U, 4U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 4U, 1U, 83U, 0U, 0U, 0U, 0U, 4U, 1U, 83U, 0U, 0U, 2306U, 2302U, 2298U, 455U, 456U, 456U}, {152U, 5760U, 128U, 23U, 16U, 12U, 12U, 12U, 48U, 64U, 2U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 4U, 1U, 67U, 0U, 0U, 0U, 0U, 4U, 1U, 67U, 0U, 0U, 2308U, 2304U, 2300U, 454U, 455U, 456U}, {153U, 5765U, 129U, 23U, 32U, 20U, 8U, 8U, 48U, 129U, 4U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 4U, 1U, 67U, 0U, 0U, 0U, 0U, 4U, 1U, 67U, 0U, 0U, 2310U, 2306U, 2302U, 454U, 455U, 456U}, {154U, 5770U, 131U, 23U, 16U, 12U, 12U, 12U, 48U, 65U, 2U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 4U, 1U, 67U, 0U, 0U, 0U, 0U, 4U, 1U, 67U, 0U, 0U, 2312U, 2308U, 2304U, 454U, 454U, 455U}, {155U, 5775U, 133U, 23U, 32U, 20U, 8U, 8U, 48U, 131U, 4U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 4U, 1U, 67U, 0U, 0U, 0U, 0U, 4U, 1U, 67U, 0U, 0U, 2314U, 2310U, 2306U, 453U, 454U, 455U}, {156U, 5780U, 134U, 23U, 16U, 12U, 12U, 12U, 48U, 66U, 2U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 3U, 1U, 67U, 0U, 0U, 0U, 0U, 3U, 1U, 67U, 0U, 0U, 2316U, 2312U, 2308U, 453U, 454U, 454U}, {157U, 5785U, 136U, 23U, 32U, 20U, 8U, 8U, 48U, 133U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2318U, 2314U, 2310U, 452U, 453U, 454U}, {158U, 5790U, 138U, 23U, 16U, 12U, 12U, 12U, 48U, 67U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2320U, 2316U, 2312U, 452U, 453U, 454U}, {159U, 5795U, 139U, 23U, 32U, 20U, 8U, 8U, 48U, 135U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2322U, 2318U, 2314U, 452U, 452U, 453U}, {160U, 5800U, 141U, 23U, 16U, 12U, 12U, 12U, 48U, 68U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2324U, 2320U, 2316U, 451U, 452U, 453U}, {161U, 5805U, 143U, 23U, 32U, 20U, 8U, 8U, 48U, 137U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2326U, 2322U, 2318U, 451U, 452U, 452U}, {162U, 5810U, 144U, 23U, 16U, 12U, 12U, 12U, 48U, 69U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2328U, 2324U, 2320U, 450U, 451U, 452U}, {163U, 5815U, 146U, 23U, 32U, 20U, 8U, 8U, 48U, 139U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2330U, 2326U, 2322U, 450U, 451U, 452U}, {164U, 5820U, 148U, 23U, 16U, 12U, 12U, 12U, 48U, 70U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2332U, 2328U, 2324U, 450U, 450U, 451U}, {165U, 5825U, 149U, 23U, 32U, 20U, 8U, 8U, 48U, 141U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2334U, 2330U, 2326U, 449U, 450U, 451U}, {166U, 5830U, 151U, 23U, 16U, 12U, 12U, 12U, 48U, 71U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2336U, 2332U, 2328U, 449U, 450U, 450U}, {168U, 5840U, 154U, 23U, 16U, 12U, 12U, 12U, 48U, 72U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2340U, 2336U, 2332U, 448U, 449U, 450U}, {170U, 5850U, 158U, 23U, 16U, 12U, 12U, 12U, 48U, 73U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2344U, 2340U, 2336U, 447U, 448U, 449U}, {172U, 5860U, 161U, 23U, 16U, 12U, 12U, 12U, 48U, 74U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2348U, 2344U, 2340U, 447U, 447U, 448U}, {174U, 5870U, 164U, 23U, 16U, 12U, 12U, 12U, 48U, 75U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2352U, 2348U, 2344U, 446U, 447U, 447U}, {176U, 5880U, 168U, 23U, 16U, 12U, 12U, 12U, 48U, 76U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2356U, 2352U, 2348U, 445U, 446U, 447U}, {178U, 5890U, 171U, 23U, 16U, 12U, 12U, 12U, 48U, 77U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2360U, 2356U, 2352U, 444U, 445U, 446U}, {180U, 5900U, 174U, 23U, 16U, 12U, 12U, 12U, 48U, 78U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 0U, 0U, 3U, 0U, 67U, 0U, 0U, 2364U, 2360U, 2356U, 444U, 444U, 445U}, {1U, 2412U, 72U, 22U, 48U, 27U, 10U, 10U, 48U, 108U, 9U, 15U, 10U, 0U, 10U, 0U, 113U, 163U, 0U, 0U, 0U, 240U, 0U, 113U, 163U, 0U, 0U, 0U, 240U, 0U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 75U, 22U, 48U, 27U, 10U, 10U, 48U, 113U, 9U, 15U, 10U, 0U, 10U, 0U, 113U, 163U, 0U, 0U, 0U, 240U, 0U, 113U, 163U, 0U, 0U, 0U, 240U, 0U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 78U, 22U, 48U, 27U, 10U, 10U, 48U, 118U, 9U, 15U, 9U, 0U, 9U, 0U, 113U, 147U, 0U, 0U, 0U, 240U, 0U, 113U, 147U, 0U, 0U, 0U, 240U, 0U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 82U, 22U, 48U, 27U, 10U, 10U, 48U, 123U, 9U, 15U, 9U, 0U, 9U, 0U, 113U, 147U, 0U, 0U, 0U, 240U, 0U, 113U, 147U, 0U, 0U, 0U, 240U, 0U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 85U, 22U, 48U, 27U, 10U, 10U, 48U, 128U, 9U, 15U, 8U, 0U, 8U, 0U, 81U, 131U, 0U, 0U, 0U, 240U, 0U, 81U, 131U, 0U, 0U, 0U, 240U, 0U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 88U, 22U, 48U, 27U, 10U, 10U, 48U, 133U, 9U, 15U, 8U, 0U, 8U, 0U, 81U, 131U, 0U, 0U, 0U, 240U, 0U, 81U, 131U, 0U, 0U, 0U, 240U, 0U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 92U, 22U, 48U, 27U, 10U, 10U, 48U, 138U, 9U, 15U, 7U, 0U, 7U, 0U, 81U, 115U, 0U, 0U, 0U, 240U, 0U, 81U, 115U, 0U, 0U, 0U, 240U, 0U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 95U, 22U, 48U, 27U, 10U, 10U, 48U, 143U, 9U, 15U, 7U, 0U, 7U, 0U, 49U, 115U, 0U, 0U, 0U, 240U, 0U, 49U, 115U, 0U, 0U, 0U, 240U, 0U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 98U, 22U, 48U, 27U, 10U, 10U, 48U, 148U, 9U, 15U, 7U, 0U, 7U, 0U, 49U, 115U, 0U, 0U, 0U, 240U, 0U, 49U, 115U, 0U, 0U, 0U, 240U, 0U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 102U, 22U, 48U, 27U, 10U, 10U, 48U, 153U, 9U, 15U, 6U, 0U, 6U, 0U, 49U, 99U, 0U, 0U, 0U, 240U, 0U, 49U, 99U, 0U, 0U, 0U, 240U, 0U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 105U, 22U, 48U, 27U, 10U, 10U, 48U, 158U, 9U, 15U, 6U, 0U, 6U, 0U, 49U, 99U, 0U, 0U, 0U, 240U, 0U, 49U, 99U, 0U, 0U, 0U, 240U, 0U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 108U, 22U, 48U, 27U, 10U, 10U, 48U, 163U, 9U, 15U, 5U, 0U, 5U, 0U, 17U, 83U, 0U, 0U, 0U, 240U, 0U, 17U, 83U, 0U, 0U, 0U, 240U, 0U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 112U, 22U, 48U, 27U, 10U, 10U, 48U, 168U, 9U, 15U, 5U, 0U, 5U, 0U, 17U, 83U, 0U, 0U, 0U, 240U, 0U, 17U, 83U, 0U, 0U, 0U, 240U, 0U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 120U, 22U, 48U, 27U, 10U, 10U, 48U, 180U, 9U, 15U, 4U, 0U, 4U, 0U, 17U, 67U, 0U, 0U, 0U, 224U, 0U, 17U, 67U, 0U, 0U, 0U, 224U, 0U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio2057_rev5 const chan_info_nphyrev8_2057_rev5[14U] = { {1U, 2412U, 72U, 22U, 48U, 27U, 10U, 10U, 48U, 108U, 9U, 13U, 8U, 14U, 97U, 3U, 255U, 97U, 3U, 255U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 75U, 22U, 48U, 27U, 10U, 10U, 48U, 113U, 9U, 13U, 8U, 14U, 97U, 3U, 255U, 97U, 3U, 255U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 78U, 22U, 48U, 27U, 10U, 10U, 48U, 118U, 9U, 13U, 8U, 14U, 97U, 3U, 239U, 97U, 3U, 239U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 82U, 22U, 48U, 27U, 10U, 10U, 48U, 123U, 9U, 12U, 8U, 14U, 97U, 3U, 223U, 97U, 3U, 223U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 85U, 22U, 48U, 27U, 10U, 10U, 48U, 128U, 9U, 12U, 7U, 13U, 97U, 3U, 207U, 97U, 3U, 207U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 88U, 22U, 48U, 27U, 10U, 10U, 48U, 133U, 9U, 12U, 7U, 13U, 97U, 3U, 191U, 97U, 3U, 191U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 92U, 22U, 48U, 27U, 10U, 10U, 48U, 138U, 9U, 11U, 7U, 13U, 97U, 3U, 175U, 97U, 3U, 175U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 95U, 22U, 48U, 27U, 10U, 10U, 48U, 143U, 9U, 11U, 7U, 13U, 97U, 3U, 159U, 97U, 3U, 159U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 98U, 22U, 48U, 27U, 10U, 10U, 48U, 148U, 9U, 11U, 7U, 13U, 97U, 3U, 143U, 97U, 3U, 143U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 102U, 22U, 48U, 27U, 10U, 10U, 48U, 153U, 9U, 11U, 7U, 12U, 97U, 3U, 127U, 97U, 3U, 127U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 105U, 22U, 48U, 27U, 10U, 10U, 48U, 158U, 9U, 11U, 7U, 12U, 97U, 3U, 111U, 97U, 3U, 111U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 108U, 22U, 48U, 27U, 10U, 10U, 48U, 163U, 9U, 11U, 6U, 12U, 97U, 3U, 95U, 97U, 3U, 95U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 112U, 22U, 48U, 27U, 10U, 10U, 48U, 168U, 9U, 10U, 6U, 11U, 97U, 3U, 79U, 97U, 3U, 79U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 120U, 22U, 48U, 27U, 10U, 10U, 48U, 180U, 9U, 10U, 6U, 11U, 97U, 3U, 63U, 97U, 3U, 63U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio2057_rev5 const chan_info_nphyrev9_2057_rev5v1[14U] = { {1U, 2412U, 72U, 22U, 48U, 27U, 10U, 10U, 48U, 108U, 9U, 13U, 8U, 14U, 97U, 3U, 255U, 97U, 3U, 255U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 75U, 22U, 48U, 27U, 10U, 10U, 48U, 113U, 9U, 13U, 8U, 14U, 97U, 3U, 255U, 97U, 3U, 255U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 78U, 22U, 48U, 27U, 10U, 10U, 48U, 118U, 9U, 13U, 8U, 14U, 97U, 3U, 239U, 97U, 3U, 239U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 82U, 22U, 48U, 27U, 10U, 10U, 48U, 123U, 9U, 12U, 8U, 14U, 97U, 3U, 223U, 97U, 3U, 223U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 85U, 22U, 48U, 27U, 10U, 10U, 48U, 128U, 9U, 12U, 7U, 13U, 97U, 3U, 207U, 97U, 3U, 207U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 88U, 22U, 48U, 27U, 10U, 10U, 48U, 133U, 9U, 12U, 7U, 13U, 97U, 3U, 191U, 97U, 3U, 191U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 92U, 22U, 48U, 27U, 10U, 10U, 48U, 138U, 9U, 11U, 7U, 13U, 97U, 3U, 175U, 97U, 3U, 175U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 95U, 22U, 48U, 27U, 10U, 10U, 48U, 143U, 9U, 11U, 7U, 13U, 97U, 3U, 159U, 97U, 3U, 159U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 98U, 22U, 48U, 27U, 10U, 10U, 48U, 148U, 9U, 11U, 7U, 13U, 97U, 3U, 143U, 97U, 3U, 143U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 102U, 22U, 48U, 27U, 10U, 10U, 48U, 153U, 9U, 11U, 7U, 12U, 97U, 3U, 127U, 97U, 3U, 127U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 105U, 22U, 48U, 27U, 10U, 10U, 48U, 158U, 9U, 11U, 7U, 12U, 97U, 3U, 111U, 97U, 3U, 111U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 108U, 22U, 48U, 27U, 10U, 10U, 48U, 163U, 9U, 11U, 6U, 12U, 97U, 3U, 95U, 97U, 3U, 95U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 112U, 22U, 48U, 27U, 10U, 10U, 48U, 168U, 9U, 10U, 6U, 11U, 97U, 3U, 79U, 97U, 3U, 79U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 120U, 22U, 48U, 27U, 10U, 10U, 48U, 180U, 9U, 10U, 6U, 11U, 97U, 3U, 63U, 97U, 3U, 63U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio2057 const chan_info_nphyrev8_2057_rev7[123U] = { {184U, 4920U, 104U, 22U, 16U, 12U, 12U, 12U, 48U, 236U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 211U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1972U, 1968U, 1964U, 532U, 533U, 534U}, {186U, 4930U, 107U, 22U, 16U, 12U, 12U, 12U, 48U, 237U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 211U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 110U, 22U, 16U, 12U, 12U, 12U, 48U, 238U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 211U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 114U, 22U, 16U, 12U, 12U, 12U, 48U, 239U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 117U, 22U, 16U, 12U, 12U, 12U, 48U, 240U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 120U, 22U, 16U, 12U, 12U, 12U, 48U, 241U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 124U, 22U, 16U, 12U, 12U, 12U, 48U, 242U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 127U, 22U, 16U, 12U, 12U, 12U, 48U, 243U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 130U, 22U, 16U, 12U, 12U, 12U, 48U, 244U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 134U, 22U, 16U, 12U, 12U, 12U, 48U, 245U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 137U, 22U, 16U, 12U, 12U, 12U, 48U, 246U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 140U, 22U, 16U, 12U, 12U, 12U, 48U, 247U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 144U, 22U, 16U, 12U, 12U, 12U, 48U, 248U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 147U, 22U, 16U, 12U, 12U, 12U, 48U, 249U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 150U, 22U, 16U, 12U, 12U, 12U, 48U, 250U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 154U, 22U, 16U, 12U, 12U, 12U, 48U, 251U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 157U, 22U, 16U, 12U, 12U, 12U, 48U, 252U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 160U, 22U, 16U, 12U, 12U, 12U, 48U, 253U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 164U, 22U, 16U, 12U, 12U, 12U, 48U, 254U, 1U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2044U, 2040U, 2036U, 513U, 514U, 515U}, {222U, 5110U, 167U, 22U, 16U, 12U, 12U, 12U, 48U, 255U, 1U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2048U, 2044U, 2040U, 512U, 513U, 514U}, {224U, 5120U, 170U, 22U, 16U, 12U, 12U, 12U, 48U, 0U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2052U, 2048U, 2044U, 511U, 512U, 513U}, {226U, 5130U, 174U, 22U, 16U, 12U, 12U, 12U, 48U, 1U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2056U, 2052U, 2048U, 510U, 511U, 512U}, {228U, 5140U, 177U, 22U, 16U, 12U, 12U, 12U, 48U, 2U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2060U, 2056U, 2052U, 509U, 510U, 511U}, {32U, 5160U, 184U, 22U, 16U, 12U, 12U, 12U, 48U, 4U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2068U, 2064U, 2060U, 507U, 508U, 509U}, {34U, 5170U, 187U, 22U, 16U, 12U, 12U, 12U, 48U, 5U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2072U, 2068U, 2064U, 506U, 507U, 508U}, {36U, 5180U, 190U, 22U, 16U, 12U, 12U, 12U, 48U, 6U, 2U, 12U, 0U, 12U, 0U, 204U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2076U, 2072U, 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6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2326U, 2322U, 2318U, 451U, 452U, 452U}, {162U, 5810U, 144U, 23U, 16U, 12U, 12U, 12U, 48U, 69U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2328U, 2324U, 2320U, 450U, 451U, 452U}, {163U, 5815U, 146U, 23U, 32U, 20U, 8U, 8U, 48U, 139U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2330U, 2326U, 2322U, 450U, 451U, 452U}, {164U, 5820U, 148U, 23U, 16U, 12U, 12U, 12U, 48U, 70U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2332U, 2328U, 2324U, 450U, 450U, 451U}, {165U, 5825U, 149U, 23U, 32U, 20U, 8U, 8U, 48U, 141U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2334U, 2330U, 2326U, 449U, 450U, 451U}, {166U, 5830U, 151U, 23U, 16U, 12U, 12U, 12U, 48U, 71U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2336U, 2332U, 2328U, 449U, 450U, 450U}, {168U, 5840U, 154U, 23U, 16U, 12U, 12U, 12U, 48U, 72U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2340U, 2336U, 2332U, 448U, 449U, 450U}, {170U, 5850U, 158U, 23U, 16U, 12U, 12U, 12U, 48U, 73U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2344U, 2340U, 2336U, 447U, 448U, 449U}, {172U, 5860U, 161U, 23U, 16U, 12U, 12U, 12U, 48U, 74U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2348U, 2344U, 2340U, 447U, 447U, 448U}, {174U, 5870U, 164U, 23U, 16U, 12U, 12U, 12U, 48U, 75U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2352U, 2348U, 2344U, 446U, 447U, 447U}, {176U, 5880U, 168U, 23U, 16U, 12U, 12U, 12U, 48U, 76U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2356U, 2352U, 2348U, 445U, 446U, 447U}, {178U, 5890U, 171U, 23U, 16U, 12U, 12U, 12U, 48U, 77U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2360U, 2356U, 2352U, 444U, 445U, 446U}, {180U, 5900U, 174U, 23U, 16U, 12U, 12U, 12U, 48U, 78U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2364U, 2360U, 2356U, 444U, 444U, 445U}, {1U, 2412U, 72U, 22U, 48U, 27U, 10U, 10U, 48U, 108U, 9U, 15U, 10U, 0U, 10U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 75U, 22U, 48U, 27U, 10U, 10U, 48U, 113U, 9U, 15U, 10U, 0U, 10U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 78U, 22U, 48U, 27U, 10U, 10U, 48U, 118U, 9U, 15U, 9U, 0U, 9U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 82U, 22U, 48U, 27U, 10U, 10U, 48U, 123U, 9U, 15U, 9U, 0U, 9U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 85U, 22U, 48U, 27U, 10U, 10U, 48U, 128U, 9U, 15U, 8U, 0U, 8U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 88U, 22U, 48U, 27U, 10U, 10U, 48U, 133U, 9U, 15U, 8U, 0U, 8U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 92U, 22U, 48U, 27U, 10U, 10U, 48U, 138U, 9U, 15U, 7U, 0U, 7U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 95U, 22U, 48U, 27U, 10U, 10U, 48U, 143U, 9U, 15U, 7U, 0U, 7U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 98U, 22U, 48U, 27U, 10U, 10U, 48U, 148U, 9U, 15U, 7U, 0U, 7U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 102U, 22U, 48U, 27U, 10U, 10U, 48U, 153U, 9U, 15U, 6U, 0U, 6U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 105U, 22U, 48U, 27U, 10U, 10U, 48U, 158U, 9U, 15U, 6U, 0U, 6U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 108U, 22U, 48U, 27U, 10U, 10U, 48U, 163U, 9U, 15U, 5U, 0U, 5U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 112U, 22U, 48U, 27U, 10U, 10U, 48U, 168U, 9U, 15U, 5U, 0U, 5U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 120U, 22U, 48U, 27U, 10U, 10U, 48U, 180U, 9U, 15U, 4U, 0U, 4U, 0U, 97U, 115U, 0U, 0U, 0U, 224U, 0U, 97U, 115U, 0U, 0U, 0U, 224U, 0U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct chan_info_nphy_radio2057 const chan_info_nphyrev8_2057_rev8[122U] = { {186U, 4930U, 107U, 22U, 16U, 12U, 12U, 12U, 48U, 237U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 211U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1976U, 1972U, 1968U, 531U, 532U, 533U}, {188U, 4940U, 110U, 22U, 16U, 12U, 12U, 12U, 48U, 238U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 211U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1980U, 1976U, 1972U, 530U, 531U, 532U}, {190U, 4950U, 114U, 22U, 16U, 12U, 12U, 12U, 48U, 239U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1984U, 1980U, 1976U, 529U, 530U, 531U}, {192U, 4960U, 117U, 22U, 16U, 12U, 12U, 12U, 48U, 240U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1988U, 1984U, 1980U, 527U, 529U, 530U}, {194U, 4970U, 120U, 22U, 16U, 12U, 12U, 12U, 48U, 241U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1992U, 1988U, 1984U, 526U, 527U, 529U}, {196U, 4980U, 124U, 22U, 16U, 12U, 12U, 12U, 48U, 242U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 1996U, 1992U, 1988U, 525U, 526U, 527U}, {198U, 4990U, 127U, 22U, 16U, 12U, 12U, 12U, 48U, 243U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 0U, 0U, 15U, 15U, 211U, 0U, 255U, 2000U, 1996U, 1992U, 524U, 525U, 526U}, {200U, 5000U, 130U, 22U, 16U, 12U, 12U, 12U, 48U, 244U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2004U, 2000U, 1996U, 523U, 524U, 525U}, {202U, 5010U, 134U, 22U, 16U, 12U, 12U, 12U, 48U, 245U, 1U, 15U, 0U, 15U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2008U, 2004U, 2000U, 522U, 523U, 524U}, {204U, 5020U, 137U, 22U, 16U, 12U, 12U, 12U, 48U, 246U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2012U, 2008U, 2004U, 521U, 522U, 523U}, {206U, 5030U, 140U, 22U, 16U, 12U, 12U, 12U, 48U, 247U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2016U, 2012U, 2008U, 520U, 521U, 522U}, {208U, 5040U, 144U, 22U, 16U, 12U, 12U, 12U, 48U, 248U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2020U, 2016U, 2012U, 519U, 520U, 521U}, {210U, 5050U, 147U, 22U, 16U, 12U, 12U, 12U, 48U, 249U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2024U, 2020U, 2016U, 518U, 519U, 520U}, {212U, 5060U, 150U, 22U, 16U, 12U, 12U, 12U, 48U, 250U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2028U, 2024U, 2020U, 517U, 518U, 519U}, {214U, 5070U, 154U, 22U, 16U, 12U, 12U, 12U, 48U, 251U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2032U, 2028U, 2024U, 516U, 517U, 518U}, {216U, 5080U, 157U, 22U, 16U, 12U, 12U, 12U, 48U, 252U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2036U, 2032U, 2028U, 515U, 516U, 517U}, {218U, 5090U, 160U, 22U, 16U, 12U, 12U, 12U, 48U, 253U, 1U, 14U, 0U, 14U, 0U, 238U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 0U, 0U, 15U, 15U, 179U, 0U, 255U, 2040U, 2036U, 2032U, 514U, 515U, 516U}, {220U, 5100U, 164U, 22U, 16U, 12U, 12U, 12U, 48U, 254U, 1U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2044U, 2040U, 2036U, 513U, 514U, 515U}, {222U, 5110U, 167U, 22U, 16U, 12U, 12U, 12U, 48U, 255U, 1U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2048U, 2044U, 2040U, 512U, 513U, 514U}, {224U, 5120U, 170U, 22U, 16U, 12U, 12U, 12U, 48U, 0U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2052U, 2048U, 2044U, 511U, 512U, 513U}, {226U, 5130U, 174U, 22U, 16U, 12U, 12U, 12U, 48U, 1U, 2U, 13U, 0U, 13U, 0U, 221U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 0U, 0U, 15U, 15U, 163U, 0U, 252U, 2056U, 2052U, 2048U, 510U, 511U, 512U}, {228U, 5140U, 177U, 22U, 16U, 12U, 12U, 12U, 48U, 2U, 2U, 13U, 0U, 13U, 0U, 221U, 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2U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 2308U, 2304U, 2300U, 454U, 455U, 456U}, {153U, 5765U, 129U, 23U, 32U, 20U, 8U, 8U, 48U, 129U, 4U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 2310U, 2306U, 2302U, 454U, 455U, 456U}, {154U, 5770U, 131U, 23U, 16U, 12U, 12U, 12U, 48U, 65U, 2U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 2312U, 2308U, 2304U, 454U, 454U, 455U}, {155U, 5775U, 133U, 23U, 32U, 20U, 8U, 8U, 48U, 131U, 4U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 2314U, 2310U, 2306U, 453U, 454U, 455U}, {156U, 5780U, 134U, 23U, 16U, 12U, 12U, 12U, 48U, 66U, 2U, 6U, 0U, 6U, 0U, 102U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 2316U, 2312U, 2308U, 453U, 454U, 454U}, {157U, 5785U, 136U, 23U, 32U, 20U, 8U, 8U, 48U, 133U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 2318U, 2314U, 2310U, 452U, 453U, 454U}, {158U, 5790U, 138U, 23U, 16U, 12U, 12U, 12U, 48U, 67U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 2320U, 2316U, 2312U, 452U, 453U, 454U}, {159U, 5795U, 139U, 23U, 32U, 20U, 8U, 8U, 48U, 135U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 0U, 0U, 8U, 2U, 19U, 0U, 0U, 2322U, 2318U, 2314U, 452U, 452U, 453U}, {160U, 5800U, 141U, 23U, 16U, 12U, 12U, 12U, 48U, 68U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 8U, 1U, 3U, 0U, 0U, 0U, 0U, 8U, 1U, 3U, 0U, 0U, 2324U, 2320U, 2316U, 451U, 452U, 453U}, {161U, 5805U, 143U, 23U, 32U, 20U, 8U, 8U, 48U, 137U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2326U, 2322U, 2318U, 451U, 452U, 452U}, {162U, 5810U, 144U, 23U, 16U, 12U, 12U, 12U, 48U, 69U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2328U, 2324U, 2320U, 450U, 451U, 452U}, {163U, 5815U, 146U, 23U, 32U, 20U, 8U, 8U, 48U, 139U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2330U, 2326U, 2322U, 450U, 451U, 452U}, {164U, 5820U, 148U, 23U, 16U, 12U, 12U, 12U, 48U, 70U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2332U, 2328U, 2324U, 450U, 450U, 451U}, {165U, 5825U, 149U, 23U, 32U, 20U, 8U, 8U, 48U, 141U, 4U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2334U, 2330U, 2326U, 449U, 450U, 451U}, {166U, 5830U, 151U, 23U, 16U, 12U, 12U, 12U, 48U, 71U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2336U, 2332U, 2328U, 449U, 450U, 450U}, {168U, 5840U, 154U, 23U, 16U, 12U, 12U, 12U, 48U, 72U, 2U, 5U, 0U, 5U, 0U, 85U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2340U, 2336U, 2332U, 448U, 449U, 450U}, {170U, 5850U, 158U, 23U, 16U, 12U, 12U, 12U, 48U, 73U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2344U, 2340U, 2336U, 447U, 448U, 449U}, {172U, 5860U, 161U, 23U, 16U, 12U, 12U, 12U, 48U, 74U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2348U, 2344U, 2340U, 447U, 447U, 448U}, {174U, 5870U, 164U, 23U, 16U, 12U, 12U, 12U, 48U, 75U, 2U, 4U, 0U, 4U, 0U, 68U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2352U, 2348U, 2344U, 446U, 447U, 447U}, {176U, 5880U, 168U, 23U, 16U, 12U, 12U, 12U, 48U, 76U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2356U, 2352U, 2348U, 445U, 446U, 447U}, {178U, 5890U, 171U, 23U, 16U, 12U, 12U, 12U, 48U, 77U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2360U, 2356U, 2352U, 444U, 445U, 446U}, {180U, 5900U, 174U, 23U, 16U, 12U, 12U, 12U, 48U, 78U, 2U, 3U, 0U, 3U, 0U, 51U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 0U, 0U, 6U, 1U, 3U, 0U, 0U, 2364U, 2360U, 2356U, 444U, 444U, 445U}, {1U, 2412U, 72U, 22U, 48U, 27U, 10U, 10U, 48U, 108U, 9U, 15U, 10U, 0U, 10U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 969U, 965U, 961U, 1082U, 1087U, 1091U}, {2U, 2417U, 75U, 22U, 48U, 27U, 10U, 10U, 48U, 113U, 9U, 15U, 10U, 0U, 10U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 971U, 967U, 963U, 1080U, 1085U, 1089U}, {3U, 2422U, 78U, 22U, 48U, 27U, 10U, 10U, 48U, 118U, 9U, 15U, 9U, 0U, 9U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 973U, 969U, 965U, 1078U, 1082U, 1087U}, {4U, 2427U, 82U, 22U, 48U, 27U, 10U, 10U, 48U, 123U, 9U, 15U, 9U, 0U, 9U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 975U, 971U, 967U, 1076U, 1080U, 1085U}, {5U, 2432U, 85U, 22U, 48U, 27U, 10U, 10U, 48U, 128U, 9U, 15U, 8U, 0U, 8U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 977U, 973U, 969U, 1073U, 1078U, 1082U}, {6U, 2437U, 88U, 22U, 48U, 27U, 10U, 10U, 48U, 133U, 9U, 15U, 8U, 0U, 8U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 979U, 975U, 971U, 1071U, 1076U, 1080U}, {7U, 2442U, 92U, 22U, 48U, 27U, 10U, 10U, 48U, 138U, 9U, 15U, 7U, 0U, 7U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 981U, 977U, 973U, 1069U, 1073U, 1078U}, {8U, 2447U, 95U, 22U, 48U, 27U, 10U, 10U, 48U, 143U, 9U, 15U, 7U, 0U, 7U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 983U, 979U, 975U, 1067U, 1071U, 1076U}, {9U, 2452U, 98U, 22U, 48U, 27U, 10U, 10U, 48U, 148U, 9U, 15U, 7U, 0U, 7U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 985U, 981U, 977U, 1065U, 1069U, 1073U}, {10U, 2457U, 102U, 22U, 48U, 27U, 10U, 10U, 48U, 153U, 9U, 15U, 6U, 0U, 6U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 987U, 983U, 979U, 1063U, 1067U, 1071U}, {11U, 2462U, 105U, 22U, 48U, 27U, 10U, 10U, 48U, 158U, 9U, 15U, 6U, 0U, 6U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 989U, 985U, 981U, 1060U, 1065U, 1069U}, {12U, 2467U, 108U, 22U, 48U, 27U, 10U, 10U, 48U, 163U, 9U, 15U, 5U, 0U, 5U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 991U, 987U, 983U, 1058U, 1063U, 1067U}, {13U, 2472U, 112U, 22U, 48U, 27U, 10U, 10U, 48U, 168U, 9U, 15U, 5U, 0U, 5U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 97U, 115U, 0U, 0U, 0U, 240U, 0U, 993U, 989U, 985U, 1056U, 1060U, 1065U}, {14U, 2484U, 120U, 22U, 48U, 27U, 10U, 10U, 48U, 180U, 9U, 15U, 4U, 0U, 4U, 0U, 97U, 115U, 0U, 0U, 0U, 224U, 0U, 97U, 115U, 0U, 0U, 0U, 224U, 0U, 998U, 994U, 990U, 1051U, 1055U, 1060U}}; static struct radio_regs regs_2055[226U] = { {2U, 128U, 128U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 39U, 39U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 39U, 39U, 0U, 0U}, {7U, 127U, 127U, 1U, 1U}, {8U, 7U, 7U, 1U, 1U}, {9U, 127U, 127U, 1U, 1U}, {10U, 7U, 7U, 1U, 1U}, {11U, 21U, 21U, 0U, 0U}, {12U, 21U, 21U, 0U, 0U}, {13U, 79U, 79U, 1U, 1U}, {14U, 5U, 5U, 1U, 1U}, {15U, 79U, 79U, 1U, 1U}, {16U, 5U, 5U, 1U, 1U}, {17U, 208U, 208U, 0U, 0U}, {18U, 2U, 2U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 64U, 64U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 192U, 192U, 0U, 0U}, {30U, 255U, 255U, 0U, 0U}, {31U, 192U, 192U, 0U, 0U}, {32U, 255U, 255U, 0U, 0U}, {33U, 192U, 192U, 0U, 0U}, {34U, 0U, 0U, 0U, 0U}, {35U, 44U, 44U, 0U, 0U}, {36U, 0U, 0U, 0U, 0U}, {37U, 0U, 0U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 0U, 0U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 0U, 0U, 0U, 0U}, {42U, 0U, 0U, 0U, 0U}, {43U, 0U, 0U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 164U, 164U, 0U, 0U}, {46U, 56U, 56U, 0U, 0U}, {47U, 0U, 0U, 0U, 0U}, {48U, 4U, 4U, 1U, 1U}, {49U, 0U, 0U, 0U, 0U}, {50U, 10U, 10U, 0U, 0U}, {51U, 135U, 135U, 0U, 0U}, {52U, 9U, 9U, 0U, 0U}, {53U, 112U, 112U, 0U, 0U}, {54U, 17U, 17U, 0U, 0U}, {55U, 24U, 24U, 1U, 1U}, {56U, 6U, 6U, 0U, 0U}, {57U, 4U, 4U, 1U, 1U}, {58U, 6U, 6U, 0U, 0U}, {59U, 158U, 158U, 0U, 0U}, {60U, 9U, 9U, 0U, 0U}, {61U, 200U, 200U, 1U, 1U}, {62U, 136U, 136U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 0U, 0U, 0U, 0U}, {66U, 1U, 1U, 0U, 0U}, {67U, 2U, 2U, 0U, 0U}, {68U, 150U, 150U, 0U, 0U}, {69U, 62U, 62U, 0U, 0U}, {70U, 62U, 62U, 0U, 0U}, {71U, 19U, 19U, 0U, 0U}, {72U, 2U, 2U, 0U, 0U}, {73U, 21U, 21U, 0U, 0U}, {74U, 7U, 7U, 0U, 0U}, {75U, 0U, 0U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 0U, 0U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 0U, 0U, 0U, 0U}, {80U, 8U, 8U, 0U, 0U}, {81U, 8U, 8U, 0U, 0U}, {82U, 6U, 6U, 0U, 0U}, {83U, 132U, 132U, 1U, 1U}, {84U, 195U, 195U, 0U, 0U}, {85U, 143U, 143U, 0U, 0U}, {86U, 255U, 255U, 0U, 0U}, {87U, 255U, 255U, 0U, 0U}, {88U, 136U, 136U, 0U, 0U}, {89U, 136U, 136U, 0U, 0U}, {90U, 0U, 0U, 0U, 0U}, {91U, 204U, 204U, 0U, 0U}, {92U, 6U, 6U, 0U, 0U}, {93U, 128U, 128U, 0U, 0U}, {94U, 128U, 128U, 0U, 0U}, {95U, 248U, 248U, 0U, 0U}, {96U, 136U, 136U, 0U, 0U}, {97U, 136U, 136U, 0U, 0U}, {98U, 136U, 8U, 1U, 1U}, {99U, 136U, 136U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 1U, 1U, 1U, 1U}, {102U, 138U, 138U, 0U, 0U}, {103U, 8U, 8U, 0U, 0U}, {104U, 131U, 131U, 0U, 0U}, {105U, 6U, 6U, 0U, 0U}, {106U, 160U, 160U, 0U, 0U}, {107U, 10U, 10U, 0U, 0U}, {108U, 135U, 135U, 1U, 1U}, {109U, 42U, 42U, 0U, 0U}, {110U, 42U, 42U, 0U, 0U}, {111U, 42U, 42U, 0U, 0U}, {112U, 42U, 42U, 0U, 0U}, {113U, 24U, 24U, 0U, 0U}, {114U, 106U, 106U, 1U, 1U}, {115U, 171U, 171U, 1U, 1U}, {116U, 19U, 19U, 1U, 1U}, {117U, 193U, 193U, 1U, 1U}, {118U, 170U, 170U, 1U, 1U}, {119U, 135U, 135U, 1U, 1U}, {120U, 0U, 0U, 0U, 0U}, {121U, 6U, 6U, 0U, 0U}, {122U, 7U, 7U, 0U, 0U}, {123U, 7U, 7U, 0U, 0U}, {124U, 21U, 21U, 0U, 0U}, {125U, 85U, 85U, 0U, 0U}, {126U, 151U, 151U, 1U, 1U}, {127U, 8U, 8U, 0U, 0U}, {128U, 20U, 20U, 1U, 1U}, {129U, 51U, 51U, 0U, 0U}, {130U, 136U, 136U, 0U, 0U}, {131U, 6U, 6U, 0U, 0U}, {132U, 3U, 3U, 1U, 1U}, {133U, 10U, 10U, 0U, 0U}, {134U, 3U, 3U, 1U, 1U}, {135U, 42U, 42U, 0U, 0U}, {136U, 164U, 164U, 0U, 0U}, {137U, 24U, 24U, 0U, 0U}, {138U, 40U, 40U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 74U, 74U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 248U, 248U, 0U, 0U}, {143U, 136U, 136U, 0U, 0U}, {144U, 136U, 136U, 0U, 0U}, {145U, 136U, 8U, 1U, 1U}, {146U, 136U, 136U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 1U, 1U, 1U, 1U}, {149U, 138U, 138U, 0U, 0U}, {150U, 8U, 8U, 0U, 0U}, {151U, 131U, 131U, 0U, 0U}, {152U, 6U, 6U, 0U, 0U}, {153U, 160U, 160U, 0U, 0U}, {154U, 10U, 10U, 0U, 0U}, {155U, 135U, 135U, 1U, 1U}, {156U, 42U, 42U, 0U, 0U}, {157U, 42U, 42U, 0U, 0U}, {158U, 42U, 42U, 0U, 0U}, {159U, 42U, 42U, 0U, 0U}, {160U, 24U, 24U, 0U, 0U}, {161U, 106U, 106U, 1U, 1U}, {162U, 171U, 171U, 1U, 1U}, {163U, 19U, 19U, 1U, 1U}, {164U, 193U, 193U, 1U, 1U}, {165U, 170U, 170U, 1U, 1U}, {166U, 135U, 135U, 1U, 1U}, {167U, 0U, 0U, 0U, 0U}, {168U, 6U, 6U, 0U, 0U}, {169U, 7U, 7U, 0U, 0U}, {170U, 7U, 7U, 0U, 0U}, {171U, 21U, 21U, 0U, 0U}, {172U, 85U, 85U, 0U, 0U}, {173U, 151U, 151U, 1U, 1U}, {174U, 8U, 8U, 0U, 0U}, {175U, 20U, 20U, 1U, 1U}, {176U, 51U, 51U, 0U, 0U}, {177U, 136U, 136U, 0U, 0U}, {178U, 6U, 6U, 0U, 0U}, {179U, 3U, 3U, 1U, 1U}, {180U, 10U, 10U, 0U, 0U}, {181U, 3U, 3U, 1U, 1U}, {182U, 42U, 42U, 0U, 0U}, {183U, 164U, 164U, 0U, 0U}, {184U, 24U, 24U, 0U, 0U}, {185U, 40U, 40U, 0U, 0U}, {186U, 0U, 0U, 0U, 0U}, {187U, 74U, 74U, 0U, 0U}, {188U, 0U, 0U, 0U, 0U}, {189U, 113U, 113U, 0U, 0U}, {190U, 114U, 114U, 0U, 0U}, {191U, 115U, 115U, 0U, 0U}, {192U, 116U, 116U, 0U, 0U}, {193U, 117U, 117U, 0U, 0U}, {194U, 118U, 118U, 0U, 0U}, {195U, 119U, 119U, 0U, 0U}, {196U, 120U, 120U, 0U, 0U}, {197U, 121U, 121U, 0U, 0U}, {198U, 122U, 122U, 0U, 0U}, {199U, 0U, 0U, 0U, 0U}, {200U, 0U, 0U, 0U, 0U}, {201U, 0U, 0U, 0U, 0U}, {202U, 0U, 0U, 0U, 0U}, {203U, 0U, 0U, 0U, 0U}, {204U, 0U, 0U, 0U, 0U}, {205U, 0U, 0U, 0U, 0U}, {206U, 6U, 6U, 0U, 0U}, {207U, 0U, 0U, 0U, 0U}, {208U, 0U, 0U, 0U, 0U}, {209U, 24U, 24U, 0U, 0U}, {210U, 136U, 136U, 0U, 0U}, {211U, 0U, 0U, 0U, 0U}, {212U, 0U, 0U, 0U, 0U}, {213U, 0U, 0U, 0U, 0U}, {214U, 0U, 0U, 0U, 0U}, {215U, 0U, 0U, 0U, 0U}, {216U, 0U, 0U, 0U, 0U}, {217U, 0U, 0U, 0U, 0U}, {218U, 6U, 6U, 0U, 0U}, {219U, 0U, 0U, 0U, 0U}, {220U, 0U, 0U, 0U, 0U}, {221U, 24U, 24U, 0U, 0U}, {222U, 136U, 136U, 0U, 0U}, {223U, 0U, 0U, 0U, 0U}, {224U, 0U, 0U, 0U, 0U}, {225U, 0U, 0U, 0U, 0U}, {226U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_SYN_2056[182U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 1U, 1U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 96U, 96U, 0U, 0U}, {35U, 6U, 6U, 0U, 0U}, {36U, 12U, 12U, 0U, 0U}, {37U, 0U, 0U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 0U, 0U, 0U, 0U}, {40U, 1U, 1U, 0U, 0U}, {41U, 0U, 0U, 0U, 0U}, {42U, 0U, 0U, 0U, 0U}, {43U, 0U, 0U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 13U, 13U, 0U, 0U}, {47U, 31U, 31U, 0U, 0U}, {48U, 21U, 21U, 0U, 0U}, {49U, 15U, 15U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 0U, 0U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 0U, 0U, 0U, 0U}, {56U, 0U, 0U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 0U, 0U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 19U, 19U, 0U, 0U}, {61U, 15U, 15U, 0U, 0U}, {62U, 24U, 24U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 32U, 32U, 0U, 0U}, {66U, 32U, 32U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 119U, 119U, 0U, 0U}, {69U, 7U, 7U, 0U, 0U}, {70U, 1U, 1U, 0U, 0U}, {71U, 4U, 4U, 0U, 0U}, {72U, 15U, 15U, 0U, 0U}, {73U, 48U, 48U, 0U, 0U}, {74U, 50U, 50U, 0U, 0U}, {75U, 13U, 13U, 0U, 0U}, {76U, 13U, 13U, 0U, 0U}, {77U, 4U, 4U, 0U, 0U}, {78U, 6U, 6U, 0U, 0U}, {79U, 1U, 1U, 0U, 0U}, {80U, 28U, 28U, 0U, 0U}, {81U, 2U, 2U, 0U, 0U}, {82U, 2U, 2U, 0U, 0U}, {83U, 247U, 247U, 1U, 1U}, {84U, 180U, 180U, 0U, 0U}, {85U, 210U, 210U, 0U, 0U}, {86U, 0U, 0U, 0U, 0U}, {87U, 0U, 0U, 0U, 0U}, {88U, 4U, 4U, 0U, 0U}, {89U, 150U, 150U, 0U, 0U}, {90U, 62U, 62U, 0U, 0U}, {91U, 62U, 62U, 0U, 0U}, {92U, 19U, 19U, 0U, 0U}, {93U, 2U, 2U, 0U, 0U}, {94U, 0U, 0U, 0U, 0U}, {95U, 7U, 7U, 0U, 0U}, {96U, 7U, 7U, 1U, 1U}, {97U, 8U, 8U, 0U, 0U}, {98U, 3U, 3U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 64U, 64U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 1U, 1U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 96U, 96U, 0U, 0U}, {113U, 102U, 102U, 0U, 0U}, {114U, 12U, 12U, 0U, 0U}, {115U, 102U, 102U, 0U, 0U}, {116U, 143U, 143U, 1U, 1U}, {117U, 0U, 0U, 0U, 0U}, {118U, 204U, 204U, 0U, 0U}, {119U, 1U, 1U, 0U, 0U}, {120U, 102U, 102U, 0U, 0U}, {121U, 102U, 102U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 255U, 255U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {149U, 0U, 0U, 0U, 0U}, {150U, 0U, 0U, 0U, 0U}, {151U, 0U, 0U, 0U, 0U}, {152U, 0U, 0U, 0U, 0U}, {153U, 0U, 0U, 0U, 0U}, {154U, 0U, 0U, 0U, 0U}, {155U, 0U, 0U, 0U, 0U}, {156U, 0U, 0U, 0U, 0U}, {157U, 0U, 0U, 0U, 0U}, {158U, 0U, 0U, 0U, 0U}, {159U, 6U, 6U, 0U, 0U}, {160U, 102U, 102U, 0U, 0U}, {161U, 102U, 102U, 0U, 0U}, {162U, 102U, 102U, 0U, 0U}, {163U, 102U, 102U, 0U, 0U}, {164U, 102U, 102U, 0U, 0U}, {165U, 102U, 102U, 0U, 0U}, {166U, 102U, 102U, 0U, 0U}, {167U, 102U, 102U, 0U, 0U}, {168U, 102U, 102U, 0U, 0U}, {169U, 102U, 102U, 0U, 0U}, {170U, 102U, 102U, 0U, 0U}, {171U, 102U, 102U, 0U, 0U}, {172U, 102U, 102U, 0U, 0U}, {173U, 102U, 102U, 0U, 0U}, {174U, 102U, 102U, 0U, 0U}, {175U, 102U, 102U, 0U, 0U}, {176U, 102U, 102U, 0U, 0U}, {177U, 102U, 102U, 0U, 0U}, {178U, 102U, 102U, 0U, 0U}, {179U, 10U, 10U, 0U, 0U}, {180U, 0U, 0U, 0U, 0U}, {181U, 0U, 0U, 0U, 0U}, {182U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_TX_2056[146U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 136U, 136U, 0U, 0U}, {34U, 136U, 136U, 0U, 0U}, {35U, 136U, 136U, 0U, 0U}, {36U, 136U, 136U, 0U, 0U}, {37U, 12U, 12U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 3U, 3U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 3U, 3U, 0U, 0U}, {42U, 55U, 55U, 0U, 0U}, {43U, 3U, 3U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 1U, 1U, 0U, 0U}, {47U, 1U, 1U, 0U, 0U}, {48U, 0U, 0U, 0U, 0U}, {49U, 0U, 0U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 17U, 17U, 0U, 0U}, {52U, 17U, 17U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 3U, 3U, 0U, 0U}, {56U, 15U, 15U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 45U, 45U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 110U, 110U, 0U, 0U}, {61U, 240U, 240U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 3U, 3U, 0U, 0U}, {66U, 3U, 3U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 30U, 30U, 0U, 0U}, {69U, 0U, 0U, 0U, 0U}, {70U, 110U, 110U, 0U, 0U}, {71U, 240U, 240U, 1U, 1U}, {72U, 0U, 0U, 0U, 0U}, {73U, 2U, 2U, 0U, 0U}, {74U, 255U, 255U, 1U, 1U}, {75U, 12U, 12U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 56U, 56U, 0U, 0U}, {78U, 112U, 112U, 1U, 1U}, {79U, 2U, 2U, 0U, 0U}, {80U, 136U, 136U, 0U, 0U}, {81U, 12U, 12U, 0U, 0U}, {82U, 0U, 0U, 0U, 0U}, {83U, 8U, 8U, 0U, 0U}, {84U, 112U, 112U, 1U, 1U}, {85U, 2U, 2U, 0U, 0U}, {86U, 255U, 255U, 1U, 1U}, {87U, 0U, 0U, 0U, 0U}, {88U, 131U, 131U, 0U, 0U}, {89U, 119U, 119U, 1U, 1U}, {90U, 0U, 0U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 136U, 136U, 0U, 0U}, {93U, 0U, 0U, 0U, 0U}, {94U, 8U, 8U, 0U, 0U}, {95U, 119U, 119U, 1U, 1U}, {96U, 1U, 1U, 0U, 0U}, {97U, 0U, 0U, 0U, 0U}, {98U, 7U, 7U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 7U, 7U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 116U, 116U, 1U, 1U}, {104U, 0U, 0U, 0U, 0U}, {105U, 10U, 10U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 2U, 2U, 0U, 0U}, {114U, 0U, 0U, 0U, 0U}, {115U, 0U, 0U, 0U, 0U}, {116U, 14U, 14U, 0U, 0U}, {117U, 14U, 14U, 0U, 0U}, {118U, 14U, 14U, 0U, 0U}, {119U, 19U, 19U, 0U, 0U}, {120U, 19U, 19U, 0U, 0U}, {121U, 27U, 27U, 0U, 0U}, {122U, 27U, 27U, 0U, 0U}, {123U, 85U, 85U, 0U, 0U}, {124U, 91U, 91U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_RX_2056[148U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 3U, 3U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 0U, 0U, 0U, 0U}, {35U, 144U, 144U, 0U, 0U}, {36U, 85U, 85U, 0U, 0U}, {37U, 21U, 21U, 0U, 0U}, {38U, 5U, 5U, 0U, 0U}, {39U, 21U, 21U, 0U, 0U}, {40U, 5U, 5U, 0U, 0U}, {41U, 32U, 32U, 0U, 0U}, {42U, 17U, 17U, 0U, 0U}, {43U, 144U, 144U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 136U, 136U, 0U, 0U}, {46U, 50U, 50U, 0U, 0U}, {47U, 119U, 119U, 0U, 0U}, {48U, 23U, 23U, 1U, 1U}, {49U, 255U, 255U, 1U, 1U}, {50U, 32U, 32U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 136U, 136U, 0U, 0U}, {53U, 50U, 50U, 0U, 0U}, {54U, 119U, 119U, 0U, 0U}, {55U, 23U, 23U, 1U, 1U}, {56U, 240U, 240U, 1U, 1U}, {57U, 32U, 32U, 0U, 0U}, {58U, 8U, 8U, 0U, 0U}, {59U, 153U, 153U, 0U, 0U}, {60U, 0U, 0U, 0U, 0U}, {61U, 68U, 68U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 68U, 68U, 0U, 0U}, {64U, 15U, 15U, 1U, 1U}, {65U, 6U, 6U, 0U, 0U}, {66U, 4U, 4U, 0U, 0U}, {67U, 80U, 80U, 1U, 1U}, {68U, 8U, 8U, 0U, 0U}, {69U, 153U, 153U, 0U, 0U}, {70U, 0U, 0U, 0U, 0U}, {71U, 17U, 17U, 0U, 0U}, {72U, 0U, 0U, 0U, 0U}, {73U, 68U, 68U, 0U, 0U}, {74U, 7U, 7U, 0U, 0U}, {75U, 6U, 6U, 0U, 0U}, {76U, 4U, 4U, 0U, 0U}, {77U, 0U, 0U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 102U, 102U, 0U, 0U}, {80U, 102U, 102U, 0U, 0U}, {81U, 87U, 87U, 0U, 0U}, {82U, 87U, 87U, 0U, 0U}, {83U, 68U, 68U, 0U, 0U}, {84U, 0U, 0U, 0U, 0U}, {85U, 0U, 0U, 0U, 0U}, {86U, 8U, 8U, 0U, 0U}, {87U, 8U, 8U, 0U, 0U}, {88U, 7U, 7U, 0U, 0U}, {89U, 34U, 34U, 0U, 0U}, {90U, 34U, 34U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 35U, 35U, 0U, 0U}, {93U, 7U, 7U, 0U, 0U}, {94U, 85U, 85U, 0U, 0U}, {95U, 35U, 35U, 0U, 0U}, {96U, 65U, 65U, 0U, 0U}, {97U, 1U, 1U, 0U, 0U}, {98U, 10U, 10U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 0U, 0U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 12U, 12U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 0U, 0U, 0U, 0U}, {114U, 34U, 34U, 0U, 0U}, {115U, 34U, 34U, 0U, 0U}, {116U, 2U, 2U, 0U, 0U}, {117U, 10U, 10U, 0U, 0U}, {118U, 1U, 1U, 0U, 0U}, {119U, 34U, 34U, 0U, 0U}, {120U, 48U, 48U, 0U, 0U}, {121U, 0U, 0U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_SYN_2056_A1[182U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 1U, 1U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 96U, 96U, 0U, 0U}, {35U, 6U, 6U, 0U, 0U}, {36U, 12U, 12U, 0U, 0U}, {37U, 0U, 0U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 0U, 0U, 0U, 0U}, {40U, 1U, 1U, 0U, 0U}, {41U, 0U, 0U, 0U, 0U}, {42U, 0U, 0U, 0U, 0U}, {43U, 0U, 0U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 13U, 13U, 0U, 0U}, {47U, 31U, 31U, 0U, 0U}, {48U, 21U, 21U, 0U, 0U}, {49U, 15U, 15U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 0U, 0U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 0U, 0U, 0U, 0U}, {56U, 0U, 0U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 0U, 0U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 19U, 19U, 0U, 0U}, {61U, 15U, 15U, 0U, 0U}, {62U, 24U, 24U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 32U, 32U, 0U, 0U}, {66U, 32U, 32U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 119U, 119U, 0U, 0U}, {69U, 7U, 7U, 0U, 0U}, {70U, 1U, 1U, 0U, 0U}, {71U, 4U, 4U, 0U, 0U}, {72U, 15U, 15U, 0U, 0U}, {73U, 48U, 48U, 0U, 0U}, {74U, 50U, 50U, 0U, 0U}, {75U, 13U, 13U, 0U, 0U}, {76U, 13U, 13U, 0U, 0U}, {77U, 4U, 4U, 0U, 0U}, {78U, 6U, 6U, 0U, 0U}, {79U, 1U, 1U, 0U, 0U}, {80U, 28U, 28U, 0U, 0U}, {81U, 2U, 2U, 0U, 0U}, {82U, 2U, 2U, 0U, 0U}, {83U, 247U, 247U, 1U, 1U}, {84U, 180U, 180U, 0U, 0U}, {85U, 210U, 210U, 0U, 0U}, {86U, 0U, 0U, 0U, 0U}, {87U, 0U, 0U, 0U, 0U}, {88U, 4U, 4U, 0U, 0U}, {89U, 150U, 150U, 0U, 0U}, {90U, 62U, 62U, 0U, 0U}, {91U, 62U, 62U, 0U, 0U}, {92U, 19U, 19U, 0U, 0U}, {93U, 2U, 2U, 0U, 0U}, {94U, 0U, 0U, 0U, 0U}, {95U, 7U, 7U, 0U, 0U}, {96U, 7U, 7U, 1U, 1U}, {97U, 8U, 8U, 0U, 0U}, {98U, 3U, 3U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 64U, 64U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 1U, 1U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 96U, 96U, 0U, 0U}, {113U, 102U, 102U, 0U, 0U}, {114U, 12U, 12U, 0U, 0U}, {115U, 102U, 102U, 0U, 0U}, {116U, 143U, 143U, 1U, 1U}, {117U, 0U, 0U, 0U, 0U}, {118U, 204U, 204U, 0U, 0U}, {119U, 1U, 1U, 0U, 0U}, {120U, 102U, 102U, 0U, 0U}, {121U, 102U, 102U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 255U, 255U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {149U, 0U, 0U, 0U, 0U}, {150U, 0U, 0U, 0U, 0U}, {151U, 0U, 0U, 0U, 0U}, {152U, 0U, 0U, 0U, 0U}, {153U, 0U, 0U, 0U, 0U}, {154U, 0U, 0U, 0U, 0U}, {155U, 0U, 0U, 0U, 0U}, {156U, 0U, 0U, 0U, 0U}, {157U, 0U, 0U, 0U, 0U}, {158U, 0U, 0U, 0U, 0U}, {159U, 6U, 6U, 0U, 0U}, {160U, 102U, 102U, 0U, 0U}, {161U, 102U, 102U, 0U, 0U}, {162U, 102U, 102U, 0U, 0U}, {163U, 102U, 102U, 0U, 0U}, {164U, 102U, 102U, 0U, 0U}, {165U, 102U, 102U, 0U, 0U}, {166U, 102U, 102U, 0U, 0U}, {167U, 102U, 102U, 0U, 0U}, {168U, 102U, 102U, 0U, 0U}, {169U, 102U, 102U, 0U, 0U}, {170U, 102U, 102U, 0U, 0U}, {171U, 102U, 102U, 0U, 0U}, {172U, 102U, 102U, 0U, 0U}, {173U, 102U, 102U, 0U, 0U}, {174U, 102U, 102U, 0U, 0U}, {175U, 102U, 102U, 0U, 0U}, {176U, 102U, 102U, 0U, 0U}, {177U, 102U, 102U, 0U, 0U}, {178U, 102U, 102U, 0U, 0U}, {179U, 10U, 10U, 0U, 0U}, {180U, 0U, 0U, 0U, 0U}, {181U, 0U, 0U, 0U, 0U}, {182U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_TX_2056_A1[146U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 136U, 136U, 0U, 0U}, {34U, 136U, 136U, 0U, 0U}, {35U, 136U, 136U, 0U, 0U}, {36U, 136U, 136U, 0U, 0U}, {37U, 12U, 12U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 3U, 3U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 3U, 3U, 0U, 0U}, {42U, 55U, 55U, 0U, 0U}, {43U, 3U, 3U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 1U, 1U, 0U, 0U}, {47U, 1U, 1U, 0U, 0U}, {48U, 0U, 0U, 0U, 0U}, {49U, 0U, 0U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 17U, 17U, 0U, 0U}, {52U, 17U, 17U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 3U, 3U, 0U, 0U}, {56U, 15U, 15U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 45U, 45U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 110U, 110U, 0U, 0U}, {61U, 240U, 240U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 3U, 3U, 0U, 0U}, {66U, 3U, 3U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 30U, 30U, 0U, 0U}, {69U, 0U, 0U, 0U, 0U}, {70U, 110U, 110U, 0U, 0U}, {71U, 240U, 240U, 1U, 1U}, {72U, 0U, 0U, 0U, 0U}, {73U, 2U, 2U, 0U, 0U}, {74U, 255U, 255U, 1U, 1U}, {75U, 12U, 12U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 56U, 56U, 0U, 0U}, {78U, 112U, 112U, 1U, 1U}, {79U, 2U, 2U, 0U, 0U}, {80U, 136U, 136U, 0U, 0U}, {81U, 12U, 12U, 0U, 0U}, {82U, 0U, 0U, 0U, 0U}, {83U, 8U, 8U, 0U, 0U}, {84U, 112U, 112U, 1U, 1U}, {85U, 2U, 2U, 0U, 0U}, {86U, 255U, 255U, 1U, 1U}, {87U, 0U, 0U, 0U, 0U}, {88U, 131U, 131U, 0U, 0U}, {89U, 119U, 119U, 1U, 1U}, {90U, 0U, 0U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 136U, 136U, 0U, 0U}, {93U, 0U, 0U, 0U, 0U}, {94U, 8U, 8U, 0U, 0U}, {95U, 119U, 119U, 1U, 1U}, {96U, 1U, 1U, 0U, 0U}, {97U, 0U, 0U, 0U, 0U}, {98U, 7U, 7U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 7U, 7U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 114U, 114U, 1U, 1U}, {104U, 0U, 0U, 0U, 0U}, {105U, 10U, 10U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 2U, 2U, 0U, 0U}, {114U, 0U, 0U, 0U, 0U}, {115U, 0U, 0U, 0U, 0U}, {116U, 14U, 14U, 0U, 0U}, {117U, 14U, 14U, 0U, 0U}, {118U, 14U, 14U, 0U, 0U}, {119U, 19U, 19U, 0U, 0U}, {120U, 19U, 19U, 0U, 0U}, {121U, 27U, 27U, 0U, 0U}, {122U, 27U, 27U, 0U, 0U}, {123U, 85U, 85U, 0U, 0U}, {124U, 91U, 91U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_RX_2056_A1[148U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 3U, 3U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 0U, 0U, 0U, 0U}, {35U, 144U, 144U, 0U, 0U}, {36U, 85U, 85U, 0U, 0U}, {37U, 21U, 21U, 0U, 0U}, {38U, 5U, 5U, 0U, 0U}, {39U, 21U, 21U, 0U, 0U}, {40U, 5U, 5U, 0U, 0U}, {41U, 32U, 32U, 0U, 0U}, {42U, 17U, 17U, 0U, 0U}, {43U, 144U, 144U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 136U, 136U, 0U, 0U}, {46U, 50U, 50U, 0U, 0U}, {47U, 119U, 119U, 0U, 0U}, {48U, 23U, 23U, 1U, 1U}, {49U, 255U, 255U, 1U, 1U}, {50U, 32U, 32U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 136U, 136U, 0U, 0U}, {53U, 50U, 50U, 0U, 0U}, {54U, 119U, 119U, 0U, 0U}, {55U, 23U, 23U, 1U, 1U}, {56U, 240U, 240U, 1U, 1U}, {57U, 32U, 32U, 0U, 0U}, {58U, 8U, 8U, 0U, 0U}, {59U, 85U, 85U, 1U, 1U}, {60U, 0U, 0U, 0U, 0U}, {61U, 68U, 68U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 68U, 68U, 0U, 0U}, {64U, 15U, 15U, 1U, 1U}, {65U, 6U, 6U, 0U, 0U}, {66U, 4U, 4U, 0U, 0U}, {67U, 80U, 80U, 1U, 1U}, {68U, 8U, 8U, 0U, 0U}, {69U, 85U, 85U, 1U, 1U}, {70U, 0U, 0U, 0U, 0U}, {71U, 17U, 17U, 0U, 0U}, {72U, 0U, 0U, 0U, 0U}, {73U, 68U, 68U, 0U, 0U}, {74U, 7U, 7U, 0U, 0U}, {75U, 6U, 6U, 0U, 0U}, {76U, 4U, 4U, 0U, 0U}, {77U, 0U, 0U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 38U, 38U, 1U, 1U}, {80U, 38U, 38U, 1U, 1U}, {81U, 15U, 15U, 1U, 1U}, {82U, 15U, 15U, 1U, 1U}, {83U, 68U, 68U, 0U, 0U}, {84U, 0U, 0U, 0U, 0U}, {85U, 0U, 0U, 0U, 0U}, {86U, 8U, 8U, 0U, 0U}, {87U, 8U, 8U, 0U, 0U}, {88U, 7U, 7U, 0U, 0U}, {89U, 34U, 34U, 0U, 0U}, {90U, 34U, 34U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 47U, 47U, 1U, 1U}, {93U, 7U, 7U, 0U, 0U}, {94U, 85U, 85U, 0U, 0U}, {95U, 35U, 35U, 0U, 0U}, {96U, 65U, 65U, 0U, 0U}, {97U, 1U, 1U, 0U, 0U}, {98U, 10U, 10U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 0U, 0U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 12U, 12U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 0U, 0U, 0U, 0U}, {114U, 34U, 34U, 0U, 0U}, {115U, 34U, 34U, 0U, 0U}, {116U, 0U, 0U, 1U, 1U}, {117U, 10U, 10U, 0U, 0U}, {118U, 1U, 1U, 0U, 0U}, {119U, 34U, 34U, 0U, 0U}, {120U, 48U, 48U, 0U, 0U}, {121U, 0U, 0U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_SYN_2056_rev5[182U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 1U, 1U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 96U, 96U, 0U, 0U}, {35U, 6U, 6U, 0U, 0U}, {36U, 12U, 12U, 0U, 0U}, {37U, 0U, 0U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 0U, 0U, 0U, 0U}, {40U, 1U, 1U, 0U, 0U}, {41U, 0U, 0U, 0U, 0U}, {42U, 0U, 0U, 0U, 0U}, {43U, 0U, 0U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 0U, 0U, 0U, 0U}, {47U, 31U, 31U, 0U, 0U}, {48U, 21U, 21U, 0U, 0U}, {49U, 15U, 15U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 0U, 0U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 0U, 0U, 0U, 0U}, {56U, 0U, 0U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 0U, 0U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 19U, 19U, 0U, 0U}, {61U, 15U, 15U, 0U, 0U}, {62U, 24U, 24U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 32U, 32U, 0U, 0U}, {66U, 32U, 32U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 119U, 119U, 0U, 0U}, {69U, 7U, 7U, 0U, 0U}, {70U, 1U, 1U, 0U, 0U}, {71U, 4U, 4U, 0U, 0U}, {72U, 15U, 15U, 0U, 0U}, {73U, 48U, 48U, 0U, 0U}, {74U, 50U, 50U, 0U, 0U}, {75U, 13U, 13U, 0U, 0U}, {76U, 13U, 13U, 0U, 0U}, {77U, 4U, 4U, 0U, 0U}, {78U, 6U, 6U, 0U, 0U}, {79U, 1U, 1U, 0U, 0U}, {80U, 28U, 28U, 0U, 0U}, {81U, 2U, 2U, 0U, 0U}, {82U, 2U, 2U, 0U, 0U}, {83U, 247U, 247U, 1U, 1U}, {84U, 180U, 180U, 0U, 0U}, {85U, 210U, 210U, 0U, 0U}, {86U, 0U, 0U, 0U, 0U}, {87U, 0U, 0U, 0U, 0U}, {88U, 4U, 4U, 0U, 0U}, {89U, 150U, 150U, 0U, 0U}, {90U, 62U, 62U, 0U, 0U}, {91U, 62U, 62U, 0U, 0U}, {92U, 19U, 19U, 0U, 0U}, {93U, 2U, 2U, 0U, 0U}, {94U, 0U, 0U, 0U, 0U}, {95U, 7U, 7U, 0U, 0U}, {96U, 7U, 7U, 1U, 1U}, {97U, 8U, 8U, 0U, 0U}, {98U, 3U, 3U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 64U, 64U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 1U, 1U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 96U, 96U, 0U, 0U}, {113U, 102U, 102U, 0U, 0U}, {114U, 12U, 12U, 0U, 0U}, {115U, 102U, 102U, 0U, 0U}, {116U, 143U, 143U, 1U, 1U}, {117U, 0U, 0U, 0U, 0U}, {118U, 204U, 204U, 0U, 0U}, {119U, 1U, 1U, 0U, 0U}, {120U, 102U, 102U, 0U, 0U}, {121U, 102U, 102U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 255U, 255U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {149U, 0U, 0U, 0U, 0U}, {150U, 0U, 0U, 0U, 0U}, {151U, 0U, 0U, 0U, 0U}, {152U, 0U, 0U, 0U, 0U}, {153U, 0U, 0U, 0U, 0U}, {154U, 0U, 0U, 0U, 0U}, {155U, 0U, 0U, 0U, 0U}, {156U, 0U, 0U, 0U, 0U}, {157U, 0U, 0U, 0U, 0U}, {158U, 0U, 0U, 0U, 0U}, {159U, 6U, 6U, 0U, 0U}, {160U, 102U, 102U, 0U, 0U}, {161U, 102U, 102U, 0U, 0U}, {162U, 102U, 102U, 0U, 0U}, {163U, 102U, 102U, 0U, 0U}, {164U, 102U, 102U, 0U, 0U}, {165U, 102U, 102U, 0U, 0U}, {166U, 102U, 102U, 0U, 0U}, {167U, 102U, 102U, 0U, 0U}, {168U, 102U, 102U, 0U, 0U}, {169U, 102U, 102U, 0U, 0U}, {170U, 102U, 102U, 0U, 0U}, {171U, 102U, 102U, 0U, 0U}, {172U, 102U, 102U, 0U, 0U}, {173U, 102U, 102U, 0U, 0U}, {174U, 102U, 102U, 0U, 0U}, {175U, 102U, 102U, 0U, 0U}, {176U, 102U, 102U, 0U, 0U}, {177U, 102U, 102U, 0U, 0U}, {178U, 102U, 102U, 0U, 0U}, {179U, 10U, 10U, 0U, 0U}, {180U, 0U, 0U, 0U, 0U}, {181U, 0U, 0U, 0U, 0U}, {182U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_TX_2056_rev5[154U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 136U, 136U, 0U, 0U}, {34U, 136U, 136U, 0U, 0U}, {35U, 136U, 136U, 0U, 0U}, {36U, 136U, 136U, 0U, 0U}, {37U, 12U, 12U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 3U, 3U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 3U, 3U, 0U, 0U}, {42U, 55U, 55U, 0U, 0U}, {43U, 3U, 3U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 1U, 1U, 0U, 0U}, {47U, 1U, 1U, 0U, 0U}, {48U, 0U, 0U, 0U, 0U}, {49U, 0U, 0U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 17U, 17U, 0U, 0U}, {52U, 17U, 17U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 3U, 3U, 0U, 0U}, {56U, 15U, 15U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 45U, 45U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 110U, 110U, 0U, 0U}, {61U, 240U, 240U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 3U, 3U, 0U, 0U}, {66U, 3U, 3U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 30U, 30U, 0U, 0U}, {69U, 0U, 0U, 0U, 0U}, {70U, 110U, 110U, 0U, 0U}, {71U, 240U, 240U, 1U, 1U}, {72U, 0U, 0U, 0U, 0U}, {73U, 2U, 2U, 0U, 0U}, {74U, 255U, 255U, 1U, 1U}, {75U, 12U, 12U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 56U, 56U, 0U, 0U}, {78U, 112U, 112U, 1U, 1U}, {79U, 2U, 2U, 0U, 0U}, {80U, 136U, 136U, 0U, 0U}, {81U, 12U, 12U, 0U, 0U}, {82U, 0U, 0U, 0U, 0U}, {83U, 8U, 8U, 0U, 0U}, {84U, 112U, 112U, 1U, 1U}, {85U, 2U, 2U, 0U, 0U}, {86U, 255U, 255U, 1U, 1U}, {87U, 0U, 0U, 0U, 0U}, {88U, 131U, 131U, 0U, 0U}, {89U, 119U, 119U, 1U, 1U}, {90U, 0U, 0U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 136U, 136U, 0U, 0U}, {93U, 0U, 0U, 0U, 0U}, {94U, 8U, 8U, 0U, 0U}, {95U, 119U, 119U, 1U, 1U}, {96U, 1U, 1U, 0U, 0U}, {97U, 0U, 0U, 0U, 0U}, {98U, 7U, 7U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 7U, 7U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 1U, 1U}, {104U, 0U, 0U, 0U, 0U}, {105U, 10U, 10U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 2U, 2U, 0U, 0U}, {114U, 0U, 0U, 0U, 0U}, {115U, 0U, 0U, 0U, 0U}, {116U, 14U, 14U, 0U, 0U}, {117U, 14U, 14U, 0U, 0U}, {118U, 14U, 14U, 0U, 0U}, {119U, 19U, 19U, 0U, 0U}, {120U, 19U, 19U, 0U, 0U}, {121U, 27U, 27U, 0U, 0U}, {122U, 27U, 27U, 0U, 0U}, {123U, 85U, 85U, 0U, 0U}, {124U, 91U, 91U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 112U, 112U, 0U, 0U}, {148U, 112U, 112U, 0U, 0U}, {149U, 113U, 113U, 1U, 1U}, {150U, 113U, 113U, 1U, 1U}, {151U, 114U, 114U, 1U, 1U}, {152U, 115U, 115U, 1U, 1U}, {153U, 116U, 116U, 1U, 1U}, {154U, 117U, 117U, 1U, 1U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_RX_2056_rev5[148U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 3U, 3U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 0U, 0U, 0U, 0U}, {35U, 144U, 144U, 0U, 0U}, {36U, 85U, 85U, 0U, 0U}, {37U, 21U, 21U, 0U, 0U}, {38U, 5U, 5U, 0U, 0U}, {39U, 21U, 21U, 0U, 0U}, {40U, 5U, 5U, 0U, 0U}, {41U, 32U, 32U, 0U, 0U}, {42U, 17U, 17U, 0U, 0U}, {43U, 144U, 144U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 136U, 136U, 0U, 0U}, {46U, 50U, 50U, 0U, 0U}, {47U, 119U, 119U, 0U, 0U}, {48U, 23U, 23U, 1U, 1U}, {49U, 255U, 255U, 1U, 1U}, {50U, 32U, 32U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 136U, 136U, 0U, 0U}, {53U, 50U, 50U, 0U, 0U}, {54U, 119U, 119U, 0U, 0U}, {55U, 23U, 23U, 1U, 1U}, {56U, 240U, 240U, 1U, 1U}, {57U, 32U, 32U, 0U, 0U}, {58U, 8U, 8U, 0U, 0U}, {59U, 85U, 85U, 1U, 1U}, {60U, 0U, 0U, 0U, 0U}, {61U, 136U, 136U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 1U, 1U}, {64U, 7U, 7U, 1U, 1U}, {65U, 6U, 6U, 0U, 0U}, {66U, 4U, 4U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 8U, 8U, 0U, 0U}, {69U, 85U, 85U, 1U, 1U}, {70U, 0U, 0U, 0U, 0U}, {71U, 17U, 17U, 0U, 0U}, {72U, 0U, 0U, 0U, 0U}, {73U, 0U, 0U, 1U, 1U}, {74U, 7U, 7U, 0U, 0U}, {75U, 6U, 6U, 0U, 0U}, {76U, 4U, 4U, 0U, 0U}, {77U, 0U, 0U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 38U, 38U, 1U, 1U}, {80U, 38U, 38U, 1U, 1U}, {81U, 15U, 15U, 1U, 1U}, {82U, 15U, 15U, 1U, 1U}, {83U, 68U, 68U, 0U, 0U}, {84U, 0U, 0U, 0U, 0U}, {85U, 0U, 0U, 0U, 0U}, {86U, 8U, 8U, 0U, 0U}, {87U, 8U, 8U, 0U, 0U}, {88U, 7U, 7U, 0U, 0U}, {89U, 34U, 34U, 0U, 0U}, {90U, 34U, 34U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 4U, 4U, 1U, 1U}, {93U, 7U, 7U, 0U, 0U}, {94U, 85U, 85U, 0U, 0U}, {95U, 35U, 35U, 0U, 0U}, {96U, 65U, 65U, 0U, 0U}, {97U, 1U, 1U, 0U, 0U}, {98U, 10U, 10U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 0U, 0U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 12U, 12U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 0U, 0U, 0U, 0U}, {114U, 34U, 34U, 0U, 0U}, {115U, 34U, 34U, 0U, 0U}, {116U, 0U, 0U, 1U, 1U}, {117U, 10U, 10U, 0U, 0U}, {118U, 1U, 1U, 0U, 0U}, {119U, 34U, 34U, 0U, 0U}, {120U, 48U, 48U, 0U, 0U}, {121U, 0U, 0U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_SYN_2056_rev6[182U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 1U, 1U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 96U, 96U, 0U, 0U}, {35U, 6U, 6U, 0U, 0U}, {36U, 12U, 12U, 0U, 0U}, {37U, 0U, 0U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 0U, 0U, 0U, 0U}, {40U, 1U, 1U, 0U, 0U}, {41U, 0U, 0U, 0U, 0U}, {42U, 0U, 0U, 0U, 0U}, {43U, 0U, 0U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 0U, 0U, 0U, 0U}, {47U, 31U, 31U, 0U, 0U}, {48U, 21U, 21U, 0U, 0U}, {49U, 15U, 15U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 0U, 0U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 0U, 0U, 0U, 0U}, {56U, 0U, 0U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 0U, 0U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 19U, 19U, 0U, 0U}, {61U, 15U, 15U, 0U, 0U}, {62U, 24U, 24U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 32U, 32U, 0U, 0U}, {66U, 32U, 32U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 119U, 119U, 0U, 0U}, {69U, 7U, 7U, 0U, 0U}, {70U, 1U, 1U, 0U, 0U}, {71U, 4U, 4U, 0U, 0U}, {72U, 15U, 15U, 0U, 0U}, {73U, 48U, 48U, 0U, 0U}, {74U, 50U, 50U, 0U, 0U}, {75U, 13U, 13U, 0U, 0U}, {76U, 13U, 13U, 0U, 0U}, {77U, 4U, 4U, 0U, 0U}, {78U, 6U, 6U, 0U, 0U}, {79U, 1U, 1U, 0U, 0U}, {80U, 28U, 28U, 0U, 0U}, {81U, 2U, 2U, 0U, 0U}, {82U, 2U, 2U, 0U, 0U}, {83U, 247U, 247U, 1U, 1U}, {84U, 180U, 180U, 0U, 0U}, {85U, 210U, 210U, 0U, 0U}, {86U, 0U, 0U, 0U, 0U}, {87U, 0U, 0U, 0U, 0U}, {88U, 4U, 4U, 0U, 0U}, {89U, 150U, 150U, 0U, 0U}, {90U, 62U, 62U, 0U, 0U}, {91U, 62U, 62U, 0U, 0U}, {92U, 19U, 19U, 0U, 0U}, {93U, 2U, 2U, 0U, 0U}, {94U, 0U, 0U, 0U, 0U}, {95U, 7U, 7U, 0U, 0U}, {96U, 7U, 7U, 1U, 1U}, {97U, 8U, 8U, 0U, 0U}, {98U, 3U, 3U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 64U, 64U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 1U, 1U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 96U, 96U, 0U, 0U}, {113U, 102U, 102U, 0U, 0U}, {114U, 12U, 12U, 0U, 0U}, {115U, 102U, 102U, 0U, 0U}, {116U, 143U, 143U, 1U, 1U}, {117U, 0U, 0U, 0U, 0U}, {118U, 204U, 204U, 0U, 0U}, {119U, 1U, 1U, 0U, 0U}, {120U, 102U, 102U, 0U, 0U}, {121U, 102U, 102U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 255U, 255U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {149U, 0U, 0U, 0U, 0U}, {150U, 0U, 0U, 0U, 0U}, {151U, 0U, 0U, 0U, 0U}, {152U, 0U, 0U, 0U, 0U}, {153U, 0U, 0U, 0U, 0U}, {154U, 0U, 0U, 0U, 0U}, {155U, 0U, 0U, 0U, 0U}, {156U, 0U, 0U, 0U, 0U}, {157U, 0U, 0U, 0U, 0U}, {158U, 0U, 0U, 0U, 0U}, {159U, 6U, 6U, 0U, 0U}, {160U, 102U, 102U, 0U, 0U}, {161U, 102U, 102U, 0U, 0U}, {162U, 102U, 102U, 0U, 0U}, {163U, 102U, 102U, 0U, 0U}, {164U, 102U, 102U, 0U, 0U}, {165U, 102U, 102U, 0U, 0U}, {166U, 102U, 102U, 0U, 0U}, {167U, 102U, 102U, 0U, 0U}, {168U, 102U, 102U, 0U, 0U}, {169U, 102U, 102U, 0U, 0U}, {170U, 102U, 102U, 0U, 0U}, {171U, 102U, 102U, 0U, 0U}, {172U, 102U, 102U, 0U, 0U}, {173U, 102U, 102U, 0U, 0U}, {174U, 102U, 102U, 0U, 0U}, {175U, 102U, 102U, 0U, 0U}, {176U, 102U, 102U, 0U, 0U}, {177U, 102U, 102U, 0U, 0U}, {178U, 102U, 102U, 0U, 0U}, {179U, 10U, 10U, 0U, 0U}, {180U, 0U, 0U, 0U, 0U}, {181U, 0U, 0U, 0U, 0U}, {182U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_TX_2056_rev6[154U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 136U, 136U, 0U, 0U}, {34U, 136U, 136U, 0U, 0U}, {35U, 136U, 136U, 0U, 0U}, {36U, 136U, 136U, 0U, 0U}, {37U, 12U, 12U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 3U, 3U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 3U, 3U, 0U, 0U}, {42U, 55U, 55U, 0U, 0U}, {43U, 3U, 3U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 1U, 1U, 0U, 0U}, {47U, 1U, 1U, 0U, 0U}, {48U, 0U, 0U, 0U, 0U}, {49U, 0U, 0U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 17U, 17U, 0U, 0U}, {52U, 238U, 238U, 1U, 1U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 3U, 3U, 0U, 0U}, {56U, 80U, 80U, 1U, 1U}, {57U, 0U, 0U, 0U, 0U}, {58U, 80U, 80U, 1U, 1U}, {59U, 0U, 0U, 0U, 0U}, {60U, 110U, 110U, 0U, 0U}, {61U, 240U, 240U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 3U, 3U, 0U, 0U}, {66U, 3U, 3U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 30U, 30U, 0U, 0U}, {69U, 0U, 0U, 0U, 0U}, {70U, 110U, 110U, 0U, 0U}, {71U, 240U, 240U, 1U, 1U}, {72U, 0U, 0U, 0U, 0U}, {73U, 2U, 2U, 0U, 0U}, {74U, 255U, 255U, 1U, 1U}, {75U, 12U, 12U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 56U, 56U, 0U, 0U}, {78U, 112U, 112U, 1U, 1U}, {79U, 2U, 2U, 0U, 0U}, {80U, 136U, 136U, 0U, 0U}, {81U, 12U, 12U, 0U, 0U}, {82U, 0U, 0U, 0U, 0U}, {83U, 8U, 8U, 0U, 0U}, {84U, 112U, 112U, 1U, 1U}, {85U, 2U, 2U, 0U, 0U}, {86U, 255U, 255U, 1U, 1U}, {87U, 0U, 0U, 0U, 0U}, {88U, 131U, 131U, 0U, 0U}, {89U, 119U, 119U, 1U, 1U}, {90U, 0U, 0U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 136U, 136U, 0U, 0U}, {93U, 0U, 0U, 0U, 0U}, {94U, 8U, 8U, 0U, 0U}, {95U, 119U, 119U, 1U, 1U}, {96U, 1U, 1U, 0U, 0U}, {97U, 0U, 0U, 0U, 0U}, {98U, 7U, 7U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 7U, 7U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 1U, 1U}, {104U, 0U, 0U, 0U, 0U}, {105U, 10U, 10U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 2U, 2U, 0U, 0U}, {114U, 0U, 0U, 0U, 0U}, {115U, 0U, 0U, 0U, 0U}, {116U, 14U, 14U, 0U, 0U}, {117U, 14U, 14U, 0U, 0U}, {118U, 14U, 14U, 0U, 0U}, {119U, 19U, 19U, 0U, 0U}, {120U, 19U, 19U, 0U, 0U}, {121U, 27U, 27U, 0U, 0U}, {122U, 27U, 27U, 0U, 0U}, {123U, 85U, 85U, 0U, 0U}, {124U, 91U, 91U, 0U, 0U}, {125U, 48U, 48U, 1U, 1U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 112U, 112U, 0U, 0U}, {148U, 112U, 112U, 0U, 0U}, {149U, 112U, 112U, 0U, 0U}, {150U, 112U, 112U, 0U, 0U}, {151U, 112U, 112U, 0U, 0U}, {152U, 112U, 112U, 0U, 0U}, {153U, 112U, 112U, 0U, 0U}, {154U, 112U, 112U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_RX_2056_rev6[148U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 3U, 3U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 0U, 0U, 0U, 0U}, {35U, 144U, 144U, 0U, 0U}, {36U, 85U, 85U, 0U, 0U}, {37U, 21U, 21U, 0U, 0U}, {38U, 5U, 5U, 0U, 0U}, {39U, 21U, 21U, 0U, 0U}, {40U, 5U, 5U, 0U, 0U}, {41U, 32U, 32U, 0U, 0U}, {42U, 17U, 17U, 0U, 0U}, {43U, 144U, 144U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 136U, 136U, 0U, 0U}, {46U, 50U, 50U, 0U, 0U}, {47U, 119U, 119U, 0U, 0U}, {48U, 23U, 23U, 1U, 1U}, {49U, 255U, 255U, 1U, 1U}, {50U, 32U, 32U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 136U, 136U, 0U, 0U}, {53U, 50U, 50U, 0U, 0U}, {54U, 119U, 119U, 0U, 0U}, {55U, 23U, 23U, 1U, 1U}, {56U, 240U, 240U, 1U, 1U}, {57U, 32U, 32U, 0U, 0U}, {58U, 8U, 8U, 0U, 0U}, {59U, 85U, 85U, 1U, 1U}, {60U, 0U, 0U, 0U, 0U}, {61U, 136U, 136U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 68U, 68U, 0U, 0U}, {64U, 7U, 7U, 1U, 1U}, {65U, 6U, 6U, 0U, 0U}, {66U, 4U, 4U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 8U, 8U, 0U, 0U}, {69U, 85U, 85U, 1U, 1U}, {70U, 0U, 0U, 0U, 0U}, {71U, 17U, 17U, 0U, 0U}, {72U, 0U, 0U, 0U, 0U}, {73U, 68U, 68U, 0U, 0U}, {74U, 7U, 7U, 0U, 0U}, {75U, 6U, 6U, 0U, 0U}, {76U, 4U, 4U, 0U, 0U}, {77U, 0U, 0U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 38U, 38U, 1U, 1U}, {80U, 38U, 38U, 1U, 1U}, {81U, 15U, 15U, 1U, 1U}, {82U, 15U, 15U, 1U, 1U}, {83U, 68U, 68U, 0U, 0U}, {84U, 0U, 0U, 0U, 0U}, {85U, 0U, 0U, 0U, 0U}, {86U, 8U, 8U, 0U, 0U}, {87U, 8U, 8U, 0U, 0U}, {88U, 7U, 7U, 0U, 0U}, {89U, 34U, 34U, 0U, 0U}, {90U, 34U, 34U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 4U, 4U, 1U, 1U}, {93U, 7U, 7U, 0U, 0U}, {94U, 85U, 85U, 0U, 0U}, {95U, 35U, 35U, 0U, 0U}, {96U, 65U, 65U, 0U, 0U}, {97U, 1U, 1U, 0U, 0U}, {98U, 10U, 10U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 0U, 0U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 12U, 12U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 0U, 0U, 0U, 0U}, {114U, 34U, 34U, 0U, 0U}, {115U, 34U, 34U, 0U, 0U}, {116U, 0U, 0U, 1U, 1U}, {117U, 10U, 10U, 0U, 0U}, {118U, 1U, 1U, 0U, 0U}, {119U, 34U, 34U, 0U, 0U}, {120U, 48U, 48U, 0U, 0U}, {121U, 0U, 0U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 5U, 5U, 1U, 1U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_SYN_2056_rev7[182U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 1U, 1U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 96U, 96U, 0U, 0U}, {35U, 6U, 6U, 0U, 0U}, {36U, 12U, 12U, 0U, 0U}, {37U, 0U, 0U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 0U, 0U, 0U, 0U}, {40U, 1U, 1U, 0U, 0U}, {41U, 0U, 0U, 0U, 0U}, {42U, 0U, 0U, 0U, 0U}, {43U, 0U, 0U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 0U, 0U, 0U, 0U}, {47U, 31U, 31U, 0U, 0U}, {48U, 21U, 21U, 0U, 0U}, {49U, 15U, 15U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 0U, 0U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 0U, 0U, 0U, 0U}, {56U, 0U, 0U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 0U, 0U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 19U, 19U, 0U, 0U}, {61U, 15U, 15U, 0U, 0U}, {62U, 24U, 24U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 32U, 32U, 0U, 0U}, {66U, 32U, 32U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 119U, 119U, 0U, 0U}, {69U, 7U, 7U, 0U, 0U}, {70U, 1U, 1U, 0U, 0U}, {71U, 4U, 4U, 0U, 0U}, {72U, 15U, 15U, 0U, 0U}, {73U, 48U, 48U, 0U, 0U}, {74U, 50U, 50U, 0U, 0U}, {75U, 13U, 13U, 0U, 0U}, {76U, 13U, 13U, 0U, 0U}, {77U, 4U, 4U, 0U, 0U}, {78U, 6U, 6U, 0U, 0U}, {79U, 1U, 1U, 0U, 0U}, {80U, 28U, 28U, 0U, 0U}, {81U, 2U, 2U, 0U, 0U}, {82U, 2U, 2U, 0U, 0U}, {83U, 247U, 247U, 1U, 1U}, {84U, 180U, 180U, 0U, 0U}, {85U, 210U, 210U, 0U, 0U}, {86U, 0U, 0U, 0U, 0U}, {87U, 0U, 0U, 0U, 0U}, {88U, 4U, 4U, 0U, 0U}, {89U, 150U, 150U, 0U, 0U}, {90U, 62U, 62U, 0U, 0U}, {91U, 62U, 62U, 0U, 0U}, {92U, 19U, 19U, 0U, 0U}, {93U, 2U, 2U, 0U, 0U}, {94U, 0U, 0U, 0U, 0U}, {95U, 7U, 7U, 0U, 0U}, {96U, 7U, 7U, 1U, 1U}, {97U, 8U, 8U, 0U, 0U}, {98U, 3U, 3U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 64U, 64U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 1U, 1U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 96U, 96U, 0U, 0U}, {113U, 102U, 102U, 0U, 0U}, {114U, 12U, 12U, 0U, 0U}, {115U, 102U, 102U, 0U, 0U}, {116U, 143U, 143U, 1U, 1U}, {117U, 0U, 0U, 0U, 0U}, {118U, 204U, 204U, 0U, 0U}, {119U, 1U, 1U, 0U, 0U}, {120U, 102U, 102U, 0U, 0U}, {121U, 102U, 102U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 255U, 255U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {149U, 0U, 0U, 0U, 0U}, {150U, 0U, 0U, 0U, 0U}, {151U, 0U, 0U, 0U, 0U}, {152U, 0U, 0U, 0U, 0U}, {153U, 0U, 0U, 0U, 0U}, {154U, 0U, 0U, 0U, 0U}, {155U, 0U, 0U, 0U, 0U}, {156U, 0U, 0U, 0U, 0U}, {157U, 0U, 0U, 0U, 0U}, {158U, 0U, 0U, 0U, 0U}, {159U, 6U, 6U, 0U, 0U}, {160U, 102U, 102U, 0U, 0U}, {161U, 102U, 102U, 0U, 0U}, {162U, 102U, 102U, 0U, 0U}, {163U, 102U, 102U, 0U, 0U}, {164U, 102U, 102U, 0U, 0U}, {165U, 102U, 102U, 0U, 0U}, {166U, 102U, 102U, 0U, 0U}, {167U, 102U, 102U, 0U, 0U}, {168U, 102U, 102U, 0U, 0U}, {169U, 102U, 102U, 0U, 0U}, {170U, 102U, 102U, 0U, 0U}, {171U, 102U, 102U, 0U, 0U}, {172U, 102U, 102U, 0U, 0U}, {173U, 102U, 102U, 0U, 0U}, {174U, 102U, 102U, 0U, 0U}, {175U, 102U, 102U, 0U, 0U}, {176U, 102U, 102U, 0U, 0U}, {177U, 102U, 102U, 0U, 0U}, {178U, 102U, 102U, 0U, 0U}, {179U, 10U, 10U, 0U, 0U}, {180U, 0U, 0U, 0U, 0U}, {181U, 0U, 0U, 0U, 0U}, {182U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_TX_2056_rev7[154U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 136U, 136U, 0U, 0U}, {34U, 136U, 136U, 0U, 0U}, {35U, 136U, 136U, 0U, 0U}, {36U, 136U, 136U, 0U, 0U}, {37U, 12U, 12U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 3U, 3U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 3U, 3U, 0U, 0U}, {42U, 55U, 55U, 0U, 0U}, {43U, 3U, 3U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 1U, 1U, 0U, 0U}, {47U, 1U, 1U, 0U, 0U}, {48U, 0U, 0U, 0U, 0U}, {49U, 0U, 0U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 17U, 17U, 0U, 0U}, {52U, 238U, 238U, 1U, 1U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 3U, 3U, 0U, 0U}, {56U, 80U, 80U, 1U, 1U}, {57U, 0U, 0U, 0U, 0U}, {58U, 80U, 80U, 1U, 1U}, {59U, 0U, 0U, 0U, 0U}, {60U, 110U, 110U, 0U, 0U}, {61U, 240U, 240U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 3U, 3U, 0U, 0U}, {66U, 3U, 3U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 30U, 30U, 0U, 0U}, {69U, 0U, 0U, 0U, 0U}, {70U, 110U, 110U, 0U, 0U}, {71U, 240U, 240U, 1U, 1U}, {72U, 0U, 0U, 0U, 0U}, {73U, 2U, 2U, 0U, 0U}, {74U, 255U, 255U, 1U, 1U}, {75U, 12U, 12U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 56U, 56U, 0U, 0U}, {78U, 112U, 112U, 1U, 1U}, {79U, 2U, 2U, 0U, 0U}, {80U, 136U, 136U, 0U, 0U}, {81U, 12U, 12U, 0U, 0U}, {82U, 0U, 0U, 0U, 0U}, {83U, 8U, 8U, 0U, 0U}, {84U, 112U, 112U, 1U, 1U}, {85U, 2U, 2U, 0U, 0U}, {86U, 255U, 255U, 1U, 1U}, {87U, 0U, 0U, 0U, 0U}, {88U, 131U, 131U, 0U, 0U}, {89U, 119U, 119U, 1U, 1U}, {90U, 0U, 0U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 136U, 136U, 0U, 0U}, {93U, 0U, 0U, 0U, 0U}, {94U, 8U, 8U, 0U, 0U}, {95U, 119U, 119U, 1U, 1U}, {96U, 1U, 1U, 0U, 0U}, {97U, 0U, 0U, 0U, 0U}, {98U, 7U, 7U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 7U, 7U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 1U, 1U}, {104U, 0U, 0U, 0U, 0U}, {105U, 10U, 10U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 2U, 2U, 0U, 0U}, {114U, 0U, 0U, 0U, 0U}, {115U, 0U, 0U, 0U, 0U}, {116U, 14U, 14U, 0U, 0U}, {117U, 14U, 14U, 0U, 0U}, {118U, 14U, 14U, 0U, 0U}, {119U, 19U, 19U, 0U, 0U}, {120U, 19U, 19U, 0U, 0U}, {121U, 27U, 27U, 0U, 0U}, {122U, 27U, 27U, 0U, 0U}, {123U, 85U, 85U, 0U, 0U}, {124U, 91U, 91U, 0U, 0U}, {125U, 48U, 48U, 1U, 1U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 112U, 112U, 0U, 0U}, {148U, 112U, 112U, 0U, 0U}, {149U, 113U, 113U, 1U, 1U}, {150U, 113U, 113U, 1U, 1U}, {151U, 114U, 114U, 1U, 1U}, {152U, 115U, 115U, 1U, 1U}, {153U, 116U, 116U, 1U, 1U}, {154U, 117U, 117U, 1U, 1U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_RX_2056_rev7[148U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 3U, 3U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 0U, 0U, 0U, 0U}, {35U, 144U, 144U, 0U, 0U}, {36U, 85U, 85U, 0U, 0U}, {37U, 21U, 21U, 0U, 0U}, {38U, 5U, 5U, 0U, 0U}, {39U, 21U, 21U, 0U, 0U}, {40U, 5U, 5U, 0U, 0U}, {41U, 32U, 32U, 0U, 0U}, {42U, 17U, 17U, 0U, 0U}, {43U, 144U, 144U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 136U, 136U, 0U, 0U}, {46U, 50U, 50U, 0U, 0U}, {47U, 119U, 119U, 0U, 0U}, {48U, 23U, 23U, 1U, 1U}, {49U, 255U, 255U, 1U, 1U}, {50U, 32U, 32U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 136U, 136U, 0U, 0U}, {53U, 50U, 50U, 0U, 0U}, {54U, 119U, 119U, 0U, 0U}, {55U, 23U, 23U, 1U, 1U}, {56U, 240U, 240U, 1U, 1U}, {57U, 32U, 32U, 0U, 0U}, {58U, 8U, 8U, 0U, 0U}, {59U, 85U, 85U, 1U, 1U}, {60U, 0U, 0U, 0U, 0U}, {61U, 136U, 136U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 1U, 1U}, {64U, 7U, 7U, 1U, 1U}, {65U, 6U, 6U, 0U, 0U}, {66U, 4U, 4U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 8U, 8U, 0U, 0U}, {69U, 85U, 85U, 1U, 1U}, {70U, 0U, 0U, 0U, 0U}, {71U, 17U, 17U, 0U, 0U}, {72U, 0U, 0U, 0U, 0U}, {73U, 0U, 0U, 1U, 1U}, {74U, 7U, 7U, 0U, 0U}, {75U, 6U, 6U, 0U, 0U}, {76U, 4U, 4U, 0U, 0U}, {77U, 0U, 0U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 38U, 38U, 1U, 1U}, {80U, 38U, 38U, 1U, 1U}, {81U, 15U, 15U, 1U, 1U}, {82U, 15U, 15U, 1U, 1U}, {83U, 68U, 68U, 0U, 0U}, {84U, 0U, 0U, 0U, 0U}, {85U, 0U, 0U, 0U, 0U}, {86U, 8U, 8U, 0U, 0U}, {87U, 8U, 8U, 0U, 0U}, {88U, 7U, 7U, 0U, 0U}, {89U, 34U, 34U, 0U, 0U}, {90U, 34U, 34U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 4U, 4U, 1U, 1U}, {93U, 7U, 7U, 0U, 0U}, {94U, 85U, 85U, 0U, 0U}, {95U, 35U, 35U, 0U, 0U}, {96U, 65U, 65U, 0U, 0U}, {97U, 1U, 1U, 0U, 0U}, {98U, 10U, 10U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 0U, 0U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 12U, 12U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 0U, 0U, 0U, 0U}, {114U, 34U, 34U, 0U, 0U}, {115U, 34U, 34U, 0U, 0U}, {116U, 0U, 0U, 1U, 1U}, {117U, 10U, 10U, 0U, 0U}, {118U, 1U, 1U, 0U, 0U}, {119U, 34U, 34U, 0U, 0U}, {120U, 48U, 48U, 0U, 0U}, {121U, 0U, 0U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_SYN_2056_rev8[182U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 1U, 1U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 96U, 96U, 0U, 0U}, {35U, 6U, 6U, 0U, 0U}, {36U, 12U, 12U, 0U, 0U}, {37U, 0U, 0U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 0U, 0U, 0U, 0U}, {40U, 1U, 1U, 0U, 0U}, {41U, 0U, 0U, 0U, 0U}, {42U, 0U, 0U, 0U, 0U}, {43U, 0U, 0U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 0U, 0U, 0U, 0U}, {47U, 31U, 31U, 0U, 0U}, {48U, 21U, 21U, 0U, 0U}, {49U, 15U, 15U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 0U, 0U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 0U, 0U, 0U, 0U}, {56U, 0U, 0U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 0U, 0U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 19U, 19U, 0U, 0U}, {61U, 15U, 15U, 0U, 0U}, {62U, 24U, 24U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 32U, 32U, 0U, 0U}, {66U, 32U, 32U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 119U, 119U, 0U, 0U}, {69U, 7U, 7U, 0U, 0U}, {70U, 1U, 1U, 0U, 0U}, {71U, 4U, 4U, 0U, 0U}, {72U, 15U, 15U, 0U, 0U}, {73U, 48U, 48U, 0U, 0U}, {74U, 50U, 50U, 0U, 0U}, {75U, 13U, 13U, 0U, 0U}, {76U, 13U, 13U, 0U, 0U}, {77U, 4U, 4U, 0U, 0U}, {78U, 6U, 6U, 0U, 0U}, {79U, 1U, 1U, 0U, 0U}, {80U, 28U, 28U, 0U, 0U}, {81U, 2U, 2U, 0U, 0U}, {82U, 2U, 2U, 0U, 0U}, {83U, 247U, 247U, 1U, 1U}, {84U, 180U, 180U, 0U, 0U}, {85U, 210U, 210U, 0U, 0U}, {86U, 0U, 0U, 0U, 0U}, {87U, 0U, 0U, 0U, 0U}, {88U, 4U, 4U, 0U, 0U}, {89U, 150U, 150U, 0U, 0U}, {90U, 62U, 62U, 0U, 0U}, {91U, 62U, 62U, 0U, 0U}, {92U, 19U, 19U, 0U, 0U}, {93U, 2U, 2U, 0U, 0U}, {94U, 0U, 0U, 0U, 0U}, {95U, 7U, 7U, 0U, 0U}, {96U, 7U, 7U, 1U, 1U}, {97U, 8U, 8U, 0U, 0U}, {98U, 3U, 3U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 64U, 64U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 1U, 1U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 96U, 96U, 0U, 0U}, {113U, 102U, 102U, 0U, 0U}, {114U, 12U, 12U, 0U, 0U}, {115U, 102U, 102U, 0U, 0U}, {116U, 143U, 143U, 1U, 1U}, {117U, 0U, 0U, 0U, 0U}, {118U, 204U, 204U, 0U, 0U}, {119U, 1U, 1U, 0U, 0U}, {120U, 102U, 102U, 0U, 0U}, {121U, 102U, 102U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 255U, 255U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {149U, 0U, 0U, 0U, 0U}, {150U, 0U, 0U, 0U, 0U}, {151U, 0U, 0U, 0U, 0U}, {152U, 0U, 0U, 0U, 0U}, {153U, 0U, 0U, 0U, 0U}, {154U, 0U, 0U, 0U, 0U}, {155U, 0U, 0U, 0U, 0U}, {156U, 0U, 0U, 0U, 0U}, {157U, 0U, 0U, 0U, 0U}, {158U, 0U, 0U, 0U, 0U}, {159U, 6U, 6U, 0U, 0U}, {160U, 102U, 102U, 0U, 0U}, {161U, 102U, 102U, 0U, 0U}, {162U, 102U, 102U, 0U, 0U}, {163U, 102U, 102U, 0U, 0U}, {164U, 102U, 102U, 0U, 0U}, {165U, 102U, 102U, 0U, 0U}, {166U, 102U, 102U, 0U, 0U}, {167U, 102U, 102U, 0U, 0U}, {168U, 102U, 102U, 0U, 0U}, {169U, 102U, 102U, 0U, 0U}, {170U, 102U, 102U, 0U, 0U}, {171U, 102U, 102U, 0U, 0U}, {172U, 102U, 102U, 0U, 0U}, {173U, 102U, 102U, 0U, 0U}, {174U, 102U, 102U, 0U, 0U}, {175U, 102U, 102U, 0U, 0U}, {176U, 102U, 102U, 0U, 0U}, {177U, 102U, 102U, 0U, 0U}, {178U, 102U, 102U, 0U, 0U}, {179U, 10U, 10U, 0U, 0U}, {180U, 0U, 0U, 0U, 0U}, {181U, 0U, 0U, 0U, 0U}, {182U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_TX_2056_rev8[154U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 136U, 136U, 0U, 0U}, {34U, 136U, 136U, 0U, 0U}, {35U, 136U, 136U, 0U, 0U}, {36U, 136U, 136U, 0U, 0U}, {37U, 12U, 12U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 3U, 3U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 3U, 3U, 0U, 0U}, {42U, 55U, 55U, 0U, 0U}, {43U, 3U, 3U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 1U, 1U, 0U, 0U}, {47U, 1U, 1U, 0U, 0U}, {48U, 0U, 0U, 0U, 0U}, {49U, 0U, 0U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 17U, 17U, 0U, 0U}, {52U, 238U, 238U, 1U, 1U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 3U, 3U, 0U, 0U}, {56U, 80U, 80U, 1U, 1U}, {57U, 0U, 0U, 0U, 0U}, {58U, 80U, 80U, 1U, 1U}, {59U, 0U, 0U, 0U, 0U}, {60U, 110U, 110U, 0U, 0U}, {61U, 240U, 240U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 3U, 3U, 0U, 0U}, {66U, 3U, 3U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 30U, 30U, 0U, 0U}, {69U, 0U, 0U, 0U, 0U}, {70U, 110U, 110U, 0U, 0U}, {71U, 240U, 240U, 1U, 1U}, {72U, 0U, 0U, 0U, 0U}, {73U, 2U, 2U, 0U, 0U}, {74U, 255U, 255U, 1U, 1U}, {75U, 12U, 12U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 56U, 56U, 0U, 0U}, {78U, 112U, 112U, 1U, 1U}, {79U, 2U, 2U, 0U, 0U}, {80U, 136U, 136U, 0U, 0U}, {81U, 12U, 12U, 0U, 0U}, {82U, 0U, 0U, 0U, 0U}, {83U, 8U, 8U, 0U, 0U}, {84U, 112U, 112U, 1U, 1U}, {85U, 2U, 2U, 0U, 0U}, {86U, 255U, 255U, 1U, 1U}, {87U, 0U, 0U, 0U, 0U}, {88U, 131U, 131U, 0U, 0U}, {89U, 119U, 119U, 1U, 1U}, {90U, 0U, 0U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 136U, 136U, 0U, 0U}, {93U, 0U, 0U, 0U, 0U}, {94U, 8U, 8U, 0U, 0U}, {95U, 119U, 119U, 1U, 1U}, {96U, 1U, 1U, 0U, 0U}, {97U, 0U, 0U, 0U, 0U}, {98U, 7U, 7U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 7U, 7U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 1U, 1U}, {104U, 0U, 0U, 0U, 0U}, {105U, 10U, 10U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 2U, 2U, 0U, 0U}, {114U, 0U, 0U, 0U, 0U}, {115U, 0U, 0U, 0U, 0U}, {116U, 14U, 14U, 0U, 0U}, {117U, 14U, 14U, 0U, 0U}, {118U, 14U, 14U, 0U, 0U}, {119U, 19U, 19U, 0U, 0U}, {120U, 19U, 19U, 0U, 0U}, {121U, 27U, 27U, 0U, 0U}, {122U, 27U, 27U, 0U, 0U}, {123U, 85U, 85U, 0U, 0U}, {124U, 91U, 91U, 0U, 0U}, {125U, 48U, 48U, 1U, 1U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 112U, 112U, 0U, 0U}, {148U, 112U, 112U, 0U, 0U}, {149U, 112U, 112U, 0U, 0U}, {150U, 112U, 112U, 0U, 0U}, {151U, 112U, 112U, 0U, 0U}, {152U, 112U, 112U, 0U, 0U}, {153U, 112U, 112U, 0U, 0U}, {154U, 112U, 112U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs regs_RX_2056_rev8[148U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 3U, 3U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 0U, 0U, 0U, 0U}, {35U, 144U, 144U, 0U, 0U}, {36U, 85U, 85U, 0U, 0U}, {37U, 21U, 21U, 0U, 0U}, {38U, 5U, 5U, 0U, 0U}, {39U, 21U, 21U, 0U, 0U}, {40U, 5U, 5U, 0U, 0U}, {41U, 32U, 32U, 0U, 0U}, {42U, 17U, 17U, 0U, 0U}, {43U, 144U, 144U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 136U, 136U, 0U, 0U}, {46U, 50U, 50U, 0U, 0U}, {47U, 119U, 119U, 0U, 0U}, {48U, 23U, 23U, 1U, 1U}, {49U, 255U, 255U, 1U, 1U}, {50U, 32U, 32U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 136U, 136U, 0U, 0U}, {53U, 50U, 50U, 0U, 0U}, {54U, 119U, 119U, 0U, 0U}, {55U, 23U, 23U, 1U, 1U}, {56U, 240U, 240U, 1U, 1U}, {57U, 32U, 32U, 0U, 0U}, {58U, 8U, 8U, 0U, 0U}, {59U, 85U, 85U, 1U, 1U}, {60U, 0U, 0U, 0U, 0U}, {61U, 136U, 136U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 68U, 68U, 0U, 0U}, {64U, 7U, 7U, 1U, 1U}, {65U, 6U, 6U, 0U, 0U}, {66U, 4U, 4U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 8U, 8U, 0U, 0U}, {69U, 85U, 85U, 1U, 1U}, {70U, 0U, 0U, 0U, 0U}, {71U, 17U, 17U, 0U, 0U}, {72U, 0U, 0U, 0U, 0U}, {73U, 68U, 68U, 0U, 0U}, {74U, 7U, 7U, 0U, 0U}, {75U, 6U, 6U, 0U, 0U}, {76U, 4U, 4U, 0U, 0U}, {77U, 0U, 0U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 38U, 38U, 1U, 1U}, {80U, 38U, 38U, 1U, 1U}, {81U, 15U, 15U, 1U, 1U}, {82U, 15U, 15U, 1U, 1U}, {83U, 68U, 68U, 0U, 0U}, {84U, 0U, 0U, 0U, 0U}, {85U, 0U, 0U, 0U, 0U}, {86U, 8U, 8U, 0U, 0U}, {87U, 8U, 8U, 0U, 0U}, {88U, 7U, 7U, 0U, 0U}, {89U, 34U, 34U, 0U, 0U}, {90U, 34U, 34U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 4U, 4U, 1U, 1U}, {93U, 7U, 7U, 0U, 0U}, {94U, 85U, 85U, 0U, 0U}, {95U, 35U, 35U, 0U, 0U}, {96U, 65U, 65U, 0U, 0U}, {97U, 1U, 1U, 0U, 0U}, {98U, 10U, 10U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 0U, 0U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 12U, 12U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 0U, 0U, 0U, 0U}, {114U, 34U, 34U, 0U, 0U}, {115U, 34U, 34U, 0U, 0U}, {116U, 0U, 0U, 1U, 1U}, {117U, 10U, 10U, 0U, 0U}, {118U, 1U, 1U, 0U, 0U}, {119U, 34U, 34U, 0U, 0U}, {120U, 48U, 48U, 0U, 0U}, {121U, 0U, 0U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 5U, 5U, 1U, 1U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs const regs_SYN_2056_rev11[182U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 1U, 1U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 96U, 96U, 0U, 0U}, {35U, 6U, 6U, 0U, 0U}, {36U, 12U, 12U, 0U, 0U}, {37U, 0U, 0U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 0U, 0U, 0U, 0U}, {40U, 1U, 1U, 0U, 0U}, {41U, 0U, 0U, 0U, 0U}, {42U, 0U, 0U, 0U, 0U}, {43U, 0U, 0U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 0U, 0U, 0U, 0U}, {47U, 31U, 31U, 0U, 0U}, {48U, 21U, 21U, 0U, 0U}, {49U, 15U, 15U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 0U, 0U, 0U, 0U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 0U, 0U, 0U, 0U}, {56U, 0U, 0U, 0U, 0U}, {57U, 0U, 0U, 0U, 0U}, {58U, 0U, 0U, 0U, 0U}, {59U, 0U, 0U, 0U, 0U}, {60U, 19U, 19U, 0U, 0U}, {61U, 15U, 15U, 0U, 0U}, {62U, 24U, 24U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 32U, 32U, 0U, 0U}, {66U, 32U, 32U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 119U, 119U, 0U, 0U}, {69U, 7U, 7U, 0U, 0U}, {70U, 1U, 1U, 0U, 0U}, {71U, 6U, 6U, 1U, 1U}, {72U, 15U, 15U, 0U, 0U}, {73U, 63U, 63U, 1U, 1U}, {74U, 50U, 50U, 0U, 0U}, {75U, 6U, 6U, 1U, 1U}, {76U, 6U, 6U, 1U, 1U}, {77U, 4U, 4U, 0U, 0U}, {78U, 43U, 43U, 1U, 1U}, {79U, 1U, 1U, 0U, 0U}, {80U, 28U, 28U, 0U, 0U}, {81U, 2U, 2U, 0U, 0U}, {82U, 2U, 2U, 0U, 0U}, {83U, 247U, 247U, 1U, 1U}, {84U, 180U, 180U, 0U, 0U}, {85U, 210U, 210U, 0U, 0U}, {86U, 0U, 0U, 0U, 0U}, {87U, 0U, 0U, 0U, 0U}, {88U, 4U, 4U, 0U, 0U}, {89U, 150U, 150U, 0U, 0U}, {90U, 62U, 62U, 0U, 0U}, {91U, 62U, 62U, 0U, 0U}, {92U, 19U, 19U, 0U, 0U}, {93U, 2U, 2U, 0U, 0U}, {94U, 0U, 0U, 0U, 0U}, {95U, 7U, 7U, 0U, 0U}, {96U, 7U, 7U, 1U, 1U}, {97U, 8U, 8U, 0U, 0U}, {98U, 3U, 3U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 64U, 64U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 1U, 1U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 96U, 96U, 0U, 0U}, {113U, 102U, 102U, 0U, 0U}, {114U, 12U, 12U, 0U, 0U}, {115U, 102U, 102U, 0U, 0U}, {116U, 143U, 143U, 1U, 1U}, {117U, 0U, 0U, 0U, 0U}, {118U, 204U, 204U, 0U, 0U}, {119U, 1U, 1U, 0U, 0U}, {120U, 102U, 102U, 0U, 0U}, {121U, 102U, 102U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 0U, 0U, 0U, 0U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 255U, 255U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {149U, 0U, 0U, 0U, 0U}, {150U, 0U, 0U, 0U, 0U}, {151U, 0U, 0U, 0U, 0U}, {152U, 0U, 0U, 0U, 0U}, {153U, 0U, 0U, 0U, 0U}, {154U, 0U, 0U, 0U, 0U}, {155U, 0U, 0U, 0U, 0U}, {156U, 0U, 0U, 0U, 0U}, {157U, 0U, 0U, 0U, 0U}, {158U, 0U, 0U, 0U, 0U}, {159U, 6U, 6U, 0U, 0U}, {160U, 102U, 102U, 0U, 0U}, {161U, 102U, 102U, 0U, 0U}, {162U, 102U, 102U, 0U, 0U}, {163U, 102U, 102U, 0U, 0U}, {164U, 102U, 102U, 0U, 0U}, {165U, 102U, 102U, 0U, 0U}, {166U, 102U, 102U, 0U, 0U}, {167U, 102U, 102U, 0U, 0U}, {168U, 102U, 102U, 0U, 0U}, {169U, 102U, 102U, 0U, 0U}, {170U, 102U, 102U, 0U, 0U}, {171U, 102U, 102U, 0U, 0U}, {172U, 102U, 102U, 0U, 0U}, {173U, 102U, 102U, 0U, 0U}, {174U, 102U, 102U, 0U, 0U}, {175U, 102U, 102U, 0U, 0U}, {176U, 102U, 102U, 0U, 0U}, {177U, 102U, 102U, 0U, 0U}, {178U, 102U, 102U, 0U, 0U}, {179U, 10U, 10U, 0U, 0U}, {180U, 0U, 0U, 0U, 0U}, {181U, 0U, 0U, 0U, 0U}, {182U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs const regs_TX_2056_rev11[154U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 0U, 0U, 0U, 0U}, {33U, 136U, 136U, 0U, 0U}, {34U, 136U, 136U, 0U, 0U}, {35U, 136U, 136U, 0U, 0U}, {36U, 136U, 136U, 0U, 0U}, {37U, 12U, 12U, 0U, 0U}, {38U, 0U, 0U, 0U, 0U}, {39U, 3U, 3U, 0U, 0U}, {40U, 0U, 0U, 0U, 0U}, {41U, 3U, 3U, 0U, 0U}, {42U, 55U, 55U, 0U, 0U}, {43U, 3U, 3U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 0U, 0U, 0U, 0U}, {46U, 1U, 1U, 0U, 0U}, {47U, 1U, 1U, 0U, 0U}, {48U, 0U, 0U, 0U, 0U}, {49U, 0U, 0U, 0U, 0U}, {50U, 0U, 0U, 0U, 0U}, {51U, 17U, 17U, 0U, 0U}, {52U, 238U, 238U, 1U, 1U}, {53U, 0U, 0U, 0U, 0U}, {54U, 0U, 0U, 0U, 0U}, {55U, 3U, 3U, 0U, 0U}, {56U, 80U, 80U, 1U, 1U}, {57U, 0U, 0U, 0U, 0U}, {58U, 80U, 80U, 1U, 1U}, {59U, 0U, 0U, 0U, 0U}, {60U, 110U, 110U, 0U, 0U}, {61U, 240U, 240U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 0U, 0U, 0U, 0U}, {64U, 0U, 0U, 0U, 0U}, {65U, 3U, 3U, 0U, 0U}, {66U, 3U, 3U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 30U, 30U, 0U, 0U}, {69U, 0U, 0U, 0U, 0U}, {70U, 110U, 110U, 0U, 0U}, {71U, 240U, 240U, 1U, 1U}, {72U, 0U, 0U, 0U, 0U}, {73U, 2U, 2U, 0U, 0U}, {74U, 255U, 255U, 1U, 1U}, {75U, 12U, 12U, 0U, 0U}, {76U, 0U, 0U, 0U, 0U}, {77U, 56U, 56U, 0U, 0U}, {78U, 112U, 112U, 1U, 1U}, {79U, 2U, 2U, 0U, 0U}, {80U, 136U, 136U, 0U, 0U}, {81U, 12U, 12U, 0U, 0U}, {82U, 0U, 0U, 0U, 0U}, {83U, 8U, 8U, 0U, 0U}, {84U, 112U, 112U, 1U, 1U}, {85U, 2U, 2U, 0U, 0U}, {86U, 255U, 255U, 1U, 1U}, {87U, 0U, 0U, 0U, 0U}, {88U, 131U, 131U, 0U, 0U}, {89U, 119U, 119U, 1U, 1U}, {90U, 0U, 0U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 136U, 136U, 0U, 0U}, {93U, 0U, 0U, 0U, 0U}, {94U, 8U, 8U, 0U, 0U}, {95U, 119U, 119U, 1U, 1U}, {96U, 1U, 1U, 0U, 0U}, {97U, 0U, 0U, 0U, 0U}, {98U, 7U, 7U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 7U, 7U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 1U, 1U}, {104U, 0U, 0U, 0U, 0U}, {105U, 10U, 10U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 0U, 0U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 2U, 2U, 0U, 0U}, {114U, 0U, 0U, 0U, 0U}, {115U, 0U, 0U, 0U, 0U}, {116U, 14U, 14U, 0U, 0U}, {117U, 14U, 14U, 0U, 0U}, {118U, 14U, 14U, 0U, 0U}, {119U, 19U, 19U, 0U, 0U}, {120U, 19U, 19U, 0U, 0U}, {121U, 27U, 27U, 0U, 0U}, {122U, 27U, 27U, 0U, 0U}, {123U, 85U, 85U, 0U, 0U}, {124U, 91U, 91U, 0U, 0U}, {125U, 48U, 48U, 1U, 1U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 112U, 112U, 0U, 0U}, {148U, 112U, 112U, 0U, 0U}, {149U, 112U, 112U, 0U, 0U}, {150U, 112U, 112U, 0U, 0U}, {151U, 112U, 112U, 0U, 0U}, {152U, 112U, 112U, 0U, 0U}, {153U, 112U, 112U, 0U, 0U}, {154U, 112U, 112U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_regs const regs_RX_2056_rev11[148U] = { {2U, 0U, 0U, 0U, 0U}, {3U, 0U, 0U, 0U, 0U}, {4U, 0U, 0U, 0U, 0U}, {5U, 0U, 0U, 0U, 0U}, {6U, 0U, 0U, 0U, 0U}, {7U, 0U, 0U, 0U, 0U}, {8U, 0U, 0U, 0U, 0U}, {9U, 0U, 0U, 0U, 0U}, {10U, 0U, 0U, 0U, 0U}, {11U, 0U, 0U, 0U, 0U}, {12U, 0U, 0U, 0U, 0U}, {13U, 0U, 0U, 0U, 0U}, {14U, 0U, 0U, 0U, 0U}, {15U, 0U, 0U, 0U, 0U}, {16U, 0U, 0U, 0U, 0U}, {17U, 0U, 0U, 0U, 0U}, {18U, 0U, 0U, 0U, 0U}, {19U, 0U, 0U, 0U, 0U}, {20U, 0U, 0U, 0U, 0U}, {21U, 0U, 0U, 0U, 0U}, {22U, 0U, 0U, 0U, 0U}, {23U, 0U, 0U, 0U, 0U}, {24U, 0U, 0U, 0U, 0U}, {25U, 0U, 0U, 0U, 0U}, {26U, 0U, 0U, 0U, 0U}, {27U, 0U, 0U, 0U, 0U}, {28U, 0U, 0U, 0U, 0U}, {29U, 0U, 0U, 0U, 0U}, {30U, 0U, 0U, 0U, 0U}, {31U, 0U, 0U, 0U, 0U}, {32U, 3U, 3U, 0U, 0U}, {33U, 0U, 0U, 0U, 0U}, {34U, 0U, 0U, 0U, 0U}, {35U, 144U, 144U, 0U, 0U}, {36U, 85U, 85U, 0U, 0U}, {37U, 21U, 21U, 0U, 0U}, {38U, 5U, 5U, 0U, 0U}, {39U, 21U, 21U, 0U, 0U}, {40U, 5U, 5U, 0U, 0U}, {41U, 32U, 32U, 0U, 0U}, {42U, 17U, 17U, 0U, 0U}, {43U, 144U, 144U, 0U, 0U}, {44U, 0U, 0U, 0U, 0U}, {45U, 136U, 136U, 0U, 0U}, {46U, 50U, 50U, 0U, 0U}, {47U, 119U, 119U, 0U, 0U}, {48U, 23U, 23U, 1U, 1U}, {49U, 255U, 255U, 1U, 1U}, {50U, 32U, 32U, 0U, 0U}, {51U, 0U, 0U, 0U, 0U}, {52U, 136U, 136U, 0U, 0U}, {53U, 50U, 50U, 0U, 0U}, {54U, 119U, 119U, 0U, 0U}, {55U, 23U, 23U, 1U, 1U}, {56U, 240U, 240U, 1U, 1U}, {57U, 32U, 32U, 0U, 0U}, {58U, 8U, 8U, 0U, 0U}, {59U, 85U, 85U, 1U, 1U}, {60U, 0U, 0U, 0U, 0U}, {61U, 136U, 136U, 1U, 1U}, {62U, 0U, 0U, 0U, 0U}, {63U, 68U, 68U, 0U, 0U}, {64U, 7U, 7U, 1U, 1U}, {65U, 6U, 6U, 0U, 0U}, {66U, 4U, 4U, 0U, 0U}, {67U, 0U, 0U, 0U, 0U}, {68U, 8U, 8U, 0U, 0U}, {69U, 85U, 85U, 1U, 1U}, {70U, 0U, 0U, 0U, 0U}, {71U, 17U, 17U, 0U, 0U}, {72U, 0U, 0U, 0U, 0U}, {73U, 68U, 68U, 0U, 0U}, {74U, 7U, 7U, 0U, 0U}, {75U, 6U, 6U, 0U, 0U}, {76U, 4U, 4U, 0U, 0U}, {77U, 0U, 0U, 0U, 0U}, {78U, 0U, 0U, 0U, 0U}, {79U, 38U, 38U, 1U, 1U}, {80U, 38U, 38U, 1U, 1U}, {81U, 15U, 15U, 1U, 1U}, {82U, 15U, 15U, 1U, 1U}, {83U, 68U, 68U, 0U, 0U}, {84U, 0U, 0U, 0U, 0U}, {85U, 0U, 0U, 0U, 0U}, {86U, 8U, 8U, 0U, 0U}, {87U, 8U, 8U, 0U, 0U}, {88U, 7U, 7U, 0U, 0U}, {89U, 34U, 34U, 0U, 0U}, {90U, 34U, 34U, 0U, 0U}, {91U, 2U, 2U, 0U, 0U}, {92U, 4U, 4U, 1U, 1U}, {93U, 7U, 7U, 0U, 0U}, {94U, 85U, 85U, 0U, 0U}, {95U, 35U, 35U, 0U, 0U}, {96U, 65U, 65U, 0U, 0U}, {97U, 1U, 1U, 0U, 0U}, {98U, 10U, 10U, 0U, 0U}, {99U, 0U, 0U, 0U, 0U}, {100U, 0U, 0U, 0U, 0U}, {101U, 0U, 0U, 0U, 0U}, {102U, 0U, 0U, 0U, 0U}, {103U, 0U, 0U, 0U, 0U}, {104U, 0U, 0U, 0U, 0U}, {105U, 0U, 0U, 0U, 0U}, {106U, 0U, 0U, 0U, 0U}, {107U, 12U, 12U, 0U, 0U}, {108U, 0U, 0U, 0U, 0U}, {109U, 0U, 0U, 0U, 0U}, {110U, 0U, 0U, 0U, 0U}, {111U, 0U, 0U, 0U, 0U}, {112U, 0U, 0U, 0U, 0U}, {113U, 0U, 0U, 0U, 0U}, {114U, 34U, 34U, 0U, 0U}, {115U, 34U, 34U, 0U, 0U}, {116U, 0U, 0U, 1U, 1U}, {117U, 10U, 10U, 0U, 0U}, {118U, 1U, 1U, 0U, 0U}, {119U, 34U, 34U, 0U, 0U}, {120U, 48U, 48U, 0U, 0U}, {121U, 0U, 0U, 0U, 0U}, {122U, 0U, 0U, 0U, 0U}, {123U, 0U, 0U, 0U, 0U}, {124U, 0U, 0U, 0U, 0U}, {125U, 5U, 5U, 1U, 1U}, {126U, 0U, 0U, 0U, 0U}, {127U, 0U, 0U, 0U, 0U}, {128U, 0U, 0U, 0U, 0U}, {129U, 0U, 0U, 0U, 0U}, {130U, 0U, 0U, 0U, 0U}, {131U, 0U, 0U, 0U, 0U}, {132U, 0U, 0U, 0U, 0U}, {133U, 0U, 0U, 0U, 0U}, {134U, 0U, 0U, 0U, 0U}, {135U, 0U, 0U, 0U, 0U}, {136U, 0U, 0U, 0U, 0U}, {137U, 0U, 0U, 0U, 0U}, {138U, 0U, 0U, 0U, 0U}, {139U, 0U, 0U, 0U, 0U}, {140U, 0U, 0U, 0U, 0U}, {141U, 0U, 0U, 0U, 0U}, {142U, 0U, 0U, 0U, 0U}, {143U, 0U, 0U, 0U, 0U}, {144U, 0U, 0U, 0U, 0U}, {145U, 0U, 0U, 0U, 0U}, {146U, 0U, 0U, 0U, 0U}, {147U, 0U, 0U, 0U, 0U}, {148U, 0U, 0U, 0U, 0U}, {65535U, 0U, 0U, 0U, 0U}}; static struct radio_20xx_regs regs_2057_rev4[387U] = { {0U, 132U, 0U}, {1U, 0U, 0U}, {2U, 96U, 0U}, {3U, 31U, 0U}, {4U, 4U, 0U}, {5U, 2U, 0U}, {6U, 1U, 0U}, {7U, 1U, 0U}, {8U, 1U, 0U}, {9U, 105U, 0U}, {10U, 102U, 0U}, {11U, 6U, 0U}, {12U, 24U, 0U}, {13U, 3U, 0U}, {14U, 32U, 1U}, {15U, 32U, 0U}, {16U, 0U, 0U}, {17U, 124U, 0U}, {18U, 66U, 0U}, {19U, 189U, 0U}, {20U, 7U, 0U}, {21U, 247U, 0U}, {22U, 8U, 0U}, {23U, 23U, 0U}, {24U, 7U, 0U}, {25U, 0U, 0U}, {26U, 2U, 0U}, {27U, 19U, 0U}, {28U, 62U, 0U}, {29U, 62U, 0U}, {30U, 150U, 0U}, {31U, 4U, 0U}, {32U, 0U, 0U}, {33U, 0U, 0U}, {34U, 23U, 0U}, {35U, 4U, 0U}, {36U, 1U, 0U}, {37U, 6U, 0U}, {38U, 4U, 0U}, {39U, 13U, 0U}, {40U, 13U, 0U}, {41U, 48U, 0U}, {42U, 50U, 0U}, {43U, 8U, 0U}, {44U, 28U, 0U}, {45U, 2U, 0U}, {46U, 4U, 0U}, {47U, 127U, 0U}, {48U, 39U, 0U}, {49U, 0U, 1U}, {50U, 0U, 1U}, {51U, 0U, 1U}, {52U, 0U, 0U}, {53U, 38U, 1U}, {54U, 24U, 0U}, {55U, 7U, 0U}, {56U, 102U, 0U}, {57U, 102U, 0U}, {58U, 102U, 0U}, {59U, 102U, 0U}, {60U, 255U, 1U}, {61U, 255U, 1U}, {62U, 255U, 1U}, {63U, 255U, 1U}, {64U, 22U, 0U}, {65U, 7U, 0U}, {66U, 25U, 0U}, {67U, 7U, 0U}, {68U, 6U, 0U}, {69U, 3U, 0U}, {70U, 1U, 0U}, {71U, 7U, 0U}, {72U, 51U, 0U}, {73U, 5U, 0U}, {74U, 119U, 0U}, {75U, 102U, 0U}, {76U, 102U, 0U}, {77U, 0U, 0U}, {78U, 4U, 0U}, {79U, 12U, 0U}, {80U, 0U, 0U}, {81U, 117U, 0U}, {86U, 7U, 0U}, {87U, 0U, 0U}, {88U, 0U, 0U}, {89U, 168U, 0U}, {90U, 0U, 0U}, {91U, 31U, 0U}, {92U, 48U, 0U}, {93U, 1U, 0U}, {94U, 48U, 0U}, {95U, 112U, 0U}, {96U, 0U, 0U}, {97U, 0U, 0U}, {98U, 51U, 1U}, {99U, 25U, 0U}, {100U, 98U, 0U}, {101U, 0U, 0U}, {102U, 17U, 0U}, {105U, 0U, 0U}, {106U, 126U, 0U}, {107U, 63U, 0U}, {108U, 127U, 0U}, {109U, 120U, 0U}, {110U, 200U, 0U}, {111U, 136U, 0U}, {112U, 8U, 0U}, {113U, 15U, 0U}, {114U, 188U, 0U}, {115U, 8U, 0U}, {116U, 96U, 0U}, {117U, 30U, 0U}, {118U, 112U, 0U}, {119U, 0U, 0U}, {120U, 0U, 0U}, {121U, 0U, 0U}, {122U, 51U, 0U}, {123U, 30U, 0U}, {124U, 98U, 0U}, {125U, 17U, 0U}, {128U, 60U, 0U}, {129U, 156U, 0U}, {130U, 10U, 0U}, {131U, 157U, 0U}, {132U, 10U, 0U}, {133U, 0U, 0U}, {134U, 64U, 0U}, {135U, 64U, 0U}, {136U, 136U, 0U}, {137U, 16U, 0U}, {138U, 240U, 1U}, {139U, 16U, 1U}, {140U, 240U, 1U}, {141U, 0U, 0U}, {142U, 0U, 0U}, {143U, 16U, 0U}, {144U, 85U, 0U}, {145U, 63U, 1U}, {146U, 54U, 1U}, {147U, 0U, 0U}, {148U, 0U, 0U}, {149U, 0U, 0U}, {150U, 135U, 0U}, {151U, 17U, 0U}, {152U, 0U, 0U}, {153U, 51U, 0U}, {154U, 136U, 0U}, {155U, 0U, 0U}, {156U, 135U, 0U}, {157U, 17U, 0U}, {158U, 0U, 0U}, {159U, 51U, 0U}, {160U, 136U, 0U}, {161U, 225U, 0U}, {162U, 63U, 0U}, {163U, 68U, 0U}, {164U, 140U, 1U}, {165U, 109U, 0U}, {166U, 34U, 0U}, {167U, 190U, 0U}, {168U, 85U, 1U}, {169U, 12U, 0U}, {170U, 12U, 0U}, {171U, 170U, 0U}, {172U, 2U, 0U}, {173U, 0U, 0U}, {174U, 16U, 0U}, {175U, 1U, 1U}, {176U, 0U, 0U}, {177U, 0U, 0U}, {178U, 128U, 0U}, {179U, 96U, 0U}, {180U, 68U, 0U}, {181U, 85U, 0U}, {182U, 1U, 0U}, {183U, 85U, 0U}, {184U, 1U, 0U}, {185U, 5U, 0U}, {186U, 85U, 0U}, {187U, 85U, 0U}, {193U, 0U, 0U}, {194U, 0U, 0U}, {195U, 0U, 0U}, {196U, 0U, 0U}, {197U, 0U, 0U}, {198U, 0U, 0U}, {199U, 0U, 0U}, {200U, 0U, 0U}, {201U, 0U, 0U}, {202U, 0U, 0U}, {203U, 0U, 0U}, {204U, 0U, 0U}, {205U, 0U, 0U}, {206U, 94U, 0U}, {207U, 12U, 0U}, {208U, 12U, 0U}, {209U, 12U, 0U}, {210U, 0U, 0U}, {211U, 43U, 0U}, {212U, 12U, 0U}, {213U, 0U, 0U}, {214U, 117U, 0U}, {219U, 7U, 0U}, {220U, 0U, 0U}, {221U, 0U, 0U}, {222U, 168U, 0U}, {223U, 0U, 0U}, {224U, 31U, 0U}, {225U, 48U, 0U}, {226U, 1U, 0U}, {227U, 48U, 0U}, {228U, 112U, 0U}, {229U, 0U, 0U}, {230U, 0U, 0U}, {231U, 51U, 0U}, {232U, 25U, 0U}, {233U, 98U, 0U}, {234U, 0U, 0U}, {235U, 17U, 0U}, {238U, 0U, 0U}, {239U, 126U, 0U}, {240U, 63U, 0U}, {241U, 127U, 0U}, {242U, 120U, 0U}, {243U, 200U, 0U}, {244U, 136U, 0U}, {245U, 8U, 0U}, {246U, 15U, 0U}, {247U, 188U, 0U}, {248U, 8U, 0U}, {249U, 96U, 0U}, {250U, 30U, 0U}, {251U, 112U, 0U}, {252U, 0U, 0U}, {253U, 0U, 0U}, {254U, 0U, 0U}, {255U, 51U, 0U}, {256U, 30U, 0U}, {257U, 98U, 0U}, {258U, 17U, 0U}, {261U, 60U, 0U}, {262U, 156U, 0U}, {263U, 10U, 0U}, {264U, 157U, 0U}, {265U, 10U, 0U}, {266U, 0U, 0U}, {267U, 64U, 0U}, {268U, 64U, 0U}, {269U, 136U, 0U}, {270U, 16U, 0U}, {271U, 240U, 1U}, {272U, 16U, 1U}, {273U, 240U, 1U}, {274U, 0U, 0U}, {275U, 0U, 0U}, {276U, 16U, 0U}, {277U, 85U, 0U}, {278U, 63U, 1U}, {279U, 54U, 1U}, {280U, 0U, 0U}, {281U, 0U, 0U}, {282U, 0U, 0U}, {283U, 135U, 0U}, {284U, 17U, 0U}, {285U, 0U, 0U}, {286U, 51U, 0U}, {287U, 136U, 0U}, {288U, 0U, 0U}, {289U, 135U, 0U}, {290U, 17U, 0U}, {291U, 0U, 0U}, {292U, 51U, 0U}, {293U, 136U, 0U}, {294U, 225U, 0U}, {295U, 63U, 0U}, {296U, 68U, 0U}, {297U, 140U, 1U}, {298U, 109U, 0U}, {299U, 34U, 0U}, {300U, 190U, 0U}, {301U, 85U, 1U}, {302U, 12U, 0U}, {303U, 12U, 0U}, {304U, 170U, 0U}, {305U, 2U, 0U}, {306U, 0U, 0U}, {307U, 16U, 0U}, {308U, 1U, 1U}, {309U, 0U, 0U}, {310U, 0U, 0U}, {311U, 128U, 0U}, {312U, 96U, 0U}, {313U, 68U, 0U}, {314U, 85U, 0U}, {315U, 1U, 0U}, {316U, 85U, 0U}, {317U, 1U, 0U}, {318U, 5U, 0U}, {319U, 85U, 0U}, {320U, 85U, 0U}, {326U, 0U, 0U}, {327U, 0U, 0U}, {328U, 0U, 0U}, {329U, 0U, 0U}, {330U, 0U, 0U}, {331U, 0U, 0U}, {332U, 0U, 0U}, {333U, 0U, 0U}, {334U, 0U, 0U}, {335U, 0U, 0U}, {336U, 0U, 0U}, {337U, 0U, 0U}, {338U, 0U, 0U}, {339U, 0U, 0U}, {340U, 12U, 0U}, {341U, 12U, 0U}, {342U, 12U, 0U}, {343U, 0U, 0U}, {344U, 43U, 0U}, {345U, 132U, 0U}, {346U, 21U, 0U}, {347U, 15U, 0U}, {348U, 0U, 0U}, {349U, 0U, 0U}, {350U, 0U, 1U}, {351U, 0U, 1U}, {352U, 0U, 1U}, {353U, 0U, 1U}, {354U, 0U, 1U}, {355U, 0U, 1U}, {356U, 0U, 0U}, {357U, 0U, 0U}, {358U, 0U, 0U}, {359U, 0U, 0U}, {360U, 0U, 0U}, {361U, 2U, 1U}, {362U, 0U, 1U}, {363U, 0U, 1U}, {364U, 0U, 1U}, {365U, 0U, 0U}, {368U, 0U, 0U}, {369U, 119U, 0U}, {370U, 119U, 0U}, {371U, 119U, 0U}, {372U, 119U, 0U}, {373U, 0U, 0U}, {374U, 3U, 0U}, {375U, 55U, 0U}, {376U, 3U, 0U}, {377U, 0U, 0U}, {378U, 33U, 0U}, {379U, 33U, 0U}, {380U, 0U, 0U}, {381U, 170U, 0U}, {382U, 0U, 0U}, {383U, 170U, 0U}, {384U, 0U, 0U}, {400U, 0U, 0U}, {401U, 119U, 0U}, {402U, 119U, 0U}, {403U, 119U, 0U}, {404U, 119U, 0U}, {405U, 0U, 0U}, {406U, 3U, 0U}, {407U, 55U, 0U}, {408U, 3U, 0U}, {409U, 0U, 0U}, {410U, 33U, 0U}, {411U, 33U, 0U}, {412U, 0U, 0U}, {413U, 170U, 0U}, {414U, 0U, 0U}, {415U, 170U, 0U}, {416U, 0U, 0U}, {417U, 2U, 0U}, {418U, 15U, 0U}, {419U, 15U, 0U}, {420U, 0U, 1U}, {421U, 0U, 1U}, {422U, 0U, 1U}, {423U, 2U, 0U}, {424U, 15U, 0U}, {425U, 15U, 0U}, {426U, 0U, 1U}, {427U, 0U, 1U}, {428U, 0U, 1U}, {65535U, 0U, 0U}}; static struct radio_20xx_regs regs_2057_rev5[329U] = { {0U, 0U, 1U}, {1U, 87U, 1U}, {2U, 32U, 1U}, {3U, 31U, 0U}, {4U, 4U, 0U}, {5U, 2U, 0U}, {6U, 1U, 0U}, {7U, 1U, 0U}, {8U, 1U, 0U}, {9U, 105U, 0U}, {10U, 102U, 0U}, {11U, 6U, 0U}, {12U, 24U, 0U}, {13U, 3U, 0U}, {14U, 32U, 0U}, {15U, 32U, 0U}, {16U, 0U, 0U}, {17U, 124U, 0U}, {18U, 66U, 0U}, {19U, 189U, 0U}, {20U, 7U, 0U}, {21U, 135U, 0U}, {22U, 8U, 0U}, {23U, 23U, 0U}, {24U, 7U, 0U}, {25U, 0U, 0U}, {26U, 2U, 0U}, {27U, 19U, 0U}, {28U, 62U, 0U}, {29U, 62U, 0U}, {30U, 150U, 0U}, {31U, 4U, 0U}, {32U, 0U, 0U}, {33U, 0U, 0U}, {34U, 23U, 0U}, {35U, 6U, 1U}, {36U, 1U, 0U}, {37U, 6U, 0U}, {38U, 4U, 0U}, {39U, 13U, 0U}, {40U, 13U, 0U}, {41U, 48U, 0U}, {42U, 50U, 0U}, {43U, 8U, 0U}, {44U, 28U, 0U}, {45U, 2U, 0U}, {46U, 4U, 0U}, {47U, 127U, 0U}, {48U, 39U, 0U}, {49U, 0U, 1U}, {50U, 0U, 1U}, {51U, 0U, 1U}, {52U, 0U, 0U}, {53U, 32U, 0U}, {54U, 24U, 0U}, {55U, 7U, 0U}, {56U, 102U, 0U}, {57U, 102U, 0U}, {60U, 255U, 0U}, {61U, 255U, 0U}, {64U, 22U, 0U}, {65U, 7U, 0U}, {69U, 3U, 0U}, {70U, 1U, 0U}, {71U, 7U, 0U}, {75U, 102U, 0U}, {76U, 102U, 0U}, {77U, 0U, 0U}, {78U, 4U, 0U}, {79U, 12U, 0U}, {80U, 0U, 0U}, {81U, 112U, 1U}, {86U, 7U, 0U}, {87U, 0U, 0U}, {88U, 0U, 0U}, {89U, 136U, 1U}, {90U, 0U, 0U}, {91U, 31U, 0U}, {92U, 32U, 1U}, {93U, 1U, 0U}, {94U, 48U, 0U}, {95U, 112U, 0U}, {96U, 0U, 0U}, {97U, 0U, 0U}, {98U, 51U, 1U}, {99U, 15U, 1U}, {100U, 15U, 1U}, {101U, 0U, 0U}, {102U, 17U, 0U}, {128U, 60U, 0U}, {129U, 1U, 1U}, {130U, 10U, 0U}, {133U, 0U, 0U}, {134U, 64U, 0U}, {135U, 64U, 0U}, {136U, 136U, 0U}, {137U, 16U, 0U}, {138U, 240U, 0U}, {139U, 16U, 0U}, {140U, 240U, 0U}, {143U, 16U, 0U}, {144U, 85U, 0U}, {145U, 63U, 1U}, {146U, 54U, 1U}, {147U, 0U, 0U}, {148U, 0U, 0U}, {149U, 0U, 0U}, {150U, 135U, 0U}, {151U, 17U, 0U}, {152U, 0U, 0U}, {153U, 51U, 0U}, {154U, 136U, 0U}, {161U, 32U, 1U}, {162U, 63U, 0U}, {163U, 68U, 0U}, {164U, 140U, 0U}, {165U, 108U, 0U}, {166U, 34U, 0U}, {167U, 190U, 0U}, {168U, 85U, 0U}, {170U, 12U, 0U}, {171U, 170U, 0U}, {172U, 2U, 0U}, {173U, 0U, 0U}, {174U, 16U, 0U}, {175U, 1U, 0U}, {176U, 0U, 0U}, {177U, 0U, 0U}, {178U, 128U, 0U}, {179U, 96U, 0U}, {180U, 68U, 0U}, {181U, 85U, 0U}, {182U, 1U, 0U}, {183U, 85U, 0U}, {184U, 1U, 0U}, {185U, 5U, 0U}, {186U, 85U, 0U}, {187U, 85U, 0U}, {195U, 0U, 0U}, {196U, 0U, 0U}, {197U, 0U, 0U}, {198U, 0U, 0U}, {199U, 0U, 0U}, {200U, 0U, 0U}, {201U, 0U, 0U}, {202U, 0U, 0U}, {203U, 0U, 0U}, {205U, 0U, 0U}, {206U, 94U, 0U}, {207U, 12U, 0U}, {208U, 12U, 0U}, {209U, 12U, 0U}, {210U, 0U, 0U}, {211U, 43U, 0U}, {212U, 12U, 0U}, {213U, 0U, 0U}, {214U, 112U, 1U}, {219U, 7U, 0U}, {220U, 0U, 0U}, {221U, 0U, 0U}, {222U, 136U, 1U}, {223U, 0U, 0U}, {224U, 31U, 0U}, {225U, 32U, 1U}, {226U, 1U, 0U}, {227U, 48U, 0U}, {228U, 112U, 0U}, {229U, 0U, 0U}, {230U, 0U, 0U}, {231U, 51U, 0U}, {232U, 15U, 1U}, {233U, 15U, 1U}, {234U, 0U, 0U}, {235U, 17U, 0U}, {261U, 60U, 0U}, {262U, 1U, 1U}, {263U, 10U, 0U}, {266U, 0U, 0U}, {267U, 64U, 0U}, {268U, 64U, 0U}, {269U, 136U, 0U}, {270U, 16U, 0U}, {271U, 240U, 0U}, {272U, 16U, 0U}, {273U, 240U, 0U}, {276U, 16U, 0U}, {277U, 85U, 0U}, {278U, 63U, 1U}, {279U, 54U, 1U}, {280U, 0U, 0U}, {281U, 0U, 0U}, {282U, 0U, 0U}, {283U, 135U, 0U}, {284U, 17U, 0U}, {285U, 0U, 0U}, {286U, 51U, 0U}, {287U, 136U, 0U}, {294U, 32U, 1U}, {295U, 63U, 0U}, {296U, 68U, 0U}, {297U, 140U, 0U}, {298U, 108U, 0U}, {299U, 34U, 0U}, {300U, 190U, 0U}, {301U, 85U, 0U}, {303U, 12U, 0U}, {304U, 170U, 0U}, {305U, 2U, 0U}, {306U, 0U, 0U}, {307U, 16U, 0U}, {308U, 1U, 0U}, {309U, 0U, 0U}, {310U, 0U, 0U}, {311U, 128U, 0U}, {312U, 96U, 0U}, {313U, 68U, 0U}, {314U, 85U, 0U}, {315U, 1U, 0U}, {316U, 85U, 0U}, {317U, 1U, 0U}, {318U, 5U, 0U}, {319U, 85U, 0U}, {320U, 85U, 0U}, {328U, 0U, 0U}, {329U, 0U, 0U}, {330U, 0U, 0U}, {331U, 0U, 0U}, {332U, 0U, 0U}, {333U, 0U, 0U}, {334U, 0U, 0U}, {335U, 0U, 0U}, {336U, 0U, 0U}, {340U, 12U, 0U}, {341U, 12U, 0U}, {342U, 12U, 0U}, {343U, 0U, 0U}, {344U, 43U, 0U}, {345U, 132U, 0U}, {346U, 21U, 0U}, {347U, 15U, 0U}, {348U, 0U, 0U}, {349U, 0U, 0U}, {350U, 0U, 1U}, {351U, 0U, 1U}, {352U, 0U, 1U}, {353U, 0U, 1U}, {354U, 0U, 1U}, {355U, 0U, 1U}, {356U, 0U, 0U}, {357U, 0U, 0U}, {358U, 0U, 0U}, {359U, 0U, 0U}, {360U, 0U, 0U}, {361U, 0U, 0U}, {362U, 0U, 1U}, {363U, 0U, 1U}, {364U, 0U, 1U}, {365U, 0U, 0U}, {368U, 0U, 0U}, {369U, 119U, 0U}, {370U, 119U, 0U}, {371U, 119U, 0U}, {372U, 119U, 0U}, {373U, 0U, 0U}, {374U, 3U, 0U}, {375U, 55U, 0U}, {376U, 3U, 0U}, {377U, 0U, 0U}, {379U, 33U, 0U}, {380U, 0U, 0U}, {381U, 170U, 0U}, {382U, 0U, 0U}, {400U, 0U, 0U}, {401U, 119U, 0U}, {402U, 119U, 0U}, {403U, 119U, 0U}, {404U, 119U, 0U}, {405U, 0U, 0U}, {406U, 3U, 0U}, {407U, 55U, 0U}, {408U, 3U, 0U}, {409U, 0U, 0U}, {411U, 33U, 0U}, {412U, 0U, 0U}, {413U, 170U, 0U}, {414U, 0U, 0U}, {417U, 2U, 0U}, {418U, 15U, 0U}, {419U, 15U, 0U}, {420U, 0U, 1U}, {421U, 0U, 1U}, {422U, 0U, 1U}, {423U, 2U, 0U}, {424U, 15U, 0U}, {425U, 15U, 0U}, {426U, 0U, 1U}, {427U, 0U, 1U}, {428U, 0U, 1U}, {429U, 132U, 0U}, {430U, 96U, 0U}, {431U, 71U, 0U}, {432U, 71U, 0U}, {433U, 0U, 0U}, {434U, 0U, 0U}, {435U, 0U, 0U}, {436U, 0U, 0U}, {437U, 0U, 0U}, {438U, 0U, 0U}, {439U, 12U, 1U}, {440U, 0U, 0U}, {441U, 0U, 0U}, {442U, 0U, 0U}, {443U, 0U, 0U}, {444U, 0U, 0U}, {445U, 0U, 0U}, {446U, 0U, 0U}, {447U, 0U, 0U}, {448U, 0U, 0U}, {449U, 1U, 1U}, {450U, 128U, 1U}, {451U, 0U, 0U}, {452U, 0U, 0U}, {453U, 0U, 0U}, {454U, 0U, 0U}, {455U, 0U, 0U}, {456U, 0U, 0U}, {457U, 0U, 0U}, {458U, 0U, 0U}, {65535U, 0U, 0U}}; static struct radio_20xx_regs regs_2057_rev7[413U] = { {0U, 0U, 1U}, {1U, 87U, 1U}, {2U, 32U, 1U}, {3U, 31U, 0U}, {4U, 4U, 0U}, {5U, 2U, 0U}, {6U, 1U, 0U}, {7U, 1U, 0U}, {8U, 1U, 0U}, {9U, 105U, 0U}, {10U, 102U, 0U}, {11U, 6U, 0U}, {12U, 24U, 0U}, {13U, 3U, 0U}, {14U, 32U, 0U}, {15U, 32U, 0U}, {16U, 0U, 0U}, {17U, 124U, 0U}, {18U, 66U, 0U}, {19U, 189U, 0U}, {20U, 7U, 0U}, {21U, 135U, 0U}, {22U, 8U, 0U}, {23U, 23U, 0U}, {24U, 7U, 0U}, {25U, 0U, 0U}, {26U, 2U, 0U}, {27U, 19U, 0U}, {28U, 62U, 0U}, {29U, 62U, 0U}, {30U, 150U, 0U}, {31U, 4U, 0U}, {32U, 0U, 0U}, {33U, 0U, 0U}, {34U, 23U, 0U}, {35U, 6U, 0U}, {36U, 1U, 0U}, {37U, 6U, 0U}, {38U, 4U, 0U}, {39U, 13U, 0U}, {40U, 13U, 0U}, {41U, 48U, 0U}, {42U, 50U, 0U}, {43U, 8U, 0U}, {44U, 28U, 0U}, {45U, 2U, 0U}, {46U, 4U, 0U}, {47U, 127U, 0U}, {48U, 39U, 0U}, {49U, 0U, 1U}, {50U, 0U, 1U}, {51U, 0U, 1U}, {52U, 0U, 0U}, {53U, 32U, 0U}, {54U, 24U, 0U}, {55U, 7U, 0U}, {56U, 102U, 0U}, {57U, 102U, 0U}, {58U, 102U, 0U}, {59U, 102U, 0U}, {60U, 255U, 0U}, {61U, 255U, 0U}, {62U, 255U, 0U}, {63U, 255U, 0U}, {64U, 22U, 0U}, {65U, 7U, 0U}, {66U, 25U, 0U}, {67U, 7U, 0U}, {68U, 6U, 0U}, {69U, 3U, 0U}, {70U, 1U, 0U}, {71U, 7U, 0U}, {72U, 51U, 0U}, {73U, 5U, 0U}, {74U, 119U, 0U}, {75U, 102U, 0U}, {76U, 102U, 0U}, {77U, 0U, 0U}, {78U, 4U, 0U}, {79U, 12U, 0U}, {80U, 0U, 0U}, {81U, 112U, 1U}, {86U, 7U, 0U}, {87U, 0U, 0U}, {88U, 0U, 0U}, {89U, 136U, 1U}, {90U, 0U, 0U}, {91U, 31U, 0U}, {92U, 32U, 1U}, {93U, 1U, 0U}, {94U, 48U, 0U}, {95U, 112U, 0U}, {96U, 0U, 0U}, {97U, 0U, 0U}, {98U, 51U, 1U}, {99U, 15U, 1U}, {100U, 19U, 1U}, {101U, 0U, 0U}, {102U, 238U, 1U}, {105U, 0U, 0U}, {106U, 126U, 0U}, {107U, 63U, 0U}, {108U, 127U, 0U}, {109U, 120U, 0U}, {110U, 88U, 1U}, {111U, 136U, 0U}, {112U, 8U, 0U}, {113U, 15U, 0U}, {114U, 188U, 0U}, {115U, 8U, 0U}, {116U, 96U, 0U}, {117U, 19U, 1U}, {118U, 112U, 0U}, {119U, 0U, 0U}, {120U, 0U, 0U}, {121U, 0U, 0U}, {122U, 51U, 0U}, {123U, 19U, 1U}, {124U, 20U, 1U}, {125U, 238U, 1U}, {128U, 60U, 0U}, {129U, 1U, 1U}, {130U, 10U, 0U}, {131U, 157U, 0U}, {132U, 10U, 0U}, {133U, 0U, 0U}, {134U, 64U, 0U}, {135U, 64U, 0U}, {136U, 136U, 0U}, {137U, 16U, 0U}, {138U, 240U, 0U}, {139U, 16U, 0U}, {140U, 240U, 0U}, {141U, 0U, 0U}, {142U, 0U, 0U}, {143U, 16U, 0U}, {144U, 85U, 0U}, {145U, 63U, 1U}, {146U, 54U, 1U}, {147U, 0U, 0U}, {148U, 0U, 0U}, {149U, 0U, 0U}, {150U, 135U, 0U}, {151U, 17U, 0U}, {152U, 0U, 0U}, {153U, 51U, 0U}, {154U, 136U, 0U}, {155U, 0U, 0U}, {156U, 135U, 0U}, {157U, 17U, 0U}, {158U, 0U, 0U}, {159U, 51U, 0U}, {160U, 136U, 0U}, {161U, 32U, 1U}, {162U, 63U, 0U}, {163U, 68U, 0U}, {164U, 140U, 0U}, {165U, 108U, 0U}, {166U, 34U, 0U}, {167U, 190U, 0U}, {168U, 85U, 0U}, {170U, 12U, 0U}, {171U, 170U, 0U}, {172U, 2U, 0U}, {173U, 0U, 0U}, {174U, 16U, 0U}, {175U, 1U, 0U}, {176U, 0U, 0U}, {177U, 0U, 0U}, {178U, 128U, 0U}, {179U, 96U, 0U}, {180U, 68U, 0U}, {181U, 85U, 0U}, {182U, 1U, 0U}, {183U, 85U, 0U}, {184U, 1U, 0U}, {185U, 5U, 0U}, {186U, 85U, 0U}, {187U, 85U, 0U}, {193U, 0U, 0U}, {194U, 0U, 0U}, {195U, 0U, 0U}, {196U, 0U, 0U}, {197U, 0U, 0U}, {198U, 0U, 0U}, {199U, 0U, 0U}, {200U, 0U, 0U}, {201U, 0U, 0U}, {202U, 0U, 0U}, {203U, 0U, 0U}, {204U, 0U, 0U}, {205U, 0U, 0U}, {206U, 94U, 0U}, {207U, 12U, 0U}, {208U, 12U, 0U}, {209U, 12U, 0U}, {210U, 0U, 0U}, {211U, 43U, 0U}, {212U, 12U, 0U}, {213U, 0U, 0U}, {214U, 112U, 1U}, {219U, 7U, 0U}, {220U, 0U, 0U}, {221U, 0U, 0U}, {222U, 136U, 1U}, {223U, 0U, 0U}, {224U, 31U, 0U}, {225U, 32U, 1U}, {226U, 1U, 0U}, {227U, 48U, 0U}, {228U, 112U, 0U}, {229U, 0U, 0U}, {230U, 0U, 0U}, {231U, 51U, 0U}, {232U, 15U, 1U}, {233U, 19U, 1U}, {234U, 0U, 0U}, {235U, 238U, 1U}, {238U, 0U, 0U}, {239U, 126U, 0U}, {240U, 63U, 0U}, {241U, 127U, 0U}, {242U, 120U, 0U}, {243U, 88U, 1U}, {244U, 136U, 0U}, {245U, 8U, 0U}, {246U, 15U, 0U}, {247U, 188U, 0U}, {248U, 8U, 0U}, {249U, 96U, 0U}, {250U, 19U, 1U}, {251U, 112U, 0U}, {252U, 0U, 0U}, {253U, 0U, 0U}, {254U, 0U, 0U}, {255U, 51U, 0U}, {256U, 19U, 1U}, {257U, 20U, 1U}, {258U, 238U, 1U}, {261U, 60U, 0U}, {262U, 1U, 1U}, {263U, 10U, 0U}, {264U, 157U, 0U}, {265U, 10U, 0U}, {266U, 0U, 0U}, {267U, 64U, 0U}, {268U, 64U, 0U}, {269U, 136U, 0U}, {270U, 16U, 0U}, {271U, 240U, 0U}, {272U, 16U, 0U}, {273U, 240U, 0U}, {274U, 0U, 0U}, {275U, 0U, 0U}, {276U, 16U, 0U}, {277U, 85U, 0U}, {278U, 63U, 1U}, {279U, 54U, 1U}, {280U, 0U, 0U}, {281U, 0U, 0U}, {282U, 0U, 0U}, {283U, 135U, 0U}, {284U, 17U, 0U}, {285U, 0U, 0U}, {286U, 51U, 0U}, {287U, 136U, 0U}, {288U, 0U, 0U}, {289U, 135U, 0U}, {290U, 17U, 0U}, {291U, 0U, 0U}, {292U, 51U, 0U}, {293U, 136U, 0U}, {294U, 32U, 1U}, {295U, 63U, 0U}, {296U, 68U, 0U}, {297U, 140U, 0U}, {298U, 108U, 0U}, {299U, 34U, 0U}, {300U, 190U, 0U}, {301U, 85U, 0U}, {303U, 12U, 0U}, {304U, 170U, 0U}, {305U, 2U, 0U}, {306U, 0U, 0U}, {307U, 16U, 0U}, {308U, 1U, 0U}, {309U, 0U, 0U}, {310U, 0U, 0U}, {311U, 128U, 0U}, {312U, 96U, 0U}, {313U, 68U, 0U}, {314U, 85U, 0U}, {315U, 1U, 0U}, {316U, 85U, 0U}, {317U, 1U, 0U}, {318U, 5U, 0U}, {319U, 85U, 0U}, {320U, 85U, 0U}, {326U, 0U, 0U}, {327U, 0U, 0U}, {328U, 0U, 0U}, {329U, 0U, 0U}, {330U, 0U, 0U}, {331U, 0U, 0U}, {332U, 0U, 0U}, {333U, 0U, 0U}, {334U, 0U, 0U}, {335U, 0U, 0U}, {336U, 0U, 0U}, {337U, 0U, 0U}, {340U, 12U, 0U}, {341U, 12U, 0U}, {342U, 12U, 0U}, {343U, 0U, 0U}, {344U, 43U, 0U}, {345U, 132U, 0U}, {346U, 21U, 0U}, {347U, 15U, 0U}, {348U, 0U, 0U}, {349U, 0U, 0U}, {350U, 0U, 1U}, {351U, 0U, 1U}, {352U, 0U, 1U}, {353U, 0U, 1U}, {354U, 0U, 1U}, {355U, 0U, 1U}, {356U, 0U, 0U}, {357U, 0U, 0U}, {358U, 0U, 0U}, {359U, 0U, 0U}, {360U, 0U, 0U}, {361U, 0U, 0U}, {362U, 0U, 1U}, {363U, 0U, 1U}, {364U, 0U, 1U}, {365U, 0U, 0U}, {368U, 0U, 0U}, {369U, 119U, 0U}, {370U, 119U, 0U}, {371U, 119U, 0U}, {372U, 119U, 0U}, {373U, 0U, 0U}, {374U, 3U, 0U}, {375U, 55U, 0U}, {376U, 3U, 0U}, {377U, 0U, 0U}, {378U, 33U, 0U}, {379U, 33U, 0U}, {380U, 0U, 0U}, {381U, 170U, 0U}, {382U, 0U, 0U}, {383U, 170U, 0U}, {384U, 0U, 0U}, {400U, 0U, 0U}, {401U, 119U, 0U}, {402U, 119U, 0U}, {403U, 119U, 0U}, {404U, 119U, 0U}, {405U, 0U, 0U}, {406U, 3U, 0U}, {407U, 55U, 0U}, {408U, 3U, 0U}, {409U, 0U, 0U}, {410U, 33U, 0U}, {411U, 33U, 0U}, {412U, 0U, 0U}, {413U, 170U, 0U}, {414U, 0U, 0U}, {415U, 170U, 0U}, {416U, 0U, 0U}, {417U, 2U, 0U}, {418U, 15U, 0U}, {419U, 15U, 0U}, {420U, 0U, 1U}, {421U, 0U, 1U}, {422U, 0U, 1U}, {423U, 2U, 0U}, {424U, 15U, 0U}, {425U, 15U, 0U}, {426U, 0U, 1U}, {427U, 0U, 1U}, {428U, 0U, 1U}, {429U, 132U, 0U}, {430U, 96U, 0U}, {431U, 71U, 0U}, {432U, 71U, 0U}, {433U, 0U, 0U}, {434U, 0U, 0U}, {435U, 0U, 0U}, {436U, 0U, 0U}, {437U, 0U, 0U}, {438U, 0U, 0U}, {439U, 5U, 1U}, {440U, 0U, 0U}, {441U, 0U, 0U}, {442U, 0U, 0U}, {443U, 0U, 0U}, {444U, 0U, 0U}, {445U, 0U, 0U}, {446U, 0U, 0U}, {447U, 0U, 0U}, {448U, 0U, 0U}, {449U, 0U, 0U}, {450U, 160U, 1U}, {451U, 0U, 0U}, {452U, 0U, 0U}, {453U, 0U, 0U}, {454U, 0U, 0U}, {455U, 0U, 0U}, {456U, 0U, 0U}, {457U, 0U, 0U}, {458U, 0U, 0U}, {65535U, 0U, 0U}}; static struct radio_20xx_regs regs_2057_rev8[413U] = { {0U, 8U, 1U}, {1U, 87U, 1U}, {2U, 32U, 1U}, {3U, 31U, 0U}, {4U, 4U, 0U}, {5U, 2U, 0U}, {6U, 1U, 0U}, {7U, 1U, 0U}, {8U, 1U, 0U}, {9U, 105U, 0U}, {10U, 102U, 0U}, {11U, 6U, 0U}, {12U, 24U, 0U}, {13U, 3U, 0U}, {14U, 32U, 0U}, {15U, 32U, 0U}, {16U, 0U, 0U}, {17U, 124U, 0U}, {18U, 66U, 0U}, {19U, 189U, 0U}, {20U, 7U, 0U}, {21U, 135U, 0U}, {22U, 8U, 0U}, {23U, 23U, 0U}, {24U, 7U, 0U}, {25U, 0U, 0U}, {26U, 2U, 0U}, {27U, 19U, 0U}, {28U, 62U, 0U}, {29U, 62U, 0U}, {30U, 150U, 0U}, {31U, 4U, 0U}, {32U, 0U, 0U}, {33U, 0U, 0U}, {34U, 23U, 0U}, {35U, 6U, 0U}, {36U, 1U, 0U}, {37U, 6U, 0U}, {38U, 4U, 0U}, {39U, 13U, 0U}, {40U, 13U, 0U}, {41U, 48U, 0U}, {42U, 50U, 0U}, {43U, 8U, 0U}, {44U, 28U, 0U}, {45U, 2U, 0U}, {46U, 4U, 0U}, {47U, 127U, 0U}, {48U, 39U, 0U}, {49U, 0U, 1U}, {50U, 0U, 1U}, {51U, 0U, 1U}, {52U, 0U, 0U}, {53U, 32U, 0U}, {54U, 24U, 0U}, {55U, 7U, 0U}, {56U, 102U, 0U}, {57U, 102U, 0U}, {58U, 102U, 0U}, {59U, 102U, 0U}, {60U, 255U, 0U}, {61U, 255U, 0U}, {62U, 255U, 0U}, {63U, 255U, 0U}, {64U, 22U, 0U}, {65U, 7U, 0U}, {66U, 25U, 0U}, {67U, 7U, 0U}, {68U, 6U, 0U}, {69U, 3U, 0U}, {70U, 1U, 0U}, {71U, 7U, 0U}, {72U, 51U, 0U}, {73U, 5U, 0U}, {74U, 119U, 0U}, {75U, 102U, 0U}, {76U, 102U, 0U}, {77U, 0U, 0U}, {78U, 4U, 0U}, {79U, 12U, 0U}, {80U, 0U, 0U}, {81U, 112U, 1U}, {86U, 7U, 0U}, {87U, 0U, 0U}, {88U, 0U, 0U}, {89U, 136U, 1U}, {90U, 0U, 0U}, {91U, 31U, 0U}, {92U, 32U, 1U}, {93U, 1U, 0U}, {94U, 48U, 0U}, {95U, 112U, 0U}, {96U, 0U, 0U}, {97U, 0U, 0U}, {98U, 51U, 1U}, {99U, 15U, 1U}, {100U, 15U, 1U}, {101U, 0U, 0U}, {102U, 17U, 0U}, {105U, 0U, 0U}, {106U, 126U, 0U}, {107U, 63U, 0U}, {108U, 127U, 0U}, {109U, 120U, 0U}, {110U, 88U, 1U}, {111U, 136U, 0U}, {112U, 8U, 0U}, {113U, 15U, 0U}, {114U, 188U, 0U}, {115U, 8U, 0U}, {116U, 96U, 0U}, {117U, 19U, 1U}, {118U, 112U, 0U}, {119U, 0U, 0U}, {120U, 0U, 0U}, {121U, 0U, 0U}, {122U, 51U, 0U}, {123U, 19U, 1U}, {124U, 15U, 1U}, {125U, 238U, 1U}, {128U, 60U, 0U}, {129U, 1U, 1U}, {130U, 10U, 0U}, {131U, 157U, 0U}, {132U, 10U, 0U}, {133U, 0U, 0U}, {134U, 64U, 0U}, {135U, 64U, 0U}, {136U, 136U, 0U}, {137U, 16U, 0U}, {138U, 240U, 0U}, {139U, 16U, 0U}, {140U, 240U, 0U}, {141U, 0U, 0U}, {142U, 0U, 0U}, {143U, 16U, 0U}, {144U, 85U, 0U}, {145U, 63U, 1U}, {146U, 54U, 1U}, {147U, 0U, 0U}, {148U, 0U, 0U}, {149U, 0U, 0U}, {150U, 135U, 0U}, {151U, 17U, 0U}, {152U, 0U, 0U}, {153U, 51U, 0U}, {154U, 136U, 0U}, {155U, 0U, 0U}, {156U, 135U, 0U}, {157U, 17U, 0U}, {158U, 0U, 0U}, {159U, 51U, 0U}, {160U, 136U, 0U}, {161U, 32U, 1U}, {162U, 63U, 0U}, {163U, 68U, 0U}, {164U, 140U, 0U}, {165U, 108U, 0U}, {166U, 34U, 0U}, {167U, 190U, 0U}, {168U, 85U, 0U}, {170U, 12U, 0U}, {171U, 170U, 0U}, {172U, 2U, 0U}, {173U, 0U, 0U}, {174U, 16U, 0U}, {175U, 1U, 0U}, {176U, 0U, 0U}, {177U, 0U, 0U}, {178U, 128U, 0U}, {179U, 96U, 0U}, {180U, 68U, 0U}, {181U, 85U, 0U}, {182U, 1U, 0U}, {183U, 85U, 0U}, {184U, 1U, 0U}, {185U, 5U, 0U}, {186U, 85U, 0U}, {187U, 85U, 0U}, {193U, 0U, 0U}, {194U, 0U, 0U}, {195U, 0U, 0U}, {196U, 0U, 0U}, {197U, 0U, 0U}, {198U, 0U, 0U}, {199U, 0U, 0U}, {200U, 0U, 0U}, {201U, 1U, 1U}, {202U, 0U, 0U}, {203U, 0U, 0U}, {204U, 0U, 0U}, {205U, 0U, 0U}, {206U, 94U, 0U}, {207U, 12U, 0U}, {208U, 12U, 0U}, {209U, 12U, 0U}, {210U, 0U, 0U}, {211U, 43U, 0U}, {212U, 12U, 0U}, {213U, 0U, 0U}, {214U, 112U, 1U}, {219U, 7U, 0U}, {220U, 0U, 0U}, {221U, 0U, 0U}, {222U, 136U, 1U}, {223U, 0U, 0U}, {224U, 31U, 0U}, {225U, 32U, 1U}, {226U, 1U, 0U}, {227U, 48U, 0U}, {228U, 112U, 0U}, {229U, 0U, 0U}, {230U, 0U, 0U}, {231U, 51U, 0U}, {232U, 15U, 1U}, {233U, 15U, 1U}, {234U, 0U, 0U}, {235U, 17U, 0U}, {238U, 0U, 0U}, {239U, 126U, 0U}, {240U, 63U, 0U}, {241U, 127U, 0U}, {242U, 120U, 0U}, {243U, 88U, 1U}, {244U, 136U, 0U}, {245U, 8U, 0U}, {246U, 15U, 0U}, {247U, 188U, 0U}, {248U, 8U, 0U}, {249U, 96U, 0U}, {250U, 19U, 1U}, {251U, 112U, 0U}, {252U, 0U, 0U}, {253U, 0U, 0U}, {254U, 0U, 0U}, {255U, 51U, 0U}, {256U, 19U, 1U}, {257U, 15U, 1U}, {258U, 238U, 1U}, {261U, 60U, 0U}, {262U, 1U, 1U}, {263U, 10U, 0U}, {264U, 157U, 0U}, {265U, 10U, 0U}, {266U, 0U, 0U}, {267U, 64U, 0U}, {268U, 64U, 0U}, {269U, 136U, 0U}, {270U, 16U, 0U}, {271U, 240U, 0U}, {272U, 16U, 0U}, {273U, 240U, 0U}, {274U, 0U, 0U}, {275U, 0U, 0U}, {276U, 16U, 0U}, {277U, 85U, 0U}, {278U, 63U, 1U}, {279U, 54U, 1U}, {280U, 0U, 0U}, {281U, 0U, 0U}, {282U, 0U, 0U}, {283U, 135U, 0U}, {284U, 17U, 0U}, {285U, 0U, 0U}, {286U, 51U, 0U}, {287U, 136U, 0U}, {288U, 0U, 0U}, {289U, 135U, 0U}, {290U, 17U, 0U}, {291U, 0U, 0U}, {292U, 51U, 0U}, {293U, 136U, 0U}, {294U, 32U, 1U}, {295U, 63U, 0U}, {296U, 68U, 0U}, {297U, 140U, 0U}, {298U, 108U, 0U}, {299U, 34U, 0U}, {300U, 190U, 0U}, {301U, 85U, 0U}, {303U, 12U, 0U}, {304U, 170U, 0U}, {305U, 2U, 0U}, {306U, 0U, 0U}, {307U, 16U, 0U}, {308U, 1U, 0U}, {309U, 0U, 0U}, {310U, 0U, 0U}, {311U, 128U, 0U}, {312U, 96U, 0U}, {313U, 68U, 0U}, {314U, 85U, 0U}, {315U, 1U, 0U}, {316U, 85U, 0U}, {317U, 1U, 0U}, {318U, 5U, 0U}, {319U, 85U, 0U}, {320U, 85U, 0U}, {326U, 0U, 0U}, {327U, 0U, 0U}, {328U, 0U, 0U}, {329U, 0U, 0U}, {330U, 0U, 0U}, {331U, 0U, 0U}, {332U, 0U, 0U}, {333U, 0U, 0U}, {334U, 1U, 1U}, {335U, 0U, 0U}, {336U, 0U, 0U}, {337U, 0U, 0U}, {340U, 12U, 0U}, {341U, 12U, 0U}, {342U, 12U, 0U}, {343U, 0U, 0U}, {344U, 43U, 0U}, {345U, 132U, 0U}, {346U, 21U, 0U}, {347U, 15U, 0U}, {348U, 0U, 0U}, {349U, 0U, 0U}, {350U, 0U, 1U}, {351U, 0U, 1U}, {352U, 0U, 1U}, {353U, 0U, 1U}, {354U, 0U, 1U}, {355U, 0U, 1U}, {356U, 0U, 0U}, {357U, 0U, 0U}, {358U, 0U, 0U}, {359U, 0U, 0U}, {360U, 0U, 0U}, {361U, 0U, 0U}, {362U, 0U, 1U}, {363U, 0U, 1U}, {364U, 0U, 1U}, {365U, 0U, 0U}, {368U, 0U, 0U}, {369U, 119U, 0U}, {370U, 119U, 0U}, {371U, 119U, 0U}, {372U, 119U, 0U}, {373U, 0U, 0U}, {374U, 3U, 0U}, {375U, 55U, 0U}, {376U, 3U, 0U}, {377U, 0U, 0U}, {378U, 33U, 0U}, {379U, 33U, 0U}, {380U, 0U, 0U}, {381U, 170U, 0U}, {382U, 0U, 0U}, {383U, 170U, 0U}, {384U, 0U, 0U}, {400U, 0U, 0U}, {401U, 119U, 0U}, {402U, 119U, 0U}, {403U, 119U, 0U}, {404U, 119U, 0U}, {405U, 0U, 0U}, {406U, 3U, 0U}, {407U, 55U, 0U}, {408U, 3U, 0U}, {409U, 0U, 0U}, {410U, 33U, 0U}, {411U, 33U, 0U}, {412U, 0U, 0U}, {413U, 170U, 0U}, {414U, 0U, 0U}, {415U, 170U, 0U}, {416U, 0U, 0U}, {417U, 2U, 0U}, {418U, 15U, 0U}, {419U, 15U, 0U}, {420U, 0U, 1U}, {421U, 0U, 1U}, {422U, 0U, 1U}, {423U, 2U, 0U}, {424U, 15U, 0U}, {425U, 15U, 0U}, {426U, 0U, 1U}, {427U, 0U, 1U}, {428U, 0U, 1U}, {429U, 132U, 0U}, {430U, 96U, 0U}, {431U, 71U, 0U}, {432U, 71U, 0U}, {433U, 0U, 0U}, {434U, 0U, 0U}, {435U, 0U, 0U}, {436U, 0U, 0U}, {437U, 0U, 0U}, {438U, 0U, 0U}, {439U, 5U, 1U}, {440U, 0U, 0U}, {441U, 0U, 0U}, {442U, 0U, 0U}, {443U, 0U, 0U}, {444U, 0U, 0U}, {445U, 0U, 0U}, {446U, 0U, 0U}, {447U, 0U, 0U}, {448U, 0U, 0U}, {449U, 0U, 0U}, {450U, 160U, 1U}, {451U, 0U, 0U}, {452U, 0U, 0U}, {453U, 0U, 0U}, {454U, 0U, 0U}, {455U, 0U, 0U}, {456U, 0U, 0U}, {457U, 0U, 0U}, {458U, 0U, 0U}, {65535U, 0U, 0U}}; static s16 nphy_def_lnagains[4U] = { -2, 10, 19, 25}; static s32 nphy_lnagain_est0[2U] = { -315, 40370}; static s32 nphy_lnagain_est1[2U] = { -224, 23242}; static u16 const tbl_iqcal_gainparams_nphy[2U][9U][8U] = { { { 0U, 0U, 0U, 2U, 105U, 105U, 105U, 105U}, { 1792U, 7U, 0U, 0U, 105U, 105U, 105U, 105U}, { 1808U, 7U, 1U, 0U, 104U, 104U, 104U, 104U}, { 1824U, 7U, 2U, 0U, 103U, 103U, 103U, 103U}, { 1840U, 7U, 3U, 0U, 102U, 102U, 102U, 102U}, { 1856U, 7U, 4U, 0U, 101U, 101U, 101U, 101U}, { 1857U, 7U, 4U, 1U, 101U, 101U, 101U, 101U}, { 1858U, 7U, 4U, 2U, 101U, 101U, 101U, 101U}, { 1859U, 7U, 4U, 3U, 101U, 101U, 101U, 101U}}, { { 0U, 7U, 0U, 0U, 121U, 121U, 121U, 121U}, { 1792U, 7U, 0U, 0U, 121U, 121U, 121U, 121U}, { 1808U, 7U, 1U, 0U, 121U, 121U, 121U, 121U}, { 1824U, 7U, 2U, 0U, 120U, 120U, 120U, 120U}, { 1840U, 7U, 3U, 0U, 120U, 120U, 120U, 120U}, { 1856U, 7U, 4U, 0U, 120U, 120U, 120U, 120U}, { 1857U, 7U, 4U, 1U, 120U, 120U, 120U, 120U}, { 1858U, 7U, 4U, 2U, 120U, 120U, 120U, 120U}, { 1859U, 7U, 4U, 3U, 120U, 120U, 120U, 120U}}}; static u32 const nphy_tpc_txgain[128U] = { 63712068U, 63712066U, 63711812U, 63711810U, 63711556U, 63449924U, 63449922U, 63449668U, 63449666U, 63449412U, 63449410U, 63449156U, 63449154U, 63187780U, 63187778U, 63187524U, 63187522U, 63187268U, 63187266U, 63187012U, 63187010U, 63186756U, 63186754U, 63186500U, 63186498U, 63186244U, 63186242U, 63185988U, 63185986U, 62925636U, 62925634U, 62925380U, 62925378U, 62925124U, 62925122U, 62924868U, 62924866U, 62924612U, 62924610U, 61877060U, 61877058U, 61876804U, 61876802U, 61876548U, 61876546U, 61876292U, 61876290U, 61876036U, 61876034U, 61875780U, 61875778U, 61875524U, 61875522U, 60828484U, 60828482U, 60828228U, 60828226U, 60827972U, 60827970U, 60827716U, 60827714U, 60827460U, 60827458U, 59779908U, 59779906U, 59779652U, 59779650U, 59779396U, 59779394U, 59779140U, 59779138U, 59778884U, 59778882U, 59778628U, 59778626U, 59778372U, 59778370U, 58731332U, 58731330U, 58731076U, 58731074U, 58730820U, 58730818U, 58730564U, 58730562U, 58730308U, 58730306U, 58730052U, 58730050U, 58729796U, 58729794U, 58729540U, 58729538U, 58729284U, 58729282U, 58729028U, 58729026U, 58728772U, 58728770U, 58728516U, 58728514U, 58728260U, 58728258U, 58728004U, 58728002U, 58727748U, 58727746U, 58727492U, 58727490U, 58727236U, 58727234U, 58726980U, 58726978U, 58726724U, 58726722U, 58726468U, 58726466U, 58726212U, 58726210U, 58725956U, 58725954U, 58725700U, 58725698U, 58725444U, 58725442U, 58725188U, 58725186U, 11008U}; static u16 const nphy_tpc_loscale[128U] = { 256U, 256U, 271U, 271U, 287U, 256U, 256U, 271U, 271U, 287U, 287U, 304U, 304U, 256U, 256U, 271U, 271U, 287U, 287U, 304U, 304U, 322U, 322U, 341U, 341U, 362U, 362U, 383U, 383U, 256U, 256U, 271U, 271U, 287U, 287U, 304U, 304U, 322U, 322U, 256U, 256U, 271U, 271U, 287U, 287U, 304U, 304U, 322U, 322U, 341U, 341U, 362U, 362U, 256U, 256U, 271U, 271U, 287U, 287U, 304U, 304U, 322U, 322U, 256U, 256U, 271U, 271U, 287U, 287U, 304U, 304U, 322U, 322U, 341U, 341U, 362U, 362U, 256U, 256U, 271U, 271U, 287U, 287U, 304U, 304U, 322U, 322U, 341U, 341U, 362U, 362U, 383U, 383U, 406U, 406U, 430U, 430U, 455U, 455U, 482U, 482U, 511U, 511U, 541U, 541U, 573U, 573U, 607U, 607U, 643U, 643U, 681U, 681U, 722U, 722U, 764U, 764U, 810U, 810U, 858U, 858U, 908U, 908U, 962U, 962U, 1019U, 1019U, 256U}; static u32 nphy_tpc_txgain_ipa[128U] = { 1610022957U, 1610022955U, 1610022954U, 1610022953U, 1610022952U, 1610022951U, 1610022950U, 1610022949U, 1593245741U, 1593245739U, 1593245738U, 1593245737U, 1593245736U, 1593245735U, 1593245734U, 1593245733U, 1576468525U, 1576468523U, 1576468522U, 1576468521U, 1576468520U, 1576468519U, 1576468518U, 1576468517U, 1559691309U, 1559691307U, 1559691306U, 1559691305U, 1559691304U, 1559691303U, 1559691302U, 1559691301U, 1542914093U, 1542914091U, 1542914090U, 1542914089U, 1542914088U, 1542914087U, 1542914086U, 1542914085U, 1526136877U, 1526136875U, 1526136874U, 1526136873U, 1526136872U, 1526136871U, 1526136870U, 1526136869U, 1509359661U, 1509359659U, 1509359658U, 1509359657U, 1509359656U, 1509359655U, 1509359654U, 1509359653U, 1492582445U, 1492582443U, 1492582442U, 1492582441U, 1492582440U, 1492582439U, 1492582438U, 1492582437U, 1475805229U, 1475805227U, 1475805226U, 1475805225U, 1475805224U, 1475805223U, 1475805222U, 1475805221U, 1459028013U, 1459028011U, 1459028010U, 1459028009U, 1459028008U, 1459028007U, 1459028006U, 1459028005U, 1442250797U, 1442250795U, 1442250794U, 1442250793U, 1442250792U, 1442250791U, 1442250790U, 1442250789U, 1425473581U, 1425473579U, 1425473578U, 1425473577U, 1425473576U, 1425473575U, 1425473574U, 1425473573U, 1408696365U, 1408696363U, 1408696362U, 1408696361U, 1408696360U, 1408696359U, 1408696358U, 1408696357U, 1391919149U, 1391919147U, 1391919146U, 1391919145U, 1391919144U, 1391919143U, 1391919142U, 1391919141U, 1375141933U, 1375141931U, 1375141930U, 1375141929U, 1375141928U, 1375141927U, 1375141926U, 1375141925U, 1358364717U, 1358364715U, 1358364714U, 1358364713U, 1358364712U, 1358364711U, 1358364710U, 1358364709U}; static u32 nphy_tpc_txgain_ipa_rev5[128U] = { 536281133U, 536281131U, 536281130U, 536281129U, 536281128U, 536281127U, 536281126U, 536281125U, 519503917U, 519503915U, 519503914U, 519503913U, 519503912U, 519503911U, 519503910U, 519503909U, 502726701U, 502726699U, 502726698U, 502726697U, 502726696U, 502726695U, 502726694U, 502726693U, 485949485U, 485949483U, 485949482U, 485949481U, 485949480U, 485949479U, 485949478U, 485949477U, 469172269U, 469172267U, 469172266U, 469172265U, 469172264U, 469172263U, 469172262U, 469172261U, 452395053U, 452395051U, 452395050U, 452395049U, 452395048U, 452395047U, 452395046U, 452395045U, 435617837U, 435617835U, 435617834U, 435617833U, 435617832U, 435617831U, 435617830U, 435617829U, 418840621U, 418840619U, 418840618U, 418840617U, 418840616U, 418840615U, 418840614U, 418840613U, 402063405U, 402063403U, 402063402U, 402063401U, 402063400U, 402063399U, 402063398U, 402063397U, 385286189U, 385286187U, 385286186U, 385286185U, 385286184U, 385286183U, 385286182U, 385286181U, 368508973U, 368508971U, 368508970U, 368508969U, 368508968U, 368508967U, 368508966U, 368508965U, 351731757U, 351731755U, 351731754U, 351731753U, 351731752U, 351731751U, 351731750U, 351731749U, 334954541U, 334954539U, 334954538U, 334954537U, 334954536U, 334954535U, 334954534U, 334954533U, 318177325U, 318177323U, 318177322U, 318177321U, 318177320U, 318177319U, 318177318U, 318177317U, 301400109U, 301400107U, 301400106U, 301400105U, 301400104U, 301400103U, 301400102U, 301400101U, 284622893U, 284622891U, 284622890U, 284622889U, 284622888U, 284622887U, 284622886U, 284622885U}; static u32 nphy_tpc_txgain_ipa_rev6[128U] = { 267845677U, 267845675U, 267845674U, 267845673U, 267845672U, 267845671U, 267845670U, 267845669U, 251068461U, 251068459U, 251068458U, 251068457U, 251068456U, 251068455U, 251068454U, 251068453U, 234291245U, 234291243U, 234291242U, 234291241U, 234291240U, 234291239U, 234291238U, 234291237U, 217514029U, 217514027U, 217514026U, 217514025U, 217514024U, 217514023U, 217514022U, 217514021U, 200736813U, 200736811U, 200736810U, 200736809U, 200736808U, 200736807U, 200736806U, 200736805U, 183959597U, 183959595U, 183959594U, 183959593U, 183959592U, 183959591U, 183959590U, 183959589U, 167182381U, 167182379U, 167182378U, 167182377U, 167182376U, 167182375U, 167182374U, 167182373U, 150405165U, 150405163U, 150405162U, 150405161U, 150405160U, 150405159U, 150405158U, 150405157U, 133627949U, 133627947U, 133627946U, 133627945U, 133627944U, 133627943U, 133627942U, 133627941U, 116850733U, 116850731U, 116850730U, 116850729U, 116850728U, 116850727U, 116850726U, 116850725U, 100073517U, 100073515U, 100073514U, 100073513U, 100073512U, 100073511U, 100073510U, 100073509U, 83296301U, 83296299U, 83296298U, 83296297U, 83296296U, 83296295U, 83296294U, 83296293U, 66519085U, 66519083U, 66519082U, 66519081U, 66519080U, 66519079U, 66519078U, 66519077U, 49741869U, 49741867U, 49741866U, 49741865U, 49741864U, 49741863U, 49741862U, 49741861U, 32964653U, 32964651U, 32964650U, 32964649U, 32964648U, 32964647U, 32964646U, 32964645U, 16187437U, 16187435U, 16187434U, 16187433U, 16187432U, 16187431U, 16187430U, 16187429U}; static u32 nphy_tpc_txgain_ipa_2g_2057rev3[128U] = { 1895759936U, 1895235646U, 1894711355U, 1894187065U, 1893662775U, 1893138486U, 1892614195U, 1892089906U, 1891565617U, 1891041327U, 1890517038U, 1889992749U, 1889468461U, 1888944172U, 1888419884U, 1887895596U, 1887371307U, 1886847020U, 1886322732U, 1885798445U, 1885274158U, 1885274155U, 1885274153U, 1884749866U, 1884749864U, 1884225578U, 1883701292U, 1883701290U, 1883701288U, 1883701286U, 1883701284U, 1883701282U, 1883701279U, 1882652711U, 1882652708U, 1882652706U, 1882652704U, 1882652703U, 1882652701U, 1882652699U, 1882652698U, 1882652696U, 1882652695U, 1881604126U, 1881604125U, 1881604122U, 1881079844U, 1881079842U, 1881079840U, 1881079839U, 1881079837U, 1881079835U, 1881079834U, 1881079832U, 1881079831U, 1881079829U, 1881079828U, 1881079827U, 1881079826U, 1881079825U, 1880555545U, 1880555544U, 1880555542U, 1880555541U, 1880555540U, 1880555539U, 1880555538U, 1880555536U, 1880555536U, 1880555535U, 1880031261U, 1880031259U, 1880031258U, 1880031256U, 1880031255U, 1880031253U, 1880031253U, 1880031251U, 1880031251U, 1880031249U, 1880031248U, 1880031248U, 1880031247U, 1880031246U, 1880031245U, 1880031244U, 1880031243U, 1880031243U, 1880031243U, 1880031242U, 1880031241U, 1880031241U, 1880031241U, 1880031240U, 1880031239U, 1880031239U, 1880031238U, 1880031238U, 1880031238U, 1880031238U, 1880031237U, 1880031237U, 1880031237U, 1880031236U, 1880031236U, 1880031236U, 1880031236U, 1880031236U, 1880031236U, 1880031235U, 1880031235U, 1880031235U, 1880031235U, 1880031234U, 1880031234U, 1880031234U, 1880031234U, 1880031234U, 1880031234U, 1880031233U, 1880031233U, 1880031233U, 1880031233U, 1880031233U, 1880031233U, 1880031233U, 1880031233U, 1880031233U}; static u32 nphy_tpc_txgain_ipa_2g_2057rev4n6[128U] = { 4043243584U, 4042719294U, 4042195003U, 4041670713U, 4041146423U, 4040622134U, 4040097843U, 4039573554U, 4039049265U, 4038524975U, 4038000686U, 4037476397U, 4036952109U, 4036427820U, 4035903532U, 4035379244U, 4034854955U, 4034330668U, 4033806380U, 4033282093U, 4032757806U, 4032757803U, 4032757801U, 4032233514U, 4032233512U, 4031709226U, 4031184940U, 4031184938U, 4031184936U, 4031184934U, 4031184932U, 4031184930U, 4031184927U, 4030136359U, 4030136356U, 4030136354U, 4030136352U, 4030136351U, 4030136349U, 4030136347U, 4030136346U, 4030136344U, 4030136343U, 4029087774U, 4029087773U, 4029087770U, 4028563492U, 4028563490U, 4028563488U, 4028563487U, 4028563485U, 4028563483U, 4028563482U, 4028563480U, 4028563479U, 4028563477U, 4028563476U, 4028563475U, 4028563474U, 4028563473U, 4028039193U, 4028039192U, 4028039190U, 4028039189U, 4028039188U, 4028039187U, 4028039186U, 4028039184U, 4028039184U, 4028039183U, 4027514909U, 4027514907U, 4027514906U, 4027514904U, 4027514903U, 4027514901U, 4027514901U, 4027514899U, 4027514899U, 4027514897U, 4027514896U, 4027514896U, 4027514895U, 4027514894U, 4027514893U, 4027514892U, 4027514891U, 4027514891U, 4027514891U, 4027514890U, 4027514889U, 4027514889U, 4027514889U, 4027514888U, 4027514887U, 4027514887U, 4027514886U, 4027514886U, 4027514886U, 4027514886U, 4027514885U, 4027514885U, 4027514885U, 4027514884U, 4027514884U, 4027514884U, 4027514884U, 4027514884U, 4027514884U, 4027514883U, 4027514883U, 4027514883U, 4027514883U, 4027514882U, 4027514882U, 4027514882U, 4027514882U, 4027514882U, 4027514882U, 4027514881U, 4027514881U, 4027514881U, 4027514881U, 4027514881U, 4027514881U, 4027514881U, 4027514881U, 4027514881U}; static u32 nphy_tpc_txgain_ipa_2g_2057rev5[128U] = { 822018097U, 820445233U, 820445230U, 818872366U, 817823790U, 816775214U, 815726639U, 813629491U, 813629489U, 813629486U, 813105198U, 812580910U, 812056622U, 811532335U, 811008048U, 811008045U, 810483758U, 809959473U, 809959470U, 809959468U, 809959465U, 809435180U, 809435177U, 808910893U, 808910890U, 808910888U, 808386604U, 808386602U, 808386600U, 808386598U, 807862316U, 807862313U, 807862311U, 807862309U, 807862307U, 807338028U, 807338026U, 807338024U, 807338021U, 807338020U, 807338018U, 807338015U, 806813741U, 806813739U, 806813736U, 806813734U, 806813732U, 806813730U, 806813728U, 806813726U, 806813725U, 806813723U, 806813722U, 806813720U, 806813719U, 806813717U, 806289452U, 806289449U, 806289447U, 806289444U, 806289442U, 806289441U, 806289439U, 806289437U, 806289435U, 806289434U, 806289432U, 806289431U, 806289430U, 806289429U, 806289685U, 806289941U, 806290197U, 806290453U, 806290709U, 806290965U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U}; static u32 nphy_tpc_txgain_ipa_2g_2057rev7[128U] = { 822018097U, 820445233U, 820445230U, 818872366U, 817823790U, 816775214U, 815726639U, 813629491U, 813629489U, 813629486U, 813105198U, 812580910U, 812056622U, 811532335U, 811008048U, 811008045U, 810483758U, 809959473U, 809959470U, 809959468U, 809959465U, 809435180U, 809435177U, 808910893U, 808910890U, 808910888U, 808386604U, 808386602U, 808386600U, 808386598U, 807862316U, 807862313U, 807862311U, 807862309U, 807862307U, 807338028U, 807338026U, 807338024U, 807338021U, 807338020U, 807338018U, 807338015U, 806813741U, 806813739U, 806813736U, 806813734U, 806813732U, 806813730U, 806813728U, 806813726U, 806813725U, 806813723U, 806813722U, 806813720U, 806813719U, 806813717U, 806289452U, 806289449U, 806289447U, 806289444U, 806289442U, 806289441U, 806289439U, 806289437U, 806289435U, 806289434U, 806289432U, 806289431U, 806289430U, 806289429U, 806289685U, 806289941U, 806290197U, 806290453U, 806290709U, 806290965U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U, 806291221U}; static u32 nphy_tpc_txgain_ipa_5g[128U] = { 2146893877U, 2146893875U, 2146893874U, 2146893873U, 2146893871U, 2146893870U, 2146893869U, 2146893867U, 2146893866U, 2146893865U, 2146893864U, 2146893863U, 2146893862U, 2146893860U, 2146893859U, 2146893858U, 2130116648U, 2130116647U, 2130116646U, 2130116645U, 2130116644U, 2130116643U, 2113339432U, 2113339431U, 2113339430U, 2113339429U, 2113339428U, 2113339427U, 2113339426U, 2096562217U, 2096562216U, 2096562215U, 2096562214U, 2096562213U, 2096562211U, 2096562210U, 2079785001U, 2079785000U, 2079784998U, 2079784997U, 2079784996U, 2079784995U, 2079784994U, 2079784993U, 2063007785U, 2063007784U, 2063007783U, 2063007782U, 2063007781U, 2063007780U, 2063007779U, 2063007778U, 2046230569U, 2046230568U, 2046230567U, 2046230566U, 2046230565U, 2046230564U, 2046230563U, 2046230562U, 2029453353U, 2029453352U, 2029453351U, 2029453350U, 2029453349U, 2029453348U, 2029453347U, 2029453346U, 2012676137U, 2012676136U, 2012676135U, 2012676134U, 2012676133U, 2012676132U, 2012676131U, 2012676130U, 1995898921U, 1995898920U, 1995898919U, 1995898918U, 1995898916U, 1995898915U, 1995898914U, 1995898913U, 1979121705U, 1979121704U, 1979121703U, 1979121702U, 1979121701U, 1979121700U, 1979121699U, 1962344489U, 1962344488U, 1962344486U, 1962344485U, 1962344484U, 1962344483U, 1962344482U, 1945567273U, 1945567271U, 1945567270U, 1945567269U, 1945567268U, 1945567267U, 1945567266U, 1928790056U, 1928790055U, 1928790054U, 1928790053U, 1928790052U, 1928790051U, 1928790050U, 1912012840U, 1912012839U, 1912012838U, 1912012837U, 1912012836U, 1912012835U, 1895235624U, 1895235623U, 1895235622U, 1895235620U, 1895235619U, 1895235618U, 1895235617U, 1895235616U, 1895235616U, 1895235615U}; static u32 nphy_tpc_txgain_ipa_5g_2057[128U] = { 2139029572U, 2139029568U, 2139029564U, 2139029561U, 2139029558U, 2122252348U, 2122252344U, 2122252341U, 2105475132U, 2105475129U, 2105475126U, 2105475123U, 2088697915U, 2088697911U, 2088697908U, 2071920698U, 2071920694U, 2071920691U, 2055143484U, 2055143481U, 2055143478U, 2055143475U, 2038366267U, 2038366264U, 2038366261U, 2038366258U, 2021589051U, 2021589048U, 2021589045U, 2021589042U, 2004811834U, 2004811831U, 2004811828U, 2004811825U, 1988034618U, 1988034614U, 1988034611U, 1988034609U, 1971257402U, 1971257399U, 1971257396U, 1954480188U, 1954480185U, 1954480182U, 1954480179U, 1937702971U, 1937702968U, 1937702965U, 1937702962U, 1920925753U, 1920925750U, 1920925747U, 1920925744U, 1904148538U, 1904148535U, 1904148532U, 1887371323U, 1887371320U, 1887371317U, 1887371314U, 1887371311U, 1887371309U, 1887371306U, 1887371304U, 1887371301U, 1887371299U, 1887371297U, 1887371296U, 1887371294U, 1887371292U, 1887371291U, 1887371289U, 1887371288U, 1887371286U, 1887371285U, 1887371284U, 1887371283U, 1887371282U, 1887371281U, 1887371280U, 1887371279U, 1887371278U, 1887371277U, 1887371277U, 1887371276U, 1887371275U, 1887371275U, 1887371274U, 1887371273U, 1887371273U, 1887371272U, 1887371272U, 1887371271U, 1887371271U, 1887371271U, 1887371270U, 1887371270U, 1887371270U, 1887371269U, 1887371269U, 1887371269U, 1887371268U, 1887371268U, 1887371268U, 1887371268U, 1887371268U, 1887371267U, 1887371267U, 1887371267U, 1887371267U, 1887371267U, 1887371267U, 1887371266U, 1887371266U, 1887371266U, 1887371266U, 1887371266U, 1887371266U, 1887371266U, 1887371266U, 1887371265U, 1887371265U, 1887371265U, 1887371265U, 1887371265U, 1887371265U, 1887371265U, 1887371265U}; static u32 nphy_tpc_txgain_ipa_5g_2057rev7[128U] = { 1870594097U, 1870594094U, 1870594092U, 1870594090U, 1870594087U, 1853816878U, 1853816876U, 1853816874U, 1837039664U, 1837039661U, 1837039658U, 1837039656U, 1820262448U, 1820262445U, 1820262443U, 1803485230U, 1803485228U, 1803485226U, 1803485223U, 1786708014U, 1786708012U, 1786708010U, 1769930800U, 1769930798U, 1769930795U, 1769930793U, 1753153583U, 1753153581U, 1753153578U, 1753153575U, 1736376367U, 1736376365U, 1736376362U, 1719599153U, 1719599150U, 1719599148U, 1719599146U, 1702821936U, 1702821934U, 1702821931U, 1702821929U, 1686044720U, 1686044717U, 1686044715U, 1686044713U, 1669267503U, 1669267501U, 1669267498U, 1652490288U, 1652490285U, 1652490283U, 1652490281U, 1635713072U, 1635713070U, 1635713067U, 1635713065U, 1618935855U, 1618935853U, 1618935850U, 1618935847U, 1618935846U, 1618935843U, 1618935841U, 1618935840U, 1618935838U, 1618935836U, 1618935834U, 1618935833U, 1618935832U, 1618935830U, 1618935829U, 1618935828U, 1618935826U, 1618935826U, 1618935825U, 1618935823U, 1618935823U, 1618935822U, 1618935821U, 1618935820U, 1618935820U, 1618935819U, 1618935819U, 1618935818U, 1618935817U, 1618935817U, 1618935816U, 1618935816U, 1618935816U, 1618935815U, 1618935815U, 1618935814U, 1618935814U, 1618935813U, 1618935813U, 1618935813U, 1618935813U, 1618935813U, 1618935812U, 1618935812U, 1618935812U, 1618935812U, 1618935811U, 1618935811U, 1618935811U, 1618935811U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935810U, 1618935809U, 1618935809U, 1618935809U, 1618935809U, 1618935809U, 1618935809U, 1618935809U}; static s8 nphy_papd_pga_gain_delta_ipa_2g[16U] = { -114, -108, -98, -91, -84, -78, -70, -62, -54, -46, -39, -31, -23, -15, -8, 0}; static s8 nphy_papd_pga_gain_delta_ipa_5g[16U] = { -100, -95, -89, -83, -77, -70, -63, -56, -48, -41, -33, -25, -19, -12, -6, 0}; static s16 nphy_papd_padgain_dlt_2g_2057rev3n4[32U] = { -159, -113, -86, -72, -62, -54, -48, -43, -39, -35, -31, -28, -25, -23, -20, -18, -17, -15, -13, -11, -10, -8, -7, -6, -5, -4, -3, -3, -2, -1, -1, 0}; static s16 nphy_papd_padgain_dlt_2g_2057rev5[32U] = { -109, -109, -82, -68, -58, -50, -44, -39, -35, -31, -28, -26, -23, -21, -19, -17, -16, -14, -13, -11, -10, -9, -8, -7, -5, -5, -4, -3, -2, -1, -1, 0}; static s16 nphy_papd_padgain_dlt_2g_2057rev7[32U] = { -122, -122, -95, -80, -69, -61, -54, -49, -43, -39, -35, -32, -28, -26, -23, -21, -18, -16, -15, -13, -11, -10, -8, -7, -6, -5, -4, -3, -2, -1, -1, 0}; static s8 nphy_papd_pgagain_dlt_5g_2057[16U] = { -107, -101, -92, -85, -78, -71, -62, -55, -47, -39, -32, -24, -19, -12, -6, 0}; static s8 nphy_papd_pgagain_dlt_5g_2057rev7[16U] = { -110, -104, -95, -88, -81, -74, -66, -58, -50, -44, -36, -28, -23, -15, -8, 0}; static u8 pad_gain_codes_used_2057rev5[20U] = { 20U, 19U, 18U, 17U, 16U, 15U, 14U, 13U, 12U, 11U, 10U, 9U, 8U, 7U, 6U, 5U, 4U, 3U, 2U, 1U}; static u8 pad_gain_codes_used_2057rev7[15U] = { 15U, 14U, 13U, 12U, 11U, 10U, 9U, 8U, 7U, 6U, 5U, 4U, 3U, 2U, 1U}; static u8 pad_all_gain_codes_2057[32U] = { 31U, 30U, 29U, 28U, 27U, 26U, 25U, 24U, 23U, 22U, 21U, 20U, 19U, 18U, 17U, 16U, 15U, 14U, 13U, 12U, 11U, 10U, 9U, 8U, 7U, 6U, 5U, 4U, 3U, 2U, 1U, 0U}; static u8 pga_all_gain_codes_2057[16U] = { 15U, 14U, 13U, 12U, 11U, 10U, 9U, 8U, 7U, 6U, 5U, 4U, 3U, 2U, 1U, 0U}; static u32 nphy_papd_scaltbl[64U] = { 182583343U, 171638834U, 161939509U, 153223224U, 143065148U, 136249407U, 128057411U, 120848455U, 114425931U, 108658767U, 102170708U, 96403545U, 91291742U, 85852260U, 80937066U, 76611696U, 72089719U, 68092030U, 64553093U, 60883085U, 57606293U, 54329502U, 51052712U, 48234674U, 45678780U, 43122887U, 40698067U, 38338784U, 36241645U, 34210043U, 32243978U, 30408986U, 28770602U, 27132220U, 25624911U, 24248674U, 22872439U, 21561742U, 20382117U, 19268030U, 18153945U, 17105397U, 16187922U, 15270450U, 14418515U, 13632118U, 12845724U, 12124867U, 11469549U, 10814234U, 10224457U, 9634682U, 9110447U, 8586215U, 8127522U, 7668833U, 7210147U, 6817002U, 6423860U, 6096259U, 5768663U, 5441071U, 5113485U, 4851441U}; static u32 nphy_tpc_txgain_rev3[128U] = { 524353604U, 524353602U, 524353600U, 524353598U, 524353596U, 524353595U, 524353593U, 524353591U, 507576388U, 507576386U, 507576384U, 507576382U, 507576380U, 507576379U, 507576377U, 507576375U, 490799172U, 490799170U, 490799168U, 490799166U, 490799164U, 490799163U, 490799161U, 490799159U, 474021956U, 474021954U, 474021952U, 474021950U, 474021948U, 474021947U, 474021945U, 474021943U, 457244740U, 457244738U, 457244736U, 457244734U, 457244732U, 457244731U, 457244729U, 457244727U, 440467524U, 440467522U, 440467520U, 440467518U, 440467516U, 440467515U, 440467513U, 440467511U, 423690308U, 423690306U, 423690304U, 423690302U, 423690300U, 423690299U, 423690297U, 423690295U, 406913092U, 406913090U, 406913088U, 406913086U, 406913084U, 406913083U, 406913081U, 406913079U, 390135876U, 390135874U, 390135872U, 390135870U, 390135868U, 390135867U, 390135865U, 390135863U, 373358660U, 373358658U, 373358656U, 373358654U, 373358652U, 373358651U, 373358649U, 373358647U, 356581444U, 356581442U, 356581440U, 356581438U, 356581436U, 356581435U, 356581433U, 356581431U, 339804228U, 339804226U, 339804224U, 339804222U, 339804220U, 339804219U, 339804217U, 339804215U, 323027012U, 323027010U, 323027008U, 323027006U, 323027004U, 323027003U, 323027001U, 323026999U, 306249796U, 306249794U, 306249792U, 306249790U, 306249788U, 306249787U, 306249785U, 306249783U, 289472580U, 289472578U, 289472576U, 289472574U, 289472572U, 289472571U, 289472569U, 289472567U, 272695364U, 272695362U, 272695360U, 272695358U, 272695356U, 272695355U, 272695353U, 272695351U}; static u32 nphy_tpc_txgain_HiPwrEPA[128U] = { 255918148U, 255918146U, 255918144U, 255918142U, 255918140U, 255918139U, 255918137U, 255918135U, 239140932U, 239140930U, 239140928U, 239140926U, 239140924U, 239140923U, 239140921U, 239140919U, 222363716U, 222363714U, 222363712U, 222363710U, 222363708U, 222363707U, 222363705U, 222363703U, 205586500U, 205586498U, 205586496U, 205586494U, 205586492U, 205586491U, 205586489U, 205586487U, 188809284U, 188809282U, 188809280U, 188809278U, 188809276U, 188809275U, 188809273U, 188809271U, 172032068U, 172032066U, 172032064U, 172032062U, 172032060U, 172032059U, 172032057U, 172032055U, 155254852U, 155254850U, 155254848U, 155254846U, 155254844U, 155254843U, 155254841U, 155254839U, 138477636U, 138477634U, 138477632U, 138477630U, 138477628U, 138477627U, 138477625U, 138477623U, 121700420U, 121700418U, 121700416U, 121700414U, 121700412U, 121700411U, 121700409U, 121700407U, 104923204U, 104923202U, 104923200U, 104923198U, 104923196U, 104923195U, 104923193U, 104923191U, 88145988U, 88145986U, 88145984U, 88145982U, 88145980U, 88145979U, 88145977U, 88145975U, 71368772U, 71368770U, 71368768U, 71368766U, 71368764U, 71368763U, 71368761U, 71368759U, 54591556U, 54591554U, 54591552U, 54591550U, 54591548U, 54591547U, 54591545U, 54591543U, 37814340U, 37814338U, 37814336U, 37814334U, 37814332U, 37814331U, 37814329U, 37814327U, 21037124U, 21037122U, 21037120U, 21037118U, 21037116U, 21037115U, 21037113U, 21037111U, 4259908U, 4259906U, 4259904U, 4259902U, 4259900U, 4259899U, 4259897U, 4259895U}; static u32 nphy_tpc_txgain_epa_2057rev3[128U] = { 2163802176U, 2162229312U, 2162229308U, 2160656445U, 2159607868U, 2158559293U, 2158035004U, 2157510715U, 2156986427U, 2156462138U, 2155937850U, 2155413561U, 2154889273U, 2154364986U, 2153840699U, 2153316413U, 2152792127U, 2152267842U, 2152267838U, 2152267835U, 2151743550U, 2151743547U, 2151219262U, 2151219259U, 2151219256U, 2151219253U, 2150694970U, 2150694966U, 2150694963U, 2150170682U, 2150170679U, 2150170676U, 2150170673U, 2149646393U, 2149646390U, 2149646387U, 2149646384U, 2149122108U, 2149122105U, 2149122102U, 2149122099U, 2149122096U, 2149122093U, 2149122091U, 2149122088U, 2148597818U, 2148597814U, 2148597811U, 2148597808U, 2148597806U, 2148597803U, 2148597801U, 2148597799U, 2148597796U, 2148597794U, 2148597792U, 2148597791U, 2148597789U, 2148073530U, 2148073527U, 2148073524U, 2148073521U, 2148073518U, 2148073516U, 2148073513U, 2148073511U, 2148073509U, 2148073507U, 2148073505U, 2148073503U, 2148073501U, 2148073757U, 2148074013U, 2148074269U, 2148074525U, 2148074781U, 2148075037U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U, 2148075293U}; static u32 nphy_tpc_txgain_epa_2057rev5[128U] = { 284753984U, 283181120U, 283181116U, 281608253U, 280559676U, 279511101U, 278986812U, 278462523U, 277938235U, 277413946U, 276889658U, 276365369U, 275841081U, 275316794U, 274792507U, 274268221U, 273743935U, 273219650U, 273219646U, 273219643U, 272695358U, 272695355U, 272171070U, 272171067U, 272171064U, 272171061U, 271646778U, 271646774U, 271646771U, 271122490U, 271122487U, 271122484U, 271122481U, 270598201U, 270598198U, 270598195U, 270598192U, 270073916U, 270073913U, 270073910U, 270073907U, 270073904U, 270073901U, 270073899U, 270073896U, 269549626U, 269549622U, 269549619U, 269549616U, 269549614U, 269549611U, 269549609U, 269549607U, 269549604U, 269549602U, 269549600U, 269549599U, 269549597U, 269025338U, 269025335U, 269025332U, 269025329U, 269025326U, 269025324U, 269025321U, 269025319U, 269025317U, 269025315U, 269025313U, 269025311U, 269025309U, 269025307U, 269025306U, 269025304U, 269025303U, 269025302U, 269025301U, 269025299U, 269025298U, 269025297U, 269025296U, 269025295U, 269025295U, 269025294U, 269025293U, 269025292U, 269025292U, 269025291U, 269025290U, 269025290U, 269025289U, 269025289U, 269025288U, 269025288U, 269025287U, 269025287U, 269025287U, 269025286U, 269025286U, 269025285U, 269025285U, 269025285U, 269025285U, 269025284U, 269025284U, 269025284U, 269025284U, 269025283U, 269025283U, 269025283U, 269025283U, 269025283U, 269025283U, 269025282U, 269025282U, 269025282U, 269025282U, 269025282U, 269025282U, 269025282U, 269025282U, 269025282U, 269025281U, 269025281U, 269025281U, 269025281U, 269025281U, 269025281U}; static u32 nphy_tpc_5GHz_txgain_rev3[128U] = { 3489071172U, 3489071170U, 3489071168U, 3489071166U, 3489071164U, 3489071163U, 3489071161U, 3489071159U, 3472293956U, 3472293954U, 3472293952U, 3472293950U, 3472293948U, 3472293947U, 3472293945U, 3472293943U, 3455516740U, 3455516738U, 3455516736U, 3455516734U, 3455516732U, 3455516731U, 3455516729U, 3455516727U, 3438739524U, 3438739522U, 3438739520U, 3438739518U, 3438739516U, 3438739515U, 3438739513U, 3438739511U, 3421962308U, 3421962306U, 3421962304U, 3421962302U, 3421962300U, 3421962299U, 3421962297U, 3421962295U, 3405185092U, 3405185090U, 3405185088U, 3405185086U, 3405185084U, 3405185083U, 3405185081U, 3405185079U, 3388407876U, 3388407874U, 3388407872U, 3388407870U, 3388407868U, 3388407867U, 3388407865U, 3388407863U, 3371630660U, 3371630658U, 3371630656U, 3371630654U, 3371630652U, 3371630651U, 3371630649U, 3371630647U, 3354853444U, 3354853442U, 3354853440U, 3354853438U, 3354853436U, 3354853435U, 3354853433U, 3354853431U, 3338076228U, 3338076226U, 3338076224U, 3338076222U, 3338076220U, 3338076219U, 3338076217U, 3338076215U, 3321299012U, 3321299010U, 3321299008U, 3321299006U, 3321299004U, 3321299003U, 3321299001U, 3321298999U, 3304521796U, 3304521794U, 3304521792U, 3304521790U, 3304521788U, 3304521787U, 3304521785U, 3304521783U, 3287744580U, 3287744578U, 3287744576U, 3287744574U, 3287744572U, 3287744571U, 3287744569U, 3287744567U, 3270967364U, 3270967362U, 3270967360U, 3270967358U, 3270967356U, 3270967355U, 3270967353U, 3270967351U, 3254190148U, 3254190146U, 3254190144U, 3254190142U, 3254190140U, 3254190139U, 3254190137U, 3254190135U, 3237412932U, 3237412930U, 3237412928U, 3237412926U, 3237412924U, 3237412923U, 3237412921U, 3237412919U}; static u32 nphy_tpc_5GHz_txgain_rev4[128U] = { 804388932U, 804388930U, 804388928U, 804388926U, 804388924U, 804388923U, 804388921U, 804388919U, 787611716U, 787611714U, 787611712U, 787611710U, 787611708U, 787611707U, 787611705U, 787611703U, 770834500U, 770834498U, 770834496U, 770834494U, 770834492U, 770834491U, 770834489U, 770834487U, 754057284U, 754057282U, 754057280U, 754057278U, 754057276U, 754057275U, 754057273U, 754057271U, 737280068U, 737280066U, 737280064U, 737280062U, 737280060U, 737280059U, 737280057U, 737280055U, 720502852U, 720502850U, 720502848U, 720502846U, 720502844U, 720502843U, 720502841U, 720502839U, 703725636U, 703725634U, 703725632U, 703725630U, 703725628U, 703725627U, 703725625U, 703725623U, 686948420U, 686948418U, 686948416U, 686948414U, 686948412U, 686948411U, 686948409U, 686948407U, 670171204U, 670171202U, 670171200U, 670171198U, 670171196U, 670171195U, 670171193U, 670171191U, 653393988U, 653393986U, 653393984U, 653393982U, 653393980U, 653393979U, 653393977U, 653393975U, 636616772U, 636616770U, 636616768U, 636616766U, 636616764U, 636616763U, 636616761U, 636616759U, 619839556U, 619839554U, 619839552U, 619839550U, 619839548U, 619839547U, 619839545U, 619839544U, 603062337U, 603062336U, 603062335U, 603062334U, 603062332U, 603062331U, 603062329U, 603062327U, 586285124U, 586285122U, 586285120U, 586285118U, 586285116U, 586285115U, 586285113U, 586285111U, 569507908U, 569507906U, 569507904U, 569507902U, 569507900U, 569507899U, 569507897U, 569507895U, 550633539U, 550633537U, 550633534U, 550633532U, 550633530U, 550633528U, 550633526U, 550633524U}; static u32 nphy_tpc_5GHz_txgain_rev5[128U] = { 258080842U, 258080840U, 258080838U, 258080836U, 258080834U, 258080832U, 258080830U, 258080828U, 241303620U, 241303618U, 241303616U, 241303614U, 241303612U, 241303613U, 241303611U, 241303610U, 224526403U, 224526401U, 224526400U, 224526398U, 224526397U, 224526396U, 224526395U, 224526394U, 207749185U, 207749184U, 207749183U, 207749182U, 207749180U, 207749179U, 207749177U, 207749175U, 190971974U, 190971972U, 190971970U, 190971968U, 190971966U, 190971964U, 190971963U, 190971962U, 174194753U, 174194752U, 174194750U, 174194748U, 174194747U, 174194746U, 174194745U, 174194744U, 157417534U, 157417533U, 157417532U, 157417531U, 157417529U, 157417527U, 157417525U, 157417523U, 140640324U, 140640322U, 140640320U, 140640318U, 140640316U, 140640315U, 140640314U, 140640313U, 123863107U, 123863106U, 123863104U, 123863103U, 123863101U, 123863099U, 123863098U, 123863097U, 107085886U, 107085885U, 107085884U, 107085883U, 107085881U, 107085879U, 107085877U, 107085875U, 90308678U, 90308676U, 90308674U, 90308672U, 90308670U, 90308668U, 90308667U, 90308665U, 73531460U, 73531458U, 73531456U, 73531454U, 73531452U, 73531451U, 73531449U, 73531448U, 56754236U, 56754235U, 56754234U, 56754233U, 56754232U, 56754231U, 56754229U, 56754227U, 39977036U, 39977034U, 39977032U, 39977031U, 39977030U, 39977028U, 39977027U, 39977026U, 23199818U, 23199816U, 23199814U, 23199812U, 23199811U, 23199810U, 23199809U, 23199808U, 6422594U, 6422592U, 6422590U, 6422588U, 6422587U, 6422585U, 6422583U, 6422581U}; static u32 nphy_tpc_5GHz_txgain_HiPwrEPA[128U] = { 804323396U, 804323394U, 804323392U, 804323390U, 804323388U, 804323387U, 804323385U, 804323383U, 787546180U, 787546178U, 787546176U, 787546174U, 787546172U, 787546171U, 787546169U, 787546167U, 770768964U, 770768962U, 770768960U, 770768958U, 770768956U, 770768955U, 770768953U, 770768951U, 753991748U, 753991746U, 753991744U, 753991742U, 753991740U, 753991739U, 753991737U, 753991735U, 737214532U, 737214530U, 737214528U, 737214526U, 737214524U, 737214523U, 737214521U, 737214519U, 720437316U, 720437314U, 720437312U, 720437310U, 720437308U, 720437307U, 720437305U, 720437303U, 703660100U, 703660098U, 703660096U, 703660094U, 703660092U, 703660091U, 703660089U, 703660087U, 686882884U, 686882882U, 686882880U, 686882878U, 686882876U, 686882875U, 686882873U, 686882871U, 670105668U, 670105666U, 670105664U, 670105662U, 670105660U, 670105659U, 670105657U, 670105655U, 653328452U, 653328450U, 653328448U, 653328446U, 653328444U, 653328443U, 653328441U, 653328439U, 636551236U, 636551234U, 636551232U, 636551230U, 636551228U, 636551227U, 636551225U, 636551223U, 619774020U, 619774018U, 619774016U, 619774014U, 619774012U, 619774011U, 619774009U, 619774008U, 602996801U, 602996800U, 602996799U, 602996798U, 602996796U, 602996795U, 602996793U, 602996791U, 586219588U, 586219586U, 586219584U, 586219582U, 586219580U, 586219579U, 586219577U, 586219575U, 569442372U, 569442370U, 569442368U, 569442366U, 569442364U, 569442363U, 569442361U, 569442359U, 550568003U, 550568001U, 550567998U, 550567996U, 550567994U, 550567992U, 550567990U, 550567988U}; static u8 ant_sw_ctrl_tbl_rev8_2o3[2U] = { 20U, 24U}; static u8 ant_sw_ctrl_tbl_rev8[6U] = { 4U, 8U, 4U, 8U, 17U, 18U}; static u8 ant_sw_ctrl_tbl_rev8_2057v7_core0[6U] = { 9U, 10U, 21U, 22U, 9U, 10U}; static u8 ant_sw_ctrl_tbl_rev8_2057v7_core1[6U] = { 9U, 10U, 9U, 10U, 21U, 22U}; bool wlc_phy_bist_check_phy(struct brcms_phy_pub *pih ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u32 phybist0 ; u32 phybist1 ; u32 phybist2 ; u32 phybist3 ; u32 phybist4 ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; u16 tmp___3 ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; tmp = read_phy_reg(pi, 14); phybist0 = (u32 )tmp; tmp___0 = read_phy_reg(pi, 15); phybist1 = (u32 )tmp___0; tmp___1 = read_phy_reg(pi, 234); phybist2 = (u32 )tmp___1; tmp___2 = read_phy_reg(pi, 235); phybist3 = (u32 )tmp___2; tmp___3 = read_phy_reg(pi, 342); phybist4 = (u32 )tmp___3; if ((((phybist0 == 0U && phybist1 == 16384U) && phybist2 == 8160U) && phybist3 == 0U) && phybist4 == 0U) { return (1); } else { } return (0); } } static void wlc_phy_bphy_init_nphy(struct brcms_phy *pi ) { u16 addr ; u16 val ; { val = 7711U; addr = 3208U; goto ldv_37490; ldv_37489: write_phy_reg(pi, (int )addr, (int )val); if ((unsigned int )addr == 3223U) { val = 15935U; } else { val = (unsigned int )val + 65022U; } addr = (u16 )((int )addr + 1); ldv_37490: ; if ((unsigned int )addr <= 3239U) { goto ldv_37489; } else { } write_phy_reg(pi, 3128, 1640); return; } } void wlc_phy_table_write_nphy(struct brcms_phy *pi , u32 id , u32 len , u32 offset , u32 width , void const *data ) { struct phytbl_info tbl ; { tbl.tbl_id = id; tbl.tbl_len = len; tbl.tbl_offset = offset; tbl.tbl_width = width; tbl.tbl_ptr = data; wlc_phy_write_table(pi, (struct phytbl_info const *)(& tbl), 114, 116, 115); return; } } void wlc_phy_table_read_nphy(struct brcms_phy *pi , u32 id , u32 len , u32 offset , u32 width , void *data ) { struct phytbl_info tbl ; { tbl.tbl_id = id; tbl.tbl_len = len; tbl.tbl_offset = offset; tbl.tbl_width = width; tbl.tbl_ptr = (void const *)data; wlc_phy_read_table(pi, (struct phytbl_info const *)(& tbl), 114, 116, 115); return; } } static void wlc_phy_static_table_download_nphy(struct brcms_phy *pi ) { uint idx ; { if (0) { idx = 0U; goto ldv_37515; ldv_37514: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev16) + (unsigned long )idx, 114, 116, 115); idx = idx + 1U; ldv_37515: ; if (idx < (uint )mimophytbl_info_sz_rev16) { goto ldv_37514; } else { } } else if (pi->pubpi.phy_rev > 6U) { idx = 0U; goto ldv_37518; ldv_37517: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev7) + (unsigned long )idx, 114, 116, 115); idx = idx + 1U; ldv_37518: ; if (idx < (uint )mimophytbl_info_sz_rev7) { goto ldv_37517; } else { } } else if (pi->pubpi.phy_rev > 2U) { idx = 0U; goto ldv_37521; ldv_37520: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev3) + (unsigned long )idx, 114, 116, 115); idx = idx + 1U; ldv_37521: ; if (idx < (uint )mimophytbl_info_sz_rev3) { goto ldv_37520; } else { } } else { idx = 0U; goto ldv_37524; ldv_37523: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev0) + (unsigned long )idx, 114, 116, 115); idx = idx + 1U; ldv_37524: ; if (idx < (uint )mimophytbl_info_sz_rev0) { goto ldv_37523; } else { } } return; } } static void wlc_phy_tbl_init_nphy(struct brcms_phy *pi ) { uint idx ; u8 antswctrllut ; { idx = 0U; if ((int )pi->phy_init_por) { wlc_phy_static_table_download_nphy(pi); } else { } if (pi->pubpi.phy_rev > 6U) { antswctrllut = ((int )pi->radio_chanspec & 61440) == 8192 ? pi->srom_fem2g.antswctrllut : pi->srom_fem5g.antswctrllut; switch ((int )antswctrllut) { case 0: ; goto ldv_37532; case 1: ; if ((unsigned int )pi->aa2g == 7U) { wlc_phy_table_write_nphy(pi, 9U, 2U, 33U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8_2o3)); } else { wlc_phy_table_write_nphy(pi, 9U, 2U, 33U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8)); } wlc_phy_table_write_nphy(pi, 9U, 2U, 37U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8) + 2U); wlc_phy_table_write_nphy(pi, 9U, 2U, 41U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8) + 4U); goto ldv_37532; case 2: wlc_phy_table_write_nphy(pi, 9U, 2U, 1U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8_2057v7_core0)); wlc_phy_table_write_nphy(pi, 9U, 2U, 5U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8_2057v7_core0) + 2U); wlc_phy_table_write_nphy(pi, 9U, 2U, 9U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8_2057v7_core0) + 4U); wlc_phy_table_write_nphy(pi, 9U, 2U, 33U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8_2057v7_core1)); wlc_phy_table_write_nphy(pi, 9U, 2U, 37U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8_2057v7_core1) + 2U); wlc_phy_table_write_nphy(pi, 9U, 2U, 41U, 8U, (void const *)(& ant_sw_ctrl_tbl_rev8_2057v7_core1) + 4U); goto ldv_37532; default: ; goto ldv_37532; } ldv_37532: ; } else if (pi->pubpi.phy_rev > 2U) { idx = 0U; goto ldv_37543; ldv_37542: ; if (idx == 0U) { antswctrllut = ((int )pi->radio_chanspec & 61440) == 8192 ? pi->srom_fem2g.antswctrllut : pi->srom_fem5g.antswctrllut; switch ((int )antswctrllut) { case 0: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev3_volatile) + (unsigned long )idx, 114, 116, 115); goto ldv_37537; case 1: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev3_volatile1) + (unsigned long )idx, 114, 116, 115); goto ldv_37537; case 2: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev3_volatile2) + (unsigned long )idx, 114, 116, 115); goto ldv_37537; case 3: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev3_volatile3) + (unsigned long )idx, 114, 116, 115); goto ldv_37537; default: ; goto ldv_37537; } ldv_37537: ; } else { wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev3_volatile) + (unsigned long )idx, 114, 116, 115); } idx = idx + 1U; ldv_37543: ; if (idx < (uint )mimophytbl_info_sz_rev3_volatile) { goto ldv_37542; } else { } } else { idx = 0U; goto ldv_37546; ldv_37545: wlc_phy_write_table(pi, (struct phytbl_info const *)(& mimophytbl_info_rev0_volatile) + (unsigned long )idx, 114, 116, 115); idx = idx + 1U; ldv_37546: ; if (idx < (uint )mimophytbl_info_sz_rev0_volatile) { goto ldv_37545; } else { } } return; } } static void wlc_phy_write_txmacreg_nphy(struct brcms_phy *pi , u16 holdoff , u16 delay ) { { write_phy_reg(pi, 119, (int )holdoff); write_phy_reg(pi, 180, (int )delay); return; } } void wlc_phy_nphy_tkip_rifs_war(struct brcms_phy *pi , u8 rifs ) { u16 holdoff ; u16 delay ; { if ((unsigned int )rifs != 0U) { holdoff = 16U; delay = 600U; } else { holdoff = 21U; delay = 800U; } wlc_phy_write_txmacreg_nphy(pi, (int )holdoff, (int )delay); if ((unsigned long )pi->sh != (unsigned long )((struct shared_phy *)0) && (int )(pi->sh)->_rifs_phy != (int )rifs) { (pi->sh)->_rifs_phy = (unsigned int )rifs != 0U; } else { } return; } } static void wlc_phy_txpwrctrl_config_nphy(struct brcms_phy *pi ) { { if (pi->pubpi.phy_rev > 2U) { pi->nphy_txpwrctrl = 1U; pi->phy_5g_pwrgain = 1; return; } else { } pi->nphy_txpwrctrl = 0U; pi->phy_5g_pwrgain = 0; if ((((pi->sh)->boardflags2 & 4U) != 0U && pi->pubpi.phy_rev > 1U) && (pi->sh)->sromrev > 3U) { pi->nphy_txpwrctrl = 1U; } else if ((pi->sh)->sromrev > 3U && ((pi->sh)->boardflags2 & 16U) != 0U) { pi->phy_5g_pwrgain = 1; } else { } return; } } static void wlc_phy_txpwr_srom_read_ppr_nphy(struct brcms_phy *pi ) { u16 bw40po ; u16 cddpo ; u16 stbcpo ; u16 bwduppo ; uint band_num ; struct ssb_sprom *sprom ; { sprom = & ((pi->d11core)->bus)->sprom; if ((pi->sh)->sromrev > 8U) { return; } else { } bw40po = sprom->bw40po; pi->bw402gpo = (unsigned int )((u8 )bw40po) & 15U; pi->bw405gpo = (u8 )(((int )bw40po & 240) >> 4); pi->bw405glpo = (u8 )(((int )bw40po & 3840) >> 8); pi->bw405ghpo = (u8 )((int )bw40po >> 12); cddpo = sprom->cddpo; pi->cdd2gpo = (unsigned int )((u8 )cddpo) & 15U; pi->cdd5gpo = (u8 )(((int )cddpo & 240) >> 4); pi->cdd5glpo = (u8 )(((int )cddpo & 3840) >> 8); pi->cdd5ghpo = (u8 )((int )cddpo >> 12); stbcpo = sprom->stbcpo; pi->stbc2gpo = (unsigned int )((u8 )stbcpo) & 15U; pi->stbc5gpo = (u8 )(((int )stbcpo & 240) >> 4); pi->stbc5glpo = (u8 )(((int )stbcpo & 3840) >> 8); pi->stbc5ghpo = (u8 )((int )stbcpo >> 12); bwduppo = sprom->bwduppo; pi->bwdup2gpo = (unsigned int )((u8 )bwduppo) & 15U; pi->bwdup5gpo = (u8 )(((int )bwduppo & 240) >> 4); pi->bwdup5glpo = (u8 )(((int )bwduppo & 3840) >> 8); pi->bwdup5ghpo = (u8 )((int )bwduppo >> 12); band_num = 0U; goto ldv_37577; ldv_37576: ; switch (band_num) { case 0U: pi->nphy_pwrctrl_info[0].max_pwr_2g = (s8 )sprom->core_pwr_info[0].maxpwr_2g; pi->nphy_pwrctrl_info[1].max_pwr_2g = (s8 )sprom->core_pwr_info[1].maxpwr_2g; pi->nphy_pwrctrl_info[0].pwrdet_2g_a1 = (s16 )sprom->core_pwr_info[0].pa_2g[0]; pi->nphy_pwrctrl_info[1].pwrdet_2g_a1 = (s16 )sprom->core_pwr_info[1].pa_2g[0]; pi->nphy_pwrctrl_info[0].pwrdet_2g_b0 = (s16 )sprom->core_pwr_info[0].pa_2g[1]; pi->nphy_pwrctrl_info[1].pwrdet_2g_b0 = (s16 )sprom->core_pwr_info[1].pa_2g[1]; pi->nphy_pwrctrl_info[0].pwrdet_2g_b1 = (s16 )sprom->core_pwr_info[0].pa_2g[2]; pi->nphy_pwrctrl_info[1].pwrdet_2g_b1 = (s16 )sprom->core_pwr_info[1].pa_2g[2]; pi->nphy_pwrctrl_info[0].idle_targ_2g = (s8 )sprom->core_pwr_info[0].itssi_2g; pi->nphy_pwrctrl_info[1].idle_targ_2g = (s8 )sprom->core_pwr_info[1].itssi_2g; pi->cck2gpo = sprom->cck2gpo; pi->ofdm2gpo = sprom->ofdm2gpo; pi->mcs2gpo[0] = sprom->mcs2gpo[0]; pi->mcs2gpo[1] = sprom->mcs2gpo[1]; pi->mcs2gpo[2] = sprom->mcs2gpo[2]; pi->mcs2gpo[3] = sprom->mcs2gpo[3]; pi->mcs2gpo[4] = sprom->mcs2gpo[4]; pi->mcs2gpo[5] = sprom->mcs2gpo[5]; pi->mcs2gpo[6] = sprom->mcs2gpo[6]; pi->mcs2gpo[7] = sprom->mcs2gpo[7]; goto ldv_37572; case 1U: pi->nphy_pwrctrl_info[0].max_pwr_5gm = (s8 )sprom->core_pwr_info[0].maxpwr_5g; pi->nphy_pwrctrl_info[1].max_pwr_5gm = (s8 )sprom->core_pwr_info[1].maxpwr_5g; pi->nphy_pwrctrl_info[0].pwrdet_5gm_a1 = (s16 )sprom->core_pwr_info[0].pa_5g[0]; pi->nphy_pwrctrl_info[1].pwrdet_5gm_a1 = (s16 )sprom->core_pwr_info[1].pa_5g[0]; pi->nphy_pwrctrl_info[0].pwrdet_5gm_b0 = (s16 )sprom->core_pwr_info[0].pa_5g[1]; pi->nphy_pwrctrl_info[1].pwrdet_5gm_b0 = (s16 )sprom->core_pwr_info[1].pa_5g[1]; pi->nphy_pwrctrl_info[0].pwrdet_5gm_b1 = (s16 )sprom->core_pwr_info[0].pa_5g[2]; pi->nphy_pwrctrl_info[1].pwrdet_5gm_b1 = (s16 )sprom->core_pwr_info[1].pa_5g[2]; pi->nphy_pwrctrl_info[0].idle_targ_5gm = (s8 )sprom->core_pwr_info[0].itssi_5g; pi->nphy_pwrctrl_info[1].idle_targ_5gm = (s8 )sprom->core_pwr_info[1].itssi_5g; pi->ofdm5gpo = sprom->ofdm5gpo; pi->mcs5gpo[0] = sprom->mcs5gpo[0]; pi->mcs5gpo[1] = sprom->mcs5gpo[1]; pi->mcs5gpo[2] = sprom->mcs5gpo[2]; pi->mcs5gpo[3] = sprom->mcs5gpo[3]; pi->mcs5gpo[4] = sprom->mcs5gpo[4]; pi->mcs5gpo[5] = sprom->mcs5gpo[5]; pi->mcs5gpo[6] = sprom->mcs5gpo[6]; pi->mcs5gpo[7] = sprom->mcs5gpo[7]; goto ldv_37572; case 2U: pi->nphy_pwrctrl_info[0].max_pwr_5gl = (s8 )sprom->core_pwr_info[0].maxpwr_5gl; pi->nphy_pwrctrl_info[1].max_pwr_5gl = (s8 )sprom->core_pwr_info[1].maxpwr_5gl; pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1 = (s16 )sprom->core_pwr_info[0].pa_5gl[0]; pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1 = (s16 )sprom->core_pwr_info[1].pa_5gl[0]; pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0 = (s16 )sprom->core_pwr_info[0].pa_5gl[1]; pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0 = (s16 )sprom->core_pwr_info[1].pa_5gl[1]; pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1 = (s16 )sprom->core_pwr_info[0].pa_5gl[2]; pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1 = (s16 )sprom->core_pwr_info[1].pa_5gl[2]; pi->nphy_pwrctrl_info[0].idle_targ_5gl = 0; pi->nphy_pwrctrl_info[1].idle_targ_5gl = 0; pi->ofdm5glpo = sprom->ofdm5glpo; pi->mcs5glpo[0] = sprom->mcs5glpo[0]; pi->mcs5glpo[1] = sprom->mcs5glpo[1]; pi->mcs5glpo[2] = sprom->mcs5glpo[2]; pi->mcs5glpo[3] = sprom->mcs5glpo[3]; pi->mcs5glpo[4] = sprom->mcs5glpo[4]; pi->mcs5glpo[5] = sprom->mcs5glpo[5]; pi->mcs5glpo[6] = sprom->mcs5glpo[6]; pi->mcs5glpo[7] = sprom->mcs5glpo[7]; goto ldv_37572; case 3U: pi->nphy_pwrctrl_info[0].max_pwr_5gh = (s8 )sprom->core_pwr_info[0].maxpwr_5gh; pi->nphy_pwrctrl_info[1].max_pwr_5gh = (s8 )sprom->core_pwr_info[1].maxpwr_5gh; pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1 = (s16 )sprom->core_pwr_info[0].pa_5gh[0]; pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1 = (s16 )sprom->core_pwr_info[1].pa_5gh[0]; pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0 = (s16 )sprom->core_pwr_info[0].pa_5gh[1]; pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0 = (s16 )sprom->core_pwr_info[1].pa_5gh[1]; pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1 = (s16 )sprom->core_pwr_info[0].pa_5gh[2]; pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1 = (s16 )sprom->core_pwr_info[1].pa_5gh[2]; pi->nphy_pwrctrl_info[0].idle_targ_5gh = 0; pi->nphy_pwrctrl_info[1].idle_targ_5gh = 0; pi->ofdm5ghpo = sprom->ofdm5ghpo; pi->mcs5ghpo[0] = sprom->mcs5ghpo[0]; pi->mcs5ghpo[1] = sprom->mcs5ghpo[1]; pi->mcs5ghpo[2] = sprom->mcs5ghpo[2]; pi->mcs5ghpo[3] = sprom->mcs5ghpo[3]; pi->mcs5ghpo[4] = sprom->mcs5ghpo[4]; pi->mcs5ghpo[5] = sprom->mcs5ghpo[5]; pi->mcs5ghpo[6] = sprom->mcs5ghpo[6]; pi->mcs5ghpo[7] = sprom->mcs5ghpo[7]; goto ldv_37572; } ldv_37572: band_num = band_num + 1U; ldv_37577: ; if (band_num <= 3U) { goto ldv_37576; } else { } wlc_phy_txpwr_apply_nphy(pi); return; } } static bool wlc_phy_txpwr_srom_read_nphy(struct brcms_phy *pi ) { struct ssb_sprom *sprom ; { sprom = & ((pi->d11core)->bus)->sprom; pi->antswitch = sprom->antswitch; pi->aa2g = sprom->ant_available_bg; pi->aa5g = sprom->ant_available_a; pi->srom_fem2g.tssipos = sprom->fem.ghz2.tssipos; pi->srom_fem2g.extpagain = sprom->fem.ghz2.extpa_gain; pi->srom_fem2g.pdetrange = sprom->fem.ghz2.pdet_range; pi->srom_fem2g.triso = sprom->fem.ghz2.tr_iso; pi->srom_fem2g.antswctrllut = sprom->fem.ghz2.antswlut; pi->srom_fem5g.tssipos = sprom->fem.ghz5.tssipos; pi->srom_fem5g.extpagain = sprom->fem.ghz5.extpa_gain; pi->srom_fem5g.pdetrange = sprom->fem.ghz5.pdet_range; pi->srom_fem5g.triso = sprom->fem.ghz5.tr_iso; if ((unsigned int )sprom->fem.ghz5.antswlut != 0U) { pi->srom_fem5g.antswctrllut = sprom->fem.ghz5.antswlut; } else { pi->srom_fem5g.antswctrllut = sprom->fem.ghz2.antswlut; } wlc_phy_txpower_ipa_upd(pi); pi->phy_txcore_disable_temp = (s16 )sprom->tempthresh; if ((int )pi->phy_txcore_disable_temp == 0) { pi->phy_txcore_disable_temp = 115; } else { } pi->phy_tempsense_offset = (s8 )sprom->tempoffset; if ((int )pi->phy_tempsense_offset != 0) { if ((int )pi->phy_tempsense_offset > 48) { pi->phy_tempsense_offset = 16; } else if ((int )pi->phy_tempsense_offset <= 15) { pi->phy_tempsense_offset = -16; } else { pi->phy_tempsense_offset = (s8 )((unsigned int )((unsigned char )pi->phy_tempsense_offset) + 224U); } } else { } pi->phy_txcore_enable_temp = (s16 )((unsigned int )((unsigned short )pi->phy_txcore_disable_temp) + 65531U); pi->phycal_tempdelta = sprom->phycal_tempdelta; if ((unsigned int )pi->phycal_tempdelta > 64U) { pi->phycal_tempdelta = 0U; } else { } wlc_phy_txpwr_srom_read_ppr_nphy(pi); return (1); } } bool wlc_phy_attach_nphy(struct brcms_phy *pi ) { uint i ; bool tmp ; int tmp___0 ; { if (pi->pubpi.phy_rev > 2U && pi->pubpi.phy_rev <= 5U) { pi->phyhang_avoid = 1; } else { } if (pi->pubpi.phy_rev > 2U && pi->pubpi.phy_rev <= 6U) { pi->nphy_gband_spurwar_en = 1; if (((pi->sh)->boardflags2 & 512U) != 0U) { pi->nphy_aband_spurwar_en = 1; } else { } } else { } if (pi->pubpi.phy_rev > 5U && pi->pubpi.phy_rev <= 6U) { if (((pi->sh)->boardflags2 & 8192U) != 0U) { pi->nphy_gband_spurwar2_en = 1; } else { } } else { } pi->n_preamble_override = -1; if (pi->pubpi.phy_rev == 3U || pi->pubpi.phy_rev == 4U) { pi->n_preamble_override = 0; } else { } pi->nphy_txrx_chain = -1; pi->phy_scraminit = -1; pi->nphy_rxcalparams = 16842933U; pi->nphy_perical = 2U; pi->mphase_cal_phase_id = 0U; pi->mphase_txcal_numcmds = 2U; pi->nphy_gain_boost = 1; pi->nphy_elna_gain_config = 0; pi->radio_is_on = 0; i = 0U; goto ldv_37588; ldv_37587: pi->nphy_txpwrindex[i].index = -1; i = i + 1U; ldv_37588: ; if ((uint )pi->pubpi.phy_corenum > i) { goto ldv_37587; } else { } wlc_phy_txpwrctrl_config_nphy(pi); if ((unsigned int )pi->nphy_txpwrctrl == 1U) { pi->hwpwrctrl_capable = 1; } else { } pi->pi_fptr.init = & wlc_phy_init_nphy; pi->pi_fptr.calinit = & wlc_phy_cal_init_nphy; pi->pi_fptr.chanset = & wlc_phy_chanspec_set_nphy; pi->pi_fptr.txpwrrecalc = & wlc_phy_txpower_recalc_target_nphy; tmp = wlc_phy_txpwr_srom_read_nphy(pi); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (0); } else { } return (1); } } static s32 get_rf_pwr_offset(struct brcms_phy *pi , s16 pga_gn , s16 pad_gn ) { s32 rfpwr_offset ; { rfpwr_offset = 0; if (((int )pi->radio_chanspec & 61440) == 8192) { if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { rfpwr_offset = (s32 )nphy_papd_padgain_dlt_2g_2057rev3n4[(int )pad_gn]; } else if ((unsigned int )pi->pubpi.radiorev == 5U) { rfpwr_offset = (s32 )nphy_papd_padgain_dlt_2g_2057rev5[(int )pad_gn]; } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { rfpwr_offset = (s32 )nphy_papd_padgain_dlt_2g_2057rev7[(int )pad_gn]; } else { } } else if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { rfpwr_offset = (s32 )nphy_papd_pgagain_dlt_5g_2057[(int )pga_gn]; } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { rfpwr_offset = (s32 )nphy_papd_pgagain_dlt_5g_2057rev7[(int )pga_gn]; } else { } return (rfpwr_offset); } } static void wlc_phy_update_mimoconfig_nphy(struct brcms_phy *pi , s32 preamble ) { bool gf_preamble ; u16 val ; { gf_preamble = 0; if (preamble == 1) { gf_preamble = 1; } else { } val = read_phy_reg(pi, 237); val = (u16 )((unsigned int )val | 256U); val = (unsigned int )val & 65531U; if ((int )gf_preamble) { val = (u16 )((unsigned int )val | 4U); } else { } write_phy_reg(pi, 237, (int )val); return; } } static void wlc_phy_ipa_set_tx_digi_filts_nphy(struct brcms_phy *pi ) { int j ; int type ; u16 addr_offset[3U] ; { addr_offset[0] = 390U; addr_offset[1] = 405U; addr_offset[2] = 709U; type = 0; goto ldv_37612; ldv_37611: j = 0; goto ldv_37609; ldv_37608: write_phy_reg(pi, (int )addr_offset[type] + (int )((u16 )j), (int )NPHY_IPA_REV4_txdigi_filtcoeffs[type][j]); j = j + 1; ldv_37609: ; if (j <= 14) { goto ldv_37608; } else { } type = type + 1; ldv_37612: ; if (type <= 2) { goto ldv_37611; } else { } if ((unsigned int )pi->bw == 3072U) { j = 0; goto ldv_37615; ldv_37614: write_phy_reg(pi, (int )((unsigned int )((u16 )j) + 390U), (int )NPHY_IPA_REV4_txdigi_filtcoeffs[3][j]); j = j + 1; ldv_37615: ; if (j <= 14) { goto ldv_37614; } else { } } else { if (((int )pi->radio_chanspec & 61440) == 4096) { j = 0; goto ldv_37618; ldv_37617: write_phy_reg(pi, (int )((unsigned int )((u16 )j) + 390U), (int )NPHY_IPA_REV4_txdigi_filtcoeffs[5][j]); j = j + 1; ldv_37618: ; if (j <= 14) { goto ldv_37617; } else { } } else { } if ((unsigned int )((unsigned char )pi->radio_chanspec) == 14U) { j = 0; goto ldv_37621; ldv_37620: write_phy_reg(pi, (int )((unsigned int )((u16 )j) + 709U), (int )NPHY_IPA_REV4_txdigi_filtcoeffs[6][j]); j = j + 1; ldv_37621: ; if (j <= 14) { goto ldv_37620; } else { } } else { } } return; } } static void wlc_phy_ipa_restore_tx_digi_filts_nphy(struct brcms_phy *pi ) { int j ; { if ((unsigned int )pi->bw == 3072U) { j = 0; goto ldv_37628; ldv_37627: write_phy_reg(pi, (int )((unsigned int )((u16 )j) + 405U), (int )NPHY_IPA_REV4_txdigi_filtcoeffs[4][j]); j = j + 1; ldv_37628: ; if (j <= 14) { goto ldv_37627; } else { } } else { j = 0; goto ldv_37631; ldv_37630: write_phy_reg(pi, (int )((unsigned int )((u16 )j) + 390U), (int )NPHY_IPA_REV4_txdigi_filtcoeffs[3][j]); j = j + 1; ldv_37631: ; if (j <= 14) { goto ldv_37630; } else { } } return; } } static void wlc_phy_set_rfseq_nphy(struct brcms_phy *pi , u8 cmd , u8 *events , u8 *dlys , u8 len ) { u32 t1_offset ; u32 t2_offset ; u8 ctr ; u8 end_event ; u8 end_dly ; { end_event = pi->pubpi.phy_rev > 2U ? 31U : 15U; end_dly = 1U; if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } t1_offset = (u32 )((int )cmd << 4); wlc_phy_table_write_nphy(pi, 7U, (u32 )len, t1_offset, 8U, (void const *)events); t2_offset = t1_offset + 128U; wlc_phy_table_write_nphy(pi, 7U, (u32 )len, t2_offset, 8U, (void const *)dlys); ctr = len; goto ldv_37646; ldv_37645: wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )ctr + t1_offset, 8U, (void const *)(& end_event)); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )ctr + t2_offset, 8U, (void const *)(& end_dly)); ctr = (u8 )((int )ctr + 1); ldv_37646: ; if ((unsigned int )ctr <= 15U) { goto ldv_37645; } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static u16 wlc_phy_read_lpf_bw_ctl_nphy(struct brcms_phy *pi , u16 offset ) { u16 lpf_bw_ctl_val ; u16 rx2tx_lpf_rc_lut_offset ; { lpf_bw_ctl_val = 0U; rx2tx_lpf_rc_lut_offset = 0U; if ((unsigned int )offset == 0U) { if (((int )pi->radio_chanspec & 3072) == 3072) { rx2tx_lpf_rc_lut_offset = 345U; } else { rx2tx_lpf_rc_lut_offset = 340U; } } else { rx2tx_lpf_rc_lut_offset = offset; } wlc_phy_table_read_nphy(pi, 7U, 1U, (unsigned int )rx2tx_lpf_rc_lut_offset, 16U, (void *)(& lpf_bw_ctl_val)); lpf_bw_ctl_val = (unsigned int )lpf_bw_ctl_val & 7U; return (lpf_bw_ctl_val); } } static void wlc_phy_rfctrl_override_nphy_rev7(struct brcms_phy *pi , u16 field , u16 value , u8 core_mask , u8 off , u8 override_id ) { u8 core_num ; u16 addr ; u16 en_addr ; u16 val_addr ; u16 en_mask ; u16 val_mask ; u8 val_shift ; { addr = 0U; en_addr = 0U; val_addr = 0U; en_mask = 0U; val_mask = 0U; val_shift = 0U; if (pi->pubpi.phy_rev > 6U) { en_mask = field; core_num = 0U; goto ldv_37704; ldv_37703: ; if ((unsigned int )override_id == 0U) { switch ((int )field) { case 4: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 2U; val_shift = 1U; goto ldv_37670; case 8: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 4U; val_shift = 2U; goto ldv_37670; case 16: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 16U; val_shift = 4U; goto ldv_37670; case 32: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 32U; val_shift = 5U; goto ldv_37670; case 64: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 64U; val_shift = 6U; goto ldv_37670; case 128: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 128U; val_shift = 7U; goto ldv_37670; case 1024: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 248U : 250U; val_mask = 112U; val_shift = 4U; goto ldv_37670; case 2048: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 123U : 126U; val_mask = 65535U; val_shift = 0U; goto ldv_37670; case 4096: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 124U : 127U; val_mask = 65535U; val_shift = 0U; goto ldv_37670; case 24576: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 840U : 841U; val_mask = 255U; val_shift = 0U; goto ldv_37670; case 8192: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 840U : 841U; val_mask = 15U; val_shift = 0U; goto ldv_37670; default: addr = 65535U; goto ldv_37670; } ldv_37670: ; } else if ((unsigned int )override_id == 1U) { switch ((int )field) { case 2: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 2U; val_shift = 1U; goto ldv_37683; case 8: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 8U; val_shift = 3U; goto ldv_37683; case 32: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 32U; val_shift = 5U; goto ldv_37683; case 16: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 16U; val_shift = 4U; goto ldv_37683; case 4: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 4U; val_shift = 2U; goto ldv_37683; case 128: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 1792U; val_shift = 8U; goto ldv_37683; case 2048: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 16384U; val_shift = 14U; goto ldv_37683; case 1024: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 8192U; val_shift = 13U; goto ldv_37683; case 512: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 4096U; val_shift = 12U; goto ldv_37683; case 256: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 2048U; val_shift = 11U; goto ldv_37683; case 64: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 64U; val_shift = 6U; goto ldv_37683; case 1: en_addr = (unsigned int )core_num == 0U ? 834U : 835U; val_addr = (unsigned int )core_num == 0U ? 832U : 833U; val_mask = 1U; val_shift = 0U; goto ldv_37683; default: addr = 65535U; goto ldv_37683; } ldv_37683: ; } else if ((unsigned int )override_id == 2U) { switch ((int )field) { case 8: en_addr = (unsigned int )core_num == 0U ? 838U : 839U; val_addr = (unsigned int )core_num == 0U ? 836U : 837U; val_mask = 8U; val_shift = 3U; goto ldv_37697; case 2: en_addr = (unsigned int )core_num == 0U ? 838U : 839U; val_addr = (unsigned int )core_num == 0U ? 836U : 837U; val_mask = 2U; val_shift = 1U; goto ldv_37697; case 1: en_addr = (unsigned int )core_num == 0U ? 838U : 839U; val_addr = (unsigned int )core_num == 0U ? 836U : 837U; val_mask = 1U; val_shift = 0U; goto ldv_37697; case 4: en_addr = (unsigned int )core_num == 0U ? 838U : 839U; val_addr = (unsigned int )core_num == 0U ? 836U : 837U; val_mask = 4U; val_shift = 2U; goto ldv_37697; case 16: en_addr = (unsigned int )core_num == 0U ? 838U : 839U; val_addr = (unsigned int )core_num == 0U ? 836U : 837U; val_mask = 16U; val_shift = 4U; goto ldv_37697; default: addr = 65535U; goto ldv_37697; } ldv_37697: ; } else { } if ((unsigned int )off != 0U) { and_phy_reg(pi, (int )en_addr, ~ ((int )en_mask)); and_phy_reg(pi, (int )val_addr, ~ ((int )val_mask)); } else if ((unsigned int )core_mask == 0U || ((int )core_mask >> (int )core_num) & 1) { or_phy_reg(pi, (int )en_addr, (int )en_mask); if ((unsigned int )addr != 65535U) { mod_phy_reg(pi, (int )val_addr, (int )val_mask, (int )((u16 )((int )value << (int )val_shift))); } else { } } else { } core_num = (u8 )((int )core_num + 1); ldv_37704: ; if ((unsigned int )core_num <= 1U) { goto ldv_37703; } else { } } else { } return; } } static void wlc_phy_adjust_lnagaintbl_nphy(struct brcms_phy *pi ) { uint core ; int ctr ; s16 gain_delta[2U] ; u8 curr_channel ; u16 minmax_gain[2U] ; u16 regval[4U] ; { if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } if ((int )pi->nphy_gain_boost) { if (((int )pi->radio_chanspec & 61440) == 8192) { gain_delta[0] = 6; gain_delta[1] = 6; } else { curr_channel = (unsigned char )pi->radio_chanspec; gain_delta[0] = (short )((unsigned int )((unsigned short )((nphy_lnagain_est0[0] * (int )curr_channel + nphy_lnagain_est0[1]) >> 13)) + ((unsigned int )((unsigned short )((nphy_lnagain_est0[0] * (int )curr_channel + nphy_lnagain_est0[1]) >> 12)) & 1U)); gain_delta[1] = (short )((unsigned int )((unsigned short )((nphy_lnagain_est1[0] * (int )curr_channel + nphy_lnagain_est1[1]) >> 13)) + ((unsigned int )((unsigned short )((nphy_lnagain_est1[0] * (int )curr_channel + nphy_lnagain_est1[1]) >> 12)) & 1U)); } } else { gain_delta[0] = 0; gain_delta[1] = 0; } core = 0U; goto ldv_37719; ldv_37718: ; if ((int )pi->nphy_elna_gain_config) { regval[0] = (int )((u16 )nphy_def_lnagains[2]) + (int )((u16 )gain_delta[core]); regval[1] = (int )((u16 )nphy_def_lnagains[3]) + (int )((u16 )gain_delta[core]); regval[2] = (int )((u16 )nphy_def_lnagains[3]) + (int )((u16 )gain_delta[core]); regval[3] = (int )((u16 )nphy_def_lnagains[3]) + (int )((u16 )gain_delta[core]); } else { ctr = 0; goto ldv_37716; ldv_37715: regval[ctr] = (int )((u16 )nphy_def_lnagains[ctr]) + (int )((u16 )gain_delta[core]); ctr = ctr + 1; ldv_37716: ; if (ctr <= 3) { goto ldv_37715; } else { } } wlc_phy_table_write_nphy(pi, core, 4U, 8U, 16U, (void const *)(& regval)); minmax_gain[core] = (unsigned int )((int )((unsigned short )nphy_def_lnagains[2]) + (int )((unsigned short )gain_delta[core])) + 4U; core = core + 1U; ldv_37719: ; if ((uint )pi->pubpi.phy_corenum > core) { goto ldv_37718; } else { } mod_phy_reg(pi, 30, 255, (int )minmax_gain[0]); mod_phy_reg(pi, 52, 255, (int )minmax_gain[1]); if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static void wlc_phy_war_force_trsw_to_R_cliplo_nphy(struct brcms_phy *pi , u8 core ) { { if ((unsigned int )core == 0U) { write_phy_reg(pi, 56, 4); if (((int )pi->radio_chanspec & 61440) == 8192) { write_phy_reg(pi, 55, 96); } else { write_phy_reg(pi, 55, 4224); } } else if ((unsigned int )core == 1U) { write_phy_reg(pi, 686, 4); if (((int )pi->radio_chanspec & 61440) == 8192) { write_phy_reg(pi, 685, 96); } else { write_phy_reg(pi, 685, 4224); } } else { } return; } } static void wlc_phy_war_txchain_upd_nphy(struct brcms_phy *pi , u8 txchain ) { u8 txchain0 ; u8 txchain1 ; { txchain0 = (unsigned int )txchain & 1U; txchain1 = (u8 )(((int )txchain & 2) >> 1); if ((unsigned int )txchain0 == 0U) { wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, 0); } else { } if ((unsigned int )txchain1 == 0U) { wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, 1); } else { } return; } } static void wlc_phy_workarounds_nphy_gainctrl_2057_rev5(struct brcms_phy *pi ) { s8 lna1_gain_db[4U] ; s8 lna2_gain_db[4U] ; s8 tia_gain_db[10U] ; s8 tia_gainbits[10U] ; { lna1_gain_db[0] = 8; lna1_gain_db[1] = 13; lna1_gain_db[2] = 17; lna1_gain_db[3] = 22; lna2_gain_db[0] = -2; lna2_gain_db[1] = 7; lna2_gain_db[2] = 11; lna2_gain_db[3] = 15; tia_gain_db[0] = -4; tia_gain_db[1] = -1; tia_gain_db[2] = 2; tia_gain_db[3] = 5; tia_gain_db[4] = 5; tia_gain_db[5] = 5; tia_gain_db[6] = 5; tia_gain_db[7] = 5; tia_gain_db[8] = 5; tia_gain_db[9] = 5; tia_gainbits[0] = 0; tia_gainbits[1] = 1; tia_gainbits[2] = 2; tia_gainbits[3] = 3; tia_gainbits[4] = 3; tia_gainbits[5] = 3; tia_gainbits[6] = 3; tia_gainbits[7] = 3; tia_gainbits[8] = 3; tia_gainbits[9] = 3; mod_phy_reg(pi, 28, 8192, 8192); mod_phy_reg(pi, 50, 8192, 8192); mod_phy_reg(pi, 649, 255, 70); mod_phy_reg(pi, 643, 255, 60); mod_phy_reg(pi, 640, 255, 60); wlc_phy_table_write_nphy(pi, 0U, 4U, 8U, 8U, (void const *)(& lna1_gain_db)); wlc_phy_table_write_nphy(pi, 1U, 4U, 8U, 8U, (void const *)(& lna1_gain_db)); wlc_phy_table_write_nphy(pi, 0U, 4U, 16U, 8U, (void const *)(& lna2_gain_db)); wlc_phy_table_write_nphy(pi, 1U, 4U, 16U, 8U, (void const *)(& lna2_gain_db)); wlc_phy_table_write_nphy(pi, 0U, 10U, 32U, 8U, (void const *)(& tia_gain_db)); wlc_phy_table_write_nphy(pi, 1U, 10U, 32U, 8U, (void const *)(& tia_gain_db)); wlc_phy_table_write_nphy(pi, 2U, 10U, 32U, 8U, (void const *)(& tia_gainbits)); wlc_phy_table_write_nphy(pi, 3U, 10U, 32U, 8U, (void const *)(& tia_gainbits)); write_phy_reg(pi, 55, 116); write_phy_reg(pi, 685, 116); write_phy_reg(pi, 56, 24); write_phy_reg(pi, 686, 24); write_phy_reg(pi, 43, 232); write_phy_reg(pi, 65, 232); if (((int )pi->radio_chanspec & 3072) == 2048) { mod_phy_reg(pi, 768, 63, 18); mod_phy_reg(pi, 769, 63, 18); } else { mod_phy_reg(pi, 768, 63, 16); mod_phy_reg(pi, 769, 63, 16); } return; } } static void wlc_phy_workarounds_nphy_gainctrl_2057_rev6(struct brcms_phy *pi ) { u16 currband ; s8 lna1G_gain_db_rev7[4U] ; s8 *lna1_gain_db ; s8 *lna1_gain_db_2 ; s8 *lna2_gain_db ; s8 tiaA_gain_db_rev7[10U] ; s8 *tia_gain_db ; s8 tiaA_gainbits_rev7[10U] ; s8 *tia_gainbits ; u16 rfseqA_init_gain_rev7[2U] ; u16 *rfseq_init_gain ; u16 init_gaincode ; u16 clip1hi_gaincode ; u16 clip1md_gaincode ; u16 clip1md_gaincode_B ; u16 clip1lo_gaincode ; u16 clip1lo_gaincode_B ; u8 crsminl_th ; u8 crsminu_th ; u16 nbclip_th ; u8 w1clip_th ; u16 freq ; s8 nvar_baseline_offset0 ; s8 nvar_baseline_offset1 ; u8 chg_nbclip_th ; u16 tmp ; s8 lna1A_gain_db_rev7[4U] ; s8 lna1A_gain_db_2_rev7[4U] ; s8 lna2A_gain_db_rev7[4U] ; s8 lna1A_gain_db_rev7___0[4U] ; s8 lna1A_gain_db_2_rev7___0[4U] ; s8 lna2A_gain_db_rev7___0[4U] ; s8 lna1A_gain_db_rev7___1[4U] ; s8 lna1A_gain_db_2_rev7___1[4U] ; s8 lna2A_gain_db_rev7___1[4U] ; { lna1G_gain_db_rev7[0] = 9; lna1G_gain_db_rev7[1] = 14; lna1G_gain_db_rev7[2] = 19; lna1G_gain_db_rev7[3] = 24; lna1_gain_db = (s8 *)0; lna1_gain_db_2 = (s8 *)0; lna2_gain_db = (s8 *)0; tiaA_gain_db_rev7[0] = -9; tiaA_gain_db_rev7[1] = -6; tiaA_gain_db_rev7[2] = -3; tiaA_gain_db_rev7[3] = 0; tiaA_gain_db_rev7[4] = 3; tiaA_gain_db_rev7[5] = 3; tiaA_gain_db_rev7[6] = 3; tiaA_gain_db_rev7[7] = 3; tiaA_gain_db_rev7[8] = 3; tiaA_gain_db_rev7[9] = 3; tiaA_gainbits_rev7[0] = 0; tiaA_gainbits_rev7[1] = 1; tiaA_gainbits_rev7[2] = 2; tiaA_gainbits_rev7[3] = 3; tiaA_gainbits_rev7[4] = 4; tiaA_gainbits_rev7[5] = 4; tiaA_gainbits_rev7[6] = 4; tiaA_gainbits_rev7[7] = 4; tiaA_gainbits_rev7[8] = 4; tiaA_gainbits_rev7[9] = 4; rfseqA_init_gain_rev7[0] = 25167U; rfseqA_init_gain_rev7[1] = 25167U; clip1md_gaincode = 0U; crsminl_th = 0U; nbclip_th = 0U; nvar_baseline_offset0 = 0; nvar_baseline_offset1 = 0; chg_nbclip_th = 0U; mod_phy_reg(pi, 28, 8192, 8192); mod_phy_reg(pi, 50, 8192, 8192); tmp = read_phy_reg(pi, 9); currband = (unsigned int )tmp & 1U; if ((unsigned int )currband == 0U) { lna1_gain_db = (s8 *)(& lna1G_gain_db_rev7); wlc_phy_table_write_nphy(pi, 0U, 4U, 8U, 8U, (void const *)lna1_gain_db); wlc_phy_table_write_nphy(pi, 1U, 4U, 8U, 8U, (void const *)lna1_gain_db); mod_phy_reg(pi, 643, 255, 64); if (((int )pi->radio_chanspec & 3072) == 3072) { mod_phy_reg(pi, 640, 255, 62); mod_phy_reg(pi, 643, 255, 62); } else { } mod_phy_reg(pi, 649, 255, 70); if (((int )pi->radio_chanspec & 3072) == 2048) { mod_phy_reg(pi, 768, 63, 13); mod_phy_reg(pi, 769, 63, 13); } else { } } else { init_gaincode = 158U; clip1hi_gaincode = 158U; clip1md_gaincode_B = 36U; clip1lo_gaincode = 138U; clip1lo_gaincode_B = 8U; rfseq_init_gain = (u16 *)(& rfseqA_init_gain_rev7); tia_gain_db = (s8 *)(& tiaA_gain_db_rev7); tia_gainbits = (s8 *)(& tiaA_gainbits_rev7); freq = (unsigned int )((u16 )((unsigned char )pi->radio_chanspec)) * 5U + 5000U; if (((int )pi->radio_chanspec & 3072) == 2048) { w1clip_th = 25U; clip1md_gaincode = 130U; if ((unsigned int )freq <= 5080U || (unsigned int )freq == 5825U) { lna1A_gain_db_rev7[0] = 11; lna1A_gain_db_rev7[1] = 16; lna1A_gain_db_rev7[2] = 20; lna1A_gain_db_rev7[3] = 24; lna1A_gain_db_2_rev7[0] = 11; lna1A_gain_db_2_rev7[1] = 17; lna1A_gain_db_2_rev7[2] = 22; lna1A_gain_db_2_rev7[3] = 25; lna2A_gain_db_rev7[0] = -1; lna2A_gain_db_rev7[1] = 6; lna2A_gain_db_rev7[2] = 10; lna2A_gain_db_rev7[3] = 14; crsminu_th = 62U; lna1_gain_db = (s8 *)(& lna1A_gain_db_rev7); lna1_gain_db_2 = (s8 *)(& lna1A_gain_db_2_rev7); lna2_gain_db = (s8 *)(& lna2A_gain_db_rev7); } else if ((unsigned int )freq > 5499U && (unsigned int )freq <= 5700U) { lna1A_gain_db_rev7___0[0] = 11; lna1A_gain_db_rev7___0[1] = 17; lna1A_gain_db_rev7___0[2] = 21; lna1A_gain_db_rev7___0[3] = 25; lna1A_gain_db_2_rev7___0[0] = 12; lna1A_gain_db_2_rev7___0[1] = 18; lna1A_gain_db_2_rev7___0[2] = 22; lna1A_gain_db_2_rev7___0[3] = 26; lna2A_gain_db_rev7___0[0] = 1; lna2A_gain_db_rev7___0[1] = 8; lna2A_gain_db_rev7___0[2] = 12; lna2A_gain_db_rev7___0[3] = 16; crsminu_th = 69U; clip1md_gaincode_B = 20U; nbclip_th = 255U; chg_nbclip_th = 1U; lna1_gain_db = (s8 *)(& lna1A_gain_db_rev7___0); lna1_gain_db_2 = (s8 *)(& lna1A_gain_db_2_rev7___0); lna2_gain_db = (s8 *)(& lna2A_gain_db_rev7___0); } else { lna1A_gain_db_rev7___1[0] = 12; lna1A_gain_db_rev7___1[1] = 18; lna1A_gain_db_rev7___1[2] = 22; lna1A_gain_db_rev7___1[3] = 26; lna1A_gain_db_2_rev7___1[0] = 12; lna1A_gain_db_2_rev7___1[1] = 18; lna1A_gain_db_2_rev7___1[2] = 22; lna1A_gain_db_2_rev7___1[3] = 26; lna2A_gain_db_rev7___1[0] = -1; lna2A_gain_db_rev7___1[1] = 6; lna2A_gain_db_rev7___1[2] = 10; lna2A_gain_db_rev7___1[3] = 14; crsminu_th = 65U; lna1_gain_db = (s8 *)(& lna1A_gain_db_rev7___1); lna1_gain_db_2 = (s8 *)(& lna1A_gain_db_2_rev7___1); lna2_gain_db = (s8 *)(& lna2A_gain_db_rev7___1); } if ((unsigned int )freq <= 4920U) { nvar_baseline_offset0 = 5; nvar_baseline_offset1 = 5; } else if ((unsigned int )freq > 4920U && (unsigned int )freq <= 5320U) { nvar_baseline_offset0 = 3; nvar_baseline_offset1 = 5; } else if ((unsigned int )freq > 5320U && (unsigned int )freq <= 5700U) { nvar_baseline_offset0 = 3; nvar_baseline_offset1 = 2; } else { nvar_baseline_offset0 = 4; nvar_baseline_offset1 = 0; } } else { crsminu_th = 58U; crsminl_th = 58U; w1clip_th = 20U; if ((unsigned int )freq > 4919U && (unsigned int )freq <= 5320U) { nvar_baseline_offset0 = 4; nvar_baseline_offset1 = 5; } else if ((unsigned int )freq > 5320U && (unsigned int )freq <= 5550U) { nvar_baseline_offset0 = 4; nvar_baseline_offset1 = 2; } else { nvar_baseline_offset0 = 5; nvar_baseline_offset1 = 3; } } write_phy_reg(pi, 32, (int )init_gaincode); write_phy_reg(pi, 679, (int )init_gaincode); wlc_phy_table_write_nphy(pi, 7U, (u32 )pi->pubpi.phy_corenum, 262U, 16U, (void const *)rfseq_init_gain); write_phy_reg(pi, 34, (int )clip1hi_gaincode); write_phy_reg(pi, 681, (int )clip1hi_gaincode); write_phy_reg(pi, 54, (int )clip1md_gaincode_B); write_phy_reg(pi, 684, (int )clip1md_gaincode_B); write_phy_reg(pi, 55, (int )clip1lo_gaincode); write_phy_reg(pi, 685, (int )clip1lo_gaincode); write_phy_reg(pi, 56, (int )clip1lo_gaincode_B); write_phy_reg(pi, 686, (int )clip1lo_gaincode_B); wlc_phy_table_write_nphy(pi, 0U, 10U, 32U, 8U, (void const *)tia_gain_db); wlc_phy_table_write_nphy(pi, 1U, 10U, 32U, 8U, (void const *)tia_gain_db); wlc_phy_table_write_nphy(pi, 2U, 10U, 32U, 8U, (void const *)tia_gainbits); wlc_phy_table_write_nphy(pi, 3U, 10U, 32U, 8U, (void const *)tia_gainbits); mod_phy_reg(pi, 643, 255, (int )crsminu_th); if ((unsigned int )chg_nbclip_th == 1U) { write_phy_reg(pi, 43, (int )nbclip_th); write_phy_reg(pi, 65, (int )nbclip_th); } else { } mod_phy_reg(pi, 768, 63, (int )w1clip_th); mod_phy_reg(pi, 769, 63, (int )w1clip_th); mod_phy_reg(pi, 740, 63, (int )((u16 )nvar_baseline_offset0)); mod_phy_reg(pi, 740, 4032, (int )((u16 )nvar_baseline_offset1) << 6U); if (((int )pi->radio_chanspec & 3072) == 2048) { wlc_phy_table_write_nphy(pi, 0U, 4U, 8U, 8U, (void const *)lna1_gain_db); wlc_phy_table_write_nphy(pi, 1U, 4U, 8U, 8U, (void const *)lna1_gain_db_2); wlc_phy_table_write_nphy(pi, 0U, 4U, 16U, 8U, (void const *)lna2_gain_db); wlc_phy_table_write_nphy(pi, 1U, 4U, 16U, 8U, (void const *)lna2_gain_db); write_phy_reg(pi, 36, (int )clip1md_gaincode); write_phy_reg(pi, 683, (int )clip1md_gaincode); } else { mod_phy_reg(pi, 640, 255, (int )crsminl_th); } } return; } } static void wlc_phy_workarounds_nphy_gainctrl(struct brcms_phy *pi ) { u16 w1th ; u16 hpf_code ; u16 currband ; int ctr ; u8 rfseq_updategainu_events[3U] ; u8 rfseq_updategainu_dlys[3U] ; s8 lna1G_gain_db[4U] ; s8 lna1G_gain_db_rev4[4U] ; s8 lna1G_gain_db_rev5[4U] ; s8 lna1G_gain_db_rev6[4U] ; s8 lna1G_gain_db_rev6_224B0[4U] ; s8 lna1A_gain_db[4U] ; s8 lna1A_gain_db_rev4[4U] ; s8 lna1A_gain_db_rev5[4U] ; s8 lna1A_gain_db_rev6[4U] ; s8 *lna1_gain_db ; s8 lna2G_gain_db[4U] ; s8 lna2G_gain_db_rev5[4U] ; s8 lna2G_gain_db_rev6[4U] ; s8 lna2G_gain_db_rev6_224B0[4U] ; s8 lna2A_gain_db[4U] ; s8 lna2A_gain_db_rev4[4U] ; s8 lna2A_gain_db_rev5[4U] ; s8 lna2A_gain_db_rev6[4U] ; s8 *lna2_gain_db ; s8 tiaG_gain_db[10U] ; s8 tiaA_gain_db[10U] ; s8 tiaA_gain_db_rev4[10U] ; s8 tiaA_gain_db_rev5[10U] ; s8 tiaA_gain_db_rev6[10U] ; s8 *tia_gain_db ; s8 tiaG_gainbits[10U] ; s8 tiaA_gainbits[10U] ; s8 tiaA_gainbits_rev4[10U] ; s8 tiaA_gainbits_rev5[10U] ; s8 tiaA_gainbits_rev6[10U] ; s8 *tia_gainbits ; s8 lpf_gain_db[6U] ; s8 lpf_gainbits[6U] ; u16 rfseqG_init_gain[4U] ; u16 rfseqG_init_gain_rev4[4U] ; u16 rfseqG_init_gain_rev5[4U] ; u16 rfseqG_init_gain_rev5_elna[4U] ; u16 rfseqG_init_gain_rev6[2U] ; u16 rfseqG_init_gain_rev6_224B0[2U] ; u16 rfseqG_init_gain_rev6_elna[2U] ; u16 rfseqA_init_gain[4U] ; u16 rfseqA_init_gain_rev4[4U] ; u16 rfseqA_init_gain_rev4_elna[4U] ; u16 rfseqA_init_gain_rev5[4U] ; u16 rfseqA_init_gain_rev6[2U] ; u16 *rfseq_init_gain ; u16 initG_gaincode ; u16 initG_gaincode_rev4 ; u16 initG_gaincode_rev5 ; u16 initG_gaincode_rev5_elna ; u16 initG_gaincode_rev6 ; u16 initG_gaincode_rev6_224B0 ; u16 initG_gaincode_rev6_elna ; u16 initA_gaincode ; u16 initA_gaincode_rev4 ; u16 initA_gaincode_rev4_elna ; u16 initA_gaincode_rev5 ; u16 initA_gaincode_rev6 ; u16 init_gaincode ; u16 clip1hiG_gaincode ; u16 clip1hiG_gaincode_rev4 ; u16 clip1hiG_gaincode_rev5 ; u16 clip1hiG_gaincode_rev6 ; u16 clip1hiA_gaincode ; u16 clip1hiA_gaincode_rev4 ; u16 clip1hiA_gaincode_rev5 ; u16 clip1hiA_gaincode_rev6 ; u16 clip1hi_gaincode ; u16 clip1mdG_gaincode ; u16 clip1mdA_gaincode ; u16 clip1mdA_gaincode_rev4 ; u16 clip1mdA_gaincode_rev5 ; u16 clip1mdA_gaincode_rev6 ; u16 clip1md_gaincode ; u16 clip1loG_gaincode ; u16 clip1loG_gaincode_rev5[8U] ; u16 clip1loG_gaincode_rev6[8U] ; u16 clip1loG_gaincode_rev6_224B0 ; u16 clip1loA_gaincode ; u16 clip1loA_gaincode_rev4 ; u16 clip1loA_gaincode_rev5 ; u16 clip1loA_gaincode_rev6 ; u16 clip1lo_gaincode ; u8 crsminG_th ; u8 crsminG_th_rev5 ; u8 crsminG_th_rev6 ; u8 crsminA_th ; u8 crsminA_th_rev4 ; u8 crsminA_th_rev5 ; u8 crsminA_th_rev6 ; u8 crsmin_th ; u8 crsminlG_th ; u8 crsminlG_th_rev5 ; u8 crsminlG_th_rev6 ; u8 crsminlA_th ; u8 crsminlA_th_rev4 ; u8 crsminlA_th_rev5 ; u8 crsminlA_th_rev6 ; u8 crsminl_th ; u8 crsminuG_th ; u8 crsminuG_th_rev5 ; u8 crsminuG_th_rev6 ; u8 crsminuA_th ; u8 crsminuA_th_rev4 ; u8 crsminuA_th_rev5 ; u8 crsminuA_th_rev6 ; u8 crsminuA_th_rev6_224B0 ; u8 crsminu_th ; u16 nbclipG_th ; u16 nbclipG_th_rev4 ; u16 nbclipG_th_rev5 ; u16 nbclipG_th_rev6 ; u16 nbclipA_th ; u16 nbclipA_th_rev4 ; u16 nbclipA_th_rev5 ; u16 nbclipA_th_rev6 ; u16 nbclip_th ; u8 w1clipG_th ; u8 w1clipG_th_rev5 ; u8 w1clipG_th_rev6 ; u8 w1clipA_th ; u8 w1clip_th ; u8 rssi_gain_default ; u8 rssiG_gain_rev6_224B0 ; u8 rssiA_gain_rev5 ; u8 rssiA_gain_rev6 ; u8 rssi_gain ; u16 regval[21U] ; u8 triso ; u16 tmp ; { rfseq_updategainu_events[0] = 6U; rfseq_updategainu_events[1] = 8U; rfseq_updategainu_events[2] = 7U; rfseq_updategainu_dlys[0] = 10U; rfseq_updategainu_dlys[1] = 30U; rfseq_updategainu_dlys[2] = 1U; lna1G_gain_db[0] = 7; lna1G_gain_db[1] = 11; lna1G_gain_db[2] = 16; lna1G_gain_db[3] = 23; lna1G_gain_db_rev4[0] = 8; lna1G_gain_db_rev4[1] = 12; lna1G_gain_db_rev4[2] = 17; lna1G_gain_db_rev4[3] = 25; lna1G_gain_db_rev5[0] = 9; lna1G_gain_db_rev5[1] = 13; lna1G_gain_db_rev5[2] = 18; lna1G_gain_db_rev5[3] = 26; lna1G_gain_db_rev6[0] = 8; lna1G_gain_db_rev6[1] = 13; lna1G_gain_db_rev6[2] = 18; lna1G_gain_db_rev6[3] = 25; lna1G_gain_db_rev6_224B0[0] = 10; lna1G_gain_db_rev6_224B0[1] = 14; lna1G_gain_db_rev6_224B0[2] = 19; lna1G_gain_db_rev6_224B0[3] = 27; lna1A_gain_db[0] = 7; lna1A_gain_db[1] = 11; lna1A_gain_db[2] = 17; lna1A_gain_db[3] = 23; lna1A_gain_db_rev4[0] = 8; lna1A_gain_db_rev4[1] = 12; lna1A_gain_db_rev4[2] = 18; lna1A_gain_db_rev4[3] = 23; lna1A_gain_db_rev5[0] = 6; lna1A_gain_db_rev5[1] = 10; lna1A_gain_db_rev5[2] = 16; lna1A_gain_db_rev5[3] = 21; lna1A_gain_db_rev6[0] = 6; lna1A_gain_db_rev6[1] = 10; lna1A_gain_db_rev6[2] = 16; lna1A_gain_db_rev6[3] = 21; lna1_gain_db = (s8 *)0; lna2G_gain_db[0] = -5; lna2G_gain_db[1] = 6; lna2G_gain_db[2] = 10; lna2G_gain_db[3] = 14; lna2G_gain_db_rev5[0] = -3; lna2G_gain_db_rev5[1] = 7; lna2G_gain_db_rev5[2] = 11; lna2G_gain_db_rev5[3] = 16; lna2G_gain_db_rev6[0] = -5; lna2G_gain_db_rev6[1] = 6; lna2G_gain_db_rev6[2] = 10; lna2G_gain_db_rev6[3] = 14; lna2G_gain_db_rev6_224B0[0] = -5; lna2G_gain_db_rev6_224B0[1] = 6; lna2G_gain_db_rev6_224B0[2] = 10; lna2G_gain_db_rev6_224B0[3] = 15; lna2A_gain_db[0] = -6; lna2A_gain_db[1] = 2; lna2A_gain_db[2] = 6; lna2A_gain_db[3] = 10; lna2A_gain_db_rev4[0] = -5; lna2A_gain_db_rev4[1] = 2; lna2A_gain_db_rev4[2] = 6; lna2A_gain_db_rev4[3] = 10; lna2A_gain_db_rev5[0] = -7; lna2A_gain_db_rev5[1] = 0; lna2A_gain_db_rev5[2] = 4; lna2A_gain_db_rev5[3] = 8; lna2A_gain_db_rev6[0] = -7; lna2A_gain_db_rev6[1] = 0; lna2A_gain_db_rev6[2] = 4; lna2A_gain_db_rev6[3] = 8; lna2_gain_db = (s8 *)0; tiaG_gain_db[0] = 10; tiaG_gain_db[1] = 10; tiaG_gain_db[2] = 10; tiaG_gain_db[3] = 10; tiaG_gain_db[4] = 10; tiaG_gain_db[5] = 10; tiaG_gain_db[6] = 10; tiaG_gain_db[7] = 10; tiaG_gain_db[8] = 10; tiaG_gain_db[9] = 10; tiaA_gain_db[0] = 19; tiaA_gain_db[1] = 19; tiaA_gain_db[2] = 19; tiaA_gain_db[3] = 19; tiaA_gain_db[4] = 19; tiaA_gain_db[5] = 19; tiaA_gain_db[6] = 19; tiaA_gain_db[7] = 19; tiaA_gain_db[8] = 19; tiaA_gain_db[9] = 19; tiaA_gain_db_rev4[0] = 13; tiaA_gain_db_rev4[1] = 13; tiaA_gain_db_rev4[2] = 13; tiaA_gain_db_rev4[3] = 13; tiaA_gain_db_rev4[4] = 13; tiaA_gain_db_rev4[5] = 13; tiaA_gain_db_rev4[6] = 13; tiaA_gain_db_rev4[7] = 13; tiaA_gain_db_rev4[8] = 13; tiaA_gain_db_rev4[9] = 13; tiaA_gain_db_rev5[0] = 13; tiaA_gain_db_rev5[1] = 13; tiaA_gain_db_rev5[2] = 13; tiaA_gain_db_rev5[3] = 13; tiaA_gain_db_rev5[4] = 13; tiaA_gain_db_rev5[5] = 13; tiaA_gain_db_rev5[6] = 13; tiaA_gain_db_rev5[7] = 13; tiaA_gain_db_rev5[8] = 13; tiaA_gain_db_rev5[9] = 13; tiaA_gain_db_rev6[0] = 13; tiaA_gain_db_rev6[1] = 13; tiaA_gain_db_rev6[2] = 13; tiaA_gain_db_rev6[3] = 13; tiaA_gain_db_rev6[4] = 13; tiaA_gain_db_rev6[5] = 13; tiaA_gain_db_rev6[6] = 13; tiaA_gain_db_rev6[7] = 13; tiaA_gain_db_rev6[8] = 13; tiaA_gain_db_rev6[9] = 13; tiaG_gainbits[0] = 3; tiaG_gainbits[1] = 3; tiaG_gainbits[2] = 3; tiaG_gainbits[3] = 3; tiaG_gainbits[4] = 3; tiaG_gainbits[5] = 3; tiaG_gainbits[6] = 3; tiaG_gainbits[7] = 3; tiaG_gainbits[8] = 3; tiaG_gainbits[9] = 3; tiaA_gainbits[0] = 6; tiaA_gainbits[1] = 6; tiaA_gainbits[2] = 6; tiaA_gainbits[3] = 6; tiaA_gainbits[4] = 6; tiaA_gainbits[5] = 6; tiaA_gainbits[6] = 6; tiaA_gainbits[7] = 6; tiaA_gainbits[8] = 6; tiaA_gainbits[9] = 6; tiaA_gainbits_rev4[0] = 4; tiaA_gainbits_rev4[1] = 4; tiaA_gainbits_rev4[2] = 4; tiaA_gainbits_rev4[3] = 4; tiaA_gainbits_rev4[4] = 4; tiaA_gainbits_rev4[5] = 4; tiaA_gainbits_rev4[6] = 4; tiaA_gainbits_rev4[7] = 4; tiaA_gainbits_rev4[8] = 4; tiaA_gainbits_rev4[9] = 4; tiaA_gainbits_rev5[0] = 4; tiaA_gainbits_rev5[1] = 4; tiaA_gainbits_rev5[2] = 4; tiaA_gainbits_rev5[3] = 4; tiaA_gainbits_rev5[4] = 4; tiaA_gainbits_rev5[5] = 4; tiaA_gainbits_rev5[6] = 4; tiaA_gainbits_rev5[7] = 4; tiaA_gainbits_rev5[8] = 4; tiaA_gainbits_rev5[9] = 4; tiaA_gainbits_rev6[0] = 4; tiaA_gainbits_rev6[1] = 4; tiaA_gainbits_rev6[2] = 4; tiaA_gainbits_rev6[3] = 4; tiaA_gainbits_rev6[4] = 4; tiaA_gainbits_rev6[5] = 4; tiaA_gainbits_rev6[6] = 4; tiaA_gainbits_rev6[7] = 4; tiaA_gainbits_rev6[8] = 4; tiaA_gainbits_rev6[9] = 4; lpf_gain_db[0] = 0; lpf_gain_db[1] = 6; lpf_gain_db[2] = 12; lpf_gain_db[3] = 18; lpf_gain_db[4] = 18; lpf_gain_db[5] = 18; lpf_gainbits[0] = 0; lpf_gainbits[1] = 1; lpf_gainbits[2] = 2; lpf_gainbits[3] = 3; lpf_gainbits[4] = 3; lpf_gainbits[5] = 3; rfseqG_init_gain[0] = 24895U; rfseqG_init_gain[1] = 24895U; rfseqG_init_gain[2] = 24895U; rfseqG_init_gain[3] = 24895U; rfseqG_init_gain_rev4[0] = 20799U; rfseqG_init_gain_rev4[1] = 20799U; rfseqG_init_gain_rev4[2] = 20799U; rfseqG_init_gain_rev4[3] = 20799U; rfseqG_init_gain_rev5[0] = 16703U; rfseqG_init_gain_rev5[1] = 16703U; rfseqG_init_gain_rev5[2] = 16703U; rfseqG_init_gain_rev5[3] = 16703U; rfseqG_init_gain_rev5_elna[0] = 319U; rfseqG_init_gain_rev5_elna[1] = 319U; rfseqG_init_gain_rev5_elna[2] = 319U; rfseqG_init_gain_rev5_elna[3] = 319U; rfseqG_init_gain_rev6[0] = 20799U; rfseqG_init_gain_rev6[1] = 20799U; rfseqG_init_gain_rev6_224B0[0] = 16703U; rfseqG_init_gain_rev6_224B0[1] = 16703U; rfseqG_init_gain_rev6_elna[0] = 4415U; rfseqG_init_gain_rev6_elna[1] = 4415U; rfseqA_init_gain[0] = 20847U; rfseqA_init_gain[1] = 20847U; rfseqA_init_gain[2] = 20847U; rfseqA_init_gain[3] = 20847U; rfseqA_init_gain_rev4[0] = 24911U; rfseqA_init_gain_rev4[1] = 24911U; rfseqA_init_gain_rev4[2] = 24911U; rfseqA_init_gain_rev4[3] = 24911U; rfseqA_init_gain_rev4_elna[0] = 12623U; rfseqA_init_gain_rev4_elna[1] = 12623U; rfseqA_init_gain_rev4_elna[2] = 12623U; rfseqA_init_gain_rev4_elna[3] = 12623U; rfseqA_init_gain_rev5[0] = 29007U; rfseqA_init_gain_rev5[1] = 29007U; rfseqA_init_gain_rev5[2] = 29007U; rfseqA_init_gain_rev5[3] = 29007U; rfseqA_init_gain_rev6[0] = 29007U; rfseqA_init_gain_rev6[1] = 29007U; initG_gaincode = 25214U; initG_gaincode_rev4 = 21118U; initG_gaincode_rev5 = 17022U; initG_gaincode_rev5_elna = 638U; initG_gaincode_rev6 = 21118U; initG_gaincode_rev6_224B0 = 17022U; initG_gaincode_rev6_elna = 4734U; initA_gaincode = 21214U; initA_gaincode_rev4 = 25246U; initA_gaincode_rev4_elna = 12958U; initA_gaincode_rev5 = 29342U; initA_gaincode_rev6 = 29342U; clip1hiG_gaincode = 4222U; clip1hiG_gaincode_rev4 = 126U; clip1hiG_gaincode_rev5 = 4214U; clip1hiG_gaincode_rev6 = 126U; clip1hiA_gaincode = 222U; clip1hiA_gaincode_rev4 = 670U; clip1hiA_gaincode_rev5 = 670U; clip1hiA_gaincode_rev6 = 670U; clip1mdG_gaincode = 102U; clip1mdA_gaincode = 202U; clip1mdA_gaincode_rev4 = 4228U; clip1mdA_gaincode_rev5 = 8324U; clip1mdA_gaincode_rev6 = 8324U; clip1md_gaincode = 0U; clip1loG_gaincode = 116U; clip1loG_gaincode_rev5[0] = 98U; clip1loG_gaincode_rev5[1] = 100U; clip1loG_gaincode_rev5[2] = 106U; clip1loG_gaincode_rev5[3] = 4202U; clip1loG_gaincode_rev5[4] = 4204U; clip1loG_gaincode_rev5[5] = 4212U; clip1loG_gaincode_rev5[6] = 4220U; clip1loG_gaincode_rev5[7] = 8316U; clip1loG_gaincode_rev6[0] = 4202U; clip1loG_gaincode_rev6[1] = 4204U; clip1loG_gaincode_rev6[2] = 4212U; clip1loG_gaincode_rev6[3] = 4220U; clip1loG_gaincode_rev6[4] = 126U; clip1loG_gaincode_rev6[5] = 4222U; clip1loG_gaincode_rev6[6] = 8318U; clip1loG_gaincode_rev6[7] = 12414U; clip1loG_gaincode_rev6_224B0 = 4212U; clip1loA_gaincode = 204U; clip1loA_gaincode_rev4 = 134U; clip1loA_gaincode_rev5 = 8326U; clip1loA_gaincode_rev6 = 8326U; crsminG_th = 24U; crsminG_th_rev5 = 24U; crsminG_th_rev6 = 24U; crsminA_th = 30U; crsminA_th_rev4 = 36U; crsminA_th_rev5 = 36U; crsminA_th_rev6 = 36U; crsminlG_th = 24U; crsminlG_th_rev5 = 24U; crsminlG_th_rev6 = 24U; crsminlA_th = 30U; crsminlA_th_rev4 = 36U; crsminlA_th_rev5 = 36U; crsminlA_th_rev6 = 36U; crsminl_th = 0U; crsminuG_th = 24U; crsminuG_th_rev5 = 24U; crsminuG_th_rev6 = 24U; crsminuA_th = 30U; crsminuA_th_rev4 = 36U; crsminuA_th_rev5 = 36U; crsminuA_th_rev6 = 36U; crsminuA_th_rev6_224B0 = 45U; nbclipG_th = 525U; nbclipG_th_rev4 = 417U; nbclipG_th_rev5 = 464U; nbclipG_th_rev6 = 464U; nbclipA_th = 417U; nbclipA_th_rev4 = 263U; nbclipA_th_rev5 = 169U; nbclipA_th_rev6 = 240U; nbclip_th = 0U; w1clipG_th = 5U; w1clipG_th_rev5 = 9U; w1clipG_th_rev6 = 5U; w1clipA_th = 25U; rssi_gain_default = 80U; rssiG_gain_rev6_224B0 = 80U; rssiA_gain_rev5 = 144U; rssiA_gain_rev6 = 144U; triso = ((int )pi->radio_chanspec & 61440) == 4096 ? pi->srom_fem5g.triso : pi->srom_fem2g.triso; if (pi->pubpi.phy_rev > 6U) { if ((unsigned int )pi->pubpi.radiorev == 5U) { wlc_phy_workarounds_nphy_gainctrl_2057_rev5(pi); } else if ((unsigned int )pi->pubpi.radiorev == 7U) { wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi); mod_phy_reg(pi, 643, 255, 68); mod_phy_reg(pi, 640, 255, 68); } else if ((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 8U) { wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi); if ((unsigned int )pi->pubpi.radiorev == 8U) { mod_phy_reg(pi, 643, 255, 68); mod_phy_reg(pi, 640, 255, 68); } else { } } else { wlc_phy_workarounds_nphy_gainctrl_2057_rev6(pi); } } else if (pi->pubpi.phy_rev > 2U) { mod_phy_reg(pi, 160, 64, 64); mod_phy_reg(pi, 28, 8192, 8192); mod_phy_reg(pi, 50, 8192, 8192); tmp = read_phy_reg(pi, 9); currband = (unsigned int )tmp & 1U; if ((unsigned int )currband == 0U) { if (pi->pubpi.phy_rev > 5U) { if ((unsigned int )pi->pubpi.radiorev == 11U) { lna1_gain_db = (s8 *)(& lna1G_gain_db_rev6_224B0); lna2_gain_db = (s8 *)(& lna2G_gain_db_rev6_224B0); rfseq_init_gain = (u16 *)(& rfseqG_init_gain_rev6_224B0); init_gaincode = initG_gaincode_rev6_224B0; clip1hi_gaincode = clip1hiG_gaincode_rev6; clip1lo_gaincode = clip1loG_gaincode_rev6_224B0; nbclip_th = nbclipG_th_rev6; w1clip_th = w1clipG_th_rev6; crsmin_th = crsminG_th_rev6; crsminl_th = crsminlG_th_rev6; crsminu_th = crsminuG_th_rev6; rssi_gain = rssiG_gain_rev6_224B0; } else { lna1_gain_db = (s8 *)(& lna1G_gain_db_rev6); lna2_gain_db = (s8 *)(& lna2G_gain_db_rev6); if (((pi->sh)->boardflags & 4096U) != 0U) { rfseq_init_gain = (u16 *)(& rfseqG_init_gain_rev6_elna); init_gaincode = initG_gaincode_rev6_elna; } else { rfseq_init_gain = (u16 *)(& rfseqG_init_gain_rev6); init_gaincode = initG_gaincode_rev6; } clip1hi_gaincode = clip1hiG_gaincode_rev6; switch ((int )triso) { case 0: clip1lo_gaincode = clip1loG_gaincode_rev6[0]; goto ldv_37914; case 1: clip1lo_gaincode = clip1loG_gaincode_rev6[1]; goto ldv_37914; case 2: clip1lo_gaincode = clip1loG_gaincode_rev6[2]; goto ldv_37914; case 3: ; default: clip1lo_gaincode = clip1loG_gaincode_rev6[3]; goto ldv_37914; case 4: clip1lo_gaincode = clip1loG_gaincode_rev6[4]; goto ldv_37914; case 5: clip1lo_gaincode = clip1loG_gaincode_rev6[5]; goto ldv_37914; case 6: clip1lo_gaincode = clip1loG_gaincode_rev6[6]; goto ldv_37914; case 7: clip1lo_gaincode = clip1loG_gaincode_rev6[7]; goto ldv_37914; } ldv_37914: nbclip_th = nbclipG_th_rev6; w1clip_th = w1clipG_th_rev6; crsmin_th = crsminG_th_rev6; crsminl_th = crsminlG_th_rev6; crsminu_th = crsminuG_th_rev6; rssi_gain = rssi_gain_default; } } else if (pi->pubpi.phy_rev == 5U) { lna1_gain_db = (s8 *)(& lna1G_gain_db_rev5); lna2_gain_db = (s8 *)(& lna2G_gain_db_rev5); if (((pi->sh)->boardflags & 4096U) != 0U) { rfseq_init_gain = (u16 *)(& rfseqG_init_gain_rev5_elna); init_gaincode = initG_gaincode_rev5_elna; } else { rfseq_init_gain = (u16 *)(& rfseqG_init_gain_rev5); init_gaincode = initG_gaincode_rev5; } clip1hi_gaincode = clip1hiG_gaincode_rev5; switch ((int )triso) { case 0: clip1lo_gaincode = clip1loG_gaincode_rev5[0]; goto ldv_37924; case 1: clip1lo_gaincode = clip1loG_gaincode_rev5[1]; goto ldv_37924; case 2: clip1lo_gaincode = clip1loG_gaincode_rev5[2]; goto ldv_37924; case 3: clip1lo_gaincode = clip1loG_gaincode_rev5[3]; goto ldv_37924; case 4: clip1lo_gaincode = clip1loG_gaincode_rev5[4]; goto ldv_37924; case 5: clip1lo_gaincode = clip1loG_gaincode_rev5[5]; goto ldv_37924; case 6: clip1lo_gaincode = clip1loG_gaincode_rev5[6]; goto ldv_37924; case 7: clip1lo_gaincode = clip1loG_gaincode_rev5[7]; goto ldv_37924; default: clip1lo_gaincode = clip1loG_gaincode_rev5[3]; goto ldv_37924; } ldv_37924: nbclip_th = nbclipG_th_rev5; w1clip_th = w1clipG_th_rev5; crsmin_th = crsminG_th_rev5; crsminl_th = crsminlG_th_rev5; crsminu_th = crsminuG_th_rev5; rssi_gain = rssi_gain_default; } else if (pi->pubpi.phy_rev == 4U) { lna1_gain_db = (s8 *)(& lna1G_gain_db_rev4); lna2_gain_db = (s8 *)(& lna2G_gain_db); rfseq_init_gain = (u16 *)(& rfseqG_init_gain_rev4); init_gaincode = initG_gaincode_rev4; clip1hi_gaincode = clip1hiG_gaincode_rev4; clip1lo_gaincode = clip1loG_gaincode; nbclip_th = nbclipG_th_rev4; w1clip_th = w1clipG_th; crsmin_th = crsminG_th; crsminl_th = crsminlG_th; crsminu_th = crsminuG_th; rssi_gain = rssi_gain_default; } else { lna1_gain_db = (s8 *)(& lna1G_gain_db); lna2_gain_db = (s8 *)(& lna2G_gain_db); rfseq_init_gain = (u16 *)(& rfseqG_init_gain); init_gaincode = initG_gaincode; clip1hi_gaincode = clip1hiG_gaincode; clip1lo_gaincode = clip1loG_gaincode; nbclip_th = nbclipG_th; w1clip_th = w1clipG_th; crsmin_th = crsminG_th; crsminl_th = crsminlG_th; crsminu_th = crsminuG_th; rssi_gain = rssi_gain_default; } tia_gain_db = (s8 *)(& tiaG_gain_db); tia_gainbits = (s8 *)(& tiaG_gainbits); clip1md_gaincode = clip1mdG_gaincode; } else { if (pi->pubpi.phy_rev > 5U) { lna1_gain_db = (s8 *)(& lna1A_gain_db_rev6); lna2_gain_db = (s8 *)(& lna2A_gain_db_rev6); tia_gain_db = (s8 *)(& tiaA_gain_db_rev6); tia_gainbits = (s8 *)(& tiaA_gainbits_rev6); rfseq_init_gain = (u16 *)(& rfseqA_init_gain_rev6); init_gaincode = initA_gaincode_rev6; clip1hi_gaincode = clip1hiA_gaincode_rev6; clip1md_gaincode = clip1mdA_gaincode_rev6; clip1lo_gaincode = clip1loA_gaincode_rev6; crsmin_th = crsminA_th_rev6; crsminl_th = crsminlA_th_rev6; if ((unsigned int )pi->pubpi.radiorev == 11U && ((int )pi->radio_chanspec & 3072) != 3072) { crsminu_th = crsminuA_th_rev6_224B0; } else { crsminu_th = crsminuA_th_rev6; } nbclip_th = nbclipA_th_rev6; rssi_gain = rssiA_gain_rev6; } else if (pi->pubpi.phy_rev == 5U) { lna1_gain_db = (s8 *)(& lna1A_gain_db_rev5); lna2_gain_db = (s8 *)(& lna2A_gain_db_rev5); tia_gain_db = (s8 *)(& tiaA_gain_db_rev5); tia_gainbits = (s8 *)(& tiaA_gainbits_rev5); rfseq_init_gain = (u16 *)(& rfseqA_init_gain_rev5); init_gaincode = initA_gaincode_rev5; clip1hi_gaincode = clip1hiA_gaincode_rev5; clip1md_gaincode = clip1mdA_gaincode_rev5; clip1lo_gaincode = clip1loA_gaincode_rev5; crsmin_th = crsminA_th_rev5; crsminl_th = crsminlA_th_rev5; crsminu_th = crsminuA_th_rev5; nbclip_th = nbclipA_th_rev5; rssi_gain = rssiA_gain_rev5; } else if (pi->pubpi.phy_rev == 4U) { lna1_gain_db = (s8 *)(& lna1A_gain_db_rev4); lna2_gain_db = (s8 *)(& lna2A_gain_db_rev4); tia_gain_db = (s8 *)(& tiaA_gain_db_rev4); tia_gainbits = (s8 *)(& tiaA_gainbits_rev4); if (((pi->sh)->boardflags & 268435456U) != 0U) { rfseq_init_gain = (u16 *)(& rfseqA_init_gain_rev4_elna); init_gaincode = initA_gaincode_rev4_elna; } else { rfseq_init_gain = (u16 *)(& rfseqA_init_gain_rev4); init_gaincode = initA_gaincode_rev4; } clip1hi_gaincode = clip1hiA_gaincode_rev4; clip1md_gaincode = clip1mdA_gaincode_rev4; clip1lo_gaincode = clip1loA_gaincode_rev4; crsmin_th = crsminA_th_rev4; crsminl_th = crsminlA_th_rev4; crsminu_th = crsminuA_th_rev4; nbclip_th = nbclipA_th_rev4; rssi_gain = rssi_gain_default; } else { lna1_gain_db = (s8 *)(& lna1A_gain_db); lna2_gain_db = (s8 *)(& lna2A_gain_db); tia_gain_db = (s8 *)(& tiaA_gain_db); tia_gainbits = (s8 *)(& tiaA_gainbits); rfseq_init_gain = (u16 *)(& rfseqA_init_gain); init_gaincode = initA_gaincode; clip1hi_gaincode = clip1hiA_gaincode; clip1md_gaincode = clip1mdA_gaincode; clip1lo_gaincode = clip1loA_gaincode; crsmin_th = crsminA_th; crsminl_th = crsminlA_th; crsminu_th = crsminuA_th; nbclip_th = nbclipA_th; rssi_gain = rssi_gain_default; } w1clip_th = w1clipA_th; } write_radio_reg(pi, 24631, 23); write_radio_reg(pi, 28727, 23); write_radio_reg(pi, 24632, 240); write_radio_reg(pi, 28728, 240); write_radio_reg(pi, 24617, 0); write_radio_reg(pi, 28713, 0); write_radio_reg(pi, 24611, (int )rssi_gain); write_radio_reg(pi, 28707, (int )rssi_gain); write_radio_reg(pi, 24624, 23); write_radio_reg(pi, 28720, 23); write_radio_reg(pi, 24625, 255); write_radio_reg(pi, 28721, 255); wlc_phy_table_write_nphy(pi, 0U, 4U, 8U, 8U, (void const *)lna1_gain_db); wlc_phy_table_write_nphy(pi, 1U, 4U, 8U, 8U, (void const *)lna1_gain_db); wlc_phy_table_write_nphy(pi, 0U, 4U, 16U, 8U, (void const *)lna2_gain_db); wlc_phy_table_write_nphy(pi, 1U, 4U, 16U, 8U, (void const *)lna2_gain_db); wlc_phy_table_write_nphy(pi, 0U, 10U, 32U, 8U, (void const *)tia_gain_db); wlc_phy_table_write_nphy(pi, 1U, 10U, 32U, 8U, (void const *)tia_gain_db); wlc_phy_table_write_nphy(pi, 2U, 10U, 32U, 8U, (void const *)tia_gainbits); wlc_phy_table_write_nphy(pi, 3U, 10U, 32U, 8U, (void const *)tia_gainbits); wlc_phy_table_write_nphy(pi, 0U, 6U, 64U, 8U, (void const *)(& lpf_gain_db)); wlc_phy_table_write_nphy(pi, 1U, 6U, 64U, 8U, (void const *)(& lpf_gain_db)); wlc_phy_table_write_nphy(pi, 2U, 6U, 64U, 8U, (void const *)(& lpf_gainbits)); wlc_phy_table_write_nphy(pi, 3U, 6U, 64U, 8U, (void const *)(& lpf_gainbits)); write_phy_reg(pi, 32, (int )init_gaincode); write_phy_reg(pi, 679, (int )init_gaincode); wlc_phy_table_write_nphy(pi, 7U, (u32 )pi->pubpi.phy_corenum, 262U, 16U, (void const *)rfseq_init_gain); write_phy_reg(pi, 34, (int )clip1hi_gaincode); write_phy_reg(pi, 681, (int )clip1hi_gaincode); write_phy_reg(pi, 36, (int )clip1md_gaincode); write_phy_reg(pi, 683, (int )clip1md_gaincode); write_phy_reg(pi, 55, (int )clip1lo_gaincode); write_phy_reg(pi, 685, (int )clip1lo_gaincode); mod_phy_reg(pi, 637, 255, (int )crsmin_th); mod_phy_reg(pi, 640, 255, (int )crsminl_th); mod_phy_reg(pi, 643, 255, (int )crsminu_th); write_phy_reg(pi, 43, (int )nbclip_th); write_phy_reg(pi, 65, (int )nbclip_th); mod_phy_reg(pi, 39, 63, (int )w1clip_th); mod_phy_reg(pi, 61, 63, (int )w1clip_th); write_phy_reg(pi, 336, 32924); } else { mod_phy_reg(pi, 28, 8192, 8192); mod_phy_reg(pi, 50, 8192, 8192); write_phy_reg(pi, 43, 132); write_phy_reg(pi, 65, 132); if (((int )pi->radio_chanspec & 3072) == 2048) { write_phy_reg(pi, 107, 43); write_phy_reg(pi, 108, 43); write_phy_reg(pi, 109, 9); write_phy_reg(pi, 110, 9); } else { } w1th = 21U; mod_phy_reg(pi, 39, 63, (int )w1th); mod_phy_reg(pi, 61, 63, (int )w1th); if (((int )pi->radio_chanspec & 3072) == 2048) { mod_phy_reg(pi, 28, 31, 1); mod_phy_reg(pi, 50, 31, 1); mod_phy_reg(pi, 29, 31, 1); mod_phy_reg(pi, 51, 31, 1); } else { } write_phy_reg(pi, 336, 32924); if ((int )pi->nphy_gain_boost) { if (((int )pi->radio_chanspec & 61440) == 8192 && ((int )pi->radio_chanspec & 3072) == 3072) { hpf_code = 4U; } else { hpf_code = 5U; } } else if (((int )pi->radio_chanspec & 3072) == 3072) { hpf_code = 6U; } else { hpf_code = 7U; } mod_phy_reg(pi, 32, 3968, (int )hpf_code << 7U); mod_phy_reg(pi, 54, 3968, (int )hpf_code << 7U); ctr = 0; goto ldv_37934; ldv_37933: regval[ctr] = (u16 )((int )((short )((int )hpf_code << 8)) | 124); ctr = ctr + 1; ldv_37934: ; if (ctr <= 3) { goto ldv_37933; } else { } wlc_phy_table_write_nphy(pi, 7U, 4U, 262U, 16U, (void const *)(& regval)); wlc_phy_adjust_lnagaintbl_nphy(pi); if ((int )pi->nphy_elna_gain_config) { regval[0] = 0U; regval[1] = 1U; regval[2] = 1U; regval[3] = 1U; wlc_phy_table_write_nphy(pi, 2U, 4U, 8U, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 3U, 4U, 8U, 16U, (void const *)(& regval)); ctr = 0; goto ldv_37937; ldv_37936: regval[ctr] = (u16 )((int )((short )((int )hpf_code << 8)) | 116); ctr = ctr + 1; ldv_37937: ; if (ctr <= 3) { goto ldv_37936; } else { } wlc_phy_table_write_nphy(pi, 7U, 4U, 262U, 16U, (void const *)(& regval)); } else { } if (pi->pubpi.phy_rev == 2U) { ctr = 0; goto ldv_37940; ldv_37939: regval[ctr] = (unsigned int )((u16 )ctr) * 3U; ctr = ctr + 1; ldv_37940: ; if (ctr <= 20) { goto ldv_37939; } else { } wlc_phy_table_write_nphy(pi, 0U, 21U, 32U, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 1U, 21U, 32U, 16U, (void const *)(& regval)); ctr = 0; goto ldv_37943; ldv_37942: regval[ctr] = (unsigned short )ctr; ctr = ctr + 1; ldv_37943: ; if (ctr <= 20) { goto ldv_37942; } else { } wlc_phy_table_write_nphy(pi, 2U, 21U, 32U, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 3U, 21U, 32U, 16U, (void const *)(& regval)); } else { } wlc_phy_set_rfseq_nphy(pi, 5, (u8 *)(& rfseq_updategainu_events), (u8 *)(& rfseq_updategainu_dlys), 3); mod_phy_reg(pi, 339, 65280, 23040); if (((int )pi->radio_chanspec & 61440) == 8192) { mod_phy_reg(pi, 3165, 127, 4); } else { } } return; } } static void wlc_phy_workarounds_nphy(struct brcms_phy *pi ) { u8 rfseq_rx2tx_events[7U] ; u8 rfseq_rx2tx_dlys[7U] ; u8 rfseq_tx2rx_events[7U] ; u8 rfseq_tx2rx_dlys[7U] ; u8 rfseq_tx2rx_events_rev3[8U] ; u8 rfseq_tx2rx_dlys_rev3[8U] ; u8 rfseq_rx2tx_events_rev3[9U] ; u8 rfseq_rx2tx_dlys_rev3[9U] ; u8 rfseq_rx2tx_events_rev3_ipa[9U] ; u8 rfseq_rx2tx_dlys_rev3_ipa[9U] ; u16 rfseq_rx2tx_dacbufpu_rev7[2U] ; s16 alpha0 ; s16 alpha1 ; s16 alpha2 ; s16 beta0 ; s16 beta1 ; s16 beta2 ; u32 leg_data_weights ; u32 ht_data_weights ; u32 nss1_data_weights ; u32 stbc_data_weights ; u8 chan_freq_range ; u16 dac_control ; u16 aux_adc_vmid_rev7_core0[4U] ; u16 aux_adc_vmid_rev7_core1[4U] ; u16 aux_adc_vmid_rev4[4U] ; u16 aux_adc_vmid_rev3[4U] ; u16 *aux_adc_vmid ; u16 aux_adc_gain_rev7[4U] ; u16 aux_adc_gain_rev4[4U] ; u16 aux_adc_gain_rev3[4U] ; u16 *aux_adc_gain ; u16 sk_adc_vmid[4U] ; u16 sk_adc_gain[4U] ; s32 min_nvar_val ; s32 min_nvar_offset_6mbps ; u8 pdetrange ; u8 triso ; u16 regval ; u16 afectrl_adc_ctrl1_rev7 ; u16 afectrl_adc_ctrl2_rev7 ; u16 rfseq_rx2tx_lpf_h_hpc_rev7 ; u16 rfseq_tx2rx_lpf_h_hpc_rev7 ; u16 rfseq_pktgn_lpf_h_hpc_rev7 ; u16 rfseq_htpktgn_lpf_hpc_rev7[3U] ; u16 rfseq_pktgn_lpf_hpc_rev7[2U] ; u16 rfseq_cckpktgn_lpf_hpc_rev7[2U] ; u16 ipalvlshift_3p3_war_en ; u16 rccal_bcap_val ; u16 rccal_scap_val ; u16 rccal_tx20_11b_bcap ; u16 rccal_tx20_11b_scap ; u16 rccal_tx20_11n_bcap ; u16 rccal_tx20_11n_scap ; u16 rccal_tx40_11n_bcap ; u16 rccal_tx40_11n_scap ; u16 rx2tx_lpf_rc_lut_tx20_11b ; u16 rx2tx_lpf_rc_lut_tx20_11n ; u16 rx2tx_lpf_rc_lut_tx40_11n ; u16 tx_lpf_bw_ofdm_20mhz ; u16 tx_lpf_bw_ofdm_40mhz ; u16 tx_lpf_bw_11b ; u16 ipa2g_mainbias ; u16 ipa2g_casconv ; u16 ipa2g_biasfilt ; u16 txgm_idac_bleed ; bool rccal_ovrd ; u16 freq ; int coreNum ; u16 bcm_adc_vmid[4U] ; u16 bcm_adc_gain[4U] ; u16 auxadc_vmid[4U] ; u16 auxadc_gain[4U] ; u16 bcm_adc_vmid___0[4U] ; u16 bcm_adc_gain___0[4U] ; u16 Vmid[2U] ; u16 Av[2U] ; uint i ; u8 war_dlys[7U] ; u16 tmp ; { rfseq_rx2tx_events[0] = 0U; rfseq_rx2tx_events[1] = 1U; rfseq_rx2tx_events[2] = 2U; rfseq_rx2tx_events[3] = 8U; rfseq_rx2tx_events[4] = 4U; rfseq_rx2tx_events[5] = 5U; rfseq_rx2tx_events[6] = 3U; rfseq_rx2tx_dlys[0] = 8U; rfseq_rx2tx_dlys[1] = 6U; rfseq_rx2tx_dlys[2] = 6U; rfseq_rx2tx_dlys[3] = 2U; rfseq_rx2tx_dlys[4] = 4U; rfseq_rx2tx_dlys[5] = 60U; rfseq_rx2tx_dlys[6] = 1U; rfseq_tx2rx_events[0] = 0U; rfseq_tx2rx_events[1] = 3U; rfseq_tx2rx_events[2] = 5U; rfseq_tx2rx_events[3] = 4U; rfseq_tx2rx_events[4] = 2U; rfseq_tx2rx_events[5] = 1U; rfseq_tx2rx_events[6] = 8U; rfseq_tx2rx_dlys[0] = 8U; rfseq_tx2rx_dlys[1] = 6U; rfseq_tx2rx_dlys[2] = 2U; rfseq_tx2rx_dlys[3] = 4U; rfseq_tx2rx_dlys[4] = 4U; rfseq_tx2rx_dlys[5] = 6U; rfseq_tx2rx_dlys[6] = 1U; rfseq_tx2rx_events_rev3[0] = 4U; rfseq_tx2rx_events_rev3[1] = 3U; rfseq_tx2rx_events_rev3[2] = 6U; rfseq_tx2rx_events_rev3[3] = 5U; rfseq_tx2rx_events_rev3[4] = 2U; rfseq_tx2rx_events_rev3[5] = 1U; rfseq_tx2rx_events_rev3[6] = 8U; rfseq_tx2rx_events_rev3[7] = 31U; rfseq_tx2rx_dlys_rev3[0] = 8U; rfseq_tx2rx_dlys_rev3[1] = 4U; rfseq_tx2rx_dlys_rev3[2] = 2U; rfseq_tx2rx_dlys_rev3[3] = 2U; rfseq_tx2rx_dlys_rev3[4] = 4U; rfseq_tx2rx_dlys_rev3[5] = 4U; rfseq_tx2rx_dlys_rev3[6] = 6U; rfseq_tx2rx_dlys_rev3[7] = 1U; rfseq_rx2tx_events_rev3[0] = 0U; rfseq_rx2tx_events_rev3[1] = 1U; rfseq_rx2tx_events_rev3[2] = 2U; rfseq_rx2tx_events_rev3[3] = 8U; rfseq_rx2tx_events_rev3[4] = 5U; rfseq_rx2tx_events_rev3[5] = 6U; rfseq_rx2tx_events_rev3[6] = 3U; rfseq_rx2tx_events_rev3[7] = 4U; rfseq_rx2tx_events_rev3[8] = 31U; rfseq_rx2tx_dlys_rev3[0] = 8U; rfseq_rx2tx_dlys_rev3[1] = 6U; rfseq_rx2tx_dlys_rev3[2] = 6U; rfseq_rx2tx_dlys_rev3[3] = 4U; rfseq_rx2tx_dlys_rev3[4] = 4U; rfseq_rx2tx_dlys_rev3[5] = 18U; rfseq_rx2tx_dlys_rev3[6] = 42U; rfseq_rx2tx_dlys_rev3[7] = 1U; rfseq_rx2tx_dlys_rev3[8] = 1U; rfseq_rx2tx_events_rev3_ipa[0] = 0U; rfseq_rx2tx_events_rev3_ipa[1] = 1U; rfseq_rx2tx_events_rev3_ipa[2] = 2U; rfseq_rx2tx_events_rev3_ipa[3] = 8U; rfseq_rx2tx_events_rev3_ipa[4] = 5U; rfseq_rx2tx_events_rev3_ipa[5] = 6U; rfseq_rx2tx_events_rev3_ipa[6] = 15U; rfseq_rx2tx_events_rev3_ipa[7] = 3U; rfseq_rx2tx_events_rev3_ipa[8] = 31U; rfseq_rx2tx_dlys_rev3_ipa[0] = 8U; rfseq_rx2tx_dlys_rev3_ipa[1] = 6U; rfseq_rx2tx_dlys_rev3_ipa[2] = 6U; rfseq_rx2tx_dlys_rev3_ipa[3] = 4U; rfseq_rx2tx_dlys_rev3_ipa[4] = 4U; rfseq_rx2tx_dlys_rev3_ipa[5] = 16U; rfseq_rx2tx_dlys_rev3_ipa[6] = 43U; rfseq_rx2tx_dlys_rev3_ipa[7] = 1U; rfseq_rx2tx_dlys_rev3_ipa[8] = 1U; rfseq_rx2tx_dacbufpu_rev7[0] = 271U; rfseq_rx2tx_dacbufpu_rev7[1] = 271U; chan_freq_range = 0U; dac_control = 2U; aux_adc_vmid_rev7_core0[0] = 142U; aux_adc_vmid_rev7_core0[1] = 150U; aux_adc_vmid_rev7_core0[2] = 150U; aux_adc_vmid_rev7_core0[3] = 150U; aux_adc_vmid_rev7_core1[0] = 143U; aux_adc_vmid_rev7_core1[1] = 159U; aux_adc_vmid_rev7_core1[2] = 159U; aux_adc_vmid_rev7_core1[3] = 150U; aux_adc_vmid_rev4[0] = 162U; aux_adc_vmid_rev4[1] = 180U; aux_adc_vmid_rev4[2] = 180U; aux_adc_vmid_rev4[3] = 137U; aux_adc_vmid_rev3[0] = 162U; aux_adc_vmid_rev3[1] = 180U; aux_adc_vmid_rev3[2] = 180U; aux_adc_vmid_rev3[3] = 137U; aux_adc_gain_rev7[0] = 2U; aux_adc_gain_rev7[1] = 2U; aux_adc_gain_rev7[2] = 2U; aux_adc_gain_rev7[3] = 2U; aux_adc_gain_rev4[0] = 2U; aux_adc_gain_rev4[1] = 2U; aux_adc_gain_rev4[2] = 2U; aux_adc_gain_rev4[3] = 0U; aux_adc_gain_rev3[0] = 2U; aux_adc_gain_rev3[1] = 2U; aux_adc_gain_rev3[2] = 2U; aux_adc_gain_rev3[3] = 0U; sk_adc_vmid[0] = 180U; sk_adc_vmid[1] = 180U; sk_adc_vmid[2] = 180U; sk_adc_vmid[3] = 36U; sk_adc_gain[0] = 2U; sk_adc_gain[1] = 2U; sk_adc_gain[2] = 2U; sk_adc_gain[3] = 2U; min_nvar_val = 397; min_nvar_offset_6mbps = 20; afectrl_adc_ctrl1_rev7 = 32U; afectrl_adc_ctrl2_rev7 = 0U; rfseq_rx2tx_lpf_h_hpc_rev7 = 119U; rfseq_tx2rx_lpf_h_hpc_rev7 = 119U; rfseq_pktgn_lpf_h_hpc_rev7 = 119U; rfseq_htpktgn_lpf_hpc_rev7[0] = 119U; rfseq_htpktgn_lpf_hpc_rev7[1] = 17U; rfseq_htpktgn_lpf_hpc_rev7[2] = 17U; rfseq_pktgn_lpf_hpc_rev7[0] = 17U; rfseq_pktgn_lpf_hpc_rev7[1] = 17U; rfseq_cckpktgn_lpf_hpc_rev7[0] = 17U; rfseq_cckpktgn_lpf_hpc_rev7[1] = 17U; ipalvlshift_3p3_war_en = 0U; rccal_tx20_11b_bcap = 0U; rccal_tx20_11b_scap = 0U; rccal_tx20_11n_bcap = 0U; rccal_tx20_11n_scap = 0U; rccal_tx40_11n_bcap = 0U; rccal_tx40_11n_scap = 0U; rx2tx_lpf_rc_lut_tx20_11b = 0U; rx2tx_lpf_rc_lut_tx20_11n = 0U; rx2tx_lpf_rc_lut_tx40_11n = 0U; tx_lpf_bw_ofdm_20mhz = 0U; tx_lpf_bw_ofdm_40mhz = 0U; tx_lpf_bw_11b = 0U; txgm_idac_bleed = 0U; rccal_ovrd = 0; if (((int )pi->radio_chanspec & 61440) == 4096) { wlc_phy_classifier_nphy(pi, 1, 0); } else { wlc_phy_classifier_nphy(pi, 1, 1); } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } or_phy_reg(pi, 177, 17); if (pi->pubpi.phy_rev > 6U) { if (pi->pubpi.phy_rev == 7U) { mod_phy_reg(pi, 545, 16, 16); mod_phy_reg(pi, 352, 127, 32); mod_phy_reg(pi, 352, 32512, 9984); mod_phy_reg(pi, 353, 127, 46); mod_phy_reg(pi, 353, 32512, 13056); mod_phy_reg(pi, 354, 127, 55); mod_phy_reg(pi, 354, 32512, 14848); mod_phy_reg(pi, 355, 127, 60); mod_phy_reg(pi, 355, 32512, 15872); mod_phy_reg(pi, 356, 127, 62); mod_phy_reg(pi, 356, 32512, 16128); mod_phy_reg(pi, 357, 127, 63); mod_phy_reg(pi, 357, 32512, 16384); mod_phy_reg(pi, 358, 127, 64); mod_phy_reg(pi, 358, 32512, 16384); mod_phy_reg(pi, 359, 127, 64); mod_phy_reg(pi, 359, 32512, 16384); } else { } write_phy_reg(pi, 575, 432); write_phy_reg(pi, 576, 432); if (pi->pubpi.phy_rev > 7U) { mod_phy_reg(pi, 189, 255, 114); } else { } wlc_phy_table_write_nphy(pi, 8U, 1U, 0U, 16U, (void const *)(& dac_control)); wlc_phy_table_write_nphy(pi, 8U, 1U, 16U, 16U, (void const *)(& dac_control)); wlc_phy_table_read_nphy(pi, 30U, 1U, 0U, 32U, (void *)(& leg_data_weights)); leg_data_weights = leg_data_weights & 16777215U; wlc_phy_table_write_nphy(pi, 30U, 1U, 0U, 32U, (void const *)(& leg_data_weights)); wlc_phy_table_write_nphy(pi, 7U, 2U, 350U, 16U, (void const *)(& rfseq_rx2tx_dacbufpu_rev7)); wlc_phy_table_write_nphy(pi, 7U, 2U, 366U, 16U, (void const *)(& rfseq_rx2tx_dacbufpu_rev7)); if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { wlc_phy_set_rfseq_nphy(pi, 0, (u8 *)(& rfseq_rx2tx_events_rev3_ipa), (u8 *)(& rfseq_rx2tx_dlys_rev3_ipa), 9); } else { } mod_phy_reg(pi, 665, 49152, 16384); mod_phy_reg(pi, 669, 49152, 16384); tx_lpf_bw_ofdm_20mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 340); tx_lpf_bw_ofdm_40mhz = wlc_phy_read_lpf_bw_ctl_nphy(pi, 345); tx_lpf_bw_11b = wlc_phy_read_lpf_bw_ctl_nphy(pi, 338); if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if ((((unsigned int )pi->pubpi.radiorev == 5U && ((int )pi->radio_chanspec & 3072) == 3072) || (unsigned int )pi->pubpi.radiorev == 7U) || (unsigned int )pi->pubpi.radiorev == 8U) { rccal_bcap_val = read_radio_reg(pi, 363); rccal_scap_val = read_radio_reg(pi, 362); rccal_tx20_11b_bcap = rccal_bcap_val; rccal_tx20_11b_scap = rccal_scap_val; if ((unsigned int )pi->pubpi.radiorev == 5U && ((int )pi->radio_chanspec & 3072) == 3072) { rccal_tx20_11n_bcap = rccal_bcap_val; rccal_tx20_11n_scap = rccal_scap_val; rccal_tx40_11n_bcap = 12U; rccal_tx40_11n_scap = 12U; rccal_ovrd = 1; } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { tx_lpf_bw_ofdm_20mhz = 4U; tx_lpf_bw_11b = 1U; if (((int )pi->radio_chanspec & 61440) == 8192) { rccal_tx20_11n_bcap = 12U; rccal_tx20_11n_scap = 12U; rccal_tx40_11n_bcap = 10U; rccal_tx40_11n_scap = 10U; } else { rccal_tx20_11n_bcap = 20U; rccal_tx20_11n_scap = 20U; rccal_tx40_11n_bcap = 15U; rccal_tx40_11n_scap = 15U; } rccal_ovrd = 1; } else { } } else { } } else if ((unsigned int )pi->pubpi.radiorev == 5U) { tx_lpf_bw_ofdm_20mhz = 1U; tx_lpf_bw_ofdm_40mhz = 3U; rccal_bcap_val = read_radio_reg(pi, 363); rccal_scap_val = read_radio_reg(pi, 362); rccal_tx20_11b_bcap = rccal_bcap_val; rccal_tx20_11b_scap = rccal_scap_val; rccal_tx20_11n_bcap = 19U; rccal_tx20_11n_scap = 17U; rccal_tx40_11n_bcap = 19U; rccal_tx40_11n_scap = 17U; rccal_ovrd = 1; } else { } if ((int )rccal_ovrd) { rx2tx_lpf_rc_lut_tx20_11b = (u16 )(((int )((short )((int )rccal_tx20_11b_bcap << 8)) | (int )((short )((int )rccal_tx20_11b_scap << 3))) | (int )((short )tx_lpf_bw_11b)); rx2tx_lpf_rc_lut_tx20_11n = (u16 )(((int )((short )((int )rccal_tx20_11n_bcap << 8)) | (int )((short )((int )rccal_tx20_11n_scap << 3))) | (int )((short )tx_lpf_bw_ofdm_20mhz)); rx2tx_lpf_rc_lut_tx40_11n = (u16 )(((int )((short )((int )rccal_tx40_11n_bcap << 8)) | (int )((short )((int )rccal_tx40_11n_scap << 3))) | (int )((short )tx_lpf_bw_ofdm_40mhz)); coreNum = 0; goto ldv_38020; ldv_38019: wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )(coreNum * 16 + 338), 16U, (void const *)(& rx2tx_lpf_rc_lut_tx20_11b)); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )(coreNum * 16 + 339), 16U, (void const *)(& rx2tx_lpf_rc_lut_tx20_11n)); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )(coreNum * 16 + 340), 16U, (void const *)(& rx2tx_lpf_rc_lut_tx20_11n)); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )(coreNum * 16 + 341), 16U, (void const *)(& rx2tx_lpf_rc_lut_tx40_11n)); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )(coreNum * 16 + 342), 16U, (void const *)(& rx2tx_lpf_rc_lut_tx40_11n)); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )(coreNum * 16 + 343), 16U, (void const *)(& rx2tx_lpf_rc_lut_tx40_11n)); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )(coreNum * 16 + 344), 16U, (void const *)(& rx2tx_lpf_rc_lut_tx40_11n)); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )(coreNum * 16 + 345), 16U, (void const *)(& rx2tx_lpf_rc_lut_tx40_11n)); coreNum = coreNum + 1; ldv_38020: ; if (coreNum <= 1) { goto ldv_38019; } else { } wlc_phy_rfctrl_override_nphy_rev7(pi, 16, 1, 3, 0, 2); } else { } write_phy_reg(pi, 815, 3); if ((unsigned int )pi->pubpi.radiorev == 4U || (unsigned int )pi->pubpi.radiorev == 6U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 4, 1, 3, 0, 0); } else { } if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { if ((pi->sh)->sromrev > 7U && ((pi->sh)->boardflags2 & 131072U) != 0U) { ipalvlshift_3p3_war_en = 1U; } else { } if ((unsigned int )ipalvlshift_3p3_war_en != 0U) { write_radio_reg(pi, 5, 5); write_radio_reg(pi, 6, 48); write_radio_reg(pi, 7, 0); or_radio_reg(pi, 79, 1); or_radio_reg(pi, 212, 1); ipa2g_mainbias = 31U; ipa2g_casconv = 111U; ipa2g_biasfilt = 170U; } else { ipa2g_mainbias = 43U; ipa2g_casconv = 127U; ipa2g_biasfilt = 238U; } if (((int )pi->radio_chanspec & 61440) == 8192) { coreNum = 0; goto ldv_38023; ldv_38022: write_radio_reg(pi, coreNum == 0 ? 99 : 232, (int )ipa2g_mainbias); write_radio_reg(pi, coreNum == 0 ? 100 : 233, (int )ipa2g_casconv); write_radio_reg(pi, coreNum == 0 ? 102 : 235, (int )ipa2g_biasfilt); coreNum = coreNum + 1; ldv_38023: ; if (coreNum <= 1) { goto ldv_38022; } else { } } else { } } else { } if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if (((int )pi->radio_chanspec & 61440) == 8192) { if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { txgm_idac_bleed = 127U; } else { } coreNum = 0; goto ldv_38026; ldv_38025: ; if ((unsigned int )txgm_idac_bleed != 0U) { write_radio_reg(pi, coreNum == 0 ? 81 : 214, (int )txgm_idac_bleed); } else { } coreNum = coreNum + 1; ldv_38026: ; if (coreNum <= 1) { goto ldv_38025; } else { } if ((unsigned int )pi->pubpi.radiorev == 5U) { coreNum = 0; goto ldv_38029; ldv_38028: write_radio_reg(pi, coreNum == 0 ? 100 : 233, 19); write_radio_reg(pi, coreNum == 0 ? 99 : 232, 31); write_radio_reg(pi, coreNum == 0 ? 102 : 235, 238); write_radio_reg(pi, coreNum == 0 ? 89 : 222, 138); write_radio_reg(pi, coreNum == 0 ? 128 : 261, 62); coreNum = coreNum + 1; ldv_38029: ; if (coreNum <= 1) { goto ldv_38028; } else { } } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { if (((int )pi->radio_chanspec & 3072) != 3072) { write_radio_reg(pi, 99, 20); write_radio_reg(pi, 232, 18); } else { write_radio_reg(pi, 99, 22); write_radio_reg(pi, 232, 22); } } else { } } else { freq = (unsigned int )((u16 )((unsigned char )pi->radio_chanspec)) * 5U + 5000U; if (((unsigned int )freq > 5179U && (unsigned int )freq <= 5230U) || ((unsigned int )freq > 5744U && (unsigned int )freq <= 5805U)) { write_radio_reg(pi, 125, 255); write_radio_reg(pi, 258, 255); } else { } } } else if ((unsigned int )pi->pubpi.radiorev != 5U) { coreNum = 0; goto ldv_38032; ldv_38031: write_radio_reg(pi, coreNum == 0 ? 92 : 225, 97); write_radio_reg(pi, coreNum == 0 ? 81 : 214, 112); coreNum = coreNum + 1; ldv_38032: ; if (coreNum <= 1) { goto ldv_38031; } else { } } else { } if ((unsigned int )pi->pubpi.radiorev == 4U) { wlc_phy_table_write_nphy(pi, 8U, 1U, 5U, 16U, (void const *)(& afectrl_adc_ctrl1_rev7)); wlc_phy_table_write_nphy(pi, 8U, 1U, 21U, 16U, (void const *)(& afectrl_adc_ctrl1_rev7)); coreNum = 0; goto ldv_38035; ldv_38034: write_radio_reg(pi, coreNum == 0 ? 417 : 423, 0); write_radio_reg(pi, coreNum == 0 ? 418 : 424, 63); write_radio_reg(pi, coreNum == 0 ? 419 : 425, 63); coreNum = coreNum + 1; ldv_38035: ; if (coreNum <= 1) { goto ldv_38034; } else { } } else { mod_phy_reg(pi, 166, 4, 4); mod_phy_reg(pi, 143, 4, 4); mod_phy_reg(pi, 167, 4, 4); mod_phy_reg(pi, 165, 4, 4); mod_phy_reg(pi, 166, 1, 0); mod_phy_reg(pi, 143, 1, 1); mod_phy_reg(pi, 167, 1, 0); mod_phy_reg(pi, 165, 1, 1); wlc_phy_table_write_nphy(pi, 8U, 1U, 5U, 16U, (void const *)(& afectrl_adc_ctrl2_rev7)); wlc_phy_table_write_nphy(pi, 8U, 1U, 21U, 16U, (void const *)(& afectrl_adc_ctrl2_rev7)); mod_phy_reg(pi, 166, 4, 0); mod_phy_reg(pi, 143, 4, 0); mod_phy_reg(pi, 167, 4, 0); mod_phy_reg(pi, 165, 4, 0); } write_phy_reg(pi, 106, 2); wlc_phy_table_write_nphy(pi, 16U, 1U, 256U, 32U, (void const *)(& min_nvar_offset_6mbps)); wlc_phy_table_write_nphy(pi, 7U, 2U, 312U, 16U, (void const *)(& rfseq_pktgn_lpf_hpc_rev7)); wlc_phy_table_write_nphy(pi, 7U, 1U, 321U, 16U, (void const *)(& rfseq_pktgn_lpf_h_hpc_rev7)); wlc_phy_table_write_nphy(pi, 7U, 3U, 307U, 16U, (void const *)(& rfseq_htpktgn_lpf_hpc_rev7)); wlc_phy_table_write_nphy(pi, 7U, 2U, 326U, 16U, (void const *)(& rfseq_cckpktgn_lpf_hpc_rev7)); wlc_phy_table_write_nphy(pi, 7U, 1U, 291U, 16U, (void const *)(& rfseq_tx2rx_lpf_h_hpc_rev7)); wlc_phy_table_write_nphy(pi, 7U, 1U, 298U, 16U, (void const *)(& rfseq_rx2tx_lpf_h_hpc_rev7)); if (((int )pi->radio_chanspec & 3072) != 3072) { wlc_phy_table_write_nphy(pi, 16U, 1U, 3U, 32U, (void const *)(& min_nvar_val)); wlc_phy_table_write_nphy(pi, 16U, 1U, 127U, 32U, (void const *)(& min_nvar_val)); } else { min_nvar_val = (s32 )noise_var_tbl_rev7[3]; wlc_phy_table_write_nphy(pi, 16U, 1U, 3U, 32U, (void const *)(& min_nvar_val)); min_nvar_val = (s32 )noise_var_tbl_rev7[127]; wlc_phy_table_write_nphy(pi, 16U, 1U, 127U, 32U, (void const *)(& min_nvar_val)); } wlc_phy_workarounds_nphy_gainctrl(pi); pdetrange = ((int )pi->radio_chanspec & 61440) == 4096 ? pi->srom_fem5g.pdetrange : pi->srom_fem2g.pdetrange; if ((unsigned int )pdetrange == 0U) { chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0U); if ((unsigned int )chan_freq_range != 0U) { aux_adc_vmid_rev7_core0[3] = 112U; aux_adc_vmid_rev7_core1[3] = 112U; aux_adc_gain_rev7[3] = 2U; } else { aux_adc_vmid_rev7_core0[3] = 128U; aux_adc_vmid_rev7_core1[3] = 128U; aux_adc_gain_rev7[3] = 3U; } } else if ((unsigned int )pdetrange == 1U) { if ((unsigned int )chan_freq_range != 0U) { aux_adc_vmid_rev7_core0[3] = 124U; aux_adc_vmid_rev7_core1[3] = 124U; aux_adc_gain_rev7[3] = 2U; } else { aux_adc_vmid_rev7_core0[3] = 140U; aux_adc_vmid_rev7_core1[3] = 140U; aux_adc_gain_rev7[3] = 1U; } } else if ((unsigned int )pdetrange == 2U) { if ((unsigned int )pi->pubpi.radioid == 8279U) { if (((unsigned int )pi->pubpi.radiorev == 5U || (unsigned int )pi->pubpi.radiorev == 7U) || (unsigned int )pi->pubpi.radiorev == 8U) { if ((unsigned int )chan_freq_range == 0U) { aux_adc_vmid_rev7_core0[3] = 140U; aux_adc_vmid_rev7_core1[3] = 140U; aux_adc_gain_rev7[3] = 0U; } else { aux_adc_vmid_rev7_core0[3] = 150U; aux_adc_vmid_rev7_core1[3] = 150U; aux_adc_gain_rev7[3] = 0U; } } else { } } else { } } else if ((unsigned int )pdetrange == 3U) { if ((unsigned int )chan_freq_range == 0U) { aux_adc_vmid_rev7_core0[3] = 137U; aux_adc_vmid_rev7_core1[3] = 137U; aux_adc_gain_rev7[3] = 0U; } else { } } else if ((unsigned int )pdetrange == 5U) { if ((unsigned int )chan_freq_range != 0U) { aux_adc_vmid_rev7_core0[3] = 128U; aux_adc_vmid_rev7_core1[3] = 128U; aux_adc_gain_rev7[3] = 3U; } else { aux_adc_vmid_rev7_core0[3] = 112U; aux_adc_vmid_rev7_core1[3] = 112U; aux_adc_gain_rev7[3] = 2U; } } else { } wlc_phy_table_write_nphy(pi, 8U, 4U, 8U, 16U, (void const *)(& aux_adc_vmid_rev7_core0)); wlc_phy_table_write_nphy(pi, 8U, 4U, 24U, 16U, (void const *)(& aux_adc_vmid_rev7_core1)); wlc_phy_table_write_nphy(pi, 8U, 4U, 12U, 16U, (void const *)(& aux_adc_gain_rev7)); wlc_phy_table_write_nphy(pi, 8U, 4U, 28U, 16U, (void const *)(& aux_adc_gain_rev7)); } else if (pi->pubpi.phy_rev > 2U) { write_phy_reg(pi, 575, 504); write_phy_reg(pi, 576, 504); wlc_phy_table_read_nphy(pi, 30U, 1U, 0U, 32U, (void *)(& leg_data_weights)); leg_data_weights = leg_data_weights & 16777215U; wlc_phy_table_write_nphy(pi, 30U, 1U, 0U, 32U, (void const *)(& leg_data_weights)); alpha0 = 293; alpha1 = 435; alpha2 = 261; beta0 = 366; beta1 = 205; beta2 = 32; write_phy_reg(pi, 325, (int )((u16 )alpha0)); write_phy_reg(pi, 326, (int )((u16 )alpha1)); write_phy_reg(pi, 327, (int )((u16 )alpha2)); write_phy_reg(pi, 328, (int )((u16 )beta0)); write_phy_reg(pi, 329, (int )((u16 )beta1)); write_phy_reg(pi, 330, (int )((u16 )beta2)); write_phy_reg(pi, 56, 12); write_phy_reg(pi, 686, 12); wlc_phy_set_rfseq_nphy(pi, 1, (u8 *)(& rfseq_tx2rx_events_rev3), (u8 *)(& rfseq_tx2rx_dlys_rev3), 8); if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { wlc_phy_set_rfseq_nphy(pi, 0, (u8 *)(& rfseq_rx2tx_events_rev3_ipa), (u8 *)(& rfseq_rx2tx_dlys_rev3_ipa), 9); } else { } if ((unsigned int )(pi->sh)->hw_phyrxchain != 3U && (int )(pi->sh)->hw_phyrxchain != (int )(pi->sh)->hw_phytxchain) { if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { rfseq_rx2tx_dlys_rev3[5] = 59U; rfseq_rx2tx_dlys_rev3[6] = 1U; rfseq_rx2tx_events_rev3[7] = 31U; } else { } wlc_phy_set_rfseq_nphy(pi, 0, (u8 *)(& rfseq_rx2tx_events_rev3), (u8 *)(& rfseq_rx2tx_dlys_rev3), 9); } else { } if (((int )pi->radio_chanspec & 61440) == 8192) { write_phy_reg(pi, 106, 2); } else { write_phy_reg(pi, 106, 40000); } mod_phy_reg(pi, 660, 3840, 1792); if (((int )pi->radio_chanspec & 3072) != 3072) { wlc_phy_table_write_nphy(pi, 16U, 1U, 3U, 32U, (void const *)(& min_nvar_val)); wlc_phy_table_write_nphy(pi, 16U, 1U, 127U, 32U, (void const *)(& min_nvar_val)); } else { min_nvar_val = (s32 )noise_var_tbl_rev3[3]; wlc_phy_table_write_nphy(pi, 16U, 1U, 3U, 32U, (void const *)(& min_nvar_val)); min_nvar_val = (s32 )noise_var_tbl_rev3[127]; wlc_phy_table_write_nphy(pi, 16U, 1U, 127U, 32U, (void const *)(& min_nvar_val)); } wlc_phy_workarounds_nphy_gainctrl(pi); wlc_phy_table_write_nphy(pi, 8U, 1U, 0U, 16U, (void const *)(& dac_control)); wlc_phy_table_write_nphy(pi, 8U, 1U, 16U, 16U, (void const *)(& dac_control)); pdetrange = ((int )pi->radio_chanspec & 61440) == 4096 ? pi->srom_fem5g.pdetrange : pi->srom_fem2g.pdetrange; if ((unsigned int )pdetrange == 0U) { if (pi->pubpi.phy_rev > 3U) { aux_adc_vmid = (u16 *)(& aux_adc_vmid_rev4); aux_adc_gain = (u16 *)(& aux_adc_gain_rev4); } else { aux_adc_vmid = (u16 *)(& aux_adc_vmid_rev3); aux_adc_gain = (u16 *)(& aux_adc_gain_rev3); } chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0U); if ((unsigned int )chan_freq_range != 0U) { switch ((int )chan_freq_range) { case 1: *(aux_adc_vmid + 3UL) = 137U; *(aux_adc_gain + 3UL) = 0U; goto ldv_38044; case 2: *(aux_adc_vmid + 3UL) = 137U; *(aux_adc_gain + 3UL) = 0U; goto ldv_38044; case 3: *(aux_adc_vmid + 3UL) = 137U; *(aux_adc_gain + 3UL) = 0U; goto ldv_38044; default: ; goto ldv_38044; } ldv_38044: ; } else { } wlc_phy_table_write_nphy(pi, 8U, 4U, 8U, 16U, (void const *)aux_adc_vmid); wlc_phy_table_write_nphy(pi, 8U, 4U, 24U, 16U, (void const *)aux_adc_vmid); wlc_phy_table_write_nphy(pi, 8U, 4U, 12U, 16U, (void const *)aux_adc_gain); wlc_phy_table_write_nphy(pi, 8U, 4U, 28U, 16U, (void const *)aux_adc_gain); } else if ((unsigned int )pdetrange == 1U) { wlc_phy_table_write_nphy(pi, 8U, 4U, 8U, 16U, (void const *)(& sk_adc_vmid)); wlc_phy_table_write_nphy(pi, 8U, 4U, 24U, 16U, (void const *)(& sk_adc_vmid)); wlc_phy_table_write_nphy(pi, 8U, 4U, 12U, 16U, (void const *)(& sk_adc_gain)); wlc_phy_table_write_nphy(pi, 8U, 4U, 28U, 16U, (void const *)(& sk_adc_gain)); } else if ((unsigned int )pdetrange == 2U) { bcm_adc_vmid[0] = 162U; bcm_adc_vmid[1] = 180U; bcm_adc_vmid[2] = 180U; bcm_adc_vmid[3] = 116U; bcm_adc_gain[0] = 2U; bcm_adc_gain[1] = 2U; bcm_adc_gain[2] = 2U; bcm_adc_gain[3] = 4U; if (pi->pubpi.phy_rev > 5U) { chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0U); if ((unsigned int )chan_freq_range != 0U) { bcm_adc_vmid[3] = 142U; bcm_adc_gain[3] = 3U; } else { bcm_adc_vmid[3] = 148U; bcm_adc_gain[3] = 3U; } } else if (pi->pubpi.phy_rev == 5U) { bcm_adc_vmid[3] = 132U; bcm_adc_gain[3] = 2U; } else { } wlc_phy_table_write_nphy(pi, 8U, 4U, 8U, 16U, (void const *)(& bcm_adc_vmid)); wlc_phy_table_write_nphy(pi, 8U, 4U, 24U, 16U, (void const *)(& bcm_adc_vmid)); wlc_phy_table_write_nphy(pi, 8U, 4U, 12U, 16U, (void const *)(& bcm_adc_gain)); wlc_phy_table_write_nphy(pi, 8U, 4U, 28U, 16U, (void const *)(& bcm_adc_gain)); } else if ((unsigned int )pdetrange == 3U) { chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0U); if (pi->pubpi.phy_rev > 3U && (unsigned int )chan_freq_range == 0U) { auxadc_vmid[0] = 162U; auxadc_vmid[1] = 180U; auxadc_vmid[2] = 180U; auxadc_vmid[3] = 624U; auxadc_gain[0] = 2U; auxadc_gain[1] = 2U; auxadc_gain[2] = 2U; auxadc_gain[3] = 0U; wlc_phy_table_write_nphy(pi, 8U, 4U, 8U, 16U, (void const *)(& auxadc_vmid)); wlc_phy_table_write_nphy(pi, 8U, 4U, 24U, 16U, (void const *)(& auxadc_vmid)); wlc_phy_table_write_nphy(pi, 8U, 4U, 12U, 16U, (void const *)(& auxadc_gain)); wlc_phy_table_write_nphy(pi, 8U, 4U, 28U, 16U, (void const *)(& auxadc_gain)); } else { } } else if ((unsigned int )pdetrange == 4U || (unsigned int )pdetrange == 5U) { bcm_adc_vmid___0[0] = 162U; bcm_adc_vmid___0[1] = 180U; bcm_adc_vmid___0[2] = 180U; bcm_adc_vmid___0[3] = 0U; bcm_adc_gain___0[0] = 2U; bcm_adc_gain___0[1] = 2U; bcm_adc_gain___0[2] = 2U; bcm_adc_gain___0[3] = 0U; chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0U); if ((unsigned int )chan_freq_range != 0U) { Vmid[0] = (unsigned int )pdetrange == 4U ? 142U : 137U; Vmid[1] = (unsigned int )pdetrange == 4U ? 150U : 137U; Av[0] = (unsigned int )pdetrange == 4U ? 2U : 0U; Av[1] = (unsigned int )pdetrange == 4U ? 2U : 0U; } else { Vmid[0] = (unsigned int )pdetrange == 4U ? 137U : 116U; Vmid[1] = (unsigned int )pdetrange == 4U ? 139U : 112U; Av[0] = (unsigned int )pdetrange == 4U ? 2U : 0U; Av[1] = (unsigned int )pdetrange == 4U ? 2U : 0U; } bcm_adc_vmid___0[3] = Vmid[0]; bcm_adc_gain___0[3] = Av[0]; wlc_phy_table_write_nphy(pi, 8U, 4U, 8U, 16U, (void const *)(& bcm_adc_vmid___0)); wlc_phy_table_write_nphy(pi, 8U, 4U, 12U, 16U, (void const *)(& bcm_adc_gain___0)); bcm_adc_vmid___0[3] = Vmid[1]; bcm_adc_gain___0[3] = Av[1]; wlc_phy_table_write_nphy(pi, 8U, 4U, 24U, 16U, (void const *)(& bcm_adc_vmid___0)); wlc_phy_table_write_nphy(pi, 8U, 4U, 28U, 16U, (void const *)(& bcm_adc_gain___0)); } else { } write_radio_reg(pi, 24643, 0); write_radio_reg(pi, 28739, 0); write_radio_reg(pi, 24641, 6); write_radio_reg(pi, 28737, 6); write_radio_reg(pi, 24640, 7); write_radio_reg(pi, 28736, 7); write_radio_reg(pi, 24637, 136); write_radio_reg(pi, 28733, 136); write_radio_reg(pi, 24639, 0); write_radio_reg(pi, 28735, 0); write_radio_reg(pi, 24649, 0); write_radio_reg(pi, 28745, 0); triso = ((int )pi->radio_chanspec & 61440) == 4096 ? pi->srom_fem5g.triso : pi->srom_fem2g.triso; if ((unsigned int )triso == 7U) { wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, 0); wlc_phy_war_force_trsw_to_R_cliplo_nphy(pi, 1); } else { } wlc_phy_war_txchain_upd_nphy(pi, (int )(pi->sh)->hw_phytxchain); if ((((pi->sh)->boardflags2 & 2U) != 0U && ((int )pi->radio_chanspec & 61440) == 4096) || ((((pi->sh)->boardflags2 & 1024U) != 0U || ((pi->sh)->boardflags2 & 65536U) != 0U) && ((int )pi->radio_chanspec & 61440) == 8192)) { nss1_data_weights = 559240U; ht_data_weights = 559240U; stbc_data_weights = 559240U; } else { nss1_data_weights = 2290649224U; ht_data_weights = 2290649224U; stbc_data_weights = 2290649224U; } wlc_phy_table_write_nphy(pi, 30U, 1U, 1U, 32U, (void const *)(& nss1_data_weights)); wlc_phy_table_write_nphy(pi, 30U, 1U, 2U, 32U, (void const *)(& ht_data_weights)); wlc_phy_table_write_nphy(pi, 30U, 1U, 3U, 32U, (void const *)(& stbc_data_weights)); if (pi->pubpi.phy_rev == 4U) { if (((int )pi->radio_chanspec & 61440) == 4096) { write_radio_reg(pi, 8295, 112); write_radio_reg(pi, 12391, 112); } else { } } else { } if (! pi->edcrs_threshold_lock) { write_phy_reg(pi, 548, 1003); write_phy_reg(pi, 549, 1003); write_phy_reg(pi, 550, 833); write_phy_reg(pi, 551, 833); write_phy_reg(pi, 552, 1067); write_phy_reg(pi, 553, 1067); write_phy_reg(pi, 554, 897); write_phy_reg(pi, 555, 897); write_phy_reg(pi, 556, 1067); write_phy_reg(pi, 557, 1067); write_phy_reg(pi, 558, 897); write_phy_reg(pi, 559, 897); } else { } if (pi->pubpi.phy_rev > 5U) { if (((pi->sh)->boardflags2 & 4096U) != 0U) { wlapi_bmac_mhf((pi->sh)->physhim, 3, 128, 128, 3); } else { } } else { } } else { if (((pi->sh)->boardflags2 & 256U) != 0U || (pi->sh)->boardtype == 139U) { war_dlys[0] = 1U; war_dlys[1] = 6U; war_dlys[2] = 6U; war_dlys[3] = 2U; war_dlys[4] = 4U; war_dlys[5] = 20U; war_dlys[6] = 1U; i = 0U; goto ldv_38061; ldv_38060: rfseq_rx2tx_dlys[i] = war_dlys[i]; i = i + 1U; ldv_38061: ; if (i <= 6U) { goto ldv_38060; } else { } } else { } if (((int )pi->radio_chanspec & 61440) == 4096 && (int )pi->phy_5g_pwrgain) { and_radio_reg(pi, 134, 247); and_radio_reg(pi, 181, 247); } else { or_radio_reg(pi, 134, 8); or_radio_reg(pi, 181, 8); } regval = 10U; wlc_phy_table_write_nphy(pi, 8U, 1U, 0U, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 8U, 1U, 16U, 16U, (void const *)(& regval)); if (pi->pubpi.phy_rev <= 2U) { regval = 52650U; wlc_phy_table_write_nphy(pi, 8U, 1U, 2U, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 8U, 1U, 18U, 16U, (void const *)(& regval)); } else { } if (pi->pubpi.phy_rev <= 1U) { regval = 0U; wlc_phy_table_write_nphy(pi, 8U, 1U, 8U, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 8U, 1U, 24U, 16U, (void const *)(& regval)); regval = 31403U; wlc_phy_table_write_nphy(pi, 8U, 1U, 7U, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 8U, 1U, 23U, 16U, (void const *)(& regval)); regval = 2048U; wlc_phy_table_write_nphy(pi, 8U, 1U, 6U, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 8U, 1U, 22U, 16U, (void const *)(& regval)); } else { } write_phy_reg(pi, 248, 728); write_phy_reg(pi, 249, 769); write_phy_reg(pi, 250, 728); write_phy_reg(pi, 251, 769); wlc_phy_set_rfseq_nphy(pi, 0, (u8 *)(& rfseq_rx2tx_events), (u8 *)(& rfseq_rx2tx_dlys), 7); wlc_phy_set_rfseq_nphy(pi, 1, (u8 *)(& rfseq_tx2rx_events), (u8 *)(& rfseq_tx2rx_dlys), 7); wlc_phy_workarounds_nphy_gainctrl(pi); if (pi->pubpi.phy_rev <= 1U) { tmp = read_phy_reg(pi, 160); if (((int )tmp & 2) != 0) { wlapi_bmac_mhf((pi->sh)->physhim, 2, 16, 16, 3); } else { } } else if (pi->pubpi.phy_rev == 2U) { write_phy_reg(pi, 483, 0); write_phy_reg(pi, 484, 0); } else { } if (pi->pubpi.phy_rev <= 1U) { mod_phy_reg(pi, 144, 128, 0); } else { } alpha0 = 293; alpha1 = 435; alpha2 = 261; beta0 = 366; beta1 = 205; beta2 = 32; write_phy_reg(pi, 325, (int )((u16 )alpha0)); write_phy_reg(pi, 326, (int )((u16 )alpha1)); write_phy_reg(pi, 327, (int )((u16 )alpha2)); write_phy_reg(pi, 328, (int )((u16 )beta0)); write_phy_reg(pi, 329, (int )((u16 )beta1)); write_phy_reg(pi, 330, (int )((u16 )beta2)); if (pi->pubpi.phy_rev <= 2U) { mod_phy_reg(pi, 322, 61440, 0); write_phy_reg(pi, 402, 181); write_phy_reg(pi, 403, 164); write_phy_reg(pi, 404, 0); } else { } if (pi->pubpi.phy_rev == 2U) { mod_phy_reg(pi, 545, 8, 8); } else { } } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static void wlc_phy_extpa_set_tx_digi_filts_nphy(struct brcms_phy *pi ) { int j ; int type ; u16 addr_offset ; { type = 2; addr_offset = 709U; j = 0; goto ldv_38074; ldv_38073: write_phy_reg(pi, (int )((u16 )j) + (int )addr_offset, (int )NPHY_IPA_REV4_txdigi_filtcoeffs[type][j]); j = j + 1; ldv_38074: ; if (j <= 14) { goto ldv_38073; } else { } return; } } static void wlc_phy_clip_det_nphy(struct brcms_phy *pi , u8 write , u16 *vals ) { { if ((unsigned int )write == 0U) { *vals = read_phy_reg(pi, 44); *(vals + 1UL) = read_phy_reg(pi, 66); } else { write_phy_reg(pi, 44, (int )*vals); write_phy_reg(pi, 66, (int )*(vals + 1UL)); } return; } } static void wlc_phy_ipa_internal_tssi_setup_nphy(struct brcms_phy *pi ) { u8 core ; { if (pi->pubpi.phy_rev > 6U) { core = 0U; goto ldv_38086; ldv_38085: ; if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, (unsigned int )core == 0U ? 373 : 405, 5); write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, 14); if ((unsigned int )pi->pubpi.radiorev != 5U) { write_radio_reg(pi, (unsigned int )core == 0U ? 378 : 410, 0); } else { } if (pi->pubpi.phy_rev != 7U) { write_radio_reg(pi, (unsigned int )core == 0U ? 379 : 411, 1); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 379 : 411, 49); } } else { write_radio_reg(pi, (unsigned int )core == 0U ? 373 : 405, 9); write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, 12); write_radio_reg(pi, (unsigned int )core == 0U ? 379 : 411, 0); if ((unsigned int )pi->pubpi.radiorev != 5U) { if (pi->pubpi.phy_rev != 7U) { write_radio_reg(pi, (unsigned int )core == 0U ? 378 : 410, 1); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 378 : 410, 49); } } else { } } write_radio_reg(pi, (unsigned int )core == 0U ? 374 : 406, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 375 : 407, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 376 : 408, 3); write_radio_reg(pi, (unsigned int )core == 0U ? 380 : 412, 0); core = (u8 )((int )core + 1); ldv_38086: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38085; } else { } } else { write_radio_reg(pi, 31, ((int )pi->radio_chanspec & 61440) == 8192 ? 296 : 128); write_radio_reg(pi, 30, 0); write_radio_reg(pi, 32, 41); core = 0U; goto ldv_38089; ldv_38088: write_radio_reg(pi, (unsigned int )core == 0U ? 8233 : 12329, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 8234 : 12330, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 8235 : 12331, 3); write_radio_reg(pi, (unsigned int )core == 0U ? 8236 : 12332, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 8240 : 12336, 8); write_radio_reg(pi, (unsigned int )core == 0U ? 8241 : 12337, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 8242 : 12338, 0); if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, (unsigned int )core == 0U ? 8232 : 12328, 5); if ((unsigned int )pi->pubpi.radiorev != 5U) { write_radio_reg(pi, (unsigned int )core == 0U ? 8238 : 12334, 0); } else { } if (pi->pubpi.phy_rev > 4U) { write_radio_reg(pi, (unsigned int )core == 0U ? 8239 : 12335, 49); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 8239 : 12335, 17); } write_radio_reg(pi, (unsigned int )core == 0U ? 8237 : 12333, 14); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 8232 : 12328, 9); write_radio_reg(pi, (unsigned int )core == 0U ? 8238 : 12334, 49); write_radio_reg(pi, (unsigned int )core == 0U ? 8239 : 12335, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 8237 : 12333, 12); } core = (u8 )((int )core + 1); ldv_38089: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38088; } else { } } return; } } static void wlc_phy_rfctrl_override_nphy(struct brcms_phy *pi , u16 field , u16 value , u8 core_mask , u8 off ) { u8 core_num ; u16 addr ; u16 mask ; u16 en_addr ; u16 val_addr ; u16 en_mask ; u16 val_mask ; u8 shift ; u8 val_shift ; { addr = 0U; mask = 0U; en_addr = 0U; val_addr = 0U; en_mask = 0U; val_mask = 0U; shift = 0U; val_shift = 0U; if (pi->pubpi.phy_rev > 2U && pi->pubpi.phy_rev <= 6U) { en_mask = field; core_num = 0U; goto ldv_38125; ldv_38124: ; switch ((int )field) { case 2: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 1U; val_shift = 0U; goto ldv_38108; case 4: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 2U; val_shift = 1U; goto ldv_38108; case 8: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 4U; val_shift = 2U; goto ldv_38108; case 16: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 16U; val_shift = 4U; goto ldv_38108; case 32: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 32U; val_shift = 5U; goto ldv_38108; case 64: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 64U; val_shift = 6U; goto ldv_38108; case 128: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 128U; val_shift = 7U; goto ldv_38108; case 256: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 1792U; val_shift = 8U; goto ldv_38108; case 2048: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 122U : 125U; val_mask = 57344U; val_shift = 13U; goto ldv_38108; case 512: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 248U : 250U; val_mask = 7U; val_shift = 0U; goto ldv_38108; case 1024: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 248U : 250U; val_mask = 112U; val_shift = 4U; goto ldv_38108; case 4096: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 123U : 126U; val_mask = 65535U; val_shift = 0U; goto ldv_38108; case 8192: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 124U : 127U; val_mask = 65535U; val_shift = 0U; goto ldv_38108; case 16384: en_addr = (unsigned int )core_num == 0U ? 231U : 236U; val_addr = (unsigned int )core_num == 0U ? 249U : 251U; val_mask = 192U; val_shift = 6U; goto ldv_38108; case 1: en_addr = (unsigned int )core_num == 0U ? 229U : 230U; val_addr = (unsigned int )core_num == 0U ? 249U : 251U; val_mask = 32768U; val_shift = 15U; goto ldv_38108; default: addr = 65535U; goto ldv_38108; } ldv_38108: ; if ((unsigned int )off != 0U) { and_phy_reg(pi, (int )en_addr, ~ ((int )en_mask)); and_phy_reg(pi, (int )val_addr, ~ ((int )val_mask)); } else if ((unsigned int )core_mask == 0U || ((int )core_mask >> (int )core_num) & 1) { or_phy_reg(pi, (int )en_addr, (int )en_mask); if ((unsigned int )addr != 65535U) { mod_phy_reg(pi, (int )val_addr, (int )val_mask, (int )((u16 )((int )value << (int )val_shift))); } else { } } else { } core_num = (u8 )((int )core_num + 1); ldv_38125: ; if ((unsigned int )core_num <= 1U) { goto ldv_38124; } else { } } else { if ((unsigned int )off != 0U) { and_phy_reg(pi, 236, ~ ((int )field)); value = 0U; } else { or_phy_reg(pi, 236, (int )field); } core_num = 0U; goto ldv_38160; ldv_38159: ; switch ((int )field) { case 2: ; case 512: ; case 4096: ; case 8192: ; case 16384: addr = 120U; core_mask = 1U; goto ldv_38132; case 4: ; case 8: ; case 16: ; case 32: ; case 64: ; case 128: ; case 256: addr = (unsigned int )core_num == 0U ? 122U : 125U; goto ldv_38132; case 1024: addr = (unsigned int )core_num == 0U ? 123U : 126U; goto ldv_38132; case 2048: addr = (unsigned int )core_num == 0U ? 124U : 127U; goto ldv_38132; default: addr = 65535U; } ldv_38132: ; switch ((int )field) { case 2: mask = 56U; shift = 3U; goto ldv_38144; case 512: mask = 4U; shift = 2U; goto ldv_38144; case 4096: mask = 256U; shift = 8U; goto ldv_38144; case 8192: mask = 512U; shift = 9U; goto ldv_38144; case 16384: mask = 61440U; shift = 12U; goto ldv_38144; case 4: mask = 1U; shift = 0U; goto ldv_38144; case 8: mask = 2U; shift = 1U; goto ldv_38144; case 16: mask = 4U; shift = 2U; goto ldv_38144; case 32: mask = 48U; shift = 4U; goto ldv_38144; case 64: mask = 192U; shift = 6U; goto ldv_38144; case 128: mask = 256U; shift = 8U; goto ldv_38144; case 256: mask = 512U; shift = 9U; goto ldv_38144; case 1024: mask = 8191U; shift = 0U; goto ldv_38144; case 2048: mask = 8191U; shift = 0U; goto ldv_38144; default: mask = 0U; shift = 0U; goto ldv_38144; } ldv_38144: ; if ((unsigned int )addr != 65535U && ((int )core_mask >> (int )core_num) & 1) { mod_phy_reg(pi, (int )addr, (int )mask, (int )((u16 )((int )value << (int )shift))); } else { } core_num = (u8 )((int )core_num + 1); ldv_38160: ; if ((unsigned int )core_num <= 1U) { goto ldv_38159; } else { } or_phy_reg(pi, 236, 1); or_phy_reg(pi, 120, 1); __const_udelay(4295UL); and_phy_reg(pi, 236, 65534); } return; } } static void wlc_phy_txpwrctrl_idle_tssi_nphy(struct brcms_phy *pi ) { s32 rssi_buf[4U] ; s32 int_val ; { if (((pi->measure_hold & 6U) != 0U || (pi->measure_hold & 8U) != 0U) || (pi->measure_hold & 16U) != 0U) { return; } else { } if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { wlc_phy_ipa_internal_tssi_setup_nphy(pi); } else { } if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 4096, 0, 3, 0, 0); } else if (pi->pubpi.phy_rev > 2U) { wlc_phy_rfctrl_override_nphy(pi, 8192, 0, 3, 0); } else { } wlc_phy_stopplayback_nphy(pi); wlc_phy_tx_tone_nphy(pi, 4000U, 0, 0, 0, 0); __const_udelay(85900UL); int_val = wlc_phy_poll_rssi_nphy(pi, 4, (s32 *)(& rssi_buf), 1); wlc_phy_stopplayback_nphy(pi); wlc_phy_rssisel_nphy(pi, 0, 0); if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 4096, 0, 3, 1, 0); } else if (pi->pubpi.phy_rev > 2U) { wlc_phy_rfctrl_override_nphy(pi, 8192, 0, 3, 1); } else { } if (pi->pubpi.phy_rev > 2U) { pi->nphy_pwrctrl_info[0].idle_tssi_2g = (s8 )(int_val >> 24); pi->nphy_pwrctrl_info[0].idle_tssi_5g = (s8 )(int_val >> 24); pi->nphy_pwrctrl_info[1].idle_tssi_2g = (s8 )(int_val >> 8); pi->nphy_pwrctrl_info[1].idle_tssi_5g = (s8 )(int_val >> 8); } else { pi->nphy_pwrctrl_info[0].idle_tssi_2g = (s8 )(int_val >> 24); pi->nphy_pwrctrl_info[1].idle_tssi_2g = (s8 )(int_val >> 8); pi->nphy_pwrctrl_info[0].idle_tssi_5g = (s8 )(int_val >> 16); pi->nphy_pwrctrl_info[1].idle_tssi_5g = (s8 )int_val; } return; } } static void wlc_phy_txpwr_limit_to_tbl_nphy(struct brcms_phy *pi ) { u8 idx ; u8 idx2 ; u8 i ; u8 delta_ind ; u8 tmp ; u8 tmp___0 ; u8 tmp___1 ; u8 tmp___2 ; u8 tmp___3 ; u8 tmp___4 ; u8 tmp___5 ; u8 tmp___6 ; u8 tmp___7 ; u8 tmp___8 ; u8 tmp___9 ; u8 tmp___10 ; u8 tmp___11 ; u8 tmp___12 ; u8 tmp___13 ; u8 tmp___14 ; u8 tmp___15 ; u8 tmp___16 ; u8 tmp___17 ; u8 tmp___18 ; u8 tmp___19 ; u8 tmp___20 ; u8 tmp___21 ; u8 tmp___22 ; u8 tmp___23 ; u8 tmp___24 ; { idx = 0U; goto ldv_38175; ldv_38174: pi->adj_pwr_tbl_nphy[(int )idx] = (u8 )pi->tx_power_offset[(int )idx]; idx = (u8 )((int )idx + 1); ldv_38175: ; if ((unsigned int )idx <= 3U) { goto ldv_38174; } else { } i = 0U; goto ldv_38183; ldv_38182: idx2 = 0U; delta_ind = 0U; switch ((int )i) { case 0: ; if (((int )pi->radio_chanspec & 3072) == 3072 && pi->pubpi.phy_rev > 4U) { idx = 68U; } else { idx = ((int )pi->radio_chanspec & 3072) == 3072 ? 52U : 4U; delta_ind = 1U; } goto ldv_38178; case 1: idx = ((int )pi->radio_chanspec & 3072) == 3072 ? 76U : 28U; goto ldv_38178; case 2: idx = ((int )pi->radio_chanspec & 3072) == 3072 ? 84U : 36U; goto ldv_38178; case 3: idx = ((int )pi->radio_chanspec & 3072) == 3072 ? 92U : 44U; goto ldv_38178; } ldv_38178: tmp = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; idx = (int )idx + (int )delta_ind; tmp___0 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___0 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___1 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___1 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___2 = idx2; idx2 = (u8 )((int )idx2 + 1); tmp___3 = idx; idx = (u8 )((int )idx + 1); pi->adj_pwr_tbl_nphy[((int )tmp___2 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )tmp___3]; tmp___4 = idx2; idx2 = (u8 )((int )idx2 + 1); tmp___5 = idx; idx = (u8 )((int )idx + 1); pi->adj_pwr_tbl_nphy[((int )tmp___4 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )tmp___5]; tmp___6 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___6 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___7 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___7 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___8 = idx2; idx2 = (u8 )((int )idx2 + 1); tmp___9 = idx; idx = (u8 )((int )idx + 1); pi->adj_pwr_tbl_nphy[((int )tmp___8 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )tmp___9]; tmp___10 = idx2; idx2 = (u8 )((int )idx2 + 1); tmp___11 = idx; idx = (u8 )((int )idx + 1); pi->adj_pwr_tbl_nphy[((int )tmp___10 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )tmp___11]; tmp___12 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___12 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___13 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___13 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___14 = idx2; idx2 = (u8 )((int )idx2 + 1); tmp___15 = idx; idx = (u8 )((int )idx + 1); pi->adj_pwr_tbl_nphy[((int )tmp___14 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )tmp___15]; tmp___16 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___16 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___17 = idx2; idx2 = (u8 )((int )idx2 + 1); tmp___18 = idx; idx = (u8 )((int )idx + 1); pi->adj_pwr_tbl_nphy[((int )tmp___17 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )tmp___18]; tmp___19 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___19 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; idx = (unsigned int )((int )idx - (int )delta_ind) + 1U; tmp___20 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___20 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___21 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___21 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___22 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___22 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___23 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___23 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; tmp___24 = idx2; idx2 = (u8 )((int )idx2 + 1); pi->adj_pwr_tbl_nphy[((int )tmp___24 + 1) * 4 + (int )i] = (u8 )pi->tx_power_offset[(int )idx]; i = (u8 )((int )i + 1); ldv_38183: ; if ((unsigned int )i <= 3U) { goto ldv_38182; } else { } return; } } static void wlc_phy_txpwrctrl_pwr_setup_nphy(struct brcms_phy *pi ) { u32 idx ; s16 a1[2U] ; s16 b0[2U] ; s16 b1[2U] ; s8 target_pwr_qtrdbm[2U] ; s32 num ; s32 den ; s32 pwr_est ; u8 chan_freq_range ; u8 idle_tssi[2U] ; u32 tbl_id ; u32 tbl_len ; u32 tbl_offset ; u32 regval[64U] ; u8 core ; s32 _max1 ; int _max2 ; s32 _max1___0 ; int _max2___0 ; { if ((pi->sh)->corerev == 11U || (pi->sh)->corerev == 12U) { wlapi_bmac_mctrl((pi->sh)->physhim, 2097152U, 2097152U); bcma_read32(pi->d11core, 288); __const_udelay(4295UL); } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } or_phy_reg(pi, 290, 1); if (pi->pubpi.phy_rev > 2U) { and_phy_reg(pi, 487, 32767); } else { or_phy_reg(pi, 487, 32768); } if ((pi->sh)->corerev == 11U || (pi->sh)->corerev == 12U) { wlapi_bmac_mctrl((pi->sh)->physhim, 2097152U, 0U); } else { } if ((pi->sh)->sromrev <= 3U) { idle_tssi[0] = (u8 )pi->nphy_pwrctrl_info[0].idle_tssi_2g; idle_tssi[1] = (u8 )pi->nphy_pwrctrl_info[1].idle_tssi_2g; a1[0] = -424; a1[1] = -424; b0[0] = 5612; b0[1] = 5612; b1[1] = -1393; b1[0] = -1393; } else { chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0U); switch ((int )chan_freq_range) { case 0: idle_tssi[0] = (u8 )pi->nphy_pwrctrl_info[0].idle_tssi_2g; idle_tssi[1] = (u8 )pi->nphy_pwrctrl_info[1].idle_tssi_2g; a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_a1; a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_a1; b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b0; b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b0; b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_2g_b1; b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_2g_b1; goto ldv_38204; case 1: idle_tssi[0] = (u8 )pi->nphy_pwrctrl_info[0].idle_tssi_5g; idle_tssi[1] = (u8 )pi->nphy_pwrctrl_info[1].idle_tssi_5g; a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_a1; a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_a1; b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b0; b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b0; b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gl_b1; b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gl_b1; goto ldv_38204; case 2: idle_tssi[0] = (u8 )pi->nphy_pwrctrl_info[0].idle_tssi_5g; idle_tssi[1] = (u8 )pi->nphy_pwrctrl_info[1].idle_tssi_5g; a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_a1; a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_a1; b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b0; b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b0; b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gm_b1; b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gm_b1; goto ldv_38204; case 3: idle_tssi[0] = (u8 )pi->nphy_pwrctrl_info[0].idle_tssi_5g; idle_tssi[1] = (u8 )pi->nphy_pwrctrl_info[1].idle_tssi_5g; a1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_a1; a1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_a1; b0[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b0; b0[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b0; b1[0] = pi->nphy_pwrctrl_info[0].pwrdet_5gh_b1; b1[1] = pi->nphy_pwrctrl_info[1].pwrdet_5gh_b1; goto ldv_38204; default: idle_tssi[0] = (u8 )pi->nphy_pwrctrl_info[0].idle_tssi_2g; idle_tssi[1] = (u8 )pi->nphy_pwrctrl_info[1].idle_tssi_2g; a1[0] = -424; a1[1] = -424; b0[0] = 5612; b0[1] = 5612; b1[1] = -1393; b1[0] = -1393; goto ldv_38204; } ldv_38204: ; } target_pwr_qtrdbm[0] = (signed char )pi->tx_power_max; target_pwr_qtrdbm[1] = (signed char )pi->tx_power_max; if (pi->pubpi.phy_rev > 2U) { if ((unsigned int )pi->srom_fem2g.tssipos != 0U) { or_phy_reg(pi, 489, 16384); } else { } if (pi->pubpi.phy_rev > 6U) { core = 0U; goto ldv_38210; ldv_38209: ; if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, 14); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, 12); } } else { } core = (u8 )((int )core + 1); ldv_38210: ; if ((unsigned int )core <= 1U) { goto ldv_38209; } else { } } else if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { write_radio_reg(pi, 8237, ((int )pi->radio_chanspec & 61440) == 4096 ? 12 : 14); write_radio_reg(pi, 12333, ((int )pi->radio_chanspec & 61440) == 4096 ? 12 : 14); } else { write_radio_reg(pi, 8237, 17); write_radio_reg(pi, 12333, 17); } } else { } if ((pi->sh)->corerev == 11U || (pi->sh)->corerev == 12U) { wlapi_bmac_mctrl((pi->sh)->physhim, 2097152U, 2097152U); bcma_read32(pi->d11core, 288); __const_udelay(4295UL); } else { } if (pi->pubpi.phy_rev > 6U) { mod_phy_reg(pi, 487, 127, 25); } else { mod_phy_reg(pi, 487, 127, 64); } if (pi->pubpi.phy_rev > 6U) { mod_phy_reg(pi, 546, 255, 25); } else if (pi->pubpi.phy_rev > 1U) { mod_phy_reg(pi, 546, 255, 64); } else { } if ((pi->sh)->corerev == 11U || (pi->sh)->corerev == 12U) { wlapi_bmac_mctrl((pi->sh)->physhim, 2097152U, 0U); } else { } write_phy_reg(pi, 488, 1008); write_phy_reg(pi, 489, (int )((u16 )(((int )((short )idle_tssi[0]) | -32768) | (int )((short )((int )idle_tssi[1] << 8))))); write_phy_reg(pi, 490, (int )((u16 )((int )((short )target_pwr_qtrdbm[0]) | (int )((short )((int )target_pwr_qtrdbm[1] << 8))))); tbl_len = 64U; tbl_offset = 0U; tbl_id = 26U; goto ldv_38222; ldv_38221: idx = 0U; goto ldv_38219; ldv_38218: num = (s32 )(((u32 )((int )b0[tbl_id - 26U] * 16) + (u32 )b1[tbl_id - 26U] * idx) * 8U); den = (s32 )((u32 )a1[tbl_id - 26U] * idx + 32768U); _max1 = (num * 4 + den / 2) / den; _max2 = -8; pwr_est = _max1 > _max2 ? _max1 : _max2; if (pi->pubpi.phy_rev <= 2U) { if ((u32 )(32 - (int )idle_tssi[tbl_id - 26U]) >= idx) { _max1___0 = pwr_est; _max2___0 = (int )target_pwr_qtrdbm[tbl_id - 26U] + 1; pwr_est = _max1___0 > _max2___0 ? _max1___0 : _max2___0; } else { } } else { } regval[idx] = (unsigned int )pwr_est; idx = idx + 1U; ldv_38219: ; if (idx < tbl_len) { goto ldv_38218; } else { } wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32U, (void const *)(& regval)); tbl_id = tbl_id + 1U; ldv_38222: ; if (tbl_id <= 27U) { goto ldv_38221; } else { } wlc_phy_txpwr_limit_to_tbl_nphy(pi); wlc_phy_table_write_nphy(pi, 26U, 84U, 64U, 8U, (void const *)(& pi->adj_pwr_tbl_nphy)); wlc_phy_table_write_nphy(pi, 27U, 84U, 64U, 8U, (void const *)(& pi->adj_pwr_tbl_nphy)); if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static u32 *wlc_phy_get_ipa_gaintbl_nphy(struct brcms_phy *pi ) { u32 *tx_pwrctrl_tbl ; { tx_pwrctrl_tbl = (u32 *)0U; if (((int )pi->radio_chanspec & 61440) == 8192) { if (pi->pubpi.phy_rev > 6U) { if ((unsigned int )pi->pubpi.radiorev == 4U || (unsigned int )pi->pubpi.radiorev == 6U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_2g_2057rev4n6); } else if ((unsigned int )pi->pubpi.radiorev == 3U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_2g_2057rev3); } else if ((unsigned int )pi->pubpi.radiorev == 5U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_2g_2057rev5); } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_2g_2057rev7); } else { } } else if (pi->pubpi.phy_rev == 6U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_rev6); if ((pi->sh)->chip == 47162U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_rev5); } else { } } else if (pi->pubpi.phy_rev == 5U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_rev5); } else { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa); } } else if (pi->pubpi.phy_rev > 6U) { if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_5g_2057); } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_5g_2057rev7); } else { } } else { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_ipa_5g); } return (tx_pwrctrl_tbl); } } static void wlc_phy_restore_rssical_nphy(struct brcms_phy *pi ) { { if (((int )pi->radio_chanspec & 61440) == 8192) { if ((unsigned int )pi->nphy_rssical_chanspec_2G == 0U) { return; } else { } if (pi->pubpi.phy_rev > 6U) { mod_radio_reg(pi, 180, 7, (int )pi->rssical_cache.rssical_radio_regs_2G[0]); mod_radio_reg(pi, 313, 7, (int )pi->rssical_cache.rssical_radio_regs_2G[1]); } else { mod_radio_reg(pi, 24619, 28, (int )pi->rssical_cache.rssical_radio_regs_2G[0]); mod_radio_reg(pi, 28715, 28, (int )pi->rssical_cache.rssical_radio_regs_2G[1]); } write_phy_reg(pi, 422, (int )pi->rssical_cache.rssical_phyregs_2G[0]); write_phy_reg(pi, 428, (int )pi->rssical_cache.rssical_phyregs_2G[1]); write_phy_reg(pi, 434, (int )pi->rssical_cache.rssical_phyregs_2G[2]); write_phy_reg(pi, 440, (int )pi->rssical_cache.rssical_phyregs_2G[3]); write_phy_reg(pi, 420, (int )pi->rssical_cache.rssical_phyregs_2G[4]); write_phy_reg(pi, 426, (int )pi->rssical_cache.rssical_phyregs_2G[5]); write_phy_reg(pi, 432, (int )pi->rssical_cache.rssical_phyregs_2G[6]); write_phy_reg(pi, 438, (int )pi->rssical_cache.rssical_phyregs_2G[7]); write_phy_reg(pi, 421, (int )pi->rssical_cache.rssical_phyregs_2G[8]); write_phy_reg(pi, 427, (int )pi->rssical_cache.rssical_phyregs_2G[9]); write_phy_reg(pi, 433, (int )pi->rssical_cache.rssical_phyregs_2G[10]); write_phy_reg(pi, 439, (int )pi->rssical_cache.rssical_phyregs_2G[11]); } else { if ((unsigned int )pi->nphy_rssical_chanspec_5G == 0U) { return; } else { } if (pi->pubpi.phy_rev > 6U) { mod_radio_reg(pi, 180, 7, (int )pi->rssical_cache.rssical_radio_regs_5G[0]); mod_radio_reg(pi, 313, 7, (int )pi->rssical_cache.rssical_radio_regs_5G[1]); } else { mod_radio_reg(pi, 24619, 28, (int )pi->rssical_cache.rssical_radio_regs_5G[0]); mod_radio_reg(pi, 28715, 28, (int )pi->rssical_cache.rssical_radio_regs_5G[1]); } write_phy_reg(pi, 422, (int )pi->rssical_cache.rssical_phyregs_5G[0]); write_phy_reg(pi, 428, (int )pi->rssical_cache.rssical_phyregs_5G[1]); write_phy_reg(pi, 434, (int )pi->rssical_cache.rssical_phyregs_5G[2]); write_phy_reg(pi, 440, (int )pi->rssical_cache.rssical_phyregs_5G[3]); write_phy_reg(pi, 420, (int )pi->rssical_cache.rssical_phyregs_5G[4]); write_phy_reg(pi, 426, (int )pi->rssical_cache.rssical_phyregs_5G[5]); write_phy_reg(pi, 432, (int )pi->rssical_cache.rssical_phyregs_5G[6]); write_phy_reg(pi, 438, (int )pi->rssical_cache.rssical_phyregs_5G[7]); write_phy_reg(pi, 421, (int )pi->rssical_cache.rssical_phyregs_5G[8]); write_phy_reg(pi, 427, (int )pi->rssical_cache.rssical_phyregs_5G[9]); write_phy_reg(pi, 433, (int )pi->rssical_cache.rssical_phyregs_5G[10]); write_phy_reg(pi, 439, (int )pi->rssical_cache.rssical_phyregs_5G[11]); } return; } } static void wlc_phy_internal_cal_txgain_nphy(struct brcms_phy *pi ) { u16 txcal_gain[2U] ; { pi->nphy_txcal_pwr_idx[0] = pi->nphy_cal_orig_pwr_idx[0]; pi->nphy_txcal_pwr_idx[1] = pi->nphy_cal_orig_pwr_idx[0]; wlc_phy_txpwr_index_nphy(pi, 1, (int )((s8 )pi->nphy_cal_orig_pwr_idx[0]), 1); wlc_phy_txpwr_index_nphy(pi, 2, (int )((s8 )pi->nphy_cal_orig_pwr_idx[1]), 1); wlc_phy_table_read_nphy(pi, 7U, 2U, 272U, 16U, (void *)(& txcal_gain)); if (((int )pi->radio_chanspec & 61440) == 8192) { txcal_gain[0] = (u16 )(((int )((short )txcal_gain[0]) & -4096) | 3904); txcal_gain[1] = (u16 )(((int )((short )txcal_gain[1]) & -4096) | 3904); } else { txcal_gain[0] = (u16 )(((int )((short )txcal_gain[0]) & -4096) | 3936); txcal_gain[1] = (u16 )(((int )((short )txcal_gain[1]) & -4096) | 3936); } wlc_phy_table_write_nphy(pi, 7U, 2U, 272U, 16U, (void const *)(& txcal_gain)); return; } } static void wlc_phy_precal_txgain_nphy(struct brcms_phy *pi ) { bool save_bbmult ; u8 txcal_index_2057_rev5n7 ; u8 txcal_index_2057_rev3n4n6 ; { save_bbmult = 0; txcal_index_2057_rev5n7 = 0U; txcal_index_2057_rev3n4n6 = 10U; if ((int )pi->use_int_tx_iqlo_cal_nphy) { if (pi->pubpi.phy_rev > 6U) { if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { pi->nphy_txcal_pwr_idx[0] = txcal_index_2057_rev3n4n6; pi->nphy_txcal_pwr_idx[1] = txcal_index_2057_rev3n4n6; wlc_phy_txpwr_index_nphy(pi, 3, (int )((s8 )txcal_index_2057_rev3n4n6), 0); } else { pi->nphy_txcal_pwr_idx[0] = txcal_index_2057_rev5n7; pi->nphy_txcal_pwr_idx[1] = txcal_index_2057_rev5n7; wlc_phy_txpwr_index_nphy(pi, 3, (int )((s8 )txcal_index_2057_rev5n7), 0); } save_bbmult = 1; } else if (pi->pubpi.phy_rev <= 4U) { wlc_phy_cal_txgainctrl_nphy(pi, 11, 0); if ((unsigned int )(pi->sh)->hw_phytxchain != 3U) { pi->nphy_txcal_pwr_idx[1] = pi->nphy_txcal_pwr_idx[0]; wlc_phy_txpwr_index_nphy(pi, 3, (int )((s8 )pi->nphy_txcal_pwr_idx[0]), 1); save_bbmult = 1; } else { } } else if (pi->pubpi.phy_rev == 5U) { if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if (((int )pi->radio_chanspec & 61440) == 8192) { wlc_phy_cal_txgainctrl_nphy(pi, 12, 0); } else { pi->nphy_txcal_pwr_idx[0] = 80U; pi->nphy_txcal_pwr_idx[1] = 80U; wlc_phy_txpwr_index_nphy(pi, 3, 80, 0); save_bbmult = 1; } } else { wlc_phy_internal_cal_txgain_nphy(pi); save_bbmult = 1; } } else if (pi->pubpi.phy_rev == 6U) { if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if (((int )pi->radio_chanspec & 61440) == 8192) { wlc_phy_cal_txgainctrl_nphy(pi, 12, 0); } else { wlc_phy_cal_txgainctrl_nphy(pi, 14, 0); } } else { wlc_phy_internal_cal_txgain_nphy(pi); save_bbmult = 1; } } else { } } else { wlc_phy_cal_txgainctrl_nphy(pi, 10, 0); } if ((int )save_bbmult) { wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& pi->nphy_txcal_bbmult)); } else { } return; } } static void wlc_phy_rfctrlintc_override_nphy(struct brcms_phy *pi , u8 field , u16 value , u8 core_code ) { u16 mask ; u16 val ; u8 core ; uint countdown ; u16 tmp ; int __ret_warn_on ; u16 tmp___0 ; long tmp___1 ; long tmp___2 ; { if (pi->pubpi.phy_rev > 2U) { core = 0U; goto ldv_38258; ldv_38257: ; if ((unsigned int )core_code == 1U && (unsigned int )core == 1U) { goto ldv_38250; } else if ((unsigned int )core_code == 2U && (unsigned int )core == 0U) { goto ldv_38250; } else { } if (pi->pubpi.phy_rev <= 6U) { mask = 1024U; val = 1024U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); } else { } if ((unsigned int )field == 0U) { write_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, 0); wlc_phy_force_rfseq_nphy(pi, 2); } else if ((unsigned int )field == 1U) { if (pi->pubpi.phy_rev > 6U) { mask = 192U; val = (int )value << 6U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); or_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, 1024); and_phy_reg(pi, 767, 16383); or_phy_reg(pi, 767, 8192); or_phy_reg(pi, 767, 1); } else { mask = 960U; val = (int )value << 6U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); mask = 1U; val = 1U; mod_phy_reg(pi, (unsigned int )core == 0U ? 231 : 236, (int )mask, (int )val); mask = (unsigned int )core == 0U ? 1U : 2U; val = (unsigned int )core != 0U ? 2U : 1U; mod_phy_reg(pi, 120, (int )mask, (int )val); countdown = 10009U; goto ldv_38253; ldv_38252: __const_udelay(42950UL); countdown = countdown - 10U; ldv_38253: tmp = read_phy_reg(pi, 120); if ((unsigned int )((int )tmp & (int )val) != 0U && countdown > 9U) { goto ldv_38252; } else { } tmp___0 = read_phy_reg(pi, 120); __ret_warn_on = (unsigned int )((int )tmp___0 & (int )val) != 0U; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c", 18217, "HW error: override failed"); } else { } tmp___2 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___2 != 0L) { return; } else { } mask = 1U; val = 0U; mod_phy_reg(pi, (unsigned int )core == 0U ? 231 : 236, (int )mask, (int )val); } } else if ((unsigned int )field == 2U) { if (pi->pubpi.phy_rev > 6U) { mask = 48U; if (((int )pi->radio_chanspec & 61440) == 4096) { val = (int )value << 5U; } else { val = (int )value << 4U; } mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); or_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, 4096); } else { if (((int )pi->radio_chanspec & 61440) == 4096) { mask = 32U; val = (int )value << 5U; } else { mask = 16U; val = (int )value << 4U; } mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); } } else if ((unsigned int )field == 3U) { if (pi->pubpi.phy_rev > 6U) { if (((int )pi->radio_chanspec & 61440) == 4096) { mask = 1U; val = value; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); mask = 4U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, 0); } else { mask = 4U; val = (int )value << 2U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); mask = 1U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, 0); } mask = 2048U; val = 2048U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); } else { if (((int )pi->radio_chanspec & 61440) == 4096) { mask = 1U; val = value; } else { mask = 4U; val = (int )value << 2U; } mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); } } else if ((unsigned int )field == 4U) { if (pi->pubpi.phy_rev > 6U) { if (((int )pi->radio_chanspec & 61440) == 4096) { mask = 2U; val = (int )value << 1U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); mask = 8U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, 0); } else { mask = 8U; val = (int )value << 3U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); mask = 2U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, 0); } mask = 2048U; val = 2048U; mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); } else { if (((int )pi->radio_chanspec & 61440) == 4096) { mask = 2U; val = (int )value << 1U; } else { mask = 8U; val = (int )value << 3U; } mod_phy_reg(pi, (unsigned int )core == 0U ? 145 : 146, (int )mask, (int )val); } } else { } ldv_38250: core = (u8 )((int )core + 1); ldv_38258: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38257; } else { } } else { } return; } } void wlc_phy_cal_txgainctrl_nphy(struct brcms_phy *pi , s32 dBm_targetpower , bool debug ) { int gainctrl_loopidx ; uint core ; u16 m0m1 ; u16 curr_m0m1 ; s32 delta_power ; s32 txpwrindex ; s32 qdBm_power[2U] ; u16 orig_BBConfig ; u16 phy_saveregs[4U] ; u32 freq_test ; u16 ampl_test ; uint stepsize ; bool phyhang_avoid_state ; u16 radio_gain ; u16 dbg_m0m1 ; unsigned long __ms ; unsigned long tmp ; { ampl_test = 250U; phyhang_avoid_state = 0; if (pi->pubpi.phy_rev > 6U) { stepsize = 2U; } else { stepsize = 1U; } if (((int )pi->radio_chanspec & 3072) == 3072) { freq_test = 5000U; } else { freq_test = 2500U; } wlc_phy_txpwr_index_nphy(pi, 1, (int )((s8 )pi->nphy_cal_orig_pwr_idx[0]), 1); wlc_phy_txpwr_index_nphy(pi, 2, (int )((s8 )pi->nphy_cal_orig_pwr_idx[1]), 1); if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } phyhang_avoid_state = pi->phyhang_avoid; pi->phyhang_avoid = 0; phy_saveregs[0] = read_phy_reg(pi, 145); phy_saveregs[1] = read_phy_reg(pi, 146); phy_saveregs[2] = read_phy_reg(pi, 231); phy_saveregs[3] = read_phy_reg(pi, 236); wlc_phy_rfctrlintc_override_nphy(pi, 2, 1, 3); if (! debug) { wlc_phy_rfctrlintc_override_nphy(pi, 1, 2, 1); wlc_phy_rfctrlintc_override_nphy(pi, 1, 8, 2); } else { wlc_phy_rfctrlintc_override_nphy(pi, 1, 1, 1); wlc_phy_rfctrlintc_override_nphy(pi, 1, 7, 2); } orig_BBConfig = read_phy_reg(pi, 1); mod_phy_reg(pi, 1, 32768, 0); wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& m0m1)); core = 0U; goto ldv_38288; ldv_38287: txpwrindex = (int )pi->nphy_cal_orig_pwr_idx[core]; gainctrl_loopidx = 0; goto ldv_38279; ldv_38278: wlc_phy_tx_tone_nphy(pi, freq_test, (int )ampl_test, 0, 0, 0); if (core == 0U) { curr_m0m1 = (unsigned int )m0m1 & 65280U; } else { curr_m0m1 = (unsigned int )m0m1 & 255U; } wlc_phy_table_write_nphy(pi, 15U, 1U, 87U, 16U, (void const *)(& curr_m0m1)); wlc_phy_table_write_nphy(pi, 15U, 1U, 95U, 16U, (void const *)(& curr_m0m1)); __const_udelay(214750UL); wlc_phy_est_tonepwr_nphy(pi, (s32 *)(& qdBm_power), 64); pi->nphy_bb_mult_save = 0U; wlc_phy_stopplayback_nphy(pi); delta_power = dBm_targetpower * 4 - qdBm_power[core]; txpwrindex = (s32 )((uint )txpwrindex - stepsize * (uint )delta_power); if (txpwrindex < 0) { txpwrindex = 0; } else if (txpwrindex > 127) { txpwrindex = 127; } else { } if (((int )pi->radio_chanspec & 61440) == 4096) { if (pi->pubpi.phy_rev == 4U && (unsigned int )pi->srom_fem5g.extpagain == 3U) { if (txpwrindex <= 29) { txpwrindex = 30; } else { } } else { } } else if (pi->pubpi.phy_rev > 4U && (unsigned int )pi->srom_fem2g.extpagain == 3U) { if (txpwrindex <= 49) { txpwrindex = 50; } else { } } else { } wlc_phy_txpwr_index_nphy(pi, (int )((u8 )(1 << (int )core)), (int )((s8 )txpwrindex), 1); gainctrl_loopidx = gainctrl_loopidx + 1; ldv_38279: ; if (gainctrl_loopidx <= 1) { goto ldv_38278; } else { } pi->nphy_txcal_pwr_idx[core] = (unsigned char )txpwrindex; if ((int )debug) { wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& dbg_m0m1)); wlc_phy_tx_tone_nphy(pi, freq_test, (int )ampl_test, 0, 0, 0); wlc_phy_table_write_nphy(pi, 15U, 1U, 87U, 16U, (void const *)(& dbg_m0m1)); wlc_phy_table_write_nphy(pi, 15U, 1U, 95U, 16U, (void const *)(& dbg_m0m1)); __const_udelay(429500UL); wlc_phy_est_tonepwr_nphy(pi, (s32 *)(& qdBm_power), 64); wlc_phy_table_read_nphy(pi, 7U, 1U, core + 272U, 16U, (void *)(& radio_gain)); __ms = 4000UL; goto ldv_38285; ldv_38284: __const_udelay(4295000UL); ldv_38285: tmp = __ms; __ms = __ms - 1UL; if (tmp != 0UL) { goto ldv_38284; } else { } pi->nphy_bb_mult_save = 0U; wlc_phy_stopplayback_nphy(pi); } else { } core = core + 1U; ldv_38288: ; if ((uint )pi->pubpi.phy_corenum > core) { goto ldv_38287; } else { } wlc_phy_txpwr_index_nphy(pi, 1, (int )((s8 )pi->nphy_txcal_pwr_idx[0]), 1); wlc_phy_txpwr_index_nphy(pi, 2, (int )((s8 )pi->nphy_txcal_pwr_idx[1]), 1); wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& pi->nphy_txcal_bbmult)); write_phy_reg(pi, 1, (int )orig_BBConfig); write_phy_reg(pi, 145, (int )phy_saveregs[0]); write_phy_reg(pi, 146, (int )phy_saveregs[1]); write_phy_reg(pi, 231, (int )phy_saveregs[2]); write_phy_reg(pi, 236, (int )phy_saveregs[3]); pi->phyhang_avoid = phyhang_avoid_state; if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static void wlc_phy_savecal_nphy(struct brcms_phy *pi ) { void *tbl_ptr ; int coreNum ; u16 *txcal_radio_regs ; { txcal_radio_regs = (u16 *)0U; if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } if (((int )pi->radio_chanspec & 61440) == 8192) { wlc_phy_rx_iq_coeffs_nphy(pi, 0, & pi->calibration_cache.rxcal_coeffs_2G); if (pi->pubpi.phy_rev > 6U) { txcal_radio_regs = (u16 *)(& pi->calibration_cache.txcal_radio_regs_2G); } else if (pi->pubpi.phy_rev > 2U) { pi->calibration_cache.txcal_radio_regs_2G[0] = read_radio_reg(pi, 8225); pi->calibration_cache.txcal_radio_regs_2G[1] = read_radio_reg(pi, 8226); pi->calibration_cache.txcal_radio_regs_2G[2] = read_radio_reg(pi, 12321); pi->calibration_cache.txcal_radio_regs_2G[3] = read_radio_reg(pi, 12322); pi->calibration_cache.txcal_radio_regs_2G[4] = read_radio_reg(pi, 8227); pi->calibration_cache.txcal_radio_regs_2G[5] = read_radio_reg(pi, 8228); pi->calibration_cache.txcal_radio_regs_2G[6] = read_radio_reg(pi, 12323); pi->calibration_cache.txcal_radio_regs_2G[7] = read_radio_reg(pi, 12324); } else { pi->calibration_cache.txcal_radio_regs_2G[0] = read_radio_reg(pi, 139); pi->calibration_cache.txcal_radio_regs_2G[1] = read_radio_reg(pi, 186); pi->calibration_cache.txcal_radio_regs_2G[2] = read_radio_reg(pi, 141); pi->calibration_cache.txcal_radio_regs_2G[3] = read_radio_reg(pi, 188); } pi->nphy_iqcal_chanspec_2G = pi->radio_chanspec; tbl_ptr = (void *)(& pi->calibration_cache.txcal_coeffs_2G); } else { wlc_phy_rx_iq_coeffs_nphy(pi, 0, & pi->calibration_cache.rxcal_coeffs_5G); if (pi->pubpi.phy_rev > 6U) { txcal_radio_regs = (u16 *)(& pi->calibration_cache.txcal_radio_regs_5G); } else if (pi->pubpi.phy_rev > 2U) { pi->calibration_cache.txcal_radio_regs_5G[0] = read_radio_reg(pi, 8225); pi->calibration_cache.txcal_radio_regs_5G[1] = read_radio_reg(pi, 8226); pi->calibration_cache.txcal_radio_regs_5G[2] = read_radio_reg(pi, 12321); pi->calibration_cache.txcal_radio_regs_5G[3] = read_radio_reg(pi, 12322); pi->calibration_cache.txcal_radio_regs_5G[4] = read_radio_reg(pi, 8227); pi->calibration_cache.txcal_radio_regs_5G[5] = read_radio_reg(pi, 8228); pi->calibration_cache.txcal_radio_regs_5G[6] = read_radio_reg(pi, 12323); pi->calibration_cache.txcal_radio_regs_5G[7] = read_radio_reg(pi, 12324); } else { pi->calibration_cache.txcal_radio_regs_5G[0] = read_radio_reg(pi, 139); pi->calibration_cache.txcal_radio_regs_5G[1] = read_radio_reg(pi, 186); pi->calibration_cache.txcal_radio_regs_5G[2] = read_radio_reg(pi, 141); pi->calibration_cache.txcal_radio_regs_5G[3] = read_radio_reg(pi, 188); } pi->nphy_iqcal_chanspec_5G = pi->radio_chanspec; tbl_ptr = (void *)(& pi->calibration_cache.txcal_coeffs_5G); } if (pi->pubpi.phy_rev > 6U) { coreNum = 0; goto ldv_38297; ldv_38296: *(txcal_radio_regs + (unsigned long )(coreNum * 2)) = read_radio_reg(pi, coreNum == 0 ? 369 : 401); *(txcal_radio_regs + ((unsigned long )(coreNum * 2) + 1UL)) = read_radio_reg(pi, coreNum == 0 ? 370 : 402); *(txcal_radio_regs + ((unsigned long )(coreNum * 2) + 4UL)) = read_radio_reg(pi, coreNum == 0 ? 371 : 403); *(txcal_radio_regs + ((unsigned long )(coreNum * 2) + 5UL)) = read_radio_reg(pi, coreNum == 0 ? 372 : 404); coreNum = coreNum + 1; ldv_38297: ; if (coreNum <= 1) { goto ldv_38296; } else { } } else { } wlc_phy_table_read_nphy(pi, 15U, 8U, 80U, 16U, tbl_ptr); if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static void wlc_phy_tx_iq_war_nphy(struct brcms_phy *pi ) { struct nphy_iq_comp tx_comp ; { wlc_phy_table_read_nphy(pi, 15U, 4U, 80U, 16U, (void *)(& tx_comp)); wlapi_bmac_write_shm((pi->sh)->physhim, 1792U, (int )((u16 )tx_comp.a0)); wlapi_bmac_write_shm((pi->sh)->physhim, 1794U, (int )((u16 )tx_comp.b0)); wlapi_bmac_write_shm((pi->sh)->physhim, 1796U, (int )((u16 )tx_comp.a1)); wlapi_bmac_write_shm((pi->sh)->physhim, 1798U, (int )((u16 )tx_comp.b1)); return; } } static void wlc_phy_restorecal_nphy(struct brcms_phy *pi ) { u16 *loft_comp ; u16 txcal_coeffs_bphy[4U] ; u16 *tbl_ptr ; int coreNum ; u16 *txcal_radio_regs ; { txcal_radio_regs = (u16 *)0U; if (((int )pi->radio_chanspec & 61440) == 8192) { if ((unsigned int )pi->nphy_iqcal_chanspec_2G == 0U) { return; } else { } tbl_ptr = (u16 *)(& pi->calibration_cache.txcal_coeffs_2G); loft_comp = (u16 *)(& pi->calibration_cache.txcal_coeffs_2G) + 5UL; } else { if ((unsigned int )pi->nphy_iqcal_chanspec_5G == 0U) { return; } else { } tbl_ptr = (u16 *)(& pi->calibration_cache.txcal_coeffs_5G); loft_comp = (u16 *)(& pi->calibration_cache.txcal_coeffs_5G) + 5UL; } wlc_phy_table_write_nphy(pi, 15U, 4U, 80U, 16U, (void const *)tbl_ptr); if (pi->pubpi.phy_rev > 2U) { txcal_coeffs_bphy[0] = *tbl_ptr; txcal_coeffs_bphy[1] = *(tbl_ptr + 1UL); txcal_coeffs_bphy[2] = *(tbl_ptr + 2UL); txcal_coeffs_bphy[3] = *(tbl_ptr + 3UL); } else { txcal_coeffs_bphy[0] = 0U; txcal_coeffs_bphy[1] = 0U; txcal_coeffs_bphy[2] = 0U; txcal_coeffs_bphy[3] = 0U; } wlc_phy_table_write_nphy(pi, 15U, 4U, 88U, 16U, (void const *)(& txcal_coeffs_bphy)); wlc_phy_table_write_nphy(pi, 15U, 2U, 85U, 16U, (void const *)loft_comp); wlc_phy_table_write_nphy(pi, 15U, 2U, 93U, 16U, (void const *)loft_comp); if (pi->pubpi.phy_rev <= 1U) { wlc_phy_tx_iq_war_nphy(pi); } else { } if (((int )pi->radio_chanspec & 61440) == 8192) { if (pi->pubpi.phy_rev > 6U) { txcal_radio_regs = (u16 *)(& pi->calibration_cache.txcal_radio_regs_2G); } else if (pi->pubpi.phy_rev > 2U) { write_radio_reg(pi, 8225, (int )pi->calibration_cache.txcal_radio_regs_2G[0]); write_radio_reg(pi, 8226, (int )pi->calibration_cache.txcal_radio_regs_2G[1]); write_radio_reg(pi, 12321, (int )pi->calibration_cache.txcal_radio_regs_2G[2]); write_radio_reg(pi, 12322, (int )pi->calibration_cache.txcal_radio_regs_2G[3]); write_radio_reg(pi, 8227, (int )pi->calibration_cache.txcal_radio_regs_2G[4]); write_radio_reg(pi, 8228, (int )pi->calibration_cache.txcal_radio_regs_2G[5]); write_radio_reg(pi, 12323, (int )pi->calibration_cache.txcal_radio_regs_2G[6]); write_radio_reg(pi, 12324, (int )pi->calibration_cache.txcal_radio_regs_2G[7]); } else { write_radio_reg(pi, 139, (int )pi->calibration_cache.txcal_radio_regs_2G[0]); write_radio_reg(pi, 186, (int )pi->calibration_cache.txcal_radio_regs_2G[1]); write_radio_reg(pi, 141, (int )pi->calibration_cache.txcal_radio_regs_2G[2]); write_radio_reg(pi, 188, (int )pi->calibration_cache.txcal_radio_regs_2G[3]); } wlc_phy_rx_iq_coeffs_nphy(pi, 1, & pi->calibration_cache.rxcal_coeffs_2G); } else { if (pi->pubpi.phy_rev > 6U) { txcal_radio_regs = (u16 *)(& pi->calibration_cache.txcal_radio_regs_5G); } else if (pi->pubpi.phy_rev > 2U) { write_radio_reg(pi, 8225, (int )pi->calibration_cache.txcal_radio_regs_5G[0]); write_radio_reg(pi, 8226, (int )pi->calibration_cache.txcal_radio_regs_5G[1]); write_radio_reg(pi, 12321, (int )pi->calibration_cache.txcal_radio_regs_5G[2]); write_radio_reg(pi, 12322, (int )pi->calibration_cache.txcal_radio_regs_5G[3]); write_radio_reg(pi, 8227, (int )pi->calibration_cache.txcal_radio_regs_5G[4]); write_radio_reg(pi, 8228, (int )pi->calibration_cache.txcal_radio_regs_5G[5]); write_radio_reg(pi, 12323, (int )pi->calibration_cache.txcal_radio_regs_5G[6]); write_radio_reg(pi, 12324, (int )pi->calibration_cache.txcal_radio_regs_5G[7]); } else { write_radio_reg(pi, 139, (int )pi->calibration_cache.txcal_radio_regs_5G[0]); write_radio_reg(pi, 186, (int )pi->calibration_cache.txcal_radio_regs_5G[1]); write_radio_reg(pi, 141, (int )pi->calibration_cache.txcal_radio_regs_5G[2]); write_radio_reg(pi, 188, (int )pi->calibration_cache.txcal_radio_regs_5G[3]); } wlc_phy_rx_iq_coeffs_nphy(pi, 1, & pi->calibration_cache.rxcal_coeffs_5G); } if (pi->pubpi.phy_rev > 6U) { coreNum = 0; goto ldv_38312; ldv_38311: write_radio_reg(pi, coreNum == 0 ? 369 : 401, (int )*(txcal_radio_regs + (unsigned long )(coreNum * 2))); write_radio_reg(pi, coreNum == 0 ? 370 : 402, (int )*(txcal_radio_regs + ((unsigned long )(coreNum * 2) + 1UL))); write_radio_reg(pi, coreNum == 0 ? 371 : 403, (int )*(txcal_radio_regs + ((unsigned long )(coreNum * 2) + 4UL))); write_radio_reg(pi, coreNum == 0 ? 372 : 404, (int )*(txcal_radio_regs + ((unsigned long )(coreNum * 2) + 5UL))); coreNum = coreNum + 1; ldv_38312: ; if (coreNum <= 1) { goto ldv_38311; } else { } } else { } return; } } static void wlc_phy_txpwrctrl_coeff_setup_nphy(struct brcms_phy *pi ) { u32 idx ; u16 iqloCalbuf[7U] ; u32 iqcomp ; u32 locomp ; u32 curr_locomp ; s8 locomp_i ; s8 locomp_q ; s8 curr_locomp_i ; s8 curr_locomp_q ; u32 tbl_id ; u32 tbl_len ; u32 tbl_offset ; u32 regval[128U] ; { if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } wlc_phy_table_read_nphy(pi, 15U, 7U, 80U, 16U, (void *)(& iqloCalbuf)); tbl_len = 128U; tbl_offset = 320U; tbl_id = 26U; goto ldv_38334; ldv_38333: iqcomp = tbl_id == 26U ? (((unsigned int )iqloCalbuf[0] & 1023U) << 10) | ((unsigned int )iqloCalbuf[1] & 1023U) : (((unsigned int )iqloCalbuf[2] & 1023U) << 10) | ((unsigned int )iqloCalbuf[3] & 1023U); idx = 0U; goto ldv_38331; ldv_38330: regval[idx] = iqcomp; idx = idx + 1U; ldv_38331: ; if (idx < tbl_len) { goto ldv_38330; } else { } wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32U, (void const *)(& regval)); tbl_id = tbl_id + 1U; ldv_38334: ; if (tbl_id <= 27U) { goto ldv_38333; } else { } tbl_offset = 448U; tbl_id = 26U; goto ldv_38340; ldv_38339: locomp = (unsigned int )(tbl_id == 26U ? iqloCalbuf[5] : iqloCalbuf[6]); locomp_i = (signed char )(locomp >> 8); locomp_q = (signed char )locomp; idx = 0U; goto ldv_38337; ldv_38336: ; if (pi->pubpi.phy_rev > 2U) { curr_locomp_i = locomp_i; curr_locomp_q = locomp_q; } else { curr_locomp_i = (signed char )(((int )locomp_i * (int )nphy_tpc_loscale[idx] + 128) >> 8); curr_locomp_q = (signed char )(((int )locomp_q * (int )nphy_tpc_loscale[idx] + 128) >> 8); } curr_locomp = (unsigned int )((int )curr_locomp_i << 8) & 65535U; curr_locomp = ((unsigned int )curr_locomp_q & 255U) | curr_locomp; regval[idx] = curr_locomp; idx = idx + 1U; ldv_38337: ; if (idx < tbl_len) { goto ldv_38336; } else { } wlc_phy_table_write_nphy(pi, tbl_id, tbl_len, tbl_offset, 32U, (void const *)(& regval)); tbl_id = tbl_id + 1U; ldv_38340: ; if (tbl_id <= 27U) { goto ldv_38339; } else { } if (pi->pubpi.phy_rev <= 1U) { wlapi_bmac_write_shm((pi->sh)->physhim, 1800U, 65535); wlapi_bmac_write_shm((pi->sh)->physhim, 1806U, 65535); } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static void wlc_phy_txlpfbw_nphy(struct brcms_phy *pi ) { u8 tx_lpf_bw ; { tx_lpf_bw = 0U; if (pi->pubpi.phy_rev > 2U && pi->pubpi.phy_rev <= 6U) { if (((int )pi->radio_chanspec & 3072) == 3072) { tx_lpf_bw = 3U; } else { tx_lpf_bw = 1U; } if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if (((int )pi->radio_chanspec & 3072) == 3072) { tx_lpf_bw = 5U; } else { tx_lpf_bw = 4U; } } else { } write_phy_reg(pi, 232, (int )((u16 )((((int )((short )tx_lpf_bw) | (int )((short )((int )tx_lpf_bw << 3))) | (int )((short )((int )tx_lpf_bw << 6))) | (int )((short )((int )tx_lpf_bw << 9))))); if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if (((int )pi->radio_chanspec & 3072) == 3072) { tx_lpf_bw = 4U; } else { tx_lpf_bw = 1U; } write_phy_reg(pi, 233, (int )((u16 )((((int )((short )tx_lpf_bw) | (int )((short )((int )tx_lpf_bw << 3))) | (int )((short )((int )tx_lpf_bw << 6))) | (int )((short )((int )tx_lpf_bw << 9))))); } else { } } else { } return; } } static void wlc_phy_adjust_rx_analpfbw_nphy(struct brcms_phy *pi , u16 reduction_factr ) { { if (pi->pubpi.phy_rev > 2U && pi->pubpi.phy_rev <= 6U) { if ((unsigned int )((unsigned char )pi->radio_chanspec) == 11U && ((int )pi->radio_chanspec & 3072) == 3072) { if (! pi->nphy_anarxlpf_adjusted) { write_radio_reg(pi, 24683, (int )((u16 )((int )((short )((int )pi->nphy_rccal_value + (int )reduction_factr)) | 128))); pi->nphy_anarxlpf_adjusted = 1; } else { } } else if ((int )pi->nphy_anarxlpf_adjusted) { write_radio_reg(pi, 24683, (int )((unsigned int )pi->nphy_rccal_value | 128U)); pi->nphy_anarxlpf_adjusted = 0; } else { } } else { } return; } } static void wlc_phy_adjust_min_noisevar_nphy(struct brcms_phy *pi , int ntones , int *tone_id_buf , u32 *noise_var_buf ) { int i ; u32 offset ; int tone_id ; int tbllen ; { tbllen = ((int )pi->radio_chanspec & 3072) == 3072 ? 256 : 128; if ((int )pi->nphy_noisevars_adjusted) { i = 0; goto ldv_38361; ldv_38360: tone_id = pi->nphy_saved_noisevars.tone_id[i]; offset = (u32 )(tone_id >= 0 ? tone_id * 2 + 1 : (tone_id * 2 + tbllen) + 1); wlc_phy_table_write_nphy(pi, 16U, 1U, offset, 32U, (void const *)(& pi->nphy_saved_noisevars.min_noise_vars) + (unsigned long )i); i = i + 1; ldv_38361: ; if (pi->nphy_saved_noisevars.bufcount > i) { goto ldv_38360; } else { } pi->nphy_saved_noisevars.bufcount = 0; pi->nphy_noisevars_adjusted = 0; } else { } if ((unsigned long )noise_var_buf != (unsigned long )((u32 *)0U) && (unsigned long )tone_id_buf != (unsigned long )((int *)0)) { pi->nphy_saved_noisevars.bufcount = 0; i = 0; goto ldv_38364; ldv_38363: tone_id = *(tone_id_buf + (unsigned long )i); offset = (u32 )(tone_id >= 0 ? tone_id * 2 + 1 : (tone_id * 2 + tbllen) + 1); pi->nphy_saved_noisevars.tone_id[i] = tone_id; wlc_phy_table_read_nphy(pi, 16U, 1U, offset, 32U, (void *)(& pi->nphy_saved_noisevars.min_noise_vars) + (unsigned long )i); wlc_phy_table_write_nphy(pi, 16U, 1U, offset, 32U, (void const *)noise_var_buf + (unsigned long )i); pi->nphy_saved_noisevars.bufcount = pi->nphy_saved_noisevars.bufcount + 1; i = i + 1; ldv_38364: ; if (i < ntones) { goto ldv_38363; } else { } pi->nphy_noisevars_adjusted = 1; } else { } return; } } static void wlc_phy_adjust_crsminpwr_nphy(struct brcms_phy *pi , u8 minpwr ) { u16 regval ; { if (pi->pubpi.phy_rev > 2U) { if ((unsigned int )((unsigned char )pi->radio_chanspec) == 11U && ((int )pi->radio_chanspec & 3072) == 3072) { if (! pi->nphy_crsminpwr_adjusted) { regval = read_phy_reg(pi, 637); pi->nphy_crsminpwr[0] = (unsigned int )regval & 255U; regval = (unsigned int )regval & 65280U; regval = (int )((u16 )minpwr) | (int )regval; write_phy_reg(pi, 637, (int )regval); regval = read_phy_reg(pi, 640); pi->nphy_crsminpwr[1] = (unsigned int )regval & 255U; regval = (unsigned int )regval & 65280U; regval = (int )((u16 )minpwr) | (int )regval; write_phy_reg(pi, 640, (int )regval); regval = read_phy_reg(pi, 643); pi->nphy_crsminpwr[2] = (unsigned int )regval & 255U; regval = (unsigned int )regval & 65280U; regval = (int )((u16 )minpwr) | (int )regval; write_phy_reg(pi, 643, (int )regval); pi->nphy_crsminpwr_adjusted = 1; } else { } } else if ((int )pi->nphy_crsminpwr_adjusted) { regval = read_phy_reg(pi, 637); regval = (unsigned int )regval & 65280U; regval = (u16 )((int )pi->nphy_crsminpwr[0] | (int )regval); write_phy_reg(pi, 637, (int )regval); regval = read_phy_reg(pi, 640); regval = (unsigned int )regval & 65280U; regval = (u16 )((int )pi->nphy_crsminpwr[1] | (int )regval); write_phy_reg(pi, 640, (int )regval); regval = read_phy_reg(pi, 643); regval = (unsigned int )regval & 65280U; regval = (u16 )((int )pi->nphy_crsminpwr[2] | (int )regval); write_phy_reg(pi, 643, (int )regval); pi->nphy_crsminpwr_adjusted = 0; } else { } } else { } return; } } static void wlc_phy_spurwar_nphy(struct brcms_phy *pi ) { u16 cur_channel ; int nphy_adj_tone_id_buf[2U] ; u32 nphy_adj_noise_var_buf[2U] ; bool isAdjustNoiseVar ; uint numTonesAdjust ; u32 tempval ; { cur_channel = 0U; nphy_adj_tone_id_buf[0] = 57; nphy_adj_tone_id_buf[1] = 58; nphy_adj_noise_var_buf[0] = 1023U; nphy_adj_noise_var_buf[1] = 1023U; isAdjustNoiseVar = 0; numTonesAdjust = 0U; tempval = 0U; if (pi->pubpi.phy_rev > 2U) { if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } cur_channel = (u16 )((unsigned char )pi->radio_chanspec); if ((int )pi->nphy_gband_spurwar_en) { wlc_phy_adjust_rx_analpfbw_nphy(pi, 7); if (((int )pi->radio_chanspec & 61440) == 8192) { if ((unsigned int )cur_channel == 11U && ((int )pi->radio_chanspec & 3072) == 3072) { wlc_phy_adjust_min_noisevar_nphy(pi, 2, (int *)(& nphy_adj_tone_id_buf), (u32 *)(& nphy_adj_noise_var_buf)); } else { wlc_phy_adjust_min_noisevar_nphy(pi, 0, (int *)0, (u32 *)0U); } } else { } wlc_phy_adjust_crsminpwr_nphy(pi, 30); } else { } if ((int )pi->nphy_gband_spurwar2_en && ((int )pi->radio_chanspec & 61440) == 8192) { if (((int )pi->radio_chanspec & 3072) == 3072) { switch ((int )cur_channel) { case 3: nphy_adj_tone_id_buf[0] = 57; nphy_adj_tone_id_buf[1] = 58; nphy_adj_noise_var_buf[0] = 559U; nphy_adj_noise_var_buf[1] = 607U; isAdjustNoiseVar = 1; goto ldv_38381; case 4: nphy_adj_tone_id_buf[0] = 41; nphy_adj_tone_id_buf[1] = 42; nphy_adj_noise_var_buf[0] = 559U; nphy_adj_noise_var_buf[1] = 607U; isAdjustNoiseVar = 1; goto ldv_38381; case 5: nphy_adj_tone_id_buf[0] = 25; nphy_adj_tone_id_buf[1] = 26; nphy_adj_noise_var_buf[0] = 591U; nphy_adj_noise_var_buf[1] = 607U; isAdjustNoiseVar = 1; goto ldv_38381; case 6: nphy_adj_tone_id_buf[0] = 9; nphy_adj_tone_id_buf[1] = 10; nphy_adj_noise_var_buf[0] = 559U; nphy_adj_noise_var_buf[1] = 591U; isAdjustNoiseVar = 1; goto ldv_38381; case 7: nphy_adj_tone_id_buf[0] = 121; nphy_adj_tone_id_buf[1] = 122; nphy_adj_noise_var_buf[0] = 399U; nphy_adj_noise_var_buf[1] = 591U; isAdjustNoiseVar = 1; goto ldv_38381; case 8: nphy_adj_tone_id_buf[0] = 105; nphy_adj_tone_id_buf[1] = 106; nphy_adj_noise_var_buf[0] = 559U; nphy_adj_noise_var_buf[1] = 607U; isAdjustNoiseVar = 1; goto ldv_38381; case 9: nphy_adj_tone_id_buf[0] = 89; nphy_adj_tone_id_buf[1] = 90; nphy_adj_noise_var_buf[0] = 559U; nphy_adj_noise_var_buf[1] = 591U; isAdjustNoiseVar = 1; goto ldv_38381; case 10: nphy_adj_tone_id_buf[0] = 73; nphy_adj_tone_id_buf[1] = 74; nphy_adj_noise_var_buf[0] = 559U; nphy_adj_noise_var_buf[1] = 591U; isAdjustNoiseVar = 1; goto ldv_38381; default: isAdjustNoiseVar = 0; goto ldv_38381; } ldv_38381: ; } else { } if ((int )isAdjustNoiseVar) { numTonesAdjust = 2U; wlc_phy_adjust_min_noisevar_nphy(pi, (int )numTonesAdjust, (int *)(& nphy_adj_tone_id_buf), (u32 *)(& nphy_adj_noise_var_buf)); tempval = 0U; } else { wlc_phy_adjust_min_noisevar_nphy(pi, 0, (int *)0, (u32 *)0U); } } else { } if ((int )pi->nphy_aband_spurwar_en && ((int )pi->radio_chanspec & 61440) == 4096) { switch ((int )cur_channel) { case 54: nphy_adj_tone_id_buf[0] = 32; nphy_adj_noise_var_buf[0] = 607U; goto ldv_38393; case 38: ; case 102: ; case 118: ; if ((pi->sh)->chip == 18198U && (pi->sh)->chippkg == 9U) { nphy_adj_tone_id_buf[0] = 32; nphy_adj_noise_var_buf[0] = 543U; } else { nphy_adj_tone_id_buf[0] = 0; nphy_adj_noise_var_buf[0] = 0U; } goto ldv_38393; case 134: nphy_adj_tone_id_buf[0] = 32; nphy_adj_noise_var_buf[0] = 543U; goto ldv_38393; case 151: nphy_adj_tone_id_buf[0] = 16; nphy_adj_noise_var_buf[0] = 575U; goto ldv_38393; case 153: ; case 161: nphy_adj_tone_id_buf[0] = 48; nphy_adj_noise_var_buf[0] = 575U; goto ldv_38393; default: nphy_adj_tone_id_buf[0] = 0; nphy_adj_noise_var_buf[0] = 0U; goto ldv_38393; } ldv_38393: ; if (nphy_adj_tone_id_buf[0] != 0 && nphy_adj_noise_var_buf[0] != 0U) { wlc_phy_adjust_min_noisevar_nphy(pi, 1, (int *)(& nphy_adj_tone_id_buf), (u32 *)(& nphy_adj_noise_var_buf)); } else { wlc_phy_adjust_min_noisevar_nphy(pi, 0, (int *)0, (u32 *)0U); } } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } } else { } return; } } void wlc_phy_init_nphy(struct brcms_phy *pi ) { u16 val ; u16 clip1_ths[2U] ; struct nphy_txgains target_gain ; u8 tx_pwr_ctrl_state ; bool do_nphy_cal ; uint core ; u32 d11_clk_ctl_st ; bool do_rssi_cal ; u32 tmp ; u32 *tx_pwrctrl_tbl ; u16 idx ; s16 pga_gn ; s16 pad_gn ; s32 rfpwr_offset ; int tmp___0 ; int tmp___1 ; { do_nphy_cal = 0; do_rssi_cal = 0; core = 0U; if ((pi->measure_hold & 2U) == 0U) { pi->measure_hold = pi->measure_hold | 32U; } else { } if ((pi->pubpi.phy_type == 4U && pi->pubpi.phy_rev > 4U) && ((pi->sh)->chippkg == 9U || (pi->sh)->chippkg == 10U)) { if (((pi->sh)->boardflags & 4096U) != 0U && ((int )pi->radio_chanspec & 61440) == 8192) { tmp = bcma_read32(((pi->d11core)->bus)->drv_cc.core, 40); bcma_write32(((pi->d11core)->bus)->drv_cc.core, 40, tmp | 64U); } else { } } else { } if (((! pi->ipa2g_on || ((int )pi->radio_chanspec & 61440) != 8192) && (! pi->ipa5g_on || ((int )pi->radio_chanspec & 61440) != 4096)) && (pi->sh)->chip == 21335U) { bcma_chipco_chipctl_maskset(& ((pi->d11core)->bus)->drv_cc, 1U, 4294950911U, 16384U); } else { } if (((int )pi->nphy_gband_spurwar2_en && ((int )pi->radio_chanspec & 61440) == 8192) && ((int )pi->radio_chanspec & 3072) == 3072) { d11_clk_ctl_st = bcma_read32(pi->d11core, 480); bcma_mask32(pi->d11core, 480, 4294967277U); bcma_write32(pi->d11core, 480, d11_clk_ctl_st); } else { } pi->use_int_tx_iqlo_cal_nphy = (bool )((((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) || (pi->pubpi.phy_rev > 6U || (pi->pubpi.phy_rev > 4U && ((pi->sh)->boardflags2 & 262144U) != 0U))); pi->internal_tx_iqlo_cal_tapoff_intpa_nphy = 0; pi->nphy_deaf_count = 0U; wlc_phy_tbl_init_nphy(pi); pi->nphy_crsminpwr_adjusted = 0; pi->nphy_noisevars_adjusted = 0; if (pi->pubpi.phy_rev > 2U) { write_phy_reg(pi, 231, 0); write_phy_reg(pi, 236, 0); if (pi->pubpi.phy_rev > 6U) { write_phy_reg(pi, 834, 0); write_phy_reg(pi, 835, 0); write_phy_reg(pi, 838, 0); write_phy_reg(pi, 839, 0); } else { } write_phy_reg(pi, 229, 0); write_phy_reg(pi, 230, 0); } else { write_phy_reg(pi, 236, 0); } write_phy_reg(pi, 145, 0); write_phy_reg(pi, 146, 0); if (pi->pubpi.phy_rev <= 5U) { write_phy_reg(pi, 147, 0); write_phy_reg(pi, 148, 0); } else { } and_phy_reg(pi, 161, 65532); if (pi->pubpi.phy_rev > 2U) { write_phy_reg(pi, 143, 0); write_phy_reg(pi, 165, 0); } else { write_phy_reg(pi, 165, 0); } if (pi->pubpi.phy_rev == 2U) { mod_phy_reg(pi, 220, 255, 59); } else if (pi->pubpi.phy_rev <= 1U) { mod_phy_reg(pi, 220, 255, 64); } else { } write_phy_reg(pi, 515, 32); write_phy_reg(pi, 513, 32); if (((pi->sh)->boardflags2 & 256U) != 0U) { write_phy_reg(pi, 525, 160); } else { write_phy_reg(pi, 525, 184); } write_phy_reg(pi, 314, 200); write_phy_reg(pi, 112, 80); write_phy_reg(pi, 511, 48); if (pi->pubpi.phy_rev <= 7U) { wlc_phy_update_mimoconfig_nphy(pi, (s32 )pi->n_preamble_override); } else { } wlc_phy_stf_chain_upd_nphy(pi); if (pi->pubpi.phy_rev <= 1U) { write_phy_reg(pi, 384, 2728); write_phy_reg(pi, 385, 2468); } else { } if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { core = 0U; goto ldv_38414; ldv_38413: mod_phy_reg(pi, core == 0U ? 663 : 667, 1, 1); mod_phy_reg(pi, core == 0U ? 664 : 668, 65408, (int )((u16 )pi->nphy_papd_epsilon_offset[core]) << 7U); core = core + 1U; ldv_38414: ; if ((uint )pi->pubpi.phy_corenum > core) { goto ldv_38413; } else { } wlc_phy_ipa_set_tx_digi_filts_nphy(pi); } else if (pi->pubpi.phy_rev > 4U) { wlc_phy_extpa_set_tx_digi_filts_nphy(pi); } else { } wlc_phy_workarounds_nphy(pi); wlapi_bmac_phyclk_fgc((pi->sh)->physhim, 1); val = read_phy_reg(pi, 1); write_phy_reg(pi, 1, (int )((unsigned int )val | 16384U)); write_phy_reg(pi, 1, (int )val & 49151); wlapi_bmac_phyclk_fgc((pi->sh)->physhim, 0); wlapi_bmac_macphyclk_set((pi->sh)->physhim, 1); wlc_phy_pa_override_nphy(pi, 0); wlc_phy_force_rfseq_nphy(pi, 0); wlc_phy_force_rfseq_nphy(pi, 2); wlc_phy_pa_override_nphy(pi, 1); wlc_phy_classifier_nphy(pi, 0, 0); wlc_phy_clip_det_nphy(pi, 0, (u16 *)(& clip1_ths)); if (((int )pi->radio_chanspec & 61440) == 8192) { wlc_phy_bphy_init_nphy(pi); } else { } tx_pwr_ctrl_state = pi->nphy_txpwrctrl; wlc_phy_txpwrctrl_enable_nphy(pi, 0); wlc_phy_txpwr_fixpower_nphy(pi); wlc_phy_txpwrctrl_idle_tssi_nphy(pi); wlc_phy_txpwrctrl_pwr_setup_nphy(pi); if (pi->pubpi.phy_rev > 2U) { tx_pwrctrl_tbl = (u32 *)0U; pga_gn = 0; pad_gn = 0; if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { tx_pwrctrl_tbl = wlc_phy_get_ipa_gaintbl_nphy(pi); } else if (((int )pi->radio_chanspec & 61440) == 4096) { if (pi->pubpi.phy_rev == 3U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_5GHz_txgain_rev3); } else if (pi->pubpi.phy_rev == 4U) { tx_pwrctrl_tbl = (unsigned int )pi->srom_fem5g.extpagain == 3U ? (u32 *)(& nphy_tpc_5GHz_txgain_HiPwrEPA) : (u32 *)(& nphy_tpc_5GHz_txgain_rev4); } else { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_5GHz_txgain_rev5); } } else if (pi->pubpi.phy_rev > 6U) { if ((unsigned int )pi->pubpi.radiorev == 5U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_epa_2057rev5); } else if ((unsigned int )pi->pubpi.radiorev == 3U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_epa_2057rev3); } else { } } else if (pi->pubpi.phy_rev > 4U && (unsigned int )pi->srom_fem2g.extpagain == 3U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_HiPwrEPA); } else { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_rev3); } wlc_phy_table_write_nphy(pi, 26U, 128U, 192U, 32U, (void const *)tx_pwrctrl_tbl); wlc_phy_table_write_nphy(pi, 27U, 128U, 192U, 32U, (void const *)tx_pwrctrl_tbl); pi->nphy_gmval = (unsigned int )((unsigned short )(*tx_pwrctrl_tbl >> 16)) & 28672U; if (pi->pubpi.phy_rev > 6U) { idx = 0U; goto ldv_38422; ldv_38421: pga_gn = (int )((s16 )(*(tx_pwrctrl_tbl + (unsigned long )idx) >> 24)) & 15; pad_gn = (int )((s16 )(*(tx_pwrctrl_tbl + (unsigned long )idx) >> 19)) & 31; rfpwr_offset = get_rf_pwr_offset(pi, (int )pga_gn, (int )pad_gn); wlc_phy_table_write_nphy(pi, 26U, 1U, (u32 )((int )idx + 576), 32U, (void const *)(& rfpwr_offset)); wlc_phy_table_write_nphy(pi, 27U, 1U, (u32 )((int )idx + 576), 32U, (void const *)(& rfpwr_offset)); idx = (u16 )((int )idx + 1); ldv_38422: ; if ((unsigned int )idx <= 127U) { goto ldv_38421; } else { } } else { idx = 0U; goto ldv_38425; ldv_38424: pga_gn = (int )((s16 )(*(tx_pwrctrl_tbl + (unsigned long )idx) >> 24)) & 15; if (((int )pi->radio_chanspec & 61440) == 8192) { rfpwr_offset = (s32 )nphy_papd_pga_gain_delta_ipa_2g[(int )pga_gn]; } else { rfpwr_offset = (s32 )nphy_papd_pga_gain_delta_ipa_5g[(int )pga_gn]; } wlc_phy_table_write_nphy(pi, 26U, 1U, (u32 )((int )idx + 576), 32U, (void const *)(& rfpwr_offset)); wlc_phy_table_write_nphy(pi, 27U, 1U, (u32 )((int )idx + 576), 32U, (void const *)(& rfpwr_offset)); idx = (u16 )((int )idx + 1); ldv_38425: ; if ((unsigned int )idx <= 127U) { goto ldv_38424; } else { } } } else { wlc_phy_table_write_nphy(pi, 26U, 128U, 192U, 32U, (void const *)(& nphy_tpc_txgain)); wlc_phy_table_write_nphy(pi, 27U, 128U, 192U, 32U, (void const *)(& nphy_tpc_txgain)); } if ((unsigned int )(pi->sh)->phyrxchain != 3U) { wlc_phy_rxcore_setstate_nphy((struct brcms_phy_pub *)pi, (int )(pi->sh)->phyrxchain); } else { } if ((unsigned int )pi->mphase_cal_phase_id != 0U) { wlc_phy_cal_perical_mphase_restart(pi); } else { } if (pi->pubpi.phy_rev > 2U) { do_rssi_cal = ((int )pi->radio_chanspec & 61440) == 8192 ? (unsigned int )pi->nphy_rssical_chanspec_2G == 0U : (unsigned int )pi->nphy_rssical_chanspec_5G == 0U; if ((int )do_rssi_cal) { wlc_phy_rssi_cal_nphy(pi); } else { wlc_phy_restore_rssical_nphy(pi); } } else { wlc_phy_rssi_cal_nphy(pi); } if ((pi->measure_hold & 6U) == 0U) { do_nphy_cal = ((int )pi->radio_chanspec & 61440) == 8192 ? (unsigned int )pi->nphy_iqcal_chanspec_2G == 0U : (unsigned int )pi->nphy_iqcal_chanspec_5G == 0U; } else { } if (! pi->do_initcal) { do_nphy_cal = 0; } else { } if ((int )do_nphy_cal) { target_gain = wlc_phy_get_tx_gain_nphy(pi); if ((unsigned int )pi->antsel_type == 2U) { wlc_phy_antsel_init((struct brcms_phy_pub *)pi, 1); } else { } if ((unsigned int )pi->nphy_perical != 2U) { wlc_phy_rssi_cal_nphy(pi); if (pi->pubpi.phy_rev > 2U) { pi->nphy_cal_orig_pwr_idx[0] = (u8 )pi->nphy_txpwrindex[0].index_internal; pi->nphy_cal_orig_pwr_idx[1] = (u8 )pi->nphy_txpwrindex[1].index_internal; wlc_phy_precal_txgain_nphy(pi); target_gain = wlc_phy_get_tx_gain_nphy(pi); } else { } tmp___1 = wlc_phy_cal_txiqlo_nphy(pi, target_gain, 1, 0); if (tmp___1 == 0) { tmp___0 = wlc_phy_cal_rxiq_nphy(pi, target_gain, 2, 0); if (tmp___0 == 0) { wlc_phy_savecal_nphy(pi); } else { } } else { } } else if ((unsigned int )pi->mphase_cal_phase_id == 0U) { wlc_phy_cal_perical((struct brcms_phy_pub *)pi, 3); } else { } } else { wlc_phy_restorecal_nphy(pi); } wlc_phy_txpwrctrl_coeff_setup_nphy(pi); wlc_phy_txpwrctrl_enable_nphy(pi, (int )tx_pwr_ctrl_state); wlc_phy_nphy_tkip_rifs_war(pi, (int )(pi->sh)->_rifs_phy); if (pi->pubpi.phy_rev > 2U && pi->pubpi.phy_rev <= 6U) { write_phy_reg(pi, 112, 50); } else { } wlc_phy_txlpfbw_nphy(pi); wlc_phy_spurwar_nphy(pi); return; } } static void wlc_phy_resetcca_nphy(struct brcms_phy *pi ) { u16 val ; { wlapi_bmac_phyclk_fgc((pi->sh)->physhim, 1); val = read_phy_reg(pi, 1); write_phy_reg(pi, 1, (int )((unsigned int )val | 16384U)); __const_udelay(4295UL); write_phy_reg(pi, 1, (int )val & 49151); wlapi_bmac_phyclk_fgc((pi->sh)->physhim, 0); wlc_phy_force_rfseq_nphy(pi, 2); return; } } void wlc_phy_pa_override_nphy(struct brcms_phy *pi , bool en ) { u16 rfctrlintc_override_val ; { if (! en) { pi->rfctrlIntc1_save = read_phy_reg(pi, 145); pi->rfctrlIntc2_save = read_phy_reg(pi, 146); if (pi->pubpi.phy_rev > 6U) { rfctrlintc_override_val = 5248U; } else if (pi->pubpi.phy_rev > 2U) { rfctrlintc_override_val = ((int )pi->radio_chanspec & 61440) == 4096 ? 1536U : 1152U; } else { rfctrlintc_override_val = ((int )pi->radio_chanspec & 61440) == 4096 ? 384U : 288U; } write_phy_reg(pi, 145, (int )rfctrlintc_override_val); write_phy_reg(pi, 146, (int )rfctrlintc_override_val); } else { write_phy_reg(pi, 145, (int )pi->rfctrlIntc1_save); write_phy_reg(pi, 146, (int )pi->rfctrlIntc2_save); } return; } } void wlc_phy_stf_chain_upd_nphy(struct brcms_phy *pi ) { u16 txrx_chain ; bool CoreActv_override ; { txrx_chain = 51U; CoreActv_override = 0; if ((int )pi->nphy_txrx_chain == 0) { txrx_chain = 17U; CoreActv_override = 1; if (pi->pubpi.phy_rev <= 2U) { and_phy_reg(pi, 160, 65503); } else { } } else if ((int )pi->nphy_txrx_chain == 1) { txrx_chain = 34U; CoreActv_override = 1; if (pi->pubpi.phy_rev <= 2U) { or_phy_reg(pi, 160, 32); } else { } } else { } mod_phy_reg(pi, 162, 255, (int )txrx_chain); if ((int )CoreActv_override) { pi->nphy_perical = 0U; or_phy_reg(pi, 161, 1); } else { pi->nphy_perical = 2U; and_phy_reg(pi, 161, 65534); } return; } } void wlc_phy_rxcore_setstate_nphy(struct brcms_phy_pub *pih , u8 rxcore_bitmask ) { u16 regval ; u16 tbl_buf[16U] ; uint i ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u16 tbl_opcode ; bool suspend ; u32 tmp ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; (pi->sh)->phyrxchain = rxcore_bitmask; if (! (pi->sh)->clk) { return; } else { } tmp = bcma_read32(pi->d11core, 288); suspend = (tmp & 1U) == 0U; if (! suspend) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } regval = read_phy_reg(pi, 162); regval = (unsigned int )regval & 65295U; regval = (u16 )((int )((short )(((int )rxcore_bitmask & 3) << 4)) | (int )((short )regval)); write_phy_reg(pi, 162, (int )regval); if (((int )rxcore_bitmask & 3) != 3) { write_phy_reg(pi, 526, 1); if (pi->pubpi.phy_rev > 2U) { if ((int )pi->rx2tx_biasentry == -1) { wlc_phy_table_read_nphy(pi, 7U, 16U, 80U, 16U, (void *)(& tbl_buf)); i = 0U; goto ldv_38459; ldv_38458: ; if ((unsigned int )tbl_buf[i] == 15U) { pi->rx2tx_biasentry = (s8 )i; tbl_opcode = 0U; wlc_phy_table_write_nphy(pi, 7U, 1U, i, 16U, (void const *)(& tbl_opcode)); goto ldv_38457; } else if ((unsigned int )tbl_buf[i] == 31U) { goto ldv_38457; } else { } i = i + 1U; ldv_38459: ; if (i <= 15U) { goto ldv_38458; } else { } ldv_38457: ; } else { } } else { } } else { write_phy_reg(pi, 526, 30); if (pi->pubpi.phy_rev > 2U) { if ((int )pi->rx2tx_biasentry != -1) { tbl_opcode = 15U; wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )pi->rx2tx_biasentry, 16U, (void const *)(& tbl_opcode)); pi->rx2tx_biasentry = -1; } else { } } else { } } wlc_phy_force_rfseq_nphy(pi, 2); if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } if (! suspend) { wlapi_enable_mac((pi->sh)->physhim); } else { } return; } } u8 wlc_phy_rxcore_getstate_nphy(struct brcms_phy_pub *pih ) { u16 regval ; u16 rxen_bits ; struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; { __mptr = (struct brcms_phy_pub const *)pih; pi = (struct brcms_phy *)__mptr; regval = read_phy_reg(pi, 162); rxen_bits = (unsigned int )((u16 )((int )regval >> 4)) & 15U; return ((u8 )rxen_bits); } } bool wlc_phy_n_txpower_ipa_ison(struct brcms_phy *pi ) { { return ((bool )(((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096))); } } void wlc_phy_cal_init_nphy(struct brcms_phy *pi ) { { return; } } static void wlc_phy_radio_preinit_205x(struct brcms_phy *pi ) { { and_phy_reg(pi, 120, 64511); and_phy_reg(pi, 120, 128); or_phy_reg(pi, 120, 65407); or_phy_reg(pi, 120, 1024); return; } } static void wlc_phy_radio_init_2057(struct brcms_phy *pi ) { struct radio_20xx_regs *regs_2057_ptr ; { regs_2057_ptr = (struct radio_20xx_regs *)0; if (pi->pubpi.phy_rev == 7U) { regs_2057_ptr = (struct radio_20xx_regs *)(& regs_2057_rev4); } else if (pi->pubpi.phy_rev == 8U) { switch ((int )pi->pubpi.radiorev) { case 5: ; if (pi->pubpi.phy_rev == 8U) { regs_2057_ptr = (struct radio_20xx_regs *)(& regs_2057_rev5); } else { } goto ldv_38482; case 7: regs_2057_ptr = (struct radio_20xx_regs *)(& regs_2057_rev7); goto ldv_38482; case 8: regs_2057_ptr = (struct radio_20xx_regs *)(& regs_2057_rev8); goto ldv_38482; default: ; goto ldv_38482; } ldv_38482: ; } else { } wlc_phy_init_radio_regs_allbands(pi, regs_2057_ptr); return; } } static u16 wlc_phy_radio205x_rcal(struct brcms_phy *pi ) { u16 rcal_reg ; int i ; int __ret_warn_on ; long tmp ; long tmp___0 ; u16 tmp___1 ; u16 savereg ; int __ret_warn_on___0 ; long tmp___2 ; long tmp___3 ; { rcal_reg = 0U; if (pi->pubpi.phy_rev > 6U) { if ((unsigned int )pi->pubpi.radiorev == 5U) { and_phy_reg(pi, 834, 65533); __const_udelay(42950UL); mod_radio_reg(pi, 205, 1, 1); mod_radio_reg(pi, 458, 2, 1); } else { } mod_radio_reg(pi, 4, 1, 1); __const_udelay(42950UL); mod_radio_reg(pi, 4, 3, 3); i = 0; goto ldv_38493; ldv_38492: rcal_reg = read_radio_reg(pi, 355); if ((int )rcal_reg & 1) { goto ldv_38491; } else { } __const_udelay(429500UL); i = i + 1; ldv_38493: ; if (i <= 9999) { goto ldv_38492; } else { } ldv_38491: __ret_warn_on = i == 10000; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c", 19910, "HW error: radio calib2"); } else { } tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { return (0U); } else { } mod_radio_reg(pi, 4, 2, 0); tmp___1 = read_radio_reg(pi, 355); rcal_reg = (unsigned int )tmp___1 & 62U; mod_radio_reg(pi, 4, 1, 0); if ((unsigned int )pi->pubpi.radiorev == 5U) { mod_radio_reg(pi, 205, 1, 0); mod_radio_reg(pi, 458, 2, 0); } else { } if ((unsigned int )pi->pubpi.radiorev <= 4U || (unsigned int )pi->pubpi.radiorev == 6U) { mod_radio_reg(pi, 12, 60, (int )rcal_reg); mod_radio_reg(pi, 10, 240, (int )rcal_reg << 2U); } else { } } else if (pi->pubpi.phy_rev == 3U) { savereg = read_radio_reg(pi, 61); write_radio_reg(pi, 61, (int )((unsigned int )savereg | 7U)); __const_udelay(42950UL); write_radio_reg(pi, 44, 1); __const_udelay(42950UL); write_radio_reg(pi, 44, 9); i = 0; goto ldv_38499; ldv_38498: rcal_reg = read_radio_reg(pi, 45); if (((int )rcal_reg & 128) != 0) { goto ldv_38497; } else { } __const_udelay(429500UL); i = i + 1; ldv_38499: ; if (i <= 9999) { goto ldv_38498; } else { } ldv_38497: __ret_warn_on___0 = i == 10000; tmp___2 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___2 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c", 19964, "HW error: radio calib3"); } else { } tmp___3 = ldv__builtin_expect(__ret_warn_on___0 != 0, 0L); if (tmp___3 != 0L) { return (0U); } else { } write_radio_reg(pi, 44, 1); rcal_reg = read_radio_reg(pi, 45); write_radio_reg(pi, 44, 0); write_radio_reg(pi, 61, (int )savereg); return ((unsigned int )rcal_reg & 31U); } else { } return ((unsigned int )rcal_reg & 62U); } } static u16 wlc_phy_radio2057_rccal(struct brcms_phy *pi ) { u16 rccal_valid ; int i ; bool chip43226_6362A0 ; int __ret_warn_on ; long tmp ; long tmp___0 ; { chip43226_6362A0 = (bool )(((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U); rccal_valid = 0U; if ((int )chip43226_6362A0) { write_radio_reg(pi, 2, 97); write_radio_reg(pi, 348, 192); } else { write_radio_reg(pi, 430, 97); write_radio_reg(pi, 348, 233); } write_radio_reg(pi, 347, 110); write_radio_reg(pi, 346, 85); i = 0; goto ldv_38510; ldv_38509: rccal_valid = read_radio_reg(pi, 350); if (((int )rccal_valid & 2) != 0) { goto ldv_38508; } else { } __const_udelay(2147500UL); i = i + 1; ldv_38510: ; if (i <= 9999) { goto ldv_38509; } else { } ldv_38508: write_radio_reg(pi, 346, 21); rccal_valid = 0U; if ((int )chip43226_6362A0) { write_radio_reg(pi, 2, 105); write_radio_reg(pi, 348, 176); } else { write_radio_reg(pi, 430, 105); write_radio_reg(pi, 348, 213); } write_radio_reg(pi, 347, 110); write_radio_reg(pi, 346, 85); i = 0; goto ldv_38513; ldv_38512: rccal_valid = read_radio_reg(pi, 350); if (((int )rccal_valid & 2) != 0) { goto ldv_38511; } else { } __const_udelay(2147500UL); i = i + 1; ldv_38513: ; if (i <= 9999) { goto ldv_38512; } else { } ldv_38511: write_radio_reg(pi, 346, 21); rccal_valid = 0U; if ((int )chip43226_6362A0) { write_radio_reg(pi, 2, 115); write_radio_reg(pi, 347, 40); write_radio_reg(pi, 348, 176); } else { write_radio_reg(pi, 430, 115); write_radio_reg(pi, 347, 110); write_radio_reg(pi, 348, 153); } write_radio_reg(pi, 346, 85); i = 0; goto ldv_38516; ldv_38515: rccal_valid = read_radio_reg(pi, 350); if (((int )rccal_valid & 2) != 0) { goto ldv_38514; } else { } __const_udelay(2147500UL); i = i + 1; ldv_38516: ; if (i <= 9999) { goto ldv_38515; } else { } ldv_38514: __ret_warn_on = ((int )rccal_valid & 2) == 0; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c", 20061, "HW error: radio calib4"); } else { } tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { return (0U); } else { } write_radio_reg(pi, 346, 21); return (rccal_valid); } } static void wlc_phy_radio_postinit_2057(struct brcms_phy *pi ) { unsigned long __ms ; unsigned long tmp ; { mod_radio_reg(pi, 356, 1, 1); mod_radio_reg(pi, 46, 120, 120); mod_radio_reg(pi, 206, 128, 128); if (1) { __const_udelay(8590000UL); } else { __ms = 2UL; goto ldv_38524; ldv_38523: __const_udelay(4295000UL); ldv_38524: tmp = __ms; __ms = __ms - 1UL; if (tmp != 0UL) { goto ldv_38523; } else { } } mod_radio_reg(pi, 46, 120, 0); mod_radio_reg(pi, 206, 128, 0); if ((int )pi->phy_init_por) { wlc_phy_radio205x_rcal(pi); wlc_phy_radio2057_rccal(pi); } else { } mod_radio_reg(pi, 17, 8, 0); return; } } static void wlc_phy_radio_init_2056(struct brcms_phy *pi ) { struct radio_regs const *regs_SYN_2056_ptr ; struct radio_regs const *regs_TX_2056_ptr ; struct radio_regs const *regs_RX_2056_ptr ; { regs_SYN_2056_ptr = (struct radio_regs const *)0; regs_TX_2056_ptr = (struct radio_regs const *)0; regs_RX_2056_ptr = (struct radio_regs const *)0; if (pi->pubpi.phy_rev == 3U) { regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056); regs_TX_2056_ptr = (struct radio_regs const *)(& regs_TX_2056); regs_RX_2056_ptr = (struct radio_regs const *)(& regs_RX_2056); } else if (pi->pubpi.phy_rev == 4U) { regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_A1); regs_TX_2056_ptr = (struct radio_regs const *)(& regs_TX_2056_A1); regs_RX_2056_ptr = (struct radio_regs const *)(& regs_RX_2056_A1); } else { switch ((int )pi->pubpi.radiorev) { case 5: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev5); regs_TX_2056_ptr = (struct radio_regs const *)(& regs_TX_2056_rev5); regs_RX_2056_ptr = (struct radio_regs const *)(& regs_RX_2056_rev5); goto ldv_38533; case 6: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev6); regs_TX_2056_ptr = (struct radio_regs const *)(& regs_TX_2056_rev6); regs_RX_2056_ptr = (struct radio_regs const *)(& regs_RX_2056_rev6); goto ldv_38533; case 7: ; case 9: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev7); regs_TX_2056_ptr = (struct radio_regs const *)(& regs_TX_2056_rev7); regs_RX_2056_ptr = (struct radio_regs const *)(& regs_RX_2056_rev7); goto ldv_38533; case 8: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev8); regs_TX_2056_ptr = (struct radio_regs const *)(& regs_TX_2056_rev8); regs_RX_2056_ptr = (struct radio_regs const *)(& regs_RX_2056_rev8); goto ldv_38533; case 11: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev11); regs_TX_2056_ptr = (struct radio_regs const *)(& regs_TX_2056_rev11); regs_RX_2056_ptr = (struct radio_regs const *)(& regs_RX_2056_rev11); goto ldv_38533; default: ; goto ldv_38533; } ldv_38533: ; } wlc_phy_init_radio_regs(pi, regs_SYN_2056_ptr, 0); wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, 8192); wlc_phy_init_radio_regs(pi, regs_TX_2056_ptr, 12288); wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, 24576); wlc_phy_init_radio_regs(pi, regs_RX_2056_ptr, 28672); return; } } static void wlc_phy_radio_postinit_2056(struct brcms_phy *pi ) { { mod_radio_reg(pi, 8, 11, 11); mod_radio_reg(pi, 9, 2, 2); mod_radio_reg(pi, 11, 2, 2); __const_udelay(4295000UL); mod_radio_reg(pi, 11, 2, 0); if (((pi->sh)->boardflags2 & 128U) != 0U || ((pi->sh)->boardflags2 & 524288U) != 0U) { mod_radio_reg(pi, 61, 244, 0); } else { mod_radio_reg(pi, 61, 252, 0); } mod_radio_reg(pi, 46, 1, 0); if ((int )pi->phy_init_por) { wlc_phy_radio205x_rcal(pi); } else { } return; } } static void wlc_phy_radio_preinit_2055(struct brcms_phy *pi ) { { and_phy_reg(pi, 120, 65471); or_phy_reg(pi, 120, 1152); or_phy_reg(pi, 120, 64); return; } } static void wlc_phy_radio_init_2055(struct brcms_phy *pi ) { { wlc_phy_init_radio_regs(pi, (struct radio_regs const *)(& regs_2055), 0); return; } } static void wlc_phy_radio_postinit_2055(struct brcms_phy *pi ) { uint countdown ; u16 tmp ; int __ret_warn_on ; u16 tmp___0 ; long tmp___1 ; long tmp___2 ; { and_radio_reg(pi, 17, 65523); if (((pi->sh)->sromrev > 3U && ((pi->sh)->boardflags2 & 1U) == 0U) || (pi->sh)->sromrev <= 3U) { and_radio_reg(pi, 119, 127); and_radio_reg(pi, 166, 127); } else { } mod_radio_reg(pi, 35, 63, 44); write_radio_reg(pi, 36, 60); and_radio_reg(pi, 36, 65470); or_radio_reg(pi, 41, 128); or_radio_reg(pi, 36, 1); __const_udelay(4295000UL); or_radio_reg(pi, 36, 64); countdown = 2009U; goto ldv_38554; ldv_38553: __const_udelay(42950UL); countdown = countdown - 10U; ldv_38554: tmp = read_radio_reg(pi, 38); if (((int )tmp & 128) == 0 && countdown > 9U) { goto ldv_38553; } else { } tmp___0 = read_radio_reg(pi, 38); __ret_warn_on = ((int )tmp___0 & 128) == 0; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c", 20218, "HW error: radio calibration1\n"); } else { } tmp___2 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___2 != 0L) { return; } else { } and_radio_reg(pi, 41, 65407); wlc_phy_chanspec_set((struct brcms_phy_pub *)pi, (int )pi->radio_chanspec); write_radio_reg(pi, 107, 9); write_radio_reg(pi, 154, 9); write_radio_reg(pi, 108, 131); write_radio_reg(pi, 155, 131); mod_radio_reg(pi, 205, 7, 6); mod_radio_reg(pi, 217, 7, 6); if ((int )pi->nphy_gain_boost) { and_radio_reg(pi, 102, 65533); and_radio_reg(pi, 149, 65533); } else { or_radio_reg(pi, 102, 2); or_radio_reg(pi, 149, 2); } __const_udelay(8590UL); return; } } void wlc_phy_switch_radio_nphy(struct brcms_phy *pi , bool on ) { { if ((int )on) { if (pi->pubpi.phy_rev > 6U) { if (! pi->radio_is_on) { wlc_phy_radio_preinit_205x(pi); wlc_phy_radio_init_2057(pi); wlc_phy_radio_postinit_2057(pi); } else { } wlc_phy_chanspec_set((struct brcms_phy_pub *)pi, (int )pi->radio_chanspec); } else if (pi->pubpi.phy_rev > 2U) { wlc_phy_radio_preinit_205x(pi); wlc_phy_radio_init_2056(pi); wlc_phy_radio_postinit_2056(pi); wlc_phy_chanspec_set((struct brcms_phy_pub *)pi, (int )pi->radio_chanspec); } else { wlc_phy_radio_preinit_2055(pi); wlc_phy_radio_init_2055(pi); wlc_phy_radio_postinit_2055(pi); } pi->radio_is_on = 1; } else { if (pi->pubpi.phy_rev > 2U && pi->pubpi.phy_rev <= 6U) { and_phy_reg(pi, 120, 64511); mod_radio_reg(pi, 9, 2, 0); write_radio_reg(pi, 8269, 0); write_radio_reg(pi, 8275, 0); write_radio_reg(pi, 8280, 0); write_radio_reg(pi, 8286, 0); mod_radio_reg(pi, 8290, 240, 0); write_radio_reg(pi, 8292, 0); write_radio_reg(pi, 12365, 0); write_radio_reg(pi, 12371, 0); write_radio_reg(pi, 12376, 0); write_radio_reg(pi, 12382, 0); mod_radio_reg(pi, 12386, 240, 0); write_radio_reg(pi, 12388, 0); pi->radio_is_on = 0; } else { } if (pi->pubpi.phy_rev > 7U) { and_phy_reg(pi, 120, 64511); pi->radio_is_on = 0; } else { } } return; } } static bool wlc_phy_chan2freq_nphy(struct brcms_phy *pi , uint channel , int *f , struct chan_info_nphy_radio2057 const **t0 , struct chan_info_nphy_radio205x const **t1 , struct chan_info_nphy_radio2057_rev5 const **t2 , struct chan_info_nphy_2055 const **t3 ) { uint i ; struct chan_info_nphy_radio2057 const *chan_info_tbl_p_0 ; struct chan_info_nphy_radio205x const *chan_info_tbl_p_1 ; struct chan_info_nphy_radio2057_rev5 const *chan_info_tbl_p_2 ; u32 tbl_len ; int freq ; { chan_info_tbl_p_0 = (struct chan_info_nphy_radio2057 const *)0; chan_info_tbl_p_1 = (struct chan_info_nphy_radio205x const *)0; chan_info_tbl_p_2 = (struct chan_info_nphy_radio2057_rev5 const *)0; tbl_len = 0U; freq = 0; if (pi->pubpi.phy_rev > 6U) { if (pi->pubpi.phy_rev == 7U) { chan_info_tbl_p_0 = (struct chan_info_nphy_radio2057 const *)(& chan_info_nphyrev7_2057_rev4); tbl_len = 123U; } else if (pi->pubpi.phy_rev == 8U) { switch ((int )pi->pubpi.radiorev) { case 5: ; if ((unsigned int )pi->pubpi.radiover == 0U) { chan_info_tbl_p_2 = (struct chan_info_nphy_radio2057_rev5 const *)(& chan_info_nphyrev8_2057_rev5); tbl_len = 14U; } else if ((unsigned int )pi->pubpi.radiover == 1U) { chan_info_tbl_p_2 = (struct chan_info_nphy_radio2057_rev5 const *)(& chan_info_nphyrev9_2057_rev5v1); tbl_len = 14U; } else { } goto ldv_38584; case 7: chan_info_tbl_p_0 = (struct chan_info_nphy_radio2057 const *)(& chan_info_nphyrev8_2057_rev7); tbl_len = 123U; goto ldv_38584; case 8: chan_info_tbl_p_0 = (struct chan_info_nphy_radio2057 const *)(& chan_info_nphyrev8_2057_rev8); tbl_len = 122U; goto ldv_38584; default: ; goto ldv_38584; } ldv_38584: ; } else { goto fail; } i = 0U; goto ldv_38597; ldv_38596: ; if ((unsigned int )pi->pubpi.radiorev == 5U) { if ((uint )(chan_info_tbl_p_2 + (unsigned long )i)->chan == channel) { goto ldv_38595; } else { } } else if ((uint )(chan_info_tbl_p_0 + (unsigned long )i)->chan == channel) { goto ldv_38595; } else { } i = i + 1U; ldv_38597: ; if (i < tbl_len) { goto ldv_38596; } else { } ldv_38595: ; if (i >= tbl_len) { goto fail; } else { } if ((unsigned int )pi->pubpi.radiorev == 5U) { *t2 = chan_info_tbl_p_2 + (unsigned long )i; freq = (int )(chan_info_tbl_p_2 + (unsigned long )i)->freq; } else { *t0 = chan_info_tbl_p_0 + (unsigned long )i; freq = (int )(chan_info_tbl_p_0 + (unsigned long )i)->freq; } } else if (pi->pubpi.phy_rev > 2U) { if (pi->pubpi.phy_rev == 3U) { chan_info_tbl_p_1 = (struct chan_info_nphy_radio205x const *)(& chan_info_nphyrev3_2056); tbl_len = 124U; } else if (pi->pubpi.phy_rev == 4U) { chan_info_tbl_p_1 = (struct chan_info_nphy_radio205x const *)(& chan_info_nphyrev4_2056_A1); tbl_len = 124U; } else if (pi->pubpi.phy_rev == 5U || pi->pubpi.phy_rev == 6U) { switch ((int )pi->pubpi.radiorev) { case 5: chan_info_tbl_p_1 = (struct chan_info_nphy_radio205x const *)(& chan_info_nphyrev5_2056v5); tbl_len = 124U; goto ldv_38605; case 6: chan_info_tbl_p_1 = (struct chan_info_nphy_radio205x const *)(& chan_info_nphyrev6_2056v6); tbl_len = 124U; goto ldv_38605; case 7: ; case 9: chan_info_tbl_p_1 = (struct chan_info_nphy_radio205x const *)(& chan_info_nphyrev5n6_2056v7); tbl_len = 124U; goto ldv_38605; case 8: chan_info_tbl_p_1 = (struct chan_info_nphy_radio205x const *)(& chan_info_nphyrev6_2056v8); tbl_len = 124U; goto ldv_38605; case 11: chan_info_tbl_p_1 = (struct chan_info_nphy_radio205x const *)(& chan_info_nphyrev6_2056v11); tbl_len = 124U; goto ldv_38605; default: ; goto ldv_38605; } ldv_38605: ; } else { } i = 0U; goto ldv_38622; ldv_38621: ; if ((uint )(chan_info_tbl_p_1 + (unsigned long )i)->chan == channel) { goto ldv_38620; } else { } i = i + 1U; ldv_38622: ; if (i < tbl_len) { goto ldv_38621; } else { } ldv_38620: ; if (i >= tbl_len) { goto fail; } else { } *t1 = chan_info_tbl_p_1 + (unsigned long )i; freq = (int )(chan_info_tbl_p_1 + (unsigned long )i)->freq; } else { i = 0U; goto ldv_38627; ldv_38626: ; if ((uint )chan_info_nphy_2055[i].chan == channel) { goto ldv_38625; } else { } i = i + 1U; ldv_38627: ; if (i <= 123U) { goto ldv_38626; } else { } ldv_38625: ; if (i > 123U) { goto fail; } else { } *t3 = (struct chan_info_nphy_2055 const *)(& chan_info_nphy_2055) + (unsigned long )i; freq = (int )chan_info_nphy_2055[i].freq; } *f = freq; return (1); fail: *f = 0; return (0); } } u8 wlc_phy_get_chan_freq_range_nphy(struct brcms_phy *pi , uint channel ) { int freq ; struct chan_info_nphy_radio2057 const *t0 ; struct chan_info_nphy_radio205x const *t1 ; struct chan_info_nphy_radio2057_rev5 const *t2 ; struct chan_info_nphy_2055 const *t3 ; { t0 = (struct chan_info_nphy_radio2057 const *)0; t1 = (struct chan_info_nphy_radio205x const *)0; t2 = (struct chan_info_nphy_radio2057_rev5 const *)0; t3 = (struct chan_info_nphy_2055 const *)0; if (channel == 0U) { channel = (uint )((unsigned char )pi->radio_chanspec); } else { } wlc_phy_chan2freq_nphy(pi, channel, & freq, & t0, & t1, & t2, & t3); if (((int )pi->radio_chanspec & 61440) == 8192) { return (0U); } else { } if (freq > 4899 && freq <= 5099) { return (1U); } else if (freq > 5099 && freq <= 5499) { return (2U); } else { return (3U); } } } static void wlc_phy_chanspec_radio2055_setup(struct brcms_phy *pi , struct chan_info_nphy_2055 const *ci ) { { write_radio_reg(pi, 53, (int )ci->RF_pll_ref); write_radio_reg(pi, 59, (int )ci->RF_rf_pll_mod0); write_radio_reg(pi, 60, (int )ci->RF_rf_pll_mod1); write_radio_reg(pi, 81, (int )ci->RF_vco_cap_tail); if (pi->pubpi.phy_rev <= 2U) { bcma_read32(pi->d11core, 288); } else { } write_radio_reg(pi, 64, (int )ci->RF_vco_cal1); write_radio_reg(pi, 65, (int )ci->RF_vco_cal2); write_radio_reg(pi, 50, (int )ci->RF_pll_lf_c1); write_radio_reg(pi, 54, (int )ci->RF_pll_lf_r1); if (pi->pubpi.phy_rev <= 2U) { bcma_read32(pi->d11core, 288); } else { } write_radio_reg(pi, 52, (int )ci->RF_pll_lf_c2); write_radio_reg(pi, 85, (int )ci->RF_lgbuf_cen_buf); write_radio_reg(pi, 86, (int )ci->RF_lgen_tune1); write_radio_reg(pi, 87, (int )ci->RF_lgen_tune2); if (pi->pubpi.phy_rev <= 2U) { bcma_read32(pi->d11core, 288); } else { } write_radio_reg(pi, 95, (int )ci->RF_core1_lgbuf_a_tune); write_radio_reg(pi, 96, (int )ci->RF_core1_lgbuf_g_tune); write_radio_reg(pi, 103, (int )ci->RF_core1_rxrf_reg1); write_radio_reg(pi, 127, (int )ci->RF_core1_tx_pga_pad_tn); if (pi->pubpi.phy_rev <= 2U) { bcma_read32(pi->d11core, 288); } else { } write_radio_reg(pi, 130, (int )ci->RF_core1_tx_mx_bgtrim); write_radio_reg(pi, 142, (int )ci->RF_core2_lgbuf_a_tune); write_radio_reg(pi, 143, (int )ci->RF_core2_lgbuf_g_tune); write_radio_reg(pi, 150, (int )ci->RF_core2_rxrf_reg1); if (pi->pubpi.phy_rev <= 2U) { bcma_read32(pi->d11core, 288); } else { } write_radio_reg(pi, 174, (int )ci->RF_core2_tx_pga_pad_tn); write_radio_reg(pi, 177, (int )ci->RF_core2_tx_mx_bgtrim); __const_udelay(214750UL); write_radio_reg(pi, 73, 5); write_radio_reg(pi, 73, 69); if (pi->pubpi.phy_rev <= 2U) { bcma_read32(pi->d11core, 288); } else { } write_radio_reg(pi, 73, 101); __const_udelay(1288500UL); return; } } static void wlc_phy_chanspec_radio2056_setup(struct brcms_phy *pi , struct chan_info_nphy_radio205x const *ci ) { struct radio_regs const *regs_SYN_2056_ptr ; u16 pag_boost_tune ; u16 padg_boost_tune ; u16 pgag_boost_tune ; u16 mixg_boost_tune ; u16 bias ; u16 cascbias ; uint core ; u16 paa_boost_tune ; u16 pada_boost_tune ; u16 pgaa_boost_tune ; u16 mixa_boost_tune ; u16 freq ; u16 pabias ; u16 cascbias___0 ; uint core___0 ; { regs_SYN_2056_ptr = (struct radio_regs const *)0; write_radio_reg(pi, 86, (int )ci->RF_SYN_pll_vcocal1); write_radio_reg(pi, 87, (int )ci->RF_SYN_pll_vcocal2); write_radio_reg(pi, 70, (int )ci->RF_SYN_pll_refdiv); write_radio_reg(pi, 81, (int )ci->RF_SYN_pll_mmd2); write_radio_reg(pi, 80, (int )ci->RF_SYN_pll_mmd1); write_radio_reg(pi, 75, (int )ci->RF_SYN_pll_loopfilter1); write_radio_reg(pi, 76, (int )ci->RF_SYN_pll_loopfilter2); write_radio_reg(pi, 77, (int )ci->RF_SYN_pll_loopfilter3); write_radio_reg(pi, 78, (int )ci->RF_SYN_pll_loopfilter4); write_radio_reg(pi, 79, (int )ci->RF_SYN_pll_loopfilter5); write_radio_reg(pi, 27, (int )ci->RF_SYN_reserved_addr27); write_radio_reg(pi, 28, (int )ci->RF_SYN_reserved_addr28); write_radio_reg(pi, 29, (int )ci->RF_SYN_reserved_addr29); write_radio_reg(pi, 112, (int )ci->RF_SYN_logen_VCOBUF1); write_radio_reg(pi, 114, (int )ci->RF_SYN_logen_MIXER2); write_radio_reg(pi, 117, (int )ci->RF_SYN_logen_BUF3); write_radio_reg(pi, 118, (int )ci->RF_SYN_logen_BUF4); write_radio_reg(pi, 24621, (int )ci->RF_RX0_lnaa_tune); write_radio_reg(pi, 24628, (int )ci->RF_RX0_lnag_tune); write_radio_reg(pi, 8247, (int )ci->RF_TX0_intpaa_boost_tune); write_radio_reg(pi, 8257, (int )ci->RF_TX0_intpag_boost_tune); write_radio_reg(pi, 8269, (int )ci->RF_TX0_pada_boost_tune); write_radio_reg(pi, 8275, (int )ci->RF_TX0_padg_boost_tune); write_radio_reg(pi, 8280, (int )ci->RF_TX0_pgaa_boost_tune); write_radio_reg(pi, 8286, (int )ci->RF_TX0_pgag_boost_tune); write_radio_reg(pi, 8290, (int )ci->RF_TX0_mixa_boost_tune); write_radio_reg(pi, 8292, (int )ci->RF_TX0_mixg_boost_tune); write_radio_reg(pi, 28717, (int )ci->RF_RX1_lnaa_tune); write_radio_reg(pi, 28724, (int )ci->RF_RX1_lnag_tune); write_radio_reg(pi, 12343, (int )ci->RF_TX1_intpaa_boost_tune); write_radio_reg(pi, 12353, (int )ci->RF_TX1_intpag_boost_tune); write_radio_reg(pi, 12365, (int )ci->RF_TX1_pada_boost_tune); write_radio_reg(pi, 12371, (int )ci->RF_TX1_padg_boost_tune); write_radio_reg(pi, 12376, (int )ci->RF_TX1_pgaa_boost_tune); write_radio_reg(pi, 12382, (int )ci->RF_TX1_pgag_boost_tune); write_radio_reg(pi, 12386, (int )ci->RF_TX1_mixa_boost_tune); write_radio_reg(pi, 12388, (int )ci->RF_TX1_mixg_boost_tune); if (pi->pubpi.phy_rev == 3U) { regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056); } else if (pi->pubpi.phy_rev == 4U) { regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_A1); } else { switch ((int )pi->pubpi.radiorev) { case 5: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev5); goto ldv_38649; case 6: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev6); goto ldv_38649; case 7: ; case 9: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev7); goto ldv_38649; case 8: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev8); goto ldv_38649; case 11: regs_SYN_2056_ptr = (struct radio_regs const *)(& regs_SYN_2056_rev11); goto ldv_38649; } ldv_38649: ; } if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, 73, (int )((unsigned short )(regs_SYN_2056_ptr + 71UL)->init_g)); } else { write_radio_reg(pi, 73, (int )((unsigned short )(regs_SYN_2056_ptr + 71UL)->init_a)); } if (((pi->sh)->boardflags2 & 1024U) != 0U) { if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, 75, 31); write_radio_reg(pi, 76, 31); if ((pi->sh)->chip == 18198U || (pi->sh)->chip == 47162U) { write_radio_reg(pi, 78, 20); write_radio_reg(pi, 73, 0); } else { write_radio_reg(pi, 78, 11); write_radio_reg(pi, 73, 20); } } else { } } else { } if (((pi->sh)->boardflags2 & 65536U) != 0U && ((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, 75, 31); write_radio_reg(pi, 76, 31); write_radio_reg(pi, 78, 11); write_radio_reg(pi, 73, 32); } else { } if (((pi->sh)->boardflags2 & 2U) != 0U) { if (((int )pi->radio_chanspec & 61440) == 4096) { write_radio_reg(pi, 75, 31); write_radio_reg(pi, 76, 31); write_radio_reg(pi, 78, 5); write_radio_reg(pi, 73, 12); } else { } } else { } if ((((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) && ((int )pi->radio_chanspec & 61440) == 8192) { core = 0U; goto ldv_38663; ldv_38662: ; if (pi->pubpi.phy_rev > 4U) { write_radio_reg(pi, core == 0U ? 8272 : 12368, 204); if ((pi->sh)->chip == 18198U || (pi->sh)->chip == 47162U) { bias = 64U; cascbias = 69U; pag_boost_tune = 5U; pgag_boost_tune = 51U; padg_boost_tune = 119U; mixg_boost_tune = 85U; } else { bias = 37U; cascbias = 32U; if (((pi->sh)->chip == 43224U || (pi->sh)->chip == 43225U) && (pi->sh)->chippkg == 10U) { bias = 42U; cascbias = 56U; } else { } pag_boost_tune = 4U; pgag_boost_tune = 3U; padg_boost_tune = 119U; mixg_boost_tune = 101U; } write_radio_reg(pi, core == 0U ? 8260 : 12356, (int )bias); write_radio_reg(pi, core == 0U ? 8258 : 12354, (int )bias); write_radio_reg(pi, core == 0U ? 8262 : 12358, (int )cascbias); write_radio_reg(pi, core == 0U ? 8257 : 12353, (int )pag_boost_tune); write_radio_reg(pi, core == 0U ? 8286 : 12382, (int )pgag_boost_tune); write_radio_reg(pi, core == 0U ? 8275 : 12371, (int )padg_boost_tune); write_radio_reg(pi, core == 0U ? 8292 : 12388, (int )mixg_boost_tune); } else { bias = (unsigned int )pi->bw == 3072U ? 64U : 32U; write_radio_reg(pi, core == 0U ? 8260 : 12356, (int )bias); write_radio_reg(pi, core == 0U ? 8258 : 12354, (int )bias); write_radio_reg(pi, core == 0U ? 8262 : 12358, 48); } write_radio_reg(pi, core == 0U ? 8243 : 12339, 238); core = core + 1U; ldv_38663: ; if ((uint )pi->pubpi.phy_corenum > core) { goto ldv_38662; } else { } } else { } if (((((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) && pi->pubpi.phy_rev == 6U) && ((int )pi->radio_chanspec & 61440) == 4096) { freq = (unsigned int )((u16 )((unsigned char )pi->radio_chanspec)) * 5U + 5000U; if ((unsigned int )freq <= 5149U) { paa_boost_tune = 10U; pada_boost_tune = 119U; pgaa_boost_tune = 15U; mixa_boost_tune = 15U; } else if ((unsigned int )freq <= 5339U) { paa_boost_tune = 8U; pada_boost_tune = 119U; pgaa_boost_tune = 251U; mixa_boost_tune = 15U; } else if ((unsigned int )freq <= 5649U) { paa_boost_tune = 0U; pada_boost_tune = 119U; pgaa_boost_tune = 11U; mixa_boost_tune = 15U; } else { paa_boost_tune = 0U; pada_boost_tune = 119U; if ((unsigned int )freq != 5825U) { pgaa_boost_tune = (unsigned int )((u16 )((18 - (int )freq) / 36)) + 168U; } else { pgaa_boost_tune = 6U; } mixa_boost_tune = 15U; } core___0 = 0U; goto ldv_38674; ldv_38673: write_radio_reg(pi, core___0 == 0U ? 8247 : 12343, (int )paa_boost_tune); write_radio_reg(pi, core___0 == 0U ? 8269 : 12365, (int )pada_boost_tune); write_radio_reg(pi, core___0 == 0U ? 8280 : 12376, (int )pgaa_boost_tune); write_radio_reg(pi, core___0 == 0U ? 8290 : 12386, (int )mixa_boost_tune); write_radio_reg(pi, core___0 == 0U ? 8317 : 12413, 48); write_radio_reg(pi, core___0 == 0U ? 8244 : 12340, 238); write_radio_reg(pi, core___0 == 0U ? 8267 : 12363, 3); cascbias___0 = 48U; if (((pi->sh)->chip == 43224U || (pi->sh)->chip == 43225U) && (pi->sh)->chippkg == 10U) { cascbias___0 = 53U; } else { } pabias = (unsigned int )pi->phy_pabias != 0U ? (u16 )pi->phy_pabias : 48U; write_radio_reg(pi, core___0 == 0U ? 8248 : 12344, (int )pabias); write_radio_reg(pi, core___0 == 0U ? 8250 : 12346, (int )pabias); write_radio_reg(pi, core___0 == 0U ? 8252 : 12348, (int )cascbias___0); core___0 = core___0 + 1U; ldv_38674: ; if ((uint )pi->pubpi.phy_corenum > core___0) { goto ldv_38673; } else { } } else { } __const_udelay(214750UL); wlc_phy_radio205x_vcocal_nphy(pi); return; } } void wlc_phy_radio205x_vcocal_nphy(struct brcms_phy *pi ) { { if (pi->pubpi.phy_rev > 6U) { mod_radio_reg(pi, 43, 1, 0); mod_radio_reg(pi, 46, 4, 0); mod_radio_reg(pi, 46, 4, 4); mod_radio_reg(pi, 43, 1, 1); } else if (pi->pubpi.phy_rev > 2U) { write_radio_reg(pi, 96, 0); write_radio_reg(pi, 62, 56); write_radio_reg(pi, 62, 24); write_radio_reg(pi, 62, 56); write_radio_reg(pi, 62, 57); } else { } __const_udelay(1288500UL); return; } } static void wlc_phy_chanspec_radio2057_setup(struct brcms_phy *pi , struct chan_info_nphy_radio2057 const *ci , struct chan_info_nphy_radio2057_rev5 const *ci2 ) { int coreNum ; u16 txmix2g_tune_boost_pu ; u16 pad2g_tune_pus ; { txmix2g_tune_boost_pu = 0U; pad2g_tune_pus = 0U; if ((unsigned int )pi->pubpi.radiorev == 5U) { write_radio_reg(pi, 22, (int )ci2->RF_vcocal_countval0); write_radio_reg(pi, 23, (int )ci2->RF_vcocal_countval1); write_radio_reg(pi, 34, (int )ci2->RF_rfpll_refmaster_sparextalsize); write_radio_reg(pi, 37, (int )ci2->RF_rfpll_loopfilter_r1); write_radio_reg(pi, 39, (int )ci2->RF_rfpll_loopfilter_c2); write_radio_reg(pi, 40, (int )ci2->RF_rfpll_loopfilter_c1); write_radio_reg(pi, 41, (int )ci2->RF_cp_kpd_idac); write_radio_reg(pi, 44, (int )ci2->RF_rfpll_mmd0); write_radio_reg(pi, 45, (int )ci2->RF_rfpll_mmd1); write_radio_reg(pi, 55, (int )ci2->RF_vcobuf_tune); write_radio_reg(pi, 65, (int )ci2->RF_logen_mx2g_tune); write_radio_reg(pi, 71, (int )ci2->RF_logen_indbuf2g_tune); write_radio_reg(pi, 92, (int )ci2->RF_txmix2g_tune_boost_pu_core0); write_radio_reg(pi, 94, (int )ci2->RF_pad2g_tune_pus_core0); write_radio_reg(pi, 154, (int )ci2->RF_lna2g_tune_core0); write_radio_reg(pi, 225, (int )ci2->RF_txmix2g_tune_boost_pu_core1); write_radio_reg(pi, 227, (int )ci2->RF_pad2g_tune_pus_core1); write_radio_reg(pi, 287, (int )ci2->RF_lna2g_tune_core1); } else { write_radio_reg(pi, 22, (int )ci->RF_vcocal_countval0); write_radio_reg(pi, 23, (int )ci->RF_vcocal_countval1); write_radio_reg(pi, 34, (int )ci->RF_rfpll_refmaster_sparextalsize); write_radio_reg(pi, 37, (int )ci->RF_rfpll_loopfilter_r1); write_radio_reg(pi, 39, (int )ci->RF_rfpll_loopfilter_c2); write_radio_reg(pi, 40, (int )ci->RF_rfpll_loopfilter_c1); write_radio_reg(pi, 41, (int )ci->RF_cp_kpd_idac); write_radio_reg(pi, 44, (int )ci->RF_rfpll_mmd0); write_radio_reg(pi, 45, (int )ci->RF_rfpll_mmd1); write_radio_reg(pi, 55, (int )ci->RF_vcobuf_tune); write_radio_reg(pi, 65, (int )ci->RF_logen_mx2g_tune); write_radio_reg(pi, 67, (int )ci->RF_logen_mx5g_tune); write_radio_reg(pi, 71, (int )ci->RF_logen_indbuf2g_tune); write_radio_reg(pi, 74, (int )ci->RF_logen_indbuf5g_tune); write_radio_reg(pi, 92, (int )ci->RF_txmix2g_tune_boost_pu_core0); write_radio_reg(pi, 94, (int )ci->RF_pad2g_tune_pus_core0); write_radio_reg(pi, 112, (int )ci->RF_pga_boost_tune_core0); write_radio_reg(pi, 115, (int )ci->RF_txmix5g_boost_tune_core0); write_radio_reg(pi, 116, (int )ci->RF_pad5g_tune_misc_pus_core0); write_radio_reg(pi, 154, (int )ci->RF_lna2g_tune_core0); write_radio_reg(pi, 160, (int )ci->RF_lna5g_tune_core0); write_radio_reg(pi, 225, (int )ci->RF_txmix2g_tune_boost_pu_core1); write_radio_reg(pi, 227, (int )ci->RF_pad2g_tune_pus_core1); write_radio_reg(pi, 245, (int )ci->RF_pga_boost_tune_core1); write_radio_reg(pi, 248, (int )ci->RF_txmix5g_boost_tune_core1); write_radio_reg(pi, 249, (int )ci->RF_pad5g_tune_misc_pus_core1); write_radio_reg(pi, 287, (int )ci->RF_lna2g_tune_core1); write_radio_reg(pi, 293, (int )ci->RF_lna5g_tune_core1); } if ((unsigned int )pi->pubpi.radiorev <= 4U || (unsigned int )pi->pubpi.radiorev == 6U) { if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, 37, 63); write_radio_reg(pi, 41, 63); write_radio_reg(pi, 40, 8); write_radio_reg(pi, 39, 8); } else { write_radio_reg(pi, 37, 31); write_radio_reg(pi, 41, 63); write_radio_reg(pi, 40, 8); write_radio_reg(pi, 39, 8); } } else if (((unsigned int )pi->pubpi.radiorev == 5U || (unsigned int )pi->pubpi.radiorev == 7U) || (unsigned int )pi->pubpi.radiorev == 8U) { if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, 37, 27); write_radio_reg(pi, 41, 48); write_radio_reg(pi, 40, 10); write_radio_reg(pi, 39, 10); } else { write_radio_reg(pi, 37, 31); write_radio_reg(pi, 41, 63); write_radio_reg(pi, 40, 8); write_radio_reg(pi, 39, 8); } } else { } if (((int )pi->radio_chanspec & 61440) == 8192) { if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if ((unsigned int )pi->pubpi.radiorev == 3U) { txmix2g_tune_boost_pu = 107U; } else { } if ((unsigned int )pi->pubpi.radiorev == 5U) { pad2g_tune_pus = 115U; } else { } } else if ((unsigned int )pi->pubpi.radiorev != 5U) { pad2g_tune_pus = 3U; txmix2g_tune_boost_pu = 97U; } else { } coreNum = 0; goto ldv_38688; ldv_38687: ; if ((unsigned int )txmix2g_tune_boost_pu != 0U) { write_radio_reg(pi, coreNum == 0 ? 92 : 225, (int )txmix2g_tune_boost_pu); } else { } if ((unsigned int )pad2g_tune_pus != 0U) { write_radio_reg(pi, coreNum == 0 ? 94 : 227, (int )pad2g_tune_pus); } else { } coreNum = coreNum + 1; ldv_38688: ; if (coreNum <= 1) { goto ldv_38687; } else { } } else { } __const_udelay(214750UL); wlc_phy_radio205x_vcocal_nphy(pi); return; } } static void wlc_phy_chanspec_nphy_setup(struct brcms_phy *pi , u16 chanspec , struct nphy_sfo_cfg const *ci ) { u16 val ; u16 tmp ; u32 tmp___0 ; u32 tmp___1 ; u8 spuravoid ; { tmp = read_phy_reg(pi, 9); val = (unsigned int )tmp & 1U; if (((int )chanspec & 61440) == 4096 && (unsigned int )val == 0U) { tmp___0 = bcma_read16(pi->d11core, 1170); val = (u16 )tmp___0; bcma_write16(pi->d11core, 1170, (unsigned int )val | 4U); or_phy_reg(pi, 3073, 49152); bcma_write16(pi->d11core, 1170, (u32 )val); or_phy_reg(pi, 9, 1); } else if (((int )chanspec & 61440) != 4096 && (unsigned int )val != 0U) { and_phy_reg(pi, 9, 65534); tmp___1 = bcma_read16(pi->d11core, 1170); val = (u16 )tmp___1; bcma_write16(pi->d11core, 1170, (unsigned int )val | 4U); and_phy_reg(pi, 3073, 16383); bcma_write16(pi->d11core, 1170, (u32 )val); } else { } write_phy_reg(pi, 462, (int )ci->PHY_BW1a); write_phy_reg(pi, 463, (int )ci->PHY_BW2); write_phy_reg(pi, 464, (int )ci->PHY_BW3); write_phy_reg(pi, 465, (int )ci->PHY_BW4); write_phy_reg(pi, 466, (int )ci->PHY_BW5); write_phy_reg(pi, 467, (int )ci->PHY_BW6); if ((unsigned int )((unsigned char )pi->radio_chanspec) == 14U) { wlc_phy_classifier_nphy(pi, 2, 0); or_phy_reg(pi, 3082, 2048); } else { wlc_phy_classifier_nphy(pi, 2, 2); if (((int )chanspec & 61440) == 8192) { and_phy_reg(pi, 3082, 63423); } else { } } if ((unsigned int )pi->nphy_txpwrctrl == 0U) { wlc_phy_txpwr_fixpower_nphy(pi); } else { } if (pi->pubpi.phy_rev <= 2U) { wlc_phy_adjust_lnagaintbl_nphy(pi); } else { } wlc_phy_txlpfbw_nphy(pi); if (pi->pubpi.phy_rev > 2U && (unsigned int )pi->phy_spuravoid != 0U) { spuravoid = 0U; val = (u16 )((unsigned char )chanspec); if (((int )pi->radio_chanspec & 3072) != 3072) { if (pi->pubpi.phy_rev > 6U) { if (((unsigned int )val == 13U || (unsigned int )val == 14U) || (unsigned int )val == 153U) { spuravoid = 1U; } else { } } else if ((((unsigned int )val > 4U && (unsigned int )val <= 8U) || (unsigned int )val == 13U) || (unsigned int )val == 14U) { spuravoid = 1U; } else { } } else if (pi->pubpi.phy_rev > 6U) { if ((unsigned int )val == 54U) { spuravoid = 1U; } else { } } else if ((int )pi->nphy_aband_spurwar_en && (((unsigned int )val == 38U || (unsigned int )val == 102U) || (unsigned int )val == 118U)) { if ((pi->sh)->chip == 18198U && (pi->sh)->chippkg == 9U) { spuravoid = 0U; } else { spuravoid = 1U; } } else { } if ((unsigned int )pi->phy_spuravoid == 2U) { spuravoid = 1U; } else { } if ((pi->sh)->chip == 18198U || (pi->sh)->chip == 43225U) { bcma_pmu_spuravoid_pllupdate(& ((pi->d11core)->bus)->drv_cc, (int )spuravoid); } else { wlapi_bmac_core_phypll_ctl((pi->sh)->physhim, 0); bcma_pmu_spuravoid_pllupdate(& ((pi->d11core)->bus)->drv_cc, (int )spuravoid); wlapi_bmac_core_phypll_ctl((pi->sh)->physhim, 1); } if ((pi->sh)->chip == 43224U || (pi->sh)->chip == 43225U) { if ((unsigned int )spuravoid == 1U) { bcma_write16(pi->d11core, 1582, 21313U); bcma_write16(pi->d11core, 1584, 8U); } else { bcma_write16(pi->d11core, 1582, 34953U); bcma_write16(pi->d11core, 1584, 8U); } } else { } if ((pi->sh)->chip != 18198U && (pi->sh)->chip != 47162U) { wlapi_bmac_core_phypll_reset((pi->sh)->physhim); } else { } mod_phy_reg(pi, 1, 32768, (unsigned int )spuravoid != 0U ? 32768 : 0); wlc_phy_resetcca_nphy(pi); pi->phy_isspuravoid = (unsigned int )spuravoid != 0U; } else { } if (pi->pubpi.phy_rev <= 6U) { write_phy_reg(pi, 382, 14384); } else { } wlc_phy_spurwar_nphy(pi); return; } } void wlc_phy_chanspec_set_nphy(struct brcms_phy *pi , u16 chanspec ) { int freq ; struct chan_info_nphy_radio2057 const *t0 ; struct chan_info_nphy_radio205x const *t1 ; struct chan_info_nphy_radio2057_rev5 const *t2 ; struct chan_info_nphy_2055 const *t3 ; bool tmp ; int tmp___0 ; { t0 = (struct chan_info_nphy_radio2057 const *)0; t1 = (struct chan_info_nphy_radio205x const *)0; t2 = (struct chan_info_nphy_radio2057_rev5 const *)0; t3 = (struct chan_info_nphy_2055 const *)0; tmp = wlc_phy_chan2freq_nphy(pi, (uint )((unsigned char )chanspec), & freq, & t0, & t1, & t2, & t3); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return; } else { } wlc_phy_chanspec_radio_set((struct brcms_phy_pub *)pi, (int )chanspec); if (((int )chanspec & 3072) != (int )pi->bw) { wlapi_bmac_bw_set((pi->sh)->physhim, (int )chanspec & 3072); } else { } if (((int )chanspec & 3072) == 3072) { if (((int )chanspec & 768) == 512) { or_phy_reg(pi, 160, 16); if (pi->pubpi.phy_rev > 6U) { or_phy_reg(pi, 784, 32768); } else { } } else { and_phy_reg(pi, 160, 65519); if (pi->pubpi.phy_rev > 6U) { and_phy_reg(pi, 784, 32767); } else { } } } else { } if (pi->pubpi.phy_rev > 2U) { if (pi->pubpi.phy_rev > 6U) { if ((unsigned int )pi->pubpi.radiorev <= 4U || (unsigned int )pi->pubpi.radiorev == 6U) { mod_radio_reg(pi, 143, 2, ((int )chanspec & 61440) == 4096 ? 2 : 0); mod_radio_reg(pi, 276, 2, ((int )chanspec & 61440) == 4096 ? 2 : 0); } else { } wlc_phy_chanspec_radio2057_setup(pi, t0, t2); wlc_phy_chanspec_nphy_setup(pi, (int )chanspec, (unsigned int )pi->pubpi.radiorev == 5U ? (struct nphy_sfo_cfg const *)(& t2->PHY_BW1a) : (struct nphy_sfo_cfg const *)(& t0->PHY_BW1a)); } else { mod_radio_reg(pi, 8, 4, ((int )chanspec & 61440) == 4096 ? 4 : 0); wlc_phy_chanspec_radio2056_setup(pi, t1); wlc_phy_chanspec_nphy_setup(pi, (int )chanspec, (struct nphy_sfo_cfg const *)(& t1->PHY_BW1a)); } } else { mod_radio_reg(pi, 17, 112, ((int )chanspec & 61440) == 4096 ? 32 : 80); wlc_phy_chanspec_radio2055_setup(pi, t3); wlc_phy_chanspec_nphy_setup(pi, (int )chanspec, (struct nphy_sfo_cfg const *)(& t3->PHY_BW1a)); } return; } } void wlc_phy_antsel_init(struct brcms_phy_pub *ppi , bool lut_init ) { struct brcms_phy *pi ; struct brcms_phy_pub const *__mptr ; u16 mask ; u32 mc ; u16 v0 ; u16 v1 ; u16 v2 ; u16 v3 ; { __mptr = (struct brcms_phy_pub const *)ppi; pi = (struct brcms_phy *)__mptr; mask = 64512U; mc = 0U; if (pi->pubpi.phy_rev > 6U) { return; } else { } if (pi->pubpi.phy_rev > 2U) { v0 = 529U; v1 = 546U; v2 = 324U; v3 = 392U; if (! lut_init) { return; } else { } if ((unsigned int )pi->srom_fem2g.antswctrllut == 0U) { wlc_phy_table_write_nphy(pi, 9U, 1U, 2U, 16U, (void const *)(& v0)); wlc_phy_table_write_nphy(pi, 9U, 1U, 3U, 16U, (void const *)(& v1)); wlc_phy_table_write_nphy(pi, 9U, 1U, 8U, 16U, (void const *)(& v2)); wlc_phy_table_write_nphy(pi, 9U, 1U, 12U, 16U, (void const *)(& v3)); } else { } if ((unsigned int )pi->srom_fem5g.antswctrllut == 0U) { wlc_phy_table_write_nphy(pi, 9U, 1U, 18U, 16U, (void const *)(& v0)); wlc_phy_table_write_nphy(pi, 9U, 1U, 19U, 16U, (void const *)(& v1)); wlc_phy_table_write_nphy(pi, 9U, 1U, 24U, 16U, (void const *)(& v2)); wlc_phy_table_write_nphy(pi, 9U, 1U, 28U, 16U, (void const *)(& v3)); } else { } } else { write_phy_reg(pi, 200, 0); write_phy_reg(pi, 201, 0); bcma_chipco_gpio_control(& ((pi->d11core)->bus)->drv_cc, (u32 )mask, (u32 )mask); mc = bcma_read32(pi->d11core, 288); mc = mc & 4294918143U; bcma_write32(pi->d11core, 288, mc); bcma_set16(pi->d11core, 1182, (int )mask); bcma_mask16(pi->d11core, 1180, ~ ((int )mask)); if ((int )lut_init) { write_phy_reg(pi, 248, 728); write_phy_reg(pi, 249, 769); write_phy_reg(pi, 250, 728); write_phy_reg(pi, 251, 769); } else { } } return; } } u16 wlc_phy_classifier_nphy(struct brcms_phy *pi , u16 mask , u16 val ) { u16 curr_ctl ; u16 new_ctl ; bool suspended ; u32 tmp ; u16 tmp___0 ; { suspended = 0; if ((pi->sh)->corerev == 16U) { tmp = bcma_read32(pi->d11core, 288); suspended = (int )tmp & 1 ? 0 : 1; if (! suspended) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } } else { } tmp___0 = read_phy_reg(pi, 176); curr_ctl = (unsigned int )tmp___0 & 7U; new_ctl = (u16 )((~ ((int )((short )mask)) & (int )((short )curr_ctl)) | (int )((short )((int )val & (int )mask))); mod_phy_reg(pi, 176, 7, (int )new_ctl); if ((pi->sh)->corerev == 16U && ! suspended) { wlapi_enable_mac((pi->sh)->physhim); } else { } return (new_ctl); } } void wlc_phy_force_rfseq_nphy(struct brcms_phy *pi , u8 cmd ) { u16 trigger_mask ; u16 status_mask ; u16 orig_RfseqCoreActv ; uint countdown ; u16 tmp ; int __ret_warn_on ; u16 tmp___0 ; long tmp___1 ; { switch ((int )cmd) { case 0: trigger_mask = 1U; status_mask = 1U; goto ldv_38735; case 1: trigger_mask = 2U; status_mask = 2U; goto ldv_38735; case 2: trigger_mask = 32U; status_mask = 32U; goto ldv_38735; case 3: trigger_mask = 4U; status_mask = 4U; goto ldv_38735; case 4: trigger_mask = 8U; status_mask = 8U; goto ldv_38735; case 5: trigger_mask = 16U; status_mask = 16U; goto ldv_38735; default: ; return; } ldv_38735: orig_RfseqCoreActv = read_phy_reg(pi, 161); or_phy_reg(pi, 161, 3); or_phy_reg(pi, 163, (int )trigger_mask); countdown = 200009U; goto ldv_38744; ldv_38743: __const_udelay(42950UL); countdown = countdown - 10U; ldv_38744: tmp = read_phy_reg(pi, 164); if ((unsigned int )((int )tmp & (int )status_mask) != 0U && countdown > 9U) { goto ldv_38743; } else { } write_phy_reg(pi, 161, (int )orig_RfseqCoreActv); tmp___0 = read_phy_reg(pi, 164); __ret_warn_on = (unsigned int )((int )tmp___0 & (int )status_mask) != 0U; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c", 21468, "HW error in rf"); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return; } } static void wlc_phy_rfctrl_override_1tomany_nphy(struct brcms_phy *pi , u16 cmd , u16 value , u8 core_mask , u8 off ) { u16 rfmxgain ; u16 lpfgain ; u16 tgain ; { rfmxgain = 0U; lpfgain = 0U; tgain = 0U; if (pi->pubpi.phy_rev > 6U) { switch ((int )cmd) { case 0: wlc_phy_rfctrl_override_nphy_rev7(pi, 32, (int )value, (int )core_mask, (int )off, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 16, (int )value, (int )core_mask, (int )off, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 8, (int )value, (int )core_mask, (int )off, 1); goto ldv_38759; case 1: wlc_phy_rfctrl_override_nphy_rev7(pi, 4, (int )value, (int )core_mask, (int )off, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 2, (int )value, (int )core_mask, (int )off, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1, (int )value, (int )core_mask, (int )off, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 2, (int )value, (int )core_mask, (int )off, 2); wlc_phy_rfctrl_override_nphy_rev7(pi, 2048, 0, (int )core_mask, (int )off, 1); goto ldv_38759; case 2: wlc_phy_rfctrl_override_nphy_rev7(pi, 4, (int )value, (int )core_mask, (int )off, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 2, (int )value, (int )core_mask, (int )off, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1, (int )value, (int )core_mask, (int )off, 2); wlc_phy_rfctrl_override_nphy_rev7(pi, 4, (int )value, (int )core_mask, (int )off, 2); wlc_phy_rfctrl_override_nphy_rev7(pi, 2048, 1, (int )core_mask, (int )off, 1); goto ldv_38759; case 3: rfmxgain = (unsigned int )value & 255U; lpfgain = (unsigned int )value & 65280U; lpfgain = (u16 )((int )lpfgain >> 8); wlc_phy_rfctrl_override_nphy_rev7(pi, 2048, (int )rfmxgain, (int )core_mask, (int )off, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 24576, (int )lpfgain, (int )core_mask, (int )off, 0); goto ldv_38759; case 4: tgain = (unsigned int )value & 32767U; lpfgain = (unsigned int )value & 32768U; lpfgain = (u16 )((int )lpfgain >> 14); wlc_phy_rfctrl_override_nphy_rev7(pi, 4096, (int )tgain, (int )core_mask, (int )off, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 8192, (int )lpfgain, (int )core_mask, (int )off, 0); goto ldv_38759; } ldv_38759: ; } else { } return; } } static void wlc_phy_scale_offset_rssi_nphy(struct brcms_phy *pi , u16 scale , s8 offset , u8 coresel , u8 rail , u8 rssi_type ) { u16 valuetostuff ; { offset = (s8 )(31 < (int )offset ? 31 : offset); offset = (s8 )(-32 > (int )offset ? -32 : offset); valuetostuff = (u16 )((int )((short )(((int )scale & 63) << 8)) | ((int )((short )offset) & 63)); if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 2U) { write_phy_reg(pi, 422, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 2U) { write_phy_reg(pi, 428, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 2U) { write_phy_reg(pi, 434, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 2U) { write_phy_reg(pi, 440, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 0U) { write_phy_reg(pi, 420, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 0U) { write_phy_reg(pi, 426, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 0U) { write_phy_reg(pi, 432, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 0U) { write_phy_reg(pi, 438, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 1U) { write_phy_reg(pi, 421, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 1U) { write_phy_reg(pi, 427, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 1U) { write_phy_reg(pi, 433, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 1U) { write_phy_reg(pi, 439, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 6U) { write_phy_reg(pi, 423, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 6U) { write_phy_reg(pi, 429, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 6U) { write_phy_reg(pi, 435, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 6U) { write_phy_reg(pi, 441, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 3U) { write_phy_reg(pi, 424, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 3U) { write_phy_reg(pi, 430, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 0U) && (unsigned int )rssi_type == 3U) { write_phy_reg(pi, 436, (int )valuetostuff); } else { } if ((((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rail == 1U) && (unsigned int )rssi_type == 3U) { write_phy_reg(pi, 442, (int )valuetostuff); } else { } if (((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rssi_type == 4U) { write_phy_reg(pi, 425, (int )valuetostuff); } else { } if (((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rssi_type == 4U) { write_phy_reg(pi, 437, (int )valuetostuff); } else { } if (((unsigned int )coresel == 1U || (unsigned int )coresel == 5U) && (unsigned int )rssi_type == 5U) { write_phy_reg(pi, 431, (int )valuetostuff); } else { } if (((unsigned int )coresel == 2U || (unsigned int )coresel == 5U) && (unsigned int )rssi_type == 5U) { write_phy_reg(pi, 443, (int )valuetostuff); } else { } return; } } static void brcms_phy_wr_tx_mux(struct brcms_phy *pi , u8 core ) { { if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if (pi->pubpi.phy_rev > 6U) { write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, ((int )pi->radio_chanspec & 61440) == 4096 ? 12 : 14); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 8237 : 12333, ((int )pi->radio_chanspec & 61440) == 4096 ? 12 : 14); } } else if (pi->pubpi.phy_rev > 6U) { write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, 17); if ((unsigned int )pi->pubpi.radioid == 8279U) { write_radio_reg(pi, 205, 1); } else { } } else { write_radio_reg(pi, (unsigned int )core == 0U ? 8237 : 12333, 17); } return; } } void wlc_phy_rssisel_nphy(struct brcms_phy *pi , u8 core_code , u8 rssi_type ) { u16 mask ; u16 val ; u16 afectrlovr_rssi_val ; u16 rfctrlcmd_rxen_val ; u16 rfctrlcmd_coresel_val ; u16 startseq ; u16 rfctrlovr_rssi_val ; u16 rfctrlovr_rxen_val ; u16 rfctrlovr_coresel_val ; u16 rfctrlovr_trigger_val ; u16 afectrlovr_rssi_mask ; u16 rfctrlcmd_mask ; u16 rfctrlovr_mask ; u16 rfctrlcmd_val ; u16 rfctrlovr_val ; u8 core ; { if (pi->pubpi.phy_rev > 2U) { if ((unsigned int )core_code == 0U) { mod_phy_reg(pi, 143, 512, 0); mod_phy_reg(pi, 165, 512, 0); mod_phy_reg(pi, 166, 768, 0); mod_phy_reg(pi, 167, 768, 0); mod_phy_reg(pi, 229, 32, 0); mod_phy_reg(pi, 230, 32, 0); mask = 60U; mod_phy_reg(pi, 249, (int )mask, 0); mod_phy_reg(pi, 251, (int )mask, 0); } else { core = 0U; goto ldv_38800; ldv_38799: ; if ((unsigned int )core_code == 1U && (unsigned int )core == 1U) { goto ldv_38798; } else if ((unsigned int )core_code == 2U && (unsigned int )core == 0U) { goto ldv_38798; } else { } mod_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165, 512, 512); if (((unsigned int )rssi_type == 0U || (unsigned int )rssi_type == 1U) || (unsigned int )rssi_type == 2U) { mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, 768, 0); mask = 60U; mod_phy_reg(pi, (unsigned int )core == 0U ? 249 : 251, (int )mask, 0); if ((unsigned int )rssi_type == 0U) { if (((int )pi->radio_chanspec & 61440) == 4096) { mask = 4U; val = 4U; } else { mask = 8U; val = 8U; } } else if ((unsigned int )rssi_type == 1U) { mask = 16U; val = 16U; } else { mask = 32U; val = 32U; } mod_phy_reg(pi, (unsigned int )core == 0U ? 249 : 251, (int )mask, (int )val); mask = 32U; val = 32U; mod_phy_reg(pi, (unsigned int )core == 0U ? 229 : 230, (int )mask, (int )val); } else if ((unsigned int )rssi_type == 6U) { mask = 768U; val = 256U; mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, (int )mask, (int )val); mask = 3072U; val = 1024U; mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, (int )mask, (int )val); } else if ((unsigned int )rssi_type == 3U) { mask = 768U; val = 512U; mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, (int )mask, (int )val); mask = 3072U; val = 2048U; mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, (int )mask, (int )val); } else { mask = 768U; val = 768U; mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, (int )mask, (int )val); mask = 3072U; val = 3072U; mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, (int )mask, (int )val); brcms_phy_wr_tx_mux(pi, (int )core); afectrlovr_rssi_val = 512U; mod_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165, 512, (int )afectrlovr_rssi_val); } ldv_38798: core = (u8 )((int )core + 1); ldv_38800: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38799; } else { } } } else { if (((unsigned int )rssi_type == 0U || (unsigned int )rssi_type == 1U) || (unsigned int )rssi_type == 2U) { val = 0U; } else if ((unsigned int )rssi_type == 6U) { val = 1U; } else if ((unsigned int )rssi_type == 3U) { val = 2U; } else { val = 3U; } mask = 61440U; val = (u16 )((int )((short )((int )val << 12)) | (int )((short )((int )val << 14))); mod_phy_reg(pi, 166, (int )mask, (int )val); mod_phy_reg(pi, 167, (int )mask, (int )val); if (((unsigned int )rssi_type == 0U || (unsigned int )rssi_type == 1U) || (unsigned int )rssi_type == 2U) { if ((unsigned int )rssi_type == 0U) { val = 1U; } else { } if ((unsigned int )rssi_type == 1U) { val = 2U; } else { } if ((unsigned int )rssi_type == 2U) { val = 3U; } else { } mask = 48U; val = (int )val << 4U; mod_phy_reg(pi, 122, (int )mask, (int )val); mod_phy_reg(pi, 125, (int )mask, (int )val); } else { } if ((unsigned int )core_code == 0U) { afectrlovr_rssi_val = 0U; rfctrlcmd_rxen_val = 0U; rfctrlcmd_coresel_val = 0U; rfctrlovr_rssi_val = 0U; rfctrlovr_rxen_val = 0U; rfctrlovr_coresel_val = 0U; rfctrlovr_trigger_val = 0U; startseq = 0U; } else { afectrlovr_rssi_val = 1U; rfctrlcmd_rxen_val = 1U; rfctrlcmd_coresel_val = (u16 )core_code; rfctrlovr_rssi_val = 1U; rfctrlovr_rxen_val = 1U; rfctrlovr_coresel_val = 1U; rfctrlovr_trigger_val = 1U; startseq = 1U; } afectrlovr_rssi_mask = 12288U; afectrlovr_rssi_val = (u16 )((int )((short )((int )afectrlovr_rssi_val << 12)) | (int )((short )((int )afectrlovr_rssi_val << 13))); mod_phy_reg(pi, 165, (int )afectrlovr_rssi_mask, (int )afectrlovr_rssi_val); if (((unsigned int )rssi_type == 0U || (unsigned int )rssi_type == 1U) || (unsigned int )rssi_type == 2U) { rfctrlcmd_mask = 312U; rfctrlcmd_val = (u16 )((int )((short )((int )rfctrlcmd_rxen_val << 8)) | (int )((short )((int )rfctrlcmd_coresel_val << 3))); rfctrlovr_mask = 4131U; rfctrlovr_val = (u16 )((((int )((short )((int )rfctrlovr_rssi_val << 5)) | (int )((short )((int )rfctrlovr_rxen_val << 12))) | (int )((short )((int )rfctrlovr_coresel_val << 1))) | (int )((short )rfctrlovr_trigger_val)); mod_phy_reg(pi, 120, (int )rfctrlcmd_mask, (int )rfctrlcmd_val); mod_phy_reg(pi, 236, (int )rfctrlovr_mask, (int )rfctrlovr_val); mod_phy_reg(pi, 120, 1, (int )startseq); __const_udelay(85900UL); mod_phy_reg(pi, 236, 1, 0); } else { } } return; } } int wlc_phy_poll_rssi_nphy(struct brcms_phy *pi , u8 rssi_type , s32 *rssi_buf , u8 nsamps ) { s16 rssi0 ; s16 rssi1 ; u16 afectrlCore1_save ; u16 afectrlCore2_save ; u16 afectrlOverride1_save ; u16 afectrlOverride2_save ; u16 rfctrlOverrideAux0_save ; u16 rfctrlOverrideAux1_save ; u16 rfctrlMiscReg1_save ; u16 rfctrlMiscReg2_save ; u16 rfctrlcmd_save ; u16 rfctrloverride_save ; u16 rfctrlrssiothers1_save ; u16 rfctrlrssiothers2_save ; s8 tmp_buf[4U] ; u8 ctr ; u8 samp ; s32 rssi_out_val ; u16 gpiosel_orig ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; u8 tmp___3 ; u8 tmp___4 ; u8 tmp___5 ; u8 tmp___6 ; { afectrlCore1_save = 0U; afectrlCore2_save = 0U; afectrlOverride1_save = 0U; afectrlOverride2_save = 0U; rfctrlOverrideAux0_save = 0U; rfctrlOverrideAux1_save = 0U; rfctrlMiscReg1_save = 0U; rfctrlMiscReg2_save = 0U; rfctrlcmd_save = 0U; rfctrloverride_save = 0U; rfctrlrssiothers1_save = 0U; rfctrlrssiothers2_save = 0U; ctr = 0U; samp = 0U; afectrlCore1_save = read_phy_reg(pi, 166); afectrlCore2_save = read_phy_reg(pi, 167); if (pi->pubpi.phy_rev > 2U) { rfctrlMiscReg1_save = read_phy_reg(pi, 249); rfctrlMiscReg2_save = read_phy_reg(pi, 251); afectrlOverride1_save = read_phy_reg(pi, 143); afectrlOverride2_save = read_phy_reg(pi, 165); rfctrlOverrideAux0_save = read_phy_reg(pi, 229); rfctrlOverrideAux1_save = read_phy_reg(pi, 230); } else { afectrlOverride1_save = read_phy_reg(pi, 165); rfctrlcmd_save = read_phy_reg(pi, 120); rfctrloverride_save = read_phy_reg(pi, 236); rfctrlrssiothers1_save = read_phy_reg(pi, 122); rfctrlrssiothers2_save = read_phy_reg(pi, 125); } wlc_phy_rssisel_nphy(pi, 5, (int )rssi_type); gpiosel_orig = read_phy_reg(pi, 202); if (pi->pubpi.phy_rev <= 1U) { write_phy_reg(pi, 202, 5); } else { } ctr = 0U; goto ldv_38828; ldv_38827: *(rssi_buf + (unsigned long )ctr) = 0; ctr = (u8 )((int )ctr + 1); ldv_38828: ; if ((unsigned int )ctr <= 3U) { goto ldv_38827; } else { } samp = 0U; goto ldv_38834; ldv_38833: ; if (pi->pubpi.phy_rev <= 1U) { tmp = read_phy_reg(pi, 457); rssi0 = (s16 )tmp; tmp___0 = read_phy_reg(pi, 458); rssi1 = (s16 )tmp___0; } else { tmp___1 = read_phy_reg(pi, 537); rssi0 = (s16 )tmp___1; tmp___2 = read_phy_reg(pi, 538); rssi1 = (s16 )tmp___2; } ctr = 0U; tmp___3 = ctr; ctr = (u8 )((int )ctr + 1); tmp_buf[(int )tmp___3] = (s8 )((int )((signed char )((int )rssi0 << 2)) >> 2); tmp___4 = ctr; ctr = (u8 )((int )ctr + 1); tmp_buf[(int )tmp___4] = (s8 )((int )((signed char )(((int )rssi0 >> 8) << 2)) >> 2); tmp___5 = ctr; ctr = (u8 )((int )ctr + 1); tmp_buf[(int )tmp___5] = (s8 )((int )((signed char )((int )rssi1 << 2)) >> 2); tmp___6 = ctr; ctr = (u8 )((int )ctr + 1); tmp_buf[(int )tmp___6] = (s8 )((int )((signed char )(((int )rssi1 >> 8) << 2)) >> 2); ctr = 0U; goto ldv_38831; ldv_38830: *(rssi_buf + (unsigned long )ctr) = *(rssi_buf + (unsigned long )ctr) + (int )tmp_buf[(int )ctr]; ctr = (u8 )((int )ctr + 1); ldv_38831: ; if ((unsigned int )ctr <= 3U) { goto ldv_38830; } else { } samp = (u8 )((int )samp + 1); ldv_38834: ; if ((int )samp < (int )nsamps) { goto ldv_38833; } else { } rssi_out_val = *(rssi_buf + 3UL) & 255; rssi_out_val = ((*(rssi_buf + 2UL) << 8) & 65535) | rssi_out_val; rssi_out_val = ((*(rssi_buf + 1UL) & 255) << 16) | rssi_out_val; rssi_out_val = (*rssi_buf << 24) | rssi_out_val; if (pi->pubpi.phy_rev <= 1U) { write_phy_reg(pi, 202, (int )gpiosel_orig); } else { } write_phy_reg(pi, 166, (int )afectrlCore1_save); write_phy_reg(pi, 167, (int )afectrlCore2_save); if (pi->pubpi.phy_rev > 2U) { write_phy_reg(pi, 249, (int )rfctrlMiscReg1_save); write_phy_reg(pi, 251, (int )rfctrlMiscReg2_save); write_phy_reg(pi, 143, (int )afectrlOverride1_save); write_phy_reg(pi, 165, (int )afectrlOverride2_save); write_phy_reg(pi, 229, (int )rfctrlOverrideAux0_save); write_phy_reg(pi, 230, (int )rfctrlOverrideAux1_save); } else { write_phy_reg(pi, 165, (int )afectrlOverride1_save); write_phy_reg(pi, 120, (int )rfctrlcmd_save); write_phy_reg(pi, 236, (int )rfctrloverride_save); write_phy_reg(pi, 122, (int )rfctrlrssiothers1_save); write_phy_reg(pi, 125, (int )rfctrlrssiothers2_save); } return (rssi_out_val); } } s16 wlc_phy_tempsense_nphy(struct brcms_phy *pi ) { u16 core1_txrf_iqcal1_save ; u16 core1_txrf_iqcal2_save ; u16 core2_txrf_iqcal1_save ; u16 core2_txrf_iqcal2_save ; u16 pwrdet_rxtx_core1_save ; u16 pwrdet_rxtx_core2_save ; u16 afectrlCore1_save ; u16 afectrlCore2_save ; u16 afectrlOverride_save ; u16 afectrlOverride2_save ; u16 pd_pll_ts_save ; u16 gpioSel_save ; s32 radio_temp[4U] ; s32 radio_temp2[4U] ; u16 syn_tempprocsense_save ; s16 offset ; u16 auxADC_Vmid ; u16 auxADC_Av ; u16 auxADC_Vmid_save ; u16 auxADC_Av_save ; u16 auxADC_rssi_ctrlL_save ; u16 auxADC_rssi_ctrlH_save ; u16 auxADC_rssi_ctrlL ; u16 auxADC_rssi_ctrlH ; s32 auxADC_Vl ; u16 RfctrlOverride5_save ; u16 RfctrlOverride6_save ; u16 RfctrlMiscReg5_save ; u16 RfctrlMiscReg6_save ; u16 RSSIMultCoef0QPowerDet_save ; u16 tempsense_Rcal ; { offset = 0; if (pi->pubpi.phy_rev > 6U) { syn_tempprocsense_save = read_radio_reg(pi, 12); afectrlCore1_save = read_phy_reg(pi, 166); afectrlCore2_save = read_phy_reg(pi, 167); afectrlOverride_save = read_phy_reg(pi, 143); afectrlOverride2_save = read_phy_reg(pi, 165); RSSIMultCoef0QPowerDet_save = read_phy_reg(pi, 430); RfctrlOverride5_save = read_phy_reg(pi, 838); RfctrlOverride6_save = read_phy_reg(pi, 839); RfctrlMiscReg5_save = read_phy_reg(pi, 836); RfctrlMiscReg6_save = read_phy_reg(pi, 837); wlc_phy_table_read_nphy(pi, 8U, 1U, 10U, 16U, (void *)(& auxADC_Vmid_save)); wlc_phy_table_read_nphy(pi, 8U, 1U, 14U, 16U, (void *)(& auxADC_Av_save)); wlc_phy_table_read_nphy(pi, 8U, 1U, 2U, 16U, (void *)(& auxADC_rssi_ctrlL_save)); wlc_phy_table_read_nphy(pi, 8U, 1U, 3U, 16U, (void *)(& auxADC_rssi_ctrlH_save)); write_phy_reg(pi, 430, 0); auxADC_rssi_ctrlL = 0U; auxADC_rssi_ctrlH = 32U; wlc_phy_table_write_nphy(pi, 8U, 1U, 2U, 16U, (void const *)(& auxADC_rssi_ctrlL)); wlc_phy_table_write_nphy(pi, 8U, 1U, 3U, 16U, (void const *)(& auxADC_rssi_ctrlH)); tempsense_Rcal = (unsigned int )syn_tempprocsense_save & 28U; write_radio_reg(pi, 12, (int )((unsigned int )tempsense_Rcal | 1U)); wlc_phy_rfctrl_override_nphy_rev7(pi, 2, 1, 0, 0, 2); mod_phy_reg(pi, 166, 128, 0); mod_phy_reg(pi, 167, 128, 0); mod_phy_reg(pi, 143, 128, 128); mod_phy_reg(pi, 165, 128, 128); mod_phy_reg(pi, 166, 4, 4); mod_phy_reg(pi, 167, 4, 4); mod_phy_reg(pi, 143, 4, 4); mod_phy_reg(pi, 165, 4, 4); __const_udelay(21475UL); mod_phy_reg(pi, 166, 4, 0); mod_phy_reg(pi, 167, 4, 0); mod_phy_reg(pi, 166, 8, 0); mod_phy_reg(pi, 167, 8, 0); mod_phy_reg(pi, 143, 8, 8); mod_phy_reg(pi, 165, 8, 8); mod_phy_reg(pi, 166, 64, 0); mod_phy_reg(pi, 167, 64, 0); mod_phy_reg(pi, 143, 64, 64); mod_phy_reg(pi, 165, 64, 64); auxADC_Vmid = 163U; auxADC_Av = 0U; wlc_phy_table_write_nphy(pi, 8U, 1U, 10U, 16U, (void const *)(& auxADC_Vmid)); wlc_phy_table_write_nphy(pi, 8U, 1U, 14U, 16U, (void const *)(& auxADC_Av)); __const_udelay(12885UL); wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp), 1); write_radio_reg(pi, 12, (int )((unsigned int )tempsense_Rcal | 3U)); __const_udelay(21475UL); wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp2), 1); auxADC_Av = 7U; if (radio_temp[1] + radio_temp2[1] < -30) { auxADC_Vmid = 69U; auxADC_Vl = 263; } else if (radio_temp[1] + radio_temp2[1] < -9) { auxADC_Vmid = 512U; auxADC_Vl = 467; } else if (radio_temp[1] + radio_temp2[1] <= 10) { auxADC_Vmid = 614U; auxADC_Vl = 634; } else { auxADC_Vmid = 725U; auxADC_Vl = 816; } wlc_phy_table_write_nphy(pi, 8U, 1U, 10U, 16U, (void const *)(& auxADC_Vmid)); wlc_phy_table_write_nphy(pi, 8U, 1U, 14U, 16U, (void const *)(& auxADC_Av)); __const_udelay(12885UL); wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp2), 1); write_radio_reg(pi, 12, (int )((unsigned int )tempsense_Rcal | 1U)); __const_udelay(21475UL); wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp), 1); write_radio_reg(pi, 12, (int )syn_tempprocsense_save); write_phy_reg(pi, 166, (int )afectrlCore1_save); write_phy_reg(pi, 167, (int )afectrlCore2_save); write_phy_reg(pi, 143, (int )afectrlOverride_save); write_phy_reg(pi, 165, (int )afectrlOverride2_save); write_phy_reg(pi, 430, (int )RSSIMultCoef0QPowerDet_save); write_phy_reg(pi, 838, (int )RfctrlOverride5_save); write_phy_reg(pi, 839, (int )RfctrlOverride6_save); write_phy_reg(pi, 836, (int )RfctrlMiscReg5_save); write_phy_reg(pi, 837, (int )RfctrlMiscReg5_save); wlc_phy_table_write_nphy(pi, 8U, 1U, 10U, 16U, (void const *)(& auxADC_Vmid_save)); wlc_phy_table_write_nphy(pi, 8U, 1U, 14U, 16U, (void const *)(& auxADC_Av_save)); wlc_phy_table_write_nphy(pi, 8U, 1U, 2U, 16U, (void const *)(& auxADC_rssi_ctrlL_save)); wlc_phy_table_write_nphy(pi, 8U, 1U, 3U, 16U, (void const *)(& auxADC_rssi_ctrlH_save)); if ((pi->sh)->chip == 21335U) { radio_temp[0] = (((radio_temp[1] + radio_temp2[1]) * 193 + auxADC_Vl * 88) + -26983) / 256; } else { radio_temp[0] = (((radio_temp[1] + radio_temp2[1]) * 179 + auxADC_Vl * 82) + -28733) / 256; } offset = (short )pi->phy_tempsense_offset; } else if (pi->pubpi.phy_rev > 2U) { syn_tempprocsense_save = read_radio_reg(pi, 37); afectrlCore1_save = read_phy_reg(pi, 166); afectrlCore2_save = read_phy_reg(pi, 167); afectrlOverride_save = read_phy_reg(pi, 143); afectrlOverride2_save = read_phy_reg(pi, 165); gpioSel_save = read_phy_reg(pi, 202); write_radio_reg(pi, 37, 1); wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp), 1); if (pi->pubpi.phy_rev <= 6U) { write_radio_reg(pi, 37, 5); } else { } wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp2), 1); if (pi->pubpi.phy_rev > 6U) { write_radio_reg(pi, 12, 1); } else { write_radio_reg(pi, 37, 1); } radio_temp[0] = ((radio_temp[1] + radio_temp2[1]) * 126 + 3987) / 64; write_radio_reg(pi, 37, (int )syn_tempprocsense_save); write_phy_reg(pi, 202, (int )gpioSel_save); write_phy_reg(pi, 166, (int )afectrlCore1_save); write_phy_reg(pi, 167, (int )afectrlCore2_save); write_phy_reg(pi, 143, (int )afectrlOverride_save); write_phy_reg(pi, 165, (int )afectrlOverride2_save); offset = (short )pi->phy_tempsense_offset; } else { pwrdet_rxtx_core1_save = read_radio_reg(pi, 31); pwrdet_rxtx_core2_save = read_radio_reg(pi, 33); core1_txrf_iqcal1_save = read_radio_reg(pi, 135); core1_txrf_iqcal2_save = read_radio_reg(pi, 136); core2_txrf_iqcal1_save = read_radio_reg(pi, 182); core2_txrf_iqcal2_save = read_radio_reg(pi, 183); pd_pll_ts_save = read_radio_reg(pi, 20); afectrlCore1_save = read_phy_reg(pi, 166); afectrlCore2_save = read_phy_reg(pi, 167); afectrlOverride_save = read_phy_reg(pi, 165); gpioSel_save = read_phy_reg(pi, 202); write_radio_reg(pi, 135, 1); write_radio_reg(pi, 182, 1); write_radio_reg(pi, 136, 8); write_radio_reg(pi, 183, 8); write_radio_reg(pi, 31, 4); write_radio_reg(pi, 33, 4); write_radio_reg(pi, 20, 0); wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp), 1); xor_radio_reg(pi, 42, 128); wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp), 1); xor_radio_reg(pi, 42, 128); wlc_phy_poll_rssi_nphy(pi, 3, (s32 *)(& radio_temp2), 1); xor_radio_reg(pi, 42, 128); radio_temp[0] = radio_temp[0] + radio_temp2[0]; radio_temp[1] = radio_temp[1] + radio_temp2[1]; radio_temp[2] = radio_temp[2] + radio_temp2[2]; radio_temp[3] = radio_temp[3] + radio_temp2[3]; radio_temp[0] = ((radio_temp[0] + radio_temp[1]) + radio_temp[2]) + radio_temp[3]; radio_temp[0] = (radio_temp[0] * 600 + 153600) / 63 + 2800; radio_temp[0] = (radio_temp[0] + -3360) / 38; write_radio_reg(pi, 31, (int )pwrdet_rxtx_core1_save); write_radio_reg(pi, 33, (int )pwrdet_rxtx_core2_save); write_radio_reg(pi, 135, (int )core1_txrf_iqcal1_save); write_radio_reg(pi, 182, (int )core2_txrf_iqcal1_save); write_radio_reg(pi, 136, (int )core1_txrf_iqcal2_save); write_radio_reg(pi, 183, (int )core2_txrf_iqcal2_save); write_radio_reg(pi, 20, (int )pd_pll_ts_save); write_phy_reg(pi, 202, (int )gpioSel_save); write_phy_reg(pi, 166, (int )afectrlCore1_save); write_phy_reg(pi, 167, (int )afectrlCore2_save); write_phy_reg(pi, 165, (int )afectrlOverride_save); } return ((s16 )((int )((unsigned short )radio_temp[0]) + (int )((unsigned short )offset))); } } static void wlc_phy_set_rssi_2055_vcm(struct brcms_phy *pi , u8 rssi_type , u8 *vcm_buf ) { u8 core ; { core = 0U; goto ldv_38877; ldv_38876: ; if ((unsigned int )rssi_type == 2U) { if ((unsigned int )core == 0U) { mod_radio_reg(pi, 210, 3, (int )*(vcm_buf + (unsigned long )((int )core * 2))); mod_radio_reg(pi, 118, 3, (int )*(vcm_buf + ((unsigned long )((int )core * 2) + 1UL))); } else { mod_radio_reg(pi, 222, 3, (int )*(vcm_buf + (unsigned long )((int )core * 2))); mod_radio_reg(pi, 165, 3, (int )*(vcm_buf + ((unsigned long )((int )core * 2) + 1UL))); } } else if ((unsigned int )core == 0U) { mod_radio_reg(pi, 118, 12, (int )((u16 )*(vcm_buf + (unsigned long )((int )core * 2))) << 2U); } else { mod_radio_reg(pi, 165, 12, (int )((u16 )*(vcm_buf + (unsigned long )((int )core * 2))) << 2U); } core = (u8 )((int )core + 1); ldv_38877: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38876; } else { } return; } } static void wlc_phy_rssi_cal_nphy_rev3(struct brcms_phy *pi ) { u16 classif_state ; u16 clip_state[2U] ; u16 clip_off[2U] ; s32 target_code ; u8 vcm ; u8 min_vcm ; u8 vcm_final ; u8 result_idx ; s32 poll_results[8U][4U] ; s32 poll_result_core[4U] ; s32 min_d ; s32 curr_d ; s32 fine_digital_offset[4U] ; s32 poll_results_min[4U] ; s32 min_poll ; u8 vcm_level_max ; u8 core ; u8 wb_cnt ; u8 rssi_type ; u16 NPHY_Rfctrlintc1_save ; u16 NPHY_Rfctrlintc2_save ; u16 NPHY_AfectrlOverride1_save ; u16 NPHY_AfectrlOverride2_save ; u16 NPHY_AfectrlCore1_save ; u16 NPHY_AfectrlCore2_save ; u16 NPHY_RfctrlOverride0_save ; u16 NPHY_RfctrlOverride1_save ; u16 NPHY_RfctrlOverrideAux0_save ; u16 NPHY_RfctrlOverrideAux1_save ; u16 NPHY_RfctrlCmd_save ; u16 NPHY_RfctrlMiscReg1_save ; u16 NPHY_RfctrlMiscReg2_save ; u16 NPHY_RfctrlRSSIOTHERS1_save ; u16 NPHY_RfctrlRSSIOTHERS2_save ; u8 rxcore_state ; u16 NPHY_REV7_RfctrlOverride3_save ; u16 NPHY_REV7_RfctrlOverride4_save ; u16 NPHY_REV7_RfctrlOverride5_save ; u16 NPHY_REV7_RfctrlOverride6_save ; u16 NPHY_REV7_RfctrlMiscReg3_save ; u16 NPHY_REV7_RfctrlMiscReg4_save ; u16 NPHY_REV7_RfctrlMiscReg5_save ; u16 NPHY_REV7_RfctrlMiscReg6_save ; long ret ; int __x___0 ; long ret___0 ; int __x___2 ; { clip_off[0] = 65535U; clip_off[1] = 65535U; vcm_final = 0U; poll_results[0][0] = 0; poll_results[0][1] = 0; poll_results[0][2] = 0; poll_results[0][3] = 0; poll_results[1][0] = 0; poll_results[1][1] = 0; poll_results[1][2] = 0; poll_results[1][3] = 0; poll_results[2][0] = 0; poll_results[2][1] = 0; poll_results[2][2] = 0; poll_results[2][3] = 0; poll_results[3][0] = 0; poll_results[3][1] = 0; poll_results[3][2] = 0; poll_results[3][3] = 0; poll_results[4][0] = 0; poll_results[4][1] = 0; poll_results[4][2] = 0; poll_results[4][3] = 0; poll_results[5][0] = 0; poll_results[5][1] = 0; poll_results[5][2] = 0; poll_results[5][3] = 0; poll_results[6][0] = 0; poll_results[6][1] = 0; poll_results[6][2] = 0; poll_results[6][3] = 0; poll_results[7][0] = 0; poll_results[7][1] = 0; poll_results[7][2] = 0; poll_results[7][3] = 0; poll_result_core[0] = 0; poll_result_core[1] = 0; poll_result_core[2] = 0; poll_result_core[3] = 0; min_d = 1048576; poll_results_min[0] = 0; poll_results_min[1] = 0; poll_results_min[2] = 0; poll_results_min[3] = 0; NPHY_REV7_RfctrlMiscReg6_save = 0U; NPHY_REV7_RfctrlMiscReg5_save = NPHY_REV7_RfctrlMiscReg6_save; NPHY_REV7_RfctrlMiscReg4_save = NPHY_REV7_RfctrlMiscReg5_save; NPHY_REV7_RfctrlMiscReg3_save = NPHY_REV7_RfctrlMiscReg4_save; NPHY_REV7_RfctrlOverride6_save = NPHY_REV7_RfctrlMiscReg3_save; NPHY_REV7_RfctrlOverride5_save = NPHY_REV7_RfctrlOverride6_save; NPHY_REV7_RfctrlOverride4_save = NPHY_REV7_RfctrlOverride5_save; NPHY_REV7_RfctrlOverride3_save = NPHY_REV7_RfctrlOverride4_save; classif_state = wlc_phy_classifier_nphy(pi, 0, 0); wlc_phy_classifier_nphy(pi, 7, 4); wlc_phy_clip_det_nphy(pi, 0, (u16 *)(& clip_state)); wlc_phy_clip_det_nphy(pi, 1, (u16 *)(& clip_off)); NPHY_Rfctrlintc1_save = read_phy_reg(pi, 145); NPHY_Rfctrlintc2_save = read_phy_reg(pi, 146); NPHY_AfectrlOverride1_save = read_phy_reg(pi, 143); NPHY_AfectrlOverride2_save = read_phy_reg(pi, 165); NPHY_AfectrlCore1_save = read_phy_reg(pi, 166); NPHY_AfectrlCore2_save = read_phy_reg(pi, 167); NPHY_RfctrlOverride0_save = read_phy_reg(pi, 231); NPHY_RfctrlOverride1_save = read_phy_reg(pi, 236); if (pi->pubpi.phy_rev > 6U) { NPHY_REV7_RfctrlOverride3_save = read_phy_reg(pi, 834); NPHY_REV7_RfctrlOverride4_save = read_phy_reg(pi, 835); NPHY_REV7_RfctrlOverride5_save = read_phy_reg(pi, 838); NPHY_REV7_RfctrlOverride6_save = read_phy_reg(pi, 839); } else { } NPHY_RfctrlOverrideAux0_save = read_phy_reg(pi, 229); NPHY_RfctrlOverrideAux1_save = read_phy_reg(pi, 230); NPHY_RfctrlCmd_save = read_phy_reg(pi, 120); NPHY_RfctrlMiscReg1_save = read_phy_reg(pi, 249); NPHY_RfctrlMiscReg2_save = read_phy_reg(pi, 251); if (pi->pubpi.phy_rev > 6U) { NPHY_REV7_RfctrlMiscReg3_save = read_phy_reg(pi, 832); NPHY_REV7_RfctrlMiscReg4_save = read_phy_reg(pi, 833); NPHY_REV7_RfctrlMiscReg5_save = read_phy_reg(pi, 836); NPHY_REV7_RfctrlMiscReg6_save = read_phy_reg(pi, 837); } else { } NPHY_RfctrlRSSIOTHERS1_save = read_phy_reg(pi, 122); NPHY_RfctrlRSSIOTHERS2_save = read_phy_reg(pi, 125); wlc_phy_rfctrlintc_override_nphy(pi, 0, 0, 7); wlc_phy_rfctrlintc_override_nphy(pi, 1, 1, 7); if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_1tomany_nphy(pi, 0, 0, 0, 0); } else { wlc_phy_rfctrl_override_nphy(pi, 1, 0, 0, 0); } if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_1tomany_nphy(pi, 1, 1, 0, 0); } else { wlc_phy_rfctrl_override_nphy(pi, 2, 1, 0, 0); } if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 128, 1, 0, 0, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 64, 1, 0, 0, 0); } else { wlc_phy_rfctrl_override_nphy(pi, 128, 1, 0, 0); wlc_phy_rfctrl_override_nphy(pi, 64, 1, 0, 0); } if (((int )pi->radio_chanspec & 61440) == 4096) { if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 32, 0, 0, 0, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 16, 1, 0, 0, 0); } else { wlc_phy_rfctrl_override_nphy(pi, 32, 0, 0, 0); wlc_phy_rfctrl_override_nphy(pi, 16, 1, 0, 0); } } else if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 16, 0, 0, 0, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 32, 1, 0, 0, 0); } else { wlc_phy_rfctrl_override_nphy(pi, 16, 0, 0, 0); wlc_phy_rfctrl_override_nphy(pi, 32, 1, 0, 0); } rxcore_state = wlc_phy_rxcore_getstate_nphy((struct brcms_phy_pub *)pi); vcm_level_max = 8U; core = 0U; goto ldv_38943; ldv_38942: ; if ((((int )rxcore_state >> (int )core) & 1) == 0) { goto ldv_38925; } else { } wlc_phy_scale_offset_rssi_nphy(pi, 0, 0, (unsigned int )core == 0U ? 1 : 2, 0, 2); wlc_phy_scale_offset_rssi_nphy(pi, 0, 0, (unsigned int )core == 0U ? 1 : 2, 1, 2); vcm = 0U; goto ldv_38927; ldv_38926: ; if (pi->pubpi.phy_rev > 6U) { mod_radio_reg(pi, (unsigned int )core == 0U ? 180 : 313, 7, (int )vcm); } else { mod_radio_reg(pi, (unsigned int )core == 0U ? 24619 : 28715, 28, (int )((u16 )vcm) << 2U); } wlc_phy_poll_rssi_nphy(pi, 2, (s32 *)(& poll_results) + (unsigned long )vcm, 8); vcm = (u8 )((int )vcm + 1); ldv_38927: ; if ((int )vcm < (int )vcm_level_max) { goto ldv_38926; } else { } result_idx = 0U; goto ldv_38933; ldv_38932: ; if ((unsigned int )result_idx / 2U == (unsigned int )core && ((unsigned int )result_idx & 1U) == 0U) { min_d = 1048576; min_vcm = 0U; min_poll = 249; vcm = 0U; goto ldv_38930; ldv_38929: curr_d = poll_results[(int )vcm][(int )result_idx] * poll_results[(int )vcm][(int )result_idx] + poll_results[(int )vcm][(int )result_idx + 1] * poll_results[(int )vcm][(int )result_idx + 1]; if (curr_d < min_d) { min_d = curr_d; min_vcm = vcm; } else { } if (poll_results[(int )vcm][(int )result_idx] < min_poll) { min_poll = poll_results[(int )vcm][(int )result_idx]; } else { } vcm = (u8 )((int )vcm + 1); ldv_38930: ; if ((int )vcm < (int )vcm_level_max) { goto ldv_38929; } else { } vcm_final = min_vcm; poll_results_min[(int )result_idx] = min_poll; } else { } result_idx = (u8 )((int )result_idx + 1); ldv_38933: ; if ((unsigned int )result_idx <= 3U) { goto ldv_38932; } else { } if (pi->pubpi.phy_rev > 6U) { mod_radio_reg(pi, (unsigned int )core == 0U ? 180 : 313, 7, (int )vcm_final); } else { mod_radio_reg(pi, (unsigned int )core == 0U ? 24619 : 28715, 28, (int )((u16 )vcm_final) << 2U); } result_idx = 0U; goto ldv_38940; ldv_38939: ; if ((unsigned int )result_idx / 2U == (unsigned int )core) { fine_digital_offset[(int )result_idx] = - poll_results[(int )vcm_final][(int )result_idx]; if (fine_digital_offset[(int )result_idx] < 0) { __x___0 = fine_digital_offset[(int )result_idx]; ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); fine_digital_offset[(int )result_idx] = (s32 )ret; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] + 4; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] / 8; fine_digital_offset[(int )result_idx] = - fine_digital_offset[(int )result_idx]; } else { fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] + 4; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] / 8; } if (poll_results_min[(int )result_idx] == 248) { fine_digital_offset[(int )result_idx] = -32; } else { } wlc_phy_scale_offset_rssi_nphy(pi, 0, (int )((signed char )fine_digital_offset[(int )result_idx]), (unsigned int )result_idx <= 1U ? 1 : 2, (int )result_idx & 1, 2); } else { } result_idx = (u8 )((int )result_idx + 1); ldv_38940: ; if ((unsigned int )result_idx <= 3U) { goto ldv_38939; } else { } ldv_38925: core = (u8 )((int )core + 1); ldv_38943: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38942; } else { } core = 0U; goto ldv_38957; ldv_38956: ; if ((((int )rxcore_state >> (int )core) & 1) == 0) { goto ldv_38945; } else { } wb_cnt = 0U; goto ldv_38954; ldv_38953: ; if ((unsigned int )wb_cnt == 0U) { rssi_type = 0U; target_code = 29; } else { rssi_type = 1U; target_code = 29; } wlc_phy_scale_offset_rssi_nphy(pi, 0, 0, (unsigned int )core == 0U ? 1 : 2, 0, (int )rssi_type); wlc_phy_scale_offset_rssi_nphy(pi, 0, 0, (unsigned int )core == 0U ? 1 : 2, 1, (int )rssi_type); wlc_phy_poll_rssi_nphy(pi, (int )rssi_type, (s32 *)(& poll_result_core), 8); result_idx = 0U; goto ldv_38951; ldv_38950: ; if ((unsigned int )result_idx / 2U == (unsigned int )core) { fine_digital_offset[(int )result_idx] = target_code * 8 - poll_result_core[(int )result_idx]; if (fine_digital_offset[(int )result_idx] < 0) { __x___2 = fine_digital_offset[(int )result_idx]; ret___0 = (long )(__x___2 < 0 ? - __x___2 : __x___2); fine_digital_offset[(int )result_idx] = (s32 )ret___0; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] + 4; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] / 8; fine_digital_offset[(int )result_idx] = - fine_digital_offset[(int )result_idx]; } else { fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] + 4; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] / 8; } wlc_phy_scale_offset_rssi_nphy(pi, 0, (int )((signed char )fine_digital_offset[(int )core * 2]), (unsigned int )core == 0U ? 1 : 2, (int )result_idx & 1, (int )rssi_type); } else { } result_idx = (u8 )((int )result_idx + 1); ldv_38951: ; if ((unsigned int )result_idx <= 3U) { goto ldv_38950; } else { } wb_cnt = (u8 )((int )wb_cnt + 1); ldv_38954: ; if ((unsigned int )wb_cnt <= 1U) { goto ldv_38953; } else { } ldv_38945: core = (u8 )((int )core + 1); ldv_38957: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_38956; } else { } write_phy_reg(pi, 145, (int )NPHY_Rfctrlintc1_save); write_phy_reg(pi, 146, (int )NPHY_Rfctrlintc2_save); wlc_phy_force_rfseq_nphy(pi, 2); mod_phy_reg(pi, 231, 1, 1); mod_phy_reg(pi, 120, 1, 1); mod_phy_reg(pi, 231, 1, 0); mod_phy_reg(pi, 236, 1, 1); mod_phy_reg(pi, 120, 2, 2); mod_phy_reg(pi, 236, 1, 0); write_phy_reg(pi, 143, (int )NPHY_AfectrlOverride1_save); write_phy_reg(pi, 165, (int )NPHY_AfectrlOverride2_save); write_phy_reg(pi, 166, (int )NPHY_AfectrlCore1_save); write_phy_reg(pi, 167, (int )NPHY_AfectrlCore2_save); write_phy_reg(pi, 231, (int )NPHY_RfctrlOverride0_save); write_phy_reg(pi, 236, (int )NPHY_RfctrlOverride1_save); if (pi->pubpi.phy_rev > 6U) { write_phy_reg(pi, 834, (int )NPHY_REV7_RfctrlOverride3_save); write_phy_reg(pi, 835, (int )NPHY_REV7_RfctrlOverride4_save); write_phy_reg(pi, 838, (int )NPHY_REV7_RfctrlOverride5_save); write_phy_reg(pi, 839, (int )NPHY_REV7_RfctrlOverride6_save); } else { } write_phy_reg(pi, 229, (int )NPHY_RfctrlOverrideAux0_save); write_phy_reg(pi, 230, (int )NPHY_RfctrlOverrideAux1_save); write_phy_reg(pi, 120, (int )NPHY_RfctrlCmd_save); write_phy_reg(pi, 249, (int )NPHY_RfctrlMiscReg1_save); write_phy_reg(pi, 251, (int )NPHY_RfctrlMiscReg2_save); if (pi->pubpi.phy_rev > 6U) { write_phy_reg(pi, 832, (int )NPHY_REV7_RfctrlMiscReg3_save); write_phy_reg(pi, 833, (int )NPHY_REV7_RfctrlMiscReg4_save); write_phy_reg(pi, 836, (int )NPHY_REV7_RfctrlMiscReg5_save); write_phy_reg(pi, 837, (int )NPHY_REV7_RfctrlMiscReg6_save); } else { } write_phy_reg(pi, 122, (int )NPHY_RfctrlRSSIOTHERS1_save); write_phy_reg(pi, 125, (int )NPHY_RfctrlRSSIOTHERS2_save); if (((int )pi->radio_chanspec & 61440) == 8192) { if (pi->pubpi.phy_rev > 6U) { pi->rssical_cache.rssical_radio_regs_2G[0] = read_radio_reg(pi, 180); pi->rssical_cache.rssical_radio_regs_2G[1] = read_radio_reg(pi, 313); } else { pi->rssical_cache.rssical_radio_regs_2G[0] = read_radio_reg(pi, 24619); pi->rssical_cache.rssical_radio_regs_2G[1] = read_radio_reg(pi, 28715); } pi->rssical_cache.rssical_phyregs_2G[0] = read_phy_reg(pi, 422); pi->rssical_cache.rssical_phyregs_2G[1] = read_phy_reg(pi, 428); pi->rssical_cache.rssical_phyregs_2G[2] = read_phy_reg(pi, 434); pi->rssical_cache.rssical_phyregs_2G[3] = read_phy_reg(pi, 440); pi->rssical_cache.rssical_phyregs_2G[4] = read_phy_reg(pi, 420); pi->rssical_cache.rssical_phyregs_2G[5] = read_phy_reg(pi, 426); pi->rssical_cache.rssical_phyregs_2G[6] = read_phy_reg(pi, 432); pi->rssical_cache.rssical_phyregs_2G[7] = read_phy_reg(pi, 438); pi->rssical_cache.rssical_phyregs_2G[8] = read_phy_reg(pi, 421); pi->rssical_cache.rssical_phyregs_2G[9] = read_phy_reg(pi, 427); pi->rssical_cache.rssical_phyregs_2G[10] = read_phy_reg(pi, 433); pi->rssical_cache.rssical_phyregs_2G[11] = read_phy_reg(pi, 439); pi->nphy_rssical_chanspec_2G = pi->radio_chanspec; } else { if (pi->pubpi.phy_rev > 6U) { pi->rssical_cache.rssical_radio_regs_5G[0] = read_radio_reg(pi, 180); pi->rssical_cache.rssical_radio_regs_5G[1] = read_radio_reg(pi, 313); } else { pi->rssical_cache.rssical_radio_regs_5G[0] = read_radio_reg(pi, 24619); pi->rssical_cache.rssical_radio_regs_5G[1] = read_radio_reg(pi, 28715); } pi->rssical_cache.rssical_phyregs_5G[0] = read_phy_reg(pi, 422); pi->rssical_cache.rssical_phyregs_5G[1] = read_phy_reg(pi, 428); pi->rssical_cache.rssical_phyregs_5G[2] = read_phy_reg(pi, 434); pi->rssical_cache.rssical_phyregs_5G[3] = read_phy_reg(pi, 440); pi->rssical_cache.rssical_phyregs_5G[4] = read_phy_reg(pi, 420); pi->rssical_cache.rssical_phyregs_5G[5] = read_phy_reg(pi, 426); pi->rssical_cache.rssical_phyregs_5G[6] = read_phy_reg(pi, 432); pi->rssical_cache.rssical_phyregs_5G[7] = read_phy_reg(pi, 438); pi->rssical_cache.rssical_phyregs_5G[8] = read_phy_reg(pi, 421); pi->rssical_cache.rssical_phyregs_5G[9] = read_phy_reg(pi, 427); pi->rssical_cache.rssical_phyregs_5G[10] = read_phy_reg(pi, 433); pi->rssical_cache.rssical_phyregs_5G[11] = read_phy_reg(pi, 439); pi->nphy_rssical_chanspec_5G = pi->radio_chanspec; } wlc_phy_classifier_nphy(pi, 7, (int )classif_state); wlc_phy_clip_det_nphy(pi, 1, (u16 *)(& clip_state)); return; } } static void wlc_phy_rssi_cal_nphy_rev2(struct brcms_phy *pi , u8 rssi_type ) { s32 target_code ; u16 classif_state ; u16 clip_state[2U] ; u16 rssi_ctrl_state[2U] ; u16 pd_state[2U] ; u16 rfctrlintc_state[2U] ; u16 rfpdcorerxtx_state[2U] ; u16 rfctrlintc_override_val ; u16 clip_off[2U] ; u16 rf_pd_val ; u16 pd_mask ; u16 rssi_ctrl_mask ; u8 vcm ; u8 min_vcm ; u8 vcm_tmp[4U] ; u8 vcm_final[4U] ; u8 result_idx ; u8 ctr ; s32 poll_results[4U][4U] ; s32 poll_miniq[4U][2U] ; s32 min_d ; s32 curr_d ; s32 fine_digital_offset[4U] ; s32 poll_results_min[4U] ; s32 min_poll ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; s32 _min1 ; s32 _min2 ; long ret ; int __x___0 ; long ret___0 ; int __x___2 ; { clip_off[0] = 65535U; clip_off[1] = 65535U; vcm_final[0] = 0U; vcm_final[1] = 0U; vcm_final[2] = 0U; vcm_final[3] = 0U; poll_results[0][0] = 0; poll_results[0][1] = 0; poll_results[0][2] = 0; poll_results[0][3] = 0; poll_results[1][0] = 0; poll_results[1][1] = 0; poll_results[1][2] = 0; poll_results[1][3] = 0; poll_results[2][0] = 0; poll_results[2][1] = 0; poll_results[2][2] = 0; poll_results[2][3] = 0; poll_results[3][0] = 0; poll_results[3][1] = 0; poll_results[3][2] = 0; poll_results[3][3] = 0; poll_miniq[0][0] = 0; poll_miniq[0][1] = 0; poll_miniq[1][0] = 0; poll_miniq[1][1] = 0; poll_miniq[2][0] = 0; poll_miniq[2][1] = 0; poll_miniq[3][0] = 0; poll_miniq[3][1] = 0; poll_results_min[0] = 0; poll_results_min[1] = 0; poll_results_min[2] = 0; poll_results_min[3] = 0; switch ((int )rssi_type) { case 2: target_code = 0; goto ldv_38989; case 0: target_code = 25; goto ldv_38989; case 1: target_code = 25; goto ldv_38989; default: ; return; } ldv_38989: classif_state = wlc_phy_classifier_nphy(pi, 0, 0); wlc_phy_classifier_nphy(pi, 7, 4); wlc_phy_clip_det_nphy(pi, 0, (u16 *)(& clip_state)); wlc_phy_clip_det_nphy(pi, 1, (u16 *)(& clip_off)); rf_pd_val = (unsigned int )rssi_type == 2U ? 6U : 4U; rfctrlintc_override_val = ((int )pi->radio_chanspec & 61440) == 4096 ? 320U : 272U; rfctrlintc_state[0] = read_phy_reg(pi, 145); rfpdcorerxtx_state[0] = read_radio_reg(pi, 23); write_phy_reg(pi, 145, (int )rfctrlintc_override_val); write_radio_reg(pi, 23, (int )rf_pd_val); rfctrlintc_state[1] = read_phy_reg(pi, 146); rfpdcorerxtx_state[1] = read_radio_reg(pi, 27); write_phy_reg(pi, 146, (int )rfctrlintc_override_val); write_radio_reg(pi, 27, (int )rf_pd_val); pd_mask = 7U; tmp = read_radio_reg(pi, 24); pd_state[0] = (u16 )((int )tmp & (int )pd_mask); tmp___0 = read_radio_reg(pi, 28); pd_state[1] = (u16 )((int )tmp___0 & (int )pd_mask); mod_radio_reg(pi, 24, (int )pd_mask, 0); mod_radio_reg(pi, 28, (int )pd_mask, 0); rssi_ctrl_mask = 7U; tmp___1 = read_radio_reg(pi, 3); rssi_ctrl_state[0] = (u16 )((int )tmp___1 & (int )rssi_ctrl_mask); tmp___2 = read_radio_reg(pi, 5); rssi_ctrl_state[1] = (u16 )((int )tmp___2 & (int )rssi_ctrl_mask); wlc_phy_rssisel_nphy(pi, 5, (int )rssi_type); wlc_phy_scale_offset_rssi_nphy(pi, 0, 0, 5, 0, (int )rssi_type); wlc_phy_scale_offset_rssi_nphy(pi, 0, 0, 5, 1, (int )rssi_type); vcm = 0U; goto ldv_39000; ldv_38999: vcm_tmp[3] = vcm; vcm_tmp[2] = vcm_tmp[3]; vcm_tmp[1] = vcm_tmp[2]; vcm_tmp[0] = vcm_tmp[1]; if ((unsigned int )rssi_type != 1U) { wlc_phy_set_rssi_2055_vcm(pi, (int )rssi_type, (u8 *)(& vcm_tmp)); } else { } wlc_phy_poll_rssi_nphy(pi, (int )rssi_type, (s32 *)(& poll_results) + (unsigned long )vcm, 8); if ((unsigned int )rssi_type == 0U || (unsigned int )rssi_type == 1U) { ctr = 0U; goto ldv_38997; ldv_38996: _min1 = poll_results[(int )vcm][(int )ctr * 2]; _min2 = poll_results[(int )vcm][(int )ctr * 2 + 1]; poll_miniq[(int )vcm][(int )ctr] = _min1 < _min2 ? _min1 : _min2; ctr = (u8 )((int )ctr + 1); ldv_38997: ; if ((unsigned int )ctr <= 1U) { goto ldv_38996; } else { } } else { } vcm = (u8 )((int )vcm + 1); ldv_39000: ; if ((unsigned int )vcm <= 3U) { goto ldv_38999; } else { } result_idx = 0U; goto ldv_39010; ldv_39009: min_d = 1048576; min_vcm = 0U; min_poll = 249; vcm = 0U; goto ldv_39007; ldv_39006: __x___0 = ((unsigned int )rssi_type == 2U ? poll_results[(int )vcm][(int )result_idx] : poll_miniq[(int )vcm][(int )((unsigned int )result_idx / 2U)]) + target_code * -8; ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); curr_d = (s32 )ret; if (curr_d < min_d) { min_d = curr_d; min_vcm = vcm; } else { } if (poll_results[(int )vcm][(int )result_idx] < min_poll) { min_poll = poll_results[(int )vcm][(int )result_idx]; } else { } vcm = (u8 )((int )vcm + 1); ldv_39007: ; if ((unsigned int )vcm <= 3U) { goto ldv_39006; } else { } vcm_final[(int )result_idx] = min_vcm; poll_results_min[(int )result_idx] = min_poll; result_idx = (u8 )((int )result_idx + 1); ldv_39010: ; if ((unsigned int )result_idx <= 3U) { goto ldv_39009; } else { } if ((unsigned int )rssi_type != 1U) { wlc_phy_set_rssi_2055_vcm(pi, (int )rssi_type, (u8 *)(& vcm_final)); } else { } result_idx = 0U; goto ldv_39017; ldv_39016: fine_digital_offset[(int )result_idx] = target_code * 8 - poll_results[(int )vcm_final[(int )result_idx]][(int )result_idx]; if (fine_digital_offset[(int )result_idx] < 0) { __x___2 = fine_digital_offset[(int )result_idx]; ret___0 = (long )(__x___2 < 0 ? - __x___2 : __x___2); fine_digital_offset[(int )result_idx] = (s32 )ret___0; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] + 4; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] / 8; fine_digital_offset[(int )result_idx] = - fine_digital_offset[(int )result_idx]; } else { fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] + 4; fine_digital_offset[(int )result_idx] = fine_digital_offset[(int )result_idx] / 8; } if (poll_results_min[(int )result_idx] == 248) { fine_digital_offset[(int )result_idx] = target_code + -32; } else { } wlc_phy_scale_offset_rssi_nphy(pi, 0, (int )((signed char )fine_digital_offset[(int )result_idx]), (unsigned int )result_idx <= 1U ? 1 : 2, (int )result_idx & 1, (int )rssi_type); result_idx = (u8 )((int )result_idx + 1); ldv_39017: ; if ((unsigned int )result_idx <= 3U) { goto ldv_39016; } else { } mod_radio_reg(pi, 24, (int )pd_mask, (int )pd_state[0]); mod_radio_reg(pi, 28, (int )pd_mask, (int )pd_state[1]); if ((unsigned int )rssi_ctrl_state[0] == 1U) { wlc_phy_rssisel_nphy(pi, 1, 2); } else if ((unsigned int )rssi_ctrl_state[0] == 4U) { wlc_phy_rssisel_nphy(pi, 1, 0); } else { wlc_phy_rssisel_nphy(pi, 1, 1); } if ((unsigned int )rssi_ctrl_state[1] == 1U) { wlc_phy_rssisel_nphy(pi, 2, 2); } else if ((unsigned int )rssi_ctrl_state[1] == 4U) { wlc_phy_rssisel_nphy(pi, 2, 0); } else { wlc_phy_rssisel_nphy(pi, 2, 1); } wlc_phy_rssisel_nphy(pi, 0, (int )rssi_type); write_phy_reg(pi, 145, (int )rfctrlintc_state[0]); write_radio_reg(pi, 23, (int )rfpdcorerxtx_state[0]); write_phy_reg(pi, 146, (int )rfctrlintc_state[1]); write_radio_reg(pi, 27, (int )rfpdcorerxtx_state[1]); wlc_phy_classifier_nphy(pi, 7, (int )classif_state); wlc_phy_clip_det_nphy(pi, 1, (u16 *)(& clip_state)); wlc_phy_resetcca_nphy(pi); return; } } void wlc_phy_rssi_cal_nphy(struct brcms_phy *pi ) { { if (pi->pubpi.phy_rev > 2U) { wlc_phy_rssi_cal_nphy_rev3(pi); } else { wlc_phy_rssi_cal_nphy_rev2(pi, 2); wlc_phy_rssi_cal_nphy_rev2(pi, 0); wlc_phy_rssi_cal_nphy_rev2(pi, 1); } return; } } int wlc_phy_rssi_compute_nphy(struct brcms_phy *pi , struct d11rxhdr *rxh ) { s16 rxpwr ; s16 rxpwr0 ; s16 rxpwr1 ; s16 phyRx0_l ; s16 phyRx2_l ; { rxpwr = 0; rxpwr0 = (int )((s16 )rxh->PhyRxStatus_1) & 255; rxpwr1 = (s16 )((int )rxh->PhyRxStatus_1 >> 8); if ((int )rxpwr0 > 127) { rxpwr0 = (s16 )((unsigned int )((unsigned short )rxpwr0) + 65280U); } else { } if ((int )rxpwr1 > 127) { rxpwr1 = (s16 )((unsigned int )((unsigned short )rxpwr1) + 65280U); } else { } phyRx0_l = (int )((s16 )rxh->PhyRxStatus_0) & 255; phyRx2_l = (int )((s16 )rxh->PhyRxStatus_2) & 255; if ((int )phyRx2_l > 127) { phyRx2_l = (s16 )((unsigned int )((unsigned short )phyRx2_l) + 65280U); } else { } if ((int )rxpwr0 == 16 || (int )rxpwr0 == 32) { rxpwr0 = rxpwr1; rxpwr1 = phyRx2_l; } else { } if ((unsigned int )(pi->sh)->rssi_mode == 0U) { rxpwr = (s16 )((int )rxpwr0 > (int )rxpwr1 ? rxpwr0 : rxpwr1); } else if ((unsigned int )(pi->sh)->rssi_mode == 1U) { rxpwr = (s16 )((int )rxpwr0 < (int )rxpwr1 ? rxpwr0 : rxpwr1); } else if ((unsigned int )(pi->sh)->rssi_mode == 2U) { rxpwr = (s16 )(((int )rxpwr0 + (int )rxpwr1) >> 1); } else { } return ((int )rxpwr); } } static void wlc_phy_loadsampletable_nphy(struct brcms_phy *pi , struct cordic_iq *tone_buf , u16 num_samps ) { u16 t ; u32 *data_buf ; void *tmp ; { data_buf = (u32 *)0U; tmp = kmalloc((unsigned long )num_samps * 4UL, 32U); data_buf = (u32 *)tmp; if ((unsigned long )data_buf == (unsigned long )((u32 *)0U)) { return; } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } t = 0U; goto ldv_39039; ldv_39038: *(data_buf + (unsigned long )t) = (((unsigned int )(tone_buf + (unsigned long )t)->i & 1023U) << 10) | ((unsigned int )(tone_buf + (unsigned long )t)->q & 1023U); t = (u16 )((int )t + 1); ldv_39039: ; if ((int )t < (int )num_samps) { goto ldv_39038; } else { } wlc_phy_table_write_nphy(pi, 17U, (u32 )num_samps, 0U, 32U, (void const *)data_buf); kfree((void const *)data_buf); if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static u16 wlc_phy_gen_load_samples_nphy(struct brcms_phy *pi , u32 f_kHz , u16 max_val , u8 dac_test_mode ) { u8 phy_bw ; u8 is_phybw40 ; u16 num_samps ; u16 t ; u16 spur ; s32 theta ; s32 rot ; u32 tbl_len ; struct cordic_iq *tone_buf ; void *tmp ; { theta = 0; rot = 0; tone_buf = (struct cordic_iq *)0; is_phybw40 = ((int )pi->radio_chanspec & 3072) == 3072; phy_bw = (unsigned int )is_phybw40 == 1U ? 40U : 20U; tbl_len = (u32 )((int )phy_bw << 3); if ((unsigned int )dac_test_mode == 1U) { spur = read_phy_reg(pi, 1); spur = (u16 )((int )spur >> 15); phy_bw = (unsigned int )spur == 1U ? 82U : 80U; phy_bw = (unsigned int )is_phybw40 == 1U ? (int )phy_bw << 1U : phy_bw; tbl_len = (u32 )((int )phy_bw << 1); } else { } tmp = kmalloc((unsigned long )tbl_len * 8UL, 32U); tone_buf = (struct cordic_iq *)tmp; if ((unsigned long )tone_buf == (unsigned long )((struct cordic_iq *)0)) { return (0U); } else { } num_samps = (unsigned short )tbl_len; rot = (s32 )(((f_kHz * 36U) / (u32 )phy_bw) / 100U); theta = 0; t = 0U; goto ldv_39057; ldv_39056: *(tone_buf + (unsigned long )t) = cordic_calc_iq(theta); theta = theta + rot; (tone_buf + (unsigned long )t)->q = (tone_buf + (unsigned long )t)->q * (int )max_val >= 0 ? (((tone_buf + (unsigned long )t)->q * (int )max_val >> 15) + 1) >> 1 : - (((- ((tone_buf + (unsigned long )t)->q * (int )max_val) >> 15) + 1) >> 1); (tone_buf + (unsigned long )t)->i = (tone_buf + (unsigned long )t)->i * (int )max_val >= 0 ? (((tone_buf + (unsigned long )t)->i * (int )max_val >> 15) + 1) >> 1 : - (((- ((tone_buf + (unsigned long )t)->i * (int )max_val) >> 15) + 1) >> 1); t = (u16 )((int )t + 1); ldv_39057: ; if ((int )t < (int )num_samps) { goto ldv_39056; } else { } wlc_phy_loadsampletable_nphy(pi, tone_buf, (int )num_samps); kfree((void const *)tone_buf); return (num_samps); } } static void wlc_phy_runsamples_nphy(struct brcms_phy *pi , u16 num_samps , u16 loops , u16 wait , u8 iqmode , u8 dac_test_mode , bool modify_bbmult ) { u16 bb_mult ; u8 phy_bw ; u8 sample_cmd ; u16 orig_RfseqCoreActv ; u16 lpf_bw_ctl_override3 ; u16 lpf_bw_ctl_override4 ; u16 lpf_bw_ctl_miscreg3 ; u16 lpf_bw_ctl_miscreg4 ; u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; u16 tmp___3 ; u16 tmp___4 ; u16 tmp___5 ; uint countdown ; u16 tmp___6 ; { if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } phy_bw = 20U; if (((int )pi->radio_chanspec & 3072) == 3072) { phy_bw = 40U; } else { } if (pi->pubpi.phy_rev > 6U) { tmp = read_phy_reg(pi, 834); lpf_bw_ctl_override3 = (unsigned int )tmp & 128U; tmp___0 = read_phy_reg(pi, 835); lpf_bw_ctl_override4 = (unsigned int )tmp___0 & 128U; if ((unsigned int )((int )lpf_bw_ctl_override3 | (int )lpf_bw_ctl_override4) != 0U) { tmp___1 = read_phy_reg(pi, 832); lpf_bw_ctl_miscreg3 = (unsigned int )tmp___1 & 1792U; tmp___2 = read_phy_reg(pi, 833); lpf_bw_ctl_miscreg4 = (unsigned int )tmp___2 & 1792U; } else { tmp___3 = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 128, (int )tmp___3, 0, 0, 1); pi->nphy_sample_play_lpf_bw_ctl_ovr = 1; tmp___4 = read_phy_reg(pi, 832); lpf_bw_ctl_miscreg3 = (unsigned int )tmp___4 & 1792U; tmp___5 = read_phy_reg(pi, 833); lpf_bw_ctl_miscreg4 = (unsigned int )tmp___5 & 1792U; } } else { } if ((int )pi->nphy_bb_mult_save >= 0) { wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& bb_mult)); pi->nphy_bb_mult_save = (unsigned int )bb_mult | 2147483648U; } else { } if ((int )modify_bbmult) { bb_mult = (unsigned int )phy_bw == 20U ? 100U : 71U; bb_mult = ((int )bb_mult << 8U) + (int )bb_mult; wlc_phy_table_write_nphy(pi, 15U, 1U, 87U, 16U, (void const *)(& bb_mult)); } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } write_phy_reg(pi, 198, (int )((unsigned int )num_samps + 65535U)); if ((unsigned int )loops != 65535U) { write_phy_reg(pi, 196, (int )((unsigned int )loops + 65535U)); } else { write_phy_reg(pi, 196, (int )loops); } write_phy_reg(pi, 197, (int )wait); orig_RfseqCoreActv = read_phy_reg(pi, 161); or_phy_reg(pi, 161, 1); if ((unsigned int )iqmode != 0U) { and_phy_reg(pi, 194, 32767); or_phy_reg(pi, 194, 32768); } else { sample_cmd = (unsigned int )dac_test_mode == 1U ? 5U : 1U; write_phy_reg(pi, 195, (int )sample_cmd); } countdown = 1009U; goto ldv_39078; ldv_39077: __const_udelay(42950UL); countdown = countdown - 10U; ldv_39078: tmp___6 = read_phy_reg(pi, 164); if ((int )tmp___6 & 1 && countdown > 9U) { goto ldv_39077; } else { } write_phy_reg(pi, 161, (int )orig_RfseqCoreActv); return; } } int wlc_phy_tx_tone_nphy(struct brcms_phy *pi , u32 f_kHz , u16 max_val , u8 iqmode , u8 dac_test_mode , bool modify_bbmult ) { u16 num_samps ; u16 loops ; u16 wait ; { loops = 65535U; wait = 0U; num_samps = wlc_phy_gen_load_samples_nphy(pi, f_kHz, (int )max_val, (int )dac_test_mode); if ((unsigned int )num_samps == 0U) { return (-52); } else { } wlc_phy_runsamples_nphy(pi, (int )num_samps, (int )loops, (int )wait, (int )iqmode, (int )dac_test_mode, (int )modify_bbmult); return (0); } } void wlc_phy_stopplayback_nphy(struct brcms_phy *pi ) { u16 playback_status ; u16 bb_mult ; { if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } playback_status = read_phy_reg(pi, 199); if ((int )playback_status & 1) { or_phy_reg(pi, 195, 2); } else if (((int )playback_status & 2) != 0) { and_phy_reg(pi, 194, 32767); } else { } and_phy_reg(pi, 195, 65531); if ((int )pi->nphy_bb_mult_save < 0) { bb_mult = (u16 )pi->nphy_bb_mult_save; wlc_phy_table_write_nphy(pi, 15U, 1U, 87U, 16U, (void const *)(& bb_mult)); pi->nphy_bb_mult_save = 0U; } else { } if (pi->pubpi.phy_rev == 7U || pi->pubpi.phy_rev > 7U) { if ((int )pi->nphy_sample_play_lpf_bw_ctl_ovr) { wlc_phy_rfctrl_override_nphy_rev7(pi, 128, 0, 0, 1, 1); pi->nphy_sample_play_lpf_bw_ctl_ovr = 0; } else { } } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static u32 *brcms_phy_get_tx_pwrctrl_tbl(struct brcms_phy *pi ) { u32 *tx_pwrctrl_tbl ; uint phyrev ; { tx_pwrctrl_tbl = (u32 *)0U; phyrev = pi->pubpi.phy_rev; if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { tx_pwrctrl_tbl = wlc_phy_get_ipa_gaintbl_nphy(pi); } else if (((int )pi->radio_chanspec & 61440) == 4096) { if (phyrev == 3U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_5GHz_txgain_rev3); } else if (phyrev == 4U) { tx_pwrctrl_tbl = (unsigned int )pi->srom_fem5g.extpagain == 3U ? (u32 *)(& nphy_tpc_5GHz_txgain_HiPwrEPA) : (u32 *)(& nphy_tpc_5GHz_txgain_rev4); } else { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_5GHz_txgain_rev5); } } else if (phyrev > 6U) { if ((unsigned int )pi->pubpi.radiorev == 3U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_epa_2057rev3); } else if ((unsigned int )pi->pubpi.radiorev == 5U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_epa_2057rev5); } else { } } else if (phyrev > 4U && (unsigned int )pi->srom_fem2g.extpagain == 3U) { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_HiPwrEPA); } else { tx_pwrctrl_tbl = (u32 *)(& nphy_tpc_txgain_rev3); } return (tx_pwrctrl_tbl); } } struct nphy_txgains wlc_phy_get_tx_gain_nphy(struct brcms_phy *pi ) { u16 base_idx[2U] ; u16 curr_gain[2U] ; u8 core_no ; struct nphy_txgains target_gain ; u32 *tx_pwrctrl_tbl ; uint phyrev ; u16 tmp ; u16 tmp___0 ; { tx_pwrctrl_tbl = (u32 *)0U; if ((unsigned int )pi->nphy_txpwrctrl == 0U) { if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } wlc_phy_table_read_nphy(pi, 7U, 2U, 272U, 16U, (void *)(& curr_gain)); if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } core_no = 0U; goto ldv_39110; ldv_39109: ; if (pi->pubpi.phy_rev > 6U) { target_gain.ipa[(int )core_no] = (unsigned int )curr_gain[(int )core_no] & 7U; target_gain.pad[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 248) >> 3); target_gain.pga[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 3840) >> 8); target_gain.txgm[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 28672) >> 12); target_gain.txlpf[(int )core_no] = (int )curr_gain[(int )core_no] >> 15; } else if (pi->pubpi.phy_rev > 2U) { target_gain.ipa[(int )core_no] = (unsigned int )curr_gain[(int )core_no] & 15U; target_gain.pad[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 240) >> 4); target_gain.pga[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 3840) >> 8); target_gain.txgm[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 28672) >> 12); } else { target_gain.ipa[(int )core_no] = (unsigned int )curr_gain[(int )core_no] & 3U; target_gain.pad[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 12) >> 2); target_gain.pga[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 112) >> 4); target_gain.txgm[(int )core_no] = (u16 )(((int )curr_gain[(int )core_no] & 896) >> 7); } core_no = (u8 )((int )core_no + 1); ldv_39110: ; if ((unsigned int )core_no <= 1U) { goto ldv_39109; } else { } } else { phyrev = pi->pubpi.phy_rev; tmp = read_phy_reg(pi, 493); base_idx[0] = (unsigned int )((u16 )((int )tmp >> 8)) & 127U; tmp___0 = read_phy_reg(pi, 494); base_idx[1] = (unsigned int )((u16 )((int )tmp___0 >> 8)) & 127U; core_no = 0U; goto ldv_39114; ldv_39113: ; if (phyrev > 2U) { tx_pwrctrl_tbl = brcms_phy_get_tx_pwrctrl_tbl(pi); if (phyrev > 6U) { target_gain.ipa[(int )core_no] = (unsigned int )((u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 16)) & 7U; target_gain.pad[(int )core_no] = (unsigned int )((u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 19)) & 31U; target_gain.pga[(int )core_no] = (unsigned int )((u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 24)) & 15U; target_gain.txgm[(int )core_no] = (unsigned int )((u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 28)) & 7U; target_gain.txlpf[(int )core_no] = (u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 31); } else { target_gain.ipa[(int )core_no] = (unsigned int )((u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 16)) & 15U; target_gain.pad[(int )core_no] = (unsigned int )((u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 20)) & 15U; target_gain.pga[(int )core_no] = (unsigned int )((u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 24)) & 15U; target_gain.txgm[(int )core_no] = (unsigned int )((u16 )(*(tx_pwrctrl_tbl + (unsigned long )base_idx[(int )core_no]) >> 28)) & 7U; } } else { target_gain.ipa[(int )core_no] = (unsigned int )((u16 )(nphy_tpc_txgain[(int )base_idx[(int )core_no]] >> 16)) & 3U; target_gain.pad[(int )core_no] = (unsigned int )((u16 )(nphy_tpc_txgain[(int )base_idx[(int )core_no]] >> 18)) & 3U; target_gain.pga[(int )core_no] = (unsigned int )((u16 )(nphy_tpc_txgain[(int )base_idx[(int )core_no]] >> 20)) & 7U; target_gain.txgm[(int )core_no] = (unsigned int )((u16 )(nphy_tpc_txgain[(int )base_idx[(int )core_no]] >> 23)) & 7U; } core_no = (u8 )((int )core_no + 1); ldv_39114: ; if ((unsigned int )core_no <= 1U) { goto ldv_39113; } else { } } return (target_gain); } } static void wlc_phy_iqcal_gainparams_nphy(struct brcms_phy *pi , u16 core_no , struct nphy_txgains target_gain , struct nphy_iqcal_params *params ) { u8 k ; int idx ; u16 gain_index ; u8 band_idx ; { band_idx = ((int )pi->radio_chanspec & 61440) == 4096; if (pi->pubpi.phy_rev > 2U) { if (pi->pubpi.phy_rev > 6U) { params->txlpf = target_gain.txlpf[(int )core_no]; } else { } params->txgm = target_gain.txgm[(int )core_no]; params->pga = target_gain.pga[(int )core_no]; params->pad = target_gain.pad[(int )core_no]; params->ipa = target_gain.ipa[(int )core_no]; if (pi->pubpi.phy_rev > 6U) { params->cal_gain = (u16 )(((((int )((short )((int )params->txlpf << 15)) | (int )((short )((int )params->txgm << 12))) | (int )((short )((int )params->pga << 8))) | (int )((short )((int )params->pad << 3))) | (int )((short )params->ipa)); } else { params->cal_gain = (u16 )((((int )((short )((int )params->txgm << 12)) | (int )((short )((int )params->pga << 8))) | (int )((short )((int )params->pad << 4))) | (int )((short )params->ipa)); } params->ncorr[0] = 121U; params->ncorr[1] = 121U; params->ncorr[2] = 121U; params->ncorr[3] = 121U; params->ncorr[4] = 121U; } else { gain_index = (u16 )(((int )((short )target_gain.pad[(int )core_no]) | (int )((short )((int )target_gain.pga[(int )core_no] << 4))) | (int )((short )((int )target_gain.txgm[(int )core_no] << 8))); idx = -1; k = 0U; goto ldv_39128; ldv_39127: ; if ((int )((unsigned short )tbl_iqcal_gainparams_nphy[(int )band_idx][(int )k][0]) == (int )gain_index) { idx = (int )k; goto ldv_39126; } else { } k = (u8 )((int )k + 1); ldv_39128: ; if ((unsigned int )k <= 8U) { goto ldv_39127; } else { } ldv_39126: params->txgm = tbl_iqcal_gainparams_nphy[(int )band_idx][(int )k][1]; params->pga = tbl_iqcal_gainparams_nphy[(int )band_idx][(int )k][2]; params->pad = tbl_iqcal_gainparams_nphy[(int )band_idx][(int )k][3]; params->cal_gain = (u16 )(((int )((short )((int )params->txgm << 7)) | (int )((short )((int )params->pga << 4))) | (int )((short )((int )params->pad << 2))); params->ncorr[0] = tbl_iqcal_gainparams_nphy[(int )band_idx][(int )k][4]; params->ncorr[1] = tbl_iqcal_gainparams_nphy[(int )band_idx][(int )k][5]; params->ncorr[2] = tbl_iqcal_gainparams_nphy[(int )band_idx][(int )k][6]; params->ncorr[3] = tbl_iqcal_gainparams_nphy[(int )band_idx][(int )k][7]; } return; } } static void wlc_phy_txcal_radio_setup_nphy(struct brcms_phy *pi ) { u16 jtag_core ; u16 core ; u16 tmp ; { if (pi->pubpi.phy_rev > 6U) { core = 0U; goto ldv_39135; ldv_39134: pi->tx_rx_cal_radio_saveregs[(int )core * 11] = read_radio_reg(pi, (unsigned int )core == 0U ? 373 : 405); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 1] = read_radio_reg(pi, (unsigned int )core == 0U ? 374 : 406); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 2] = read_radio_reg(pi, (unsigned int )core == 0U ? 375 : 407); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 3] = read_radio_reg(pi, (unsigned int )core == 0U ? 376 : 408); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 4] = 0U; pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 5] = read_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409); if ((unsigned int )pi->pubpi.radiorev != 5U) { pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 6] = read_radio_reg(pi, (unsigned int )core == 0U ? 378 : 410); } else { } pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 7] = read_radio_reg(pi, (unsigned int )core == 0U ? 379 : 411); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 8] = read_radio_reg(pi, (unsigned int )core == 0U ? 380 : 412); if (((int )pi->radio_chanspec & 61440) == 4096) { write_radio_reg(pi, (unsigned int )core == 0U ? 373 : 405, 10); write_radio_reg(pi, (unsigned int )core == 0U ? 374 : 406, 67); write_radio_reg(pi, (unsigned int )core == 0U ? 375 : 407, 85); write_radio_reg(pi, (unsigned int )core == 0U ? 376 : 408, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 379 : 411, 0); if ((int )pi->use_int_tx_iqlo_cal_nphy) { write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, 4); if (! pi->internal_tx_iqlo_cal_tapoff_intpa_nphy) { write_radio_reg(pi, (unsigned int )core == 0U ? 378 : 410, 49); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 378 : 410, 33); } } else { } write_radio_reg(pi, (unsigned int )core == 0U ? 380 : 412, 0); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 373 : 405, 6); write_radio_reg(pi, (unsigned int )core == 0U ? 374 : 406, 67); write_radio_reg(pi, (unsigned int )core == 0U ? 375 : 407, 85); write_radio_reg(pi, (unsigned int )core == 0U ? 376 : 408, 0); if ((unsigned int )pi->pubpi.radiorev != 5U) { write_radio_reg(pi, (unsigned int )core == 0U ? 378 : 410, 0); } else { } if ((int )pi->use_int_tx_iqlo_cal_nphy) { write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, 6); if (! pi->internal_tx_iqlo_cal_tapoff_intpa_nphy) { write_radio_reg(pi, (unsigned int )core == 0U ? 379 : 411, 49); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 379 : 411, 33); } } else { } write_radio_reg(pi, (unsigned int )core == 0U ? 380 : 412, 0); } core = (u16 )((int )core + 1); ldv_39135: ; if ((unsigned int )core <= 1U) { goto ldv_39134; } else { } } else if (pi->pubpi.phy_rev > 2U) { core = 0U; goto ldv_39138; ldv_39137: jtag_core = (unsigned int )core == 0U ? 8192U : 12288U; pi->tx_rx_cal_radio_saveregs[(int )core * 11] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 40U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 1] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 41U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 2] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 42U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 3] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 43U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 4] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 44U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 5] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 45U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 6] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 46U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 7] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 47U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 8] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 48U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 9] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 49U)); pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 10] = read_radio_reg(pi, (int )((unsigned int )jtag_core | 50U)); if (((int )pi->radio_chanspec & 61440) == 4096) { write_radio_reg(pi, (int )((unsigned int )jtag_core | 40U), 10); write_radio_reg(pi, (int )((unsigned int )jtag_core | 41U), 64); write_radio_reg(pi, (int )((unsigned int )jtag_core | 42U), 85); write_radio_reg(pi, (int )((unsigned int )jtag_core | 43U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 44U), 0); if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { write_radio_reg(pi, (int )((unsigned int )jtag_core | 45U), 4); write_radio_reg(pi, (int )((unsigned int )jtag_core | 46U), 1); } else { write_radio_reg(pi, (int )((unsigned int )jtag_core | 45U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 46U), 47); } write_radio_reg(pi, (int )((unsigned int )jtag_core | 47U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 48U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 49U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 50U), 0); } else { write_radio_reg(pi, (int )((unsigned int )jtag_core | 40U), 6); write_radio_reg(pi, (int )((unsigned int )jtag_core | 41U), 64); write_radio_reg(pi, (int )((unsigned int )jtag_core | 42U), 85); write_radio_reg(pi, (int )((unsigned int )jtag_core | 43U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 44U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 46U), 0); if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { write_radio_reg(pi, (int )((unsigned int )jtag_core | 45U), 6); if (pi->pubpi.phy_rev <= 4U) { write_radio_reg(pi, (int )((unsigned int )jtag_core | 47U), 17); } else { write_radio_reg(pi, (int )((unsigned int )jtag_core | 47U), 1); } } else { write_radio_reg(pi, (int )((unsigned int )jtag_core | 45U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 47U), 32); } write_radio_reg(pi, (int )((unsigned int )jtag_core | 48U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 49U), 0); write_radio_reg(pi, (int )((unsigned int )jtag_core | 50U), 0); } core = (u16 )((int )core + 1); ldv_39138: ; if ((unsigned int )core <= 1U) { goto ldv_39137; } else { } } else { pi->tx_rx_cal_radio_saveregs[0] = read_radio_reg(pi, 135); write_radio_reg(pi, 135, 41); pi->tx_rx_cal_radio_saveregs[1] = read_radio_reg(pi, 136); write_radio_reg(pi, 136, 84); pi->tx_rx_cal_radio_saveregs[2] = read_radio_reg(pi, 182); write_radio_reg(pi, 182, 41); pi->tx_rx_cal_radio_saveregs[3] = read_radio_reg(pi, 183); write_radio_reg(pi, 183, 84); pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 31); pi->tx_rx_cal_radio_saveregs[5] = read_radio_reg(pi, 33); tmp = read_phy_reg(pi, 9); if (((int )tmp & 1) == 0) { write_radio_reg(pi, 31, 4); write_radio_reg(pi, 33, 4); } else { write_radio_reg(pi, 31, 32); write_radio_reg(pi, 33, 32); } if (pi->pubpi.phy_rev <= 1U) { or_radio_reg(pi, 141, 32); or_radio_reg(pi, 188, 32); } else { and_radio_reg(pi, 141, 223); and_radio_reg(pi, 188, 223); } } return; } } static void wlc_phy_txcal_radio_cleanup_nphy(struct brcms_phy *pi ) { u16 jtag_core ; u16 core ; { if (pi->pubpi.phy_rev > 6U) { core = 0U; goto ldv_39146; ldv_39145: write_radio_reg(pi, (unsigned int )core == 0U ? 373 : 405, (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11]); write_radio_reg(pi, (unsigned int )core == 0U ? 374 : 406, (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 1]); write_radio_reg(pi, (unsigned int )core == 0U ? 375 : 407, (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 2]); write_radio_reg(pi, (unsigned int )core == 0U ? 376 : 408, (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 3]); write_radio_reg(pi, (unsigned int )core == 0U ? 377 : 409, (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 5]); if ((unsigned int )pi->pubpi.radiorev != 5U) { write_radio_reg(pi, (unsigned int )core == 0U ? 378 : 410, (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 6]); } else { } write_radio_reg(pi, (unsigned int )core == 0U ? 379 : 411, (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 7]); write_radio_reg(pi, (unsigned int )core == 0U ? 380 : 412, (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 8]); core = (u16 )((int )core + 1); ldv_39146: ; if ((unsigned int )core <= 1U) { goto ldv_39145; } else { } } else if (pi->pubpi.phy_rev > 2U) { core = 0U; goto ldv_39149; ldv_39148: jtag_core = (unsigned int )core == 0U ? 8192U : 12288U; write_radio_reg(pi, (int )((unsigned int )jtag_core | 40U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 41U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 1]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 42U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 2]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 43U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 3]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 44U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 4]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 45U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 5]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 46U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 6]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 47U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 7]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 48U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 8]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 49U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 9]); write_radio_reg(pi, (int )((unsigned int )jtag_core | 50U), (int )pi->tx_rx_cal_radio_saveregs[(int )core * 11 + 10]); core = (u16 )((int )core + 1); ldv_39149: ; if ((unsigned int )core <= 1U) { goto ldv_39148; } else { } } else { write_radio_reg(pi, 135, (int )pi->tx_rx_cal_radio_saveregs[0]); write_radio_reg(pi, 136, (int )pi->tx_rx_cal_radio_saveregs[1]); write_radio_reg(pi, 182, (int )pi->tx_rx_cal_radio_saveregs[2]); write_radio_reg(pi, 183, (int )pi->tx_rx_cal_radio_saveregs[3]); write_radio_reg(pi, 31, (int )pi->tx_rx_cal_radio_saveregs[4]); write_radio_reg(pi, 33, (int )pi->tx_rx_cal_radio_saveregs[5]); } return; } } static void wlc_phy_txcal_physetup_nphy(struct brcms_phy *pi ) { u16 val ; u16 mask ; u16 tmp ; { if (pi->pubpi.phy_rev > 2U) { pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 166); pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 167); mask = 3840U; val = 512U; val = (u16 )((unsigned int )val | 2048U); mod_phy_reg(pi, 166, (int )mask, (int )val); mod_phy_reg(pi, 167, (int )mask, (int )val); val = read_phy_reg(pi, 143); pi->tx_rx_cal_phy_saveregs[2] = val; val = (u16 )((unsigned int )val | 1536U); write_phy_reg(pi, 143, (int )val); val = read_phy_reg(pi, 165); pi->tx_rx_cal_phy_saveregs[3] = val; val = (u16 )((unsigned int )val | 1536U); write_phy_reg(pi, 165, (int )val); pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 1); mod_phy_reg(pi, 1, 32768, 0); wlc_phy_table_read_nphy(pi, 8U, 1U, 3U, 16U, (void *)(& val)); pi->tx_rx_cal_phy_saveregs[5] = val; val = 0U; wlc_phy_table_write_nphy(pi, 8U, 1U, 3U, 16U, (void const *)(& val)); wlc_phy_table_read_nphy(pi, 8U, 1U, 19U, 16U, (void *)(& val)); pi->tx_rx_cal_phy_saveregs[6] = val; val = 0U; wlc_phy_table_write_nphy(pi, 8U, 1U, 19U, 16U, (void const *)(& val)); pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 145); pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 146); if (! pi->use_int_tx_iqlo_cal_nphy) { wlc_phy_rfctrlintc_override_nphy(pi, 2, 1, 3); } else { wlc_phy_rfctrlintc_override_nphy(pi, 2, 0, 3); } wlc_phy_rfctrlintc_override_nphy(pi, 1, 2, 1); wlc_phy_rfctrlintc_override_nphy(pi, 1, 8, 2); pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 663); pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 667); mod_phy_reg(pi, 663, 1, 0); mod_phy_reg(pi, 667, 1, 0); if (pi->pubpi.phy_rev == 7U || pi->pubpi.phy_rev > 7U) { tmp = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 128, (int )tmp, 0, 0, 1); } else { } if ((int )pi->use_int_tx_iqlo_cal_nphy && ! pi->internal_tx_iqlo_cal_tapoff_intpa_nphy) { if (pi->pubpi.phy_rev == 7U) { mod_radio_reg(pi, 357, 16, 16); if (((int )pi->radio_chanspec & 61440) == 8192) { mod_radio_reg(pi, 94, 1, 0); mod_radio_reg(pi, 227, 1, 0); } else { mod_radio_reg(pi, 121, 1, 0); mod_radio_reg(pi, 254, 1, 0); } } else if (pi->pubpi.phy_rev > 7U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 0, 3, 0, 0); } else { } } else { } } else { pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 166); pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, 167); mask = 61440U; val = 8192U; val = (u16 )((unsigned int )val | 32768U); mod_phy_reg(pi, 166, (int )mask, (int )val); mod_phy_reg(pi, 167, (int )mask, (int )val); val = read_phy_reg(pi, 165); pi->tx_rx_cal_phy_saveregs[2] = val; val = (u16 )((unsigned int )val | 12288U); write_phy_reg(pi, 165, (int )val); wlc_phy_table_read_nphy(pi, 8U, 1U, 2U, 16U, (void *)(& val)); pi->tx_rx_cal_phy_saveregs[3] = val; val = (u16 )((unsigned int )val | 8192U); wlc_phy_table_write_nphy(pi, 8U, 1U, 2U, 16U, (void const *)(& val)); wlc_phy_table_read_nphy(pi, 8U, 1U, 18U, 16U, (void *)(& val)); pi->tx_rx_cal_phy_saveregs[4] = val; val = (u16 )((unsigned int )val | 8192U); wlc_phy_table_write_nphy(pi, 8U, 1U, 18U, 16U, (void const *)(& val)); pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 145); pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 146); val = ((int )pi->radio_chanspec & 61440) == 4096 ? 384U : 288U; write_phy_reg(pi, 145, (int )val); write_phy_reg(pi, 146, (int )val); } return; } } static void wlc_phy_txcal_phycleanup_nphy(struct brcms_phy *pi ) { u16 mask ; { if (pi->pubpi.phy_rev > 2U) { write_phy_reg(pi, 166, (int )pi->tx_rx_cal_phy_saveregs[0]); write_phy_reg(pi, 167, (int )pi->tx_rx_cal_phy_saveregs[1]); write_phy_reg(pi, 143, (int )pi->tx_rx_cal_phy_saveregs[2]); write_phy_reg(pi, 165, (int )pi->tx_rx_cal_phy_saveregs[3]); write_phy_reg(pi, 1, (int )pi->tx_rx_cal_phy_saveregs[4]); wlc_phy_table_write_nphy(pi, 8U, 1U, 3U, 16U, (void const *)(& pi->tx_rx_cal_phy_saveregs) + 5U); wlc_phy_table_write_nphy(pi, 8U, 1U, 19U, 16U, (void const *)(& pi->tx_rx_cal_phy_saveregs) + 6U); write_phy_reg(pi, 145, (int )pi->tx_rx_cal_phy_saveregs[7]); write_phy_reg(pi, 146, (int )pi->tx_rx_cal_phy_saveregs[8]); write_phy_reg(pi, 663, (int )pi->tx_rx_cal_phy_saveregs[9]); write_phy_reg(pi, 667, (int )pi->tx_rx_cal_phy_saveregs[10]); if (pi->pubpi.phy_rev == 7U || pi->pubpi.phy_rev > 7U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 128, 0, 0, 1, 1); } else { } wlc_phy_resetcca_nphy(pi); if ((int )pi->use_int_tx_iqlo_cal_nphy && ! pi->internal_tx_iqlo_cal_tapoff_intpa_nphy) { if (pi->pubpi.phy_rev == 7U) { if (((int )pi->radio_chanspec & 61440) == 8192) { mod_radio_reg(pi, 94, 1, 1); mod_radio_reg(pi, 227, 1, 1); } else { mod_radio_reg(pi, 121, 1, 1); mod_radio_reg(pi, 254, 1, 1); } mod_radio_reg(pi, 357, 16, 0); } else if (pi->pubpi.phy_rev > 7U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 0, 3, 1, 0); } else { } } else { } } else { mask = 61440U; mod_phy_reg(pi, 166, (int )mask, (int )pi->tx_rx_cal_phy_saveregs[0]); mod_phy_reg(pi, 167, (int )mask, (int )pi->tx_rx_cal_phy_saveregs[1]); write_phy_reg(pi, 165, (int )pi->tx_rx_cal_phy_saveregs[2]); wlc_phy_table_write_nphy(pi, 8U, 1U, 2U, 16U, (void const *)(& pi->tx_rx_cal_phy_saveregs) + 3U); wlc_phy_table_write_nphy(pi, 8U, 1U, 18U, 16U, (void const *)(& pi->tx_rx_cal_phy_saveregs) + 4U); write_phy_reg(pi, 145, (int )pi->tx_rx_cal_phy_saveregs[5]); write_phy_reg(pi, 146, (int )pi->tx_rx_cal_phy_saveregs[6]); } return; } } void wlc_phy_est_tonepwr_nphy(struct brcms_phy *pi , s32 *qdBm_pwrbuf , u8 num_samps ) { u16 tssi_reg ; s32 temp ; s32 pwrindex[2U] ; s32 idle_tssi[2U] ; s32 rssi_buf[4U] ; s32 tssival[2U] ; u8 tssi_type ; { tssi_reg = read_phy_reg(pi, 489); temp = (int )tssi_reg & 63; idle_tssi[0] = temp > 31 ? temp + -64 : temp; temp = ((int )tssi_reg >> 8) & 63; idle_tssi[1] = temp > 31 ? temp + -64 : temp; tssi_type = ((int )pi->radio_chanspec & 61440) == 4096 ? 5U : 4U; wlc_phy_poll_rssi_nphy(pi, (int )tssi_type, (s32 *)(& rssi_buf), (int )num_samps); tssival[0] = rssi_buf[0] / (int )num_samps; tssival[1] = rssi_buf[2] / (int )num_samps; pwrindex[0] = (idle_tssi[0] - tssival[0]) + 64; pwrindex[1] = (idle_tssi[1] - tssival[1]) + 64; if (pwrindex[0] < 0) { pwrindex[0] = 0; } else if (pwrindex[0] > 63) { pwrindex[0] = 63; } else { } if (pwrindex[1] < 0) { pwrindex[1] = 0; } else if (pwrindex[1] > 63) { pwrindex[1] = 63; } else { } wlc_phy_table_read_nphy(pi, 26U, 1U, (unsigned int )pwrindex[0], 32U, (void *)qdBm_pwrbuf); wlc_phy_table_read_nphy(pi, 27U, 1U, (unsigned int )pwrindex[1], 32U, (void *)qdBm_pwrbuf + 1U); return; } } static void wlc_phy_update_txcal_ladder_nphy(struct brcms_phy *pi , u16 core ) { int index ; u32 bbmult_scale ; u16 bbmult ; u16 tblentry ; struct nphy_txiqcal_ladder ladder_lo[18U] ; struct nphy_txiqcal_ladder ladder_iq[18U] ; { ladder_lo[0].percent = 3U; ladder_lo[0].g_env = 0U; ladder_lo[1].percent = 4U; ladder_lo[1].g_env = 0U; ladder_lo[2].percent = 6U; ladder_lo[2].g_env = 0U; ladder_lo[3].percent = 9U; ladder_lo[3].g_env = 0U; ladder_lo[4].percent = 13U; ladder_lo[4].g_env = 0U; ladder_lo[5].percent = 18U; ladder_lo[5].g_env = 0U; ladder_lo[6].percent = 25U; ladder_lo[6].g_env = 0U; ladder_lo[7].percent = 25U; ladder_lo[7].g_env = 1U; ladder_lo[8].percent = 25U; ladder_lo[8].g_env = 2U; ladder_lo[9].percent = 25U; ladder_lo[9].g_env = 3U; ladder_lo[10].percent = 25U; ladder_lo[10].g_env = 4U; ladder_lo[11].percent = 25U; ladder_lo[11].g_env = 5U; ladder_lo[12].percent = 25U; ladder_lo[12].g_env = 6U; ladder_lo[13].percent = 25U; ladder_lo[13].g_env = 7U; ladder_lo[14].percent = 35U; ladder_lo[14].g_env = 7U; ladder_lo[15].percent = 50U; ladder_lo[15].g_env = 7U; ladder_lo[16].percent = 71U; ladder_lo[16].g_env = 7U; ladder_lo[17].percent = 100U; ladder_lo[17].g_env = 7U; ladder_iq[0].percent = 3U; ladder_iq[0].g_env = 0U; ladder_iq[1].percent = 4U; ladder_iq[1].g_env = 0U; ladder_iq[2].percent = 6U; ladder_iq[2].g_env = 0U; ladder_iq[3].percent = 9U; ladder_iq[3].g_env = 0U; ladder_iq[4].percent = 13U; ladder_iq[4].g_env = 0U; ladder_iq[5].percent = 18U; ladder_iq[5].g_env = 0U; ladder_iq[6].percent = 25U; ladder_iq[6].g_env = 0U; ladder_iq[7].percent = 35U; ladder_iq[7].g_env = 0U; ladder_iq[8].percent = 50U; ladder_iq[8].g_env = 0U; ladder_iq[9].percent = 71U; ladder_iq[9].g_env = 0U; ladder_iq[10].percent = 100U; ladder_iq[10].g_env = 0U; ladder_iq[11].percent = 100U; ladder_iq[11].g_env = 1U; ladder_iq[12].percent = 100U; ladder_iq[12].g_env = 2U; ladder_iq[13].percent = 100U; ladder_iq[13].g_env = 3U; ladder_iq[14].percent = 100U; ladder_iq[14].g_env = 4U; ladder_iq[15].percent = 100U; ladder_iq[15].g_env = 5U; ladder_iq[16].percent = 100U; ladder_iq[16].g_env = 6U; ladder_iq[17].percent = 100U; ladder_iq[17].g_env = 7U; bbmult = (unsigned int )core == 0U ? (u16 )((int )pi->nphy_txcal_bbmult >> 8) : (unsigned int )pi->nphy_txcal_bbmult & 255U; index = 0; goto ldv_39183; ldv_39182: bbmult_scale = (u32 )((int )ladder_lo[index].percent * (int )bbmult); bbmult_scale = bbmult_scale / 100U; tblentry = ((int )((u16 )bbmult_scale) << 8U) | (int )((u16 )ladder_lo[index].g_env); wlc_phy_table_write_nphy(pi, 15U, 1U, (u32 )index, 16U, (void const *)(& tblentry)); bbmult_scale = (u32 )((int )ladder_iq[index].percent * (int )bbmult); bbmult_scale = bbmult_scale / 100U; tblentry = ((int )((u16 )bbmult_scale) << 8U) | (int )((u16 )ladder_iq[index].g_env); wlc_phy_table_write_nphy(pi, 15U, 1U, (u32 )(index + 32), 16U, (void const *)(& tblentry)); index = index + 1; ldv_39183: ; if (index <= 17) { goto ldv_39182; } else { } return; } } static u8 wlc_phy_txpwr_idx_cur_get_nphy(struct brcms_phy *pi , u8 core ) { u16 tmp ; { tmp = read_phy_reg(pi, (unsigned int )core == 0U ? 493 : 494); tmp = (u16 )(((int )tmp & 32512) >> 8); return ((u8 )tmp); } } static void wlc_phy_txpwr_idx_cur_set_nphy(struct brcms_phy *pi , u8 idx0 , u8 idx1 ) { { mod_phy_reg(pi, 487, 127, (int )idx0); if (pi->pubpi.phy_rev > 1U) { mod_phy_reg(pi, 546, 255, (int )idx1); } else { } return; } } static u16 wlc_phy_ipa_get_bbmult_nphy(struct brcms_phy *pi ) { u16 m0m1 ; { wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& m0m1)); return (m0m1); } } static void wlc_phy_ipa_set_bbmult_nphy(struct brcms_phy *pi , u8 m0 , u8 m1 ) { u16 m0m1 ; { m0m1 = (unsigned short )((int )((short )((int )m0 << 8)) | (int )((short )m1)); wlc_phy_table_write_nphy(pi, 15U, 1U, 87U, 16U, (void const *)(& m0m1)); wlc_phy_table_write_nphy(pi, 15U, 1U, 95U, 16U, (void const *)(& m0m1)); return; } } static void wlc_phy_papd_cal_setup_nphy(struct brcms_phy *pi , struct nphy_papd_restore_state *state , u8 core ) { s32 tone_freq ; u8 off_core ; u16 mixgain ; u16 tmp ; { mixgain = 0U; off_core = (u8 )((unsigned int )core ^ 1U); if (pi->pubpi.phy_rev > 6U) { if (pi->pubpi.phy_rev == 7U || pi->pubpi.phy_rev > 7U) { tmp = wlc_phy_read_lpf_bw_ctl_nphy(pi, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 128, (int )tmp, 0, 0, 1); } else { } if (((int )pi->radio_chanspec & 61440) == 8192) { if ((unsigned int )pi->pubpi.radiorev == 5U) { mixgain = (unsigned int )core == 0U ? 32U : 0U; } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { mixgain = 0U; } else if ((unsigned int )pi->pubpi.radiorev <= 4U || (unsigned int )pi->pubpi.radiorev == 6U) { mixgain = 0U; } else { } } else if ((unsigned int )pi->pubpi.radiorev == 4U || (unsigned int )pi->pubpi.radiorev == 6U) { mixgain = 80U; } else if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 7U) || (unsigned int )pi->pubpi.radiorev == 8U) { mixgain = 0U; } else { } wlc_phy_rfctrl_override_nphy_rev7(pi, 2048, (int )mixgain, (int )((u8 )(1 << (int )core)), 0, 0); wlc_phy_rfctrl_override_1tomany_nphy(pi, 2, 1, (int )((u8 )(1 << (int )core)), 0); wlc_phy_rfctrl_override_1tomany_nphy(pi, 2, 0, (int )((u8 )(1 << (int )off_core)), 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 0, 3, 0, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 4, 1, (int )((u8 )(1 << (int )core)), 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1, 0, (int )((u8 )(1 << (int )core)), 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 2, 1, (int )((u8 )(1 << (int )core)), 0, 2); wlc_phy_rfctrl_override_nphy_rev7(pi, 256, 0, (int )((u8 )(1 << (int )core)), 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 512, 1, (int )((u8 )(1 << (int )core)), 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1024, 0, (int )((u8 )(1 << (int )core)), 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 1, (int )((u8 )(1 << (int )core)), 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 32, 0, (int )((u8 )(1 << (int )core)), 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 16, 0, (int )((u8 )(1 << (int )core)), 0, 1); state->afectrl[(int )core] = read_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167); state->afeoverride[(int )core] = read_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165); state->afectrl[(int )off_core] = read_phy_reg(pi, (unsigned int )core == 0U ? 167 : 166); state->afeoverride[(int )off_core] = read_phy_reg(pi, (unsigned int )core == 0U ? 165 : 143); mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, 4, 0); mod_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165, 4, 4); mod_phy_reg(pi, (unsigned int )core == 0U ? 167 : 166, 4, 4); mod_phy_reg(pi, (unsigned int )core == 0U ? 165 : 143, 4, 4); if (((int )pi->radio_chanspec & 61440) == 8192) { state->pwrup[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 382 : 414); state->atten[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 381 : 413); state->pwrup[(int )off_core] = read_radio_reg(pi, (unsigned int )off_core == 0U ? 382 : 414); state->atten[(int )off_core] = read_radio_reg(pi, (unsigned int )off_core == 0U ? 381 : 413); write_radio_reg(pi, (unsigned int )core == 0U ? 382 : 414, 12); if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { write_radio_reg(pi, (unsigned int )core == 0U ? 381 : 413, 240); } else if ((unsigned int )pi->pubpi.radiorev == 5U) { write_radio_reg(pi, (unsigned int )core == 0U ? 381 : 413, (unsigned int )core == 0U ? 247 : 242); } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { write_radio_reg(pi, (unsigned int )core == 0U ? 381 : 413, 240); } else { } write_radio_reg(pi, (unsigned int )off_core == 0U ? 382 : 414, 0); write_radio_reg(pi, (unsigned int )off_core == 0U ? 381 : 413, 255); } else { state->pwrup[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 384 : 416); state->atten[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 383 : 415); state->pwrup[(int )off_core] = read_radio_reg(pi, (unsigned int )off_core == 0U ? 384 : 416); state->atten[(int )off_core] = read_radio_reg(pi, (unsigned int )off_core == 0U ? 383 : 415); write_radio_reg(pi, (unsigned int )core == 0U ? 384 : 416, 12); if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { write_radio_reg(pi, (unsigned int )core == 0U ? 383 : 415, 244); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 383 : 415, 240); } write_radio_reg(pi, (unsigned int )off_core == 0U ? 384 : 416, 0); write_radio_reg(pi, (unsigned int )off_core == 0U ? 383 : 415, 255); } tone_freq = 4000; wlc_phy_tx_tone_nphy(pi, (u32 )tone_freq, 181, 0, 0, 0); mod_phy_reg(pi, (unsigned int )core == 0U ? 663 : 667, 1, 1); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 8192, 8192); mod_phy_reg(pi, (unsigned int )off_core == 0U ? 663 : 667, 1, 0); mod_phy_reg(pi, (unsigned int )off_core == 0U ? 675 : 676, 8192, 0); } else { wlc_phy_rfctrl_override_nphy(pi, 4096, 0, 3, 0); wlc_phy_rfctrl_override_nphy(pi, 8, 1, 0, 0); wlc_phy_rfctrl_override_nphy(pi, 1, 0, 3, 0); wlc_phy_rfctrl_override_nphy(pi, 4, 1, 3, 0); wlc_phy_rfctrl_override_nphy(pi, 2, 1, 3, 0); state->afectrl[(int )core] = read_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167); state->afeoverride[(int )core] = read_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165); mod_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, 7, 0); mod_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165, 7, 7); state->vga_master[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 24690 : 28786); write_radio_reg(pi, (unsigned int )core == 0U ? 24690 : 28786, 43); if (((int )pi->radio_chanspec & 61440) == 8192) { state->fbmix[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 24698 : 28794); state->intpa_master[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 8255 : 12351); write_radio_reg(pi, (unsigned int )core == 0U ? 24698 : 28794, 3); write_radio_reg(pi, (unsigned int )core == 0U ? 8255 : 12351, 4); } else { state->fbmix[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 24697 : 28793); state->intpa_master[(int )core] = read_radio_reg(pi, (unsigned int )core == 0U ? 8245 : 12341); write_radio_reg(pi, (unsigned int )core == 0U ? 24697 : 28793, 3); write_radio_reg(pi, (unsigned int )core == 0U ? 8245 : 12341, 4); } tone_freq = 4000; wlc_phy_tx_tone_nphy(pi, (u32 )tone_freq, 181, 0, 0, 0); mod_phy_reg(pi, (unsigned int )core == 0U ? 663 : 667, 1, 1); mod_phy_reg(pi, (unsigned int )off_core == 0U ? 663 : 667, 1, 0); wlc_phy_rfctrl_override_nphy(pi, 8, 0, 3, 0); } return; } } static void wlc_phy_papd_cal_cleanup_nphy(struct brcms_phy *pi , struct nphy_papd_restore_state *state ) { u8 core ; { wlc_phy_stopplayback_nphy(pi); if (pi->pubpi.phy_rev > 6U) { core = 0U; goto ldv_39219; ldv_39218: ; if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, (unsigned int )core == 0U ? 382 : 414, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 381 : 413, (int )state->atten[(int )core]); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 384 : 416, 0); write_radio_reg(pi, (unsigned int )core == 0U ? 383 : 415, (int )state->atten[(int )core]); } core = (u8 )((int )core + 1); ldv_39219: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_39218; } else { } if ((unsigned int )pi->pubpi.radiorev == 4U || (unsigned int )pi->pubpi.radiorev == 6U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 4, 1, 3, 0, 0); } else { wlc_phy_rfctrl_override_nphy_rev7(pi, 4, 0, 3, 1, 0); } wlc_phy_rfctrl_override_nphy_rev7(pi, 2, 0, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1, 0, 3, 1, 2); wlc_phy_rfctrl_override_nphy_rev7(pi, 4, 0, 3, 1, 2); wlc_phy_rfctrl_override_nphy_rev7(pi, 2048, 1, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 0, 3, 1, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 2048, 0, 3, 1, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 4096, 0, 3, 1, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 4, 1, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1, 0, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 2, 1, 3, 1, 2); wlc_phy_rfctrl_override_nphy_rev7(pi, 256, 0, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 512, 1, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1024, 0, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 1, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 32, 0, 3, 1, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 16, 0, 3, 1, 1); core = 0U; goto ldv_39222; ldv_39221: write_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, (int )state->afectrl[(int )core]); write_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165, (int )state->afeoverride[(int )core]); core = (u8 )((int )core + 1); ldv_39222: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_39221; } else { } wlc_phy_ipa_set_bbmult_nphy(pi, (int )((u8 )((int )state->mm >> 8)), (int )((u8 )state->mm)); if (pi->pubpi.phy_rev == 7U || pi->pubpi.phy_rev > 7U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 128, 0, 0, 1, 1); } else { } } else { wlc_phy_rfctrl_override_nphy(pi, 4096, 0, 3, 1); wlc_phy_rfctrl_override_nphy(pi, 8192, 0, 3, 1); wlc_phy_rfctrl_override_nphy(pi, 1, 0, 3, 1); wlc_phy_rfctrl_override_nphy(pi, 4, 0, 3, 1); wlc_phy_rfctrl_override_nphy(pi, 2, 0, 3, 1); core = 0U; goto ldv_39225; ldv_39224: write_radio_reg(pi, (unsigned int )core == 0U ? 24690 : 28786, (int )state->vga_master[(int )core]); if (((int )pi->radio_chanspec & 61440) == 8192) { write_radio_reg(pi, (unsigned int )core == 0U ? 24698 : 28794, (int )state->fbmix[(int )core]); write_radio_reg(pi, (unsigned int )core == 0U ? 8255 : 12351, (int )state->intpa_master[(int )core]); } else { write_radio_reg(pi, (unsigned int )core == 0U ? 24697 : 28793, (int )state->fbmix[(int )core]); write_radio_reg(pi, (unsigned int )core == 0U ? 8245 : 12341, (int )state->intpa_master[(int )core]); } write_phy_reg(pi, (unsigned int )core == 0U ? 166 : 167, (int )state->afectrl[(int )core]); write_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165, (int )state->afeoverride[(int )core]); core = (u8 )((int )core + 1); ldv_39225: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_39224; } else { } wlc_phy_ipa_set_bbmult_nphy(pi, (int )((u8 )((int )state->mm >> 8)), (int )((u8 )state->mm)); wlc_phy_rfctrl_override_nphy(pi, 8, 0, 3, 1); } return; } } static void wlc_phy_a1_nphy(struct brcms_phy *pi , u8 core , u32 winsz , u32 start , u32 end ) { u32 *buf ; u32 *src ; u32 *dst ; u32 sz ; void *tmp ; u32 phy_a1 ; u32 phy_a2 ; s32 phy_a3 ; s32 phy_a4 ; s32 phy_a5 ; s32 phy_a6 ; s32 phy_a7 ; u32 _min1 ; u32 _min2 ; u32 __min1 ; u32 __min2 ; u32 tmp___0 ; u32 tmp___1 ; { sz = (end - start) + 1U; tmp = kmalloc(512UL, 32U); buf = (u32 *)tmp; if ((unsigned long )buf == (unsigned long )((u32 *)0U)) { return; } else { } src = buf; dst = buf + 64UL; wlc_phy_table_read_nphy(pi, (unsigned int )core == 0U ? 31U : 33U, 64U, 0U, 32U, (void *)src); ldv_39253: _min1 = end; _min2 = winsz >> 1; phy_a1 = end - (_min1 < _min2 ? _min1 : _min2); __min1 = 63U; __min2 = (winsz >> 1) + end; phy_a2 = __min1 < __min2 ? __min1 : __min2; phy_a3 = (s32 )((phy_a2 - phy_a1) + 1U); phy_a6 = 0; phy_a7 = 0; ldv_39251: wlc_phy_papd_decode_epsilon(*(src + (unsigned long )phy_a2), & phy_a4, & phy_a5); phy_a6 = phy_a6 + phy_a4; phy_a7 = phy_a7 + phy_a5; tmp___0 = phy_a2; phy_a2 = phy_a2 - 1U; if (tmp___0 != phy_a1) { goto ldv_39251; } else { } phy_a6 = phy_a6 / phy_a3; phy_a7 = phy_a7 / phy_a3; *(dst + (unsigned long )end) = ((unsigned int )phy_a7 << 13) | ((unsigned int )phy_a6 & 8191U); tmp___1 = end; end = end - 1U; if (tmp___1 != start) { goto ldv_39253; } else { } wlc_phy_table_write_nphy(pi, (unsigned int )core == 0U ? 31U : 33U, sz, start, 32U, (void const *)dst); kfree((void const *)buf); return; } } static void wlc_phy_a2_nphy(struct brcms_phy *pi , struct nphy_ipa_txcalgains *txgains , enum phy_cal_mode cal_mode , u8 core ) { u16 phy_a1 ; u16 phy_a2 ; u16 phy_a3 ; u16 phy_a4 ; u16 phy_a5 ; bool phy_a6 ; u8 phy_a7 ; u8 m[2U] ; u32 phy_a8 ; struct nphy_txgains phy_a9 ; uint countdown ; u16 tmp ; uint countdown___0 ; u16 tmp___0 ; { phy_a8 = 0U; if (pi->pubpi.phy_rev <= 2U) { return; } else { } phy_a7 = (unsigned int )core == 0U; phy_a6 = (bool )((unsigned int )cal_mode == 4U || (unsigned int )cal_mode == 5U); if (pi->pubpi.phy_rev > 6U) { phy_a9 = wlc_phy_get_tx_gain_nphy(pi); if (((int )pi->radio_chanspec & 61440) == 8192) { phy_a5 = (u16 )(((((int )((short )((int )phy_a9.txlpf[(int )core] << 15)) | (int )((short )((int )phy_a9.txgm[(int )core] << 12))) | (int )((short )((int )phy_a9.pga[(int )core] << 8))) | (int )((short )((int )txgains->gains.pad[(int )core] << 3))) | (int )((short )phy_a9.ipa[(int )core])); } else { phy_a5 = (u16 )(((((int )((short )((int )phy_a9.txlpf[(int )core] << 15)) | (int )((short )((int )phy_a9.txgm[(int )core] << 12))) | (int )((short )((int )txgains->gains.pga[(int )core] << 8))) | (int )((short )((int )phy_a9.pad[(int )core] << 3))) | (int )((short )phy_a9.ipa[(int )core])); } wlc_phy_rfctrl_override_1tomany_nphy(pi, 4, (int )phy_a5, (int )((u8 )(1 << (int )core)), 0); if (((int )pi->radio_chanspec & 61440) == 8192) { if ((unsigned int )pi->pubpi.radiorev <= 4U || (unsigned int )pi->pubpi.radiorev == 6U) { m[(int )core] = (unsigned int )pi->bw == 3072U ? 60U : 79U; } else { m[(int )core] = (unsigned int )pi->bw == 3072U ? 45U : 64U; } } else { m[(int )core] = (unsigned int )pi->bw == 3072U ? 75U : 107U; } m[(int )phy_a7] = 0U; wlc_phy_ipa_set_bbmult_nphy(pi, (int )m[0], (int )m[1]); phy_a2 = 63U; if (((int )pi->radio_chanspec & 61440) == 8192) { if ((unsigned int )pi->pubpi.radiorev == 4U || (unsigned int )pi->pubpi.radiorev == 6U) { phy_a1 = 30U; phy_a3 = 30U; } else { phy_a1 = 25U; phy_a3 = 25U; } } else if (((unsigned int )pi->pubpi.radiorev == 5U || (unsigned int )pi->pubpi.radiorev == 7U) || (unsigned int )pi->pubpi.radiorev == 8U) { phy_a1 = 25U; phy_a3 = 25U; } else { phy_a1 = 35U; phy_a3 = 35U; } if ((unsigned int )cal_mode == 4U) { if ((unsigned int )pi->pubpi.radiorev == 5U && ((int )pi->radio_chanspec & 61440) == 8192) { phy_a1 = 55U; } else if (((unsigned int )pi->pubpi.radiorev == 7U && ((int )pi->radio_chanspec & 61440) == 8192) || ((unsigned int )pi->pubpi.radiorev == 8U && ((int )pi->radio_chanspec & 61440) == 8192)) { phy_a1 = 60U; } else { phy_a1 = 63U; } } else if ((unsigned int )cal_mode != 0U && (unsigned int )cal_mode != 5U) { phy_a1 = 35U; phy_a3 = 35U; } else { } mod_phy_reg(pi, (unsigned int )core == 0U ? 663 : 667, 1, 1); mod_phy_reg(pi, (unsigned int )phy_a7 == 0U ? 663 : 667, 1, 0); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 8192, 8192); mod_phy_reg(pi, (unsigned int )phy_a7 == 0U ? 675 : 676, 8192, 0); write_phy_reg(pi, 673, 128); write_phy_reg(pi, 674, 256); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 112, 176); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 1792, 2816); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 7, 3); write_phy_reg(pi, 741, 32); mod_phy_reg(pi, 672, 63, (int )phy_a3); mod_phy_reg(pi, 671, 63, (int )phy_a1); mod_phy_reg(pi, 671, 16128, (int )phy_a2 << 8U); wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 1, (unsigned int )core == 0U ? 1 : 2, 0, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 0, (unsigned int )core == 0U ? 2 : 1, 0, 0); write_phy_reg(pi, 702, 1); countdown = 10000009U; goto ldv_39273; ldv_39272: __const_udelay(42950UL); countdown = countdown - 10U; ldv_39273: tmp = read_phy_reg(pi, 702); if ((unsigned int )tmp != 0U && countdown > 9U) { goto ldv_39272; } else { } wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 0, 3, 0, 0); wlc_phy_table_write_nphy(pi, (unsigned int )core == 0U ? 31U : 33U, 1U, (u32 )phy_a3, 32U, (void const *)(& phy_a8)); if ((unsigned int )cal_mode != 4U) { if (((int )pi->radio_chanspec & 61440) == 4096) { wlc_phy_a1_nphy(pi, (int )core, 5U, 0U, 35U); } else { } } else { } wlc_phy_rfctrl_override_1tomany_nphy(pi, 4, (int )phy_a5, (int )((u8 )(1 << (int )core)), 1); } else { if ((unsigned long )txgains != (unsigned long )((struct nphy_ipa_txcalgains *)0)) { if ((int )txgains->useindex) { phy_a4 = 15U - (unsigned int )((u16 )((int )txgains->index >> 3)); if (((int )pi->radio_chanspec & 61440) == 8192) { if (pi->pubpi.phy_rev > 5U && (pi->sh)->chip == 47162U) { phy_a5 = (u16 )((int )((short )((int )phy_a4 << 8)) | 4343); } else if (pi->pubpi.phy_rev > 5U) { phy_a5 = (u16 )((int )((short )((int )phy_a4 << 8)) | 247); } else if (pi->pubpi.phy_rev == 5U) { phy_a5 = (u16 )((int )((short )((int )phy_a4 << 8)) | 4343); } else { phy_a5 = (u16 )((int )((short )((int )phy_a4 << 8)) | 20727); } } else { phy_a5 = (u16 )((int )((short )((int )phy_a4 << 8)) | 28919); } wlc_phy_rfctrl_override_nphy(pi, 8192, (int )phy_a5, (int )((u8 )(1 << (int )core)), 0); } else { wlc_phy_rfctrl_override_nphy(pi, 8192, 23543, (int )((u8 )(1 << (int )core)), 0); } } else { } if (((int )pi->radio_chanspec & 61440) == 8192) { m[(int )core] = (unsigned int )pi->bw == 3072U ? 45U : 64U; } else { m[(int )core] = (unsigned int )pi->bw == 3072U ? 75U : 107U; } m[(int )phy_a7] = 0U; wlc_phy_ipa_set_bbmult_nphy(pi, (int )m[0], (int )m[1]); phy_a2 = 63U; if ((unsigned int )cal_mode == 0U) { phy_a1 = 25U; phy_a3 = 25U; } else if ((unsigned int )cal_mode == 5U) { phy_a1 = 25U; phy_a3 = 25U; } else if ((unsigned int )cal_mode == 4U) { phy_a1 = 63U; phy_a3 = 25U; } else { phy_a1 = 25U; phy_a3 = 25U; } mod_phy_reg(pi, (unsigned int )core == 0U ? 663 : 667, 1, 1); mod_phy_reg(pi, (unsigned int )phy_a7 == 0U ? 663 : 667, 1, 0); if (pi->pubpi.phy_rev > 5U) { mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 8192, 8192); mod_phy_reg(pi, (unsigned int )phy_a7 == 0U ? 675 : 676, 8192, 0); write_phy_reg(pi, 673, 32); write_phy_reg(pi, 674, 96); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 240, 144); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 3840, 2304); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 15, 2); write_phy_reg(pi, 741, 32); } else { mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 2048, 2048); mod_phy_reg(pi, (unsigned int )phy_a7 == 0U ? 675 : 676, 2048, 0); write_phy_reg(pi, 673, 128); write_phy_reg(pi, 674, 1536); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 112, 0); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 1792, 0); mod_phy_reg(pi, (unsigned int )core == 0U ? 675 : 676, 7, 3); mod_phy_reg(pi, 672, 16128, 8192); } mod_phy_reg(pi, 672, 63, (int )phy_a3); mod_phy_reg(pi, 671, 63, (int )phy_a1); mod_phy_reg(pi, 671, 16128, (int )phy_a2 << 8U); wlc_phy_rfctrl_override_nphy(pi, 8, 1, 3, 0); write_phy_reg(pi, 702, 1); countdown___0 = 10000009U; goto ldv_39277; ldv_39276: __const_udelay(42950UL); countdown___0 = countdown___0 - 10U; ldv_39277: tmp___0 = read_phy_reg(pi, 702); if ((unsigned int )tmp___0 != 0U && countdown___0 > 9U) { goto ldv_39276; } else { } wlc_phy_rfctrl_override_nphy(pi, 8, 0, 3, 0); wlc_phy_table_write_nphy(pi, (unsigned int )core == 0U ? 31U : 33U, 1U, (u32 )phy_a3, 32U, (void const *)(& phy_a8)); if ((unsigned int )cal_mode != 4U) { wlc_phy_a1_nphy(pi, (int )core, 5U, 0U, 40U); } else { } } return; } } static u8 wlc_phy_a3_nphy(struct brcms_phy *pi , u8 start_gain , u8 core ) { int phy_a1 ; int phy_a2 ; bool phy_a3 ; struct nphy_ipa_txcalgains phy_a4 ; bool phy_a5 ; bool phy_a6 ; s32 phy_a7 ; s32 phy_a8 ; u32 phy_a9 ; int phy_a10 ; bool phy_a11 ; int phy_a12 ; u8 phy_a13 ; u8 phy_a14 ; u8 *phy_a15 ; { phy_a5 = 0; phy_a6 = 1; phy_a11 = 0; phy_a13 = 0U; phy_a15 = (u8 *)0U; phy_a4.useindex = 1; phy_a12 = (int )start_gain; if (pi->pubpi.phy_rev > 6U) { phy_a2 = 20; phy_a1 = 1; if (((int )pi->radio_chanspec & 61440) == 8192) { if ((unsigned int )pi->pubpi.radiorev == 5U) { phy_a15 = (u8 *)(& pad_gain_codes_used_2057rev5); phy_a13 = 19U; } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { phy_a15 = (u8 *)(& pad_gain_codes_used_2057rev7); phy_a13 = 14U; } else { phy_a15 = (u8 *)(& pad_all_gain_codes_2057); phy_a13 = 31U; } } else { phy_a15 = (u8 *)(& pga_all_gain_codes_2057); phy_a13 = 15U; } phy_a14 = 0U; phy_a10 = 0; goto ldv_39309; ldv_39308: ; if (((int )pi->radio_chanspec & 61440) == 8192) { phy_a4.gains.pad[(int )core] = (unsigned short )*(phy_a15 + (unsigned long )phy_a12); } else { phy_a4.gains.pga[(int )core] = (unsigned short )*(phy_a15 + (unsigned long )phy_a12); } wlc_phy_a2_nphy(pi, & phy_a4, 4, (int )core); wlc_phy_table_read_nphy(pi, (unsigned int )core == 0U ? 31U : 33U, 1U, 63U, 32U, (void *)(& phy_a9)); wlc_phy_papd_decode_epsilon(phy_a9, & phy_a7, & phy_a8); phy_a3 = (bool )(((phy_a7 == 4095 || phy_a7 == -4096) || phy_a8 == 4095) || phy_a8 == -4096); if (! phy_a6 && (int )phy_a3 != (int )phy_a5) { if (! phy_a3) { phy_a12 = phy_a12 - (int )((unsigned char )phy_a1); } else { } phy_a11 = 1; goto ldv_39307; } else { } if ((int )phy_a3) { phy_a12 = (int )((unsigned char )phy_a1) + phy_a12; } else { phy_a12 = phy_a12 - (int )((unsigned char )phy_a1); } if ((int )phy_a14 > phy_a12 || (int )phy_a13 < phy_a12) { if ((int )phy_a14 > phy_a12) { phy_a12 = (int )phy_a14; } else { phy_a12 = (int )phy_a13; } phy_a11 = 1; goto ldv_39307; } else { } phy_a6 = 0; phy_a5 = phy_a3; phy_a10 = phy_a10 + 1; ldv_39309: ; if (phy_a10 < phy_a2) { goto ldv_39308; } else { } ldv_39307: ; } else { phy_a2 = 10; phy_a1 = 8; phy_a10 = 0; goto ldv_39312; ldv_39311: phy_a4.index = (unsigned char )phy_a12; wlc_phy_a2_nphy(pi, & phy_a4, 4, (int )core); wlc_phy_table_read_nphy(pi, (unsigned int )core == 0U ? 31U : 33U, 1U, 63U, 32U, (void *)(& phy_a9)); wlc_phy_papd_decode_epsilon(phy_a9, & phy_a7, & phy_a8); phy_a3 = (bool )(((phy_a7 == 4095 || phy_a7 == -4096) || phy_a8 == 4095) || phy_a8 == -4096); if (! phy_a6 && (int )phy_a3 != (int )phy_a5) { if (! phy_a3) { phy_a12 = phy_a12 - (int )((unsigned char )phy_a1); } else { } phy_a11 = 1; goto ldv_39310; } else { } if ((int )phy_a3) { phy_a12 = (int )((unsigned char )phy_a1) + phy_a12; } else { phy_a12 = phy_a12 - (int )((unsigned char )phy_a1); } if (phy_a12 < 0 || phy_a12 > 127) { if (phy_a12 < 0) { phy_a12 = 0; } else { phy_a12 = 127; } phy_a11 = 1; goto ldv_39310; } else { } phy_a6 = 0; phy_a5 = phy_a3; phy_a10 = phy_a10 + 1; ldv_39312: ; if (phy_a10 < phy_a2) { goto ldv_39311; } else { } ldv_39310: ; } if (pi->pubpi.phy_rev > 6U) { return (*(phy_a15 + (unsigned long )phy_a12)); } else { return ((u8 )phy_a12); } } } static void wlc_phy_a4(struct brcms_phy *pi , bool full_cal ) { struct nphy_ipa_txcalgains phy_b1[2U] ; struct nphy_papd_restore_state phy_b2 ; bool phy_b3 ; u8 phy_b4 ; u8 phy_b5 ; s16 phy_b6 ; s16 phy_b7 ; s16 phy_b8 ; u16 phy_b9 ; s16 phy_b10 ; s16 phy_b11 ; s16 phy_b12 ; u32 tmp ; u8 tmp___0 ; s32 i ; s32 val ; int eps_offset ; { phy_b11 = 0; phy_b12 = 0; phy_b7 = 0; phy_b8 = 0; phy_b6 = 0; if ((unsigned int )pi->nphy_papd_skip == 1U) { return; } else { } tmp = bcma_read32(pi->d11core, 288); phy_b3 = (tmp & 1U) == 0U; if (! phy_b3) { wlapi_suspend_mac_and_wait((pi->sh)->physhim); } else { } wlc_phy_stay_in_carriersearch_nphy(pi, 1); pi->nphy_force_papd_cal = 0; phy_b5 = 0U; goto ldv_39330; ldv_39329: tmp___0 = wlc_phy_txpwr_idx_cur_get_nphy(pi, (int )phy_b5); pi->nphy_papd_tx_gain_at_last_cal[(int )phy_b5] = (u16 )tmp___0; phy_b5 = (u8 )((int )phy_b5 + 1); ldv_39330: ; if ((int )pi->pubpi.phy_corenum > (int )phy_b5) { goto ldv_39329; } else { } pi->nphy_papd_last_cal = (pi->sh)->now; pi->nphy_papd_recal_counter = pi->nphy_papd_recal_counter + 1U; phy_b4 = pi->nphy_txpwrctrl; wlc_phy_txpwrctrl_enable_nphy(pi, 0); wlc_phy_table_write_nphy(pi, 32U, 64U, 0U, 32U, (void const *)(& nphy_papd_scaltbl)); wlc_phy_table_write_nphy(pi, 34U, 64U, 0U, 32U, (void const *)(& nphy_papd_scaltbl)); phy_b9 = read_phy_reg(pi, 1); mod_phy_reg(pi, 1, 32768, 0); phy_b5 = 0U; goto ldv_39338; ldv_39337: val = 0; i = 0; goto ldv_39335; ldv_39334: wlc_phy_table_write_nphy(pi, (unsigned int )phy_b5 == 0U ? 31U : 33U, 1U, (u32 )i, 32U, (void const *)(& val)); i = i + 1; ldv_39335: ; if (i <= 63) { goto ldv_39334; } else { } phy_b5 = (u8 )((int )phy_b5 + 1); ldv_39338: ; if ((int )pi->pubpi.phy_corenum > (int )phy_b5) { goto ldv_39337; } else { } wlc_phy_ipa_restore_tx_digi_filts_nphy(pi); phy_b2.mm = wlc_phy_ipa_get_bbmult_nphy(pi); phy_b5 = 0U; goto ldv_39344; ldv_39343: wlc_phy_papd_cal_setup_nphy(pi, & phy_b2, (int )phy_b5); if (pi->pubpi.phy_rev > 6U) { if (((int )pi->radio_chanspec & 61440) == 8192) { if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { pi->nphy_papd_cal_gain_index[(int )phy_b5] = 23U; } else if ((unsigned int )pi->pubpi.radiorev == 5U) { pi->nphy_papd_cal_gain_index[(int )phy_b5] = 0U; pi->nphy_papd_cal_gain_index[(int )phy_b5] = wlc_phy_a3_nphy(pi, (int )pi->nphy_papd_cal_gain_index[(int )phy_b5], (int )phy_b5); } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { pi->nphy_papd_cal_gain_index[(int )phy_b5] = 0U; pi->nphy_papd_cal_gain_index[(int )phy_b5] = wlc_phy_a3_nphy(pi, (int )pi->nphy_papd_cal_gain_index[(int )phy_b5], (int )phy_b5); } else { } phy_b1[(int )phy_b5].gains.pad[(int )phy_b5] = (u16 )pi->nphy_papd_cal_gain_index[(int )phy_b5]; } else { pi->nphy_papd_cal_gain_index[(int )phy_b5] = 0U; pi->nphy_papd_cal_gain_index[(int )phy_b5] = wlc_phy_a3_nphy(pi, (int )pi->nphy_papd_cal_gain_index[(int )phy_b5], (int )phy_b5); phy_b1[(int )phy_b5].gains.pga[(int )phy_b5] = (u16 )pi->nphy_papd_cal_gain_index[(int )phy_b5]; } } else { phy_b1[(int )phy_b5].useindex = 1; phy_b1[(int )phy_b5].index = 16U; phy_b1[(int )phy_b5].index = wlc_phy_a3_nphy(pi, (int )phy_b1[(int )phy_b5].index, (int )phy_b5); pi->nphy_papd_cal_gain_index[(int )phy_b5] = 15U - (unsigned int )((u8 )((int )phy_b1[(int )phy_b5].index >> 3)); } switch ((int )pi->nphy_papd_cal_type) { case 0: wlc_phy_a2_nphy(pi, (struct nphy_ipa_txcalgains *)(& phy_b1) + (unsigned long )phy_b5, 0, (int )phy_b5); goto ldv_39341; case 1: wlc_phy_a2_nphy(pi, (struct nphy_ipa_txcalgains *)(& phy_b1) + (unsigned long )phy_b5, 5, (int )phy_b5); goto ldv_39341; } ldv_39341: ; if (pi->pubpi.phy_rev > 6U) { wlc_phy_papd_cal_cleanup_nphy(pi, & phy_b2); } else { } phy_b5 = (u8 )((int )phy_b5 + 1); ldv_39344: ; if ((int )pi->pubpi.phy_corenum > (int )phy_b5) { goto ldv_39343; } else { } if (pi->pubpi.phy_rev <= 6U) { wlc_phy_papd_cal_cleanup_nphy(pi, & phy_b2); } else { } phy_b5 = 0U; goto ldv_39348; ldv_39347: eps_offset = 0; if (pi->pubpi.phy_rev > 6U) { if (((int )pi->radio_chanspec & 61440) == 8192) { if ((unsigned int )pi->pubpi.radiorev == 3U) { eps_offset = -2; } else if ((unsigned int )pi->pubpi.radiorev == 5U) { eps_offset = 3; } else { eps_offset = -1; } } else { eps_offset = 2; } if (((int )pi->radio_chanspec & 61440) == 8192) { phy_b8 = (s16 )phy_b1[(int )phy_b5].gains.pad[(int )phy_b5]; phy_b10 = 0; if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { phy_b12 = (s16 )(~ ((int )nphy_papd_padgain_dlt_2g_2057rev3n4[(int )phy_b8]) / 2); phy_b10 = -1; } else if ((unsigned int )pi->pubpi.radiorev == 5U) { phy_b12 = (s16 )(~ ((int )nphy_papd_padgain_dlt_2g_2057rev5[(int )phy_b8]) / 2); } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { phy_b12 = (s16 )(~ ((int )nphy_papd_padgain_dlt_2g_2057rev7[(int )phy_b8]) / 2); } else { } } else { phy_b7 = (s16 )phy_b1[(int )phy_b5].gains.pga[(int )phy_b5]; if (((unsigned int )pi->pubpi.radiorev == 3U || (unsigned int )pi->pubpi.radiorev == 4U) || (unsigned int )pi->pubpi.radiorev == 6U) { phy_b11 = (s16 )(~ ((int )nphy_papd_pgagain_dlt_5g_2057[(int )phy_b7]) / 2); } else if ((unsigned int )pi->pubpi.radiorev == 7U || (unsigned int )pi->pubpi.radiorev == 8U) { phy_b11 = (s16 )(~ ((int )nphy_papd_pgagain_dlt_5g_2057rev7[(int )phy_b7]) / 2); } else { } phy_b10 = -9; } if (((int )pi->radio_chanspec & 61440) == 8192) { phy_b6 = (s16 )((unsigned int )(((int )((unsigned short )eps_offset) + (int )((unsigned short )phy_b12)) + (int )((unsigned short )phy_b10)) + 65503U); } else { phy_b6 = (s16 )((unsigned int )(((int )((unsigned short )eps_offset) + (int )((unsigned short )phy_b11)) + (int )((unsigned short )phy_b10)) + 65503U); } mod_phy_reg(pi, (unsigned int )phy_b5 == 0U ? 664 : 668, 65408, (int )((u16 )phy_b6) << 7U); pi->nphy_papd_epsilon_offset[(int )phy_b5] = phy_b6; } else { if (pi->pubpi.phy_rev <= 4U) { eps_offset = 4; } else { eps_offset = 2; } phy_b7 = (s16 )(15U - (unsigned int )((unsigned short )((int )phy_b1[(int )phy_b5].index >> 3))); if (((int )pi->radio_chanspec & 61440) == 8192) { phy_b11 = (s16 )(~ ((int )nphy_papd_pga_gain_delta_ipa_2g[(int )phy_b7]) / 2); phy_b10 = 0; } else { phy_b11 = (s16 )(~ ((int )nphy_papd_pga_gain_delta_ipa_5g[(int )phy_b7]) / 2); phy_b10 = -9; } phy_b6 = (s16 )((unsigned int )(((int )((unsigned short )eps_offset) + (int )((unsigned short )phy_b11)) + (int )((unsigned short )phy_b10)) + 65503U); mod_phy_reg(pi, (unsigned int )phy_b5 == 0U ? 664 : 668, 65408, (int )((u16 )phy_b6) << 7U); pi->nphy_papd_epsilon_offset[(int )phy_b5] = phy_b6; } phy_b5 = (u8 )((int )phy_b5 + 1); ldv_39348: ; if ((int )pi->pubpi.phy_corenum > (int )phy_b5) { goto ldv_39347; } else { } mod_phy_reg(pi, 663, 1, 1); mod_phy_reg(pi, 667, 1, 1); if (pi->pubpi.phy_rev > 5U) { mod_phy_reg(pi, 675, 8192, 0); mod_phy_reg(pi, 676, 8192, 0); } else { mod_phy_reg(pi, 675, 2048, 0); mod_phy_reg(pi, 676, 2048, 0); } pi->nphy_papdcomp = 1; write_phy_reg(pi, 1, (int )phy_b9); wlc_phy_ipa_set_tx_digi_filts_nphy(pi); wlc_phy_txpwrctrl_enable_nphy(pi, (int )phy_b4); if ((unsigned int )phy_b4 == 0U) { wlc_phy_txpwr_index_nphy(pi, 1, (int )pi->nphy_txpwrindex[0].index_internal, 0); wlc_phy_txpwr_index_nphy(pi, 2, (int )pi->nphy_txpwrindex[1].index_internal, 0); } else { } wlc_phy_stay_in_carriersearch_nphy(pi, 0); if (! phy_b3) { wlapi_enable_mac((pi->sh)->physhim); } else { } return; } } void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi , u8 caltype ) { struct nphy_txgains target_gain ; u8 tx_pwr_ctrl_state ; bool fullcal ; bool restore_tx_gain ; bool mphase ; u16 tmp ; u16 tmp___0 ; int tmp___1 ; int tmp___2 ; int tmp___3 ; int tmp___4 ; { fullcal = 1; restore_tx_gain = 0; if ((pi->measure_hold & 16U) != 0U) { return; } else { } if ((unsigned int )caltype == 0U) { fullcal = (int )pi->radio_chanspec != (int )pi->nphy_txiqlocal_chanspec; } else if ((unsigned int )caltype == 2U) { fullcal = 0; } else { } if ((unsigned int )pi->cal_type_override != 0U) { fullcal = (unsigned int )pi->cal_type_override == 1U; } else { } if ((unsigned int )pi->mphase_cal_phase_id > 1U) { if ((int )pi->nphy_txiqlocal_chanspec != (int )pi->radio_chanspec) { wlc_phy_cal_perical_mphase_restart(pi); } else { } } else { } if ((unsigned int )pi->mphase_cal_phase_id == 9U) { wlapi_bmac_write_shm((pi->sh)->physhim, 184U, 10000); } else { } wlapi_suspend_mac_and_wait((pi->sh)->physhim); wlc_phyreg_enter((struct brcms_phy_pub *)pi); if ((unsigned int )pi->mphase_cal_phase_id == 0U || (unsigned int )pi->mphase_cal_phase_id == 1U) { tmp = read_phy_reg(pi, 493); pi->nphy_cal_orig_pwr_idx[0] = (unsigned int )((unsigned char )((int )tmp >> 8)) & 127U; tmp___0 = read_phy_reg(pi, 494); pi->nphy_cal_orig_pwr_idx[1] = (unsigned int )((unsigned char )((int )tmp___0 >> 8)) & 127U; if ((unsigned int )pi->nphy_txpwrctrl != 0U) { wlc_phy_table_read_nphy(pi, 7U, 2U, 272U, 16U, (void *)(& pi->nphy_cal_orig_tx_gain)); } else { pi->nphy_cal_orig_tx_gain[0] = 0U; pi->nphy_cal_orig_tx_gain[1] = 0U; } } else { } target_gain = wlc_phy_get_tx_gain_nphy(pi); tx_pwr_ctrl_state = pi->nphy_txpwrctrl; wlc_phy_txpwrctrl_enable_nphy(pi, 0); if ((unsigned int )pi->antsel_type == 2U) { wlc_phy_antsel_init((struct brcms_phy_pub *)pi, 1); } else { } mphase = (unsigned int )pi->mphase_cal_phase_id != 0U; if (! mphase) { if (pi->pubpi.phy_rev > 2U) { wlc_phy_precal_txgain_nphy(pi); pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi); restore_tx_gain = 1; target_gain = pi->nphy_cal_target_gain; } else { } tmp___2 = wlc_phy_cal_txiqlo_nphy(pi, target_gain, (int )fullcal, (int )mphase); if (tmp___2 == 0) { if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { wlc_phy_a4(pi, 1); } else { } wlc_phyreg_exit((struct brcms_phy_pub *)pi); wlapi_enable_mac((pi->sh)->physhim); wlapi_bmac_write_shm((pi->sh)->physhim, 184U, 10000); wlapi_suspend_mac_and_wait((pi->sh)->physhim); wlc_phyreg_enter((struct brcms_phy_pub *)pi); tmp___1 = wlc_phy_cal_rxiq_nphy(pi, target_gain, (int )pi->first_cal_after_assoc || (unsigned int )pi->cal_type_override == 1U ? 2 : 0, 0); if (tmp___1 == 0) { wlc_phy_savecal_nphy(pi); wlc_phy_txpwrctrl_coeff_setup_nphy(pi); pi->nphy_perical_last = (pi->sh)->now; } else { } } else { } if ((unsigned int )caltype != 0U) { wlc_phy_rssi_cal_nphy(pi); } else { } if ((int )pi->first_cal_after_assoc || (unsigned int )pi->cal_type_override == 1U) { pi->first_cal_after_assoc = 0; wlc_phy_txpwrctrl_idle_tssi_nphy(pi); wlc_phy_txpwrctrl_pwr_setup_nphy(pi); } else { } if (pi->pubpi.phy_rev > 2U) { wlc_phy_radio205x_vcocal_nphy(pi); } else { } } else { switch ((int )pi->mphase_cal_phase_id) { case 1: pi->nphy_perical_last = (pi->sh)->now; pi->nphy_txiqlocal_chanspec = pi->radio_chanspec; if (pi->pubpi.phy_rev > 2U) { wlc_phy_precal_txgain_nphy(pi); } else { } pi->nphy_cal_target_gain = wlc_phy_get_tx_gain_nphy(pi); pi->mphase_cal_phase_id = (u8 )((int )pi->mphase_cal_phase_id + 1); goto ldv_39360; case 2: ; case 3: ; case 4: ; case 5: ; case 6: ; case 7: ; if (((int )pi->radar_percal_mask & 16) != 0) { pi->nphy_rxcal_active = 1; } else { } tmp___3 = wlc_phy_cal_txiqlo_nphy(pi, pi->nphy_cal_target_gain, (int )fullcal, 1); if (tmp___3 != 0) { wlc_phy_cal_perical_mphase_reset(pi); goto ldv_39360; } else { } if (pi->pubpi.phy_rev <= 2U && (unsigned int )pi->mphase_cal_phase_id == 6U) { pi->mphase_cal_phase_id = (unsigned int )pi->mphase_cal_phase_id + 2U; } else { pi->mphase_cal_phase_id = (u8 )((int )pi->mphase_cal_phase_id + 1); } goto ldv_39360; case 8: ; if (((int )pi->radar_percal_mask & 2) != 0) { pi->nphy_rxcal_active = 1; } else { } if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { wlc_phy_a4(pi, 1); } else { } pi->mphase_cal_phase_id = (u8 )((int )pi->mphase_cal_phase_id + 1); goto ldv_39360; case 9: ; if ((int )pi->radar_percal_mask & 1) { pi->nphy_rxcal_active = 1; } else { } tmp___4 = wlc_phy_cal_rxiq_nphy(pi, target_gain, (int )pi->first_cal_after_assoc || (unsigned int )pi->cal_type_override == 1U ? 2 : 0, 0); if (tmp___4 == 0) { wlc_phy_savecal_nphy(pi); } else { } pi->mphase_cal_phase_id = (u8 )((int )pi->mphase_cal_phase_id + 1); goto ldv_39360; case 10: ; if (((int )pi->radar_percal_mask & 4) != 0) { pi->nphy_rxcal_active = 1; } else { } wlc_phy_txpwrctrl_coeff_setup_nphy(pi); wlc_phy_rssi_cal_nphy(pi); if (pi->pubpi.phy_rev > 2U) { wlc_phy_radio205x_vcocal_nphy(pi); } else { } restore_tx_gain = 1; if ((int )pi->first_cal_after_assoc) { pi->mphase_cal_phase_id = (u8 )((int )pi->mphase_cal_phase_id + 1); } else { wlc_phy_cal_perical_mphase_reset(pi); } goto ldv_39360; case 11: ; if (((int )pi->radar_percal_mask & 8) != 0) { pi->nphy_rxcal_active = 1; } else { } if ((int )pi->first_cal_after_assoc) { pi->first_cal_after_assoc = 0; wlc_phy_txpwrctrl_idle_tssi_nphy(pi); wlc_phy_txpwrctrl_pwr_setup_nphy(pi); } else { } wlc_phy_cal_perical_mphase_reset(pi); goto ldv_39360; default: wlc_phy_cal_perical_mphase_reset(pi); goto ldv_39360; } ldv_39360: ; } if (pi->pubpi.phy_rev > 2U) { if ((int )restore_tx_gain) { if ((unsigned int )tx_pwr_ctrl_state != 0U) { wlc_phy_txpwr_index_nphy(pi, 1, (int )((s8 )pi->nphy_cal_orig_pwr_idx[0]), 0); wlc_phy_txpwr_index_nphy(pi, 2, (int )((s8 )pi->nphy_cal_orig_pwr_idx[1]), 0); pi->nphy_txpwrindex[0].index = -1; pi->nphy_txpwrindex[1].index = -1; } else { wlc_phy_txpwr_index_nphy(pi, 1, (int )pi->nphy_txpwrindex[0].index_internal, 0); wlc_phy_txpwr_index_nphy(pi, 2, (int )pi->nphy_txpwrindex[1].index_internal, 0); } } else { } } else { } wlc_phy_txpwrctrl_enable_nphy(pi, (int )tx_pwr_ctrl_state); wlc_phyreg_exit((struct brcms_phy_pub *)pi); wlapi_enable_mac((pi->sh)->physhim); return; } } int wlc_phy_cal_txiqlo_nphy(struct brcms_phy *pi , struct nphy_txgains target_gain , bool fullcal , bool mphase ) { u16 val ; u16 tbl_buf[11U] ; u8 cal_cnt ; u16 cal_cmd ; u8 num_cals ; u8 max_cal_cmds ; u16 core_no ; u16 cal_type ; u16 diq_start ; u8 phy_bw ; u16 max_val ; u16 tone_freq ; u16 gain_save[2U] ; u16 cal_gain[2U] ; struct nphy_iqcal_params cal_params[2U] ; u32 tbl_len ; void *tbl_ptr ; bool ladder_updated[2U] ; u8 mphase_cal_lastphase ; int bcmerror ; bool phyhang_avoid_state ; u16 tbl_tx_iqlo_cal_loft_ladder_20[18U] ; u16 tbl_tx_iqlo_cal_iqimb_ladder_20[18U] ; u16 tbl_tx_iqlo_cal_loft_ladder_40[18U] ; u16 tbl_tx_iqlo_cal_iqimb_ladder_40[18U] ; u16 tbl_tx_iqlo_cal_startcoefs[9U] ; u16 tbl_tx_iqlo_cal_cmds_fullcal[10U] ; u16 tbl_tx_iqlo_cal_cmds_recal[10U] ; u16 tbl_tx_iqlo_cal_startcoefs_nphyrev3[11U] ; u16 tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[12U] ; u16 tbl_tx_iqlo_cal_cmds_recal_nphyrev3[12U] ; uint countdown ; u16 tmp ; int __ret_warn_on ; u16 tmp___0 ; long tmp___1 ; long tmp___2 ; { diq_start = 0U; mphase_cal_lastphase = 0U; bcmerror = 0; phyhang_avoid_state = 0; tbl_tx_iqlo_cal_loft_ladder_20[0] = 768U; tbl_tx_iqlo_cal_loft_ladder_20[1] = 1280U; tbl_tx_iqlo_cal_loft_ladder_20[2] = 1792U; tbl_tx_iqlo_cal_loft_ladder_20[3] = 2304U; tbl_tx_iqlo_cal_loft_ladder_20[4] = 3328U; tbl_tx_iqlo_cal_loft_ladder_20[5] = 4352U; tbl_tx_iqlo_cal_loft_ladder_20[6] = 6400U; tbl_tx_iqlo_cal_loft_ladder_20[7] = 6401U; tbl_tx_iqlo_cal_loft_ladder_20[8] = 6402U; tbl_tx_iqlo_cal_loft_ladder_20[9] = 6403U; tbl_tx_iqlo_cal_loft_ladder_20[10] = 6404U; tbl_tx_iqlo_cal_loft_ladder_20[11] = 6405U; tbl_tx_iqlo_cal_loft_ladder_20[12] = 6406U; tbl_tx_iqlo_cal_loft_ladder_20[13] = 6407U; tbl_tx_iqlo_cal_loft_ladder_20[14] = 9223U; tbl_tx_iqlo_cal_loft_ladder_20[15] = 12807U; tbl_tx_iqlo_cal_loft_ladder_20[16] = 17927U; tbl_tx_iqlo_cal_loft_ladder_20[17] = 25607U; tbl_tx_iqlo_cal_iqimb_ladder_20[0] = 512U; tbl_tx_iqlo_cal_iqimb_ladder_20[1] = 768U; tbl_tx_iqlo_cal_iqimb_ladder_20[2] = 1536U; tbl_tx_iqlo_cal_iqimb_ladder_20[3] = 2304U; tbl_tx_iqlo_cal_iqimb_ladder_20[4] = 3328U; tbl_tx_iqlo_cal_iqimb_ladder_20[5] = 4352U; tbl_tx_iqlo_cal_iqimb_ladder_20[6] = 6400U; tbl_tx_iqlo_cal_iqimb_ladder_20[7] = 9216U; tbl_tx_iqlo_cal_iqimb_ladder_20[8] = 12800U; tbl_tx_iqlo_cal_iqimb_ladder_20[9] = 17920U; tbl_tx_iqlo_cal_iqimb_ladder_20[10] = 25600U; tbl_tx_iqlo_cal_iqimb_ladder_20[11] = 25601U; tbl_tx_iqlo_cal_iqimb_ladder_20[12] = 25602U; tbl_tx_iqlo_cal_iqimb_ladder_20[13] = 25603U; tbl_tx_iqlo_cal_iqimb_ladder_20[14] = 25604U; tbl_tx_iqlo_cal_iqimb_ladder_20[15] = 25605U; tbl_tx_iqlo_cal_iqimb_ladder_20[16] = 25606U; tbl_tx_iqlo_cal_iqimb_ladder_20[17] = 25607U; tbl_tx_iqlo_cal_loft_ladder_40[0] = 512U; tbl_tx_iqlo_cal_loft_ladder_40[1] = 768U; tbl_tx_iqlo_cal_loft_ladder_40[2] = 1024U; tbl_tx_iqlo_cal_loft_ladder_40[3] = 1792U; tbl_tx_iqlo_cal_loft_ladder_40[4] = 2304U; tbl_tx_iqlo_cal_loft_ladder_40[5] = 3072U; tbl_tx_iqlo_cal_loft_ladder_40[6] = 4608U; tbl_tx_iqlo_cal_loft_ladder_40[7] = 4609U; tbl_tx_iqlo_cal_loft_ladder_40[8] = 4610U; tbl_tx_iqlo_cal_loft_ladder_40[9] = 4611U; tbl_tx_iqlo_cal_loft_ladder_40[10] = 4612U; tbl_tx_iqlo_cal_loft_ladder_40[11] = 4613U; tbl_tx_iqlo_cal_loft_ladder_40[12] = 4614U; tbl_tx_iqlo_cal_loft_ladder_40[13] = 4615U; tbl_tx_iqlo_cal_loft_ladder_40[14] = 6407U; tbl_tx_iqlo_cal_loft_ladder_40[15] = 8967U; tbl_tx_iqlo_cal_loft_ladder_40[16] = 12807U; tbl_tx_iqlo_cal_loft_ladder_40[17] = 18183U; tbl_tx_iqlo_cal_iqimb_ladder_40[0] = 256U; tbl_tx_iqlo_cal_iqimb_ladder_40[1] = 512U; tbl_tx_iqlo_cal_iqimb_ladder_40[2] = 1024U; tbl_tx_iqlo_cal_iqimb_ladder_40[3] = 1792U; tbl_tx_iqlo_cal_iqimb_ladder_40[4] = 2304U; tbl_tx_iqlo_cal_iqimb_ladder_40[5] = 3072U; tbl_tx_iqlo_cal_iqimb_ladder_40[6] = 4608U; tbl_tx_iqlo_cal_iqimb_ladder_40[7] = 6400U; tbl_tx_iqlo_cal_iqimb_ladder_40[8] = 8960U; tbl_tx_iqlo_cal_iqimb_ladder_40[9] = 12800U; tbl_tx_iqlo_cal_iqimb_ladder_40[10] = 18176U; tbl_tx_iqlo_cal_iqimb_ladder_40[11] = 18177U; tbl_tx_iqlo_cal_iqimb_ladder_40[12] = 18178U; tbl_tx_iqlo_cal_iqimb_ladder_40[13] = 18179U; tbl_tx_iqlo_cal_iqimb_ladder_40[14] = 18180U; tbl_tx_iqlo_cal_iqimb_ladder_40[15] = 18181U; tbl_tx_iqlo_cal_iqimb_ladder_40[16] = 18182U; tbl_tx_iqlo_cal_iqimb_ladder_40[17] = 18183U; tbl_tx_iqlo_cal_startcoefs[0] = 0U; tbl_tx_iqlo_cal_startcoefs[1] = 0U; tbl_tx_iqlo_cal_startcoefs[2] = 0U; tbl_tx_iqlo_cal_startcoefs[3] = 0U; tbl_tx_iqlo_cal_startcoefs[4] = 0U; tbl_tx_iqlo_cal_startcoefs[5] = 0U; tbl_tx_iqlo_cal_startcoefs[6] = 0U; tbl_tx_iqlo_cal_startcoefs[7] = 0U; tbl_tx_iqlo_cal_startcoefs[8] = 0U; tbl_tx_iqlo_cal_cmds_fullcal[0] = 33059U; tbl_tx_iqlo_cal_cmds_fullcal[1] = 33380U; tbl_tx_iqlo_cal_cmds_fullcal[2] = 32902U; tbl_tx_iqlo_cal_cmds_fullcal[3] = 33349U; tbl_tx_iqlo_cal_cmds_fullcal[4] = 32854U; tbl_tx_iqlo_cal_cmds_fullcal[5] = 37155U; tbl_tx_iqlo_cal_cmds_fullcal[6] = 37476U; tbl_tx_iqlo_cal_cmds_fullcal[7] = 36998U; tbl_tx_iqlo_cal_cmds_fullcal[8] = 37445U; tbl_tx_iqlo_cal_cmds_fullcal[9] = 36950U; tbl_tx_iqlo_cal_cmds_recal[0] = 33025U; tbl_tx_iqlo_cal_cmds_recal[1] = 33363U; tbl_tx_iqlo_cal_cmds_recal[2] = 32851U; tbl_tx_iqlo_cal_cmds_recal[3] = 33332U; tbl_tx_iqlo_cal_cmds_recal[4] = 32820U; tbl_tx_iqlo_cal_cmds_recal[5] = 37121U; tbl_tx_iqlo_cal_cmds_recal[6] = 37459U; tbl_tx_iqlo_cal_cmds_recal[7] = 36947U; tbl_tx_iqlo_cal_cmds_recal[8] = 37428U; tbl_tx_iqlo_cal_cmds_recal[9] = 36916U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[0] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[1] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[2] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[3] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[4] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[5] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[6] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[7] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[8] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[9] = 0U; tbl_tx_iqlo_cal_startcoefs_nphyrev3[10] = 0U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[0] = 33844U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[1] = 33588U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[2] = 32900U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[3] = 33383U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[4] = 32854U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[5] = 33332U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[6] = 37940U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[7] = 37684U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[8] = 36996U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[9] = 37479U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[10] = 36950U; tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[11] = 37428U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[0] = 33827U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[1] = 33571U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[2] = 32883U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[3] = 33366U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[4] = 32837U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[5] = 33315U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[6] = 37923U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[7] = 37667U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[8] = 36979U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[9] = 37462U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[10] = 36933U; tbl_tx_iqlo_cal_cmds_recal_nphyrev3[11] = 37411U; wlc_phy_stay_in_carriersearch_nphy(pi, 1); if (pi->pubpi.phy_rev > 3U) { phyhang_avoid_state = pi->phyhang_avoid; pi->phyhang_avoid = 0; } else { } if (((int )pi->radio_chanspec & 3072) == 3072) { phy_bw = 40U; } else { phy_bw = 20U; } wlc_phy_table_read_nphy(pi, 7U, 2U, 272U, 16U, (void *)(& gain_save)); core_no = 0U; goto ldv_39410; ldv_39409: wlc_phy_iqcal_gainparams_nphy(pi, (int )core_no, target_gain, (struct nphy_iqcal_params *)(& cal_params) + (unsigned long )core_no); cal_gain[(int )core_no] = cal_params[(int )core_no].cal_gain; core_no = (u16 )((int )core_no + 1); ldv_39410: ; if ((unsigned int )core_no <= 1U) { goto ldv_39409; } else { } wlc_phy_table_write_nphy(pi, 7U, 2U, 272U, 16U, (void const *)(& cal_gain)); wlc_phy_txcal_radio_setup_nphy(pi); wlc_phy_txcal_physetup_nphy(pi); ladder_updated[1] = 0; ladder_updated[0] = ladder_updated[1]; if (pi->pubpi.phy_rev <= 5U && ((pi->pubpi.phy_rev != 5U || ((! pi->ipa2g_on || ((int )pi->radio_chanspec & 61440) != 8192) && (! pi->ipa5g_on || ((int )pi->radio_chanspec & 61440) != 4096))) || ((int )pi->radio_chanspec & 61440) != 8192)) { if ((unsigned int )phy_bw == 40U) { tbl_ptr = (void *)(& tbl_tx_iqlo_cal_loft_ladder_40); tbl_len = 18U; } else { tbl_ptr = (void *)(& tbl_tx_iqlo_cal_loft_ladder_20); tbl_len = 18U; } wlc_phy_table_write_nphy(pi, 15U, tbl_len, 0U, 16U, (void const *)tbl_ptr); if ((unsigned int )phy_bw == 40U) { tbl_ptr = (void *)(& tbl_tx_iqlo_cal_iqimb_ladder_40); tbl_len = 18U; } else { tbl_ptr = (void *)(& tbl_tx_iqlo_cal_iqimb_ladder_20); tbl_len = 18U; } wlc_phy_table_write_nphy(pi, 15U, tbl_len, 32U, 16U, (void const *)tbl_ptr); } else { } if (pi->pubpi.phy_rev > 6U) { write_phy_reg(pi, 194, 35545); } else { write_phy_reg(pi, 194, 35497); } max_val = 250U; tone_freq = (unsigned int )phy_bw == 20U ? 2500U : 5000U; if ((unsigned int )pi->mphase_cal_phase_id > 2U) { wlc_phy_runsamples_nphy(pi, (int )((unsigned int )((u16 )phy_bw) * 8U), 65535, 0, 1, 0, 0); bcmerror = 0; } else { bcmerror = wlc_phy_tx_tone_nphy(pi, (u32 )tone_freq, (int )max_val, 1, 0, 0); } if (bcmerror == 0) { if ((unsigned int )pi->mphase_cal_phase_id > 2U) { tbl_ptr = (void *)(& pi->mphase_txcal_bestcoeffs); tbl_len = 11U; if (pi->pubpi.phy_rev <= 2U) { tbl_len = tbl_len - 2U; } else { } } else if (! fullcal && (int )pi->nphy_txiqlocal_coeffsvalid) { tbl_ptr = (void *)(& pi->nphy_txiqlocal_bestc); tbl_len = 11U; if (pi->pubpi.phy_rev <= 2U) { tbl_len = tbl_len - 2U; } else { } } else { fullcal = 1; if (pi->pubpi.phy_rev > 2U) { tbl_ptr = (void *)(& tbl_tx_iqlo_cal_startcoefs_nphyrev3); tbl_len = 11U; } else { tbl_ptr = (void *)(& tbl_tx_iqlo_cal_startcoefs); tbl_len = 9U; } } wlc_phy_table_write_nphy(pi, 15U, tbl_len, 64U, 16U, (void const *)tbl_ptr); if ((int )fullcal) { max_cal_cmds = pi->pubpi.phy_rev > 2U ? 12U : 10U; } else { max_cal_cmds = pi->pubpi.phy_rev > 2U ? 12U : 10U; } if ((int )mphase) { cal_cnt = pi->mphase_txcal_cmdidx; if ((int )cal_cnt + (int )pi->mphase_txcal_numcmds < (int )max_cal_cmds) { num_cals = (int )pi->mphase_txcal_numcmds + (int )cal_cnt; } else { num_cals = max_cal_cmds; } } else { cal_cnt = 0U; num_cals = max_cal_cmds; } goto ldv_39443; ldv_39442: ; if ((int )fullcal) { cal_cmd = pi->pubpi.phy_rev > 2U ? tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[(int )cal_cnt] : tbl_tx_iqlo_cal_cmds_fullcal[(int )cal_cnt]; } else { cal_cmd = pi->pubpi.phy_rev > 2U ? tbl_tx_iqlo_cal_cmds_recal_nphyrev3[(int )cal_cnt] : tbl_tx_iqlo_cal_cmds_recal[(int )cal_cnt]; } core_no = (u16 )(((int )cal_cmd & 12288) >> 12); cal_type = (u16 )(((int )cal_cmd & 3840) >> 8); if (pi->pubpi.phy_rev > 5U || ((pi->pubpi.phy_rev == 5U && (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096))) && ((int )pi->radio_chanspec & 61440) == 8192)) { if (! ladder_updated[(int )core_no]) { wlc_phy_update_txcal_ladder_nphy(pi, (int )core_no); ladder_updated[(int )core_no] = 1; } else { } } else { } val = (u16 )((int )((short )((int )cal_params[(int )core_no].ncorr[(int )cal_type] << 8)) | 102); write_phy_reg(pi, 193, (int )val); if (((unsigned int )cal_type == 1U || (unsigned int )cal_type == 3U) || (unsigned int )cal_type == 4U) { wlc_phy_table_read_nphy(pi, 15U, 1U, (u32 )((int )core_no + 69), 16U, (void *)(& tbl_buf)); diq_start = tbl_buf[0]; tbl_buf[0] = 0U; wlc_phy_table_write_nphy(pi, 15U, 1U, (u32 )((int )core_no + 69), 16U, (void const *)(& tbl_buf)); } else { } write_phy_reg(pi, 192, (int )cal_cmd); countdown = 20009U; goto ldv_39438; ldv_39437: __const_udelay(42950UL); countdown = countdown - 10U; ldv_39438: tmp = read_phy_reg(pi, 192); if (((int )tmp & 49152) != 0 && countdown > 9U) { goto ldv_39437; } else { } tmp___0 = read_phy_reg(pi, 192); __ret_warn_on = ((int )tmp___0 & 49152) != 0; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c", 26021, "HW error: txiq calib"); } else { } tmp___2 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___2 != 0L) { return (-5); } else { } wlc_phy_table_read_nphy(pi, 15U, tbl_len, 96U, 16U, (void *)(& tbl_buf)); wlc_phy_table_write_nphy(pi, 15U, tbl_len, 64U, 16U, (void const *)(& tbl_buf)); if (((unsigned int )cal_type == 1U || (unsigned int )cal_type == 3U) || (unsigned int )cal_type == 4U) { tbl_buf[0] = diq_start; } else { } cal_cnt = (u8 )((int )cal_cnt + 1); ldv_39443: ; if ((int )cal_cnt < (int )num_cals) { goto ldv_39442; } else { } if ((int )mphase) { pi->mphase_txcal_cmdidx = num_cals; if ((int )pi->mphase_txcal_cmdidx >= (int )max_cal_cmds) { pi->mphase_txcal_cmdidx = 0U; } else { } } else { } mphase_cal_lastphase = pi->pubpi.phy_rev <= 2U ? 6U : 7U; if (! mphase || (int )pi->mphase_cal_phase_id == (int )mphase_cal_lastphase) { wlc_phy_table_read_nphy(pi, 15U, 4U, 96U, 16U, (void *)(& tbl_buf)); wlc_phy_table_write_nphy(pi, 15U, 4U, 80U, 16U, (void const *)(& tbl_buf)); if (pi->pubpi.phy_rev <= 1U) { tbl_buf[0] = 0U; tbl_buf[1] = 0U; tbl_buf[2] = 0U; tbl_buf[3] = 0U; } else { } wlc_phy_table_write_nphy(pi, 15U, 4U, 88U, 16U, (void const *)(& tbl_buf)); wlc_phy_table_read_nphy(pi, 15U, 2U, 101U, 16U, (void *)(& tbl_buf)); wlc_phy_table_write_nphy(pi, 15U, 2U, 85U, 16U, (void const *)(& tbl_buf)); wlc_phy_table_write_nphy(pi, 15U, 2U, 93U, 16U, (void const *)(& tbl_buf)); tbl_len = 11U; if (pi->pubpi.phy_rev <= 2U) { tbl_len = tbl_len - 2U; } else { } wlc_phy_table_read_nphy(pi, 15U, tbl_len, 96U, 16U, (void *)(& pi->nphy_txiqlocal_bestc)); pi->nphy_txiqlocal_coeffsvalid = 1; pi->nphy_txiqlocal_chanspec = pi->radio_chanspec; } else { tbl_len = 11U; if (pi->pubpi.phy_rev <= 2U) { tbl_len = tbl_len - 2U; } else { } wlc_phy_table_read_nphy(pi, 15U, tbl_len, 96U, 16U, (void *)(& pi->mphase_txcal_bestcoeffs)); } wlc_phy_stopplayback_nphy(pi); write_phy_reg(pi, 194, 0); } else { } wlc_phy_txcal_phycleanup_nphy(pi); wlc_phy_table_write_nphy(pi, 7U, 2U, 272U, 16U, (void const *)(& gain_save)); wlc_phy_txcal_radio_cleanup_nphy(pi); if (pi->pubpi.phy_rev <= 1U) { if (! mphase || (int )pi->mphase_cal_phase_id == (int )mphase_cal_lastphase) { wlc_phy_tx_iq_war_nphy(pi); } else { } } else { } if (pi->pubpi.phy_rev > 3U) { pi->phyhang_avoid = phyhang_avoid_state; } else { } wlc_phy_stay_in_carriersearch_nphy(pi, 0); return (bcmerror); } } static void wlc_phy_reapply_txcal_coeffs_nphy(struct brcms_phy *pi ) { u16 tbl_buf[7U] ; { if ((int )pi->nphy_txiqlocal_chanspec == (int )pi->radio_chanspec && (int )pi->nphy_txiqlocal_coeffsvalid) { wlc_phy_table_read_nphy(pi, 15U, 7U, 80U, 16U, (void *)(& tbl_buf)); if ((((int )pi->nphy_txiqlocal_bestc[0] != (int )tbl_buf[0] || (int )pi->nphy_txiqlocal_bestc[1] != (int )tbl_buf[1]) || (int )pi->nphy_txiqlocal_bestc[2] != (int )tbl_buf[2]) || (int )pi->nphy_txiqlocal_bestc[3] != (int )tbl_buf[3]) { wlc_phy_table_write_nphy(pi, 15U, 4U, 80U, 16U, (void const *)(& pi->nphy_txiqlocal_bestc)); tbl_buf[0] = 0U; tbl_buf[1] = 0U; tbl_buf[2] = 0U; tbl_buf[3] = 0U; wlc_phy_table_write_nphy(pi, 15U, 4U, 88U, 16U, (void const *)(& tbl_buf)); wlc_phy_table_write_nphy(pi, 15U, 2U, 85U, 16U, (void const *)(& pi->nphy_txiqlocal_bestc) + 5U); wlc_phy_table_write_nphy(pi, 15U, 2U, 93U, 16U, (void const *)(& pi->nphy_txiqlocal_bestc) + 5U); } else { } } else { } return; } } void wlc_phy_rx_iq_coeffs_nphy(struct brcms_phy *pi , u8 write , struct nphy_iq_comp *pcomp ) { u16 tmp ; u16 tmp___0 ; u16 tmp___1 ; u16 tmp___2 ; { if ((unsigned int )write != 0U) { write_phy_reg(pi, 154, (int )((u16 )pcomp->a0)); write_phy_reg(pi, 155, (int )((u16 )pcomp->b0)); write_phy_reg(pi, 156, (int )((u16 )pcomp->a1)); write_phy_reg(pi, 157, (int )((u16 )pcomp->b1)); } else { tmp = read_phy_reg(pi, 154); pcomp->a0 = (s16 )tmp; tmp___0 = read_phy_reg(pi, 155); pcomp->b0 = (s16 )tmp___0; tmp___1 = read_phy_reg(pi, 156); pcomp->a1 = (s16 )tmp___1; tmp___2 = read_phy_reg(pi, 157); pcomp->b1 = (s16 )tmp___2; } return; } } void wlc_phy_rx_iq_est_nphy(struct brcms_phy *pi , struct phy_iq_est *est , u16 num_samps , u8 wait_time , u8 wait_for_crs ) { u8 core ; uint countdown ; u16 tmp ; int __ret_warn_on ; u16 tmp___0 ; long tmp___1 ; long tmp___2 ; u16 tmp___3 ; u16 tmp___4 ; u16 tmp___5 ; u16 tmp___6 ; u16 tmp___7 ; u16 tmp___8 ; u16 tmp___9 ; { write_phy_reg(pi, 299, (int )num_samps); mod_phy_reg(pi, 298, 255, (int )wait_time); mod_phy_reg(pi, 297, 2, (unsigned int )wait_for_crs != 0U ? 2 : 0); mod_phy_reg(pi, 297, 1, 1); countdown = 10009U; goto ldv_39470; ldv_39469: __const_udelay(42950UL); countdown = countdown - 10U; ldv_39470: tmp = read_phy_reg(pi, 297); if ((int )tmp & 1 && countdown > 9U) { goto ldv_39469; } else { } tmp___0 = read_phy_reg(pi, 297); __ret_warn_on = (int )tmp___0 & 1; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_fmt("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c", 26190, "HW error: rxiq est"); } else { } tmp___2 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___2 != 0L) { return; } else { } tmp___9 = read_phy_reg(pi, 297); if (((int )tmp___9 & 1) == 0) { core = 0U; goto ldv_39475; ldv_39474: tmp___3 = read_phy_reg(pi, (unsigned int )core == 0U ? 303 : 311); tmp___4 = read_phy_reg(pi, (unsigned int )core == 0U ? 302 : 310); (est + (unsigned long )core)->i_pwr = (u32 )(((int )tmp___3 << 16) | (int )tmp___4); tmp___5 = read_phy_reg(pi, (unsigned int )core == 0U ? 305 : 313); tmp___6 = read_phy_reg(pi, (unsigned int )core == 0U ? 304 : 312); (est + (unsigned long )core)->q_pwr = (u32 )(((int )tmp___5 << 16) | (int )tmp___6); tmp___7 = read_phy_reg(pi, (unsigned int )core == 0U ? 301 : 309); tmp___8 = read_phy_reg(pi, (unsigned int )core == 0U ? 300 : 308); (est + (unsigned long )core)->iq_prod = ((int )tmp___7 << 16) | (int )tmp___8; core = (u8 )((int )core + 1); ldv_39475: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_39474; } else { } } else { } return; } } static void wlc_phy_calc_rx_iq_comp_nphy(struct brcms_phy *pi , u8 core_mask ) { u8 curr_core ; struct phy_iq_est est[4U] ; struct nphy_iq_comp old_comp ; struct nphy_iq_comp new_comp ; s32 iq ; u32 ii ; u32 qq ; s16 iq_nbits ; s16 qq_nbits ; s16 brsh ; s16 arsh ; s32 a ; s32 b ; s32 temp ; int bcmerror ; uint cal_retry ; u8 tmp ; u8 tmp___0 ; unsigned long tmp___1 ; struct _ddebug descriptor ; long tmp___2 ; { iq = 0; ii = 0U; qq = 0U; bcmerror = 0; cal_retry = 0U; if ((unsigned int )core_mask == 0U) { return; } else { } wlc_phy_rx_iq_coeffs_nphy(pi, 0, & old_comp); new_comp.b1 = 0; new_comp.a1 = new_comp.b1; new_comp.b0 = new_comp.a1; new_comp.a0 = new_comp.b0; wlc_phy_rx_iq_coeffs_nphy(pi, 1, & new_comp); cal_try: wlc_phy_rx_iq_est_nphy(pi, (struct phy_iq_est *)(& est), 16384, 32, 0); new_comp = old_comp; curr_core = 0U; goto ldv_39501; ldv_39500: ; if ((unsigned int )curr_core == 0U && (int )core_mask & 1) { iq = est[(int )curr_core].iq_prod; ii = est[(int )curr_core].i_pwr; qq = est[(int )curr_core].q_pwr; } else if ((unsigned int )curr_core == 1U && ((int )core_mask & 2) != 0) { iq = est[(int )curr_core].iq_prod; ii = est[(int )curr_core].i_pwr; qq = est[(int )curr_core].q_pwr; } else { goto ldv_39498; } if (ii + qq <= 1U) { bcmerror = -52; goto ldv_39499; } else { } tmp = wlc_phy_nbits(iq); iq_nbits = (s16 )tmp; tmp___0 = wlc_phy_nbits((s32 )qq); qq_nbits = (s16 )tmp___0; arsh = (s16 )((unsigned int )((unsigned short )iq_nbits) + 65516U); if ((int )arsh >= 0) { a = (s32 )((ii >> ((int )arsh + 1)) - (u32 )(iq << (30 - (int )iq_nbits))); temp = (int )(ii >> (int )arsh); if (temp == 0) { bcmerror = -52; goto ldv_39499; } else { } } else { a = (s32 )((ii << ~ ((int )arsh)) - (u32 )(iq << (30 - (int )iq_nbits))); temp = (int )(ii << - ((int )arsh)); if (temp == 0) { bcmerror = -52; goto ldv_39499; } else { } } a = a / temp; brsh = (s16 )((unsigned int )((unsigned short )qq_nbits) + 65525U); if ((int )brsh >= 0) { b = (s32 )(qq << (31 - (int )qq_nbits)); temp = (int )(ii >> (int )brsh); if (temp == 0) { bcmerror = -52; goto ldv_39499; } else { } } else { b = (s32 )(qq << (31 - (int )qq_nbits)); temp = (int )(ii << - ((int )brsh)); if (temp == 0) { bcmerror = -52; goto ldv_39499; } else { } } b = b / temp; b = b - a * a; tmp___1 = int_sqrt((unsigned long )b); b = (int )tmp___1; b = b + -1024; if ((unsigned int )curr_core == 0U && (int )core_mask & 1) { if (pi->pubpi.phy_rev > 2U) { new_comp.a0 = (int )((s16 )a) & 1023; new_comp.b0 = (int )((s16 )b) & 1023; } else { new_comp.a0 = (int )((s16 )b) & 1023; new_comp.b0 = (int )((s16 )a) & 1023; } } else { } if ((unsigned int )curr_core == 1U && ((int )core_mask & 2) != 0) { if (pi->pubpi.phy_rev > 2U) { new_comp.a1 = (int )((s16 )a) & 1023; new_comp.b1 = (int )((s16 )b) & 1023; } else { new_comp.a1 = (int )((s16 )b) & 1023; new_comp.b1 = (int )((s16 )a) & 1023; } } else { } ldv_39498: curr_core = (u8 )((int )curr_core + 1); ldv_39501: ; if ((int )pi->pubpi.phy_corenum > (int )curr_core) { goto ldv_39500; } else { } ldv_39499: ; if (bcmerror != 0) { descriptor.modname = "brcmsmac"; descriptor.function = "wlc_phy_calc_rx_iq_comp_nphy"; descriptor.filename = "/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c"; descriptor.format = "%s: Failed, cnt = %d\n"; descriptor.lineno = 26321U; descriptor.flags = 0U; tmp___2 = ldv__builtin_expect((long )descriptor.flags & 1L, 0L); if (tmp___2 != 0L) { __dynamic_pr_debug(& descriptor, "brcmsmac: %s: Failed, cnt = %d\n", "wlc_phy_calc_rx_iq_comp_nphy", cal_retry); } else { } if (cal_retry <= 1U) { cal_retry = cal_retry + 1U; goto cal_try; } else { } new_comp = old_comp; } else { } wlc_phy_rx_iq_coeffs_nphy(pi, 1, & new_comp); return; } } static void wlc_phy_rxcal_radio_setup_nphy(struct brcms_phy *pi , u8 rx_core ) { u16 offtune_val ; u16 bias_g ; u16 bias_a ; { bias_g = 0U; bias_a = 0U; if (pi->pubpi.phy_rev > 6U) { if ((unsigned int )rx_core == 0U) { if (((int )pi->radio_chanspec & 61440) == 4096) { pi->tx_rx_cal_radio_saveregs[0] = read_radio_reg(pi, 384); pi->tx_rx_cal_radio_saveregs[1] = read_radio_reg(pi, 383); write_radio_reg(pi, 384, 3); write_radio_reg(pi, 383, 175); } else { pi->tx_rx_cal_radio_saveregs[0] = read_radio_reg(pi, 382); pi->tx_rx_cal_radio_saveregs[1] = read_radio_reg(pi, 381); write_radio_reg(pi, 382, 3); write_radio_reg(pi, 381, 127); } } else if (((int )pi->radio_chanspec & 61440) == 4096) { pi->tx_rx_cal_radio_saveregs[0] = read_radio_reg(pi, 416); pi->tx_rx_cal_radio_saveregs[1] = read_radio_reg(pi, 415); write_radio_reg(pi, 416, 3); write_radio_reg(pi, 415, 175); } else { pi->tx_rx_cal_radio_saveregs[0] = read_radio_reg(pi, 414); pi->tx_rx_cal_radio_saveregs[1] = read_radio_reg(pi, 413); write_radio_reg(pi, 414, 3); write_radio_reg(pi, 413, 127); } } else if ((unsigned int )rx_core == 0U) { pi->tx_rx_cal_radio_saveregs[0] = read_radio_reg(pi, 12327); pi->tx_rx_cal_radio_saveregs[1] = read_radio_reg(pi, 24608); if ((unsigned int )pi->pubpi.radiorev > 4U) { pi->tx_rx_cal_radio_saveregs[2] = read_radio_reg(pi, 24700); pi->tx_rx_cal_radio_saveregs[3] = read_radio_reg(pi, 12414); } else { } if (((int )pi->radio_chanspec & 61440) == 4096) { if ((unsigned int )pi->pubpi.radiorev > 4U) { pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 24620); write_radio_reg(pi, 24620, 64); write_radio_reg(pi, 12414, (int )bias_a); write_radio_reg(pi, 24700, (int )bias_a); } else { pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 24621); offtune_val = 0U; offtune_val = (unsigned int )offtune_val <= 7U ? 15U : 0U; mod_radio_reg(pi, 24621, 240, (int )offtune_val << 8U); } write_radio_reg(pi, 12327, 9); write_radio_reg(pi, 24608, 9); } else { if ((unsigned int )pi->pubpi.radiorev > 4U) { pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 24627); write_radio_reg(pi, 24627, 64); write_radio_reg(pi, 12414, (int )bias_g); write_radio_reg(pi, 24700, (int )bias_g); } else { pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 24628); offtune_val = 0U; offtune_val = (unsigned int )offtune_val <= 7U ? 15U : 0U; mod_radio_reg(pi, 24628, 240, (int )offtune_val << 8U); } write_radio_reg(pi, 12327, 6); write_radio_reg(pi, 24608, 6); } } else { pi->tx_rx_cal_radio_saveregs[0] = read_radio_reg(pi, 8231); pi->tx_rx_cal_radio_saveregs[1] = read_radio_reg(pi, 28704); if ((unsigned int )pi->pubpi.radiorev > 4U) { pi->tx_rx_cal_radio_saveregs[2] = read_radio_reg(pi, 28796); pi->tx_rx_cal_radio_saveregs[3] = read_radio_reg(pi, 8318); } else { } if (((int )pi->radio_chanspec & 61440) == 4096) { if ((unsigned int )pi->pubpi.radiorev > 4U) { pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 28716); write_radio_reg(pi, 28716, 64); write_radio_reg(pi, 8318, (int )bias_a); write_radio_reg(pi, 28796, (int )bias_a); } else { pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 28717); offtune_val = 0U; offtune_val = (unsigned int )offtune_val <= 7U ? 15U : 0U; mod_radio_reg(pi, 28717, 240, (int )offtune_val << 8U); } write_radio_reg(pi, 8231, 9); write_radio_reg(pi, 28704, 9); } else { if ((unsigned int )pi->pubpi.radiorev > 4U) { pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 28723); write_radio_reg(pi, 28723, 64); write_radio_reg(pi, 8318, (int )bias_g); write_radio_reg(pi, 28796, (int )bias_g); } else { pi->tx_rx_cal_radio_saveregs[4] = read_radio_reg(pi, 28724); offtune_val = 0U; offtune_val = (unsigned int )offtune_val <= 7U ? 15U : 0U; mod_radio_reg(pi, 28724, 240, (int )offtune_val << 8U); } write_radio_reg(pi, 8231, 6); write_radio_reg(pi, 28704, 6); } } return; } } static void wlc_phy_rxcal_radio_cleanup_nphy(struct brcms_phy *pi , u8 rx_core ) { { if (pi->pubpi.phy_rev > 6U) { if ((unsigned int )rx_core == 0U) { if (((int )pi->radio_chanspec & 61440) == 4096) { write_radio_reg(pi, 384, (int )pi->tx_rx_cal_radio_saveregs[0]); write_radio_reg(pi, 383, (int )pi->tx_rx_cal_radio_saveregs[1]); } else { write_radio_reg(pi, 382, (int )pi->tx_rx_cal_radio_saveregs[0]); write_radio_reg(pi, 381, (int )pi->tx_rx_cal_radio_saveregs[1]); } } else if (((int )pi->radio_chanspec & 61440) == 4096) { write_radio_reg(pi, 416, (int )pi->tx_rx_cal_radio_saveregs[0]); write_radio_reg(pi, 415, (int )pi->tx_rx_cal_radio_saveregs[1]); } else { write_radio_reg(pi, 414, (int )pi->tx_rx_cal_radio_saveregs[0]); write_radio_reg(pi, 413, (int )pi->tx_rx_cal_radio_saveregs[1]); } } else if ((unsigned int )rx_core == 0U) { write_radio_reg(pi, 12327, (int )pi->tx_rx_cal_radio_saveregs[0]); write_radio_reg(pi, 24608, (int )pi->tx_rx_cal_radio_saveregs[1]); if ((unsigned int )pi->pubpi.radiorev > 4U) { write_radio_reg(pi, 24700, (int )pi->tx_rx_cal_radio_saveregs[2]); write_radio_reg(pi, 12414, (int )pi->tx_rx_cal_radio_saveregs[3]); } else { } if (((int )pi->radio_chanspec & 61440) == 4096) { if ((unsigned int )pi->pubpi.radiorev > 4U) { write_radio_reg(pi, 24620, (int )pi->tx_rx_cal_radio_saveregs[4]); } else { write_radio_reg(pi, 24621, (int )pi->tx_rx_cal_radio_saveregs[4]); } } else if ((unsigned int )pi->pubpi.radiorev > 4U) { write_radio_reg(pi, 24627, (int )pi->tx_rx_cal_radio_saveregs[4]); } else { write_radio_reg(pi, 24628, (int )pi->tx_rx_cal_radio_saveregs[4]); } } else { write_radio_reg(pi, 8231, (int )pi->tx_rx_cal_radio_saveregs[0]); write_radio_reg(pi, 28704, (int )pi->tx_rx_cal_radio_saveregs[1]); if ((unsigned int )pi->pubpi.radiorev > 4U) { write_radio_reg(pi, 28796, (int )pi->tx_rx_cal_radio_saveregs[2]); write_radio_reg(pi, 8318, (int )pi->tx_rx_cal_radio_saveregs[3]); } else { } if (((int )pi->radio_chanspec & 61440) == 4096) { if ((unsigned int )pi->pubpi.radiorev > 4U) { write_radio_reg(pi, 28716, (int )pi->tx_rx_cal_radio_saveregs[4]); } else { write_radio_reg(pi, 28717, (int )pi->tx_rx_cal_radio_saveregs[4]); } } else if ((unsigned int )pi->pubpi.radiorev > 4U) { write_radio_reg(pi, 28723, (int )pi->tx_rx_cal_radio_saveregs[4]); } else { write_radio_reg(pi, 28724, (int )pi->tx_rx_cal_radio_saveregs[4]); } } return; } } static void wlc_phy_rxcal_physetup_nphy(struct brcms_phy *pi , u8 rx_core ) { u8 tx_core ; u16 rx_antval ; u16 tx_antval ; { if (pi->pubpi.phy_rev > 6U) { tx_core = rx_core; } else { tx_core = (unsigned int )rx_core == 0U; } pi->tx_rx_cal_phy_saveregs[0] = read_phy_reg(pi, 162); pi->tx_rx_cal_phy_saveregs[1] = read_phy_reg(pi, (unsigned int )rx_core == 0U ? 166 : 167); pi->tx_rx_cal_phy_saveregs[2] = read_phy_reg(pi, (unsigned int )rx_core == 0U ? 143 : 165); pi->tx_rx_cal_phy_saveregs[3] = read_phy_reg(pi, 145); pi->tx_rx_cal_phy_saveregs[4] = read_phy_reg(pi, 146); pi->tx_rx_cal_phy_saveregs[5] = read_phy_reg(pi, 122); pi->tx_rx_cal_phy_saveregs[6] = read_phy_reg(pi, 125); pi->tx_rx_cal_phy_saveregs[7] = read_phy_reg(pi, 231); pi->tx_rx_cal_phy_saveregs[8] = read_phy_reg(pi, 236); if (pi->pubpi.phy_rev > 6U) { pi->tx_rx_cal_phy_saveregs[11] = read_phy_reg(pi, 834); pi->tx_rx_cal_phy_saveregs[12] = read_phy_reg(pi, 835); pi->tx_rx_cal_phy_saveregs[13] = read_phy_reg(pi, 838); pi->tx_rx_cal_phy_saveregs[14] = read_phy_reg(pi, 839); } else { } pi->tx_rx_cal_phy_saveregs[9] = read_phy_reg(pi, 663); pi->tx_rx_cal_phy_saveregs[10] = read_phy_reg(pi, 667); mod_phy_reg(pi, 663, 1, 0); mod_phy_reg(pi, 667, 1, 0); if (pi->pubpi.phy_rev > 6U) { mod_phy_reg(pi, 162, 15, (int )((u16 )(1 << (int )tx_core))); mod_phy_reg(pi, 162, 61440, (int )((u16 )(1 << (1 - (int )rx_core))) << 12U); } else { mod_phy_reg(pi, 162, 61440, (int )((u16 )(1 << (int )tx_core)) << 12U); mod_phy_reg(pi, 162, 15, (int )((u16 )(1 << (int )tx_core))); mod_phy_reg(pi, 162, 240, (int )((u16 )(1 << (int )rx_core)) << 4U); mod_phy_reg(pi, 162, 3840, (int )((u16 )(1 << (int )rx_core)) << 8U); } mod_phy_reg(pi, (unsigned int )rx_core == 0U ? 166 : 167, 4, 0); mod_phy_reg(pi, (unsigned int )rx_core == 0U ? 143 : 165, 4, 4); if (pi->pubpi.phy_rev <= 6U) { mod_phy_reg(pi, (unsigned int )rx_core == 0U ? 166 : 167, 3, 0); mod_phy_reg(pi, (unsigned int )rx_core == 0U ? 143 : 165, 3, 3); } else { } wlc_phy_rfctrlintc_override_nphy(pi, 2, 0, 3); if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_nphy_rev7(pi, 8, 0, 0, 0, 0); wlc_phy_rfctrl_override_nphy_rev7(pi, 512, 0, 0, 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1024, 1, 0, 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 1, 1, 0, 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 2, 1, 0, 0, 2); wlc_phy_rfctrl_override_nphy_rev7(pi, 2048, 0, 0, 0, 1); if (((int )pi->radio_chanspec & 3072) == 3072) { wlc_phy_rfctrl_override_nphy_rev7(pi, 128, 2, 0, 0, 1); } else { wlc_phy_rfctrl_override_nphy_rev7(pi, 128, 0, 0, 0, 1); } wlc_phy_rfctrl_override_nphy_rev7(pi, 128, 0, 0, 0, 1); wlc_phy_rfctrl_override_nphy_rev7(pi, 32, 0, 0, 0, 1); } else { wlc_phy_rfctrl_override_nphy(pi, 8, 0, 3, 0); } wlc_phy_force_rfseq_nphy(pi, 0); if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrlintc_override_nphy(pi, 1, 1, (int )((unsigned int )rx_core + 1U)); } else { if ((unsigned int )rx_core == 0U) { rx_antval = 1U; tx_antval = 8U; } else { rx_antval = 4U; tx_antval = 2U; } wlc_phy_rfctrlintc_override_nphy(pi, 1, (int )rx_antval, (int )((unsigned int )rx_core + 1U)); wlc_phy_rfctrlintc_override_nphy(pi, 1, (int )tx_antval, (int )((unsigned int )tx_core + 1U)); } return; } } static void wlc_phy_rxcal_phycleanup_nphy(struct brcms_phy *pi , u8 rx_core ) { { write_phy_reg(pi, 162, (int )pi->tx_rx_cal_phy_saveregs[0]); write_phy_reg(pi, (unsigned int )rx_core == 0U ? 166 : 167, (int )pi->tx_rx_cal_phy_saveregs[1]); write_phy_reg(pi, (unsigned int )rx_core == 0U ? 143 : 165, (int )pi->tx_rx_cal_phy_saveregs[2]); write_phy_reg(pi, 145, (int )pi->tx_rx_cal_phy_saveregs[3]); write_phy_reg(pi, 146, (int )pi->tx_rx_cal_phy_saveregs[4]); write_phy_reg(pi, 122, (int )pi->tx_rx_cal_phy_saveregs[5]); write_phy_reg(pi, 125, (int )pi->tx_rx_cal_phy_saveregs[6]); write_phy_reg(pi, 231, (int )pi->tx_rx_cal_phy_saveregs[7]); write_phy_reg(pi, 236, (int )pi->tx_rx_cal_phy_saveregs[8]); if (pi->pubpi.phy_rev > 6U) { write_phy_reg(pi, 834, (int )pi->tx_rx_cal_phy_saveregs[11]); write_phy_reg(pi, 835, (int )pi->tx_rx_cal_phy_saveregs[12]); write_phy_reg(pi, 838, (int )pi->tx_rx_cal_phy_saveregs[13]); write_phy_reg(pi, 839, (int )pi->tx_rx_cal_phy_saveregs[14]); } else { } write_phy_reg(pi, 663, (int )pi->tx_rx_cal_phy_saveregs[9]); write_phy_reg(pi, 667, (int )pi->tx_rx_cal_phy_saveregs[10]); return; } } static void wlc_phy_rxcal_gainctrl_nphy_rev5(struct brcms_phy *pi , u8 rx_core , u16 *rxgain , u8 cal_type ) { u16 num_samps ; struct phy_iq_est est[4U] ; u8 tx_core ; struct nphy_iq_comp save_comp ; struct nphy_iq_comp zero_comp ; u32 i_pwr ; u32 q_pwr ; u32 curr_pwr ; u32 optim_pwr ; u32 prev_pwr ; u32 thresh_pwr ; s16 desired_log2_pwr ; s16 actual_log2_pwr ; s16 delta_pwr ; bool gainctrl_done ; u8 mix_tia_gain ; s8 optim_gaintbl_index ; s8 prev_gaintbl_index ; s8 curr_gaintbl_index ; u8 gainctrl_dirn ; struct nphy_ipa_txrxgain const *nphy_rxcal_gaintbl ; u16 hpvga ; u16 lpf_biq1 ; u16 lpf_biq0 ; u16 lna2 ; u16 lna1 ; int fine_gain_idx ; s8 txpwrindex ; u16 nphy_rxcal_txgain[2U] ; u8 tmp ; int _max1 ; int _max2 ; int _max1___0 ; int _min1 ; int _min2 ; int _max2___0 ; u16 *tmp___0 ; u16 *tmp___1 ; u16 *tmp___2 ; u16 *tmp___3 ; u16 *tmp___4 ; { optim_pwr = 0U; prev_pwr = 0U; thresh_pwr = 10000U; gainctrl_done = 0; mix_tia_gain = 3U; optim_gaintbl_index = 0; prev_gaintbl_index = 0; curr_gaintbl_index = 3; gainctrl_dirn = 0U; if (pi->pubpi.phy_rev > 6U) { tx_core = rx_core; } else { tx_core = 1U - (unsigned int )rx_core; } num_samps = 1024U; desired_log2_pwr = 13; wlc_phy_rx_iq_coeffs_nphy(pi, 0, & save_comp); zero_comp.b1 = 0; zero_comp.a1 = zero_comp.b1; zero_comp.b0 = zero_comp.a1; zero_comp.a0 = zero_comp.b0; wlc_phy_rx_iq_coeffs_nphy(pi, 1, & zero_comp); if (((int )pi->radio_chanspec & 61440) == 4096) { if (pi->pubpi.phy_rev > 6U) { mix_tia_gain = 3U; } else if (pi->pubpi.phy_rev > 3U) { mix_tia_gain = 4U; } else { mix_tia_gain = 6U; } if (pi->pubpi.phy_rev > 6U) { nphy_rxcal_gaintbl = (struct nphy_ipa_txrxgain const *)(& nphy_ipa_rxcal_gaintbl_5GHz_rev7); } else { nphy_rxcal_gaintbl = (struct nphy_ipa_txrxgain const *)(& nphy_ipa_rxcal_gaintbl_5GHz); } } else if (pi->pubpi.phy_rev > 6U) { nphy_rxcal_gaintbl = (struct nphy_ipa_txrxgain const *)(& nphy_ipa_rxcal_gaintbl_2GHz_rev7); } else { nphy_rxcal_gaintbl = (struct nphy_ipa_txrxgain const *)(& nphy_ipa_rxcal_gaintbl_2GHz); } ldv_39566: hpvga = pi->pubpi.phy_rev <= 6U ? (u16 )(nphy_rxcal_gaintbl + (unsigned long )curr_gaintbl_index)->hpvga : 0U; lpf_biq1 = (nphy_rxcal_gaintbl + (unsigned long )curr_gaintbl_index)->lpf_biq1; lpf_biq0 = (nphy_rxcal_gaintbl + (unsigned long )curr_gaintbl_index)->lpf_biq0; lna2 = (nphy_rxcal_gaintbl + (unsigned long )curr_gaintbl_index)->lna2; lna1 = (nphy_rxcal_gaintbl + (unsigned long )curr_gaintbl_index)->lna1; txpwrindex = (nphy_rxcal_gaintbl + (unsigned long )curr_gaintbl_index)->txpwrindex; if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_1tomany_nphy(pi, 3, (int )((u16 )(((((int )((short )((int )lpf_biq1 << 12)) | (int )((short )((int )lpf_biq0 << 8))) | (int )((short )((int )mix_tia_gain << 4))) | (int )((short )((int )lna2 << 2))) | (int )((short )lna1))), 3, 0); } else { wlc_phy_rfctrl_override_nphy(pi, 4096, (int )((u16 )((((((int )((short )((int )hpvga << 12)) | (int )((short )((int )lpf_biq1 << 10))) | (int )((short )((int )lpf_biq0 << 8))) | (int )((short )((int )mix_tia_gain << 4))) | (int )((short )((int )lna2 << 2))) | (int )((short )lna1))), 3, 0); } pi->nphy_rxcal_pwr_idx[(int )tx_core] = (u8 )txpwrindex; if ((int )txpwrindex == -1) { nphy_rxcal_txgain[0] = (u16 )((unsigned int )pi->nphy_gmval | 36848U); nphy_rxcal_txgain[1] = (u16 )((unsigned int )pi->nphy_gmval | 36848U); wlc_phy_table_write_nphy(pi, 7U, 2U, 272U, 16U, (void const *)(& nphy_rxcal_txgain)); } else { wlc_phy_txpwr_index_nphy(pi, (int )((unsigned int )tx_core + 1U), (int )txpwrindex, 0); } wlc_phy_tx_tone_nphy(pi, ((int )pi->radio_chanspec & 3072) == 3072 ? 4000U : 2000U, 181, 0, (int )cal_type, 0); wlc_phy_rx_iq_est_nphy(pi, (struct phy_iq_est *)(& est), (int )num_samps, 32, 0); i_pwr = (est[(int )rx_core].i_pwr + (unsigned int )num_samps / 2U) / (u32 )num_samps; q_pwr = (est[(int )rx_core].q_pwr + (unsigned int )num_samps / 2U) / (u32 )num_samps; curr_pwr = i_pwr + q_pwr; switch ((int )gainctrl_dirn) { case 0: ; if (curr_pwr > thresh_pwr) { gainctrl_dirn = 2U; prev_gaintbl_index = curr_gaintbl_index; curr_gaintbl_index = (s8 )((int )curr_gaintbl_index - 1); } else { gainctrl_dirn = 1U; prev_gaintbl_index = curr_gaintbl_index; curr_gaintbl_index = (s8 )((int )curr_gaintbl_index + 1); } goto ldv_39562; case 1: ; if (curr_pwr > thresh_pwr) { gainctrl_done = 1; optim_pwr = prev_pwr; optim_gaintbl_index = prev_gaintbl_index; } else { prev_gaintbl_index = curr_gaintbl_index; curr_gaintbl_index = (s8 )((int )curr_gaintbl_index + 1); } goto ldv_39562; case 2: ; if (curr_pwr > thresh_pwr) { prev_gaintbl_index = curr_gaintbl_index; curr_gaintbl_index = (s8 )((int )curr_gaintbl_index - 1); } else { gainctrl_done = 1; optim_pwr = curr_pwr; optim_gaintbl_index = curr_gaintbl_index; } goto ldv_39562; default: ; goto ldv_39562; } ldv_39562: ; if ((int )curr_gaintbl_index < 0 || (int )curr_gaintbl_index > 5) { gainctrl_done = 1; optim_pwr = curr_pwr; optim_gaintbl_index = prev_gaintbl_index; } else { prev_pwr = curr_pwr; } wlc_phy_stopplayback_nphy(pi); if (! gainctrl_done) { goto ldv_39566; } else { } hpvga = (nphy_rxcal_gaintbl + (unsigned long )optim_gaintbl_index)->hpvga; lpf_biq1 = (nphy_rxcal_gaintbl + (unsigned long )optim_gaintbl_index)->lpf_biq1; lpf_biq0 = (nphy_rxcal_gaintbl + (unsigned long )optim_gaintbl_index)->lpf_biq0; lna2 = (nphy_rxcal_gaintbl + (unsigned long )optim_gaintbl_index)->lna2; lna1 = (nphy_rxcal_gaintbl + (unsigned long )optim_gaintbl_index)->lna1; txpwrindex = (nphy_rxcal_gaintbl + (unsigned long )optim_gaintbl_index)->txpwrindex; tmp = wlc_phy_nbits((s32 )optim_pwr); actual_log2_pwr = (s16 )tmp; delta_pwr = (s16 )((int )((unsigned short )desired_log2_pwr) - (int )((unsigned short )actual_log2_pwr)); if (pi->pubpi.phy_rev > 6U) { fine_gain_idx = (int )lpf_biq1 + (int )delta_pwr; if ((int )lpf_biq0 + fine_gain_idx > 10) { lpf_biq1 = 10U - (unsigned int )lpf_biq0; } else { _max1 = fine_gain_idx; _max2 = 0; lpf_biq1 = (unsigned short )(_max1 > _max2 ? _max1 : _max2); } wlc_phy_rfctrl_override_1tomany_nphy(pi, 3, (int )((u16 )(((((int )((short )((int )lpf_biq1 << 12)) | (int )((short )((int )lpf_biq0 << 8))) | (int )((short )((int )mix_tia_gain << 4))) | (int )((short )((int )lna2 << 2))) | (int )((short )lna1))), 3, 0); } else { _min1 = (int )hpvga + (int )delta_pwr; _min2 = 10; _max1___0 = _min1 < _min2 ? _min1 : _min2; _max2___0 = 0; hpvga = (unsigned short )(_max1___0 > _max2___0 ? _max1___0 : _max2___0); wlc_phy_rfctrl_override_nphy(pi, 4096, (int )((u16 )((((((int )((short )((int )hpvga << 12)) | (int )((short )((int )lpf_biq1 << 10))) | (int )((short )((int )lpf_biq0 << 8))) | (int )((short )((int )mix_tia_gain << 4))) | (int )((short )((int )lna2 << 2))) | (int )((short )lna1))), 3, 0); } if ((unsigned long )rxgain != (unsigned long )((u16 *)0U)) { tmp___0 = rxgain; rxgain = rxgain + 1; *tmp___0 = lna1; tmp___1 = rxgain; rxgain = rxgain + 1; *tmp___1 = lna2; tmp___2 = rxgain; rxgain = rxgain + 1; *tmp___2 = (u16 )mix_tia_gain; tmp___3 = rxgain; rxgain = rxgain + 1; *tmp___3 = lpf_biq0; tmp___4 = rxgain; rxgain = rxgain + 1; *tmp___4 = lpf_biq1; *rxgain = hpvga; } else { } wlc_phy_rx_iq_coeffs_nphy(pi, 1, & save_comp); return; } } static void wlc_phy_rxcal_gainctrl_nphy(struct brcms_phy *pi , u8 rx_core , u16 *rxgain , u8 cal_type ) { { wlc_phy_rxcal_gainctrl_nphy_rev5(pi, (int )rx_core, rxgain, (int )cal_type); return; } } static u8 wlc_phy_rc_sweep_nphy(struct brcms_phy *pi , u8 core_idx , u8 loopback_type ) { u32 target_bws[2U] ; u32 ref_tones[2U] ; u32 target_bw ; u32 ref_tone ; u32 target_pwr_ratios[2U] ; u32 target_pwr_ratio ; u32 pwr_ratio ; u32 last_pwr_ratio ; u16 start_rccal_ovr_val ; u16 txlpf_rccal_lpc_ovr_val ; u16 rxlpf_rccal_hpc_ovr_val ; u16 orig_txlpf_rccal_lpc_ovr_val ; u16 orig_rxlpf_rccal_hpc_ovr_val ; u16 radio_addr_offset_rx ; u16 radio_addr_offset_tx ; u16 orig_dcBypass ; u16 orig_RxStrnFilt40Num[6U] ; u16 orig_RxStrnFilt40Den[4U] ; u16 orig_rfctrloverride[2U] ; u16 orig_rfctrlauxreg[2U] ; u16 orig_rfctrlrssiothers ; u16 tx_lpf_bw ; u16 rx_lpf_bw ; u16 rx_lpf_bws[2U] ; u16 lpf_hpc ; u16 hpvga_hpc ; s8 rccal_stepsize ; u16 rccal_val ; u16 last_rccal_val ; u16 best_rccal_val ; u32 ref_iq_vals ; u32 target_iq_vals ; u16 num_samps ; u16 log_num_samps ; struct phy_iq_est est[4U] ; u16 tmp ; u32 __max1 ; u32 __max2 ; u32 __max1___0 ; u32 __max2___0 ; long ret ; int __x___0 ; long ret___0 ; int __x___2 ; { target_bws[0] = 9500U; target_bws[1] = 21000U; ref_tones[0] = 3000U; ref_tones[1] = 6000U; target_pwr_ratios[0] = 28606U; target_pwr_ratios[1] = 18468U; last_pwr_ratio = 0U; start_rccal_ovr_val = 128U; txlpf_rccal_lpc_ovr_val = 128U; rxlpf_rccal_hpc_ovr_val = 159U; tx_lpf_bw = 4U; rx_lpf_bws[0] = 2U; rx_lpf_bws[1] = 4U; lpf_hpc = 7U; hpvga_hpc = 7U; last_rccal_val = 0U; best_rccal_val = 0U; ref_iq_vals = 0U; target_iq_vals = 0U; log_num_samps = 10U; if (pi->pubpi.phy_rev > 6U) { return (0U); } else { } num_samps = (u16 )(1 << (int )log_num_samps); if (((int )pi->radio_chanspec & 3072) == 3072) { target_bw = target_bws[1]; target_pwr_ratio = target_pwr_ratios[1]; ref_tone = ref_tones[1]; rx_lpf_bw = rx_lpf_bws[1]; } else { target_bw = target_bws[0]; target_pwr_ratio = target_pwr_ratios[0]; ref_tone = ref_tones[0]; rx_lpf_bw = rx_lpf_bws[0]; } if ((unsigned int )core_idx == 0U) { radio_addr_offset_rx = 24576U; radio_addr_offset_tx = (unsigned int )loopback_type == 0U ? 8192U : 12288U; } else { radio_addr_offset_rx = 28672U; radio_addr_offset_tx = (unsigned int )loopback_type == 0U ? 12288U : 8192U; } orig_txlpf_rccal_lpc_ovr_val = read_radio_reg(pi, (int )((unsigned int )radio_addr_offset_tx | 105U)); orig_rxlpf_rccal_hpc_ovr_val = read_radio_reg(pi, (int )((unsigned int )radio_addr_offset_rx | 98U)); tmp = read_phy_reg(pi, 72); orig_dcBypass = (unsigned int )((u16 )((int )tmp >> 8)) & 1U; orig_RxStrnFilt40Num[0] = read_phy_reg(pi, 615); orig_RxStrnFilt40Num[1] = read_phy_reg(pi, 616); orig_RxStrnFilt40Num[2] = read_phy_reg(pi, 617); orig_RxStrnFilt40Den[0] = read_phy_reg(pi, 618); orig_RxStrnFilt40Den[1] = read_phy_reg(pi, 619); orig_RxStrnFilt40Num[3] = read_phy_reg(pi, 620); orig_RxStrnFilt40Num[4] = read_phy_reg(pi, 621); orig_RxStrnFilt40Num[5] = read_phy_reg(pi, 622); orig_RxStrnFilt40Den[2] = read_phy_reg(pi, 623); orig_RxStrnFilt40Den[3] = read_phy_reg(pi, 624); orig_rfctrloverride[0] = read_phy_reg(pi, 231); orig_rfctrloverride[1] = read_phy_reg(pi, 236); orig_rfctrlauxreg[0] = read_phy_reg(pi, 248); orig_rfctrlauxreg[1] = read_phy_reg(pi, 250); orig_rfctrlrssiothers = read_phy_reg(pi, (unsigned int )core_idx == 0U ? 122 : 125); write_radio_reg(pi, (int )((unsigned int )radio_addr_offset_tx | 105U), (int )txlpf_rccal_lpc_ovr_val); write_radio_reg(pi, (int )((unsigned int )radio_addr_offset_rx | 98U), (int )rxlpf_rccal_hpc_ovr_val); mod_phy_reg(pi, 72, 256, 256); write_phy_reg(pi, 615, 724); write_phy_reg(pi, 616, 0); write_phy_reg(pi, 617, 0); write_phy_reg(pi, 618, 0); write_phy_reg(pi, 619, 0); write_phy_reg(pi, 620, 724); write_phy_reg(pi, 621, 0); write_phy_reg(pi, 622, 0); write_phy_reg(pi, 623, 0); write_phy_reg(pi, 624, 0); or_phy_reg(pi, (unsigned int )core_idx == 0U ? 231 : 236, 256); or_phy_reg(pi, (unsigned int )core_idx == 0U ? 236 : 231, 32768); or_phy_reg(pi, (unsigned int )core_idx == 0U ? 231 : 236, 512); or_phy_reg(pi, (unsigned int )core_idx == 0U ? 231 : 236, 1024); mod_phy_reg(pi, (unsigned int )core_idx == 0U ? 250 : 248, 7168, (int )tx_lpf_bw << 10U); mod_phy_reg(pi, (unsigned int )core_idx == 0U ? 248 : 250, 7, (int )hpvga_hpc); mod_phy_reg(pi, (unsigned int )core_idx == 0U ? 248 : 250, 112, (int )lpf_hpc << 4U); mod_phy_reg(pi, (unsigned int )core_idx == 0U ? 122 : 125, 1792, (int )rx_lpf_bw << 8U); rccal_stepsize = 16; rccal_val = (int )((u16 )rccal_stepsize) + (int )start_rccal_ovr_val; goto ldv_39641; ldv_39640: write_radio_reg(pi, (int )((unsigned int )radio_addr_offset_rx | 107U), (int )rccal_val); if ((int )rccal_stepsize == 16) { wlc_phy_tx_tone_nphy(pi, ref_tone, 181, 0, 1, 0); __const_udelay(8590UL); wlc_phy_rx_iq_est_nphy(pi, (struct phy_iq_est *)(& est), (int )num_samps, 32, 0); if ((unsigned int )core_idx == 0U) { __max1 = (est[0].i_pwr + est[0].q_pwr) >> ((int )log_num_samps + 1); __max2 = 1U; ref_iq_vals = __max1 > __max2 ? __max1 : __max2; } else { __max1___0 = (est[1].i_pwr + est[1].q_pwr) >> ((int )log_num_samps + 1); __max2___0 = 1U; ref_iq_vals = __max1___0 > __max2___0 ? __max1___0 : __max2___0; } wlc_phy_tx_tone_nphy(pi, target_bw, 181, 0, 1, 0); __const_udelay(8590UL); } else { } wlc_phy_rx_iq_est_nphy(pi, (struct phy_iq_est *)(& est), (int )num_samps, 32, 0); if ((unsigned int )core_idx == 0U) { target_iq_vals = (est[0].i_pwr + est[0].q_pwr) >> ((int )log_num_samps + 1); } else { target_iq_vals = (est[1].i_pwr + est[1].q_pwr) >> ((int )log_num_samps + 1); } pwr_ratio = (target_iq_vals << 16) / ref_iq_vals; if ((int )rccal_stepsize == 0) { rccal_stepsize = (s8 )((int )rccal_stepsize - 1); } else if ((int )rccal_stepsize == 1) { last_rccal_val = rccal_val; rccal_val = (pwr_ratio > target_pwr_ratio ? 1U : 65535U) + (unsigned int )rccal_val; last_pwr_ratio = pwr_ratio; rccal_stepsize = (s8 )((int )rccal_stepsize - 1); } else { rccal_stepsize = (s8 )((int )rccal_stepsize >> 1); rccal_val = (pwr_ratio > target_pwr_ratio ? (u16 )rccal_stepsize : - ((int )((u16 )rccal_stepsize))) + (int )rccal_val; } if ((int )rccal_stepsize == -1) { __x___0 = (int )last_pwr_ratio - (int )target_pwr_ratio; ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); __x___2 = (int )pwr_ratio - (int )target_pwr_ratio; ret___0 = (long )(__x___2 < 0 ? - __x___2 : __x___2); best_rccal_val = ret < ret___0 ? last_rccal_val : rccal_val; if (((int )pi->radio_chanspec & 3072) == 3072) { if ((unsigned int )best_rccal_val > 140U || (unsigned int )best_rccal_val <= 134U) { best_rccal_val = 138U; } else { } } else if ((unsigned int )best_rccal_val > 142U || (unsigned int )best_rccal_val <= 136U) { best_rccal_val = 140U; } else { } write_radio_reg(pi, (int )((unsigned int )radio_addr_offset_rx | 107U), (int )best_rccal_val); } else { } ldv_39641: ; if ((int )rccal_stepsize >= 0) { goto ldv_39640; } else { } wlc_phy_stopplayback_nphy(pi); write_radio_reg(pi, (int )((unsigned int )radio_addr_offset_tx | 105U), (int )orig_txlpf_rccal_lpc_ovr_val); write_radio_reg(pi, (int )((unsigned int )radio_addr_offset_rx | 98U), (int )orig_rxlpf_rccal_hpc_ovr_val); mod_phy_reg(pi, 72, 256, (int )orig_dcBypass << 8U); write_phy_reg(pi, 615, (int )orig_RxStrnFilt40Num[0]); write_phy_reg(pi, 616, (int )orig_RxStrnFilt40Num[1]); write_phy_reg(pi, 617, (int )orig_RxStrnFilt40Num[2]); write_phy_reg(pi, 618, (int )orig_RxStrnFilt40Den[0]); write_phy_reg(pi, 619, (int )orig_RxStrnFilt40Den[1]); write_phy_reg(pi, 620, (int )orig_RxStrnFilt40Num[3]); write_phy_reg(pi, 621, (int )orig_RxStrnFilt40Num[4]); write_phy_reg(pi, 622, (int )orig_RxStrnFilt40Num[5]); write_phy_reg(pi, 623, (int )orig_RxStrnFilt40Den[2]); write_phy_reg(pi, 624, (int )orig_RxStrnFilt40Den[3]); write_phy_reg(pi, 231, (int )orig_rfctrloverride[0]); write_phy_reg(pi, 236, (int )orig_rfctrloverride[1]); write_phy_reg(pi, 248, (int )orig_rfctrlauxreg[0]); write_phy_reg(pi, 250, (int )orig_rfctrlauxreg[1]); write_phy_reg(pi, (unsigned int )core_idx == 0U ? 122 : 125, (int )orig_rfctrlrssiothers); pi->nphy_anarxlpf_adjusted = 0; return ((unsigned int )((u8 )best_rccal_val) + 128U); } } static int wlc_phy_cal_rxiq_nphy_rev3(struct brcms_phy *pi , struct nphy_txgains target_gain , u8 cal_type , bool debug ) { u16 orig_BBConfig ; u8 core_no ; u8 rx_core ; u8 best_rccal[2U] ; u16 gain_save[2U] ; u16 cal_gain[2U] ; struct nphy_iqcal_params cal_params[2U] ; u8 rxcore_state ; s8 rxlpf_rccal_hpc ; s8 txlpf_rccal_lpc ; s8 txlpf_idac ; bool phyhang_avoid_state ; bool skip_rxiqcal ; unsigned long __ms ; unsigned long tmp ; int _max1 ; u8 __min1 ; u8 __min2 ; int _max2 ; int _max1___0 ; u8 __min1___0 ; u8 __min2___0 ; int _max2___0 ; { phyhang_avoid_state = 0; skip_rxiqcal = 0; orig_BBConfig = read_phy_reg(pi, 1); mod_phy_reg(pi, 1, 32768, 0); wlc_phy_stay_in_carriersearch_nphy(pi, 1); if (pi->pubpi.phy_rev > 3U) { phyhang_avoid_state = pi->phyhang_avoid; pi->phyhang_avoid = 0; } else { } wlc_phy_table_read_nphy(pi, 7U, 2U, 272U, 16U, (void *)(& gain_save)); core_no = 0U; goto ldv_39663; ldv_39662: wlc_phy_iqcal_gainparams_nphy(pi, (int )core_no, target_gain, (struct nphy_iqcal_params *)(& cal_params) + (unsigned long )core_no); cal_gain[(int )core_no] = cal_params[(int )core_no].cal_gain; core_no = (u8 )((int )core_no + 1); ldv_39663: ; if ((unsigned int )core_no <= 1U) { goto ldv_39662; } else { } wlc_phy_table_write_nphy(pi, 7U, 2U, 272U, 16U, (void const *)(& cal_gain)); rxcore_state = wlc_phy_rxcore_getstate_nphy((struct brcms_phy_pub *)pi); rx_core = 0U; goto ldv_39670; ldv_39669: skip_rxiqcal = (((int )rxcore_state >> (int )rx_core) & 1) == 0; wlc_phy_rxcal_physetup_nphy(pi, (int )rx_core); wlc_phy_rxcal_radio_setup_nphy(pi, (int )rx_core); if (! skip_rxiqcal && ((unsigned int )cal_type == 0U || (unsigned int )cal_type == 2U)) { wlc_phy_rxcal_gainctrl_nphy(pi, (int )rx_core, (u16 *)0U, 0); wlc_phy_tx_tone_nphy(pi, ((int )pi->radio_chanspec & 3072) == 3072 ? 4000U : 2000U, 181, 0, (int )cal_type, 0); if ((int )debug) { __ms = 4000UL; goto ldv_39667; ldv_39666: __const_udelay(4295000UL); ldv_39667: tmp = __ms; __ms = __ms - 1UL; if (tmp != 0UL) { goto ldv_39666; } else { } } else { } wlc_phy_calc_rx_iq_comp_nphy(pi, (int )((unsigned int )rx_core + 1U)); wlc_phy_stopplayback_nphy(pi); } else { } if (((unsigned int )cal_type == 1U || (unsigned int )cal_type == 2U) && pi->pubpi.phy_rev <= 6U) { if ((unsigned int )rx_core == 1U) { if ((unsigned int )rxcore_state == 1U) { wlc_phy_rxcore_setstate_nphy((struct brcms_phy_pub *)pi, 3); } else { } wlc_phy_rxcal_gainctrl_nphy(pi, (int )rx_core, (u16 *)0U, 1); best_rccal[(int )rx_core] = wlc_phy_rc_sweep_nphy(pi, (int )rx_core, 1); pi->nphy_rccal_value = (u16 )best_rccal[(int )rx_core]; if ((unsigned int )rxcore_state == 1U) { wlc_phy_rxcore_setstate_nphy((struct brcms_phy_pub *)pi, (int )rxcore_state); } else { } } else { } } else { } wlc_phy_rxcal_radio_cleanup_nphy(pi, (int )rx_core); wlc_phy_rxcal_phycleanup_nphy(pi, (int )rx_core); wlc_phy_force_rfseq_nphy(pi, 2); rx_core = (u8 )((int )rx_core + 1); ldv_39670: ; if ((int )pi->pubpi.phy_corenum > (int )rx_core) { goto ldv_39669; } else { } if ((unsigned int )cal_type == 1U || (unsigned int )cal_type == 2U) { best_rccal[0] = best_rccal[1]; write_radio_reg(pi, 24683, (int )((unsigned int )best_rccal[0] | 128U)); rx_core = 0U; goto ldv_39691; ldv_39690: rxlpf_rccal_hpc = (s8 )((unsigned int )((unsigned char )(((int )best_rccal[(int )rx_core] + -12) >> 1)) + 10U); txlpf_rccal_lpc = (s8 )((unsigned int )best_rccal[(int )rx_core] + 254U); if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { txlpf_rccal_lpc = (s8 )(((unsigned int )pi->bw == 3072U ? 24U : 12U) + (unsigned int )((unsigned char )txlpf_rccal_lpc)); txlpf_idac = (unsigned int )pi->bw == 3072U ? 14 : 19; write_radio_reg(pi, (unsigned int )rx_core == 0U ? 8312 : 12408, (int )((u16 )txlpf_idac)); } else { } __min1 = (u8 )rxlpf_rccal_hpc; __min2 = 31U; _max1 = (int )__min1 < (int )__min2 ? __min1 : __min2; _max2 = 0; rxlpf_rccal_hpc = (s8 )(_max1 > _max2 ? _max1 : _max2); __min1___0 = (u8 )txlpf_rccal_lpc; __min2___0 = 31U; _max1___0 = (int )__min1___0 < (int )__min2___0 ? __min1___0 : __min2___0; _max2___0 = 0; txlpf_rccal_lpc = (s8 )(_max1___0 > _max2___0 ? _max1___0 : _max2___0); write_radio_reg(pi, (unsigned int )rx_core == 0U ? 24674 : 28770, (int )((u16 )((int )((short )rxlpf_rccal_hpc) | 128))); write_radio_reg(pi, (unsigned int )rx_core == 0U ? 8297 : 12393, (int )((u16 )((int )((short )txlpf_rccal_lpc) | 128))); rx_core = (u8 )((int )rx_core + 1); ldv_39691: ; if ((int )pi->pubpi.phy_corenum > (int )rx_core) { goto ldv_39690; } else { } } else { } write_phy_reg(pi, 1, (int )orig_BBConfig); wlc_phy_resetcca_nphy(pi); if (pi->pubpi.phy_rev > 6U) { wlc_phy_rfctrl_override_1tomany_nphy(pi, 3, 0, 3, 1); } else { wlc_phy_rfctrl_override_nphy(pi, 4096, 0, 3, 1); } wlc_phy_force_rfseq_nphy(pi, 2); wlc_phy_table_write_nphy(pi, 7U, 2U, 272U, 16U, (void const *)(& gain_save)); if (pi->pubpi.phy_rev > 3U) { pi->phyhang_avoid = phyhang_avoid_state; } else { } wlc_phy_stay_in_carriersearch_nphy(pi, 0); return (0); } } static int wlc_phy_cal_rxiq_nphy_rev2(struct brcms_phy *pi , struct nphy_txgains target_gain , bool debug ) { struct phy_iq_est est[4U] ; u8 core_num ; u8 rx_core ; u8 tx_core ; u16 lna_vals[3U] ; u16 hpf1_vals[3U] ; u16 hpf2_vals[3U] ; s16 curr_hpf1 ; s16 curr_hpf2 ; s16 curr_hpf ; s16 curr_lna ; s16 desired_log2_pwr ; s16 actual_log2_pwr ; s16 hpf_change ; u16 orig_RfseqCoreActv ; u16 orig_AfectrlCore ; u16 orig_AfectrlOverride ; u16 orig_RfctrlIntcRx ; u16 orig_RfctrlIntcTx ; u16 num_samps ; u32 i_pwr ; u32 q_pwr ; u32 tot_pwr[3U] ; u8 gain_pass ; u8 use_hpf_num ; u16 mask ; u16 val1 ; u16 val2 ; u16 core_no ; u16 gain_save[2U] ; u16 cal_gain[2U] ; struct nphy_iqcal_params cal_params[2U] ; u8 phy_bw ; int bcmerror ; bool first_playtone ; unsigned long __ms ; unsigned long tmp ; u8 tmp___0 ; u8 tmp___1 ; u8 tmp___2 ; int _max1 ; u16 __min1 ; u16 __min2 ; int _max2 ; { lna_vals[0] = 3U; lna_vals[1] = 3U; lna_vals[2] = 1U; hpf1_vals[0] = 7U; hpf1_vals[1] = 2U; hpf1_vals[2] = 0U; hpf2_vals[0] = 2U; hpf2_vals[1] = 0U; hpf2_vals[2] = 0U; bcmerror = 0; first_playtone = 1; wlc_phy_stay_in_carriersearch_nphy(pi, 1); if (pi->pubpi.phy_rev <= 1U) { wlc_phy_reapply_txcal_coeffs_nphy(pi); } else { } wlc_phy_table_read_nphy(pi, 7U, 2U, 272U, 16U, (void *)(& gain_save)); core_no = 0U; goto ldv_39734; ldv_39733: wlc_phy_iqcal_gainparams_nphy(pi, (int )core_no, target_gain, (struct nphy_iqcal_params *)(& cal_params) + (unsigned long )core_no); cal_gain[(int )core_no] = cal_params[(int )core_no].cal_gain; core_no = (u16 )((int )core_no + 1); ldv_39734: ; if ((unsigned int )core_no <= 1U) { goto ldv_39733; } else { } wlc_phy_table_write_nphy(pi, 7U, 2U, 272U, 16U, (void const *)(& cal_gain)); num_samps = 1024U; desired_log2_pwr = 13; core_num = 0U; goto ldv_39754; ldv_39753: rx_core = core_num; tx_core = 1U - (unsigned int )core_num; orig_RfseqCoreActv = read_phy_reg(pi, 162); orig_AfectrlCore = read_phy_reg(pi, (unsigned int )rx_core == 0U ? 166 : 167); orig_AfectrlOverride = read_phy_reg(pi, 165); orig_RfctrlIntcRx = read_phy_reg(pi, (unsigned int )rx_core == 0U ? 145 : 146); orig_RfctrlIntcTx = read_phy_reg(pi, (unsigned int )tx_core == 0U ? 145 : 146); mod_phy_reg(pi, 162, 61440, (int )((u16 )(1 << (int )tx_core)) << 12U); mod_phy_reg(pi, 162, 15, (int )((u16 )(1 << (int )tx_core))); or_phy_reg(pi, (unsigned int )rx_core == 0U ? 166 : 167, 6); or_phy_reg(pi, 165, 6); if ((pi->nphy_rxcalparams & 4278190080U) != 0U) { write_phy_reg(pi, (unsigned int )rx_core == 0U ? 145 : 146, ((int )pi->radio_chanspec & 61440) == 4096 ? 320 : 272); } else { write_phy_reg(pi, (unsigned int )rx_core == 0U ? 145 : 146, ((int )pi->radio_chanspec & 61440) == 4096 ? 384 : 288); } write_phy_reg(pi, (unsigned int )tx_core == 0U ? 145 : 146, ((int )pi->radio_chanspec & 61440) == 4096 ? 328 : 276); mask = 3U; if ((unsigned int )rx_core == 0U) { val1 = 1U; val2 = 2U; } else { val1 = 2U; val2 = 1U; } if ((pi->nphy_rxcalparams & 65536U) != 0U) { mod_radio_reg(pi, 214, (int )mask, (int )val1); mod_radio_reg(pi, 226, (int )mask, (int )val2); } else { } gain_pass = 0U; goto ldv_39751; ldv_39750: ; if ((int )debug) { __ms = 4000UL; goto ldv_39738; ldv_39737: __const_udelay(4295000UL); ldv_39738: tmp = __ms; __ms = __ms - 1UL; if (tmp != 0UL) { goto ldv_39737; } else { } } else { } if ((unsigned int )gain_pass <= 2U) { curr_lna = (s16 )lna_vals[(int )gain_pass]; curr_hpf1 = (s16 )hpf1_vals[(int )gain_pass]; curr_hpf2 = (s16 )hpf2_vals[(int )gain_pass]; } else { if (tot_pwr[1] > 10000U) { curr_lna = (s16 )lna_vals[2]; curr_hpf1 = (s16 )hpf1_vals[2]; curr_hpf2 = (s16 )hpf2_vals[2]; use_hpf_num = 1U; curr_hpf = curr_hpf1; tmp___0 = wlc_phy_nbits((s32 )tot_pwr[2]); actual_log2_pwr = (s16 )tmp___0; } else if (tot_pwr[0] > 10000U) { curr_lna = (s16 )lna_vals[1]; curr_hpf1 = (s16 )hpf1_vals[1]; curr_hpf2 = (s16 )hpf2_vals[1]; use_hpf_num = 1U; curr_hpf = curr_hpf1; tmp___1 = wlc_phy_nbits((s32 )tot_pwr[1]); actual_log2_pwr = (s16 )tmp___1; } else { curr_lna = (s16 )lna_vals[0]; curr_hpf1 = (s16 )hpf1_vals[0]; curr_hpf2 = (s16 )hpf2_vals[0]; use_hpf_num = 2U; curr_hpf = curr_hpf2; tmp___2 = wlc_phy_nbits((s32 )tot_pwr[0]); actual_log2_pwr = (s16 )tmp___2; } hpf_change = (s16 )((int )((unsigned short )desired_log2_pwr) - (int )((unsigned short )actual_log2_pwr)); curr_hpf = (s16 )((int )((unsigned short )curr_hpf) + (int )((unsigned short )hpf_change)); __min1 = (u16 )curr_hpf; __min2 = 10U; _max1 = (int )__min1 < (int )__min2 ? __min1 : __min2; _max2 = 0; curr_hpf = (s16 )(_max1 > _max2 ? _max1 : _max2); if ((unsigned int )use_hpf_num == 1U) { curr_hpf1 = curr_hpf; } else { curr_hpf2 = curr_hpf; } } wlc_phy_rfctrl_override_nphy(pi, 1024, (int )((u16 )(((int )((short )((int )curr_hpf2 << 8)) | (int )((short )((int )curr_hpf1 << 4))) | (int )((short )((int )curr_lna << 2)))), 3, 0); wlc_phy_force_rfseq_nphy(pi, 2); wlc_phy_stopplayback_nphy(pi); if ((int )first_playtone) { bcmerror = wlc_phy_tx_tone_nphy(pi, 4000U, (int )((unsigned short )pi->nphy_rxcalparams), 0, 0, 1); first_playtone = 0; } else { phy_bw = ((int )pi->radio_chanspec & 3072) == 3072 ? 40U : 20U; wlc_phy_runsamples_nphy(pi, (int )((unsigned int )((u16 )phy_bw) * 8U), 65535, 0, 0, 0, 1); } if (bcmerror == 0) { if ((unsigned int )gain_pass <= 2U) { wlc_phy_rx_iq_est_nphy(pi, (struct phy_iq_est *)(& est), (int )num_samps, 32, 0); i_pwr = (est[(int )rx_core].i_pwr + (unsigned int )num_samps / 2U) / (u32 )num_samps; q_pwr = (est[(int )rx_core].q_pwr + (unsigned int )num_samps / 2U) / (u32 )num_samps; tot_pwr[(int )gain_pass] = i_pwr + q_pwr; } else { wlc_phy_calc_rx_iq_comp_nphy(pi, (int )((u8 )(1 << (int )rx_core))); } wlc_phy_stopplayback_nphy(pi); } else { } if (bcmerror != 0) { goto ldv_39749; } else { } gain_pass = (u8 )((int )gain_pass + 1); ldv_39751: ; if ((unsigned int )gain_pass <= 3U) { goto ldv_39750; } else { } ldv_39749: and_radio_reg(pi, 214, ~ ((int )mask)); and_radio_reg(pi, 226, ~ ((int )mask)); write_phy_reg(pi, (unsigned int )tx_core == 0U ? 145 : 146, (int )orig_RfctrlIntcTx); write_phy_reg(pi, (unsigned int )rx_core == 0U ? 145 : 146, (int )orig_RfctrlIntcRx); write_phy_reg(pi, 165, (int )orig_AfectrlOverride); write_phy_reg(pi, (unsigned int )rx_core == 0U ? 166 : 167, (int )orig_AfectrlCore); write_phy_reg(pi, 162, (int )orig_RfseqCoreActv); if (bcmerror != 0) { goto ldv_39752; } else { } core_num = (u8 )((int )core_num + 1); ldv_39754: ; if ((unsigned int )core_num <= 1U) { goto ldv_39753; } else { } ldv_39752: wlc_phy_rfctrl_override_nphy(pi, 1024, 0, 3, 1); wlc_phy_force_rfseq_nphy(pi, 2); wlc_phy_table_write_nphy(pi, 7U, 2U, 272U, 16U, (void const *)(& gain_save)); wlc_phy_stay_in_carriersearch_nphy(pi, 0); return (bcmerror); } } int wlc_phy_cal_rxiq_nphy(struct brcms_phy *pi , struct nphy_txgains target_gain , u8 cal_type , bool debug ) { int tmp ; int tmp___0 ; { if (pi->pubpi.phy_rev > 6U) { cal_type = 0U; } else { } if (pi->pubpi.phy_rev > 2U) { tmp = wlc_phy_cal_rxiq_nphy_rev3(pi, target_gain, (int )cal_type, (int )debug); return (tmp); } else { tmp___0 = wlc_phy_cal_rxiq_nphy_rev2(pi, target_gain, (int )debug); return (tmp___0); } } } void wlc_phy_txpwr_fixpower_nphy(struct brcms_phy *pi ) { uint core ; u32 txgain ; u16 rad_gain ; u16 dac_gain ; u16 bbmult ; u16 m1m2 ; u8 txpi[2U] ; u8 chan_freq_range ; s32 rfpwr_offset ; uint phyrev ; u32 *tx_gaintbl ; u32 *tmp ; { if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } if ((pi->sh)->sromrev <= 3U) { txpi[1] = 72U; txpi[0] = txpi[1]; } else { chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, 0U); switch ((int )chan_freq_range) { case 0: ; case 1: ; case 2: ; case 3: txpi[0] = 0U; txpi[1] = 0U; goto ldv_39777; default: txpi[1] = 91U; txpi[0] = txpi[1]; goto ldv_39777; } ldv_39777: ; } if (pi->pubpi.phy_rev > 6U) { txpi[1] = 30U; txpi[0] = txpi[1]; } else if (pi->pubpi.phy_rev > 2U) { txpi[1] = 40U; txpi[0] = txpi[1]; } else { } if (pi->pubpi.phy_rev <= 6U) { if ((((unsigned int )txpi[0] <= 39U || (unsigned int )txpi[0] > 100U) || (unsigned int )txpi[1] <= 39U) || (unsigned int )txpi[1] > 100U) { txpi[1] = 91U; txpi[0] = txpi[1]; } else { } } else { } pi->nphy_txpwrindex[0].index_internal = (s8 )txpi[0]; pi->nphy_txpwrindex[1].index_internal = (s8 )txpi[1]; pi->nphy_txpwrindex[0].index_internal_save = (s8 )txpi[0]; pi->nphy_txpwrindex[1].index_internal_save = (s8 )txpi[1]; core = 0U; goto ldv_39782; ldv_39781: phyrev = pi->pubpi.phy_rev; if (phyrev > 2U) { if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { tmp = wlc_phy_get_ipa_gaintbl_nphy(pi); tx_gaintbl = tmp; txgain = *(tx_gaintbl + (unsigned long )txpi[core]); } else if (((int )pi->radio_chanspec & 61440) == 4096) { if (phyrev == 3U) { txgain = nphy_tpc_5GHz_txgain_rev3[(int )txpi[core]]; } else if (phyrev == 4U) { txgain = (unsigned int )pi->srom_fem5g.extpagain == 3U ? nphy_tpc_5GHz_txgain_HiPwrEPA[(int )txpi[core]] : nphy_tpc_5GHz_txgain_rev4[(int )txpi[core]]; } else { txgain = nphy_tpc_5GHz_txgain_rev5[(int )txpi[core]]; } } else if (phyrev > 4U && (unsigned int )pi->srom_fem2g.extpagain == 3U) { txgain = nphy_tpc_txgain_HiPwrEPA[(int )txpi[core]]; } else { txgain = nphy_tpc_txgain_rev3[(int )txpi[core]]; } } else { txgain = nphy_tpc_txgain[(int )txpi[core]]; } if (phyrev > 2U) { rad_gain = (u16 )(txgain >> 16); } else { rad_gain = (unsigned int )((u16 )(txgain >> 16)) & 8191U; } if (phyrev > 6U) { dac_gain = (unsigned int )((u16 )(txgain >> 8)) & 7U; } else { dac_gain = (unsigned int )((u16 )(txgain >> 8)) & 63U; } bbmult = (unsigned int )((u16 )txgain) & 255U; if (phyrev > 2U) { mod_phy_reg(pi, core == 0U ? 143 : 165, 256, 256); } else { mod_phy_reg(pi, 165, 16384, 16384); } write_phy_reg(pi, core == 0U ? 170 : 171, (int )dac_gain); wlc_phy_table_write_nphy(pi, 7U, 1U, core + 272U, 16U, (void const *)(& rad_gain)); wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& m1m2)); m1m2 = (u16 )((core == 0U ? 255 : -256) & (int )((short )m1m2)); m1m2 = (u16 )((core == 0U ? (short )((int )bbmult << 8) : (short )bbmult) | (int )((short )m1m2)); wlc_phy_table_write_nphy(pi, 15U, 1U, 87U, 16U, (void const *)(& m1m2)); if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { wlc_phy_table_read_nphy(pi, core == 0U ? 26U : 27U, 1U, (u32 )((int )txpi[core] + 576), 32U, (void *)(& rfpwr_offset)); mod_phy_reg(pi, core == 0U ? 663 : 667, 8176, (int )((u16 )rfpwr_offset) << 4U); mod_phy_reg(pi, core == 0U ? 663 : 667, 4, 4); } else { } core = core + 1U; ldv_39782: ; if ((uint )pi->pubpi.phy_corenum > core) { goto ldv_39781; } else { } and_phy_reg(pi, 191, 65504); if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } static void wlc_phy_txpwr_nphy_srom_convert(u8 *srom_max , u16 *pwr_offset , u8 tmp_max_pwr , u8 rate_start , u8 rate_end ) { u8 rate ; u8 word_num ; u8 nibble_num ; u8 tmp_nibble ; { rate = rate_start; goto ldv_39796; ldv_39795: word_num = (u8 )(((int )rate - (int )rate_start) >> 2); nibble_num = (unsigned int )((u8 )((int )rate - (int )rate_start)) & 3U; tmp_nibble = (unsigned int )((u8 )((int )*(pwr_offset + (unsigned long )word_num) >> (int )nibble_num * 4)) & 15U; *(srom_max + (unsigned long )rate) = (unsigned int )tmp_nibble * 254U + (unsigned int )tmp_max_pwr; rate = (u8 )((int )rate + 1); ldv_39796: ; if ((int )rate <= (int )rate_end) { goto ldv_39795; } else { } return; } } static void wlc_phy_txpwr_nphy_po_apply(u8 *srom_max , u8 pwr_offset , u8 rate_start , u8 rate_end ) { u8 rate ; { rate = rate_start; goto ldv_39806; ldv_39805: *(srom_max + (unsigned long )rate) = (unsigned int )*(srom_max + (unsigned long )rate) + (unsigned int )pwr_offset * 254U; rate = (u8 )((int )rate + 1); ldv_39806: ; if ((int )rate <= (int )rate_end) { goto ldv_39805; } else { } return; } } void wlc_phy_ofdm_to_mcs_powers_nphy(u8 *power , u8 rate_mcs_start , u8 rate_mcs_end , u8 rate_ofdm_start ) { u8 rate1 ; u8 rate2 ; { rate2 = rate_ofdm_start; rate1 = rate_mcs_start; goto ldv_39817; ldv_39816: *(power + (unsigned long )rate1) = *(power + (unsigned long )rate2); rate2 = ((int )rate1 == (int )rate_mcs_start ? 2U : 1U) + (unsigned int )rate2; rate1 = (u8 )((int )rate1 + 1); ldv_39817: ; if ((int )rate1 <= (int )rate_mcs_end + -1) { goto ldv_39816; } else { } *(power + (unsigned long )rate_mcs_end) = *(power + ((unsigned long )rate_mcs_end + 0xffffffffffffffffUL)); return; } } void wlc_phy_mcs_to_ofdm_powers_nphy(u8 *power , u8 rate_ofdm_start , u8 rate_ofdm_end , u8 rate_mcs_start ) { u8 rate1 ; u8 rate2 ; { rate1 = rate_ofdm_start; rate2 = rate_mcs_start; goto ldv_39828; ldv_39827: *(power + (unsigned long )rate1) = *(power + (unsigned long )rate2); if ((int )rate1 == (int )rate_ofdm_start) { rate1 = (u8 )((int )rate1 + 1); *(power + (unsigned long )rate1) = *(power + (unsigned long )rate2); } else { } rate1 = (u8 )((int )rate1 + 1); rate2 = (u8 )((int )rate2 + 1); ldv_39828: ; if ((int )rate1 <= (int )rate_ofdm_end) { goto ldv_39827; } else { } return; } } void wlc_phy_txpwr_apply_nphy(struct brcms_phy *pi ) { uint rate1 ; uint rate2 ; uint band_num ; u8 tmp_bw40po ; u8 tmp_cddpo ; u8 tmp_stbcpo ; u8 tmp_max_pwr ; u16 pwr_offsets1[2U] ; u16 *pwr_offsets2 ; u8 *tx_srom_max_rate ; s8 _min1 ; s8 _min2 ; s8 _min1___0 ; s8 _min2___0 ; s8 _min1___1 ; s8 _min2___1 ; s8 _min1___2 ; s8 _min2___2 ; { tmp_bw40po = 0U; tmp_cddpo = 0U; tmp_stbcpo = 0U; tmp_max_pwr = 0U; pwr_offsets2 = (u16 *)0U; tx_srom_max_rate = (u8 *)0U; band_num = 0U; goto ldv_39864; ldv_39863: ; switch (band_num) { case 0U: _min1 = pi->nphy_pwrctrl_info[0].max_pwr_2g; _min2 = pi->nphy_pwrctrl_info[1].max_pwr_2g; tmp_max_pwr = (u8 )((int )_min1 < (int )_min2 ? _min1 : _min2); pwr_offsets1[0] = pi->cck2gpo; wlc_phy_txpwr_nphy_srom_convert((u8 *)(& pi->tx_srom_max_rate_2g), (u16 *)(& pwr_offsets1), (int )tmp_max_pwr, 0, 3); pwr_offsets1[0] = (unsigned short )pi->ofdm2gpo; pwr_offsets1[1] = (u16 )(pi->ofdm2gpo >> 16); pwr_offsets2 = (u16 *)(& pi->mcs2gpo); tmp_cddpo = pi->cdd2gpo; tmp_stbcpo = pi->stbc2gpo; tmp_bw40po = pi->bw402gpo; tx_srom_max_rate = (u8 *)(& pi->tx_srom_max_rate_2g); goto ldv_39847; case 1U: _min1___0 = pi->nphy_pwrctrl_info[0].max_pwr_5gm; _min2___0 = pi->nphy_pwrctrl_info[1].max_pwr_5gm; tmp_max_pwr = (u8 )((int )_min1___0 < (int )_min2___0 ? _min1___0 : _min2___0); pwr_offsets1[0] = (unsigned short )pi->ofdm5gpo; pwr_offsets1[1] = (u16 )(pi->ofdm5gpo >> 16); pwr_offsets2 = (u16 *)(& pi->mcs5gpo); tmp_cddpo = pi->cdd5gpo; tmp_stbcpo = pi->stbc5gpo; tmp_bw40po = pi->bw405gpo; tx_srom_max_rate = (u8 *)(& pi->tx_srom_max_rate_5g_mid); goto ldv_39847; case 2U: _min1___1 = pi->nphy_pwrctrl_info[0].max_pwr_5gl; _min2___1 = pi->nphy_pwrctrl_info[1].max_pwr_5gl; tmp_max_pwr = (u8 )((int )_min1___1 < (int )_min2___1 ? _min1___1 : _min2___1); pwr_offsets1[0] = (unsigned short )pi->ofdm5glpo; pwr_offsets1[1] = (u16 )(pi->ofdm5glpo >> 16); pwr_offsets2 = (u16 *)(& pi->mcs5glpo); tmp_cddpo = pi->cdd5glpo; tmp_stbcpo = pi->stbc5glpo; tmp_bw40po = pi->bw405glpo; tx_srom_max_rate = (u8 *)(& pi->tx_srom_max_rate_5g_low); goto ldv_39847; case 3U: _min1___2 = pi->nphy_pwrctrl_info[0].max_pwr_5gh; _min2___2 = pi->nphy_pwrctrl_info[1].max_pwr_5gh; tmp_max_pwr = (u8 )((int )_min1___2 < (int )_min2___2 ? _min1___2 : _min2___2); pwr_offsets1[0] = (unsigned short )pi->ofdm5ghpo; pwr_offsets1[1] = (u16 )(pi->ofdm5ghpo >> 16); pwr_offsets2 = (u16 *)(& pi->mcs5ghpo); tmp_cddpo = pi->cdd5ghpo; tmp_stbcpo = pi->stbc5ghpo; tmp_bw40po = pi->bw405ghpo; tx_srom_max_rate = (u8 *)(& pi->tx_srom_max_rate_5g_hi); goto ldv_39847; } ldv_39847: wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, (u16 *)(& pwr_offsets1), (int )tmp_max_pwr, 4, 11); wlc_phy_ofdm_to_mcs_powers_nphy(tx_srom_max_rate, 20, 27, 4); wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2, (int )tmp_max_pwr, 28, 35); if (pi->pubpi.phy_rev > 2U) { wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, (int )tmp_cddpo, 28, 35); } else { } wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate, 12, 19, 28); wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2, (int )tmp_max_pwr, 36, 43); if (pi->pubpi.phy_rev > 2U) { wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, (int )tmp_stbcpo, 36, 43); } else { } wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2 + 2UL, (int )tmp_max_pwr, 44, 51); if (pi->pubpi.phy_rev > 4U) { wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2 + 4UL, (int )tmp_max_pwr, 68, 75); wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate, 52, 59, 68); wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2 + 4UL, (int )tmp_max_pwr, 76, 83); wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, (int )tmp_cddpo, 76, 83); wlc_phy_mcs_to_ofdm_powers_nphy(tx_srom_max_rate, 60, 67, 76); wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2 + 4UL, (int )tmp_max_pwr, 84, 91); wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, (int )tmp_stbcpo, 84, 91); wlc_phy_txpwr_nphy_srom_convert(tx_srom_max_rate, pwr_offsets2 + 6UL, (int )tmp_max_pwr, 92, 99); } else { rate1 = 52U; rate2 = 4U; goto ldv_39861; ldv_39860: *(tx_srom_max_rate + (unsigned long )rate1) = *(tx_srom_max_rate + (unsigned long )rate2); rate1 = rate1 + 1U; rate2 = rate2 + 1U; ldv_39861: ; if (rate1 <= 99U) { goto ldv_39860; } else { } } if (pi->pubpi.phy_rev > 2U) { wlc_phy_txpwr_nphy_po_apply(tx_srom_max_rate, (int )tmp_bw40po, 52, 99); } else { } *(tx_srom_max_rate + 100UL) = *(tx_srom_max_rate + 76UL); band_num = band_num + 1U; ldv_39864: ; if (band_num <= 3U) { goto ldv_39863; } else { } return; } } void wlc_phy_txpower_recalc_target_nphy(struct brcms_phy *pi ) { u8 tx_pwr_ctrl_state ; { wlc_phy_txpwr_limit_to_tbl_nphy(pi); wlc_phy_txpwrctrl_pwr_setup_nphy(pi); tx_pwr_ctrl_state = pi->nphy_txpwrctrl; if ((pi->sh)->corerev == 11U || (pi->sh)->corerev == 12U) { wlapi_bmac_mctrl((pi->sh)->physhim, 2097152U, 2097152U); bcma_read32(pi->d11core, 288); __const_udelay(4295UL); } else { } wlc_phy_txpwrctrl_enable_nphy(pi, (int )tx_pwr_ctrl_state); if ((pi->sh)->corerev == 11U || (pi->sh)->corerev == 12U) { wlapi_bmac_mctrl((pi->sh)->physhim, 2097152U, 0U); } else { } return; } } static bool wlc_phy_txpwr_ison_nphy(struct brcms_phy *pi ) { u16 tmp ; { tmp = read_phy_reg(pi, 487); return (((int )tmp & 57344) != 0); } } u16 wlc_phy_txpwr_idx_get_nphy(struct brcms_phy *pi ) { u16 tmp ; u16 pwr_idx[2U] ; u8 tmp___0 ; u8 tmp___1 ; bool tmp___2 ; { tmp___2 = wlc_phy_txpwr_ison_nphy(pi); if ((int )tmp___2) { tmp___0 = wlc_phy_txpwr_idx_cur_get_nphy(pi, 0); pwr_idx[0] = (u16 )tmp___0; tmp___1 = wlc_phy_txpwr_idx_cur_get_nphy(pi, 1); pwr_idx[1] = (u16 )tmp___1; tmp = (u16 )((int )((short )((int )pwr_idx[0] << 8)) | (int )((short )pwr_idx[1])); } else { tmp = (u16 )((int )((short )((int )pi->nphy_txpwrindex[0].index_internal << 8)) | ((int )((short )pi->nphy_txpwrindex[1].index_internal) & 255)); } return (tmp); } } void wlc_phy_txpwr_papd_cal_nphy(struct brcms_phy *pi ) { bool tmp ; long ret ; int __x___0 ; u8 tmp___1 ; long ret___0 ; int __x___2 ; u8 tmp___3 ; { if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { if ((int )pi->nphy_force_papd_cal) { wlc_phy_a4(pi, 1); } else { tmp = wlc_phy_txpwr_ison_nphy(pi); if ((int )tmp) { tmp___1 = wlc_phy_txpwr_idx_cur_get_nphy(pi, 0); __x___0 = (int )tmp___1 - (int )pi->nphy_papd_tx_gain_at_last_cal[0]; ret = (long )(__x___0 < 0 ? - __x___0 : __x___0); if ((unsigned int )ret > 3U) { wlc_phy_a4(pi, 1); } else { tmp___3 = wlc_phy_txpwr_idx_cur_get_nphy(pi, 1); __x___2 = (int )tmp___3 - (int )pi->nphy_papd_tx_gain_at_last_cal[1]; ret___0 = (long )(__x___2 < 0 ? - __x___2 : __x___2); if ((unsigned int )ret___0 > 3U) { wlc_phy_a4(pi, 1); } else { } } } else { } } } else { } return; } } void wlc_phy_txpwrctrl_enable_nphy(struct brcms_phy *pi , u8 ctrl_type ) { u16 mask ; u16 val ; u16 ishw ; u8 ctr ; uint core ; u32 tbl_offset ; u32 tbl_len ; u16 regval[84U] ; bool tmp ; { mask = 0U; val = 0U; ishw = 0U; if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } switch ((int )ctrl_type) { case 0: ; case 1: pi->nphy_txpwrctrl = ctrl_type; goto ldv_39903; default: ; goto ldv_39903; } ldv_39903: ; if ((unsigned int )ctrl_type == 0U) { if (pi->pubpi.phy_rev > 2U) { tmp = wlc_phy_txpwr_ison_nphy(pi); if ((int )tmp) { core = 0U; goto ldv_39906; ldv_39905: pi->nphy_txpwr_idx[core] = wlc_phy_txpwr_idx_cur_get_nphy(pi, (int )((unsigned char )core)); core = core + 1U; ldv_39906: ; if ((uint )pi->pubpi.phy_corenum > core) { goto ldv_39905; } else { } } else { } } else { } tbl_len = 84U; tbl_offset = 64U; ctr = 0U; goto ldv_39909; ldv_39908: regval[(int )ctr] = 0U; ctr = (u8 )((int )ctr + 1); ldv_39909: ; if ((u32 )ctr < tbl_len) { goto ldv_39908; } else { } wlc_phy_table_write_nphy(pi, 26U, tbl_len, tbl_offset, 16U, (void const *)(& regval)); wlc_phy_table_write_nphy(pi, 27U, tbl_len, tbl_offset, 16U, (void const *)(& regval)); if (pi->pubpi.phy_rev > 2U) { and_phy_reg(pi, 487, 8191); } else { and_phy_reg(pi, 487, 40959); } if (pi->pubpi.phy_rev > 2U) { or_phy_reg(pi, 143, 256); or_phy_reg(pi, 165, 256); } else { or_phy_reg(pi, 165, 16384); } if (pi->pubpi.phy_rev == 2U) { mod_phy_reg(pi, 220, 255, 83); } else if (pi->pubpi.phy_rev <= 1U) { mod_phy_reg(pi, 220, 255, 90); } else { } if (pi->pubpi.phy_rev <= 1U && (unsigned int )pi->bw == 3072U) { wlapi_bmac_mhf((pi->sh)->physhim, 0, 512, 512, 3); } else { } } else { wlc_phy_table_write_nphy(pi, 26U, 84U, 64U, 8U, (void const *)(& pi->adj_pwr_tbl_nphy)); wlc_phy_table_write_nphy(pi, 27U, 84U, 64U, 8U, (void const *)(& pi->adj_pwr_tbl_nphy)); ishw = (unsigned int )ctrl_type == 1U; mask = 24576U; val = (u16 )((int )((short )((int )ishw << 14)) | (int )((short )((int )ishw << 13))); if (pi->pubpi.phy_rev > 2U) { mask = (u16 )((unsigned int )mask | 32768U); val = (u16 )((int )((short )((int )ishw << 15)) | (int )((short )val)); } else { } mod_phy_reg(pi, 487, (int )mask, (int )val); if (((int )pi->radio_chanspec & 61440) == 4096) { if (pi->pubpi.phy_rev > 6U) { mod_phy_reg(pi, 487, 127, 50); mod_phy_reg(pi, 546, 255, 50); } else { mod_phy_reg(pi, 487, 127, 100); if (pi->pubpi.phy_rev > 1U) { mod_phy_reg(pi, 546, 255, 100); } else { } } } else { } if (pi->pubpi.phy_rev > 2U) { if ((unsigned int )pi->nphy_txpwr_idx[0] != 128U && (unsigned int )pi->nphy_txpwr_idx[1] != 128U) { wlc_phy_txpwr_idx_cur_set_nphy(pi, (int )pi->nphy_txpwr_idx[0], (int )pi->nphy_txpwr_idx[1]); } else { } } else { } if (pi->pubpi.phy_rev > 2U) { and_phy_reg(pi, 143, 65279); and_phy_reg(pi, 165, 65279); } else { and_phy_reg(pi, 165, 49151); } if (pi->pubpi.phy_rev == 2U) { mod_phy_reg(pi, 220, 255, 59); } else if (pi->pubpi.phy_rev <= 1U) { mod_phy_reg(pi, 220, 255, 64); } else { } if (pi->pubpi.phy_rev <= 1U && (unsigned int )pi->bw == 3072U) { wlapi_bmac_mhf((pi->sh)->physhim, 0, 512, 0, 3); } else { } if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { mod_phy_reg(pi, 663, 4, 0); mod_phy_reg(pi, 667, 4, 0); } else { } } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } void wlc_phy_txpwr_index_nphy(struct brcms_phy *pi , u8 core_mask , s8 txpwrindex , bool restore_cals ) { u8 core ; u8 txpwrctl_tbl ; u16 tx_ind0 ; u16 iq_ind0 ; u16 lo_ind0 ; u16 m1m2 ; u32 txgain ; u16 rad_gain ; u16 dac_gain ; u8 bbmult ; u32 iqcomp ; u16 iqcomp_a ; u16 iqcomp_b ; u32 locomp ; u16 tmpval ; u8 tx_pwr_ctrl_state ; s32 rfpwr_offset ; u16 regval[2U] ; { if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } tx_ind0 = 192U; iq_ind0 = 320U; lo_ind0 = 448U; core = 0U; goto ldv_39937; ldv_39936: ; if ((((int )core_mask >> (int )core) & 1) == 0) { goto ldv_39935; } else { } txpwrctl_tbl = (unsigned int )core == 0U ? 26U : 27U; if ((int )txpwrindex < 0) { if ((int )pi->nphy_txpwrindex[(int )core].index < 0) { goto ldv_39935; } else { } if (pi->pubpi.phy_rev > 2U) { mod_phy_reg(pi, 143, 256, (int )pi->nphy_txpwrindex[(int )core].AfectrlOverride); mod_phy_reg(pi, 165, 256, (int )pi->nphy_txpwrindex[(int )core].AfectrlOverride); } else { mod_phy_reg(pi, 165, 16384, (int )pi->nphy_txpwrindex[(int )core].AfectrlOverride); } write_phy_reg(pi, (unsigned int )core == 0U ? 170 : 171, (int )pi->nphy_txpwrindex[(int )core].AfeCtrlDacGain); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )((int )core + 272), 16U, (void const *)(& pi->nphy_txpwrindex[(int )core].rad_gain)); wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& m1m2)); m1m2 = (u16 )(((unsigned int )core == 0U ? 255 : -256) & (int )((short )m1m2)); m1m2 = (u16 )(((unsigned int )core == 0U ? (short )((int )pi->nphy_txpwrindex[(int )core].bbmult << 8) : (short )pi->nphy_txpwrindex[(int )core].bbmult) | (int )((short )m1m2)); wlc_phy_table_write_nphy(pi, 15U, 1U, 87U, 16U, (void const *)(& m1m2)); if ((int )restore_cals) { wlc_phy_table_write_nphy(pi, 15U, 2U, (u32 )(((int )core + 40) * 2), 16U, (void const *)(& pi->nphy_txpwrindex[(int )core].iqcomp_a)); wlc_phy_table_write_nphy(pi, 15U, 1U, (u32 )((int )core + 85), 16U, (void const *)(& pi->nphy_txpwrindex[(int )core].locomp)); wlc_phy_table_write_nphy(pi, 15U, 1U, (u32 )((int )core + 93), 16U, (void const *)(& pi->nphy_txpwrindex[(int )core].locomp)); } else { } wlc_phy_txpwrctrl_enable_nphy(pi, (int )pi->nphy_txpwrctrl); pi->nphy_txpwrindex[(int )core].index_internal = pi->nphy_txpwrindex[(int )core].index_internal_save; } else { if ((int )pi->nphy_txpwrindex[(int )core].index < 0) { if (pi->pubpi.phy_rev > 2U) { mod_phy_reg(pi, 143, 256, (int )pi->nphy_txpwrindex[(int )core].AfectrlOverride); mod_phy_reg(pi, 165, 256, (int )pi->nphy_txpwrindex[(int )core].AfectrlOverride); } else { pi->nphy_txpwrindex[(int )core].AfectrlOverride = read_phy_reg(pi, 165); } pi->nphy_txpwrindex[(int )core].AfeCtrlDacGain = read_phy_reg(pi, (unsigned int )core == 0U ? 170 : 171); wlc_phy_table_read_nphy(pi, 7U, 1U, (u32 )((int )core + 272), 16U, (void *)(& pi->nphy_txpwrindex[(int )core].rad_gain)); wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& tmpval)); tmpval = (u16 )((int )tmpval >> ((unsigned int )core == 0U ? 8 : 0)); tmpval = (unsigned int )tmpval & 255U; pi->nphy_txpwrindex[(int )core].bbmult = (unsigned char )tmpval; wlc_phy_table_read_nphy(pi, 15U, 2U, (u32 )(((int )core + 40) * 2), 16U, (void *)(& pi->nphy_txpwrindex[(int )core].iqcomp_a)); wlc_phy_table_read_nphy(pi, 15U, 1U, (u32 )((int )core + 85), 16U, (void *)(& pi->nphy_txpwrindex[(int )core].locomp)); pi->nphy_txpwrindex[(int )core].index_internal_save = pi->nphy_txpwrindex[(int )core].index_internal; } else { } tx_pwr_ctrl_state = pi->nphy_txpwrctrl; wlc_phy_txpwrctrl_enable_nphy(pi, 0); if (pi->pubpi.phy_rev == 1U) { wlapi_bmac_phyclk_fgc((pi->sh)->physhim, 1); } else { } wlc_phy_table_read_nphy(pi, (u32 )txpwrctl_tbl, 1U, (u32 )((int )tx_ind0 + (int )txpwrindex), 32U, (void *)(& txgain)); if (pi->pubpi.phy_rev > 2U) { rad_gain = (u16 )(txgain >> 16); } else { rad_gain = (unsigned int )((u16 )(txgain >> 16)) & 8191U; } dac_gain = (unsigned int )((u16 )(txgain >> 8)) & 63U; bbmult = (u8 )txgain; if (pi->pubpi.phy_rev > 2U) { mod_phy_reg(pi, (unsigned int )core == 0U ? 143 : 165, 256, 256); } else { mod_phy_reg(pi, 165, 16384, 16384); } write_phy_reg(pi, (unsigned int )core == 0U ? 170 : 171, (int )dac_gain); wlc_phy_table_write_nphy(pi, 7U, 1U, (u32 )((int )core + 272), 16U, (void const *)(& rad_gain)); wlc_phy_table_read_nphy(pi, 15U, 1U, 87U, 16U, (void *)(& m1m2)); m1m2 = (u16 )(((unsigned int )core == 0U ? 255 : -256) & (int )((short )m1m2)); m1m2 = (u16 )(((unsigned int )core == 0U ? (short )((int )bbmult << 8) : (short )bbmult) | (int )((short )m1m2)); wlc_phy_table_write_nphy(pi, 15U, 1U, 87U, 16U, (void const *)(& m1m2)); wlc_phy_table_read_nphy(pi, (u32 )txpwrctl_tbl, 1U, (u32 )((int )iq_ind0 + (int )txpwrindex), 32U, (void *)(& iqcomp)); iqcomp_a = (unsigned int )((u16 )(iqcomp >> 10)) & 1023U; iqcomp_b = (unsigned int )((u16 )iqcomp) & 1023U; if ((int )restore_cals) { regval[0] = iqcomp_a; regval[1] = iqcomp_b; wlc_phy_table_write_nphy(pi, 15U, 2U, (u32 )(((int )core + 40) * 2), 16U, (void const *)(& regval)); } else { } wlc_phy_table_read_nphy(pi, (u32 )txpwrctl_tbl, 1U, (u32 )((int )lo_ind0 + (int )txpwrindex), 32U, (void *)(& locomp)); if ((int )restore_cals) { wlc_phy_table_write_nphy(pi, 15U, 1U, (u32 )((int )core + 85), 16U, (void const *)(& locomp)); } else { } if (pi->pubpi.phy_rev == 1U) { wlapi_bmac_phyclk_fgc((pi->sh)->physhim, 0); } else { } if (((int )pi->ipa2g_on && ((int )pi->radio_chanspec & 61440) == 8192) || ((int )pi->ipa5g_on && ((int )pi->radio_chanspec & 61440) == 4096)) { wlc_phy_table_read_nphy(pi, (unsigned int )core == 0U ? 26U : 27U, 1U, (u32 )((int )txpwrindex + 576), 32U, (void *)(& rfpwr_offset)); mod_phy_reg(pi, (unsigned int )core == 0U ? 663 : 667, 8176, (int )((u16 )rfpwr_offset) << 4U); mod_phy_reg(pi, (unsigned int )core == 0U ? 663 : 667, 4, 4); } else { } wlc_phy_txpwrctrl_enable_nphy(pi, (int )tx_pwr_ctrl_state); } pi->nphy_txpwrindex[(int )core].index = txpwrindex; ldv_39935: core = (u8 )((int )core + 1); ldv_39937: ; if ((int )pi->pubpi.phy_corenum > (int )core) { goto ldv_39936; } else { } if ((int )pi->phyhang_avoid) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } return; } } void wlc_phy_txpower_sromlimit_get_nphy(struct brcms_phy *pi , uint chan , u8 *max_pwr , u8 txp_rate_idx ) { u8 chan_freq_range ; { chan_freq_range = wlc_phy_get_chan_freq_range_nphy(pi, chan); switch ((int )chan_freq_range) { case 0: *max_pwr = pi->tx_srom_max_rate_2g[(int )txp_rate_idx]; goto ldv_39947; case 2: *max_pwr = pi->tx_srom_max_rate_5g_mid[(int )txp_rate_idx]; goto ldv_39947; case 1: *max_pwr = pi->tx_srom_max_rate_5g_low[(int )txp_rate_idx]; goto ldv_39947; case 3: *max_pwr = pi->tx_srom_max_rate_5g_hi[(int )txp_rate_idx]; goto ldv_39947; default: *max_pwr = pi->tx_srom_max_rate_2g[(int )txp_rate_idx]; goto ldv_39947; } ldv_39947: ; return; } } void wlc_phy_stay_in_carriersearch_nphy(struct brcms_phy *pi , bool enable ) { u16 clip_off[2U] ; { clip_off[0] = 65535U; clip_off[1] = 65535U; if ((int )enable) { if (pi->nphy_deaf_count == 0U) { pi->classifier_state = wlc_phy_classifier_nphy(pi, 0, 0); wlc_phy_classifier_nphy(pi, 7, 4); wlc_phy_clip_det_nphy(pi, 0, (u16 *)(& pi->clip_state)); wlc_phy_clip_det_nphy(pi, 1, (u16 *)(& clip_off)); } else { } pi->nphy_deaf_count = pi->nphy_deaf_count + 1U; wlc_phy_resetcca_nphy(pi); } else { pi->nphy_deaf_count = pi->nphy_deaf_count - 1U; if (pi->nphy_deaf_count == 0U) { wlc_phy_classifier_nphy(pi, 7, (int )pi->classifier_state); wlc_phy_clip_det_nphy(pi, 1, (u16 *)(& pi->clip_state)); } else { } } return; } } void wlc_nphy_deaf_mode(struct brcms_phy *pi , bool mode ) { { wlapi_suspend_mac_and_wait((pi->sh)->physhim); if ((int )mode) { if (pi->nphy_deaf_count == 0U) { wlc_phy_stay_in_carriersearch_nphy(pi, 1); } else { } } else if (pi->nphy_deaf_count != 0U) { wlc_phy_stay_in_carriersearch_nphy(pi, 0); } else { } wlapi_enable_mac((pi->sh)->physhim); return; } } bool ldv_queue_work_on_199(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_200(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_201(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_202(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_203(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_213(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_215(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_214(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_217(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_216(struct workqueue_struct *ldv_func_arg1 ) ; struct phytbl_info const dot11lcnphytbl_rx_gain_info_rev0[3U] ; unsigned int const dot11lcnphytbl_rx_gain_info_sz_rev0 ; struct lcnphy_tx_gain_tbl_entry const dot11lcnphy_5GHz_gaintable_rev0[128U] ; static u32 const dot11lcn_gain_tbl_rev0[96U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 4U, 0U, 4U, 8U, 1U, 5U, 9U, 13U, 77U, 141U, 13U, 77U, 141U, 205U, 79U, 143U, 207U, 211U, 275U, 1299U, 2323U, 2387U, 3411U, 4435U, 4499U, 20883U, 37267U, 53651U, 70035U, 0U, 0U, 0U, 0U, 0U, 0U, 4U, 0U, 4U, 8U, 1U, 5U, 9U, 13U, 77U, 141U, 13U, 77U, 141U, 205U, 79U, 143U, 207U, 211U, 275U, 1299U, 2323U, 2387U, 3411U, 4435U, 20819U, 37203U, 53587U, 69971U, 86355U, 102739U, 119123U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u16 const dot11lcn_aux_gain_idx_tbl_rev0[38U] = { 1025U, 1026U, 1027U, 1028U, 1029U, 1030U, 1031U, 1032U, 1033U, 1034U, 1419U, 1420U, 1421U, 1422U, 1423U, 144U, 145U, 146U, 403U, 404U, 405U, 406U, 407U, 408U, 409U, 410U, 411U, 412U, 413U, 414U, 415U, 416U, 417U, 418U, 419U, 420U, 421U, 0U}; static u32 const dot11lcn_gain_idx_tbl_rev0[148U] = { 0U, 0U, 268435456U, 0U, 536870912U, 0U, 805306368U, 0U, 1073741824U, 0U, 1342177280U, 0U, 1610612736U, 0U, 1879048192U, 0U, 2147483648U, 0U, 2415919104U, 8U, 2684354560U, 8U, 2952790016U, 8U, 3221225472U, 8U, 3489660928U, 8U, 3758096384U, 8U, 4026531840U, 8U, 0U, 9U, 268435456U, 9U, 536870912U, 25U, 805306368U, 25U, 1073741824U, 25U, 1342177280U, 25U, 1610612736U, 25U, 1879048192U, 25U, 2147483648U, 25U, 2415919104U, 25U, 2684354560U, 25U, 2952790016U, 25U, 3221225472U, 25U, 3489660928U, 25U, 3758096384U, 25U, 4026531840U, 25U, 0U, 26U, 268435456U, 26U, 536870912U, 26U, 805306368U, 26U, 1073741824U, 26U, 1342177280U, 2U, 1610612736U, 2U, 1879048192U, 2U, 2147483648U, 2U, 2415919104U, 2U, 2684354560U, 2U, 2952790016U, 2U, 3221225472U, 10U, 3489660928U, 10U, 3758096384U, 10U, 4026531840U, 10U, 0U, 11U, 268435456U, 11U, 536870912U, 11U, 805306368U, 11U, 1073741824U, 11U, 1342177280U, 27U, 1610612736U, 27U, 1879048192U, 27U, 2147483648U, 27U, 2415919104U, 27U, 2684354560U, 27U, 2952790016U, 27U, 3221225472U, 27U, 3489660928U, 27U, 3758096384U, 27U, 4026531840U, 27U, 0U, 28U, 268435456U, 28U, 536870912U, 28U, 805306368U, 28U, 1073741824U, 28U, 1342177280U, 28U, 1610612736U, 28U, 1879048192U, 28U, 2147483648U, 28U, 2415919104U, 28U}; static u16 const dot11lcn_aux_gain_idx_tbl_2G[38U] = { 0U, 0U, 0U, 0U, 1U, 128U, 129U, 256U, 257U, 384U, 385U, 386U, 387U, 388U, 389U, 390U, 391U, 392U, 645U, 649U, 650U, 651U, 652U, 653U, 654U, 655U, 656U, 657U, 658U, 659U, 660U, 661U, 662U, 663U, 664U, 665U, 666U, 0U}; static u8 const dot11lcn_gain_val_tbl_2G[68U] = { 252U, 2U, 8U, 14U, 19U, 27U, 252U, 2U, 8U, 14U, 19U, 27U, 252U, 0U, 12U, 3U, 235U, 254U, 7U, 11U, 15U, 251U, 254U, 1U, 5U, 8U, 11U, 14U, 17U, 20U, 23U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 21U, 24U, 27U, 0U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_gain_idx_tbl_2G[152U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 268435456U, 0U, 0U, 8U, 268435456U, 8U, 0U, 16U, 268435456U, 16U, 0U, 24U, 268435456U, 24U, 536870912U, 24U, 805306368U, 24U, 1073741824U, 24U, 1342177280U, 24U, 1610612736U, 24U, 1879048192U, 24U, 2147483648U, 24U, 1342177280U, 40U, 2415919104U, 40U, 2684354560U, 40U, 2952790016U, 40U, 3221225472U, 40U, 3489660928U, 40U, 3758096384U, 40U, 4026531840U, 40U, 0U, 41U, 268435456U, 41U, 536870912U, 41U, 805306368U, 41U, 1073741824U, 41U, 1342177280U, 41U, 1610612736U, 41U, 1879048192U, 41U, 2147483648U, 41U, 2415919104U, 41U, 2684354560U, 41U, 0U, 0U, 0U, 0U, 268435456U, 0U, 0U, 8U, 268435456U, 8U, 0U, 16U, 268435456U, 16U, 0U, 24U, 268435456U, 24U, 536870912U, 24U, 805306368U, 24U, 1073741824U, 24U, 1342177280U, 24U, 1610612736U, 24U, 1879048192U, 24U, 2147483648U, 24U, 1342177280U, 40U, 2415919104U, 40U, 2684354560U, 40U, 2952790016U, 40U, 3221225472U, 40U, 3489660928U, 40U, 3758096384U, 40U, 4026531840U, 40U, 0U, 41U, 268435456U, 41U, 536870912U, 41U, 805306368U, 41U, 1073741824U, 41U, 1342177280U, 41U, 1610612736U, 41U, 1879048192U, 41U, 2147483648U, 41U, 2415919104U, 41U, 2684354560U, 41U, 2952790016U, 41U, 3221225472U, 41U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_gain_tbl_2G[96U] = { 0U, 4U, 8U, 1U, 5U, 9U, 13U, 77U, 141U, 73U, 137U, 201U, 75U, 139U, 203U, 207U, 271U, 1295U, 2319U, 2383U, 3407U, 4431U, 4495U, 20879U, 37263U, 53647U, 70031U, 86415U, 102799U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_gain_tbl_extlna_2G[96U] = { 0U, 4U, 8U, 1U, 5U, 9U, 13U, 3U, 7U, 11U, 15U, 79U, 143U, 207U, 271U, 335U, 399U, 1423U, 2447U, 3471U, 32768U, 32772U, 32776U, 32769U, 32773U, 32777U, 32781U, 32771U, 32775U, 32779U, 32783U, 32847U, 32911U, 32975U, 33039U, 33103U, 33167U, 34191U, 35215U, 36239U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u16 const dot11lcn_aux_gain_idx_tbl_extlna_2G[38U] = { 1024U, 1024U, 1024U, 1024U, 1024U, 1024U, 1024U, 1024U, 1024U, 1025U, 1026U, 1027U, 1028U, 1155U, 1156U, 1157U, 1158U, 1411U, 1412U, 1413U, 1415U, 1416U, 1417U, 1418U, 1671U, 1672U, 1673U, 1674U, 1675U, 1676U, 1677U, 1678U, 1679U, 1680U, 1681U, 1682U, 1683U, 0U}; static u8 const dot11lcn_gain_val_tbl_extlna_2G[68U] = { 252U, 2U, 8U, 14U, 19U, 27U, 252U, 2U, 8U, 14U, 19U, 27U, 252U, 0U, 15U, 3U, 235U, 254U, 7U, 11U, 15U, 251U, 254U, 1U, 5U, 8U, 11U, 14U, 17U, 20U, 23U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 21U, 24U, 27U, 0U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_gain_idx_tbl_extlna_2G[152U] = { 0U, 64U, 0U, 64U, 0U, 64U, 0U, 64U, 0U, 64U, 0U, 64U, 0U, 64U, 0U, 64U, 0U, 64U, 268435456U, 64U, 536870912U, 64U, 805306368U, 64U, 1073741824U, 64U, 805306368U, 72U, 1073741824U, 72U, 1342177280U, 72U, 1610612736U, 72U, 805306368U, 88U, 1073741824U, 88U, 1342177280U, 88U, 1879048192U, 88U, 2147483648U, 88U, 2415919104U, 88U, 2684354560U, 88U, 1879048192U, 104U, 2147483648U, 104U, 2415919104U, 104U, 2684354560U, 104U, 2952790016U, 104U, 3221225472U, 104U, 3489660928U, 104U, 3758096384U, 104U, 4026531840U, 104U, 0U, 105U, 268435456U, 105U, 536870912U, 105U, 805306368U, 105U, 1073741824U, 65U, 1073741824U, 65U, 1073741824U, 65U, 1073741824U, 65U, 1073741824U, 65U, 1073741824U, 65U, 1073741824U, 65U, 1073741824U, 65U, 1073741824U, 65U, 1342177280U, 65U, 1610612736U, 65U, 1879048192U, 65U, 2147483648U, 65U, 1879048192U, 73U, 2147483648U, 73U, 2415919104U, 73U, 2684354560U, 73U, 1879048192U, 89U, 2147483648U, 89U, 2415919104U, 89U, 2952790016U, 89U, 3221225472U, 89U, 3489660928U, 89U, 3758096384U, 89U, 2952790016U, 105U, 3221225472U, 105U, 3489660928U, 105U, 3758096384U, 105U, 4026531840U, 105U, 0U, 106U, 268435456U, 106U, 536870912U, 106U, 805306368U, 106U, 1073741824U, 106U, 1342177280U, 106U, 1610612736U, 106U, 1879048192U, 106U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_aux_gain_idx_tbl_5G[38U] = { 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 131U, 132U, 133U, 134U, 135U, 390U, 391U, 392U, 393U, 394U, 395U, 396U, 397U, 398U, 399U, 400U, 401U, 402U, 403U, 404U, 405U, 406U, 407U, 408U, 409U, 410U, 411U, 412U, 413U, 0U}; static u32 const dot11lcn_gain_val_tbl_5G[68U] = { 247U, 253U, 0U, 4U, 4U, 4U, 247U, 253U, 0U, 4U, 4U, 4U, 246U, 0U, 12U, 3U, 235U, 254U, 6U, 10U, 16U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 21U, 24U, 27U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 21U, 24U, 27U, 0U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_gain_idx_tbl_5G[152U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 268435456U, 0U, 536870912U, 0U, 805306368U, 0U, 1073741824U, 0U, 805306368U, 8U, 1073741824U, 8U, 1342177280U, 8U, 1610612736U, 8U, 1879048192U, 8U, 1610612736U, 24U, 1879048192U, 24U, 2147483648U, 24U, 2415919104U, 24U, 2684354560U, 24U, 2952790016U, 24U, 3221225472U, 24U, 3489660928U, 24U, 3758096384U, 24U, 4026531840U, 24U, 0U, 25U, 268435456U, 25U, 536870912U, 25U, 805306368U, 25U, 1073741824U, 25U, 1342177280U, 25U, 1610612736U, 25U, 1879048192U, 25U, 2147483648U, 25U, 2415919104U, 25U, 2684354560U, 25U, 2952790016U, 25U, 3221225472U, 25U, 3489660928U, 25U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_gain_tbl_5G[96U] = { 0U, 64U, 128U, 1U, 5U, 9U, 13U, 17U, 21U, 85U, 149U, 23U, 27U, 91U, 155U, 219U, 283U, 347U, 411U, 1435U, 2459U, 3483U, 4507U, 20891U, 37275U, 53659U, 70043U, 86427U, 102811U, 119195U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; struct phytbl_info const dot11lcnphytbl_rx_gain_info_rev0[3U] = { {(void const *)(& dot11lcn_gain_tbl_rev0), 96U, 18U, 0U, 32U}, {(void const *)(& dot11lcn_aux_gain_idx_tbl_rev0), 38U, 14U, 0U, 16U}, {(void const *)(& dot11lcn_gain_idx_tbl_rev0), 148U, 13U, 0U, 32U}}; struct phytbl_info const dot11lcnphytbl_rx_gain_info_2G_rev2[4U] = { {(void const *)(& dot11lcn_gain_tbl_2G), 96U, 18U, 0U, 32U}, {(void const *)(& dot11lcn_aux_gain_idx_tbl_2G), 38U, 14U, 0U, 16U}, {(void const *)(& dot11lcn_gain_idx_tbl_2G), 152U, 13U, 0U, 32U}, {(void const *)(& dot11lcn_gain_val_tbl_2G), 68U, 17U, 0U, 8U}}; struct phytbl_info const dot11lcnphytbl_rx_gain_info_5G_rev2[4U] = { {(void const *)(& dot11lcn_gain_tbl_5G), 96U, 18U, 0U, 32U}, {(void const *)(& dot11lcn_aux_gain_idx_tbl_5G), 38U, 14U, 0U, 16U}, {(void const *)(& dot11lcn_gain_idx_tbl_5G), 152U, 13U, 0U, 32U}, {(void const *)(& dot11lcn_gain_val_tbl_5G), 68U, 17U, 0U, 8U}}; struct phytbl_info const dot11lcnphytbl_rx_gain_info_extlna_2G_rev2[4U] = { {(void const *)(& dot11lcn_gain_tbl_extlna_2G), 96U, 18U, 0U, 32U}, {(void const *)(& dot11lcn_aux_gain_idx_tbl_extlna_2G), 38U, 14U, 0U, 16U}, {(void const *)(& dot11lcn_gain_idx_tbl_extlna_2G), 152U, 13U, 0U, 32U}, {(void const *)(& dot11lcn_gain_val_tbl_extlna_2G), 68U, 17U, 0U, 8U}}; struct phytbl_info const dot11lcnphytbl_rx_gain_info_extlna_5G_rev2[4U] = { {(void const *)(& dot11lcn_gain_tbl_5G), 96U, 18U, 0U, 32U}, {(void const *)(& dot11lcn_aux_gain_idx_tbl_5G), 38U, 14U, 0U, 16U}, {(void const *)(& dot11lcn_gain_idx_tbl_5G), 152U, 13U, 0U, 32U}, {(void const *)(& dot11lcn_gain_val_tbl_5G), 68U, 17U, 0U, 8U}}; unsigned int const dot11lcnphytbl_rx_gain_info_sz_rev0 = 3U; unsigned int const dot11lcnphytbl_rx_gain_info_2G_rev2_sz = 4U; unsigned int const dot11lcnphytbl_rx_gain_info_5G_rev2_sz = 4U; static u16 const dot11lcn_min_sig_sq_tbl_rev0[64U] = { 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U, 333U}; static u16 const dot11lcn_noise_scale_tbl_rev0[64U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_fltr_ctrl_tbl_rev0[10U] = { 82424U, 8696U, 8699U, 16891U, 130635U, 8571U, 8499U, 16619U, 130723U, 587U}; static u32 const dot11lcn_ps_ctrl_tbl_rev0[20U] = { 1048577U, 2097168U, 3145729U, 4194320U, 5242914U, 6291746U, 7340578U, 8389410U, 9438242U, 10487074U, 11535906U, 12584738U, 13633570U, 15730978U, 1051170U, 2100002U, 3148834U, 4197666U, 5246498U, 6295330U}; static u16 const dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo[64U] = { 7U, 5U, 6U, 4U, 7U, 5U, 6U, 4U, 7U, 5U, 6U, 4U, 7U, 5U, 6U, 4U, 11U, 11U, 10U, 10U, 11U, 11U, 10U, 10U, 11U, 11U, 10U, 10U, 11U, 11U, 10U, 10U, 7U, 5U, 6U, 4U, 7U, 5U, 6U, 4U, 7U, 5U, 6U, 4U, 7U, 5U, 6U, 4U, 11U, 11U, 10U, 10U, 11U, 11U, 10U, 10U, 11U, 11U, 10U, 10U, 11U, 11U, 10U, 10U}; static u16 const dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0[64U] = { 7U, 5U, 2U, 0U, 7U, 5U, 2U, 0U, 7U, 5U, 2U, 0U, 7U, 5U, 2U, 0U, 7U, 7U, 2U, 2U, 7U, 7U, 2U, 2U, 7U, 7U, 2U, 2U, 7U, 7U, 2U, 2U, 7U, 5U, 2U, 0U, 7U, 5U, 2U, 0U, 7U, 5U, 2U, 0U, 7U, 5U, 2U, 0U, 7U, 7U, 2U, 2U, 7U, 7U, 2U, 2U, 7U, 7U, 2U, 2U, 7U, 7U, 2U, 2U}; static u16 const dot11lcn_sw_ctrl_tbl_4313_epa_rev0[64U] = { 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U, 2U, 8U, 4U, 1U}; static u16 const dot11lcn_sw_ctrl_tbl_4313_rev0[64U] = { 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U, 10U, 9U, 6U, 5U}; static u16 const dot11lcn_sw_ctrl_tbl_4313_ipa_rev0_combo[64U] = { 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U, 5U, 6U, 9U, 10U}; static u16 const dot11lcn_sw_ctrl_tbl_rev0[64U] = { 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U, 4U, 4U, 2U, 2U}; static u8 const dot11lcn_nf_table_rev0[16U] = { 95U, 54U, 41U, 31U, 95U, 54U, 41U, 31U, 95U, 54U, 41U, 31U, 95U, 54U, 41U, 31U}; static u8 const dot11lcn_gain_val_tbl_rev0[60U] = { 9U, 15U, 20U, 24U, 254U, 7U, 11U, 15U, 251U, 254U, 1U, 5U, 8U, 11U, 14U, 17U, 20U, 23U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 6U, 9U, 12U, 15U, 18U, 21U, 24U, 27U, 0U, 0U, 0U, 0U, 0U, 0U, 3U, 235U, 0U, 0U}; static u8 const dot11lcn_spur_tbl_rev0[128U] = { 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 2U, 3U, 1U, 3U, 2U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 2U, 3U, 1U, 3U, 2U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U, 1U}; static u16 const dot11lcn_unsup_mcs_tbl_rev0[154U] = { 26U, 52U, 78U, 104U, 156U, 208U, 234U, 260U, 52U, 104U, 156U, 208U, 312U, 416U, 468U, 520U, 78U, 156U, 234U, 312U, 468U, 624U, 702U, 780U, 104U, 208U, 312U, 416U, 624U, 832U, 936U, 1040U, 24U, 156U, 208U, 260U, 234U, 312U, 390U, 208U, 260U, 260U, 312U, 364U, 364U, 416U, 312U, 390U, 390U, 468U, 546U, 546U, 624U, 260U, 312U, 364U, 312U, 364U, 416U, 468U, 416U, 468U, 520U, 520U, 572U, 390U, 468U, 546U, 468U, 546U, 624U, 702U, 624U, 702U, 780U, 780U, 858U, 54U, 108U, 162U, 216U, 324U, 432U, 486U, 540U, 108U, 216U, 324U, 432U, 648U, 864U, 972U, 1080U, 162U, 324U, 486U, 648U, 972U, 1296U, 1458U, 1620U, 216U, 432U, 648U, 864U, 1296U, 1728U, 1944U, 2160U, 24U, 324U, 432U, 540U, 486U, 648U, 810U, 432U, 540U, 540U, 648U, 756U, 756U, 864U, 648U, 810U, 810U, 972U, 1134U, 1134U, 1296U, 540U, 648U, 756U, 648U, 756U, 864U, 972U, 864U, 972U, 1080U, 1080U, 1188U, 810U, 972U, 1134U, 972U, 1134U, 1296U, 1458U, 1296U, 1458U, 1620U, 1620U, 1782U}; static u16 const dot11lcn_iq_local_tbl_rev0[108U] = { 512U, 768U, 1024U, 1536U, 2048U, 2816U, 4096U, 4097U, 4098U, 4099U, 4100U, 4101U, 4102U, 4103U, 5895U, 8199U, 11527U, 16391U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 512U, 768U, 1024U, 1536U, 2048U, 2816U, 4096U, 4097U, 4098U, 4099U, 4100U, 4101U, 4102U, 4103U, 5895U, 8199U, 11527U, 16391U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 16384U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const dot11lcn_papd_compdelta_tbl_rev0[160U] = { 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U, 524288U}; struct phytbl_info const dot11lcnphytbl_info_rev0[14U] = { {(void const *)(& dot11lcn_min_sig_sq_tbl_rev0), 64U, 2U, 0U, 16U}, {(void const *)(& dot11lcn_noise_scale_tbl_rev0), 64U, 1U, 0U, 16U}, {(void const *)(& dot11lcn_fltr_ctrl_tbl_rev0), 10U, 11U, 0U, 32U}, {(void const *)(& dot11lcn_ps_ctrl_tbl_rev0), 20U, 12U, 0U, 32U}, {(void const *)(& dot11lcn_gain_idx_tbl_rev0), 148U, 13U, 0U, 32U}, {(void const *)(& dot11lcn_aux_gain_idx_tbl_rev0), 38U, 14U, 0U, 16U}, {(void const *)(& dot11lcn_sw_ctrl_tbl_rev0), 64U, 15U, 0U, 16U}, {(void const *)(& dot11lcn_nf_table_rev0), 16U, 16U, 0U, 8U}, {(void const *)(& dot11lcn_gain_val_tbl_rev0), 60U, 17U, 0U, 8U}, {(void const *)(& dot11lcn_gain_tbl_rev0), 96U, 18U, 0U, 32U}, {(void const *)(& dot11lcn_spur_tbl_rev0), 128U, 20U, 0U, 8U}, {(void const *)(& dot11lcn_unsup_mcs_tbl_rev0), 154U, 23U, 0U, 16U}, {(void const *)(& dot11lcn_iq_local_tbl_rev0), 108U, 0U, 0U, 16U}, {(void const *)(& dot11lcn_papd_compdelta_tbl_rev0), 160U, 24U, 0U, 32U}}; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313 = {(void const *)(& dot11lcn_sw_ctrl_tbl_4313_rev0), 64U, 15U, 0U, 16U}; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313_bt_ipa = {(void const *)(& dot11lcn_sw_ctrl_tbl_4313_ipa_rev0_combo), 64U, 15U, 0U, 16U}; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313_epa = {(void const *)(& dot11lcn_sw_ctrl_tbl_4313_epa_rev0), 64U, 15U, 0U, 16U}; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313_bt_epa = {(void const *)(& dot11lcn_sw_ctrl_tbl_4313_epa_rev0_combo), 64U, 15U, 0U, 16U}; struct phytbl_info const dot11lcn_sw_ctrl_tbl_info_4313_bt_epa_p250 = {(void const *)(& dot11lcn_sw_ctrl_tbl_4313_bt_epa_p250_rev0), 64U, 15U, 0U, 16U}; unsigned int const dot11lcnphytbl_info_sz_rev0 = 14U; struct lcnphy_tx_gain_tbl_entry const dot11lcnphy_2GHz_extPA_gaintable_rev0[128U] = { {3U, 0U, 31U, 0U, 72U}, {3U, 0U, 31U, 0U, 70U}, {3U, 0U, 31U, 0U, 68U}, {3U, 0U, 30U, 0U, 67U}, {3U, 0U, 29U, 0U, 68U}, {3U, 0U, 28U, 0U, 68U}, {3U, 0U, 27U, 0U, 69U}, {3U, 0U, 26U, 0U, 70U}, {3U, 0U, 25U, 0U, 70U}, {3U, 0U, 24U, 0U, 71U}, {3U, 0U, 23U, 0U, 72U}, {3U, 0U, 23U, 0U, 70U}, {3U, 0U, 22U, 0U, 71U}, {3U, 0U, 21U, 0U, 72U}, {3U, 0U, 21U, 0U, 70U}, {3U, 0U, 21U, 0U, 68U}, {3U, 0U, 21U, 0U, 66U}, {3U, 0U, 21U, 0U, 64U}, {3U, 0U, 21U, 0U, 63U}, {3U, 0U, 20U, 0U, 64U}, {3U, 0U, 19U, 0U, 65U}, {3U, 0U, 19U, 0U, 64U}, {3U, 0U, 18U, 0U, 65U}, {3U, 0U, 18U, 0U, 64U}, {3U, 0U, 17U, 0U, 65U}, {3U, 0U, 17U, 0U, 64U}, {3U, 0U, 16U, 0U, 65U}, {3U, 0U, 16U, 0U, 64U}, {3U, 0U, 16U, 0U, 62U}, {3U, 0U, 16U, 0U, 60U}, {3U, 0U, 16U, 0U, 58U}, {3U, 0U, 15U, 0U, 61U}, {3U, 0U, 15U, 0U, 59U}, {3U, 0U, 14U, 0U, 61U}, {3U, 0U, 14U, 0U, 60U}, {3U, 0U, 14U, 0U, 58U}, {3U, 0U, 13U, 0U, 60U}, {3U, 0U, 13U, 0U, 59U}, {3U, 0U, 12U, 0U, 62U}, {3U, 0U, 12U, 0U, 60U}, {3U, 0U, 12U, 0U, 58U}, {3U, 0U, 11U, 0U, 62U}, {3U, 0U, 11U, 0U, 60U}, {3U, 0U, 11U, 0U, 59U}, {3U, 0U, 11U, 0U, 57U}, {3U, 0U, 10U, 0U, 61U}, {3U, 0U, 10U, 0U, 59U}, {3U, 0U, 10U, 0U, 57U}, {3U, 0U, 9U, 0U, 62U}, {3U, 0U, 9U, 0U, 60U}, {3U, 0U, 9U, 0U, 58U}, {3U, 0U, 9U, 0U, 57U}, {3U, 0U, 8U, 0U, 62U}, {3U, 0U, 8U, 0U, 60U}, {3U, 0U, 8U, 0U, 58U}, {3U, 0U, 8U, 0U, 57U}, {3U, 0U, 8U, 0U, 55U}, {3U, 0U, 7U, 0U, 61U}, {3U, 0U, 7U, 0U, 60U}, {3U, 0U, 7U, 0U, 58U}, {3U, 0U, 7U, 0U, 56U}, {3U, 0U, 7U, 0U, 55U}, {3U, 0U, 6U, 0U, 62U}, {3U, 0U, 6U, 0U, 60U}, {3U, 0U, 6U, 0U, 58U}, {3U, 0U, 6U, 0U, 57U}, {3U, 0U, 6U, 0U, 55U}, {3U, 0U, 6U, 0U, 54U}, {3U, 0U, 6U, 0U, 52U}, {3U, 0U, 5U, 0U, 61U}, {3U, 0U, 5U, 0U, 59U}, {3U, 0U, 5U, 0U, 57U}, {3U, 0U, 5U, 0U, 56U}, {3U, 0U, 5U, 0U, 54U}, {3U, 0U, 5U, 0U, 53U}, {3U, 0U, 5U, 0U, 51U}, {3U, 0U, 4U, 0U, 62U}, {3U, 0U, 4U, 0U, 60U}, {3U, 0U, 4U, 0U, 58U}, {3U, 0U, 4U, 0U, 57U}, {3U, 0U, 4U, 0U, 55U}, {3U, 0U, 4U, 0U, 54U}, {3U, 0U, 4U, 0U, 52U}, {3U, 0U, 4U, 0U, 51U}, {3U, 0U, 4U, 0U, 49U}, {3U, 0U, 4U, 0U, 48U}, {3U, 0U, 4U, 0U, 46U}, {3U, 0U, 3U, 0U, 60U}, {3U, 0U, 3U, 0U, 58U}, {3U, 0U, 3U, 0U, 57U}, {3U, 0U, 3U, 0U, 55U}, {3U, 0U, 3U, 0U, 54U}, {3U, 0U, 3U, 0U, 52U}, {3U, 0U, 3U, 0U, 51U}, {3U, 0U, 3U, 0U, 49U}, {3U, 0U, 3U, 0U, 48U}, {3U, 0U, 3U, 0U, 46U}, {3U, 0U, 3U, 0U, 45U}, {3U, 0U, 3U, 0U, 44U}, {3U, 0U, 3U, 0U, 43U}, {3U, 0U, 3U, 0U, 41U}, {3U, 0U, 2U, 0U, 61U}, {3U, 0U, 2U, 0U, 59U}, {3U, 0U, 2U, 0U, 57U}, {3U, 0U, 2U, 0U, 56U}, {3U, 0U, 2U, 0U, 54U}, {3U, 0U, 2U, 0U, 53U}, {3U, 0U, 2U, 0U, 51U}, {3U, 0U, 2U, 0U, 50U}, {3U, 0U, 2U, 0U, 48U}, {3U, 0U, 2U, 0U, 47U}, {3U, 0U, 2U, 0U, 46U}, {3U, 0U, 2U, 0U, 44U}, {3U, 0U, 2U, 0U, 43U}, {3U, 0U, 2U, 0U, 42U}, {3U, 0U, 2U, 0U, 41U}, {3U, 0U, 2U, 0U, 39U}, {3U, 0U, 2U, 0U, 38U}, {3U, 0U, 2U, 0U, 37U}, {3U, 0U, 2U, 0U, 36U}, {3U, 0U, 2U, 0U, 35U}, {3U, 0U, 2U, 0U, 34U}, {3U, 0U, 2U, 0U, 33U}, {3U, 0U, 2U, 0U, 32U}, {3U, 0U, 1U, 0U, 63U}, {3U, 0U, 1U, 0U, 61U}, {3U, 0U, 1U, 0U, 59U}, {3U, 0U, 1U, 0U, 57U}}; struct lcnphy_tx_gain_tbl_entry const dot11lcnphy_2GHz_gaintable_rev0[128U] = { {15U, 0U, 31U, 0U, 72U}, {15U, 0U, 31U, 0U, 70U}, {15U, 0U, 31U, 0U, 68U}, {15U, 0U, 30U, 0U, 68U}, {15U, 0U, 29U, 0U, 69U}, {15U, 0U, 28U, 0U, 69U}, {15U, 0U, 27U, 0U, 70U}, {15U, 0U, 26U, 0U, 70U}, {15U, 0U, 25U, 0U, 71U}, {15U, 0U, 24U, 0U, 72U}, {15U, 0U, 23U, 0U, 73U}, {15U, 0U, 23U, 0U, 71U}, {15U, 0U, 22U, 0U, 72U}, {15U, 0U, 21U, 0U, 73U}, {15U, 0U, 21U, 0U, 71U}, {15U, 0U, 21U, 0U, 69U}, {15U, 0U, 21U, 0U, 67U}, {15U, 0U, 21U, 0U, 65U}, {15U, 0U, 21U, 0U, 63U}, {15U, 0U, 20U, 0U, 65U}, {15U, 0U, 19U, 0U, 66U}, {15U, 0U, 19U, 0U, 64U}, {15U, 0U, 18U, 0U, 66U}, {15U, 0U, 18U, 0U, 64U}, {15U, 0U, 17U, 0U, 66U}, {15U, 0U, 17U, 0U, 64U}, {15U, 0U, 16U, 0U, 66U}, {15U, 0U, 16U, 0U, 64U}, {15U, 0U, 16U, 0U, 62U}, {15U, 0U, 16U, 0U, 61U}, {15U, 0U, 16U, 0U, 59U}, {15U, 0U, 15U, 0U, 61U}, {15U, 0U, 15U, 0U, 59U}, {15U, 0U, 14U, 0U, 62U}, {15U, 0U, 14U, 0U, 60U}, {15U, 0U, 14U, 0U, 58U}, {15U, 0U, 13U, 0U, 61U}, {15U, 0U, 13U, 0U, 59U}, {15U, 0U, 12U, 0U, 62U}, {15U, 0U, 12U, 0U, 61U}, {15U, 0U, 12U, 0U, 59U}, {15U, 0U, 11U, 0U, 62U}, {15U, 0U, 11U, 0U, 61U}, {15U, 0U, 11U, 0U, 59U}, {15U, 0U, 11U, 0U, 57U}, {15U, 0U, 10U, 0U, 61U}, {15U, 0U, 10U, 0U, 59U}, {15U, 0U, 10U, 0U, 58U}, {15U, 0U, 9U, 0U, 62U}, {15U, 0U, 9U, 0U, 61U}, {15U, 0U, 9U, 0U, 59U}, {15U, 0U, 9U, 0U, 57U}, {15U, 0U, 8U, 0U, 62U}, {15U, 0U, 8U, 0U, 61U}, {15U, 0U, 8U, 0U, 59U}, {15U, 0U, 8U, 0U, 57U}, {15U, 0U, 8U, 0U, 56U}, {15U, 0U, 8U, 0U, 54U}, {15U, 0U, 8U, 0U, 53U}, {15U, 0U, 8U, 0U, 51U}, {15U, 0U, 8U, 0U, 50U}, {7U, 0U, 7U, 0U, 69U}, {7U, 0U, 7U, 0U, 67U}, {7U, 0U, 7U, 0U, 65U}, {7U, 0U, 7U, 0U, 64U}, {7U, 0U, 7U, 0U, 62U}, {7U, 0U, 7U, 0U, 60U}, {7U, 0U, 7U, 0U, 58U}, {7U, 0U, 7U, 0U, 57U}, {7U, 0U, 7U, 0U, 55U}, {7U, 0U, 6U, 0U, 62U}, {7U, 0U, 6U, 0U, 61U}, {7U, 0U, 6U, 0U, 59U}, {7U, 0U, 6U, 0U, 57U}, {7U, 0U, 6U, 0U, 56U}, {7U, 0U, 6U, 0U, 54U}, {7U, 0U, 6U, 0U, 53U}, {7U, 0U, 5U, 0U, 61U}, {7U, 0U, 5U, 0U, 60U}, {7U, 0U, 5U, 0U, 58U}, {7U, 0U, 5U, 0U, 56U}, {7U, 0U, 5U, 0U, 55U}, {7U, 0U, 5U, 0U, 53U}, {7U, 0U, 5U, 0U, 52U}, {7U, 0U, 5U, 0U, 50U}, {7U, 0U, 5U, 0U, 49U}, {7U, 0U, 5U, 0U, 47U}, {7U, 0U, 4U, 0U, 57U}, {7U, 0U, 4U, 0U, 56U}, {7U, 0U, 4U, 0U, 54U}, {7U, 0U, 4U, 0U, 53U}, {7U, 0U, 4U, 0U, 51U}, {7U, 0U, 4U, 0U, 50U}, {7U, 0U, 4U, 0U, 48U}, {7U, 0U, 4U, 0U, 47U}, {7U, 0U, 4U, 0U, 46U}, {7U, 0U, 4U, 0U, 44U}, {7U, 0U, 4U, 0U, 43U}, {7U, 0U, 4U, 0U, 42U}, {7U, 0U, 4U, 0U, 41U}, {7U, 0U, 4U, 0U, 40U}, {7U, 0U, 3U, 0U, 51U}, {7U, 0U, 3U, 0U, 50U}, {7U, 0U, 3U, 0U, 48U}, {7U, 0U, 3U, 0U, 47U}, {7U, 0U, 3U, 0U, 46U}, {7U, 0U, 3U, 0U, 44U}, {7U, 0U, 3U, 0U, 43U}, {7U, 0U, 3U, 0U, 42U}, {7U, 0U, 3U, 0U, 41U}, {3U, 0U, 3U, 0U, 56U}, {3U, 0U, 3U, 0U, 54U}, {3U, 0U, 3U, 0U, 53U}, {3U, 0U, 3U, 0U, 51U}, {3U, 0U, 3U, 0U, 50U}, {3U, 0U, 3U, 0U, 48U}, {3U, 0U, 3U, 0U, 47U}, {3U, 0U, 3U, 0U, 46U}, {3U, 0U, 3U, 0U, 44U}, {3U, 0U, 3U, 0U, 43U}, {3U, 0U, 3U, 0U, 42U}, {3U, 0U, 3U, 0U, 41U}, {3U, 0U, 3U, 0U, 39U}, {3U, 0U, 3U, 0U, 38U}, {3U, 0U, 3U, 0U, 37U}, {3U, 0U, 3U, 0U, 36U}, {3U, 0U, 3U, 0U, 35U}, {3U, 0U, 3U, 0U, 34U}}; struct lcnphy_tx_gain_tbl_entry const dot11lcnphy_5GHz_gaintable_rev0[128U] = { {255U, 255U, 240U, 0U, 152U}, {255U, 255U, 240U, 0U, 147U}, {255U, 255U, 240U, 0U, 143U}, {255U, 255U, 240U, 0U, 139U}, {255U, 255U, 240U, 0U, 135U}, {255U, 255U, 240U, 0U, 131U}, {255U, 255U, 240U, 0U, 128U}, {255U, 255U, 240U, 0U, 124U}, {255U, 255U, 240U, 0U, 121U}, {255U, 255U, 240U, 0U, 117U}, {255U, 255U, 240U, 0U, 114U}, {255U, 255U, 240U, 0U, 111U}, {255U, 255U, 240U, 0U, 107U}, {255U, 255U, 240U, 0U, 104U}, {255U, 255U, 240U, 0U, 101U}, {255U, 255U, 240U, 0U, 99U}, {255U, 255U, 240U, 0U, 96U}, {255U, 255U, 240U, 0U, 93U}, {255U, 255U, 240U, 0U, 90U}, {255U, 255U, 240U, 0U, 88U}, {255U, 255U, 240U, 0U, 85U}, {255U, 255U, 240U, 0U, 83U}, {255U, 255U, 240U, 0U, 81U}, {255U, 255U, 240U, 0U, 78U}, {255U, 255U, 240U, 0U, 76U}, {255U, 255U, 240U, 0U, 74U}, {255U, 255U, 240U, 0U, 72U}, {255U, 255U, 240U, 0U, 70U}, {255U, 255U, 240U, 0U, 68U}, {255U, 255U, 240U, 0U, 66U}, {255U, 255U, 240U, 0U, 64U}, {255U, 248U, 240U, 0U, 64U}, {255U, 241U, 240U, 0U, 64U}, {255U, 251U, 224U, 0U, 64U}, {255U, 244U, 224U, 0U, 64U}, {255U, 254U, 208U, 0U, 64U}, {255U, 246U, 208U, 0U, 64U}, {255U, 239U, 208U, 0U, 64U}, {255U, 249U, 192U, 0U, 64U}, {255U, 242U, 192U, 0U, 64U}, {255U, 255U, 176U, 0U, 64U}, {255U, 248U, 176U, 0U, 64U}, {255U, 241U, 176U, 0U, 64U}, {255U, 254U, 160U, 0U, 64U}, {255U, 246U, 160U, 0U, 64U}, {255U, 239U, 160U, 0U, 64U}, {255U, 255U, 144U, 0U, 64U}, {255U, 248U, 144U, 0U, 64U}, {255U, 241U, 144U, 0U, 64U}, {255U, 234U, 144U, 0U, 64U}, {255U, 255U, 128U, 0U, 64U}, {255U, 248U, 128U, 0U, 64U}, {255U, 241U, 128U, 0U, 64U}, {255U, 234U, 128U, 0U, 64U}, {255U, 255U, 112U, 0U, 64U}, {255U, 248U, 112U, 0U, 64U}, {255U, 241U, 112U, 0U, 64U}, {255U, 234U, 112U, 0U, 64U}, {255U, 227U, 112U, 0U, 64U}, {255U, 221U, 112U, 0U, 64U}, {255U, 215U, 112U, 0U, 64U}, {255U, 208U, 112U, 0U, 64U}, {255U, 203U, 112U, 0U, 64U}, {255U, 197U, 112U, 0U, 64U}, {255U, 255U, 96U, 0U, 64U}, {255U, 248U, 96U, 0U, 64U}, {255U, 241U, 96U, 0U, 64U}, {255U, 234U, 96U, 0U, 64U}, {255U, 227U, 96U, 0U, 64U}, {255U, 221U, 96U, 0U, 64U}, {255U, 255U, 80U, 0U, 64U}, {255U, 248U, 80U, 0U, 64U}, {255U, 241U, 80U, 0U, 64U}, {255U, 234U, 80U, 0U, 64U}, {255U, 227U, 80U, 0U, 64U}, {255U, 221U, 80U, 0U, 64U}, {255U, 215U, 80U, 0U, 64U}, {255U, 208U, 80U, 0U, 64U}, {255U, 255U, 64U, 0U, 64U}, {255U, 248U, 64U, 0U, 64U}, {255U, 241U, 64U, 0U, 64U}, {255U, 234U, 64U, 0U, 64U}, {255U, 227U, 64U, 0U, 64U}, {255U, 221U, 64U, 0U, 64U}, {255U, 215U, 64U, 0U, 64U}, {255U, 208U, 64U, 0U, 64U}, {255U, 203U, 64U, 0U, 64U}, {255U, 197U, 64U, 0U, 64U}, {255U, 255U, 48U, 0U, 64U}, {255U, 248U, 48U, 0U, 64U}, {255U, 241U, 48U, 0U, 64U}, {255U, 234U, 48U, 0U, 64U}, {255U, 227U, 48U, 0U, 64U}, {255U, 221U, 48U, 0U, 64U}, {255U, 215U, 48U, 0U, 64U}, {255U, 208U, 48U, 0U, 64U}, {255U, 203U, 48U, 0U, 64U}, {255U, 197U, 48U, 0U, 64U}, {255U, 191U, 48U, 0U, 64U}, {255U, 186U, 48U, 0U, 64U}, {255U, 181U, 48U, 0U, 64U}, {255U, 175U, 48U, 0U, 64U}, {255U, 255U, 32U, 0U, 64U}, {255U, 248U, 32U, 0U, 64U}, {255U, 241U, 32U, 0U, 64U}, {255U, 234U, 32U, 0U, 64U}, {255U, 227U, 32U, 0U, 64U}, {255U, 221U, 32U, 0U, 64U}, {255U, 215U, 32U, 0U, 64U}, {255U, 208U, 32U, 0U, 64U}, {255U, 203U, 32U, 0U, 64U}, {255U, 197U, 32U, 0U, 64U}, {255U, 191U, 32U, 0U, 64U}, {255U, 186U, 32U, 0U, 64U}, {255U, 181U, 32U, 0U, 64U}, {255U, 175U, 32U, 0U, 64U}, {255U, 170U, 32U, 0U, 64U}, {255U, 166U, 32U, 0U, 64U}, {255U, 161U, 32U, 0U, 64U}, {255U, 156U, 32U, 0U, 64U}, {255U, 152U, 32U, 0U, 64U}, {255U, 148U, 32U, 0U, 64U}, {255U, 143U, 32U, 0U, 64U}, {255U, 139U, 32U, 0U, 64U}, {255U, 135U, 32U, 0U, 64U}, {255U, 132U, 32U, 0U, 64U}, {255U, 255U, 16U, 0U, 64U}, {255U, 248U, 16U, 0U, 64U}}; bool ldv_queue_work_on_213(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_214(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_215(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_216(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_217(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_227(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_229(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_228(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_231(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_230(struct workqueue_struct *ldv_func_arg1 ) ; unsigned int const mimophytbl_info_sz_rev3_volatile1 ; unsigned int const mimophytbl_info_sz_rev3_volatile2 ; unsigned int const mimophytbl_info_sz_rev3_volatile3 ; static u32 const frame_struct_rev0[832U] = { 134236676U, 1048576U, 16779781U, 1048608U, 159401222U, 1048624U, 159401223U, 1048624U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 134236684U, 1048580U, 16779789U, 1048612U, 159401230U, 1048628U, 159401231U, 1048628U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2564U, 1048576U, 285248005U, 1048608U, 427869446U, 1048624U, 562103558U, 1048624U, 562103558U, 1048624U, 25167108U, 1048624U, 293635333U, 1048624U, 696337671U, 17825840U, 2564U, 1048576U, 285248005U, 1048608U, 562103558U, 1048624U, 562103558U, 1048624U, 696337671U, 17825840U, 0U, 0U, 0U, 0U, 0U, 0U, 2572U, 1048584U, 285248013U, 1048616U, 427869454U, 1048632U, 562103566U, 1048632U, 562103566U, 1048632U, 25167116U, 1048632U, 293635341U, 1048632U, 696337679U, 17825848U, 2572U, 1048584U, 285248013U, 1048616U, 562103566U, 1048632U, 562103566U, 1048632U, 696337679U, 17825848U, 0U, 0U, 0U, 0U, 0U, 0U, 134236676U, 1048576U, 16779781U, 1048608U, 427869446U, 1048624U, 427869446U, 1048624U, 293635332U, 1048624U, 964807173U, 1048624U, 696337671U, 17825840U, 0U, 0U, 268470788U, 1048576U, 964807173U, 1048624U, 427869446U, 1048624U, 696337671U, 17825840U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 134236684U, 1048584U, 16779789U, 1048616U, 427869454U, 1048632U, 427869454U, 1048632U, 293635340U, 1048632U, 964807181U, 1048632U, 696337679U, 17825848U, 0U, 0U, 268470796U, 1048584U, 964807181U, 1048632U, 427869454U, 1048632U, 696337679U, 17825848U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878020U, 1048576U, 33559557U, 1048640U, 184568326U, 26214496U, 318802438U, 26214496U, 318802438U, 26214496U, 1124207108U, 1048672U, 453036549U, 1048672U, 587270663U, 22020192U, 1073878020U, 1048576U, 436261893U, 1048640U, 318802438U, 26214496U, 318802438U, 26214496U, 587270663U, 22020192U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048592U, 33559565U, 1048656U, 184568334U, 26214512U, 318802446U, 26214512U, 318802446U, 26214512U, 1124207116U, 1048688U, 453036557U, 1048688U, 587270671U, 22020208U, 1073878028U, 1048592U, 436261901U, 1048656U, 318802446U, 26214512U, 318802446U, 26214512U, 587270671U, 22020208U, 0U, 0U, 0U, 0U, 0U, 0U, 1342346244U, 1048576U, 838964229U, 1048640U, 184568326U, 26214496U, 184568326U, 26214496U, 1526909444U, 1048672U, 989975557U, 1048672U, 587270663U, 22020192U, 0U, 0U, 1476580356U, 1048576U, 989975557U, 1048672U, 184568326U, 26214496U, 587270663U, 22020192U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1342346252U, 1048592U, 838964237U, 1048656U, 184568334U, 26214512U, 184568334U, 26214512U, 1526909452U, 1048688U, 989975565U, 1048688U, 587270671U, 22020208U, 0U, 0U, 1476580364U, 1048592U, 989975565U, 1048688U, 184568334U, 26214512U, 587270671U, 22020208U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878020U, 1001472U, 1644368901U, 1048640U, 1392675334U, 26214496U, 1392675335U, 26214496U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1001480U, 1644368909U, 1048648U, 1392675342U, 26214504U, 1392675343U, 26214504U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2572U, 1048580U, 285248013U, 1048612U, 427869454U, 1048628U, 562103566U, 1048628U, 562103566U, 1048628U, 25167116U, 1048632U, 293635341U, 1048632U, 293700877U, 1048632U, 696337679U, 17825848U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2572U, 1048584U, 285248013U, 1048616U, 562103566U, 1048632U, 562103566U, 1048632U, 293700877U, 1048632U, 696337679U, 17825848U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 134236676U, 1048576U, 16779781U, 1048608U, 25216262U, 1048624U, 25216262U, 1048624U, 562087180U, 1048624U, 1233259021U, 1483056U, 1099057677U, 1483056U, 696337679U, 17825840U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 536922636U, 1048576U, 1233259021U, 1483056U, 427869454U, 1048624U, 1099057677U, 1483056U, 696337679U, 17825840U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048584U, 33559565U, 1048648U, 184568334U, 26214504U, 318802446U, 26214504U, 318802446U, 26214504U, 1124207116U, 1048688U, 453036557U, 1048688U, 453069325U, 1048688U, 587270671U, 22020208U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048592U, 436261901U, 1048656U, 318802446U, 26214512U, 318802446U, 26214512U, 453069325U, 1048688U, 587270671U, 22020208U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1342346244U, 1048576U, 838964229U, 1048640U, 50350598U, 26214496U, 50350598U, 26214496U, 1795361292U, 1048672U, 1258427405U, 1483104U, 1124226061U, 1483104U, 587270671U, 22020192U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1795363852U, 1048672U, 1258427405U, 1483104U, 184568334U, 26214496U, 1124226061U, 1483104U, 587270671U, 22020192U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878020U, 1048576U, 436261893U, 1048640U, 1392675334U, 26214496U, 1526909446U, 26214496U, 1526909446U, 26214496U, 1124207108U, 1048672U, 453036549U, 1048672U, 1392675335U, 26263648U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048592U, 436261901U, 1048656U, 1392675342U, 26214512U, 1526909454U, 26214512U, 1526909454U, 26214512U, 1124207116U, 1048688U, 453036557U, 1048688U, 1392675343U, 26263664U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878020U, 1048576U, 436261893U, 1048640U, 1526909446U, 26214496U, 1526909446U, 26214496U, 1392675335U, 26263648U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048592U, 436261901U, 1048656U, 1526909454U, 26214512U, 1526909454U, 26214512U, 1392675343U, 26263664U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u8 const frame_lut_rev0[32U] = { 2U, 4U, 20U, 20U, 3U, 5U, 22U, 22U, 10U, 12U, 28U, 28U, 11U, 13U, 30U, 30U, 6U, 8U, 24U, 24U, 7U, 9U, 26U, 26U, 14U, 16U, 32U, 40U, 15U, 17U, 34U, 42U}; static u32 const tmap_tbl_rev0[448U] = { 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 4044427536U, 286331153U, 301011217U, 273U, 285212672U, 286388497U, 286331153U, 286331377U, 2324212352U, 2326440586U, 2324335272U, 698504U, 2290614272U, 2324334762U, 2326300808U, 2290657448U, 2702250256U, 286331153U, 297865489U, 273U, 285212672U, 286368017U, 286331153U, 286331297U, 2720145952U, 572662306U, 583148066U, 546U, 570425344U, 572695074U, 572662306U, 572662434U, 4044427536U, 286331153U, 301011217U, 69905U, 286326784U, 286388497U, 286331153U, 286331377U, 2829748384U, 2827520168U, 2829625482U, 559786U, 2863267840U, 2829625992U, 2827659946U, 2863303306U, 2863180448U, 2326432426U, 2861206154U, 699016U, 2326396928U, 2863179912U, 2326301322U, 2324211848U, 134744576U, 168298506U, 134875656U, 526344U, 134873088U, 134875144U, 134875144U, 168430088U, 2694881440U, 2158010496U, 2155913376U, 32896U, 2157969408U, 2158002336U, 2692784288U, 2155913376U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2576977920U, 2610665915U, 2612631961U, 2576988601U, 2610543504U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 11184264U, 570425344U, 572699170U, 572662306U, 572662450U, 2988581408U, 572662306U, 584196642U, 546U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 855638016U, 859026227U, 858993459U, 858993587U, 3006477104U, 858993459U, 869479219U, 819U, 570425344U, 572695074U, 572662306U, 572662434U, 2720145952U, 572662306U, 583148066U, 546U, 2579077888U, 2610665915U, 2612631961U, 2576988601U, 2610543513U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 145401992U, 572662272U, 572715554U, 572662306U, 572662514U, 572662306U, 572662306U, 586293794U, 546U, 285212672U, 286388497U, 286331153U, 286331153U, 4044427537U, 286331153U, 301011217U, 17895697U, 3147544832U, 3115957145U, 3113991099U, 3149634459U, 3116079547U, 3113851321U, 3115956635U, 3003U, 2852126720U, 2829625992U, 2827659946U, 2863303306U, 2829748394U, 2827520168U, 2829625482U, 176720554U, 2852126720U, 2829625992U, 2827659946U, 2863303306U, 2829748384U, 2827520168U, 2829625482U, 2730U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 3149642496U, 2577120187U, 2612632475U, 3115956667U, 3115948987U, 3115956667U, 3116080025U, 2457U, 2315255808U, 2861082760U, 2827520170U, 2827651720U, 2827659402U, 2292755114U, 2829748906U, 143173770U, 185273088U, 151718667U, 185142027U, 151587083U, 151587595U, 151587595U, 151587593U, 2313U, 167772160U, 168298504U, 134875146U, 134875656U, 134875146U, 134744074U, 168430088U, 134744074U, 2964369408U, 2425401520U, 2427490448U, 2964369552U, 2964361392U, 2427498672U, 2964361360U, 144U, 2147483648U, 2692784256U, 2692776096U, 2692776064U, 2692784256U, 2158010528U, 2694873248U, 10526880U, 570425344U, 572715554U, 572662306U, 572662514U, 4062323232U, 572662306U, 586293794U, 546U, 285212672U, 286388497U, 286331153U, 286331377U, 4044427536U, 286331153U, 301011217U, 273U, 855638016U, 859042611U, 858993459U, 858993651U, 4080218928U, 858993459U, 871576371U, 819U, 570425344U, 572715554U, 572662306U, 572662514U, 4062323232U, 572662306U, 586293794U, 546U, 2566914048U, 2610665915U, 2612631961U, 2576988601U, 2610543504U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2290647040U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 11184264U, 2292746752U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 145401992U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const tdtrn_tbl_rev0[704U] = { 102499868U, 5303912U, 4120051254U, 4266791670U, 3128U, 4266791670U, 4120051254U, 5303912U, 102499868U, 3999793232U, 4265014674U, 318176850U, 204996608U, 318176850U, 4265014674U, 3999793232U, 102499868U, 5303912U, 4120051254U, 4266791670U, 3128U, 4266791670U, 4120051254U, 5303912U, 102499868U, 3999793232U, 4265014674U, 318176850U, 204996608U, 318176850U, 4265014674U, 3999793232U, 98764259U, 5107468U, 4126408263U, 4267774534U, 3015U, 4267774534U, 4126408263U, 5107468U, 98764259U, 4010541133U, 4266128883U, 306642529U, 197591040U, 306642529U, 4266128883U, 4010541133U, 98764259U, 5107468U, 4126408263U, 4267774534U, 3015U, 4267774534U, 4126408263U, 5107468U, 98764259U, 4010541133U, 4266128883U, 306642529U, 197591040U, 306642529U, 4266128883U, 4010541133U, 4200135256U, 4170515515U, 4283173312U, 4224122792U, 4219794308U, 127465209U, 91619618U, 92539382U, 189792256U, 95941954U, 143000626U, 115212007U, 4219794308U, 4191749732U, 4159177308U, 16775101U, 94897576U, 4156358911U, 39647208U, 107280857U, 4085578628U, 4276553437U, 70387846U, 4114744759U, 2896U, 167118212U, 19006838U, 4143515544U, 4085578628U, 4289264582U, 163643212U, 71039125U, 47448788U, 131990128U, 4237690780U, 4178247316U, 4261478188U, 47449693U, 153747606U, 1375160U, 4247584044U, 124451644U, 9893714U, 4187094407U, 4213965312U, 4273535328U, 148962454U, 77071016U, 4247584044U, 44565656U, 4237691104U, 4183883448U, 33618732U, 4253546897U, 4149346454U, 4215015274U, 4247584044U, 4223139860U, 9832746U, 106758868U, 4281138688U, 4271175946U, 127728790U, 40896478U, 47448788U, 40896478U, 127728790U, 4271175946U, 4281138688U, 106758868U, 9832746U, 4223139860U, 4247584044U, 4215015274U, 4149346454U, 4253546897U, 33618732U, 4183883448U, 4237691104U, 44565656U, 4247584044U, 77071016U, 148962454U, 4273535328U, 4213965312U, 4187094407U, 9893714U, 124451644U, 4247584044U, 1375160U, 153747606U, 47449693U, 4261478188U, 4178247316U, 4237690780U, 131990128U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 103415808U, 4277798745U, 146278664U, 4086758445U, 4191552604U, 4233033224U, 4148753814U, 129107903U, 103417386U, 4165924929U, 4148753814U, 61999608U, 4191552604U, 208274387U, 146278664U, 17234087U, 103415808U, 4277860519U, 146339576U, 4086694867U, 4191615908U, 4232972792U, 4148693610U, 129169473U, 103479766U, 4165863359U, 4148693610U, 62060040U, 4191615908U, 208337965U, 146339576U, 17172313U, 103415808U, 4277798745U, 146278664U, 4086758445U, 4191552604U, 4233033224U, 4148753814U, 129107903U, 103417386U, 4165924929U, 4148753814U, 61999608U, 4191552604U, 208274387U, 146278664U, 17234087U, 103415808U, 4277860519U, 146339576U, 4086694867U, 4191615908U, 4232972792U, 4148693610U, 129169473U, 103479766U, 4165863359U, 4148693610U, 62060040U, 4191615908U, 208337965U, 146339576U, 17172313U, 102499868U, 4281335965U, 4289859905U, 4253547348U, 4133355097U, 49215902U, 23523388U, 4294445494U, 2212U, 717867U, 15725943U, 4202957810U, 4228054865U, 136712039U, 4293919599U, 138607043U, 0U, 104724414U, 4237361168U, 4036622298U, 11469822U, 4094559612U, 176815889U, 198574070U, 4150001664U, 4132044808U, 264568474U, 107150610U, 27724195U, 78381689U, 4005494862U, 4284678352U, 4192532964U, 13696867U, 5172927U, 41485484U, 161677735U, 4245816930U, 4271509444U, 587338U, 63324U, 4294314965U, 4279306889U, 92075022U, 66977967U, 4158320793U, 1113233U, 4156425789U, 0U, 4190308418U, 57671664U, 258410534U, 4283563010U, 200473220U, 4118216943U, 4096458762U, 144965632U, 162988024U, 4030464358U, 4187882222U, 4267308637U, 4216651143U, 289537970U, 10354480U, 98762752U, 4278585093U, 139724960U, 4096130137U, 4196205610U, 4235785850U, 4155307534U, 123340646U, 98764259U, 4171692186U, 4155307534U, 59246982U, 4196205610U, 198902695U, 139724960U, 16447739U, 98762752U, 4278647035U, 139786080U, 4096066471U, 4196269014U, 4235725190U, 4155247090U, 123402394U, 98826781U, 4171630438U, 4155247090U, 59307642U, 4196269014U, 198966361U, 139786080U, 16385797U, 98762752U, 4278585093U, 139724960U, 4096130137U, 4196205610U, 4235785850U, 4155307534U, 123340646U, 98764259U, 4171692186U, 4155307534U, 59246982U, 4196205610U, 198902695U, 139724960U, 16447739U, 98762752U, 4278647035U, 139786080U, 4096066471U, 4196269014U, 4235725190U, 4155247090U, 123402394U, 98826781U, 4171630438U, 4155247090U, 59307642U, 4196269014U, 198966361U, 139786080U, 16385797U, 4200135256U, 4176543232U, 71829309U, 4257873478U, 4187030104U, 144507911U, 4250728218U, 45088224U, 138282134U, 4284090176U, 4286250391U, 16646641U, 591918U, 4204068725U, 4274911466U, 4289787539U, 4247583320U, 70516502U, 4221830621U, 4200661825U, 111544011U, 3800365U, 108526231U, 33162720U, 4170580030U, 123340427U, 19725374U, 4196661645U, 4236049731U, 4287691789U, 29428098U, 12976598U, 4247584044U, 30802118U, 159515073U, 4228775824U, 4249091196U, 4186831395U, 4231921964U, 109774682U, 4126870U, 98566650U, 4204201591U, 4247584825U, 113968806U, 54655585U, 98433956U, 4279632947U, 4200135980U, 4136894384U, 4176150221U, 4285921940U, 137232393U, 32571646U, 4254596986U, 121700186U, 76941374U, 4259316399U, 4145741148U, 67569821U, 39385489U, 4266065353U, 121439304U, 4261476592U, 4247584044U, 4242539776U, 4228513244U, 4268228951U, 80151921U, 4231724833U, 4241949224U, 91030135U, 33619456U, 2292007U, 4265345835U, 4232380220U, 65666011U, 72811283U, 80346972U, 852920U, 4200071168U, 4226351314U, 4191223307U, 19267065U, 69534143U, 53017131U, 4289266416U, 4196729175U, 33619456U, 57934904U, 4278453757U, 51183186U, 3668793U, 4285072581U, 83426595U, 4247911451U, 4247584044U, 4229692721U, 4246930680U, 80084841U, 4214816823U, 4266787596U, 100531972U, 70779764U, 4261413376U, 22542885U, 49348521U, 4197122856U, 29295653U, 4260954405U, 4262197712U, 13827049U, 64088U, 62390285U, 4284220617U, 51577943U, 4225434601U, 4282186820U, 53214780U, 4180082722U, 4261413376U, 41354605U, 36240599U, 4280417338U, 91292871U, 22543976U, 4259118089U, 83950816U, 4247584044U, 83950816U, 4259118089U, 22543976U, 91292871U, 4280417338U, 36240599U, 41354605U, 4261413376U, 4180082722U, 53214780U, 4282186820U, 4225434601U, 51577943U, 4284220617U, 62390285U, 64088U, 13827049U, 4262197712U, 4260954405U, 29295653U, 4197122856U, 49348521U, 22542885U, 4261413376U, 70779764U, 100531972U, 4266787596U, 4214816823U, 80084841U, 4246930680U, 4229692721U, 4247584044U, 4247911451U, 83426595U, 4285072581U, 3668793U, 51183186U, 4278453757U, 57934904U, 33619456U, 4196729175U, 4289266416U, 53017131U, 69534143U, 19267065U, 4191223307U, 4226351314U, 4200071168U, 852920U, 80346972U, 72811283U, 65666011U, 4232380220U, 4265345835U, 2292007U, 33619456U, 91030135U, 4241949224U, 4231724833U, 80151921U, 4268228951U, 4228513244U, 4242539776U, 94896128U, 4279240382U, 134219850U, 4103928958U, 4200072192U, 4238145242U, 4160812658U, 118490908U, 94897576U, 4176541924U, 4160812658U, 56887590U, 4200072192U, 191103874U, 134219850U, 15792450U, 94896128U, 4279302466U, 134281142U, 4103865218U, 4200135680U, 4238084390U, 4160752014U, 118552804U, 94960216U, 4176480028U, 4160752014U, 56948442U, 4200135680U, 191167614U, 134281142U, 15730366U, 94896128U, 4279240382U, 134219850U, 4103928958U, 4200072192U, 4238145242U, 4160812658U, 118490908U, 94897576U, 4176541924U, 4160812658U, 56887590U, 4200072192U, 191103874U, 134219850U, 15792450U, 94896128U, 4279302466U, 134281142U, 4103865218U, 4200135680U, 4238084390U, 4160752014U, 118552804U, 94960216U, 4176480028U, 4160752014U, 56948442U, 4200135680U, 191167614U, 134281142U, 15730366U}; static u32 const intlv_tbl_rev0[7U] = { 8396912U, 108075149U, 174070060U, 170921542U, 12654733U, 134227154U, 112U}; static u16 const pilot_tbl_rev0[88U] = { 65288U, 65288U, 65288U, 65288U, 65288U, 65288U, 65288U, 65288U, 32981U, 32981U, 32981U, 32981U, 32981U, 32981U, 32981U, 32981U, 65290U, 65410U, 65440U, 65320U, 65535U, 65535U, 65535U, 65535U, 65410U, 65440U, 65320U, 65290U, 65535U, 65535U, 65535U, 65535U, 63551U, 64031U, 64151U, 64181U, 62141U, 61631U, 65535U, 65535U, 61463U, 63509U, 61973U, 61589U, 61493U, 61469U, 65535U, 65535U, 65288U, 65282U, 65408U, 65312U, 65288U, 65282U, 65408U, 65312U, 61471U, 63511U, 64021U, 62101U, 61621U, 61501U, 65535U, 65535U, 63530U, 64010U, 64130U, 64160U, 62120U, 61610U, 65535U, 65535U, 61442U, 63488U, 61952U, 61568U, 61472U, 61448U, 65535U, 65535U, 61450U, 63490U, 64000U, 62080U, 61600U, 61480U, 65535U, 65535U}; static u32 const pltlut_tbl_rev0[6U] = { 1985216803U, 1648390993U, 1985229313U, 1985217043U, 1985216803U, 1984103713U}; static u32 const tdi_tbl20_ant0_rev0[55U] = { 594470U, 660521U, 743085U, 809136U, 875187U, 957622U, 1023674U, 49469U, 131841U, 197892U, 263944U, 329995U, 412558U, 610961U, 677012U, 759576U, 825639U, 891690U, 974126U, 1040177U, 65972U, 148407U, 214459U, 280510U, 362882U, 429061U, 627465U, 693516U, 776079U, 842130U, 908182U, 990617U, 24488U, 82476U, 164911U, 230962U, 297013U, 379448U, 445628U, 644031U, 726531U, 792582U, 858634U, 924685U, 1007120U, 32915U, 98967U, 181402U, 247424U, 313472U, 396032U, 462080U, 0U, 0U, 0U}; static u32 const tdi_tbl20_ant1_rev0[55U] = { 84774U, 167209U, 234413U, 300592U, 383027U, 449078U, 629818U, 695869U, 770177U, 836228U, 902280U, 984715U, 18574U, 101265U, 184852U, 250904U, 317095U, 399530U, 465582U, 646321U, 728756U, 786743U, 852795U, 918846U, 1001218U, 35077U, 134153U, 201356U, 267407U, 333586U, 416022U, 596761U, 662824U, 745260U, 803247U, 869298U, 951733U, 1017784U, 51644U, 150719U, 217859U, 283910U, 366474U, 432525U, 613264U, 679315U, 761751U, 819738U, 885760U, 968192U, 1034240U, 68096U, 0U, 0U, 0U}; static u32 const tdi_tbl40_ant0_rev0[110U] = { 1155910U, 1273039U, 1373657U, 1458658U, 1559403U, 1660021U, 1778563U, 1879308U, 1996310U, 33311U, 134056U, 251058U, 353351U, 470480U, 571098U, 656099U, 756844U, 857590U, 1172612U, 1289741U, 1390359U, 1475360U, 1576105U, 1676851U, 1795400U, 1896145U, 2013147U, 50148U, 150893U, 268023U, 370053U, 487183U, 587800U, 672801U, 773547U, 890676U, 1189449U, 1306578U, 1407196U, 1492197U, 1592942U, 1710072U, 1812102U, 1912848U, 2029977U, 66850U, 167596U, 284725U, 386890U, 504019U, 604765U, 689638U, 790383U, 907513U, 1206151U, 1323281U, 1424026U, 1508899U, 1609645U, 1726774U, 1828939U, 1946068U, 2046814U, 83687U, 200816U, 301562U, 403592U, 520722U, 621467U, 706468U, 807086U, 924215U, 1222988U, 1340117U, 1440863U, 1525864U, 1626481U, 1743611U, 1845641U, 1962771U, 2063516U, 100517U, 217519U, 318264U, 436813U, 537559U, 638304U, 723305U, 823923U, 941052U, 1256074U, 1356820U, 1457565U, 1542566U, 1643184U, 1760313U, 1862606U, 1979608U, 2080353U, 117354U, 234356U, 335101U, 453643U, 554261U, 655006U, 740007U, 840625U, 957754U, 0U, 0U}; static u32 const tdi_tbl40_ant1_rev0[110U] = { 2022198U, 76234U, 176979U, 294109U, 379110U, 496111U, 596985U, 698887U, 799633U, 916762U, 1181987U, 1298989U, 1399863U, 1501899U, 1602644U, 1719774U, 1804775U, 1905392U, 2039034U, 93064U, 210066U, 310811U, 395812U, 512814U, 613688U, 715852U, 816469U, 933599U, 1198824U, 1315825U, 1418107U, 1518729U, 1619347U, 1720732U, 1821477U, 1938479U, 2057145U, 109901U, 226903U, 311904U, 429033U, 529651U, 631932U, 732554U, 833172U, 934557U, 1215526U, 1332656U, 1434810U, 1535566U, 1636184U, 1737569U, 1838314U, 1955444U, 2073981U, 126603U, 243605U, 328606U, 445735U, 546481U, 648646U, 749391U, 850009U, 951394U, 1248747U, 1349493U, 1451523U, 1552268U, 1652886U, 1754271U, 1855016U, 1972146U, 42695U, 143440U, 260570U, 345443U, 462572U, 563318U, 665348U, 766093U, 866839U, 1148320U, 1265449U, 1366195U, 1468360U, 1569105U, 1669851U, 1771108U, 1871853U, 1988983U, 59397U, 160143U, 277272U, 362145U, 479275U, 580020U, 682185U, 782930U, 900060U, 1165285U, 1282286U, 1383032U, 1485062U, 1585808U, 1686553U, 1787938U, 1888556U, 2005685U, 0U, 0U}; static u16 const bdi_tbl_rev0[6U] = { 112U, 294U, 300U, 582U, 1165U, 1234U}; static u32 const chanest_tbl_rev0[96U] = { 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U}; static u8 const mcs_tbl_rev0[128U] = { 0U, 8U, 10U, 16U, 18U, 25U, 26U, 28U, 64U, 72U, 74U, 80U, 82U, 89U, 90U, 92U, 128U, 136U, 138U, 144U, 146U, 153U, 154U, 156U, 192U, 200U, 202U, 208U, 210U, 217U, 218U, 220U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 4U, 8U, 9U, 10U, 12U, 16U, 17U, 18U, 20U, 24U, 25U, 26U, 28U, 32U, 33U, 34U, 36U, 64U, 65U, 66U, 68U, 72U, 73U, 74U, 76U, 80U, 81U, 82U, 84U, 88U, 89U, 90U, 92U, 96U, 97U, 98U, 100U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const noise_var_tbl0_rev0[256U] = { 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U}; static u32 const noise_var_tbl1_rev0[256U] = { 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U}; static u8 const est_pwr_lut_core0_rev0[64U] = { 80U, 79U, 78U, 77U, 76U, 75U, 74U, 73U, 72U, 71U, 70U, 69U, 68U, 67U, 66U, 65U, 64U, 63U, 62U, 61U, 60U, 59U, 58U, 57U, 56U, 55U, 54U, 53U, 52U, 51U, 50U, 49U, 48U, 47U, 46U, 45U, 44U, 43U, 42U, 41U, 40U, 39U, 38U, 37U, 36U, 35U, 34U, 33U, 32U, 31U, 30U, 29U, 28U, 27U, 26U, 25U, 24U, 23U, 22U, 21U, 20U, 19U, 18U, 17U}; static u8 const est_pwr_lut_core1_rev0[64U] = { 80U, 79U, 78U, 77U, 76U, 75U, 74U, 73U, 72U, 71U, 70U, 69U, 68U, 67U, 66U, 65U, 64U, 63U, 62U, 61U, 60U, 59U, 58U, 57U, 56U, 55U, 54U, 53U, 52U, 51U, 50U, 49U, 48U, 47U, 46U, 45U, 44U, 43U, 42U, 41U, 40U, 39U, 38U, 37U, 36U, 35U, 34U, 33U, 32U, 31U, 30U, 29U, 28U, 27U, 26U, 25U, 24U, 23U, 22U, 21U, 20U, 19U, 18U, 17U}; static u8 const adj_pwr_lut_core0_rev0[128U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u8 const adj_pwr_lut_core1_rev0[128U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const gainctrl_lut_core0_rev0[128U] = { 63712068U, 63712066U, 63712064U, 63712062U, 63712061U, 63712059U, 63449924U, 63449922U, 63449920U, 63449918U, 63449917U, 63449915U, 63449913U, 63449912U, 63449910U, 63449908U, 63187780U, 63187778U, 63187776U, 63187774U, 63187773U, 63187771U, 63187769U, 63187768U, 63187766U, 63187764U, 63187763U, 63187762U, 63187760U, 63187759U, 63187757U, 62925636U, 62925634U, 62925632U, 62925630U, 62925629U, 62925627U, 62925625U, 62925624U, 62925622U, 62925620U, 61877060U, 61877058U, 61877056U, 61877054U, 61877053U, 61877051U, 61877049U, 61877048U, 61877046U, 61877044U, 61877043U, 61877042U, 61877040U, 61877039U, 61877037U, 60828484U, 60828482U, 60828480U, 60828478U, 60828477U, 60828475U, 60828473U, 60828472U, 60828470U, 60828468U, 59779908U, 59779906U, 59779904U, 59779902U, 59779901U, 59779899U, 59779897U, 59779896U, 59779894U, 59779892U, 59779891U, 59779890U, 59779888U, 58731332U, 58731330U, 58731328U, 58731326U, 58731325U, 58731323U, 58731321U, 58731320U, 58731318U, 58731316U, 58731315U, 58731314U, 58731312U, 58731311U, 58731309U, 58731308U, 58731307U, 58731306U, 58731305U, 58731303U, 58731302U, 58731301U, 58731300U, 58731299U, 58731298U, 58731297U, 58731296U, 58731295U, 58731294U, 58731294U, 58731293U, 58731292U, 58731291U, 58731290U, 58731290U, 58731289U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 11008U}; static u32 const gainctrl_lut_core1_rev0[128U] = { 63712068U, 63712066U, 63712064U, 63712062U, 63712061U, 63712059U, 63449924U, 63449922U, 63449920U, 63449918U, 63449917U, 63449915U, 63449913U, 63449912U, 63449910U, 63449908U, 63187780U, 63187778U, 63187776U, 63187774U, 63187773U, 63187771U, 63187769U, 63187768U, 63187766U, 63187764U, 63187763U, 63187762U, 63187760U, 63187759U, 63187757U, 62925636U, 62925634U, 62925632U, 62925630U, 62925629U, 62925627U, 62925625U, 62925624U, 62925622U, 62925620U, 61877060U, 61877058U, 61877056U, 61877054U, 61877053U, 61877051U, 61877049U, 61877048U, 61877046U, 61877044U, 61877043U, 61877042U, 61877040U, 61877039U, 61877037U, 60828484U, 60828482U, 60828480U, 60828478U, 60828477U, 60828475U, 60828473U, 60828472U, 60828470U, 60828468U, 59779908U, 59779906U, 59779904U, 59779902U, 59779901U, 59779899U, 59779897U, 59779896U, 59779894U, 59779892U, 59779891U, 59779890U, 59779888U, 58731332U, 58731330U, 58731328U, 58731326U, 58731325U, 58731323U, 58731321U, 58731320U, 58731318U, 58731316U, 58731315U, 58731314U, 58731312U, 58731311U, 58731309U, 58731308U, 58731307U, 58731306U, 58731305U, 58731303U, 58731302U, 58731301U, 58731300U, 58731299U, 58731298U, 58731297U, 58731296U, 58731295U, 58731294U, 58731294U, 58731293U, 58731292U, 58731291U, 58731290U, 58731290U, 58731289U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 58731288U, 11008U}; static u32 const iq_lut_core0_rev0[128U] = { 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U}; static u32 const iq_lut_core1_rev0[128U] = { 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U, 127U}; static u16 const loft_lut_core0_rev0[128U] = { 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U}; static u16 const loft_lut_core1_rev0[128U] = { 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U, 0U, 257U, 2U, 259U}; struct phytbl_info const mimophytbl_info_rev0_volatile[12U] = { {(void const *)(& bdi_tbl_rev0), 6U, 21U, 0U, 16U}, {(void const *)(& pltlut_tbl_rev0), 6U, 20U, 0U, 32U}, {(void const *)(& gainctrl_lut_core0_rev0), 128U, 26U, 192U, 32U}, {(void const *)(& gainctrl_lut_core1_rev0), 128U, 27U, 192U, 32U}, {(void const *)(& est_pwr_lut_core0_rev0), 64U, 26U, 0U, 8U}, {(void const *)(& est_pwr_lut_core1_rev0), 64U, 27U, 0U, 8U}, {(void const *)(& adj_pwr_lut_core0_rev0), 128U, 26U, 64U, 8U}, {(void const *)(& adj_pwr_lut_core1_rev0), 128U, 27U, 64U, 8U}, {(void const *)(& iq_lut_core0_rev0), 128U, 26U, 320U, 32U}, {(void const *)(& iq_lut_core1_rev0), 128U, 27U, 320U, 32U}, {(void const *)(& loft_lut_core0_rev0), 128U, 26U, 448U, 16U}, {(void const *)(& loft_lut_core1_rev0), 128U, 27U, 448U, 16U}}; struct phytbl_info const mimophytbl_info_rev0[14U] = { {(void const *)(& frame_struct_rev0), 832U, 10U, 0U, 32U}, {(void const *)(& frame_lut_rev0), 32U, 24U, 0U, 8U}, {(void const *)(& tmap_tbl_rev0), 448U, 12U, 0U, 32U}, {(void const *)(& tdtrn_tbl_rev0), 704U, 14U, 0U, 32U}, {(void const *)(& intlv_tbl_rev0), 7U, 13U, 0U, 32U}, {(void const *)(& pilot_tbl_rev0), 88U, 11U, 0U, 16U}, {(void const *)(& tdi_tbl20_ant0_rev0), 55U, 19U, 128U, 32U}, {(void const *)(& tdi_tbl20_ant1_rev0), 55U, 19U, 256U, 32U}, {(void const *)(& tdi_tbl40_ant0_rev0), 110U, 19U, 640U, 32U}, {(void const *)(& tdi_tbl40_ant1_rev0), 110U, 19U, 768U, 32U}, {(void const *)(& chanest_tbl_rev0), 96U, 22U, 0U, 32U}, {(void const *)(& mcs_tbl_rev0), 128U, 18U, 0U, 8U}, {(void const *)(& noise_var_tbl0_rev0), 256U, 16U, 0U, 32U}, {(void const *)(& noise_var_tbl1_rev0), 256U, 16U, 128U, 32U}}; unsigned int const mimophytbl_info_sz_rev0 = 14U; unsigned int const mimophytbl_info_sz_rev0_volatile = 12U; static u16 const ant_swctrl_tbl_rev3[32U] = { 130U, 130U, 529U, 546U, 808U, 0U, 0U, 0U, 324U, 0U, 0U, 0U, 392U, 0U, 0U, 0U, 130U, 130U, 529U, 546U, 808U, 0U, 0U, 0U, 324U, 0U, 0U, 0U, 392U, 0U, 0U, 0U}; static u16 const ant_swctrl_tbl_rev3_1[32U] = { 34U, 34U, 17U, 34U, 34U, 0U, 0U, 0U, 17U, 0U, 0U, 0U, 34U, 0U, 0U, 0U, 34U, 34U, 17U, 34U, 34U, 0U, 0U, 0U, 17U, 0U, 0U, 0U, 34U, 0U, 0U, 0U}; static u16 const ant_swctrl_tbl_rev3_2[32U] = { 136U, 136U, 68U, 136U, 136U, 0U, 0U, 0U, 68U, 0U, 0U, 0U, 136U, 0U, 0U, 0U, 136U, 136U, 68U, 136U, 136U, 0U, 0U, 0U, 68U, 0U, 0U, 0U, 136U, 0U, 0U, 0U}; static u16 const ant_swctrl_tbl_rev3_3[32U] = { 34U, 34U, 17U, 34U, 0U, 0U, 0U, 0U, 17U, 0U, 0U, 0U, 34U, 0U, 0U, 972U, 34U, 34U, 17U, 34U, 0U, 0U, 0U, 0U, 17U, 0U, 0U, 0U, 34U, 0U, 0U, 972U}; static u32 const frame_struct_rev3[832U] = { 134236676U, 1048576U, 16779781U, 1048608U, 159401222U, 1048624U, 159401223U, 1048624U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 134236684U, 1048580U, 16779789U, 1048612U, 159401230U, 1048628U, 159401231U, 1048628U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2564U, 1048576U, 285248005U, 1048608U, 427869446U, 1048624U, 562103558U, 1048624U, 562103558U, 1048624U, 25167108U, 1048624U, 293635333U, 1048624U, 696337671U, 17825840U, 2564U, 1048576U, 285248005U, 1048608U, 562103558U, 1048624U, 562103558U, 1048624U, 696337671U, 17825840U, 0U, 0U, 0U, 0U, 0U, 0U, 2572U, 1048584U, 285248013U, 1048616U, 427869454U, 1048632U, 562103566U, 1048632U, 562103566U, 1048632U, 25167116U, 1048632U, 293635341U, 1048632U, 696337679U, 17825848U, 2572U, 1048584U, 285248013U, 1048616U, 562103566U, 1048632U, 562103566U, 1048632U, 696337679U, 17825848U, 0U, 0U, 0U, 0U, 0U, 0U, 134236676U, 1048576U, 16779781U, 1048608U, 427869446U, 1048624U, 427869446U, 1048624U, 293635332U, 1048624U, 964807173U, 1048624U, 696337671U, 17825840U, 0U, 0U, 268470788U, 1048576U, 964807173U, 1048624U, 427869446U, 1048624U, 696337671U, 17825840U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 134236684U, 1048584U, 16779789U, 1048616U, 427869454U, 1048632U, 427869454U, 1048632U, 293635340U, 1048632U, 964807181U, 1048632U, 696337679U, 17825848U, 0U, 0U, 268470796U, 1048584U, 964807181U, 1048632U, 427869454U, 1048632U, 696337679U, 17825848U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878020U, 1048576U, 33559557U, 1048640U, 184568326U, 26214496U, 318802438U, 26214496U, 318802438U, 26214496U, 1124207108U, 1048672U, 453036549U, 1048672U, 587270663U, 22020192U, 1073878020U, 1048576U, 436261893U, 1048640U, 318802438U, 26214496U, 318802438U, 26214496U, 587270663U, 22020192U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048592U, 33559565U, 1048656U, 184568334U, 26214512U, 318802446U, 26214512U, 318802446U, 26214512U, 1124207116U, 1048688U, 453036557U, 1048688U, 587270671U, 22020208U, 1073878028U, 1048592U, 436261901U, 1048656U, 318802446U, 26214512U, 318802446U, 26214512U, 587270671U, 22020208U, 0U, 0U, 0U, 0U, 0U, 0U, 1342346244U, 1048576U, 838964229U, 1048640U, 184568326U, 26214496U, 184568326U, 26214496U, 1526909444U, 1048672U, 989975557U, 1048672U, 587270663U, 22020192U, 0U, 0U, 1476580356U, 1048576U, 989975557U, 1048672U, 184568326U, 26214496U, 587270663U, 22020192U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1342346252U, 1048592U, 838964237U, 1048656U, 184568334U, 26214512U, 184568334U, 26214512U, 1526909452U, 1048688U, 989975565U, 1048688U, 587270671U, 22020208U, 0U, 0U, 1476580364U, 1048592U, 989975565U, 1048688U, 184568334U, 26214512U, 587270671U, 22020208U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878020U, 1001472U, 1644368901U, 1048640U, 1392675334U, 26214496U, 1392675335U, 26214496U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1001480U, 1644368909U, 1048648U, 1392675342U, 26214504U, 1392675343U, 26214504U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2572U, 1048580U, 285248013U, 1048612U, 427869454U, 1048628U, 562103566U, 1048628U, 562103566U, 1048628U, 25167116U, 1048632U, 293635341U, 1048632U, 293700877U, 1048632U, 696337679U, 17825848U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2572U, 1048584U, 285248013U, 1048616U, 562103566U, 1048632U, 562103566U, 1048632U, 293700877U, 1048632U, 696337679U, 17825848U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 134236676U, 1048576U, 16779781U, 1048608U, 25216262U, 1048624U, 25216262U, 1048624U, 562087180U, 1048624U, 1233259021U, 1483056U, 1099057677U, 1483056U, 696337679U, 17825840U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 536922636U, 1048576U, 1233259021U, 1483056U, 427869454U, 1048624U, 1099057677U, 1483056U, 696337679U, 17825840U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048584U, 33559565U, 1048648U, 184568334U, 26214504U, 318802446U, 26214504U, 318802446U, 26214504U, 1124207116U, 1048688U, 453036557U, 1048688U, 453069325U, 1048688U, 587270671U, 22020208U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048592U, 436261901U, 1048656U, 318802446U, 26214512U, 318802446U, 26214512U, 453069325U, 1048688U, 587270671U, 22020208U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1342346244U, 1048576U, 838964229U, 1048640U, 50350598U, 26214496U, 50350598U, 26214496U, 1795361292U, 1048672U, 1258427405U, 1483104U, 1124226061U, 1483104U, 587270671U, 22020192U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1795363852U, 1048672U, 1258427405U, 1483104U, 184568334U, 26214496U, 1124226061U, 1483104U, 587270671U, 22020192U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878020U, 1048576U, 436261893U, 1048640U, 1392675334U, 26214496U, 1526909446U, 26214496U, 1526909446U, 26214496U, 1124207108U, 1048672U, 453036549U, 1048672U, 1392675335U, 26263648U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048592U, 436261901U, 1048656U, 1392675342U, 26214512U, 1526909454U, 26214512U, 1526909454U, 26214512U, 1124207116U, 1048688U, 453036557U, 1048688U, 1392675343U, 26263664U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878020U, 1048576U, 436261893U, 1048640U, 1526909446U, 26214496U, 1526909446U, 26214496U, 1392675335U, 26263648U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1073878028U, 1048592U, 436261901U, 1048656U, 1526909454U, 26214512U, 1526909454U, 26214512U, 1392675343U, 26263664U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u16 const pilot_tbl_rev3[88U] = { 65288U, 65288U, 65288U, 65288U, 65288U, 65288U, 65288U, 65288U, 32981U, 32981U, 32981U, 32981U, 32981U, 32981U, 32981U, 32981U, 65290U, 65410U, 65440U, 65320U, 65535U, 65535U, 65535U, 65535U, 65410U, 65440U, 65320U, 65290U, 65535U, 65535U, 65535U, 65535U, 63551U, 64031U, 64151U, 64181U, 62141U, 61631U, 65535U, 65535U, 61463U, 63509U, 61973U, 61589U, 61493U, 61469U, 65535U, 65535U, 65288U, 65282U, 65408U, 65312U, 65288U, 65282U, 65408U, 65312U, 61471U, 63511U, 64021U, 62101U, 61621U, 61501U, 65535U, 65535U, 63530U, 64010U, 64130U, 64160U, 62120U, 61610U, 65535U, 65535U, 61442U, 63488U, 61952U, 61568U, 61472U, 61448U, 65535U, 65535U, 61450U, 63490U, 64000U, 62080U, 61600U, 61480U, 65535U, 65535U}; static u32 const tmap_tbl_rev3[448U] = { 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 4044427536U, 286331153U, 301011217U, 273U, 285212672U, 286388497U, 286331153U, 286331377U, 2324212352U, 2326440586U, 2324335272U, 698504U, 2290614272U, 2324334762U, 2326300808U, 2290657448U, 2702250256U, 286331153U, 297865489U, 273U, 285212672U, 286368017U, 286331153U, 286331297U, 2720145952U, 572662306U, 583148066U, 546U, 570425344U, 572695074U, 572662306U, 572662434U, 4044427536U, 286331153U, 301011217U, 69905U, 286326784U, 286388497U, 286331153U, 286331377U, 2829748384U, 2827520168U, 2829625482U, 559786U, 2863267840U, 2829625992U, 2827659946U, 2863303306U, 2863180448U, 2326432426U, 2861206154U, 699016U, 2326396928U, 2863179912U, 2326301322U, 2324211848U, 134744576U, 168298506U, 134875656U, 526344U, 134873088U, 134875144U, 134875144U, 168430088U, 2694881440U, 2158010496U, 2155913376U, 32896U, 2157969408U, 2158002336U, 2692784288U, 2155913376U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2576977920U, 2610665915U, 2612631961U, 2576988601U, 2610543504U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 11184264U, 570425344U, 572699170U, 572662306U, 572662450U, 2988581408U, 572662306U, 584196642U, 546U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 855638016U, 859026227U, 858993459U, 858993587U, 3006477104U, 858993459U, 869479219U, 819U, 570425344U, 572695074U, 572662306U, 572662434U, 2720145952U, 572662306U, 583148066U, 546U, 2579077888U, 2610665915U, 2612631961U, 2576988601U, 2610543513U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 145401992U, 572662272U, 572715554U, 572662306U, 572662514U, 572662306U, 572662306U, 586293794U, 546U, 285212672U, 286388497U, 286331153U, 286331153U, 4044427537U, 286331153U, 301011217U, 17895697U, 3147544832U, 3115957145U, 3113991099U, 3149634459U, 3116079547U, 3113851321U, 3115956635U, 3003U, 2852126720U, 2829625992U, 2827659946U, 2863303306U, 2829748394U, 2827520168U, 2829625482U, 176720554U, 2852126720U, 2829625992U, 2827659946U, 2863303306U, 2829748384U, 2827520168U, 2829625482U, 2730U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 3149642496U, 2577120187U, 2612632475U, 3115956667U, 3115948987U, 3115956667U, 3116080025U, 2457U, 2315255808U, 2861082760U, 2827520170U, 2827651720U, 2827659402U, 2292755114U, 2829748906U, 143173770U, 185273088U, 151718667U, 185142027U, 151587083U, 151587595U, 151587595U, 151587593U, 2313U, 167772160U, 168298504U, 134875146U, 134875656U, 134875146U, 134744074U, 168430088U, 134744074U, 2964369408U, 2425401520U, 2427490448U, 2964369552U, 2964361392U, 2427498672U, 2964361360U, 144U, 2147483648U, 2692784256U, 2692776096U, 2692776064U, 2692784256U, 2158010528U, 2694873248U, 10526880U, 570425344U, 572715554U, 572662306U, 572662514U, 4062323232U, 572662306U, 586293794U, 546U, 285212672U, 286388497U, 286331153U, 286331377U, 4044427536U, 286331153U, 301011217U, 273U, 855638016U, 859042611U, 858993459U, 858993651U, 4080218928U, 858993459U, 871576371U, 819U, 570425344U, 572715554U, 572662306U, 572662514U, 4062323232U, 572662306U, 586293794U, 546U, 2566914048U, 2610665915U, 2612631961U, 2576988601U, 2610543504U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2290647040U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 11184264U, 2292746752U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 145401992U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const intlv_tbl_rev3[7U] = { 8396912U, 108075149U, 174070060U, 170921542U, 12654733U, 134227154U, 112U}; static u32 const tdtrn_tbl_rev3[704U] = { 102499868U, 5303912U, 4120051254U, 4266791670U, 3128U, 4266791670U, 4120051254U, 5303912U, 102499868U, 3999793232U, 4265014674U, 318176850U, 204996608U, 318176850U, 4265014674U, 3999793232U, 102499868U, 5303912U, 4120051254U, 4266791670U, 3128U, 4266791670U, 4120051254U, 5303912U, 102499868U, 3999793232U, 4265014674U, 318176850U, 204996608U, 318176850U, 4265014674U, 3999793232U, 98764259U, 5107468U, 4126408263U, 4267774534U, 3015U, 4267774534U, 4126408263U, 5107468U, 98764259U, 4010541133U, 4266128883U, 306642529U, 197591040U, 306642529U, 4266128883U, 4010541133U, 98764259U, 5107468U, 4126408263U, 4267774534U, 3015U, 4267774534U, 4126408263U, 5107468U, 98764259U, 4010541133U, 4266128883U, 306642529U, 197591040U, 306642529U, 4266128883U, 4010541133U, 4200135256U, 4170515515U, 4283173312U, 4224122792U, 4219794308U, 127465209U, 91619618U, 92539382U, 189792256U, 95941954U, 143000626U, 115212007U, 4219794308U, 4191749732U, 4159177308U, 16775101U, 94897576U, 4156358911U, 39647208U, 107280857U, 4085578628U, 4276553437U, 70387846U, 4114744759U, 2896U, 167118212U, 19006838U, 4143515544U, 4085578628U, 4289264582U, 163643212U, 71039125U, 47448788U, 131990128U, 4237690780U, 4178247316U, 4261478188U, 47449693U, 153747606U, 1375160U, 4247584044U, 124451644U, 9893714U, 4187094407U, 4213965312U, 4273535328U, 148962454U, 77071016U, 4247584044U, 44565656U, 4237691104U, 4183883448U, 33618732U, 4253546897U, 4149346454U, 4215015274U, 4247584044U, 4223139860U, 9832746U, 106758868U, 4281138688U, 4271175946U, 127728790U, 40896478U, 47448788U, 40896478U, 127728790U, 4271175946U, 4281138688U, 106758868U, 9832746U, 4223139860U, 4247584044U, 4215015274U, 4149346454U, 4253546897U, 33618732U, 4183883448U, 4237691104U, 44565656U, 4247584044U, 77071016U, 148962454U, 4273535328U, 4213965312U, 4187094407U, 9893714U, 124451644U, 4247584044U, 1375160U, 153747606U, 47449693U, 4261478188U, 4178247316U, 4237690780U, 131990128U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 103415808U, 4277798745U, 146278664U, 4086758445U, 4191552604U, 4233033224U, 4148753814U, 129107903U, 103417386U, 4165924929U, 4148753814U, 61999608U, 4191552604U, 208274387U, 146278664U, 17234087U, 103415808U, 4277860519U, 146339576U, 4086694867U, 4191615908U, 4232972792U, 4148693610U, 129169473U, 103479766U, 4165863359U, 4148693610U, 62060040U, 4191615908U, 208337965U, 146339576U, 17172313U, 103415808U, 4277798745U, 146278664U, 4086758445U, 4191552604U, 4233033224U, 4148753814U, 129107903U, 103417386U, 4165924929U, 4148753814U, 61999608U, 4191552604U, 208274387U, 146278664U, 17234087U, 103415808U, 4277860519U, 146339576U, 4086694867U, 4191615908U, 4232972792U, 4148693610U, 129169473U, 103479766U, 4165863359U, 4148693610U, 62060040U, 4191615908U, 208337965U, 146339576U, 17172313U, 102499868U, 4281335965U, 4289859905U, 4253547348U, 4133355097U, 49215902U, 23523388U, 4294445494U, 2212U, 717867U, 15725943U, 4202957810U, 4228054865U, 136712039U, 4293919599U, 138607043U, 0U, 104724414U, 4237361168U, 4036622298U, 11469822U, 4094559612U, 176815889U, 198574070U, 4150001664U, 4132044808U, 264568474U, 107150610U, 27724195U, 78381689U, 4005494862U, 4284678352U, 4192532964U, 13696867U, 5172927U, 41485484U, 161677735U, 4245816930U, 4271509444U, 587338U, 63324U, 4294314965U, 4279306889U, 92075022U, 66977967U, 4158320793U, 1113233U, 4156425789U, 0U, 4190308418U, 57671664U, 258410534U, 4283563010U, 200473220U, 4118216943U, 4096458762U, 144965632U, 162988024U, 4030464358U, 4187882222U, 4267308637U, 4216651143U, 289537970U, 10354480U, 98762752U, 4278585093U, 139724960U, 4096130137U, 4196205610U, 4235785850U, 4155307534U, 123340646U, 98764259U, 4171692186U, 4155307534U, 59246982U, 4196205610U, 198902695U, 139724960U, 16447739U, 98762752U, 4278647035U, 139786080U, 4096066471U, 4196269014U, 4235725190U, 4155247090U, 123402394U, 98826781U, 4171630438U, 4155247090U, 59307642U, 4196269014U, 198966361U, 139786080U, 16385797U, 98762752U, 4278585093U, 139724960U, 4096130137U, 4196205610U, 4235785850U, 4155307534U, 123340646U, 98764259U, 4171692186U, 4155307534U, 59246982U, 4196205610U, 198902695U, 139724960U, 16447739U, 98762752U, 4278647035U, 139786080U, 4096066471U, 4196269014U, 4235725190U, 4155247090U, 123402394U, 98826781U, 4171630438U, 4155247090U, 59307642U, 4196269014U, 198966361U, 139786080U, 16385797U, 4200135256U, 4176543232U, 71829309U, 4257873478U, 4187030104U, 144507911U, 4250728218U, 45088224U, 138282134U, 4284090176U, 4286250391U, 16646641U, 591918U, 4204068725U, 4274911466U, 4289787539U, 4247583320U, 70516502U, 4221830621U, 4200661825U, 111544011U, 3800365U, 108526231U, 33162720U, 4170580030U, 123340427U, 19725374U, 4196661645U, 4236049731U, 4287691789U, 29428098U, 12976598U, 4247584044U, 30802118U, 159515073U, 4228775824U, 4249091196U, 4186831395U, 4231921964U, 109774682U, 4126870U, 98566650U, 4204201591U, 4247584825U, 113968806U, 54655585U, 98433956U, 4279632947U, 4200135980U, 4136894384U, 4176150221U, 4285921940U, 137232393U, 32571646U, 4254596986U, 121700186U, 76941374U, 4259316399U, 4145741148U, 67569821U, 39385489U, 4266065353U, 121439304U, 4261476592U, 4247584044U, 4242539776U, 4228513244U, 4268228951U, 80151921U, 4231724833U, 4241949224U, 91030135U, 33619456U, 2292007U, 4265345835U, 4232380220U, 65666011U, 72811283U, 80346972U, 852920U, 4200071168U, 4226351314U, 4191223307U, 19267065U, 69534143U, 53017131U, 4289266416U, 4196729175U, 33619456U, 57934904U, 4278453757U, 51183186U, 3668793U, 4285072581U, 83426595U, 4247911451U, 4247584044U, 4229692721U, 4246930680U, 80084841U, 4214816823U, 4266787596U, 100531972U, 70779764U, 4261413376U, 22542885U, 49348521U, 4197122856U, 29295653U, 4260954405U, 4262197712U, 13827049U, 64088U, 62390285U, 4284220617U, 51577943U, 4225434601U, 4282186820U, 53214780U, 4180082722U, 4261413376U, 41354605U, 36240599U, 4280417338U, 91292871U, 22543976U, 4259118089U, 83950816U, 4247584044U, 83950816U, 4259118089U, 22543976U, 91292871U, 4280417338U, 36240599U, 41354605U, 4261413376U, 4180082722U, 53214780U, 4282186820U, 4225434601U, 51577943U, 4284220617U, 62390285U, 64088U, 13827049U, 4262197712U, 4260954405U, 29295653U, 4197122856U, 49348521U, 22542885U, 4261413376U, 70779764U, 100531972U, 4266787596U, 4214816823U, 80084841U, 4246930680U, 4229692721U, 4247584044U, 4247911451U, 83426595U, 4285072581U, 3668793U, 51183186U, 4278453757U, 57934904U, 33619456U, 4196729175U, 4289266416U, 53017131U, 69534143U, 19267065U, 4191223307U, 4226351314U, 4200071168U, 852920U, 80346972U, 72811283U, 65666011U, 4232380220U, 4265345835U, 2292007U, 33619456U, 91030135U, 4241949224U, 4231724833U, 80151921U, 4268228951U, 4228513244U, 4242539776U, 94896128U, 4279240382U, 134219850U, 4103928958U, 4200072192U, 4238145242U, 4160812658U, 118490908U, 94897576U, 4176541924U, 4160812658U, 56887590U, 4200072192U, 191103874U, 134219850U, 15792450U, 94896128U, 4279302466U, 134281142U, 4103865218U, 4200135680U, 4238084390U, 4160752014U, 118552804U, 94960216U, 4176480028U, 4160752014U, 56948442U, 4200135680U, 191167614U, 134281142U, 15730366U, 94896128U, 4279240382U, 134219850U, 4103928958U, 4200072192U, 4238145242U, 4160812658U, 118490908U, 94897576U, 4176541924U, 4160812658U, 56887590U, 4200072192U, 191103874U, 134219850U, 15792450U, 94896128U, 4279302466U, 134281142U, 4103865218U, 4200135680U, 4238084390U, 4160752014U, 118552804U, 94960216U, 4176480028U, 4160752014U, 56948442U, 4200135680U, 191167614U, 134281142U, 15730366U}; u32 const noise_var_tbl_rev3[256U] = { 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U, 34669073U, 333U}; static u16 const mcs_tbl_rev3[128U] = { 0U, 8U, 10U, 16U, 18U, 25U, 26U, 28U, 128U, 136U, 138U, 144U, 146U, 153U, 154U, 156U, 256U, 264U, 266U, 272U, 274U, 281U, 282U, 284U, 384U, 392U, 394U, 400U, 402U, 409U, 410U, 412U, 0U, 152U, 160U, 168U, 154U, 162U, 170U, 288U, 296U, 296U, 304U, 312U, 312U, 320U, 290U, 298U, 298U, 306U, 314U, 314U, 322U, 424U, 432U, 440U, 432U, 440U, 448U, 456U, 448U, 456U, 464U, 464U, 472U, 426U, 434U, 442U, 434U, 442U, 450U, 458U, 450U, 458U, 466U, 466U, 474U, 1U, 2U, 4U, 9U, 12U, 17U, 20U, 24U, 32U, 33U, 34U, 36U, 129U, 130U, 132U, 137U, 140U, 145U, 148U, 152U, 160U, 161U, 162U, 164U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U, 7U}; static u32 const tdi_tbl20_ant0_rev3[55U] = { 594470U, 660521U, 743085U, 809136U, 875187U, 957622U, 1023674U, 49469U, 131841U, 197892U, 263944U, 329995U, 412558U, 610961U, 677012U, 759576U, 825639U, 891690U, 974126U, 1040177U, 65972U, 148407U, 214459U, 280510U, 362882U, 429061U, 627465U, 693516U, 776079U, 842130U, 908182U, 990617U, 24488U, 82476U, 164911U, 230962U, 297013U, 379448U, 445628U, 644031U, 726531U, 792582U, 858634U, 924685U, 1007120U, 32915U, 98967U, 181402U, 247424U, 313472U, 396032U, 462080U, 0U, 0U, 0U}; static u32 const tdi_tbl20_ant1_rev3[55U] = { 84774U, 167209U, 234413U, 300592U, 383027U, 449078U, 629818U, 695869U, 770177U, 836228U, 902280U, 984715U, 18574U, 101265U, 184852U, 250904U, 317095U, 399530U, 465582U, 646321U, 728756U, 786743U, 852795U, 918846U, 1001218U, 35077U, 134153U, 201356U, 267407U, 333586U, 416022U, 596761U, 662824U, 745260U, 803247U, 869298U, 951733U, 1017784U, 51644U, 150719U, 217859U, 283910U, 366474U, 432525U, 613264U, 679315U, 761751U, 819738U, 885760U, 968192U, 1034240U, 68096U, 0U, 0U, 0U}; static u32 const tdi_tbl40_ant0_rev3[110U] = { 1155910U, 1273039U, 1373657U, 1458658U, 1559403U, 1660021U, 1778563U, 1879308U, 1996310U, 33311U, 134056U, 251058U, 353351U, 470480U, 571098U, 656099U, 756844U, 857590U, 1172612U, 1289741U, 1390359U, 1475360U, 1576105U, 1676851U, 1795400U, 1896145U, 2013147U, 50148U, 150893U, 268023U, 370053U, 487183U, 587800U, 672801U, 773547U, 890676U, 1189449U, 1306578U, 1407196U, 1492197U, 1592942U, 1710072U, 1812102U, 1912848U, 2029977U, 66850U, 167596U, 284725U, 386890U, 504019U, 604765U, 689638U, 790383U, 907513U, 1206151U, 1323281U, 1424026U, 1508899U, 1609645U, 1726774U, 1828939U, 1946068U, 2046814U, 83687U, 200816U, 301562U, 403592U, 520722U, 621467U, 706468U, 807086U, 924215U, 1222988U, 1340117U, 1440863U, 1525864U, 1626481U, 1743611U, 1845641U, 1962771U, 2063516U, 100517U, 217519U, 318264U, 436813U, 537559U, 638304U, 723305U, 823923U, 941052U, 1256074U, 1356820U, 1457565U, 1542566U, 1643184U, 1760313U, 1862606U, 1979608U, 2080353U, 117354U, 234356U, 335101U, 453643U, 554261U, 655006U, 740007U, 840625U, 957754U, 0U, 0U}; static u32 const tdi_tbl40_ant1_rev3[110U] = { 2022198U, 76234U, 176979U, 294109U, 379110U, 496111U, 596985U, 698887U, 799633U, 916762U, 1181987U, 1298989U, 1399863U, 1501899U, 1602644U, 1719774U, 1804775U, 1905392U, 2039034U, 93064U, 210066U, 310811U, 395812U, 512814U, 613688U, 715852U, 816469U, 933599U, 1198824U, 1315825U, 1418107U, 1518729U, 1619347U, 1720732U, 1821477U, 1938479U, 2057145U, 109901U, 226903U, 311904U, 429033U, 529651U, 631932U, 732554U, 833172U, 934557U, 1215526U, 1332656U, 1434810U, 1535566U, 1636184U, 1737569U, 1838314U, 1955444U, 2073981U, 126603U, 243605U, 328606U, 445735U, 546481U, 648646U, 749391U, 850009U, 951394U, 1248747U, 1349493U, 1451523U, 1552268U, 1652886U, 1754271U, 1855016U, 1972146U, 42695U, 143440U, 260570U, 345443U, 462572U, 563318U, 665348U, 766093U, 866839U, 1148320U, 1265449U, 1366195U, 1468360U, 1569105U, 1669851U, 1771108U, 1871853U, 1988983U, 59397U, 160143U, 277272U, 362145U, 479275U, 580020U, 682185U, 782930U, 900060U, 1165285U, 1282286U, 1383032U, 1485062U, 1585808U, 1686553U, 1787938U, 1888556U, 2005685U, 0U, 0U}; static u32 const pltlut_tbl_rev3[6U] = { 1985217043U, 1648390993U, 1985229328U, 1985217043U, 1985217043U, 1984103713U}; static u32 const chanest_tbl_rev3[96U] = { 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 1145324612U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U, 269488144U}; static u8 const frame_lut_rev3[32U] = { 2U, 4U, 20U, 20U, 3U, 5U, 22U, 22U, 10U, 12U, 28U, 28U, 11U, 13U, 30U, 30U, 6U, 8U, 24U, 24U, 7U, 9U, 26U, 26U, 14U, 16U, 32U, 40U, 15U, 17U, 34U, 42U}; static u8 const est_pwr_lut_core0_rev3[64U] = { 85U, 84U, 84U, 83U, 82U, 82U, 81U, 81U, 80U, 79U, 79U, 78U, 78U, 77U, 76U, 76U, 75U, 74U, 73U, 73U, 72U, 71U, 70U, 70U, 69U, 68U, 67U, 66U, 65U, 64U, 64U, 63U, 62U, 61U, 60U, 58U, 57U, 56U, 55U, 54U, 53U, 51U, 50U, 49U, 47U, 46U, 44U, 43U, 41U, 39U, 37U, 35U, 33U, 31U, 29U, 26U, 24U, 21U, 18U, 14U, 11U, 7U, 2U, 253U}; static u8 const est_pwr_lut_core1_rev3[64U] = { 85U, 84U, 84U, 83U, 82U, 82U, 81U, 81U, 80U, 79U, 79U, 78U, 78U, 77U, 76U, 76U, 75U, 74U, 73U, 73U, 72U, 71U, 70U, 70U, 69U, 68U, 67U, 66U, 65U, 64U, 64U, 63U, 62U, 61U, 60U, 58U, 57U, 56U, 55U, 54U, 53U, 51U, 50U, 49U, 47U, 46U, 44U, 43U, 41U, 39U, 37U, 35U, 33U, 31U, 29U, 26U, 24U, 21U, 18U, 14U, 11U, 7U, 2U, 253U}; static u8 const adj_pwr_lut_core0_rev3[128U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u8 const adj_pwr_lut_core1_rev3[128U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const gainctrl_lut_core0_rev3[128U] = { 1542914116U, 1542914114U, 1542914112U, 1542914110U, 1542914108U, 1542914107U, 1542914105U, 1542914103U, 1542914102U, 1542914100U, 1542914099U, 1542914097U, 1542914096U, 1537671236U, 1537671234U, 1537671232U, 1537671230U, 1537671228U, 1537671227U, 1537671225U, 1537671223U, 1537671222U, 1537671220U, 1537671219U, 1534525508U, 1534525506U, 1534525504U, 1534525502U, 1534525500U, 1534525499U, 1534525497U, 1534525495U, 1534525494U, 1534525492U, 1534525491U, 1534525489U, 1534525488U, 1534525487U, 1534525485U, 1534525484U, 1531379780U, 1531379778U, 1531379776U, 1531379774U, 1531379772U, 1531379771U, 1531379769U, 1531379767U, 1531379766U, 1531379764U, 1531379763U, 1531379761U, 1531379760U, 1531379759U, 1531379757U, 1531379756U, 1531379755U, 1531379754U, 1529282628U, 1529282626U, 1529282624U, 1529282622U, 1529282620U, 1529282619U, 1529282617U, 1529282615U, 1529282614U, 1529282612U, 1529282611U, 1529282609U, 1529282608U, 1529282607U, 1528234052U, 1528234050U, 1528234048U, 1528234046U, 1528234044U, 1528234043U, 1528234041U, 1528234039U, 1528234038U, 1528234036U, 1528234035U, 1528234033U, 1528234032U, 1528234031U, 1528234029U, 1528234028U, 1528234027U, 1528234026U, 1528234024U, 1528234023U, 1528234022U, 1528234021U, 1528234020U, 1528234019U, 1527185476U, 1527185474U, 1527185472U, 1527185470U, 1527185468U, 1527185467U, 1527185465U, 1527185463U, 1527185462U, 1527185460U, 1527185459U, 1527185457U, 1527185456U, 1527185455U, 1527185453U, 1527185452U, 1527185451U, 1527185450U, 1527185448U, 1527185447U, 1527185446U, 1527185445U, 1527185444U, 1527185443U, 1527185442U, 1527185441U, 1527185440U, 1527185439U, 1527185438U, 1527185437U, 1527185437U, 1527185436U}; static u32 const gainctrl_lut_core1_rev3[128U] = { 1542914116U, 1542914114U, 1542914112U, 1542914110U, 1542914108U, 1542914107U, 1542914105U, 1542914103U, 1542914102U, 1542914100U, 1542914099U, 1542914097U, 1542914096U, 1537671236U, 1537671234U, 1537671232U, 1537671230U, 1537671228U, 1537671227U, 1537671225U, 1537671223U, 1537671222U, 1537671220U, 1537671219U, 1534525508U, 1534525506U, 1534525504U, 1534525502U, 1534525500U, 1534525499U, 1534525497U, 1534525495U, 1534525494U, 1534525492U, 1534525491U, 1534525489U, 1534525488U, 1534525487U, 1534525485U, 1534525484U, 1531379780U, 1531379778U, 1531379776U, 1531379774U, 1531379772U, 1531379771U, 1531379769U, 1531379767U, 1531379766U, 1531379764U, 1531379763U, 1531379761U, 1531379760U, 1531379759U, 1531379757U, 1531379756U, 1531379755U, 1531379754U, 1529282628U, 1529282626U, 1529282624U, 1529282622U, 1529282620U, 1529282619U, 1529282617U, 1529282615U, 1529282614U, 1529282612U, 1529282611U, 1529282609U, 1529282608U, 1529282607U, 1528234052U, 1528234050U, 1528234048U, 1528234046U, 1528234044U, 1528234043U, 1528234041U, 1528234039U, 1528234038U, 1528234036U, 1528234035U, 1528234033U, 1528234032U, 1528234031U, 1528234029U, 1528234028U, 1528234027U, 1528234026U, 1528234024U, 1528234023U, 1528234022U, 1528234021U, 1528234020U, 1528234019U, 1527185476U, 1527185474U, 1527185472U, 1527185470U, 1527185468U, 1527185467U, 1527185465U, 1527185463U, 1527185462U, 1527185460U, 1527185459U, 1527185457U, 1527185456U, 1527185455U, 1527185453U, 1527185452U, 1527185451U, 1527185450U, 1527185448U, 1527185447U, 1527185446U, 1527185445U, 1527185444U, 1527185443U, 1527185442U, 1527185441U, 1527185440U, 1527185439U, 1527185438U, 1527185437U, 1527185437U, 1527185436U}; static u32 const iq_lut_core0_rev3[128U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u32 const iq_lut_core1_rev3[128U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u16 const loft_lut_core0_rev3[128U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u16 const loft_lut_core1_rev3[128U] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; static u16 const papd_comp_rfpwr_tbl_core0_rev3[128U] = { 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U}; static u16 const papd_comp_rfpwr_tbl_core1_rev3[128U] = { 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 54U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 42U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 30U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 14U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 508U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 494U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U, 470U}; struct phytbl_info const mimophytbl_info_rev3_volatile[1U] = { {(void const *)(& ant_swctrl_tbl_rev3), 32U, 9U, 0U, 16U}}; struct phytbl_info const mimophytbl_info_rev3_volatile1[1U] = { {(void const *)(& ant_swctrl_tbl_rev3_1), 32U, 9U, 0U, 16U}}; struct phytbl_info const mimophytbl_info_rev3_volatile2[1U] = { {(void const *)(& ant_swctrl_tbl_rev3_2), 32U, 9U, 0U, 16U}}; struct phytbl_info const mimophytbl_info_rev3_volatile3[1U] = { {(void const *)(& ant_swctrl_tbl_rev3_3), 32U, 9U, 0U, 16U}}; struct phytbl_info const mimophytbl_info_rev3[24U] = { {(void const *)(& frame_struct_rev3), 832U, 10U, 0U, 32U}, {(void const *)(& pilot_tbl_rev3), 88U, 11U, 0U, 16U}, {(void const *)(& tmap_tbl_rev3), 448U, 12U, 0U, 32U}, {(void const *)(& intlv_tbl_rev3), 7U, 13U, 0U, 32U}, {(void const *)(& tdtrn_tbl_rev3), 704U, 14U, 0U, 32U}, {(void const *)(& noise_var_tbl_rev3), 256U, 16U, 0U, 32U}, {(void const *)(& mcs_tbl_rev3), 128U, 18U, 0U, 16U}, {(void const *)(& tdi_tbl20_ant0_rev3), 55U, 19U, 128U, 32U}, {(void const *)(& tdi_tbl20_ant1_rev3), 55U, 19U, 256U, 32U}, {(void const *)(& tdi_tbl40_ant0_rev3), 110U, 19U, 640U, 32U}, {(void const *)(& tdi_tbl40_ant1_rev3), 110U, 19U, 768U, 32U}, {(void const *)(& pltlut_tbl_rev3), 6U, 20U, 0U, 32U}, {(void const *)(& chanest_tbl_rev3), 96U, 22U, 0U, 32U}, {(void const *)(& frame_lut_rev3), 32U, 24U, 0U, 8U}, {(void const *)(& est_pwr_lut_core0_rev3), 64U, 26U, 0U, 8U}, {(void const *)(& est_pwr_lut_core1_rev3), 64U, 27U, 0U, 8U}, {(void const *)(& adj_pwr_lut_core0_rev3), 128U, 26U, 64U, 8U}, {(void const *)(& adj_pwr_lut_core1_rev3), 128U, 27U, 64U, 8U}, {(void const *)(& gainctrl_lut_core0_rev3), 128U, 26U, 192U, 32U}, {(void const *)(& gainctrl_lut_core1_rev3), 128U, 27U, 192U, 32U}, {(void const *)(& iq_lut_core0_rev3), 128U, 26U, 320U, 32U}, {(void const *)(& iq_lut_core1_rev3), 128U, 27U, 320U, 32U}, {(void const *)(& loft_lut_core0_rev3), 128U, 26U, 448U, 16U}, {(void const *)(& loft_lut_core1_rev3), 128U, 27U, 448U, 16U}}; unsigned int const mimophytbl_info_sz_rev3 = 24U; unsigned int const mimophytbl_info_sz_rev3_volatile = 1U; unsigned int const mimophytbl_info_sz_rev3_volatile1 = 1U; unsigned int const mimophytbl_info_sz_rev3_volatile2 = 1U; unsigned int const mimophytbl_info_sz_rev3_volatile3 = 1U; static u32 const tmap_tbl_rev7[448U] = { 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 4044427536U, 286331153U, 301011217U, 273U, 285212672U, 286388497U, 286331153U, 286331377U, 2324212352U, 2326440586U, 2324335272U, 698504U, 2290614272U, 2324334762U, 2326300808U, 2290657448U, 2702250256U, 286331153U, 297865489U, 273U, 285212672U, 286368017U, 286331153U, 286331297U, 2720145952U, 572662306U, 583148066U, 546U, 570425344U, 572695074U, 572662306U, 572662434U, 4044427536U, 286331153U, 301011217U, 69905U, 286326784U, 286388497U, 286331153U, 286331377U, 2829748384U, 2827520168U, 2829625482U, 559786U, 2863267840U, 2829625992U, 2827659946U, 2863303306U, 2863180448U, 2326432426U, 2861206154U, 699016U, 2326396928U, 2863179912U, 2326301322U, 2324211848U, 134744576U, 168298506U, 134875656U, 526344U, 134873088U, 134875144U, 134875144U, 168430088U, 2694881440U, 2158010496U, 2155913376U, 32896U, 2157969408U, 2158002336U, 2692784288U, 2155913376U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 2576977920U, 2610665915U, 2612631961U, 2576988601U, 2610543504U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 11184264U, 570425344U, 572699170U, 572662306U, 572662450U, 2988581408U, 572662306U, 584196642U, 546U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 855638016U, 859026227U, 858993459U, 858993587U, 3006477104U, 858993459U, 869479219U, 819U, 570425344U, 572695074U, 572662306U, 572662434U, 2720145952U, 572662306U, 583148066U, 546U, 2579077888U, 2610665915U, 2612631961U, 2576988601U, 2610543513U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 145401992U, 572662272U, 572715554U, 572662306U, 572662514U, 572662306U, 572662306U, 586293794U, 546U, 285212672U, 286388497U, 286331153U, 286331153U, 4044427537U, 286331153U, 301011217U, 17895697U, 3147544832U, 3115957145U, 3113991099U, 3149634459U, 3116079547U, 3113851321U, 3115956635U, 3003U, 2852126720U, 2829625992U, 2827659946U, 2863303306U, 2829748394U, 2827520168U, 2829625482U, 176720554U, 2852126720U, 2829625992U, 2827659946U, 2863303306U, 2829748384U, 2827520168U, 2829625482U, 2730U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 3149642496U, 2577120187U, 2612632475U, 3115956667U, 3115948987U, 3115956667U, 3116080025U, 2457U, 2315255808U, 2861082760U, 2827520170U, 2827651720U, 2827659402U, 2292755114U, 2829748906U, 143173770U, 185273088U, 151718667U, 185142027U, 151587083U, 151587595U, 151587595U, 151587593U, 2313U, 167772160U, 168298504U, 134875146U, 134875656U, 134875146U, 134744074U, 168430088U, 134744074U, 2964369408U, 2425401520U, 2427490448U, 2964369552U, 2964361392U, 2427498672U, 2964361360U, 144U, 2147483648U, 2692784256U, 2692776096U, 2692776064U, 2692784256U, 2158010528U, 2694873248U, 10526880U, 570425344U, 572715554U, 572662306U, 572662514U, 4062323232U, 572662306U, 586293794U, 546U, 285212672U, 286388497U, 286331153U, 286331377U, 4044427536U, 286331153U, 301011217U, 273U, 855638016U, 859042611U, 858993459U, 858993651U, 4080218928U, 858993459U, 871576371U, 819U, 570425344U, 572715554U, 572662306U, 572662514U, 4062323232U, 572662306U, 586293794U, 546U, 2566914048U, 2610665915U, 2612631961U, 2576988601U, 2610543504U, 2612771739U, 2610666425U, 2457U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2290647040U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 11184264U, 2292746752U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 698504U, 2290614272U, 2324334762U, 2326300808U, 2290657448U, 2324212360U, 2326440586U, 2324335272U, 145401992U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 285212672U, 286368017U, 286331153U, 286331297U, 2702250256U, 286331153U, 297865489U, 273U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 2281701376U, 2324334762U, 2326300808U, 2290657448U, 2324212352U, 2326440586U, 2324335272U, 2184U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U}; u32 const noise_var_tbl_rev7[256U] = { 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U, 34341388U, 333U}; static u32 const papd_comp_epsilon_tbl_core0_rev7[64U] = { 0U, 0U, 90147U, 24616U, 213046U, 213038U, 467004U, 450615U, 458800U, 606239U, 630799U, 745485U, 819207U, 843783U, 1056767U, 1187833U, 1236996U, 1368060U, 1499126U, 1630185U, 1785829U, 1859536U, 1957826U, 2039734U, 2129828U, 2203535U, 2293629U, 2391916U, 2416475U, 2522955U, 2613051U, 2735931U, 2842415U, 2965294U, 3104554U, 3145493U, 3235595U, 3333882U, 3391211U, 3473113U, 3489477U, 3546800U, 3554971U, 3587719U, 3587696U, 3735143U, 4505266U, 5324531U, 5857041U, 6725437U, 7921631U, 10568618U, 23343103U, 23244799U, 23203839U, 23121919U, 23007231U, 22917119U, 22794239U, 22794239U, 22761471U, 22728703U, 22614015U, 22466559U}; static u32 const papd_cal_scalars_tbl_core0_rev7[64U] = { 190709805U, 182583343U, 171638834U, 161939509U, 153223224U, 145424443U, 136249407U, 128057411U, 120848455U, 114425931U, 108658767U, 102170708U, 96403545U, 91291742U, 85852260U, 80937066U, 76611696U, 72089719U, 68092030U, 64553093U, 60883085U, 57606293U, 54329502U, 51052712U, 48234674U, 45678780U, 43122887U, 40698067U, 38338784U, 36241645U, 34210043U, 32243978U, 30540057U, 28770602U, 27132220U, 25690446U, 24248674U, 22872439U, 21561742U, 20382117U, 19268030U, 18153944U, 17170932U, 16187922U, 15270449U, 14418515U, 13632118U, 12845723U, 12124867U, 11469549U, 10814233U, 10224456U, 9634682U, 9110447U, 8586214U, 8127522U, 7668832U, 7210147U, 6817001U, 6423859U, 6096258U, 5768662U, 5441070U, 5113484U}; static u32 const papd_comp_epsilon_tbl_core1_rev7[64U] = { 0U, 0U, 90147U, 24616U, 213046U, 213038U, 467004U, 450615U, 458800U, 606239U, 630799U, 745485U, 819207U, 843783U, 1056767U, 1187833U, 1236996U, 1368060U, 1499126U, 1630185U, 1785829U, 1859536U, 1957826U, 2039734U, 2129828U, 2203535U, 2293629U, 2391916U, 2416475U, 2522955U, 2613051U, 2735931U, 2842415U, 2965294U, 3104554U, 3145493U, 3235595U, 3333882U, 3391211U, 3473113U, 3489477U, 3546800U, 3554971U, 3587719U, 3587696U, 3735143U, 4505266U, 5324531U, 5857041U, 6725437U, 7921631U, 10568618U, 23343103U, 23244799U, 23203839U, 23121919U, 23007231U, 22917119U, 22794239U, 22794239U, 22761471U, 22728703U, 22614015U, 22466559U}; static u32 const papd_cal_scalars_tbl_core1_rev7[64U] = { 190709805U, 182583343U, 171638834U, 161939509U, 153223224U, 145424443U, 136249407U, 128057411U, 120848455U, 114425931U, 108658767U, 102170708U, 96403545U, 91291742U, 85852260U, 80937066U, 76611696U, 72089719U, 68092030U, 64553093U, 60883085U, 57606293U, 54329502U, 51052712U, 48234674U, 45678780U, 43122887U, 40698067U, 38338784U, 36241645U, 34210043U, 32243978U, 30540057U, 28770602U, 27132220U, 25690446U, 24248674U, 22872439U, 21561742U, 20382117U, 19268030U, 18153944U, 17170932U, 16187922U, 15270449U, 14418515U, 13632118U, 12845723U, 12124867U, 11469549U, 10814233U, 10224456U, 9634682U, 9110447U, 8586214U, 8127522U, 7668832U, 7210147U, 6817001U, 6423859U, 6096258U, 5768662U, 5441070U, 5113484U}; struct phytbl_info const mimophytbl_info_rev7[30U] = { {(void const *)(& frame_struct_rev3), 832U, 10U, 0U, 32U}, {(void const *)(& pilot_tbl_rev3), 88U, 11U, 0U, 16U}, {(void const *)(& tmap_tbl_rev7), 448U, 12U, 0U, 32U}, {(void const *)(& intlv_tbl_rev3), 7U, 13U, 0U, 32U}, {(void const *)(& tdtrn_tbl_rev3), 704U, 14U, 0U, 32U}, {(void const *)(& noise_var_tbl_rev7), 256U, 16U, 0U, 32U}, {(void const *)(& mcs_tbl_rev3), 128U, 18U, 0U, 16U}, {(void const *)(& tdi_tbl20_ant0_rev3), 55U, 19U, 128U, 32U}, {(void const *)(& tdi_tbl20_ant1_rev3), 55U, 19U, 256U, 32U}, {(void const *)(& tdi_tbl40_ant0_rev3), 110U, 19U, 640U, 32U}, {(void const *)(& tdi_tbl40_ant1_rev3), 110U, 19U, 768U, 32U}, {(void const *)(& pltlut_tbl_rev3), 6U, 20U, 0U, 32U}, {(void const *)(& chanest_tbl_rev3), 96U, 22U, 0U, 32U}, {(void const *)(& frame_lut_rev3), 32U, 24U, 0U, 8U}, {(void const *)(& est_pwr_lut_core0_rev3), 64U, 26U, 0U, 8U}, {(void const *)(& est_pwr_lut_core1_rev3), 64U, 27U, 0U, 8U}, {(void const *)(& adj_pwr_lut_core0_rev3), 128U, 26U, 64U, 8U}, {(void const *)(& adj_pwr_lut_core1_rev3), 128U, 27U, 64U, 8U}, {(void const *)(& gainctrl_lut_core0_rev3), 128U, 26U, 192U, 32U}, {(void const *)(& gainctrl_lut_core1_rev3), 128U, 27U, 192U, 32U}, {(void const *)(& iq_lut_core0_rev3), 128U, 26U, 320U, 32U}, {(void const *)(& iq_lut_core1_rev3), 128U, 27U, 320U, 32U}, {(void const *)(& loft_lut_core0_rev3), 128U, 26U, 448U, 16U}, {(void const *)(& loft_lut_core1_rev3), 128U, 27U, 448U, 16U}, {(void const *)(& papd_comp_rfpwr_tbl_core0_rev3), 128U, 26U, 576U, 16U}, {(void const *)(& papd_comp_rfpwr_tbl_core1_rev3), 128U, 27U, 576U, 16U}, {(void const *)(& papd_comp_epsilon_tbl_core0_rev7), 64U, 31U, 0U, 32U}, {(void const *)(& papd_cal_scalars_tbl_core0_rev7), 64U, 32U, 0U, 32U}, {(void const *)(& papd_comp_epsilon_tbl_core1_rev7), 64U, 33U, 0U, 32U}, {(void const *)(& papd_cal_scalars_tbl_core1_rev7), 64U, 34U, 0U, 32U}}; unsigned int const mimophytbl_info_sz_rev7 = 30U; struct phytbl_info const mimophytbl_info_rev16[11U] = { {(void const *)(& noise_var_tbl_rev7), 256U, 16U, 0U, 32U}, {(void const *)(& est_pwr_lut_core0_rev3), 64U, 26U, 0U, 8U}, {(void const *)(& est_pwr_lut_core1_rev3), 64U, 27U, 0U, 8U}, {(void const *)(& adj_pwr_lut_core0_rev3), 128U, 26U, 64U, 8U}, {(void const *)(& adj_pwr_lut_core1_rev3), 128U, 27U, 64U, 8U}, {(void const *)(& gainctrl_lut_core0_rev3), 128U, 26U, 192U, 32U}, {(void const *)(& gainctrl_lut_core1_rev3), 128U, 27U, 192U, 32U}, {(void const *)(& iq_lut_core0_rev3), 128U, 26U, 320U, 32U}, {(void const *)(& iq_lut_core1_rev3), 128U, 27U, 320U, 32U}, {(void const *)(& loft_lut_core0_rev3), 128U, 26U, 448U, 16U}, {(void const *)(& loft_lut_core1_rev3), 128U, 27U, 448U, 16U}}; unsigned int const mimophytbl_info_sz_rev16 = 11U; bool ldv_queue_work_on_227(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_228(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_229(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_230(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_231(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_241(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_243(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_242(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_245(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_244(struct workqueue_struct *ldv_func_arg1 ) ; u16 qm_mulu16(u16 op1 , u16 op2 ) ; s16 qm_muls16(s16 op1 , s16 op2 ) ; s32 qm_add32(s32 op1 , s32 op2 ) ; s16 qm_add16(s16 op1 , s16 op2 ) ; s32 qm_shl32(s32 op , int shift ) ; s16 qm_shl16(s16 op , int shift ) ; s16 qm_norm32(s32 op ) ; u16 qm_mulu16(u16 op1 , u16 op2 ) { { return ((u16 )((unsigned int )op1 * (unsigned int )op2 >> 16)); } } s16 qm_muls16(s16 op1 , s16 op2 ) { s32 result ; { if ((int )op1 == -32768 && (int )op2 == -32768) { result = 2147483647; } else { result = (int )op1 * (int )op2; } return ((s16 )(result >> 15)); } } s32 qm_add32(s32 op1 , s32 op2 ) { s32 result ; { result = op1 + op2; if ((op1 < 0 && op2 < 0) && result > 0) { result = (-0x7FFFFFFF-1); } else if ((op1 > 0 && op2 > 0) && result < 0) { result = 2147483647; } else { } return (result); } } s16 qm_add16(s16 op1 , s16 op2 ) { s16 result ; s32 temp ; { temp = (int )op1 + (int )op2; if (temp > 32767) { result = 32767; } else if (temp < -32768) { result = -32768; } else { result = (short )temp; } return (result); } } s16 qm_sub16(s16 op1 , s16 op2 ) { s16 result ; s32 temp ; { temp = (int )op1 - (int )op2; if (temp > 32767) { result = 32767; } else if (temp < -32768) { result = -32768; } else { result = (short )temp; } return (result); } } s32 qm_shl32(s32 op , int shift ) { int i ; s32 result ; { result = op; if (shift > 31) { shift = 31; } else if (shift < -31) { shift = -31; } else { } if (shift >= 0) { i = 0; goto ldv_20157; ldv_20156: result = qm_add32(result, result); i = i + 1; ldv_20157: ; if (i < shift) { goto ldv_20156; } else { } } else { result = result >> - shift; } return (result); } } s16 qm_shl16(s16 op , int shift ) { int i ; s16 result ; { result = op; if (shift > 15) { shift = 15; } else if (shift < -15) { shift = -15; } else { } if (shift > 0) { i = 0; goto ldv_20166; ldv_20165: result = qm_add16((int )result, (int )result); i = i + 1; ldv_20166: ; if (i < shift) { goto ldv_20165; } else { } } else { result = (s16 )((int )result >> - shift); } return (result); } } s16 qm_shr16(s16 op , int shift ) { s16 tmp ; { tmp = qm_shl16((int )op, - shift); return (tmp); } } s16 qm_norm32(s32 op ) { u16 u16extraSignBits ; { if (op == 0) { return (31); } else { u16extraSignBits = 0U; goto ldv_20177; ldv_20176: u16extraSignBits = (u16 )((int )u16extraSignBits + 1); op = op << 1; ldv_20177: ; if (op >> 31 == op >> 30) { goto ldv_20176; } else { } } return ((s16 )u16extraSignBits); } } static s16 const log_table[32U] = { 0, 1455, 2866, 4236, 5568, 6863, 8124, 9352, 10549, 11716, 12855, 13968, 15055, 16117, 17156, 18173, 19168, 20143, 21098, 22034, 22952, 23852, 24736, 25604, 26455, 27292, 28114, 28922, 29717, 30498, 31267, 32024}; void qm_log10(s32 N , s16 qN , s16 *log10N , s16 *qLog10N ) { s16 s16norm ; s16 s16tableIndex ; s16 s16errorApproximation ; u16 u16offset ; s32 s32log ; u16 tmp ; s16 tmp___0 ; { s16norm = qm_norm32(N); N = N << (int )s16norm; qN = (s16 )((unsigned int )((int )((unsigned short )qN) + (int )((unsigned short )s16norm)) + 65506U); s16tableIndex = (short )(N >> 25); s16tableIndex = (int )s16tableIndex & 31; N = N & 33554431; u16offset = (unsigned short )(N >> 9); s32log = (s32 )log_table[(int )s16tableIndex]; tmp = qm_mulu16((int )u16offset, (int )((unsigned short )log_table[(int )s16tableIndex + 1]) - (int )((unsigned short )log_table[(int )s16tableIndex])); s16errorApproximation = (short )tmp; tmp___0 = qm_add16((int )((short )s32log), (int )s16errorApproximation); s32log = (s32 )tmp___0; s32log = qm_add32(s32log, - ((int )qN) << 15); s16norm = qm_norm32(s32log); s32log = qm_shl32(s32log, (int )s16norm + -16); *log10N = qm_muls16((int )((short )s32log), 19728); *qLog10N = s16norm; return; } } bool ldv_queue_work_on_241(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_242(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_243(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_244(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_245(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } __inline static long ldv__builtin_expect(long exp , long c ) ; extern unsigned long __phys_addr(unsigned long ) ; __inline static unsigned long arch_local_save_flags___1(void) { unsigned long __ret ; unsigned long __edi ; unsigned long __esi ; unsigned long __edx ; unsigned long __ecx ; unsigned long __eax ; long tmp ; { __edi = __edi; __esi = __esi; __edx = __edx; __ecx = __ecx; __eax = __eax; tmp = ldv__builtin_expect((unsigned long )pv_irq_ops.save_fl.func == (unsigned long )((void *)0), 0L); if (tmp != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"./arch/x86/include/asm/paravirt.h"), "i" (831), "i" (12UL)); ldv_4860: ; goto ldv_4860; } else { } __asm__ volatile ("771:\n\tcall *%c2;\n772:\n.pushsection .parainstructions,\"a\"\n .balign 8 \n .quad 771b\n .byte %c1\n .byte 772b-771b\n .short %c3\n.popsection\n": "=a" (__eax): [paravirt_typenum] "i" (43UL), [paravirt_opptr] "i" (& pv_irq_ops.save_fl.func), [paravirt_clobber] "i" (1): "memory", "cc"); __ret = __eax; return (__ret); } } __inline static bool static_key_false___1(struct static_key *key ) { int tmp ; long tmp___0 ; { tmp = static_key_count(key); tmp___0 = ldv__builtin_expect(tmp > 0, 0L); if (tmp___0 != 0L) { return (1); } else { } return (0); } } __inline static int rcu_read_lock_sched_held___1(void) { int lockdep_opinion ; int tmp ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; int tmp___4 ; unsigned long _flags ; int tmp___5 ; int tmp___6 ; { lockdep_opinion = 0; tmp = debug_lockdep_rcu_enabled(); if (tmp == 0) { return (1); } else { } tmp___0 = rcu_is_watching(); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return (0); } else { } tmp___2 = rcu_lockdep_current_cpu_online(); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { return (0); } else { } if (debug_locks != 0) { lockdep_opinion = lock_is_held(& rcu_sched_lock_map); } else { } if (lockdep_opinion != 0) { tmp___6 = 1; } else { tmp___4 = preempt_count(); if (tmp___4 != 0) { tmp___6 = 1; } else { _flags = arch_local_save_flags___1(); tmp___5 = arch_irqs_disabled_flags(_flags); if (tmp___5 != 0) { tmp___6 = 1; } else { tmp___6 = 0; } } } return (tmp___6); } } bool ldv_queue_work_on_255(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_257(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_256(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_259(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_258(struct workqueue_struct *ldv_func_arg1 ) ; __inline static int valid_dma_direction(int dma_direction ) { { return ((dma_direction == 0 || dma_direction == 1) || dma_direction == 2); } } __inline static void kmemcheck_mark_initialized(void *address , unsigned int n ) { { return; } } extern void debug_dma_map_page(struct device * , struct page * , size_t , size_t , int , dma_addr_t , bool ) ; extern void debug_dma_mapping_error(struct device * , dma_addr_t ) ; extern void debug_dma_unmap_page(struct device * , dma_addr_t , size_t , int , bool ) ; extern struct dma_map_ops *dma_ops ; __inline static struct dma_map_ops *get_dma_ops(struct device *dev ) { long tmp ; { tmp = ldv__builtin_expect((unsigned long )dev == (unsigned long )((struct device *)0), 0L); if (tmp != 0L || (unsigned long )dev->archdata.dma_ops == (unsigned long )((struct dma_map_ops *)0)) { return (dma_ops); } else { return (dev->archdata.dma_ops); } } } __inline static dma_addr_t dma_map_single_attrs(struct device *dev , void *ptr , size_t size , enum dma_data_direction dir , struct dma_attrs *attrs ) { struct dma_map_ops *ops ; struct dma_map_ops *tmp ; dma_addr_t addr ; int tmp___0 ; long tmp___1 ; unsigned long tmp___2 ; unsigned long tmp___3 ; { tmp = get_dma_ops(dev); ops = tmp; kmemcheck_mark_initialized(ptr, (unsigned int )size); tmp___0 = valid_dma_direction((int )dir); tmp___1 = ldv__builtin_expect(tmp___0 == 0, 0L); if (tmp___1 != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"include/asm-generic/dma-mapping-common.h"), "i" (19), "i" (12UL)); ldv_26419: ; goto ldv_26419; } else { } tmp___2 = __phys_addr((unsigned long )ptr); addr = (*(ops->map_page))(dev, (struct page *)-24189255811072L + (tmp___2 >> 12), (unsigned long )ptr & 4095UL, size, dir, attrs); tmp___3 = __phys_addr((unsigned long )ptr); debug_dma_map_page(dev, (struct page *)-24189255811072L + (tmp___3 >> 12), (unsigned long )ptr & 4095UL, size, (int )dir, addr, 1); return (addr); } } __inline static void dma_unmap_single_attrs(struct device *dev , dma_addr_t addr , size_t size , enum dma_data_direction dir , struct dma_attrs *attrs ) { struct dma_map_ops *ops ; struct dma_map_ops *tmp ; int tmp___0 ; long tmp___1 ; { tmp = get_dma_ops(dev); ops = tmp; tmp___0 = valid_dma_direction((int )dir); tmp___1 = ldv__builtin_expect(tmp___0 == 0, 0L); if (tmp___1 != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"include/asm-generic/dma-mapping-common.h"), "i" (36), "i" (12UL)); ldv_26428: ; goto ldv_26428; } else { } if ((unsigned long )ops->unmap_page != (unsigned long )((void (*)(struct device * , dma_addr_t , size_t , enum dma_data_direction , struct dma_attrs * ))0)) { (*(ops->unmap_page))(dev, addr, size, dir, attrs); } else { } debug_dma_unmap_page(dev, addr, size, (int )dir, 1); return; } } __inline static int dma_mapping_error(struct device *dev , dma_addr_t dma_addr ) { struct dma_map_ops *ops ; struct dma_map_ops *tmp ; int tmp___0 ; { tmp = get_dma_ops(dev); ops = tmp; debug_dma_mapping_error(dev, dma_addr); if ((unsigned long )ops->mapping_error != (unsigned long )((int (*)(struct device * , dma_addr_t ))0)) { tmp___0 = (*(ops->mapping_error))(dev, dma_addr); return (tmp___0); } else { } return (dma_addr == 0ULL); } } extern void *dma_alloc_attrs(struct device * , size_t , dma_addr_t * , gfp_t , struct dma_attrs * ) ; extern void dma_free_attrs(struct device * , size_t , void * , dma_addr_t , struct dma_attrs * ) ; __inline static void __skb_queue_splice(struct sk_buff_head const *list , struct sk_buff *prev , struct sk_buff *next ) { struct sk_buff *first ; struct sk_buff *last ; { first = list->next; last = list->prev; first->__annonCompField68.__annonCompField67.prev = prev; prev->__annonCompField68.__annonCompField67.next = first; last->__annonCompField68.__annonCompField67.next = next; next->__annonCompField68.__annonCompField67.prev = last; return; } } __inline static void skb_queue_splice_tail(struct sk_buff_head const *list , struct sk_buff_head *head ) { int tmp ; { tmp = skb_queue_empty(list); if (tmp == 0) { __skb_queue_splice(list, head->prev, (struct sk_buff *)head); head->qlen = head->qlen + (__u32 )list->qlen; } else { } return; } } extern struct sk_buff *skb_dequeue(struct sk_buff_head * ) ; extern struct sk_buff *brcmu_pkt_buf_get_skb(uint ) ; void dma_txflush(struct dma_pub *pub ) ; bool dma_txsuspended(struct dma_pub *pub ) ; __inline static void dma_spin_for_len(uint len , struct sk_buff *head ) { { return; } } struct tracepoint __tracepoint_brcms_ampdu_session ; __inline static void trace_brcms_ampdu_session(struct device const *dev , unsigned int max_ampdu_len , u16 max_ampdu_frames , u16 ampdu_len , u16 ampdu_frames , u16 dma_len ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_414 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_416 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___1(& __tracepoint_brcms_ampdu_session.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_ampdu_session.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___1(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_tx.h", 99, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_54970: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct device const * , unsigned int , u16 , u16 , u16 , u16 ))it_func))(__data, dev, max_ampdu_len, (int )max_ampdu_frames, (int )ampdu_len, (int )ampdu_frames, (int )dma_len); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_54970; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_ampdu_session.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___1(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_tx.h", 99, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } static u32 parity32(__le32 data ) { u32 par_data ; { par_data = data; par_data = (par_data >> 16) ^ par_data; par_data = (par_data >> 8) ^ par_data; par_data = (par_data >> 4) ^ par_data; par_data = (par_data >> 2) ^ par_data; par_data = (par_data >> 1) ^ par_data; return (par_data & 1U); } } static bool dma64_dd_parity(struct dma64desc *dd ) { u32 tmp ; { tmp = parity32(((dd->addrlow ^ dd->addrhigh) ^ dd->ctrl1) ^ dd->ctrl2); return (tmp != 0U); } } static uint xxd(uint x , uint n ) { { return ((n - 1U) & x); } } static uint txd(struct dma_info *di , uint x ) { uint tmp ; { tmp = xxd(x, (uint )di->ntxd); return (tmp); } } static uint rxd(struct dma_info *di , uint x ) { uint tmp ; { tmp = xxd(x, (uint )di->nrxd); return (tmp); } } static uint nexttxd(struct dma_info *di , uint i ) { uint tmp ; { tmp = txd(di, i + 1U); return (tmp); } } static uint prevtxd(struct dma_info *di , uint i ) { uint tmp ; { tmp = txd(di, i - 1U); return (tmp); } } static uint nextrxd(struct dma_info *di , uint i ) { uint tmp ; { tmp = rxd(di, i + 1U); return (tmp); } } static uint ntxdactive(struct dma_info *di , uint h , uint t ) { uint tmp ; { tmp = txd(di, t - h); return (tmp); } } static uint nrxdactive(struct dma_info *di , uint h , uint t ) { uint tmp ; { tmp = rxd(di, t - h); return (tmp); } } static uint _dma_ctrlflags(struct dma_info *di , uint mask , uint flags ) { uint dmactrlflags ; u32 control ; u32 tmp ; { if ((unsigned long )di == (unsigned long )((struct dma_info *)0)) { return (0U); } else { } dmactrlflags = di->dma.dmactrlflags; dmactrlflags = ~ mask & dmactrlflags; dmactrlflags = dmactrlflags | flags; if ((int )dmactrlflags & 1) { control = bcma_read32(di->core, (int )((u16 )di->d64txregbase)); bcma_write32(di->core, (int )((u16 )di->d64txregbase), control | 2048U); tmp = bcma_read32(di->core, (int )((u16 )di->d64txregbase)); if ((tmp & 2048U) != 0U) { bcma_write32(di->core, (int )((u16 )di->d64txregbase), control); } else { dmactrlflags = dmactrlflags & 4294967294U; } } else { } di->dma.dmactrlflags = dmactrlflags; return (dmactrlflags); } } static bool _dma64_addrext(struct dma_info *di , uint ctrl_offset ) { u32 w ; { bcma_set32(di->core, (int )((u16 )ctrl_offset), 196608U); w = bcma_read32(di->core, (int )((u16 )ctrl_offset)); bcma_mask32(di->core, (int )((u16 )ctrl_offset), 4294770687U); return ((w & 196608U) == 196608U); } } static bool _dma_isaddrext(struct dma_info *di ) { bool tmp ; int tmp___0 ; bool tmp___1 ; int tmp___2 ; { if (di->d64txregbase != 0U) { tmp = _dma64_addrext(di, di->d64txregbase); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { __brcms_dbg(& (di->core)->dev, 32U, "_dma_isaddrext", "%s: DMA64 tx doesn\'t have AE set\n", (char *)(& di->name)); } else { } return (1); } else if (di->d64rxregbase != 0U) { tmp___1 = _dma64_addrext(di, di->d64rxregbase); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { __brcms_dbg(& (di->core)->dev, 32U, "_dma_isaddrext", "%s: DMA64 rx doesn\'t have AE set\n", (char *)(& di->name)); } else { } return (1); } else { } return (0); } } static bool _dma_descriptor_align(struct dma_info *di ) { u32 addrl ; { if (di->d64txregbase != 0U) { bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 8U), 4080U); addrl = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 8U)); if (addrl != 0U) { return (0); } else { } } else if (di->d64rxregbase != 0U) { bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 8U), 4080U); addrl = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 8U)); if (addrl != 0U) { return (0); } else { } } else { } return (1); } } static void *dma_alloc_consistent(struct dma_info *di , uint size , u16 align_bits , uint *alloced , dma_addr_t *pap ) { u16 align ; void *tmp ; { if ((unsigned int )align_bits != 0U) { align = (u16 )(1 << (int )align_bits); if ((((unsigned long )align - 1UL) & 4096UL) != 0UL) { size = (uint )align + size; } else { } *alloced = size; } else { } tmp = dma_alloc_attrs(di->dmadev, (size_t )size, pap, 32U, (struct dma_attrs *)0); return (tmp); } } static u8 dma_align_sizetobits(uint size ) { u8 bitpos ; { bitpos = 0U; goto ldv_55401; ldv_55400: bitpos = (u8 )((int )bitpos + 1); ldv_55401: size = size >> 1; if (size != 0U) { goto ldv_55400; } else { } return (bitpos); } } static void *dma_ringalloc(struct dma_info *di , u32 boundary , uint size , u16 *alignbits , uint *alloced , dma_addr_t *descpa ) { void *va ; u32 desc_strtaddr ; u32 alignbytes ; u32 __y ; u8 tmp ; { alignbytes = (u32 )(1 << (int )*alignbits); va = dma_alloc_consistent(di, size, (int )*alignbits, alloced, descpa); if ((unsigned long )va == (unsigned long )((void *)0)) { return ((void *)0); } else { } __y = alignbytes; desc_strtaddr = (unsigned int )((((unsigned long )(__y - 1U) + (unsigned long )va) / (unsigned long )__y) * (unsigned long )__y); if (((((desc_strtaddr + size) - 1U) ^ desc_strtaddr) & boundary) != 0U) { tmp = dma_align_sizetobits(size); *alignbits = (u16 )tmp; dma_free_attrs(di->dmadev, (size_t )size, va, *descpa, (struct dma_attrs *)0); va = dma_alloc_consistent(di, size, (int )*alignbits, alloced, descpa); } else { } return (va); } } static bool dma64_alloc(struct dma_info *di , uint direction ) { u16 size ; uint ddlen ; void *va ; uint alloced ; u16 align ; u16 align_bits ; u16 __y ; u16 __y___0 ; { alloced = 0U; ddlen = 16U; size = direction == 1U ? (int )di->ntxd * (int )((u16 )ddlen) : (int )di->nrxd * (int )((u16 )ddlen); align_bits = di->dmadesc_align; align = (u16 )(1 << (int )align_bits); if (direction == 1U) { va = dma_ringalloc(di, 8192U, (uint )size, & align_bits, & alloced, & di->txdpaorig); if ((unsigned long )va == (unsigned long )((void *)0)) { __brcms_dbg(& (di->core)->dev, 32U, "dma64_alloc", "%s: DMA_ALLOC_CONSISTENT(ntxd) failed\n", (char *)(& di->name)); return (0); } else { } align = (u16 )(1 << (int )align_bits); __y = align; di->txd64 = (struct dma64desc *)((((unsigned long )((int )__y + -1) + (unsigned long )va) / (unsigned long )__y) * (unsigned long )__y); di->txdalign = (int )((u16 )((long )di->txd64)) - (int )((u16 )((long )va)); di->txdpa = di->txdpaorig + (dma_addr_t )di->txdalign; di->txdalloc = alloced; } else { va = dma_ringalloc(di, 8192U, (uint )size, & align_bits, & alloced, & di->rxdpaorig); if ((unsigned long )va == (unsigned long )((void *)0)) { __brcms_dbg(& (di->core)->dev, 32U, "dma64_alloc", "%s: DMA_ALLOC_CONSISTENT(nrxd) failed\n", (char *)(& di->name)); return (0); } else { } align = (u16 )(1 << (int )align_bits); __y___0 = align; di->rxd64 = (struct dma64desc *)((((unsigned long )((int )__y___0 + -1) + (unsigned long )va) / (unsigned long )__y___0) * (unsigned long )__y___0); di->rxdalign = (int )((u16 )((long )di->rxd64)) - (int )((u16 )((long )va)); di->rxdpa = di->rxdpaorig + (dma_addr_t )di->rxdalign; di->rxdalloc = alloced; } return (1); } } static bool _dma_alloc(struct dma_info *di , uint direction ) { bool tmp ; { tmp = dma64_alloc(di, direction); return (tmp); } } struct dma_pub *dma_attach(char *name , struct brcms_c_info *wlc , uint txregbase , uint rxregbase , uint ntxd , uint nrxd , uint rxbufsize , int rxextheadroom , uint nrxpost , uint rxoffset ) { struct si_pub *sih ; struct bcma_device *core ; struct dma_info *di ; u8 rev ; uint size ; struct si_info *sii ; struct si_pub const *__mptr ; void *tmp ; u32 tmp___0 ; void *tmp___1 ; void *tmp___2 ; bool tmp___3 ; int tmp___4 ; bool tmp___5 ; int tmp___6 ; { sih = (wlc->hw)->sih; core = (wlc->hw)->d11core; rev = core->id.rev; __mptr = (struct si_pub const *)sih; sii = (struct si_info *)__mptr; tmp = kzalloc(328UL, 32U); di = (struct dma_info *)tmp; if ((unsigned long )di == (unsigned long )((struct dma_info *)0)) { return ((struct dma_pub *)0); } else { } tmp___0 = bcma_aread32(core, 1280); di->dma64 = (tmp___0 & 4096U) != 0U; di->core = core; di->d64txregbase = txregbase; di->d64rxregbase = rxregbase; _dma_ctrlflags(di, 3U, 0U); __brcms_dbg(& (di->core)->dev, 32U, "dma_attach", "%s: %s flags 0x%x ntxd %d nrxd %d rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d txregbase %u rxregbase %u\n", name, (char *)"DMA64", di->dma.dmactrlflags, ntxd, nrxd, rxbufsize, rxextheadroom, nrxpost, rxoffset, txregbase, rxregbase); strncpy((char *)(& di->name), (char const *)name, 8UL); di->name[7] = 0; di->dmadev = core->dma_dev; di->ntxd = (unsigned short )ntxd; di->nrxd = (unsigned short )nrxd; di->rxextrahdrroom = rxextheadroom != -1 ? (uint )rxextheadroom : 172U; if (rxbufsize > 172U) { di->rxbufsize = (unsigned int )((int )((unsigned short )rxbufsize) - (int )((unsigned short )di->rxextrahdrroom)); } else { di->rxbufsize = (unsigned int )((unsigned short )rxbufsize); } di->nrxpost = (uint )((unsigned short )nrxpost); di->rxoffset = (unsigned int )((unsigned char )rxoffset); di->ddoffsetlow = 0U; di->dataoffsetlow = 0U; if ((unsigned int )(sii->icbus)->hosttype == 0U) { di->ddoffsetlow = 0U; di->ddoffsethigh = 2147483648U; } else { } di->dataoffsetlow = di->ddoffsetlow; di->dataoffsethigh = di->ddoffsethigh; if ((unsigned int )core->id.id == 2089U && ((unsigned int )rev != 0U && (unsigned int )rev <= 2U)) { di->addrext = 0; } else if ((unsigned int )core->id.id == 2100U && ((unsigned int )rev == 0U || (unsigned int )rev == 1U)) { di->addrext = 0; } else { di->addrext = _dma_isaddrext(di); } di->aligndesc_4k = _dma_descriptor_align(di); if ((int )di->aligndesc_4k) { di->dmadesc_align = 13U; if (ntxd <= 255U && nrxd <= 255U) { di->dmadesc_align = 12U; } else { } } else { di->dmadesc_align = 4U; } __brcms_dbg(& (di->core)->dev, 32U, "dma_attach", "DMA descriptor align_needed %d, align %d\n", (int )di->aligndesc_4k, (int )di->dmadesc_align); if (ntxd != 0U) { size = ntxd * 8U; tmp___1 = kzalloc((size_t )size, 32U); di->txp = (struct sk_buff **)tmp___1; if ((unsigned long )di->txp == (unsigned long )((struct sk_buff **)0)) { goto fail; } else { } } else { } if (nrxd != 0U) { size = nrxd * 8U; tmp___2 = kzalloc((size_t )size, 32U); di->rxp = (struct sk_buff **)tmp___2; if ((unsigned long )di->rxp == (unsigned long )((struct sk_buff **)0)) { goto fail; } else { } } else { } if (ntxd != 0U) { tmp___3 = _dma_alloc(di, 1U); if (tmp___3) { tmp___4 = 0; } else { tmp___4 = 1; } if (tmp___4) { goto fail; } else { } } else { } if (nrxd != 0U) { tmp___5 = _dma_alloc(di, 2U); if (tmp___5) { tmp___6 = 0; } else { tmp___6 = 1; } if (tmp___6) { goto fail; } else { } } else { } if (di->ddoffsetlow != 0U && ! di->addrext) { if (di->txdpa > 1073741824ULL) { __brcms_dbg(& (di->core)->dev, 32U, "dma_attach", "%s: txdpa 0x%x: addrext not supported\n", (char *)(& di->name), (unsigned int )di->txdpa); goto fail; } else { } if (di->rxdpa > 1073741824ULL) { __brcms_dbg(& (di->core)->dev, 32U, "dma_attach", "%s: rxdpa 0x%x: addrext not supported\n", (char *)(& di->name), (unsigned int )di->rxdpa); goto fail; } else { } } else { } brcms_c_ampdu_reset_session(& di->ampdu_session, wlc); __brcms_dbg(& (di->core)->dev, 32U, "dma_attach", "ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x dataoffsethigh 0x%x addrext %d\n", di->ddoffsetlow, di->ddoffsethigh, di->dataoffsetlow, di->dataoffsethigh, (int )di->addrext); return ((struct dma_pub *)di); fail: dma_detach((struct dma_pub *)di); return ((struct dma_pub *)0); } } __inline static void dma64_dd_upd(struct dma_info *di , struct dma64desc *ddring , dma_addr_t pa , uint outidx , u32 *flags , u32 bufcount ) { u32 ctrl2 ; u32 ae ; bool tmp ; { ctrl2 = bufcount & 32767U; if (di->dataoffsetlow == 0U || (pa & 3221225472ULL) == 0ULL) { (ddring + (unsigned long )outidx)->addrlow = (unsigned int )pa + di->dataoffsetlow; (ddring + (unsigned long )outidx)->addrhigh = di->dataoffsethigh; (ddring + (unsigned long )outidx)->ctrl1 = *flags; (ddring + (unsigned long )outidx)->ctrl2 = ctrl2; } else { ae = (u32 )((pa & 3221225472ULL) >> 30); pa = pa & 1073741823ULL; ctrl2 = ((ae << 16) & 196608U) | ctrl2; (ddring + (unsigned long )outidx)->addrlow = (unsigned int )pa + di->dataoffsetlow; (ddring + (unsigned long )outidx)->addrhigh = di->dataoffsethigh; (ddring + (unsigned long )outidx)->ctrl1 = *flags; (ddring + (unsigned long )outidx)->ctrl2 = ctrl2; } if ((int )di->dma.dmactrlflags & 1) { tmp = dma64_dd_parity(ddring + (unsigned long )outidx); if ((int )tmp) { (ddring + (unsigned long )outidx)->ctrl2 = ctrl2 | 262144U; } else { } } else { } return; } } void dma_detach(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; __brcms_dbg(& (di->core)->dev, 32U, "dma_detach", "%s:\n", (char *)(& di->name)); if ((unsigned long )di->txd64 != (unsigned long )((struct dma64desc *)0)) { dma_free_attrs(di->dmadev, (size_t )di->txdalloc, (void *)di->txd64 + - ((unsigned long )di->txdalign), di->txdpaorig, (struct dma_attrs *)0); } else { } if ((unsigned long )di->rxd64 != (unsigned long )((struct dma64desc *)0)) { dma_free_attrs(di->dmadev, (size_t )di->rxdalloc, (void *)di->rxd64 + - ((unsigned long )di->rxdalign), di->rxdpaorig, (struct dma_attrs *)0); } else { } kfree((void const *)di->txp); kfree((void const *)di->rxp); kfree((void const *)di); return; } } static void _dma_ddtable_init(struct dma_info *di , uint direction , dma_addr_t pa ) { u32 ae ; { if (! di->aligndesc_4k) { if (direction == 1U) { di->xmtptrbase = (u32 )pa; } else { di->rcvptrbase = (u32 )pa; } } else { } if (di->ddoffsetlow == 0U || (pa & 3221225472ULL) == 0ULL) { if (direction == 1U) { bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 8U), di->ddoffsetlow + (u32 )pa); bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 12U), di->ddoffsethigh); } else { bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 8U), di->ddoffsetlow + (u32 )pa); bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 12U), di->ddoffsethigh); } } else { ae = (u32 )((pa & 3221225472ULL) >> 30); pa = pa & 1073741823ULL; if (direction == 1U) { bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 8U), di->ddoffsetlow + (u32 )pa); bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 12U), di->ddoffsethigh); bcma_maskset32(di->core, (int )((u16 )di->d64txregbase), 196608U, ae << 16); } else { bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 8U), di->ddoffsetlow + (u32 )pa); bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 12U), di->ddoffsethigh); bcma_maskset32(di->core, (int )((u16 )di->d64rxregbase), 196608U, ae << 16); } } return; } } static void _dma_rxenable(struct dma_info *di ) { uint dmactrlflags ; u32 control ; u32 tmp ; { dmactrlflags = di->dma.dmactrlflags; __brcms_dbg(& (di->core)->dev, 32U, "_dma_rxenable", "%s:\n", (char *)(& di->name)); tmp = bcma_read32(di->core, (int )((u16 )di->d64rxregbase)); control = (tmp & 196608U) | 1U; if ((dmactrlflags & 1U) == 0U) { control = control | 2048U; } else { } if ((dmactrlflags & 2U) != 0U) { control = control | 1024U; } else { } bcma_write32(di->core, (int )((u16 )di->d64rxregbase), (di->rxoffset << 1) | control); return; } } void dma_rxinit(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; u16 tmp ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; __brcms_dbg(& (di->core)->dev, 32U, "dma_rxinit", "%s:\n", (char *)(& di->name)); if ((unsigned int )di->nrxd == 0U) { return; } else { } tmp = 0U; di->rxout = tmp; di->rxin = tmp; memset((void *)di->rxd64, 0, (unsigned long )di->nrxd * 16UL); if (! di->aligndesc_4k) { _dma_ddtable_init(di, 2U, di->rxdpa); } else { } _dma_rxenable(di); if ((int )di->aligndesc_4k) { _dma_ddtable_init(di, 2U, di->rxdpa); } else { } return; } } static struct sk_buff *dma64_getnextrxp(struct dma_info *di , bool forceall ) { uint i ; uint curr ; struct sk_buff *rxp ; dma_addr_t pa ; u32 tmp ; uint tmp___0 ; { i = (uint )di->rxin; if ((uint )di->rxout == i) { return ((struct sk_buff *)0); } else { } tmp = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 16U)); curr = (uint )(((unsigned long )((tmp & 8191U) - di->rcvptrbase) & 8191UL) / 16UL); if (! forceall && i == curr) { return ((struct sk_buff *)0); } else { } rxp = *(di->rxp + (unsigned long )i); *(di->rxp + (unsigned long )i) = (struct sk_buff *)0; pa = (dma_addr_t )((di->rxd64 + (unsigned long )i)->addrlow - di->dataoffsetlow); dma_unmap_single_attrs(di->dmadev, pa, (size_t )di->rxbufsize, 2, (struct dma_attrs *)0); (di->rxd64 + (unsigned long )i)->addrlow = 3735928559U; (di->rxd64 + (unsigned long )i)->addrhigh = 3735928559U; tmp___0 = nextrxd(di, i); di->rxin = (u16 )tmp___0; return (rxp); } } static struct sk_buff *_dma_getnextrxp(struct dma_info *di , bool forceall ) { struct sk_buff *tmp ; { if ((unsigned int )di->nrxd == 0U) { return ((struct sk_buff *)0); } else { } tmp = dma64_getnextrxp(di, (int )forceall); return (tmp); } } int dma_rx(struct dma_pub *pub , struct sk_buff_head *skb_list ) { struct dma_info *di ; struct dma_pub const *__mptr ; struct sk_buff_head dma_frames ; struct sk_buff *p ; struct sk_buff *next ; uint len ; uint pkt_len ; int resid ; int pktcnt ; unsigned int _min1 ; unsigned int _min2 ; uint __min1 ; uint __min2 ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; resid = 0; pktcnt = 1; skb_queue_head_init(& dma_frames); next_frame: p = _dma_getnextrxp(di, 0); if ((unsigned long )p == (unsigned long )((struct sk_buff *)0)) { return (0); } else { } len = (uint )*((__le16 *)p->data); __brcms_dbg(& (di->core)->dev, 32U, "dma_rx", "%s: dma_rx len %d\n", (char *)(& di->name), len); dma_spin_for_len(len, p); _min1 = di->rxoffset + len; _min2 = di->rxbufsize; pkt_len = _min1 < _min2 ? _min1 : _min2; __skb_trim(p, pkt_len); skb_queue_tail(& dma_frames, p); resid = (int )((di->rxoffset - di->rxbufsize) + len); if (resid > 0) { goto ldv_55528; ldv_55527: __min1 = (uint )resid; __min2 = di->rxbufsize; pkt_len = __min1 < __min2 ? __min1 : __min2; __skb_trim(p, pkt_len); skb_queue_tail(& dma_frames, p); resid = (int )((unsigned int )resid - di->rxbufsize); pktcnt = pktcnt + 1; ldv_55528: ; if (resid > 0) { p = _dma_getnextrxp(di, 0); if ((unsigned long )p != (unsigned long )((struct sk_buff *)0)) { goto ldv_55527; } else { goto ldv_55529; } } else { } ldv_55529: ; if ((di->dma.dmactrlflags & 4U) == 0U) { __brcms_dbg(& (di->core)->dev, 32U, "dma_rx", "%s: bad frame length (%d)\n", (char *)(& di->name), len); p = dma_frames.next; next = p->__annonCompField68.__annonCompField67.next; goto ldv_55531; ldv_55530: skb_unlink(p, & dma_frames); brcmu_pkt_buf_free_skb(p); p = next; next = p->__annonCompField68.__annonCompField67.next; ldv_55531: ; if ((unsigned long )((struct sk_buff *)(& dma_frames)) != (unsigned long )p) { goto ldv_55530; } else { } di->dma.rxgiants = di->dma.rxgiants + 1U; pktcnt = 1; goto next_frame; } else { } } else { } skb_queue_splice_tail((struct sk_buff_head const *)(& dma_frames), skb_list); return (pktcnt); } } static bool dma64_rxidle(struct dma_info *di ) { u32 tmp ; u32 tmp___0 ; { __brcms_dbg(& (di->core)->dev, 32U, "dma64_rxidle", "%s:\n", (char *)(& di->name)); if ((unsigned int )di->nrxd == 0U) { return (1); } else { } tmp = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 16U)); tmp___0 = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 4U)); return (((tmp ^ tmp___0) & 8191U) == 0U); } } static bool dma64_txidle(struct dma_info *di ) { u32 tmp ; u32 tmp___0 ; { if ((unsigned int )di->ntxd == 0U) { return (1); } else { } tmp = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 16U)); tmp___0 = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 4U)); return (((tmp ^ tmp___0) & 8191U) == 0U); } } bool dma_rxfill(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; struct sk_buff *p ; u16 rxin ; u16 rxout ; u32 flags ; uint n ; uint i ; dma_addr_t pa ; uint extra_offset ; bool ring_empty ; uint tmp ; bool tmp___0 ; int tmp___1 ; uint tmp___2 ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; flags = 0U; extra_offset = 0U; ring_empty = 0; rxin = di->rxin; rxout = di->rxout; tmp = nrxdactive(di, (uint )rxin, (uint )rxout); n = di->nrxpost - tmp; __brcms_dbg(& (di->core)->dev, 32U, "dma_rxfill", "%s: post %d\n", (char *)(& di->name), n); if (di->rxbufsize > 172U) { extra_offset = di->rxextrahdrroom; } else { } i = 0U; goto ldv_55558; ldv_55557: p = brcmu_pkt_buf_get_skb(di->rxbufsize + extra_offset); if ((unsigned long )p == (unsigned long )((struct sk_buff *)0)) { __brcms_dbg(& (di->core)->dev, 32U, "dma_rxfill", "%s: out of rxbufs\n", (char *)(& di->name)); if (i == 0U) { tmp___0 = dma64_rxidle(di); if ((int )tmp___0) { __brcms_dbg(& (di->core)->dev, 32U, "dma_rxfill", "%s: ring is empty !\n", (char *)(& di->name)); ring_empty = 1; } else { } } else { } di->dma.rxnobuf = di->dma.rxnobuf + 1U; goto ldv_55556; } else { } if (extra_offset != 0U) { skb_pull(p, extra_offset); } else { } *((u32 *)p->data) = 0U; pa = dma_map_single_attrs(di->dmadev, (void *)p->data, (size_t )di->rxbufsize, 2, (struct dma_attrs *)0); tmp___1 = dma_mapping_error(di->dmadev, pa); if (tmp___1 != 0) { return (0); } else { } *(di->rxp + (unsigned long )rxout) = p; flags = 0U; if ((int )rxout == (int )di->nrxd + -1) { flags = 268435456U; } else { } dma64_dd_upd(di, di->rxd64, pa, (uint )rxout, & flags, di->rxbufsize); tmp___2 = nextrxd(di, (uint )rxout); rxout = (u16 )tmp___2; i = i + 1U; ldv_55558: ; if (i < n) { goto ldv_55557; } else { } ldv_55556: di->rxout = rxout; bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 4U), di->rcvptrbase + (u32 )rxout * 16U); return (ring_empty); } } void dma_rxreclaim(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; struct sk_buff *p ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; __brcms_dbg(& (di->core)->dev, 32U, "dma_rxreclaim", "%s:\n", (char *)(& di->name)); goto ldv_55568; ldv_55567: brcmu_pkt_buf_free_skb(p); ldv_55568: p = _dma_getnextrxp(di, 1); if ((unsigned long )p != (unsigned long )((struct sk_buff *)0)) { goto ldv_55567; } else { } return; } } void dma_counterreset(struct dma_pub *pub ) { { pub->rxgiants = 0U; pub->rxnobuf = 0U; pub->txnobuf = 0U; return; } } unsigned long dma_getvar(struct dma_pub *pub , char const *name ) { struct dma_info *di ; struct dma_pub const *__mptr ; int tmp ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; tmp = strcmp(name, "&txavail"); if (tmp == 0) { return ((unsigned long )(& di->dma.txavail)); } else { } return (0UL); } } void dma_txinit(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; u32 control ; u16 tmp ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; control = 1U; __brcms_dbg(& (di->core)->dev, 32U, "dma_txinit", "%s:\n", (char *)(& di->name)); if ((unsigned int )di->ntxd == 0U) { return; } else { } tmp = 0U; di->txout = tmp; di->txin = tmp; di->dma.txavail = (uint )((int )di->ntxd + -1); memset((void *)di->txd64, 0, (unsigned long )di->ntxd * 16UL); if (! di->aligndesc_4k) { _dma_ddtable_init(di, 1U, di->txdpa); } else { } if ((di->dma.dmactrlflags & 1U) == 0U) { control = control | 2048U; } else { } bcma_set32(di->core, (int )((u16 )di->d64txregbase), control); if ((int )di->aligndesc_4k) { _dma_ddtable_init(di, 1U, di->txdpa); } else { } return; } } void dma_txsuspend(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; __brcms_dbg(& (di->core)->dev, 32U, "dma_txsuspend", "%s:\n", (char *)(& di->name)); if ((unsigned int )di->ntxd == 0U) { return; } else { } bcma_set32(di->core, (int )((u16 )di->d64txregbase), 2U); return; } } void dma_txresume(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; __brcms_dbg(& (di->core)->dev, 32U, "dma_txresume", "%s:\n", (char *)(& di->name)); if ((unsigned int )di->ntxd == 0U) { return; } else { } bcma_mask32(di->core, (int )((u16 )di->d64txregbase), 4294967293U); return; } } bool dma_txsuspended(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; u32 tmp ; int tmp___0 ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; if ((unsigned int )di->ntxd == 0U) { tmp___0 = 1; } else { tmp = bcma_read32(di->core, (int )((u16 )di->d64txregbase)); if ((tmp & 2U) != 0U) { tmp___0 = 1; } else { tmp___0 = 0; } } return ((bool )tmp___0); } } void dma_txreclaim(struct dma_pub *pub , enum txd_range range ) { struct dma_info *di ; struct dma_pub const *__mptr ; struct sk_buff *p ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; __brcms_dbg(& (di->core)->dev, 32U, "dma_txreclaim", "%s: %s\n", (char *)(& di->name), (unsigned int )range != 1U ? ((unsigned int )range == 2U ? (char *)"transmitted" : (char *)"transferred") : (char *)"all"); if ((int )di->txin == (int )di->txout) { return; } else { } goto ldv_55618; ldv_55617: ; if ((di->dma.dmactrlflags & 8U) == 0U) { brcmu_pkt_buf_free_skb(p); } else { } ldv_55618: p = dma_getnexttxp(pub, range); if ((unsigned long )p != (unsigned long )((struct sk_buff *)0)) { goto ldv_55617; } else { } return; } } bool dma_txreset(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; u32 status ; uint countdown ; u32 tmp ; uint countdown___0 ; u32 tmp___0 ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; if ((unsigned int )di->ntxd == 0U) { return (1); } else { } bcma_write32(di->core, (int )((u16 )di->d64txregbase), 2U); countdown = 10009U; goto ldv_55629; ldv_55628: __const_udelay(42950UL); countdown = countdown - 10U; ldv_55629: tmp = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 16U)); status = tmp & 4026531840U; if (((status != 0U && status != 536870912U) && status != 805306368U) && countdown > 9U) { goto ldv_55628; } else { } bcma_write32(di->core, (int )((u16 )di->d64txregbase), 0U); countdown___0 = 10009U; goto ldv_55633; ldv_55632: __const_udelay(42950UL); countdown___0 = countdown___0 - 10U; ldv_55633: tmp___0 = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 16U)); status = tmp___0 & 4026531840U; if (status != 0U && countdown___0 > 9U) { goto ldv_55632; } else { } __const_udelay(1288500UL); return (status == 0U); } } bool dma_rxreset(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; u32 status ; uint countdown ; u32 tmp ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; if ((unsigned int )di->nrxd == 0U) { return (1); } else { } bcma_write32(di->core, (int )((u16 )di->d64rxregbase), 0U); countdown = 10009U; goto ldv_55644; ldv_55643: __const_udelay(42950UL); countdown = countdown - 10U; ldv_55644: tmp = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64rxregbase) + 16U)); status = tmp & 4026531840U; if (status != 0U && countdown > 9U) { goto ldv_55643; } else { } return (status == 0U); } } static void dma_txenq(struct dma_info *di , struct sk_buff *p ) { unsigned char *data ; uint len ; u16 txout ; u32 flags ; dma_addr_t pa ; int __ret_warn_on ; uint tmp ; long tmp___0 ; long tmp___1 ; int tmp___2 ; uint tmp___3 ; uint tmp___4 ; { flags = 0U; txout = di->txout; tmp = nexttxd(di, (uint )txout); __ret_warn_on = tmp == (uint )di->txin; tmp___0 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___0 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/dma.c", 1279); } else { } tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { return; } else { } data = p->data; len = p->len; pa = dma_map_single_attrs(di->dmadev, (void *)data, (size_t )len, 1, (struct dma_attrs *)0); tmp___2 = dma_mapping_error(di->dmadev, pa); if (tmp___2 != 0) { brcmu_pkt_buf_free_skb(p); return; } else { } flags = 3758096384U; if ((int )txout == (int )di->ntxd + -1) { flags = flags | 268435456U; } else { } dma64_dd_upd(di, di->txd64, pa, (uint )txout, & flags, len); tmp___3 = nexttxd(di, (uint )txout); txout = (u16 )tmp___3; tmp___4 = prevtxd(di, (uint )txout); *(di->txp + (unsigned long )tmp___4) = p; di->txout = txout; return; } } static void ampdu_finalize(struct dma_info *di ) { struct brcms_ampdu_session *session ; struct sk_buff *p ; __u32 tmp ; int __ret_warn_on ; int tmp___0 ; long tmp___1 ; long tmp___2 ; int tmp___3 ; { session = & di->ampdu_session; tmp = skb_queue_len((struct sk_buff_head const *)(& session->skb_list)); trace_brcms_ampdu_session((struct device const *)(& (((session->wlc)->hw)->d11core)->dev), session->max_ampdu_len, (int )session->max_ampdu_frames, (int )session->ampdu_len, (int )((u16 )tmp), (int )session->dma_len); tmp___0 = skb_queue_empty((struct sk_buff_head const *)(& session->skb_list)); __ret_warn_on = tmp___0 != 0; tmp___1 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___1 != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/dma.c", 1327); } else { } tmp___2 = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp___2 != 0L) { return; } else { } brcms_c_ampdu_finalize(session); goto ldv_55665; ldv_55664: p = skb_dequeue(& session->skb_list); dma_txenq(di, p); ldv_55665: tmp___3 = skb_queue_empty((struct sk_buff_head const *)(& session->skb_list)); if (tmp___3 == 0) { goto ldv_55664; } else { } bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 4U), di->xmtptrbase + (u32 )di->txout * 16U); brcms_c_ampdu_reset_session(session, session->wlc); return; } } static void prep_ampdu_frame(struct dma_info *di , struct sk_buff *p ) { struct brcms_ampdu_session *session ; int ret ; int __ret_warn_on ; long tmp ; { session = & di->ampdu_session; ret = brcms_c_ampdu_add_frame(session, p); if (ret == -28) { ampdu_finalize(di); ret = brcms_c_ampdu_add_frame(session, p); } else { } __ret_warn_on = ret != 0; tmp = ldv__builtin_expect(__ret_warn_on != 0, 0L); if (tmp != 0L) { warn_slowpath_null("/work/ldvuser/mutilin/launch/work/current--X--drivers/--X--defaultlinux-4.2-rc1.tar.xz--X--08_1a--X--cpachecker/linux-4.2-rc1.tar.xz/csd_deg_dscv/11786/dscv_tempdir/dscv/ri/08_1a/drivers/net/wireless/brcm80211/brcmsmac/dma.c", 1357); } else { } ldv__builtin_expect(__ret_warn_on != 0, 0L); return; } } static void dma_update_txavail(struct dma_info *di ) { uint tmp ; __u32 tmp___0 ; { tmp = ntxdactive(di, (uint )di->txin, (uint )di->txout); tmp___0 = skb_queue_len((struct sk_buff_head const *)(& di->ampdu_session.skb_list)); di->dma.txavail = (((uint )di->ntxd - tmp) - tmp___0) - 1U; return; } } int dma_txfast(struct brcms_c_info *wlc , struct dma_pub *pub , struct sk_buff *p ) { struct dma_info *di ; struct dma_pub const *__mptr ; struct brcms_ampdu_session *session ; struct ieee80211_tx_info *tx_info ; bool is_ampdu ; uint tmp ; __u32 tmp___0 ; bool tmp___1 ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; session = & di->ampdu_session; if (p->len == 0U) { return (0); } else { } if (di->dma.txavail == 0U) { goto outoftxd; } else { tmp = nexttxd(di, (uint )di->txout); if (tmp == (uint )di->txin) { goto outoftxd; } else { } } tx_info = IEEE80211_SKB_CB(p); is_ampdu = (tx_info->flags & 64U) != 0U; if ((int )is_ampdu) { prep_ampdu_frame(di, p); } else { dma_txenq(di, p); } dma_update_txavail(di); if ((int )is_ampdu) { tmp___0 = skb_queue_len((struct sk_buff_head const *)(& session->skb_list)); if (tmp___0 == (__u32 )session->max_ampdu_frames || di->dma.txavail == 0U) { ampdu_finalize(di); } else { tmp___1 = dma64_txidle(di); if ((int )tmp___1) { ampdu_finalize(di); } else { } } } else { bcma_write32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 4U), di->xmtptrbase + (u32 )di->txout * 16U); } return (0); outoftxd: __brcms_dbg(& (di->core)->dev, 32U, "dma_txfast", "%s: out of txds !!!\n", (char *)(& di->name)); brcmu_pkt_buf_free_skb(p); di->dma.txavail = 0U; di->dma.txnobuf = di->dma.txnobuf + 1U; return (-28); } } void dma_txflush(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; struct brcms_ampdu_session *session ; int tmp ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; session = & di->ampdu_session; tmp = skb_queue_empty((struct sk_buff_head const *)(& session->skb_list)); if (tmp == 0) { ampdu_finalize(di); } else { } return; } } int dma_txpending(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; uint tmp ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; tmp = ntxdactive(di, (uint )di->txin, (uint )di->txout); return ((int )tmp); } } void dma_kick_tx(struct dma_pub *pub ) { struct dma_info *di ; struct dma_pub const *__mptr ; struct brcms_ampdu_session *session ; int tmp ; bool tmp___0 ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; session = & di->ampdu_session; tmp = skb_queue_empty((struct sk_buff_head const *)(& session->skb_list)); if (tmp == 0) { tmp___0 = dma64_txidle(di); if ((int )tmp___0) { ampdu_finalize(di); } else { } } else { } return; } } struct sk_buff *dma_getnexttxp(struct dma_pub *pub , enum txd_range range ) { struct dma_info *di ; struct dma_pub const *__mptr ; u16 start ; u16 end ; u16 i ; u16 active_desc ; struct sk_buff *txp ; u32 tmp ; u32 tmp___0 ; uint tmp___1 ; dma_addr_t pa ; uint size ; uint tmp___2 ; { __mptr = (struct dma_pub const *)pub; di = (struct dma_info *)__mptr; __brcms_dbg(& (di->core)->dev, 32U, "dma_getnexttxp", "%s: %s\n", (char *)(& di->name), (unsigned int )range != 1U ? ((unsigned int )range == 2U ? (char *)"transmitted" : (char *)"transferred") : (char *)"all"); if ((unsigned int )di->ntxd == 0U) { return ((struct sk_buff *)0); } else { } txp = (struct sk_buff *)0; start = di->txin; if ((unsigned int )range == 1U) { end = di->txout; } else { tmp = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 16U)); end = (unsigned short )(((unsigned long )((tmp & 8191U) - di->xmtptrbase) & 8191UL) / 16UL); if ((unsigned int )range == 3U) { tmp___0 = bcma_read32(di->core, (int )((unsigned int )((u16 )di->d64txregbase) + 20U)); active_desc = (unsigned int )((unsigned short )tmp___0) & 8191U; active_desc = (unsigned int )((int )active_desc - (int )((u16 )di->xmtptrbase)) & 8191U; active_desc = (u16 )((unsigned int )active_desc / 16U); if ((int )end != (int )active_desc) { tmp___1 = prevtxd(di, (uint )active_desc); end = (u16 )tmp___1; } else { } } else { } } if ((unsigned int )start == 0U && (int )di->txout < (int )end) { goto bogus; } else { } i = start; goto ldv_55728; ldv_55727: pa = (dma_addr_t )((di->txd64 + (unsigned long )i)->addrlow - di->dataoffsetlow); size = (di->txd64 + (unsigned long )i)->ctrl2 & 32767U; (di->txd64 + (unsigned long )i)->addrlow = 3735928559U; (di->txd64 + (unsigned long )i)->addrhigh = 3735928559U; txp = *(di->txp + (unsigned long )i); *(di->txp + (unsigned long )i) = (struct sk_buff *)0; dma_unmap_single_attrs(di->dmadev, pa, (size_t )size, 1, (struct dma_attrs *)0); tmp___2 = nexttxd(di, (uint )i); i = (u16 )tmp___2; ldv_55728: ; if ((int )i != (int )end && (unsigned long )txp == (unsigned long )((struct sk_buff *)0)) { goto ldv_55727; } else { } di->txin = i; dma_update_txavail(di); return (txp); bogus: __brcms_dbg(& (di->core)->dev, 32U, "dma_getnexttxp", "bogus curr: start %d end %d txout %d\n", (int )start, (int )end, (int )di->txout); return ((struct sk_buff *)0); } } void dma_walk_packets(struct dma_pub *dmah , void (*callback_fnc)(void * , void * ) , void *arg_a ) { struct dma_info *di ; struct dma_pub const *__mptr ; uint i ; uint end ; struct sk_buff *skb ; struct ieee80211_tx_info *tx_info ; { __mptr = (struct dma_pub const *)dmah; di = (struct dma_info *)__mptr; i = (uint )di->txin; end = (uint )di->txout; goto ldv_55745; ldv_55744: skb = *(di->txp + (unsigned long )i); if ((unsigned long )skb != (unsigned long )((struct sk_buff *)0)) { tx_info = (struct ieee80211_tx_info *)(& skb->cb); (*callback_fnc)((void *)tx_info, arg_a); } else { } i = nexttxd(di, i); ldv_55745: ; if (i != end) { goto ldv_55744; } else { } return; } } bool ldv_queue_work_on_255(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_256(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_257(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_258(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_259(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_269(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_271(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_270(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_273(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_272(struct workqueue_struct *ldv_func_arg1 ) ; struct tracepoint __tracepoint_brcms_timer ; struct tracepoint __tracepoint_brcms_dpc ; static char const __tpstrtab_brcms_timer[12U] = { 'b', 'r', 'c', 'm', 's', '_', 't', 'i', 'm', 'e', 'r', '\000'}; struct tracepoint __tracepoint_brcms_timer = {(char const *)(& __tpstrtab_brcms_timer), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static char const __tpstrtab_brcms_dpc[10U] = { 'b', 'r', 'c', 'm', 's', '_', 'd', 'p', 'c', '\000'}; struct tracepoint __tracepoint_brcms_dpc = {(char const *)(& __tpstrtab_brcms_dpc), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static char const __tpstrtab_brcms_macintstatus[19U] = { 'b', 'r', 'c', 'm', 's', '_', 'm', 'a', 'c', 'i', 'n', 't', 's', 't', 'a', 't', 'u', 's', '\000'}; struct tracepoint __tracepoint_brcms_macintstatus = {(char const *)(& __tpstrtab_brcms_macintstatus), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; __inline static bool seq_buf_has_overflowed(struct seq_buf *s ) { { return (s->len > s->size); } } __inline static bool trace_seq_has_overflowed(struct trace_seq *s ) { bool tmp ; int tmp___0 ; { if (s->full != 0) { tmp___0 = 1; } else { tmp = seq_buf_has_overflowed(& s->seq); if ((int )tmp) { tmp___0 = 1; } else { tmp___0 = 0; } } return ((bool )tmp___0); } } extern void trace_seq_printf(struct trace_seq * , char const * , ...) ; extern int trace_raw_output_prep(struct trace_iterator * , struct trace_event * ) ; __inline static enum print_line_t trace_handle_return(struct trace_seq *s ) { bool tmp ; { tmp = trace_seq_has_overflowed(s); return ((int )tmp ? 0 : 1); } } extern int trace_event_reg(struct trace_event_call * , enum trace_reg , void * ) ; extern int trace_event_raw_init(struct trace_event_call * ) ; extern int trace_define_field(struct trace_event_call * , char const * , char const * , int , int , int , int ) ; static enum print_line_t trace_raw_output_brcms_timer(struct trace_iterator *iter , int flags , struct trace_event *trace_event ) { struct trace_seq *s ; struct trace_seq *p ; struct trace_event_raw_brcms_timer *field ; int ret ; enum print_line_t tmp ; { s = & iter->seq; p = & iter->tmp_seq; field = (struct trace_event_raw_brcms_timer *)iter->ent; ret = trace_raw_output_prep(iter, trace_event); if (ret != 1) { return ((enum print_line_t )ret); } else { } trace_seq_printf(s, "ms=%u set=%u periodic=%u\n", field->ms, field->set, field->periodic); tmp = trace_handle_return(s); return (tmp); } } static enum print_line_t trace_raw_output_brcms_dpc(struct trace_iterator *iter , int flags , struct trace_event *trace_event ) { struct trace_seq *s ; struct trace_seq *p ; struct trace_event_raw_brcms_dpc *field ; int ret ; enum print_line_t tmp ; { s = & iter->seq; p = & iter->tmp_seq; field = (struct trace_event_raw_brcms_dpc *)iter->ent; ret = trace_raw_output_prep(iter, trace_event); if (ret != 1) { return ((enum print_line_t )ret); } else { } trace_seq_printf(s, "data=%p\n", (void *)field->data); tmp = trace_handle_return(s); return (tmp); } } static enum print_line_t trace_raw_output_brcms_macintstatus(struct trace_iterator *iter , int flags , struct trace_event *trace_event ) { struct trace_seq *s ; struct trace_seq *p ; struct trace_event_raw_brcms_macintstatus *field ; int ret ; enum print_line_t tmp ; { s = & iter->seq; p = & iter->tmp_seq; field = (struct trace_event_raw_brcms_macintstatus *)iter->ent; ret = trace_raw_output_prep(iter, trace_event); if (ret != 1) { return ((enum print_line_t )ret); } else { } trace_seq_printf(s, "[%s] in_isr=%d macintstatus=%#x mask=%#x\n", (char *)field + ((unsigned long )field->__data_loc_dev & 65535UL), field->in_isr, field->macintstatus, field->mask); tmp = trace_handle_return(s); return (tmp); } } static int trace_event_define_fields_brcms_timer(struct trace_event_call *event_call ) { int ret ; { ret = trace_define_field(event_call, "uint", "ms", 8, 4, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "uint", "set", 12, 4, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "uint", "periodic", 16, 4, 0, 0); if (ret != 0) { return (ret); } else { } return (ret); } } static int trace_event_define_fields_brcms_dpc(struct trace_event_call *event_call ) { int ret ; { ret = trace_define_field(event_call, "unsigned long", "data", 8, 8, 0, 0); if (ret != 0) { return (ret); } else { } return (ret); } } static int trace_event_define_fields_brcms_macintstatus(struct trace_event_call *event_call ) { int ret ; { ret = trace_define_field(event_call, "__data_loc char[]", "dev", 8, 4, 1, 0); ret = trace_define_field(event_call, "int", "in_isr", 12, 4, 1, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u32", "macintstatus", 16, 4, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u32", "mask", 20, 4, 0, 0); if (ret != 0) { return (ret); } else { } return (ret); } } static char const __tpstrtab_brcms_txdesc[13U] = { 'b', 'r', 'c', 'm', 's', '_', 't', 'x', 'd', 'e', 's', 'c', '\000'}; struct tracepoint __tracepoint_brcms_txdesc = {(char const *)(& __tpstrtab_brcms_txdesc), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static char const __tpstrtab_brcms_txstatus[15U] = { 'b', 'r', 'c', 'm', 's', '_', 't', 'x', 's', 't', 'a', 't', 'u', 's', '\000'}; struct tracepoint __tracepoint_brcms_txstatus = {(char const *)(& __tpstrtab_brcms_txstatus), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static char const __tpstrtab_brcms_ampdu_session[20U] = { 'b', 'r', 'c', 'm', 's', '_', 'a', 'm', 'p', 'd', 'u', '_', 's', 'e', 's', 's', 'i', 'o', 'n', '\000'}; struct tracepoint __tracepoint_brcms_ampdu_session = {(char const *)(& __tpstrtab_brcms_ampdu_session), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static enum print_line_t trace_raw_output_brcms_txdesc(struct trace_iterator *iter , int flags , struct trace_event *trace_event ) { struct trace_seq *s ; struct trace_seq *p ; struct trace_event_raw_brcms_txdesc *field ; int ret ; enum print_line_t tmp ; { s = & iter->seq; p = & iter->tmp_seq; field = (struct trace_event_raw_brcms_txdesc *)iter->ent; ret = trace_raw_output_prep(iter, trace_event); if (ret != 1) { return ((enum print_line_t )ret); } else { } trace_seq_printf(s, "[%s] txdesc\n", (char *)field + ((unsigned long )field->__data_loc_dev & 65535UL)); tmp = trace_handle_return(s); return (tmp); } } static enum print_line_t trace_raw_output_brcms_txstatus(struct trace_iterator *iter , int flags , struct trace_event *trace_event ) { struct trace_seq *s ; struct trace_seq *p ; struct trace_event_raw_brcms_txstatus *field ; int ret ; enum print_line_t tmp ; { s = & iter->seq; p = & iter->tmp_seq; field = (struct trace_event_raw_brcms_txstatus *)iter->ent; ret = trace_raw_output_prep(iter, trace_event); if (ret != 1) { return ((enum print_line_t )ret); } else { } trace_seq_printf(s, "[%s] FrameId %#04x TxStatus %#04x LastTxTime %#04x Seq %#04x PHYTxStatus %#04x RxAck %#04x\n", (char *)field + ((unsigned long )field->__data_loc_dev & 65535UL), (int )field->frameid, (int )field->status, (int )field->lasttxtime, (int )field->sequence, (int )field->phyerr, (int )field->ackphyrxsh); tmp = trace_handle_return(s); return (tmp); } } static enum print_line_t trace_raw_output_brcms_ampdu_session(struct trace_iterator *iter , int flags , struct trace_event *trace_event ) { struct trace_seq *s ; struct trace_seq *p ; struct trace_event_raw_brcms_ampdu_session *field ; int ret ; enum print_line_t tmp ; { s = & iter->seq; p = & iter->tmp_seq; field = (struct trace_event_raw_brcms_ampdu_session *)iter->ent; ret = trace_raw_output_prep(iter, trace_event); if (ret != 1) { return ((enum print_line_t )ret); } else { } trace_seq_printf(s, "[%s] ampdu session max_len=%u max_frames=%u len=%u frames=%u dma_len=%u\n", (char *)field + ((unsigned long )field->__data_loc_dev & 65535UL), field->max_ampdu_len, (int )field->max_ampdu_frames, (int )field->ampdu_len, (int )field->ampdu_frames, (int )field->dma_len); tmp = trace_handle_return(s); return (tmp); } } static int trace_event_define_fields_brcms_txdesc(struct trace_event_call *event_call ) { int ret ; { ret = trace_define_field(event_call, "__data_loc char[]", "dev", 8, 4, 1, 0); ret = trace_define_field(event_call, "__data_loc u8[]", "txh", 12, 4, 0, 0); return (ret); } } static int trace_event_define_fields_brcms_txstatus(struct trace_event_call *event_call ) { int ret ; { ret = trace_define_field(event_call, "__data_loc char[]", "dev", 8, 4, 1, 0); ret = trace_define_field(event_call, "u16", "framelen", 12, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "frameid", 14, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "status", 16, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "lasttxtime", 18, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "sequence", 20, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "phyerr", 22, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "ackphyrxsh", 24, 2, 0, 0); if (ret != 0) { return (ret); } else { } return (ret); } } static int trace_event_define_fields_brcms_ampdu_session(struct trace_event_call *event_call ) { int ret ; { ret = trace_define_field(event_call, "__data_loc char[]", "dev", 8, 4, 1, 0); ret = trace_define_field(event_call, "unsigned", "max_ampdu_len", 12, 4, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "max_ampdu_frames", 16, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "ampdu_len", 18, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "ampdu_frames", 20, 2, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "u16", "dma_len", 22, 2, 0, 0); if (ret != 0) { return (ret); } else { } return (ret); } } struct tracepoint __tracepoint_brcms_info ; struct tracepoint __tracepoint_brcms_warn ; struct tracepoint __tracepoint_brcms_err ; struct tracepoint __tracepoint_brcms_crit ; struct tracepoint __tracepoint_brcms_dbg ; static char const __tpstrtab_brcms_info[11U] = { 'b', 'r', 'c', 'm', 's', '_', 'i', 'n', 'f', 'o', '\000'}; struct tracepoint __tracepoint_brcms_info = {(char const *)(& __tpstrtab_brcms_info), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static char const __tpstrtab_brcms_warn[11U] = { 'b', 'r', 'c', 'm', 's', '_', 'w', 'a', 'r', 'n', '\000'}; struct tracepoint __tracepoint_brcms_warn = {(char const *)(& __tpstrtab_brcms_warn), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static char const __tpstrtab_brcms_err[10U] = { 'b', 'r', 'c', 'm', 's', '_', 'e', 'r', 'r', '\000'}; struct tracepoint __tracepoint_brcms_err = {(char const *)(& __tpstrtab_brcms_err), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static char const __tpstrtab_brcms_crit[11U] = { 'b', 'r', 'c', 'm', 's', '_', 'c', 'r', 'i', 't', '\000'}; struct tracepoint __tracepoint_brcms_crit = {(char const *)(& __tpstrtab_brcms_crit), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static char const __tpstrtab_brcms_dbg[10U] = { 'b', 'r', 'c', 'm', 's', '_', 'd', 'b', 'g', '\000'}; struct tracepoint __tracepoint_brcms_dbg = {(char const *)(& __tpstrtab_brcms_dbg), {{0}}, (void (*)(void))0, (void (*)(void))0, (struct tracepoint_func *)0}; static enum print_line_t trace_raw_output_brcms_msg_event(struct trace_iterator *iter , int flags , struct trace_event *trace_event ) { struct trace_seq *s ; struct trace_seq *p ; struct trace_event_raw_brcms_msg_event *field ; int ret ; enum print_line_t tmp ; { s = & iter->seq; p = & iter->tmp_seq; field = (struct trace_event_raw_brcms_msg_event *)iter->ent; ret = trace_raw_output_prep(iter, trace_event); if (ret != 1) { return ((enum print_line_t )ret); } else { } trace_seq_printf(s, "%s\n", (char *)field + ((unsigned long )field->__data_loc_msg & 65535UL)); tmp = trace_handle_return(s); return (tmp); } } static enum print_line_t trace_raw_output_brcms_dbg(struct trace_iterator *iter , int flags , struct trace_event *trace_event ) { struct trace_seq *s ; struct trace_seq *p ; struct trace_event_raw_brcms_dbg *field ; int ret ; enum print_line_t tmp ; { s = & iter->seq; p = & iter->tmp_seq; field = (struct trace_event_raw_brcms_dbg *)iter->ent; ret = trace_raw_output_prep(iter, trace_event); if (ret != 1) { return ((enum print_line_t )ret); } else { } trace_seq_printf(s, "%s: %s\n", (char *)field + ((unsigned long )field->__data_loc_func & 65535UL), (char *)field + ((unsigned long )field->__data_loc_msg & 65535UL)); tmp = trace_handle_return(s); return (tmp); } } static int trace_event_define_fields_brcms_msg_event(struct trace_event_call *event_call ) { int ret ; { ret = trace_define_field(event_call, "__data_loc char[]", "msg", 8, 4, 1, 0); return (ret); } } static int trace_event_define_fields_brcms_dbg(struct trace_event_call *event_call ) { int ret ; { ret = trace_define_field(event_call, "u32", "level", 8, 4, 0, 0); if (ret != 0) { return (ret); } else { } ret = trace_define_field(event_call, "__data_loc char[]", "func", 12, 4, 1, 0); ret = trace_define_field(event_call, "__data_loc char[]", "msg", 16, 4, 1, 0); return (ret); } } void ldv_initialize_trace_event_class_15(void) { void *tmp ; { tmp = ldv_init_zalloc(144UL); event_class_brcms_macintstatus_group0 = (struct trace_event_call *)tmp; return; } } void ldv_initialize_trace_event_class_6(void) { void *tmp ; { tmp = ldv_init_zalloc(144UL); event_class_brcms_msg_event_group0 = (struct trace_event_call *)tmp; return; } } void ldv_initialize_trace_event_class_16(void) { void *tmp ; { tmp = ldv_init_zalloc(144UL); event_class_brcms_dpc_group0 = (struct trace_event_call *)tmp; return; } } void ldv_initialize_trace_event_class_17(void) { void *tmp ; { tmp = ldv_init_zalloc(144UL); event_class_brcms_timer_group0 = (struct trace_event_call *)tmp; return; } } void ldv_initialize_trace_event_class_11(void) { void *tmp ; { tmp = ldv_init_zalloc(144UL); event_class_brcms_txdesc_group0 = (struct trace_event_call *)tmp; return; } } void ldv_initialize_trace_event_class_10(void) { void *tmp ; { tmp = ldv_init_zalloc(144UL); event_class_brcms_txstatus_group0 = (struct trace_event_call *)tmp; return; } } void ldv_initialize_trace_event_class_9(void) { void *tmp ; { tmp = ldv_init_zalloc(144UL); event_class_brcms_ampdu_session_group0 = (struct trace_event_call *)tmp; return; } } void ldv_initialize_trace_event_class_5(void) { void *tmp ; { tmp = ldv_init_zalloc(144UL); event_class_brcms_dbg_group0 = (struct trace_event_call *)tmp; return; } } void ldv_main_exported_11(void) { void *ldvarg0 ; void *tmp ; enum trace_reg ldvarg1 ; int tmp___0 ; { tmp = ldv_init_zalloc(1UL); ldvarg0 = tmp; ldv_memset((void *)(& ldvarg1), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_11 == 1) { trace_event_reg(event_class_brcms_txdesc_group0, ldvarg1, ldvarg0); ldv_state_variable_11 = 1; } else { } goto ldv_34872; case 1: ; if (ldv_state_variable_11 == 1) { trace_event_raw_init(event_class_brcms_txdesc_group0); ldv_state_variable_11 = 1; } else { } goto ldv_34872; case 2: ; if (ldv_state_variable_11 == 1) { trace_event_define_fields_brcms_txdesc(event_class_brcms_txdesc_group0); ldv_state_variable_11 = 1; } else { } goto ldv_34872; default: ldv_stop(); } ldv_34872: ; return; } } void ldv_main_exported_7(void) { int ldvarg5 ; struct trace_iterator *ldvarg3 ; void *tmp ; struct trace_event *ldvarg4 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(8560UL); ldvarg3 = (struct trace_iterator *)tmp; tmp___0 = ldv_init_zalloc(48UL); ldvarg4 = (struct trace_event *)tmp___0; ldv_memset((void *)(& ldvarg5), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_7 == 1) { trace_raw_output_brcms_dbg(ldvarg3, ldvarg5, ldvarg4); ldv_state_variable_7 = 1; } else { } goto ldv_34883; default: ldv_stop(); } ldv_34883: ; return; } } void ldv_main_exported_17(void) { void *ldvarg6 ; void *tmp ; enum trace_reg ldvarg7 ; int tmp___0 ; { tmp = ldv_init_zalloc(1UL); ldvarg6 = tmp; ldv_memset((void *)(& ldvarg7), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_17 == 1) { trace_event_reg(event_class_brcms_timer_group0, ldvarg7, ldvarg6); ldv_state_variable_17 = 1; } else { } goto ldv_34891; case 1: ; if (ldv_state_variable_17 == 1) { trace_event_raw_init(event_class_brcms_timer_group0); ldv_state_variable_17 = 1; } else { } goto ldv_34891; case 2: ; if (ldv_state_variable_17 == 1) { trace_event_define_fields_brcms_timer(event_class_brcms_timer_group0); ldv_state_variable_17 = 1; } else { } goto ldv_34891; default: ldv_stop(); } ldv_34891: ; return; } } void ldv_main_exported_18(void) { struct trace_event *ldvarg9 ; void *tmp ; int ldvarg10 ; struct trace_iterator *ldvarg8 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(48UL); ldvarg9 = (struct trace_event *)tmp; tmp___0 = ldv_init_zalloc(8560UL); ldvarg8 = (struct trace_iterator *)tmp___0; ldv_memset((void *)(& ldvarg10), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_18 == 1) { trace_raw_output_brcms_macintstatus(ldvarg8, ldvarg10, ldvarg9); ldv_state_variable_18 = 1; } else { } goto ldv_34902; default: ldv_stop(); } ldv_34902: ; return; } } void ldv_main_exported_16(void) { void *ldvarg42 ; void *tmp ; enum trace_reg ldvarg43 ; int tmp___0 ; { tmp = ldv_init_zalloc(1UL); ldvarg42 = tmp; ldv_memset((void *)(& ldvarg43), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_16 == 1) { trace_event_reg(event_class_brcms_dpc_group0, ldvarg43, ldvarg42); ldv_state_variable_16 = 1; } else { } goto ldv_34910; case 1: ; if (ldv_state_variable_16 == 1) { trace_event_raw_init(event_class_brcms_dpc_group0); ldv_state_variable_16 = 1; } else { } goto ldv_34910; case 2: ; if (ldv_state_variable_16 == 1) { trace_event_define_fields_brcms_dpc(event_class_brcms_dpc_group0); ldv_state_variable_16 = 1; } else { } goto ldv_34910; default: ldv_stop(); } ldv_34910: ; return; } } void ldv_main_exported_13(void) { int ldvarg46 ; struct trace_iterator *ldvarg44 ; void *tmp ; struct trace_event *ldvarg45 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(8560UL); ldvarg44 = (struct trace_iterator *)tmp; tmp___0 = ldv_init_zalloc(48UL); ldvarg45 = (struct trace_event *)tmp___0; ldv_memset((void *)(& ldvarg46), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_13 == 1) { trace_raw_output_brcms_txstatus(ldvarg44, ldvarg46, ldvarg45); ldv_state_variable_13 = 1; } else { } goto ldv_34921; default: ldv_stop(); } ldv_34921: ; return; } } void ldv_main_exported_6(void) { void *ldvarg47 ; void *tmp ; enum trace_reg ldvarg48 ; int tmp___0 ; { tmp = ldv_init_zalloc(1UL); ldvarg47 = tmp; ldv_memset((void *)(& ldvarg48), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_6 == 1) { trace_event_reg(event_class_brcms_msg_event_group0, ldvarg48, ldvarg47); ldv_state_variable_6 = 1; } else { } goto ldv_34929; case 1: ; if (ldv_state_variable_6 == 1) { trace_event_raw_init(event_class_brcms_msg_event_group0); ldv_state_variable_6 = 1; } else { } goto ldv_34929; case 2: ; if (ldv_state_variable_6 == 1) { trace_event_define_fields_brcms_msg_event(event_class_brcms_msg_event_group0); ldv_state_variable_6 = 1; } else { } goto ldv_34929; default: ldv_stop(); } ldv_34929: ; return; } } void ldv_main_exported_9(void) { enum trace_reg ldvarg50 ; void *ldvarg49 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(1UL); ldvarg49 = tmp; ldv_memset((void *)(& ldvarg50), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_9 == 1) { trace_event_reg(event_class_brcms_ampdu_session_group0, ldvarg50, ldvarg49); ldv_state_variable_9 = 1; } else { } goto ldv_34939; case 1: ; if (ldv_state_variable_9 == 1) { trace_event_raw_init(event_class_brcms_ampdu_session_group0); ldv_state_variable_9 = 1; } else { } goto ldv_34939; case 2: ; if (ldv_state_variable_9 == 1) { trace_event_define_fields_brcms_ampdu_session(event_class_brcms_ampdu_session_group0); ldv_state_variable_9 = 1; } else { } goto ldv_34939; default: ldv_stop(); } ldv_34939: ; return; } } void ldv_main_exported_12(void) { struct trace_event *ldvarg52 ; void *tmp ; int ldvarg53 ; struct trace_iterator *ldvarg51 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(48UL); ldvarg52 = (struct trace_event *)tmp; tmp___0 = ldv_init_zalloc(8560UL); ldvarg51 = (struct trace_iterator *)tmp___0; ldv_memset((void *)(& ldvarg53), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_12 == 1) { trace_raw_output_brcms_ampdu_session(ldvarg51, ldvarg53, ldvarg52); ldv_state_variable_12 = 1; } else { } goto ldv_34950; default: ldv_stop(); } ldv_34950: ; return; } } void ldv_main_exported_14(void) { int ldvarg59 ; struct trace_event *ldvarg58 ; void *tmp ; struct trace_iterator *ldvarg57 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(48UL); ldvarg58 = (struct trace_event *)tmp; tmp___0 = ldv_init_zalloc(8560UL); ldvarg57 = (struct trace_iterator *)tmp___0; ldv_memset((void *)(& ldvarg59), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_14 == 1) { trace_raw_output_brcms_txdesc(ldvarg57, ldvarg59, ldvarg58); ldv_state_variable_14 = 1; } else { } goto ldv_34959; default: ldv_stop(); } ldv_34959: ; return; } } void ldv_main_exported_15(void) { void *ldvarg60 ; void *tmp ; enum trace_reg ldvarg61 ; int tmp___0 ; { tmp = ldv_init_zalloc(1UL); ldvarg60 = tmp; ldv_memset((void *)(& ldvarg61), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_15 == 1) { trace_event_reg(event_class_brcms_macintstatus_group0, ldvarg61, ldvarg60); ldv_state_variable_15 = 1; } else { } goto ldv_34967; case 1: ; if (ldv_state_variable_15 == 1) { trace_event_raw_init(event_class_brcms_macintstatus_group0); ldv_state_variable_15 = 1; } else { } goto ldv_34967; case 2: ; if (ldv_state_variable_15 == 1) { trace_event_define_fields_brcms_macintstatus(event_class_brcms_macintstatus_group0); ldv_state_variable_15 = 1; } else { } goto ldv_34967; default: ldv_stop(); } ldv_34967: ; return; } } void ldv_main_exported_20(void) { int ldvarg56 ; struct trace_event *ldvarg55 ; void *tmp ; struct trace_iterator *ldvarg54 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(48UL); ldvarg55 = (struct trace_event *)tmp; tmp___0 = ldv_init_zalloc(8560UL); ldvarg54 = (struct trace_iterator *)tmp___0; ldv_memset((void *)(& ldvarg56), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_20 == 1) { trace_raw_output_brcms_timer(ldvarg54, ldvarg56, ldvarg55); ldv_state_variable_20 = 1; } else { } goto ldv_34978; default: ldv_stop(); } ldv_34978: ; return; } } void ldv_main_exported_8(void) { struct trace_iterator *ldvarg62 ; void *tmp ; int ldvarg64 ; struct trace_event *ldvarg63 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(8560UL); ldvarg62 = (struct trace_iterator *)tmp; tmp___0 = ldv_init_zalloc(48UL); ldvarg63 = (struct trace_event *)tmp___0; ldv_memset((void *)(& ldvarg64), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_8 == 1) { trace_raw_output_brcms_msg_event(ldvarg62, ldvarg64, ldvarg63); ldv_state_variable_8 = 1; } else { } goto ldv_34987; default: ldv_stop(); } ldv_34987: ; return; } } void ldv_main_exported_10(void) { enum trace_reg ldvarg74 ; void *ldvarg73 ; void *tmp ; int tmp___0 ; { tmp = ldv_init_zalloc(1UL); ldvarg73 = tmp; ldv_memset((void *)(& ldvarg74), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_10 == 1) { trace_event_reg(event_class_brcms_txstatus_group0, ldvarg74, ldvarg73); ldv_state_variable_10 = 1; } else { } goto ldv_34995; case 1: ; if (ldv_state_variable_10 == 1) { trace_event_raw_init(event_class_brcms_txstatus_group0); ldv_state_variable_10 = 1; } else { } goto ldv_34995; case 2: ; if (ldv_state_variable_10 == 1) { trace_event_define_fields_brcms_txstatus(event_class_brcms_txstatus_group0); ldv_state_variable_10 = 1; } else { } goto ldv_34995; default: ldv_stop(); } ldv_34995: ; return; } } void ldv_main_exported_19(void) { int ldvarg72 ; struct trace_event *ldvarg71 ; void *tmp ; struct trace_iterator *ldvarg70 ; void *tmp___0 ; int tmp___1 ; { tmp = ldv_init_zalloc(48UL); ldvarg71 = (struct trace_event *)tmp; tmp___0 = ldv_init_zalloc(8560UL); ldvarg70 = (struct trace_iterator *)tmp___0; ldv_memset((void *)(& ldvarg72), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_19 == 1) { trace_raw_output_brcms_dpc(ldvarg70, ldvarg72, ldvarg71); ldv_state_variable_19 = 1; } else { } goto ldv_35006; default: ldv_stop(); } ldv_35006: ; return; } } void ldv_main_exported_5(void) { void *ldvarg75 ; void *tmp ; enum trace_reg ldvarg76 ; int tmp___0 ; { tmp = ldv_init_zalloc(1UL); ldvarg75 = tmp; ldv_memset((void *)(& ldvarg76), 0, 4UL); tmp___0 = __VERIFIER_nondet_int(); switch (tmp___0) { case 0: ; if (ldv_state_variable_5 == 1) { trace_event_reg(event_class_brcms_dbg_group0, ldvarg76, ldvarg75); ldv_state_variable_5 = 1; } else { } goto ldv_35014; case 1: ; if (ldv_state_variable_5 == 1) { trace_event_raw_init(event_class_brcms_dbg_group0); ldv_state_variable_5 = 1; } else { } goto ldv_35014; case 2: ; if (ldv_state_variable_5 == 1) { trace_event_define_fields_brcms_dbg(event_class_brcms_dbg_group0); ldv_state_variable_5 = 1; } else { } goto ldv_35014; default: ldv_stop(); } ldv_35014: ; return; } } bool ldv_queue_work_on_269(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_270(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_271(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_272(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_273(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } void ldv__builtin_va_end(__builtin_va_list * ) ; __inline static long ldv__builtin_expect(long exp , long c ) ; void ldv__builtin_va_start(__builtin_va_list * ) ; bool ldv_is_err_or_null(void const *ptr ) ; long ldv_ptr_err(void const *ptr ) ; __inline static unsigned long arch_local_save_flags___2(void) { unsigned long __ret ; unsigned long __edi ; unsigned long __esi ; unsigned long __edx ; unsigned long __ecx ; unsigned long __eax ; long tmp ; { __edi = __edi; __esi = __esi; __edx = __edx; __ecx = __ecx; __eax = __eax; tmp = ldv__builtin_expect((unsigned long )pv_irq_ops.save_fl.func == (unsigned long )((void *)0), 0L); if (tmp != 0L) { __asm__ volatile ("1:\tud2\n.pushsection __bug_table,\"a\"\n2:\t.long 1b - 2b, %c0 - 2b\n\t.word %c1, 0\n\t.org 2b+%c2\n.popsection": : "i" ((char *)"./arch/x86/include/asm/paravirt.h"), "i" (831), "i" (12UL)); ldv_4860: ; goto ldv_4860; } else { } __asm__ volatile ("771:\n\tcall *%c2;\n772:\n.pushsection .parainstructions,\"a\"\n .balign 8 \n .quad 771b\n .byte %c1\n .byte 772b-771b\n .short %c3\n.popsection\n": "=a" (__eax): [paravirt_typenum] "i" (43UL), [paravirt_opptr] "i" (& pv_irq_ops.save_fl.func), [paravirt_clobber] "i" (1): "memory", "cc"); __ret = __eax; return (__ret); } } __inline static long PTR_ERR(void const *ptr ) ; __inline static bool IS_ERR(void const *ptr ) ; __inline static bool IS_ERR_OR_NULL(void const *ptr ) ; __inline static int PTR_ERR_OR_ZERO(void const *ptr ) { long tmp ; bool tmp___0 ; { tmp___0 = IS_ERR(ptr); if ((int )tmp___0) { tmp = PTR_ERR(ptr); return ((int )tmp); } else { return (0); } } } __inline static bool static_key_false___2(struct static_key *key ) { int tmp ; long tmp___0 ; { tmp = static_key_count(key); tmp___0 = ldv__builtin_expect(tmp > 0, 0L); if (tmp___0 != 0L) { return (1); } else { } return (0); } } __inline static int rcu_read_lock_sched_held___2(void) { int lockdep_opinion ; int tmp ; bool tmp___0 ; int tmp___1 ; bool tmp___2 ; int tmp___3 ; int tmp___4 ; unsigned long _flags ; int tmp___5 ; int tmp___6 ; { lockdep_opinion = 0; tmp = debug_lockdep_rcu_enabled(); if (tmp == 0) { return (1); } else { } tmp___0 = rcu_is_watching(); if (tmp___0) { tmp___1 = 0; } else { tmp___1 = 1; } if (tmp___1) { return (0); } else { } tmp___2 = rcu_lockdep_current_cpu_online(); if (tmp___2) { tmp___3 = 0; } else { tmp___3 = 1; } if (tmp___3) { return (0); } else { } if (debug_locks != 0) { lockdep_opinion = lock_is_held(& rcu_sched_lock_map); } else { } if (lockdep_opinion != 0) { tmp___6 = 1; } else { tmp___4 = preempt_count(); if (tmp___4 != 0) { tmp___6 = 1; } else { _flags = arch_local_save_flags___2(); tmp___5 = arch_irqs_disabled_flags(_flags); if (tmp___5 != 0) { tmp___6 = 1; } else { tmp___6 = 0; } } } return (tmp___6); } } bool ldv_queue_work_on_283(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_285(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_284(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_287(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_286(struct workqueue_struct *ldv_func_arg1 ) ; __inline static char const *kobject_name(struct kobject const *kobj ) { { return ((char const *)kobj->name); } } extern ssize_t seq_read(struct file * , char * , size_t , loff_t * ) ; extern loff_t seq_lseek(struct file * , loff_t , int ) ; extern int seq_printf(struct seq_file * , char const * , ...) ; extern int single_open(struct file * , int (*)(struct seq_file * , void * ) , void * ) ; extern int single_release(struct inode * , struct file * ) ; extern struct dentry *debugfs_create_file(char const * , umode_t , struct dentry * , void * , struct file_operations const * ) ; extern struct dentry *debugfs_create_dir(char const * , struct dentry * ) ; extern void debugfs_remove_recursive(struct dentry * ) ; extern int net_ratelimit(void) ; extern void *devm_kmalloc(struct device * , size_t , gfp_t ) ; __inline static void *devm_kzalloc(struct device *dev , size_t size , gfp_t gfp ) { void *tmp ; { tmp = devm_kmalloc(dev, size, gfp | 32768U); return (tmp); } } __inline static char const *dev_name(struct device const *dev ) { char const *tmp ; { if ((unsigned long )dev->init_name != (unsigned long )((char const */* const */)0)) { return ((char const *)dev->init_name); } else { } tmp = kobject_name(& dev->kobj); return (tmp); } } extern void dev_crit(struct device const * , char const * , ...) ; extern void dev_warn(struct device const * , char const * , ...) ; extern char *brcmu_boardrev_str(u32 , char * ) ; void __brcms_info(struct device *dev , char const *fmt , ...) ; void __brcms_crit(struct device *dev , char const *fmt , ...) ; struct dentry *brcms_debugfs_get_devdir(struct brcms_pub *drvr ) ; __inline static void trace_brcms_info(struct va_format *vaf ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_418 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_420 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___2(& __tracepoint_brcms_info.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_info.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___2(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 44, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_54938: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct va_format * ))it_func))(__data, vaf); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_54938; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_info.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___2(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 44, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } __inline static void trace_brcms_warn(struct va_format *vaf ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_422 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_424 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___2(& __tracepoint_brcms_warn.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_warn.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___2(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 49, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_54989: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct va_format * ))it_func))(__data, vaf); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_54989; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_warn.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___2(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 49, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } __inline static void trace_brcms_err(struct va_format *vaf ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_426 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_428 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___2(& __tracepoint_brcms_err.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_err.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___2(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 54, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_55040: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct va_format * ))it_func))(__data, vaf); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_55040; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_err.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___2(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 54, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } __inline static void trace_brcms_crit(struct va_format *vaf ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_430 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_432 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___2(& __tracepoint_brcms_crit.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_crit.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___2(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 59, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_55091: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , struct va_format * ))it_func))(__data, vaf); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_55091; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_crit.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___2(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 59, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } __inline static void trace_brcms_dbg(u32 level , char const *func , struct va_format *vaf ) { struct tracepoint_func *it_func_ptr ; void *it_func ; void *__data ; struct tracepoint_func *________p1 ; struct tracepoint_func *_________p1 ; union __anonunion___u_434 __u ; bool __warned ; int tmp ; int tmp___0 ; bool tmp___1 ; struct tracepoint_func *________p1___0 ; struct tracepoint_func *_________p1___0 ; union __anonunion___u_436 __u___0 ; bool __warned___0 ; int tmp___2 ; int tmp___3 ; { tmp___1 = static_key_false___2(& __tracepoint_brcms_dbg.key); if ((int )tmp___1) { rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_dbg.funcs), (void *)(& __u.__c), 8); _________p1 = __u.__val; ________p1 = _________p1; tmp = debug_lockdep_rcu_enabled(); if (tmp != 0 && ! __warned) { tmp___0 = rcu_read_lock_sched_held___2(); if (tmp___0 == 0) { __warned = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 77, "suspicious rcu_dereference_check() usage"); } else { } } else { } it_func_ptr = ________p1; if ((unsigned long )it_func_ptr != (unsigned long )((struct tracepoint_func *)0)) { ldv_55146: it_func = it_func_ptr->func; __data = it_func_ptr->data; (*((void (*)(void * , u32 , char const * , struct va_format * ))it_func))(__data, level, func, vaf); it_func_ptr = it_func_ptr + 1; if ((unsigned long )it_func_ptr->func != (unsigned long )((void *)0)) { goto ldv_55146; } else { } } else { } rcu_read_unlock_sched_notrace(); } else { } rcu_read_lock_sched_notrace(); __read_once_size((void const volatile *)(& __tracepoint_brcms_dbg.funcs), (void *)(& __u___0.__c), 8); _________p1___0 = __u___0.__val; ________p1___0 = _________p1___0; tmp___2 = debug_lockdep_rcu_enabled(); if (tmp___2 != 0 && ! __warned___0) { tmp___3 = rcu_read_lock_sched_held___2(); if (tmp___3 == 0) { __warned___0 = 1; lockdep_rcu_suspicious("drivers/net/wireless/brcm80211/brcmsmac/brcms_trace_brcmsmac_msg.h", 77, "suspicious rcu_dereference_check() usage"); } else { } } else { } rcu_read_unlock_sched_notrace(); return; } } static struct dentry *root_folder ; void brcms_debugfs_init(void) { bool tmp ; { root_folder = debugfs_create_dir("brcmsmac", (struct dentry *)0); tmp = IS_ERR((void const *)root_folder); if ((int )tmp) { root_folder = (struct dentry *)0; } else { } return; } } void brcms_debugfs_exit(void) { { if ((unsigned long )root_folder == (unsigned long )((struct dentry *)0)) { return; } else { } debugfs_remove_recursive(root_folder); root_folder = (struct dentry *)0; return; } } int brcms_debugfs_attach(struct brcms_pub *drvr ) { char const *tmp ; int tmp___0 ; { if ((unsigned long )root_folder == (unsigned long )((struct dentry *)0)) { return (-19); } else { } tmp = dev_name((struct device const *)(& (((drvr->wlc)->hw)->d11core)->dev)); drvr->dbgfs_dir = debugfs_create_dir(tmp, root_folder); tmp___0 = PTR_ERR_OR_ZERO((void const *)drvr->dbgfs_dir); return (tmp___0); } } void brcms_debugfs_detach(struct brcms_pub *drvr ) { bool tmp ; int tmp___0 ; { tmp = IS_ERR_OR_NULL((void const *)drvr->dbgfs_dir); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { debugfs_remove_recursive(drvr->dbgfs_dir); } else { } return; } } struct dentry *brcms_debugfs_get_devdir(struct brcms_pub *drvr ) { { return (drvr->dbgfs_dir); } } static int brcms_debugfs_hardware_read(struct seq_file *s , void *data ) { struct brcms_pub *drvr ; struct brcms_hardware *hw ; struct bcma_device *core ; struct bcma_bus *bus ; char boardrev[8U] ; char *tmp ; { drvr = (struct brcms_pub *)s->private; hw = (drvr->wlc)->hw; core = hw->d11core; bus = core->bus; tmp = brcmu_boardrev_str((u32 )hw->boardrev, (char *)(& boardrev)); seq_printf(s, "chipnum 0x%x\nchiprev 0x%x\nchippackage 0x%x\ncorerev 0x%x\nboardid 0x%x\nboardvendor 0x%x\nboardrev %s\nboardflags 0x%x\nboardflags2 0x%x\nucoderev 0x%x\nradiorev 0x%x\nphytype 0x%x\nphyrev 0x%x\nanarev 0x%x\nnvramrev %d\n", (int )bus->chipinfo.id, (int )bus->chipinfo.rev, (int )bus->chipinfo.pkg, (int )core->id.rev, (int )bus->boardinfo.type, (int )bus->boardinfo.vendor, tmp, ((drvr->wlc)->hw)->boardflags, ((drvr->wlc)->hw)->boardflags2, (drvr->wlc)->ucode_rev, (int )(hw->band)->radiorev, (int )(hw->band)->phytype, (int )(hw->band)->phyrev, ((hw->band)->pi)->ana_rev, (int )hw->sromrev); return (0); } } static int brcms_debugfs_macstat_read(struct seq_file *s , void *data ) { struct brcms_pub *drvr ; struct brcms_info *wl ; struct macstat stats ; int i ; { drvr = (struct brcms_pub *)s->private; wl = (struct brcms_info *)(drvr->ieee_hw)->priv; spin_lock_bh(& wl->lock); stats = *(((drvr->wlc)->core)->macstat_snapshot); spin_unlock_bh(& wl->lock); seq_printf(s, "txallfrm: %d\n", (int )stats.txallfrm); seq_printf(s, "txrtsfrm: %d\n", (int )stats.txrtsfrm); seq_printf(s, "txctsfrm: %d\n", (int )stats.txctsfrm); seq_printf(s, "txackfrm: %d\n", (int )stats.txackfrm); seq_printf(s, "txdnlfrm: %d\n", (int )stats.txdnlfrm); seq_printf(s, "txbcnfrm: %d\n", (int )stats.txbcnfrm); seq_printf(s, "txfunfl[8]:"); i = 0; goto ldv_56210; ldv_56209: seq_printf(s, " %d", (int )stats.txfunfl[i]); i = i + 1; ldv_56210: ; if ((unsigned int )i <= 7U) { goto ldv_56209; } else { } seq_printf(s, "\ntxtplunfl: %d\n", (int )stats.txtplunfl); seq_printf(s, "txphyerr: %d\n", (int )stats.txphyerr); seq_printf(s, "pktengrxducast: %d\n", (int )stats.pktengrxducast); seq_printf(s, "pktengrxdmcast: %d\n", (int )stats.pktengrxdmcast); seq_printf(s, "rxfrmtoolong: %d\n", (int )stats.rxfrmtoolong); seq_printf(s, "rxfrmtooshrt: %d\n", (int )stats.rxfrmtooshrt); seq_printf(s, "rxinvmachdr: %d\n", (int )stats.rxinvmachdr); seq_printf(s, "rxbadfcs: %d\n", (int )stats.rxbadfcs); seq_printf(s, "rxbadplcp: %d\n", (int )stats.rxbadplcp); seq_printf(s, "rxcrsglitch: %d\n", (int )stats.rxcrsglitch); seq_printf(s, "rxstrt: %d\n", (int )stats.rxstrt); seq_printf(s, "rxdfrmucastmbss: %d\n", (int )stats.rxdfrmucastmbss); seq_printf(s, "rxmfrmucastmbss: %d\n", (int )stats.rxmfrmucastmbss); seq_printf(s, "rxcfrmucast: %d\n", (int )stats.rxcfrmucast); seq_printf(s, "rxrtsucast: %d\n", (int )stats.rxrtsucast); seq_printf(s, "rxctsucast: %d\n", (int )stats.rxctsucast); seq_printf(s, "rxackucast: %d\n", (int )stats.rxackucast); seq_printf(s, "rxdfrmocast: %d\n", (int )stats.rxdfrmocast); seq_printf(s, "rxmfrmocast: %d\n", (int )stats.rxmfrmocast); seq_printf(s, "rxcfrmocast: %d\n", (int )stats.rxcfrmocast); seq_printf(s, "rxrtsocast: %d\n", (int )stats.rxrtsocast); seq_printf(s, "rxctsocast: %d\n", (int )stats.rxctsocast); seq_printf(s, "rxdfrmmcast: %d\n", (int )stats.rxdfrmmcast); seq_printf(s, "rxmfrmmcast: %d\n", (int )stats.rxmfrmmcast); seq_printf(s, "rxcfrmmcast: %d\n", (int )stats.rxcfrmmcast); seq_printf(s, "rxbeaconmbss: %d\n", (int )stats.rxbeaconmbss); seq_printf(s, "rxdfrmucastobss: %d\n", (int )stats.rxdfrmucastobss); seq_printf(s, "rxbeaconobss: %d\n", (int )stats.rxbeaconobss); seq_printf(s, "rxrsptmout: %d\n", (int )stats.rxrsptmout); seq_printf(s, "bcntxcancl: %d\n", (int )stats.bcntxcancl); seq_printf(s, "rxf0ovfl: %d\n", (int )stats.rxf0ovfl); seq_printf(s, "rxf1ovfl: %d\n", (int )stats.rxf1ovfl); seq_printf(s, "rxf2ovfl: %d\n", (int )stats.rxf2ovfl); seq_printf(s, "txsfovfl: %d\n", (int )stats.txsfovfl); seq_printf(s, "pmqovfl: %d\n", (int )stats.pmqovfl); seq_printf(s, "rxcgprqfrm: %d\n", (int )stats.rxcgprqfrm); seq_printf(s, "rxcgprsqovfl: %d\n", (int )stats.rxcgprsqovfl); seq_printf(s, "txcgprsfail: %d\n", (int )stats.txcgprsfail); seq_printf(s, "txcgprssuc: %d\n", (int )stats.txcgprssuc); seq_printf(s, "prs_timeout: %d\n", (int )stats.prs_timeout); seq_printf(s, "rxnack: %d\n", (int )stats.rxnack); seq_printf(s, "frmscons: %d\n", (int )stats.frmscons); seq_printf(s, "txnack: %d\n", (int )stats.txnack); seq_printf(s, "txglitch_nack: %d\n", (int )stats.txglitch_nack); seq_printf(s, "txburst: %d\n", (int )stats.txburst); seq_printf(s, "bphy_rxcrsglitch: %d\n", (int )stats.bphy_rxcrsglitch); seq_printf(s, "phywatchdog: %d\n", (int )stats.phywatchdog); seq_printf(s, "bphy_badplcp: %d\n", (int )stats.bphy_badplcp); return (0); } } static int brcms_debugfs_entry_open(struct inode *inode , struct file *f ) { struct brcms_debugfs_entry *entry ; int tmp ; { entry = (struct brcms_debugfs_entry *)inode->i_private; tmp = single_open(f, entry->read, (void *)entry->drvr); return (tmp); } } static struct file_operations const brcms_debugfs_def_ops = {& __this_module, & seq_lseek, & seq_read, 0, 0, 0, 0, 0, 0, 0, 0, 0, & brcms_debugfs_entry_open, 0, & single_release, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static int brcms_debugfs_add_entry(struct brcms_pub *drvr , char const *fn , int (*read_fn)(struct seq_file * , void * ) ) { struct device *dev ; struct dentry *dentry ; struct brcms_debugfs_entry *entry ; bool tmp ; void *tmp___0 ; int tmp___1 ; { dev = & (((drvr->wlc)->hw)->d11core)->dev; dentry = drvr->dbgfs_dir; tmp = IS_ERR_OR_NULL((void const *)dentry); if ((int )tmp) { return (-2); } else { } tmp___0 = devm_kzalloc(dev, 16UL, 208U); entry = (struct brcms_debugfs_entry *)tmp___0; if ((unsigned long )entry == (unsigned long )((struct brcms_debugfs_entry *)0)) { return (-12); } else { } entry->read = read_fn; entry->drvr = drvr; dentry = debugfs_create_file(fn, 292, dentry, (void *)entry, & brcms_debugfs_def_ops); tmp___1 = PTR_ERR_OR_ZERO((void const *)dentry); return (tmp___1); } } void brcms_debugfs_create_files(struct brcms_pub *drvr ) { bool tmp ; { tmp = IS_ERR_OR_NULL((void const *)drvr->dbgfs_dir); if ((int )tmp) { return; } else { } brcms_debugfs_add_entry(drvr, "hardware", & brcms_debugfs_hardware_read); brcms_debugfs_add_entry(drvr, "macstat", & brcms_debugfs_macstat_read); return; } } void __brcms_info(struct device *dev , char const *fmt , ...) { struct va_format vaf ; va_list args ; { vaf.fmt = fmt; vaf.va = 0; ldv__builtin_va_start((va_list *)(& args)); vaf.va = & args; _dev_info((struct device const *)dev, "%pV", & vaf); trace_brcms_info(& vaf); ldv__builtin_va_end((va_list *)(& args)); return; } } void __brcms_warn(struct device *dev , char const *fmt , ...) { struct va_format vaf ; va_list args ; { vaf.fmt = fmt; vaf.va = 0; ldv__builtin_va_start((va_list *)(& args)); vaf.va = & args; dev_warn((struct device const *)dev, "%pV", & vaf); trace_brcms_warn(& vaf); ldv__builtin_va_end((va_list *)(& args)); return; } } void __brcms_err(struct device *dev , char const *fmt , ...) { struct va_format vaf ; va_list args ; { vaf.fmt = fmt; vaf.va = 0; ldv__builtin_va_start((va_list *)(& args)); vaf.va = & args; dev_err((struct device const *)dev, "%pV", & vaf); trace_brcms_err(& vaf); ldv__builtin_va_end((va_list *)(& args)); return; } } void __brcms_crit(struct device *dev , char const *fmt , ...) { struct va_format vaf ; va_list args ; { vaf.fmt = fmt; vaf.va = 0; ldv__builtin_va_start((va_list *)(& args)); vaf.va = & args; dev_crit((struct device const *)dev, "%pV", & vaf); trace_brcms_crit(& vaf); ldv__builtin_va_end((va_list *)(& args)); return; } } void __brcms_dbg(struct device *dev , u32 level , char const *func , char const *fmt , ...) { struct va_format vaf ; va_list args ; int tmp ; { vaf.fmt = fmt; vaf.va = 0; ldv__builtin_va_start((va_list *)(& args)); vaf.va = & args; if ((brcm_msg_level & level) != 0U) { tmp = net_ratelimit(); if (tmp != 0) { dev_err((struct device const *)dev, "%s %pV", func, & vaf); } else { } } else { } trace_brcms_dbg(level, func, & vaf); ldv__builtin_va_end((va_list *)(& args)); return; } } int ldv_retval_5 ; void ldv_file_operations_4(void) { void *tmp ; void *tmp___0 ; { tmp = ldv_init_zalloc(1000UL); brcms_debugfs_def_ops_group1 = (struct inode *)tmp; tmp___0 = ldv_init_zalloc(504UL); brcms_debugfs_def_ops_group2 = (struct file *)tmp___0; return; } } void ldv_main_exported_4(void) { char *ldvarg69 ; void *tmp ; size_t ldvarg68 ; loff_t ldvarg66 ; loff_t *ldvarg67 ; void *tmp___0 ; int ldvarg65 ; int tmp___1 ; { tmp = ldv_init_zalloc(1UL); ldvarg69 = (char *)tmp; tmp___0 = ldv_init_zalloc(8UL); ldvarg67 = (loff_t *)tmp___0; ldv_memset((void *)(& ldvarg68), 0, 8UL); ldv_memset((void *)(& ldvarg66), 0, 8UL); ldv_memset((void *)(& ldvarg65), 0, 4UL); tmp___1 = __VERIFIER_nondet_int(); switch (tmp___1) { case 0: ; if (ldv_state_variable_4 == 1) { ldv_retval_5 = brcms_debugfs_entry_open(brcms_debugfs_def_ops_group1, brcms_debugfs_def_ops_group2); if (ldv_retval_5 == 0) { ldv_state_variable_4 = 2; ref_cnt = ref_cnt + 1; } else { } } else { } goto ldv_56281; case 1: ; if (ldv_state_variable_4 == 2) { single_release(brcms_debugfs_def_ops_group1, brcms_debugfs_def_ops_group2); ldv_state_variable_4 = 1; ref_cnt = ref_cnt - 1; } else { } goto ldv_56281; case 2: ; if (ldv_state_variable_4 == 2) { seq_read(brcms_debugfs_def_ops_group2, ldvarg69, ldvarg68, ldvarg67); ldv_state_variable_4 = 2; } else { } goto ldv_56281; case 3: ; if (ldv_state_variable_4 == 2) { seq_lseek(brcms_debugfs_def_ops_group2, ldvarg66, ldvarg65); ldv_state_variable_4 = 2; } else { } goto ldv_56281; default: ldv_stop(); } ldv_56281: ; return; } } __inline static long PTR_ERR(void const *ptr ) { long tmp ; { tmp = ldv_ptr_err(ptr); return (tmp); } } __inline static bool IS_ERR_OR_NULL(void const *ptr ) { bool tmp ; { tmp = ldv_is_err_or_null(ptr); return (tmp); } } bool ldv_queue_work_on_283(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_284(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_285(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_286(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_287(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_297(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_work_on_299(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) ; bool ldv_queue_delayed_work_on_298(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; bool ldv_queue_delayed_work_on_301(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) ; void ldv_flush_workqueue_300(struct workqueue_struct *ldv_func_arg1 ) ; __inline static struct device *wiphy_dev(struct wiphy *wiphy ) { { return (wiphy->dev.parent); } } __inline static char const *wiphy_name(struct wiphy const *wiphy ) { char const *tmp ; { tmp = dev_name(& wiphy->dev); return (tmp); } } extern char const *__ieee80211_get_radio_led_name(struct ieee80211_hw * ) ; __inline static char const *ieee80211_get_radio_led_name(struct ieee80211_hw *hw ) { char const *tmp ; { tmp = __ieee80211_get_radio_led_name(hw); return (tmp); } } extern int gpiod_direction_output_raw(struct gpio_desc * , int ) ; extern struct gpio_desc *gpio_to_desc(unsigned int ) ; __inline static bool gpio_is_valid(int number ) { { return ((bool )(number >= 0 && number <= 511)); } } extern void gpio_free(unsigned int ) ; __inline static int gpio_direction_output(unsigned int gpio , int value ) { struct gpio_desc *tmp ; int tmp___0 ; { tmp = gpio_to_desc(gpio); tmp___0 = gpiod_direction_output_raw(tmp, value); return (tmp___0); } } __inline static void __gpio_set_value(unsigned int gpio , int value ) { { return; } } extern int gpio_request_one(unsigned int , unsigned long , char const * ) ; __inline static void gpio_set_value(unsigned int gpio , int value ) { { __gpio_set_value(gpio, value); return; } } extern int led_classdev_register(struct device * , struct led_classdev * ) ; extern void led_classdev_unregister(struct led_classdev * ) ; static void brcms_radio_led_ctrl(struct brcms_info *wl , bool state ) { { if (wl->radio_led.gpio == 4294967295U) { return; } else { } if ((int )wl->radio_led.active_low) { state = (bool )(! ((int )state != 0)); } else { } if ((int )state) { gpio_set_value(wl->radio_led.gpio, 1); } else { gpio_set_value(wl->radio_led.gpio, 0); } return; } } static void brcms_led_brightness_set(struct led_classdev *led_dev , enum led_brightness brightness ) { struct brcms_info *wl ; struct led_classdev const *__mptr ; { __mptr = (struct led_classdev const *)led_dev; wl = (struct brcms_info *)__mptr + 0xfffffffffffffdb8UL; brcms_radio_led_ctrl(wl, (unsigned int )brightness != 0U); return; } } void brcms_led_unregister(struct brcms_info *wl ) { { if ((unsigned long )wl->led_dev.dev != (unsigned long )((struct device *)0)) { led_classdev_unregister(& wl->led_dev); } else { } if (wl->radio_led.gpio != 4294967295U) { gpio_free(wl->radio_led.gpio); } else { } return; } } int brcms_led_register(struct brcms_info *wl ) { int i ; int err ; struct brcms_led *radio_led ; struct bcma_drv_cc *cc_drv ; struct gpio_chip *bcma_gpio ; struct ssb_sprom *sprom ; u8 *leds[4U] ; unsigned int gpio ; bool active_low ; bool tmp ; int tmp___0 ; u8 led ; bool tmp___1 ; int tmp___2 ; char const *tmp___3 ; struct device *tmp___4 ; { radio_led = & wl->radio_led; cc_drv = & ((((wl->wlc)->hw)->d11core)->bus)->drv_cc; bcma_gpio = & cc_drv->gpio; sprom = & ((((wl->wlc)->hw)->d11core)->bus)->sprom; leds[0] = & sprom->gpio0; leds[1] = & sprom->gpio1; leds[2] = & sprom->gpio2; leds[3] = & sprom->gpio3; gpio = 4294967295U; active_low = 0; radio_led->gpio = 4294967295U; radio_led->active_low = 0; if ((unsigned long )bcma_gpio == (unsigned long )((struct gpio_chip *)0)) { return (-19); } else { tmp = gpio_is_valid(bcma_gpio->base); if (tmp) { tmp___0 = 0; } else { tmp___0 = 1; } if (tmp___0) { return (-19); } else { } } i = 0; goto ldv_54486; ldv_54485: led = *(leds[i]); if (((int )led & 127) == 3) { gpio = (unsigned int )(bcma_gpio->base + i); if ((int )((signed char )led) < 0) { active_low = 1; } else { } goto ldv_54484; } else { } i = i + 1; ldv_54486: ; if (i <= 3) { goto ldv_54485; } else { } ldv_54484: ; if (gpio == 4294967295U) { return (-19); } else { tmp___1 = gpio_is_valid((int )gpio); if (tmp___1) { tmp___2 = 0; } else { tmp___2 = 1; } if (tmp___2) { return (-19); } else { } } err = gpio_request_one(gpio, (int )active_low ? 2UL : 0UL, "radio on"); if (err != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "requesting led gpio %d failed (err: %d)\n", gpio, err); return (err); } else { } err = gpio_direction_output(gpio, 1); if (err != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "cannot set led gpio %d to output (err: %d)\n", gpio, err); return (err); } else { } tmp___3 = wiphy_name((struct wiphy const *)wl->wiphy); snprintf((char *)(& wl->radio_led.name), 32UL, "brcmsmac-%s:radio", tmp___3); wl->led_dev.name = (char const *)(& wl->radio_led.name); wl->led_dev.default_trigger = ieee80211_get_radio_led_name((wl->pub)->ieee_hw); wl->led_dev.brightness_set = & brcms_led_brightness_set; tmp___4 = wiphy_dev(wl->wiphy); err = led_classdev_register(tmp___4, & wl->led_dev); if (err != 0) { dev_err((struct device const *)(& (wl->wiphy)->dev), "cannot register led device: %s (err: %d)\n", (char *)(& wl->radio_led.name), err); return (err); } else { } _dev_info((struct device const *)(& (wl->wiphy)->dev), "registered radio enabled led device: %s gpio: %d\n", (char *)(& wl->radio_led.name), gpio); radio_led->gpio = gpio; radio_led->active_low = active_low; return (0); } } bool ldv_queue_work_on_297(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } bool ldv_queue_delayed_work_on_298(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___0 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } bool ldv_queue_work_on_299(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct work_struct *ldv_func_arg3 ) { ldv_func_ret_type___1 ldv_func_res ; bool tmp ; { tmp = queue_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3); ldv_func_res = tmp; activate_work_2(ldv_func_arg3, 2); return (ldv_func_res); } } void ldv_flush_workqueue_300(struct workqueue_struct *ldv_func_arg1 ) { { flush_workqueue(ldv_func_arg1); call_and_disable_all_2(2); return; } } bool ldv_queue_delayed_work_on_301(int ldv_func_arg1 , struct workqueue_struct *ldv_func_arg2 , struct delayed_work *ldv_func_arg3 , unsigned long ldv_func_arg4 ) { ldv_func_ret_type___2 ldv_func_res ; bool tmp ; { tmp = queue_delayed_work_on(ldv_func_arg1, ldv_func_arg2, ldv_func_arg3, ldv_func_arg4); ldv_func_res = tmp; activate_work_2(& ldv_func_arg3->work, 2); return (ldv_func_res); } } extern void *memset(void * , int , size_t ) ; __inline static void ldv_error(void) { { ERROR: ; __VERIFIER_error(); } } bool ldv_is_err(void const *ptr ) { { return ((unsigned long )ptr > 2012UL); } } void *ldv_err_ptr(long error ) { { return ((void *)(2012L - error)); } } long ldv_ptr_err(void const *ptr ) { { return ((long )(2012UL - (unsigned long )ptr)); } } bool ldv_is_err_or_null(void const *ptr ) { bool tmp ; int tmp___0 ; { if ((unsigned long )ptr == (unsigned long )((void const *)0)) { tmp___0 = 1; } else { tmp = ldv_is_err(ptr); if ((int )tmp) { tmp___0 = 1; } else { tmp___0 = 0; } } return ((bool )tmp___0); } } int ldv_module_refcounter = 1; void ldv_module_get(struct module *module ) { { if ((unsigned long )module != (unsigned long )((struct module *)0)) { ldv_module_refcounter = ldv_module_refcounter + 1; } else { } return; } } int ldv_try_module_get(struct module *module ) { int module_get_succeeded ; { if ((unsigned long )module != (unsigned long )((struct module *)0)) { module_get_succeeded = ldv_undef_int(); if (module_get_succeeded == 1) { ldv_module_refcounter = ldv_module_refcounter + 1; return (1); } else { return (0); } } else { } return (0); } } void ldv_module_put(struct module *module ) { { if ((unsigned long )module != (unsigned long )((struct module *)0)) { if (ldv_module_refcounter <= 1) { ldv_error(); } else { } ldv_module_refcounter = ldv_module_refcounter - 1; } else { } return; } } void ldv_module_put_and_exit(void) { { ldv_module_put((struct module *)1); LDV_STOP: ; goto LDV_STOP; } } unsigned int ldv_module_refcount(void) { { return ((unsigned int )(ldv_module_refcounter + -1)); } } void ldv_check_final_state(void) { { if (ldv_module_refcounter != 1) { ldv_error(); } else { } return; } }