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微處理器 - Altera EP4CE6E22C8N - VHDL - Button

---

main.vhd

library ieee;
use ieee.std_logic_1164.all;
 
entity main is
    port(
        btn : in std_logic;
        led : out std_logic
    );
end main;
 
architecture logic of main is
begin
    process(btn) is
    begin
        led <= not btn;
    end process;
end logic;

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完成