微處理器 - Lattice iCE40LP1K-CM36 (iCESugar-nano) - Verilog - LED

LED腳位


main.v

module main (
    input clk,
    output reg led
);

reg [23:0] cnt;
    
always @(posedge clk) begin
    if (cnt == 1000000) begin
        cnt = 0;
        led <= ~led;
    end else
        cnt = cnt + 1;
end
endmodule

main.pcf

set_io led B6
set_io clk D1

Makefile

all:
	yosys -p "synth_ice40 -json main.json -blif main.blif" main.v
	nextpnr-ice40 --lp1k --package cm36 --json main.json --pcf main.pcf --asc main.asc --freq 48
	icepack main.asc main.bin

run:
	icesprog -w  main.bin

clean:
	rm -rf main.blif main.asc main.bin main.json

編譯、燒錄

$ make
$ make run

完成