微處理器 - Gowin GW1NR-LV9QN88PC6/I5 (Lichee Tang Nano 9K) - Verilog - Button

參考資訊：
https://github.com/YosysHQ/apicula/issues/244
https://github.com/YosysHQ/apicula/wiki/Nextpnr%E2%80%90Himbaechel-Gowin

main.v

module main (
    input btn,
    output reg led
);
   
initial begin
    led = 0;
end
     
always @(posedge btn) begin
    led <= ~led;
end
    
endmodule

main.cst

IO_LOC "led" 10;
IO_LOC "btn" 4;

完成