微處理器 - Gowin GW1NR-LV9QN88PC6/I5 (Lichee Tang Nano 9K) - Verilog - LED

參考資訊：
https://github.com/YosysHQ/apicula/issues/244
https://github.com/YosysHQ/apicula/wiki/Nextpnr%E2%80%90Himbaechel-Gowin

main.v

module main (
    input clk,
    output reg led
);
   
reg [23:0] clk_cnt;
   
always @(posedge clk) begin
    if (clk_cnt == 24'd10000000)
        clk_cnt <= 24'd0;
    else
        clk_cnt <= clk_cnt + 1;
  
    if (clk_cnt == 24'd10000000)
        led <= ~led;
end
   
endmodule

main.cst

IO_LOC "led" 10;
IO_LOC "clk" 52;

Makefile

all:
	yosys -p "synth_gowin -json main.json -top main" main.v
	nextpnr-himbaechel --json main.json --write main.pack --device GW1NR-LV9QN88PC6/I5 --vopt family=GW1N-9C --vopt cst=main.cst
	gowin_pack -d GW1N-9C -o main.fs main.pack

ram:
	openFPGALoader -m -b tangnano9k main.fs

flash:
	openFPGALoader -f -b tangnano9k main.fs

clean:
	rm -f *.json *.fs *.pack

編譯、下載

$ make
$ make ram

完成