參考資訊：
https://en.wikichip.org/wiki/mips/coprocessor_0
http://www.cs.cornell.edu/courses/cs3410/2008fa/MIPS_Vol3.pdf
MIPS General Register
| Register | Conventional Name | Usage |
|---|---|---|
| $0 | $zero | Hard-wired to 0 |
| $1 | $at | Reserved for pseudo-instructions |
| $2-$3 | $v0, $v1 | Return values from functions |
| $4-$7 | $a0-$a3 | Arguments to functions - not preserved by subprograms |
| $8-$15 | $t0-$t7 | Temporary data, not preserved by subprograms |
| $16-$23 | $s0-$s7 | Saved registers, preserved by subprograms |
| $24-$25 | $t8-$t9 | More temporary registers, not preserved by subprograms |
| $26-$27 | $k0-$k1 | Reserved for kernel. Do not use. |
| $28 | $gp | Global Area Pointer (base of global data segment) |
| $29 | $sp | Stack Pointer |
| $30 | $fp | Frame Pointer |
| $31 | $ra | Return Address |
| $f0-$f3 | Floating point return values | |
| $f4-$f10 | Temporary registers, not preserved by subprograms | |
| $f12-$f14 | First two arguments to subprograms, not preserved by subprograms | |
| $f16-$f18 | More temporary registers, not preserved by subprograms | |
| $f20-$f31 | Saved registers, preserved by subprograms |
MIPS Coprocessor Register
| Register | Number | Description |
|---|---|---|
| Context | 0 | memory management (TLB) |
| Random | 1 | memory management (TLB) |
| EntryLo0 | 2 | memory management (TLB) |
| EntryLo1 | 3 | memory management (TLB) |
| Context | 4 | memory management (TLB) |
| PageMask | 5 | memory management (TLB) |
| Wired | 6 | memory management (TLB) |
| EntryHi | 10 | memory management (TLB) |
| HWREna | 7.0 | Sets user-privilege programs permissions |
| BadVAddr | 8 | Program address of the violation |
| Count | 9 | high-resolution time |
| Compare | 11 | high-resolution time |
| SR | 12 | Status Register |
| IntCtl | 12.1 | Interrupt vector setup |
| SRSCtl | 12.2 | Shadow register control |
| SRSMap | 12.3 | Shadow register map |
| Cause | 13 | Cause Register |
| EPC | 14 | Exception Program Counter |
| PRId | 15 | Product ID register |
| EBase | 15.1 | Exception entry point base address |
| Config | 16 | CPU setup |
| Config1 | 16.1 | CPU setup |
| Config2 | 16.2 | CPU setup |
| Config3 | 16.3 | CPU setup |
| LLAddr | 17.0 | Cache address |
| Debug | 23.0 | EJTAG debug |
| DEPC | 24.0 | EJTAG debug |
| DESAVE | 31.0 | EJTAG debug |
| CacheErr | 27 | Memory error analysis registers |
| ECC | 26 | Memory error analysis registers |
| ErrorEPC | 30 | Memory error analysis registers |
| TagLo | 28 | Cache manipulation |
| DataLo | 28.1 | Cache manipulation |
| TagHi | 29 | Cache manipulation |
| DataHi | 29.1 | Cache manipulation |
| WatchLo | 18.0 | Data watchpoint facility |
| WatchHi | 19.0 | Data watchpoint facility |
| PrefCtl | 25.0 | Performance counter registers |
| PrefCnt | 25.1 | Performance counter registers |